Power conversion device

Abstract

This power conversion device comprises: a power converter in which a plurality of the AC sides of single-phase inverters that convert DC power into AC power are connected in series and which supplies, to a load, the DC power or the AC power of the total output voltage obtained by summing the output voltages output by the plurality of single-phase inverters; and a control unit that controls the power converter. The single-phase inverter that outputs the minimum output voltage that is larger than zero voltage and minimum in the absolute value of the output voltage is used as a minimum single-phase inverter. The absolute value of the total output voltage which can be discretely set by selectively combining the outputs of the plurality of single-phase inverters is set as a gradation level. The gradation level includes a special level by which the same total output voltage can be obtained by a combination of the output voltages of the plurality of single-phase inverters. When the control unit controls the power converter using the special level, a voltage combination is selected in which the output voltage of at least one single-phase inverter excluding the minimum single-phase inverter does not change.

Description

Power Conversion Device

[0001] The present application relates to a power conversion device.

[0002] A gradation-controlled power conversion device, which is one type of power conversion device, can output a smooth AC waveform to a load without using a large-capacity output filter. The gradation-controlled power conversion device is configured by connecting multiple single-phase inverters in series. Patent Document 1 discloses a gradation-controlled power conversion device in which the absolute value of the minimum generated voltage among the multiple single-phase inverters is set to 1, and the ratio of the absolute values ​​of the output voltages among the multiple single-phase inverters is a power-of-2 ratio. The power conversion device of Patent Document 1 gradation-controls the sum of the generated voltages of the multiple single-phase inverters by selecting and combining whether or not to output.

[0003] JP 2011-155786 A

[0004] The power conversion device disclosed in Patent Document 1 drives a gradation-controlled inverter using PWM (Pulse Width Modulation) control to supply power to a load. Gradation-controlled inverters are typically characterized by reducing the number of switching operations of a single-phase inverter with a high output voltage, thereby reducing the switching loss of the single-phase inverter with a high output voltage. However, the power conversion device disclosed in Patent Document 1 may extend the period during which the single-phase inverter with a high output voltage performs PWM control. In the power conversion device disclosed in Patent Document 1, as the PWM operation period of the single-phase inverter with a high output voltage increases, the number of switching operations of the single-phase inverter with a high output voltage increases, thereby increasing the switching loss of the single-phase inverter. As a result, the power conversion device disclosed in Patent Document 1 has a problem in that the components and heat sinks constituting the single-phase inverter are large, resulting in an increase in the size of the power conversion device itself.

[0005] The technology disclosed in this specification aims to realize a small-sized gradation-controlled power conversion device.

[0006] An example power conversion device disclosed in the present specification includes a power converter in which the AC sides of multiple single-phase inverters that convert DC power to AC power are connected in series, and the power converter supplies a load with DC or AC power having a total output voltage equal to the sum of the output voltages of the multiple single-phase inverters, and a control unit for controlling the power converter. The single-phase inverter that outputs a minimum output voltage whose absolute value is greater than zero and minimum is defined as a minimum single-phase inverter. The absolute values ​​of the total output voltage, which can be discretely set by selectively combining the outputs of the multiple single-phase inverters, are defined as gradation levels, and predetermined gradation levels at which the same total output voltage level is achieved by multiple voltage combinations that are output voltage combinations, are defined as special levels, and the settable gradation levels include at least one special level. The control unit controls the single-phase inverters to output a total output voltage of a set voltage value by selecting a combination of output voltages of the multiple single-phase inverters. When changing the gradation levels to include the special level at either the front or back, the control unit selects a voltage combination that does not change the output voltage of at least one single-phase inverter other than the minimum single-phase inverter.

[0007] An example power conversion device disclosed in the present specification includes a special level in the gradation level that can achieve the same overall output voltage by combining the output voltages of multiple single-phase inverters, and when the control unit controls the power converter using the special level, it selects a voltage combination that does not change at least one output voltage except for the minimum output voltage whose absolute value is the smallest, thereby realizing a small-sized gradation-controlled power conversion device.

[0008] 1 is a diagram showing a configuration of a power conversion device according to a first embodiment. 2 is a diagram showing a configuration of a single-phase inverter of FIG. 1. 3 is a diagram showing a configuration of a gate driver of FIG. 1. 4 is a diagram showing output terminals and control signals in the control unit of FIG. 1. 5 is a diagram showing the configuration of the control unit of FIG. 1. 6 is a diagram showing an example of control of the single-phase inverter of FIG. 2. 7 is a diagram showing examples of gradation levels and output voltages in the power conversion device of FIG. 1. 8 is a diagram showing an example of operation of the power conversion device of FIG. 1. 9 is a diagram showing examples of gradation levels and output voltages in a power conversion device of a comparative example. 10 is a diagram showing an example of operation of the power conversion device of the comparative example. 11 is a diagram showing a third example of gradation levels and output voltages in the power conversion device of FIG. 1. 12 is a diagram showing examples of gradation levels and output voltages in a power conversion device according to a second embodiment. 13 is a diagram showing a first example of operation of the power conversion device according to the second embodiment. 14 is a diagram showing an example of operation of the power conversion device of the comparative example. 15 is a diagram showing a second example of operation of the power conversion device according to the second embodiment. 16 is a diagram showing examples of gradation levels and output voltages in a power conversion device according to a third embodiment. 17 is a diagram showing an example of operation of the power conversion device of the comparative example. 18 is a diagram showing an example of operation of the power conversion device of the comparative example. 19 is a diagram showing an example of operation of the power conversion device of the comparative example. 27 is a diagram showing a first example of gradation levels and output voltages in a power conversion device according to embodiment 5. FIG. 28 is a diagram showing a first example of gradation levels and output voltages in a power conversion device according to embodiment 5. FIG. 29 is a diagram showing a second example of gradation levels and output voltages in a power conversion device according to embodiment 5. FIG. 30 is a diagram showing a second example of gradation levels and output voltages in a power conversion device according to embodiment 5. FIG. 31 is a diagram showing an operation example of a power conversion device according to embodiment 5. FIG. 32 is a diagram showing a third example of gradation levels and output voltages in a power conversion device according to embodiment 5. FIG. 33 is a diagram showing a configuration of a power conversion device according to embodiment 6. FIG. 34 is a diagram showing the configuration of the control unit of FIG. 27. FIG. 35 is a diagram showing the configuration of a first example of the output detection unit of FIG. 27. FIG. 36 is a diagram showing the configuration of a second example of the output detection unit of FIG. 27. FIG. 37 is a diagram showing an example of a hardware configuration that realizes the functions of the control unit.

[0009] Embodiment 1. FIG. 1 is a diagram showing the configuration of a power conversion device according to embodiment 1. FIG. 2 is a diagram showing the configuration of the single-phase inverter of FIG. 1, and FIG. 3 is a diagram showing the configuration of the gate driver of FIG. 1. FIG. 4 is a diagram showing output terminals and control signals in the control unit of FIG. 1, and FIG. 5 is a diagram showing the configuration of the control unit of FIG. 1. FIG. 6 is a diagram showing an example of control of the single-phase inverter of FIG. 2. FIG. 7 is a diagram showing examples of gradation levels and output voltages in the power conversion device of FIG. 1. FIG. 8 is a diagram showing an example of operation of the power conversion device of FIG. 1. FIG. 9 is a diagram showing examples of gradation levels and output voltages in a power conversion device of a comparative example, and FIG. 10 is a diagram showing an example of operation of the power conversion device of the comparative example. FIG. 11 is a diagram showing a third example of gradation levels and output voltages in the power conversion device of FIG. 1. The power conversion device 100 of embodiment 1 is a gradation-controlled power conversion device that includes three or more single-phase inverters A or two single-phase inverters A connected in series and performs PWM operation. 1 includes a power converter 50 in which n single-phase inverters A1 to An are connected in series, and a control unit 10 that controls the power converter 50. The power converter 50 includes n single-phase inverters A1 to An and n gate drivers GD1 to GDn.

[0010] The power converter 50 has a plurality of single-phase inverters A1-An whose AC sides (output terminals N and P) are connected in series to convert DC power to AC power, and supplies DC or AC power of a total output voltage Vsum, which is the sum of the output voltages V1-Vn output by the plurality of single-phase inverters A1-An, to a load 20. The control unit 10 determines the gradation level of the total output voltage Vsum by selecting a combination of the output voltages V1-Vn of the plurality of single-phase inverters A1-An, and executes PWM control on the single-phase inverters so that the total output voltage Vsum is output at a preset voltage value between adjacent gradation levels. The gradation level is the absolute value of the total output voltage Vsum, which can be set discretely by selectively combining the outputs of the plurality of inverters.

[0011] The single-phase inverters A1 to An are controlled based on control signals S1N to SnN and S1P to SnP output from the control unit 10 via gate drivers GD1 to GDn. The single-phase inverters A1 to An are connected to DC power supplies BT1 to BTn. The DC power supplies BT1 to BTn output power supply voltages Vd1 to Vdn. Where appropriate, the single-phase inverters are generally designated by A, with A1 to An used to distinguish them. The gate drivers are generally designated by GD, with GD1 to GDn used to distinguish them. The control signals for one half-bridge inverter (described below) are generally designated by SN, with S1N to SnN used to distinguish them. The control signals for the other half-bridge inverter (described below) are generally designated by SP, with S1P to SnP used to distinguish them. The DC power supplies are generally designated by BT, with BT1 to BTn used to distinguish them.

[0012] FIG. 1 specifically illustrates four single-phase inverters A1, A2, Am, and An, four gate drivers GD1, GD2, GDm, and GDn, and four DC power supplies BT1, BT2, BTm, and BTn. In FIG. 1, m and n are natural numbers equal to or greater than 3, and m is a natural number smaller than n. Note that when describing single-phase inverter Am as a representative, m is a natural number. When expressing the output voltages V1 to Vn output by single-phase inverters A1 to An as voltage values, the following principle applies: The absolute values ​​of the respective output voltages are V1 to Vn, and are displayed with + or - to indicate the polarity of the voltage. Note that the absolute value of the voltage generated when a single-phase inverter outputs a voltage will be referred to as the absolute voltage value, where appropriate.

[0013] The control unit 10 controls each of the single-phase inverters A1 to An and controls the power conversion device 100 so that the sum of the output voltages V1 to Vn of each of the single-phase inverters A1 to An is output as a total output voltage Vsum to the load 20. By combining the output voltages V1 to Vn of each of the single-phase inverters A1 to An, the power conversion device 100 can output DC power or AC power of a predetermined arbitrary magnitude. Note that the power conversion device 100 of the first embodiment can accommodate a wide variety of loads 20, such as resistive loads, capacitive loads, inductive loads, and loads that are combinations thereof.

[0014] The single-phase inverter A and gate driver GD will be described using Figures 2 and 3. The single-phase inverter A is a full-bridge inverter having four switching elements QNL, QNH, QPL, and QPH. This full-bridge inverter is composed of one half-bridge inverter BN consisting of two switching elements QNL and QNH, and another half-bridge inverter BP consisting of two switching elements QPL and QPH. A DC power supply BT with a power supply voltage Vd is connected to the half-bridge inverter, with the positive voltage being in the direction indicated by the arrow in Figure 2, i.e., from the low-potential side wiring Ll to the high-potential side wiring Lh. Where appropriate, the symbol Vd will be used collectively to designate the power supply voltage of the DC power supply, with Vd1 to Vdn used to distinguish between them. A capacitor may be provided between the DC power supply BT and the single-phase inverter A.

[0015] The single-phase inverter A has a positive voltage in the direction indicated by the arrow in FIG. 2 , i.e., from output terminal N to output terminal P, and outputs an output voltage V whose absolute value is V. The sign of the output voltages of the single-phase inverter A is collectively designated V, and V1 to Vn are used to distinguish between them. In the first embodiment, resistance components of switching elements, wiring, etc. present between the DC power supply BT and the output terminals N and P of the single-phase inverter A are at a negligible level, so the output voltage V of the single-phase inverter A is the same as the power supply voltage Vd of the DC power supply BT.

[0016] The single-phase inverter A includes a half-bridge inverter BN and a half-bridge inverter BP connected in parallel between a high-potential side wiring Lh connected to the positive side of a DC power supply BT and a low-potential side wiring Ll connected to the negative side of the DC power supply BT. The half-bridge inverter BN includes a switching element QNH and a switching element QNL connected in series between the high-potential side wiring Lh and the low-potential side wiring Ll. The half-bridge inverter BP includes a switching element QPH and a switching element QPL connected in series between the high-potential side wiring Lh and the low-potential side wiring Ll. In FIG. 2 , MOSFETs (Metal Oxide Semiconductor Field Effect Transistors) are shown as examples of the switching elements QNL, QNH, QPL, and QPH. The switching elements QNL, QNH, QPL, and QPH each have a drain terminal d, a source terminal s, and a gate terminal g. The switching elements QNL, QNH, QPL, and QPH each include a transistor Tr and a diode Di. The diode Di may be an element separate from the transistor Tr, or may be a parasitic diode.

[0017] A drive signal soNH output from the gate driver GD is input to the gate terminal g of the switching element QNH, and a drive signal soNL output from the gate driver GD is input to the gate terminal g of the switching element QNL. The drain terminal d of the switching element QNH is connected to the high-potential side wiring Lh, the source terminal s of the switching element QNH is connected to the drain terminal d of the switching element QNL, and the source terminal s of the switching element QNL is connected to the low-potential side wiring Ll. The connection point between the source terminal s of the switching element QNH and the drain terminal d of the switching element QNL is connected to the output terminal N. A reference potential signal srNH is output from the source terminal s of the switching element QNH to the gate driver GD, and a reference potential signal srNL is output from the source terminal s of the switching element QNL to the gate driver GD.

[0018] A drive signal soPH output from the gate driver GD is input to the gate terminal g of the switching element QPH, and a drive signal soPL output from the gate driver GD is input to the gate terminal g of the switching element QPL. The drain terminal d of the switching element QPH is connected to the high-potential side wiring Lh, the source terminal s of the switching element QPH is connected to the drain terminal d of the switching element QPL, and the source terminal s of the switching element QPL is connected to the low-potential side wiring Ll. The connection point between the source terminal s of the switching element QPH and the drain terminal d of the switching element QPL is connected to the output terminal P. A reference potential signal srPH is output from the source terminal s of the switching element QPH to the gate driver GD, and a reference potential signal srPL is output from the source terminal s of the switching element QNL to the gate driver GD.

[0019] 2, the switching elements QNL, QNH, QPL, and QPH are MOSFETs, but this is not a limitation and they may be switching elements other than MOSFETs, such as IGBTs (Insulated Gate Bipolar Transistors), thyristors, etc. Furthermore, although an example has been shown in which the switching elements QNL, QNH, QPL, and QPH are each configured as a single component, in order to ensure a withstand voltage and withstand current, each switching element QNL, QNH, QPL, and QPH may be configured as a plurality of switching elements connected in series or in parallel, or may be configured as a combination of series and parallel connections, i.e., a series-parallel state.

[0020] The gate driver GD includes two dead time generators DTN and DTP, four gate signal output units GONH, GONL, GOPH, and GOPL, and two inverters 61. Control signals SN and SP are input to the gate driver GD via input terminals DiN and DiP, respectively, and the dead time generators DTN and DTP generate predetermined desired dead times. These signals are then output to the single-phase inverter A as level-shifted drive signals soNH, soNL and soPH, soPL from the gate signal output units GONH, GONL, and GOPH, GOPL. Finally, the two half-bridge inverters BN and BP are driven by the drive signals soNH, soNL, soPH, and soPL, respectively.

[0021] A circuit for generating drive signals soNH and soNL for driving the half-bridge inverter BN will now be described. A control signal SN output from the control unit 10 is input to an input terminal DiN, and the control signal SN and an inverted signal obtained by inverting the control signal SN by an inverter 61 are input to a dead time generation unit DTN. The dead time generation unit DTN outputs dead time signals sdtNH and sdtNL indicating a predetermined desired dead time from output terminals ToNH and ToNL, respectively. The gate signal output unit GONH receives a reference potential signal srNH output from the source terminal s of the switching element QNH at its reference terminal DsNH, and receives the dead time signal sdtNH at its input terminal TiNH. The gate signal output unit GONH outputs a drive signal soNH, to which a predetermined desired dead time has been added, from an output terminal DoNH to the gate terminal g of the switching element QNH based on the reference potential signal srNH and the dead time signal sdtNH. The gate signal output unit GONL receives the reference potential signal srNL output from the source terminal s of the switching element QNL via a reference terminal DsNL and receives the dead time signal sdtNL via an input terminal TiNL. The gate signal output unit GONL outputs a drive signal soNL, to which a predetermined desired dead time has been added, from an output terminal DoNL to the gate terminal g of the switching element QNL based on the reference potential signal srNL and the dead time signal sdtNL.

[0022] A circuit for generating drive signals soPH and soPL for driving the half-bridge inverter BP will now be described. A control signal SP output from the control unit 10 is input to an input terminal DiP, and the control signal SP and an inverted signal obtained by inverting the control signal SP by an inverter 61 are input to a dead time generation unit DTP. The dead time generation unit DTP outputs dead time signals sdtPH and sdtPL indicating a predetermined desired dead time from output terminals ToPH and ToPL, respectively. The gate signal output unit GOPH receives a reference potential signal srPH output from the source terminal s of the switching element QPH at its reference terminal DsPH, and receives the dead time signal sdtPH at its input terminal TiPH. The gate signal output unit GOPH outputs a drive signal soPH, to which a predetermined desired dead time has been added, from an output terminal DoPH to a gate terminal g of the switching element QPH based on a reference potential signal srPH and a dead time signal sdtPH. The gate signal output unit GOPL receives the reference potential signal srPL output from the source terminal s of the switching element QPL at a reference terminal DsPL and receives the dead time signal sdtPL at an input terminal TiPL. The gate signal output unit GOPL outputs a drive signal soPL, to which a predetermined desired dead time has been added, from an output terminal DoPL to the gate terminal g of the switching element QPL based on the reference potential signal srPL and the dead time signal sdtPL.

[0023] Four reference terminals DsNH, DsNL, DsPH, and DsPL constitute a reference terminal Dss of the gate driver GD. Output terminals DoNH, DoNL, DoPH, and DoPL constitute an output terminal Doo of the gate driver GD. Four reference potential signals srNH, srNL, srPH, and srPL constitute a reference potential signal sr. Four drive signals soNH, soNL, soPH, and soPL constitute a drive signal so.

[0024] 4 shows control signals S1N to SnN output from output terminals Co1N to ConN of the control unit 10, and control signals S1P to SnP output from output terminals Co1P to ConP of the control unit 10. Control signals S1N and S1P are output from output terminals Co1N and Co1P, respectively. Control signals S2N and S2P are output from output terminals Co2N and Co2P, respectively. Control signals SmN and SmP are output from output terminals ComN and Comp, respectively. Control signals SnN and SnP are output from output terminals ConN and ConP, respectively. 1 and 4 specifically show eight output terminals Co1N, Co1P, Co2N, Co2P, ComN, CompP, ConN, and ConP and eight control signals S1N, S1P, S2N, S2P, SmN, SmP, SnN, and SnP corresponding to four single-phase inverters A1, A2, Am, and An. In Fig. 1 and Fig. 4, m and n are natural numbers equal to or greater than 3, and m is a natural number smaller than n.

[0025] The output terminal P of the uppermost single-phase inverter An among the multiple single-phase inverters A1 to An connected in series is connected to one terminal of a load (not shown) via an output power line 19, and the output terminal N of the lowermost single-phase inverter A1 among the multiple single-phase inverters A1 to An is connected to the other terminal of the load (not shown) via a grounded reference power line 18. The reference power line 18 is at a reference ground potential (GND potential). The output terminal P of the single-phase inverter A1 is connected to the output terminal N of the upper single-phase inverter A2. In a single-phase inverter Am, where m is a natural number greater than or equal to 2, the output terminal N is connected to the output terminal P of the adjacent lower single-phase inverter Ak, and the output terminal P is connected to the output terminal N of the adjacent upper single-phase inverter Aka. Here, k is m-1 and ka is m+1.

[0026] A drive signal so1 input to the single-phase inverter A1 is output from the output terminal Doo of the gate driver GD1 based on control signals S1N and S1P output from the control unit 10 and a reference potential signal sr1 output from the single-phase inverter A1. The reference potential signal sr1 is input to the reference terminal Dss of the gate driver GD1. Similarly, a drive signal so2 input to the single-phase inverter A2 is output from the output terminal Doo of the gate driver GD2 based on control signals S2N and S2P output from the control unit 10 and a reference potential signal sr2 output from the single-phase inverter A2. The reference potential signal sr2 is input to the reference terminal Dss of the gate driver GD2.

[0027] Similarly, the drive signal som input to the single-phase inverter Am is output from the output terminal Doo of the gate driver GDm based on the control signals SmN and SmP output from the control unit 10 and the reference potential signal srm output from the single-phase inverter Am. The reference potential signal srm is input to the reference terminal Dss of the gate driver GDm. The drive signal son input to the single-phase inverter An is output from the output terminal Doo of the gate driver GDn based on the control signals SnN and SnP output from the control unit 10 and the reference potential signal srn output from the single-phase inverter An. The reference potential signal srn is input to the reference terminal Dss of the gate driver GDn. Where appropriate, the symbol so will be used collectively for the drive signals, with so1 to son being used when distinguishing between them. The symbols sr will be used collectively for the reference potential signals, with sr1 to srn being used when distinguishing between them.

[0028] An example of control of single-phase inverter A will be described using FIG. 6 . In FIG. 6 , single-phase inverter Am is illustrated as a representative of single-phase inverters A1 to An. FIG. 6 shows an example of the changes in the on state STon and off state SToff of the four switching elements QNH, QNL, QPH, and QPL constituting single-phase inverter Am and the output voltage Vm of single-phase inverter Am in response to changes in control signals SmN and SmP. Note that FIG. 6 shows an example in which the aforementioned dead time is omitted, i.e., the switching elements QNH and QNL change simultaneously at times t3 and t4, and the switching elements QPH and QPL change simultaneously at times t1 and t2. In FIG. 6 , the horizontal axis represents time. The vertical axis of control signals SmN and SmP represents the voltage of the digital signal, which is shown in two states: high level (H level) and low level (L level). The vertical axis of the switching elements QNH, QNL, QPH, and QPL represents the on / off state, and shows two states: the on state STon and the off state SToff. The vertical axis of the output voltage Vm represents voltage, and shows three states: a positive voltage +Vm, a negative voltage −Vm with the polarity reversed from this positive voltage, and zero voltage (0).

[0029] At time t0, the control signals SmN and SmP are both at low levels. The switching element QNH on the high potential side wiring Lh of the half-bridge inverter BN, i.e., the high side, is in the off state, and the switching element QNL on the low potential side wiring Ll of the half-bridge inverter BN, i.e., the low side, is in the on state. The switching element QPH on the high potential side wiring Lh of the half-bridge inverter BP, i.e., the high side, is in the off state, and the switching element QPL on the low potential side wiring Ll of the half-bridge inverter BP, i.e., the low side, is in the on state. The output voltage Vm is zero voltage, i.e., a zero voltage output state (Vm = 0 V (Volt)).

[0030] At time t1, the control signal SmP changes to high level, the control signal SmN changes to low level, and the control signal SmP changes to high level. In this case, the switching elements QNH and QNL of the half-bridge inverter BN are in the off state and on state, respectively, and the switching elements QPH and QPL of the half-bridge inverter BP are in the on state and off state, respectively. As a result, the output voltage Vm becomes a positive voltage (+Vm), i.e., a positive voltage output state is entered.

[0031] At time t2, the control signal SmP changes to low level, and the control signal SmN and the control signal SmP also go low level, resulting in the same state as at time t0.

[0032] At time t3, the control signal SmN changes to high level, and the control signal SmN goes high and the control signal SmP goes low. In this case, the switching elements QNH and QNL of the half-bridge inverter BN are turned on and off, respectively, and the switching elements QPH and QPL of the half-bridge inverter BP remain off and on, respectively. As a result, the output voltage Vm becomes a negative voltage (-Vm), i.e., a negative voltage output state is entered.

[0033] At time t4, the control signal SmN changes to low level, and the control signal SmN and the control signal SmP also go low level, resulting in the same state as at time t0.

[0034] A method for setting and controlling the output voltage of each single-phase inverter A, which is a feature of the present application, will now be described. A first power conversion device 100 according to the first embodiment includes single-phase inverters A having at least three different output voltages, and is characterized in that the output voltage of each single-phase inverter A is set so that the same overall output voltage Vsum can be output by combining multiple outputs at at least one gradation level. As described above, the gradation level is the absolute value of the overall output voltage that can be discretely set by selectively combining the outputs of multiple inverters. In the case of PWM control, the following may also be used. The gradation level is the absolute value of the overall output voltage Vsum that can be discretely set when the output voltage V is constant during the control period Tc of PWM control, i.e., the level of the overall output voltage Vsum. Furthermore, a predetermined gradation level that can be set and that achieves the same overall output voltage Vsum level by multiple voltage combinations of the output voltages V is referred to as a special level. Figure 7 shows examples of the gradation levels, output voltages V1 to V3, and overall output voltage Vsum for a first power conversion device 100 equipped with three single-phase inverters A.

[0035] The second power conversion device 100 of the first embodiment includes single-phase inverters A having two different output voltages, and is characterized in that the output voltage of each single-phase inverter A is set so that the same overall output voltage Vsum can be output with a combination of multiple outputs for at least one gradation level. Examples of gradation levels, output voltages V1 to V3, and overall output voltage Vsum in the second power conversion device 100 including two single-phase inverters A are shown in FIG.

[0036] The examples of gradation levels, output voltages V1 to V3, and total output voltage Vsum shown in FIG. 7 are examples of gradation level settings for a power conversion device 100 including three single-phase inverters A1, A2, and A3. The gradation level setting example shown in FIG. 7 can also be referred to as gradation level setting data. The examples of gradation levels, output voltages V1 to V3, and total output voltage Vsum shown in FIG. 7 are examples in which the ratio of the output voltages V1, V2, and V3 of the single-phase inverters A1, A2, and A3 is set to 1:3:8. The examples of gradation levels, output voltages V1, V2, and total output voltage Vsum shown in FIG. 11 are examples of settings for a power conversion device 100 including two single-phase inverters A1 and A2. The examples of gradation levels, output voltages V1, V2, and total output voltage Vsum shown in FIG. 11 are examples in which the ratio of the output voltages V1, V2 of the single-phase inverters A1 and A2 is set to 1:2. First, an example will be described in which the ratio of the output voltages V1, V2, and V3 of the single-phase inverters A1, A2, and A3 is set to 1:3:8.

[0037] Figure 7 shows the ratio of the gradation levels and the total output voltage Vsum when the ratio of the output voltages V1 to V3 of the three single-phase inverters A1 to A3 is 1:3:8. The ratio of the total output voltage Vsum is the ratio to the output voltage V1. In Figure 7, the states in which the three single-phase inverters A1 to A3 receive output commands for absolute voltages V1 to V3 are indicated by "1" or "-1," and the states in which they receive no output commands are indicated by "0." During periods in which the output polarity determination unit 33 (described later) determines a positive voltage command, the output voltages V1, V2, and V3 set to "1" become positive voltages +V1, +V2, and +V3, respectively. The output voltages V1, V2, and V3 set to "-1" become negative voltages -V1, -V2, and -V3, respectively. The output voltages V1, V2, and V3 set to "0" become zero voltage, 0V (volt).

[0038] Each single-phase inverter A outputs a positive voltage when it receives an output instruction of "1" during a period determined by the output polarity determination unit 33 (described later) to be a positive voltage instruction, and outputs a negative voltage when it receives an output instruction of "-1." Furthermore, each single-phase inverter A outputs a negative voltage when it receives an output instruction of "1" during a period determined by the output polarity determination unit 33 to be a negative voltage instruction, and outputs a positive voltage when it receives an output instruction of "-1." Furthermore, regardless of the voltage instruction, if the output instruction is "0," the single-phase inverter A outputs zero voltage. As an example, when the overall output voltage Vsum is to be output at gradation level 7 during a period when the output voltage instruction is a positive voltage instruction, this can be achieved by setting output voltage V3 to a positive voltage output, output voltage V2 to a zero voltage output, and output voltage V1 to a negative voltage output. In this case, the ratio of the overall output voltage Vsum to the minimum output voltage V1 is 8 + 0 - 1 = 7. The voltage ratio of the absolute value of the output voltage V1 of the single-phase inverter A1 that outputs the minimum output voltage to the minimum output voltage is 1. The overall output voltage Vsum at gradation level 7 is 7 x V1.

[0039] 7, the ratio of the total output voltage Vsum is 0, 1 to 12, and the gradation levels are 0, 1 to 12. The gradation level at which the ratio of the total output voltage Vsum is 4 is the special level SL, and the gradation level for the first voltage combination at the special level SL is written as 4a, and the gradation level for the second voltage combination at the special level SL is written as 4b. Note that the gradation levels at the special level SL may be written as numbers before the lowercase letters, instead of using the final lowercase letters such as "a" and "b" to distinguish between the voltage combinations.

[0040] 7, the power conversion device 100 operates with a combination of output voltages V1 to V3, and includes single-phase inverters A1 to A3 that output three different output voltages with a ratio of 1:3:8 between the output voltages V1 to V3, and is configured to achieve gradation level 4 with two voltage combinations. Specifically, gradation level 4, where the ratio of the overall output voltage Vsum is 4, can be achieved with a first voltage combination of V1: "1", V2: "1", and V3: "0", and a second voltage combination of V1: "-1", V2: "-1", and V3: "1".

[0041] A method for setting the gradation levels and voltage combinations shown in FIG. 7 will be described. The configuration of the power conversion device 100 of the first embodiment, which has gradation levels, i.e., special levels SL, that can be realized by combining the output voltages V of multiple single-phase inverters A, satisfies the following setting conditions. For example, if the absolute value of the output voltage V1 is the minimum output voltage Vmin, the voltage ratio of the absolute value |V1| of the output voltage of the single-phase inverter A1 that outputs the minimum output voltage Vmin to the minimum output voltage Vmin is 1. The single-phase inverter A1 that outputs the minimum output voltage Vmin, whose absolute value is greater than zero voltage and is the smallest, is defined as the smallest single-phase inverter. Let m and i be natural numbers. The first and second conditions are satisfied when J is the voltage ratio of the absolute value |Vm| of the output voltage Vm of the mth single-phase inverter Am, counted in ascending order of the absolute value of the output voltages excluding the smallest single-phase inverter, to the minimum output voltage |V1|, and K is the sum of the voltage ratios of the single-phase inverters whose voltage ratios are smaller than J. First condition: The other single-phase inverters excluding the smallest single-phase inverter satisfy formula (1). Second condition: At least one single-phase inverter satisfies the formula (2): J≦2K+1 (1) J=2K+1−i (2)

[0042] In addition, since the voltage ratio of a single-phase inverter that outputs the minimum output voltage Vmin to the minimum output voltage Vmin is 1, the voltage ratio J and the sum of the voltage ratios K may be expressed by setting the minimum voltage ratio of a single-phase inverter that outputs the minimum output voltage Vmin to 1.

[0043] Here, the single-phase inverter that satisfies the second condition is defined as the target single-phase inverter. Since the target single-phase inverter satisfies the second condition, the target single-phase inverter satisfies formula (3) included in formula (1), and other single-phase inverters that are not the target single-phase inverter satisfy formula (4) included in formula (1). J<2K+1 (3) J=2K+1 (4) Note that the target single-phase inverter is a single-phase inverter that reduces the number of switching operations, as described below.

[0044] The power conversion device 100 of the first embodiment includes at least one single-phase inverter that satisfies the formula (2), i.e., one target single-phase inverter, and it can also be said that the other single-phase inverters other than the target single-phase inverter satisfy the formula (4).

[0045] In the example shown in Figure 7 where the ratio of output voltages V1 to V3 is 1:3:8, single-phase inverter A1, whose output voltage V1 has a voltage ratio of 1, is the minimum single-phase inverter that outputs the minimum output voltage Vmin, output voltage V2, whose voltage ratio is 3, is a single-phase inverter that satisfies equation (4), and output voltage V3, whose voltage ratio is 8, is a single-phase inverter that satisfies equation (2), i.e., the target single-phase inverter. The voltage ratio of output voltage V2 of single-phase inverter A2 is K = 1, and from equation (4) J = 2 x 1 + 1 = 3 is set. The voltage ratio of output voltage V3 of single-phase inverter A3 is i = 1, and K = 1 + 3 = 4, and from equation (2) J = 2 x 4 + 1 - 1 = 8 is set.

[0046] Next, a control method for the power conversion device 100 of embodiment 1 will be described. The power conversion device 100 of embodiment 1 performs PWM control. Fig. 5 shows the configuration of the control unit 10 of the power conversion device 100. The control unit 10 includes an output instruction unit 31, a compensation unit 32, an output polarity determination unit 33, an absolute value processing unit 34, an integer processing unit 35, a subtraction unit 36, a pulse modulation unit 37, an addition unit 38, and a control signal generation unit 39.

[0047] The output instruction unit 31 outputs an output instruction value Oref, such as a sine wave or a DC waveform. The compensation unit 32 performs gain calculations on the output instruction value Oref and outputs a compensation signal Ocmp. The output polarity determination unit 33 outputs an output polarity instruction signal Opol that determines whether the polarity of the overall output voltage Vsum is positive or negative from the compensation signal Ocmp. The absolute value processing unit 34 outputs an absolute value signal Oabs obtained by converting the compensation signal Ocmp to an absolute value. The integer processing unit 35 outputs an integer signal Oint obtained by converting the absolute value signal Oabs to an integer value.

[0048] The subtraction unit 36 ​​outputs a decimal value signal Odeci by subtracting the integer value signal Oint from the absolute value signal Oabs. The pulse modulation unit 37 performs pulse width modulation on the decimal value signal Odeci at a carrier frequency to generate a decimal part PWM signal dPMW, and outputs this decimal part PWM signal dPMW. The addition unit 38 outputs an output voltage control signal Octnt by adding the decimal part PWM signal dPMW to the integer value signal Oint. The control signal generation unit 39 outputs n control signals S1N to SnN and n control signals S1P to SnP for controlling the switching elements QNH, QNL, QPH, and QPL of each of the single-phase inverters A1 to An based on the output polarity instruction signal Opol and the output voltage control signal Octnt.

[0049] The power conversion device 100 of the first embodiment generates control signals S1N-SnN and S1P-SnP that perform PWM control between adjacent gradation levels of the total output voltage Vsum based on the value of the compensation signal Ocmp that compensates for the output command value Oref, and controls each single-phase inverter A1-An using the control signals S1N-SnN and S1P-SnP to realize the total output voltage Vsum averaged to the value of the compensation signal Ocmp. For example, if the value of the compensation signal Ocmp that compensates for the output command value Oref is 2.5, the power conversion device 100 of the first embodiment realizes the total output voltage Vsum averaged to the value of the compensation signal Ocmp by performing PWM operation using a voltage combination of gradation level 2 and a voltage combination of gradation level 3. As described above, the power conversion device 100 of the first embodiment is configured so that there is a predetermined special level SL at which the same level of the total output voltage Vsum is realized by multiple voltage combinations of the output voltages V1-Vn of each single-phase inverter A1-An. That is, the power conversion device 100 of the first embodiment has a predetermined special level SL at which the same level of the total output voltage Vsum is realized by a voltage combination of a plurality of output voltages V. The power conversion device 100 of the first embodiment includes a special level SL at which the same total output voltage Vsum can be realized by a voltage combination of the output voltages V1 to Vn of the plurality of single-phase inverters A1 to An at the gradation level of the gradation control, and the control unit 10 selects a voltage combination of the output voltages V so as not to increase the number of switching times of the target single-phase inverter, which is a specific single-phase inverter, and controls each of the single-phase inverters A1 to An. More specifically, when changing the gradation level so as to include the special level at either the front or back, i.e., when changing from a gradation level other than the special level SL to the special level SL or when changing from the special level SL to a gradation level other than the special level SL, the control unit 10 selects a voltage combination of the output voltage V so as not to increase the number of switching times of the target single-phase inverter, which is a specific single-phase inverter, and controls each of the single-phase inverters A1 to An.

[0050] The operation of the power conversion device 100 of the first embodiment will be described using FIG. 8 . FIG. 8 shows a time series of gradation level changes selected based on the gradation level setting data shown in FIG. 7 so as to reduce the number of switching operations of a specific single-phase inverter, i.e., a target single-phase inverter. In the gradation level setting data shown in FIG. 7 , the ratio of output voltages V1 to V3 is 1:3:8, and the special level SL is set to gradation level 4. The special level SL has gradation levels 4a and 4b, which have different voltage combinations. For comparison, FIG. 9 shows gradation level setting data in which the ratio of output voltages V1 to V3 is 1:3:9 and does not have the special level SL. FIG. 10 shows an example of the operation of a comparative power conversion device using the gradation level setting data of FIG. 9 . The gradation level setting data of the comparative example shown in FIG. 9 is an example in which all output voltages V1 to V3 satisfy equation (4). Because the gradation level setting data of the comparative example in FIG. 9 does not have the special level SL, the number of gradation levels is greater than that of the gradation level setting data of FIG. 7 , up to gradation level 13.

[0051] Figure 8 shows voltage waveforms 41a, 41b, and 41c of the output voltages V3, V2, and V1, the order of one cycle of the control cycle Tc (i.e., the cycle ordinal number Nc), the waveform of the total output voltage Vsum, and the waveform of the compensation signal Ocmp. Figure 10 shows voltage waveforms 42a, 42b, and 42c of the output voltages V3, V2, and V1, the cycle ordinal number Nc, the waveform of the total output voltage Vsum, and the waveform of the compensation signal Ocmp. In Figures 8 and 10, the waveforms of the cycle ordinal number Nc and the compensation signal Ocmp are the same. In Figures 8 and 10, the horizontal axis represents time. The vertical axis of the total output voltage Vsum and the compensation signal Ocmp represents the grayscale level, and the vertical axis of the output voltages V3, V2, and V1 represents the digital voltage level.

[0052] 8 and 10 show operational waveforms in which the compensation signal Ocmp monotonically increases from a voltage correction value corresponding to gradation level 3 to a voltage correction value corresponding to gradation level 5. Also, both FIGS. 8 and 10 show a case in which the output polarity instruction signal Opol is positive, i.e., indicates a positive voltage. Times t0 to t12 shown in FIGS. 8 and 10 represent the start and end times of the cycle ordinal number Nc or ​​the times at which the total output voltage Vsum changes. Six control cycles Tc, each with cycle ordinal numbers Nc ranging from 1 to 6, are shown in FIGS. 8 and 10. Note that the example of the output voltage V3 shown in FIGS. 8 and 10 shows only "1" and "0" because the output polarity instruction signal Opol is positive, i.e., indicates a positive voltage, and the output voltage V3 in the gradation level setting data is only "1" and "0" and does not output a voltage level of "-1." When the output polarity instruction signal Opol is negative, i.e., indicates a negative voltage, the voltage levels of the voltage waveforms 41b, 41c and voltage waveforms 42b, 42c of the output voltages V2, V1 are inverted between positive and negative, and the voltage levels of the voltage waveforms 41a and 42a of the output voltage V3 change between "0" and "-1."

[0053] 8, when the compensation signal Ocmp is between gradation level 3 and gradation level 4, the voltage combination of gradation level 3 and the voltage combination of gradation level 4a are used, and when the compensation signal Ocmp is between gradation level 4 and gradation level 5, the voltage combination of gradation level 4b and the voltage combination of gradation level 5 are used. It can be seen from FIG. 8 that the single-phase inverters A2 and A3 that output the output voltages V2 and V3 perform switching only at the timing when the gradation level becomes 4 (time t6).

[0054] The operation example of FIG. 8 will be explained in detail. The compensation signal Ocmp is at gradation level 3 at time t0, at gradation level 4 at time t6, and at gradation level 5 at time t12. The gradation levels of the output voltages V3, V2, and V1 change from time t0 to t12 as follows. From time t0 to t6, the output voltages V3, V2, and V1 are PWM controlled at voltages set at gradation level 3 and gradation level 4a, respectively. From time t6 to t12, the output voltages V3, V2, and V1 are PWM controlled at voltages set at gradation level 4b and gradation level 5, respectively. The gradation level is 3 from time t0 to t1, gradation level 4a from time t1 to t2, gradation level 3 from time t2 to t3, and gradation level 4a from time t3 to t4. The period from time t4 to time t5 is gradation level 3, and the period from time t5 to time t6 is gradation level 4a. The period from time t6 to time t7 is gradation level 4b, and the period from time t7 to time t8 is gradation level 5. The period from time t8 to time t9 is gradation level 4b, the period from time t9 to time t10 is gradation level 5, the period from time t10 to time t11 is gradation level 4b, and the period from time t11 to time t12 is gradation level 5.

[0055] Next, let us look at the comparative example in FIG. 10 . In the comparative example in FIG. 10 , the gradation level setting data in FIG. 9 is used. In the comparative example in FIG. 10 , when the compensation signal Ocmp is between gradation levels 3 and 4, the voltage combination for gradation level 3 and the voltage combination for gradation level 4 are used, and when the compensation signal Ocmp is between gradation levels 4 and 5, the voltage combination for gradation level 4 and the voltage combination for gradation level 5 are used. In FIG. 10 , it can be seen that when the compensation signal Ocmp is between gradation levels 3 and 4, the single-phase inverters A2 and A3 that output output voltages V2 and V3 do not perform switching, but when the compensation signal Ocmp is between gradation levels 4 and 5, the single-phase inverters A2 and A3 that output output voltages V2 and V3 perform switching multiple times.

[0056] The operation of the comparative example in Figure 10 will be described in detail. As in Figure 8, the compensation signal Ocmp is at gradation level 3 at time t0, gradation level 4 at time t6, and gradation level 5 at time t12. The gradation levels of the output voltages V3, V2, and V1 change from time t0 to t12 as follows: from time t0 to time t1 it is at gradation level 3, from time t1 to time t2 it is at gradation level 4, from time t2 to time t3 it is at gradation level 3, and from time t3 to time t4 it is at gradation level 4. From time t4 to time t5 it is at gradation level 3, and from time t5 to time t6 it is at gradation level 4. From time t6 to time t7 it is at gradation level 4, and from time t7 to time t8 it is at gradation level 5. The period from time t8 to time t9 is gradation level 4, the period from time t9 to time t10 is gradation level 5, the period from time t10 to time t11 is gradation level 4, and the period from time t11 to time t12 is gradation level 5.

[0057] As described above, the power conversion device 100 of the first embodiment has gradation level setting data in which the ratios of the output voltages V1 to Vn of the single-phase inverters A1 to An are set so that there is a gradation level, i.e., a special level SL, that can be achieved by a voltage combination of multiple output voltages V. Furthermore, by devising the selection of the voltage combinations of the output voltages V1 to Vn used for PWM control, the number of switching operations of a specific single-phase inverter, i.e., a target single-phase inverter, can be reduced. The gradation level setting data is stored, for example, in the control signal generating unit 39 of the control unit 10. In the example of FIG. 8 , the target single-phase inverter is the single-phase inverter A3 that outputs the output voltage V3. Note that in FIG. 8 , although the single-phase inverter A2 that outputs the output voltage V2 is not the target single-phase inverter in the gradation level setting data, the single-phase inverter A2 is an example in which the number of switching operations can be reduced.

[0058] The power conversion device 100 of the first embodiment reduces the number of switching operations of the target single-phase inverter, thereby reducing the switching loss generated in the target single-phase inverter. This reduces the loss, thereby enabling the power conversion device 100 to be highly efficient. Furthermore, the power conversion device 100 of the first embodiment reduces heat generation in the power converter 50, thereby increasing the options for the types of switching elements, enabling the use of a smaller heat sink, and thus enabling the miniaturization of the power conversion device 100. The power conversion device of Patent Document 1 has a problem in that the components and heat sink constituting the single-phase inverter are large, resulting in a large-sized power conversion device, which increases the cost of the power conversion device. In contrast, the power conversion device 100 of the first embodiment increases the options for the types of switching elements, allowing the use of smaller switching elements and heat sinks, thereby enabling the miniaturization of the power conversion device 100, thereby enabling the use of a low-cost power conversion device 100.

[0059] When switching the single-phase inverter A, a dead time is provided to prevent short-circuiting of the half-bridge inverters BN and BP of the single-phase inverter A. During the dead time, the output voltage cannot be controlled, which causes the output waveform to become distorted. The power conversion device 100 of the first embodiment reduces the number of switching operations of the target single-phase inverter, thereby making it possible to relatively shorten the dead time, which is also effective in preventing distortion of the output voltage.

[0060] The target single-phase inverter is particularly desirable to apply to single-phase inverters with large voltage ratios. Single-phase inverters with large voltage ratios need to use switching elements with high withstand voltages. In general, switching elements with high withstand voltages have characteristics such as lower switching speeds compared to switching elements with low withstand voltages, so a longer dead time is required, resulting in large switching losses. Furthermore, switching a large voltage results in larger switching losses than switching a small voltage. For this reason, the target single-phase inverter that reduces the number of switching operations according to embodiment 1 is highly effective when applied to single-phase inverters with large voltage ratios.

[0061] In FIG. 8 , the voltage combination of gradation level 4a at special level SL is switched to the voltage combination of gradation level 4b when the compensation signal Ocmp reaches 4. However, the timing of switching gradation levels is not limited to this, and other timings may be used. While the switching timing shown in FIG. 8 is dependent on the compensation signal, the switching timing may also be dependent on adjacent gradation levels based on a change to a gradation level adjacent to special level SL. Specifically, in the gradation level setting data of FIG. 7 , the gradation levels other than the special level adjacent to special level SL are gradation level 5 and gradation level 3. Gradation level 4a continues to be used until the voltage combination of gradation level 5 in FIG. 8 is required, that is, until time t7 in the period when cycle ordinal number Nc is 4. Gradation level 5 may then be used before gradation level 4b begins to be used. Furthermore, when switching from a voltage combination of gradation level 4b to an adjacent gradation level below special level SL, gradation level 4b may continue to be used until the voltage combination of gradation level 3 is required, and then gradation level 3 may be used before gradation level 4a begins to be used. Note that the adjacent gray level dependency occurs when the gray level is switched with a delay from the timing of arrival of the compensation signal, and therefore can also be said to be a switching timing with hysteresis.

[0062] In the gradation level setting data of FIG. 7 , the target single-phase inverter for reducing the number of switching operations was the single-phase inverter A3, which outputs an output voltage V3. As shown in FIG. 7 , this single-phase inverter A3 has a state change from "0" to "1." FIG. 8 shows that the number of switching operations of the single-phase inverter A3 can be reduced when the state changes from "0" to "1." FIG. 8 also shows that the number of switching operations of the single-phase inverter A2, which outputs an output voltage V2 that is not the target single-phase inverter, is reduced. However, the number of switching operations of V2 is reduced only when the state changes from "1" to "-1." In the gradation level setting data of FIG. 7 , the output voltage V2 of the single-phase inverter A2 also changes from "0" to "1" and from "-1" to "0," and the number of switching operations in these cases is not reduced. To reduce the number of switching operations of the output voltage V2 of the single-phase inverter A2 for all state changes, the output voltage V2 must also be set to a voltage ratio that satisfies Equation (2).

[0063] In the comparative example in which the gradation level setting data does not have the special level SL, the number of switching operations of the single-phase inverter A2 that outputs the output voltage V2 is not reduced even when the state changes from "1" to "-1." Therefore, the power conversion device 100 of the first embodiment can also reduce the number of switching operations of the single-phase inverter A2 that outputs the output voltage V2 that is not the target single-phase inverter, although only for some changing states. This is because the power conversion device 100 of the first embodiment has the special level SL in the gradation level setting data, and therefore, an effect is obtained in that the number of switching operations of the single-phase inverter that is not the target single-phase inverter can also be reduced compared to the comparative example.

[0064] The gradation level setting data shown in FIG. 11 is an example of gradation level setting data for a second power conversion device 100 including two single-phase inverters A1 and A2. The single-phase inverter A2 that outputs an output voltage V2 is the target single-phase inverter, and the voltage ratio of the output voltage V2 satisfies equation (2) in which i is 1. The single-phase inverter A1, which outputs an output voltage V1 with a voltage ratio of 1, is the minimum single-phase inverter that outputs a minimum output voltage Vmin. The voltage ratio of the output voltage V2 is K=1, and from equation (2), J=2×1+1−1=2 is set. Similar to the first power conversion device 100, the second power conversion device 100 can also reduce the number of switching operations of the target single-phase inverter, thereby realizing a compact, gradation-controlled power conversion device.

[0065] As described above, the power conversion device 100 of embodiment 1 includes a special level SL that can achieve the same overall output voltage Vsum by combining the output voltages V1 to Vn of multiple single-phase inverters A1 to An at the gradation level of the gradation control, and when the control unit 10 performs PWM control on the power converter 50 using the special level SL, it selects one voltage combination at the special level SL that does not change at least one output voltage (for example, output voltage Vn) excluding the minimum output voltage (output voltage V1) whose absolute value other than zero voltage is the smallest, so that a small-sized gradation-controlled power conversion device can be realized.

[0066] FIGS. 1 and 3 show an example in which the drive signals so1 to son for all single-phase inverters A1 to An are generated by a single gate driver GD1 to GD2. That is, the example shows a case in which the two half-bridge inverters BN and BP of single-phase inverter A are driven by a single gate driver GD. However, this is not a limitation. The gate driver GD may have a different configuration, such as two gate drivers capable of driving one half-bridge inverter, i.e., a first gate driver for driving half-bridge inverter BN and a second gate driver for driving half-bridge inverter BP are configured as separate components. Also, FIGS. 1 and 3 show an example in which the gate driver GD generates the drive signal so using control signals SN and SP for single-phase inverter A output from control unit 10 and a control signal obtained by inverting the control signals SN and SP using inverter 61. However, this is not a limitation. For example, a gate driver GD in which the inverter 61 is omitted and the control unit 10 outputs control signals SN and SP as well as control signals obtained by logically inverting the control signals SN and SP may be used. Alternatively, the inverter 61 and the dead time generation units DTN and DTP may be removed from the gate driver GD, and these dead time generation units DTN and DTP may be provided in the control unit 10, with the dead time signals sdtNH, sdtNL, sdtPH, and sdtPL being output to the gate driver GD from the control unit 10. In this case, the control unit 10 outputs a control signal to which a dead time has been added to the gate driver GD.

[0067] Although the configuration example of the single-phase inverter A shown in FIG. 2 illustrates a case where the polarity of the output voltage V can be switched and output, the single-phase inverter A is not limited to this. If the power conversion device 100 is required to output only a single-polarity output voltage to the load 20, the single-phase inverter A may be configured with only one half-bridge inverter. For example, in the case of the power conversion device 100 that is required to output only a positive voltage, the switching element QNH on the high-side (i.e., high-potential side wiring Lh) side of the half-bridge inverter BN in FIG. 2 may be removed to be in an open state, and the drain terminal d and source terminal s of the switching element QNL on the low-side (i.e., low-potential side wiring Ll) side may be shorted, thereby configuring the single-phase inverter A with only the half-bridge inverter BP. The low-side switching element QNL may also be removed. For example, in the case of the power conversion device 100 that is required to output only a negative voltage, the high-side switching element QPH on the half-bridge inverter BP in FIG. 2 may be removed to be in an open state, and the drain terminal d and source terminal s of the low-side switching element QPL may be shorted, thereby configuring the single-phase inverter A with only the half-bridge inverter BN. The low-side switching element QPL may be removed.

[0068] In FIG. 5, the control unit 10 is configured to have the output instruction unit 31 inside, but the output instruction unit 31 may be located outside the control unit 10, and the control unit 10 may receive the output instruction value Oref from outside.

[0069] While the power conversion device 100 of the first embodiment has been described assuming PWM operation, it can also be applied to control without PWM operation. For example, it can also be applied to a configuration in which the subtractor 36, pulse modulator 37, and adder 38 are removed from the control unit 10. When the subtractor 36, pulse modulator 37, and adder 38 are removed, the gradation level is selected based on the integer conversion signal Oint output from the integer conversion processor 35. In this configuration, if fluctuations in the compensation signal Ocmp occur as shown in FIG. 14 of the comparative example in the second embodiment described below, a single-phase inverter with a high output voltage may switch in the comparative example without a special level. However, if the special level SL described herein is provided, switching can be reduced. The power conversion devices 100 of the second to sixth embodiments described below can also be applied to control without PWM operation.

[0070] As described above, the power conversion device 100 of the first embodiment includes a power converter 50 in which the AC sides (output terminals N and P) of a plurality of single-phase inverters A that convert DC power to AC power are connected in series, and which supplies DC or AC power of a total output voltage Vsum, which is the sum of the output voltages V output by the plurality of single-phase inverters A, to a load 20, and a control unit 10 that controls the power converter 50. In the following description, symbols are used in the case where the gradation level setting data shown in FIG. 7 is used. The single-phase inverter A1 that outputs a minimum output voltage (output voltage V1), the absolute value of which is greater than zero and is the smallest, is referred to as the minimum single-phase inverter. The absolute values ​​of the total output voltage Vsum, which can be discretely set by selectively combining the outputs of the plurality of single-phase inverters A, are referred to as gradation levels, and the predetermined gradation levels at which the same level of the total output voltage Vsum is realized by a plurality of voltage combinations, which are combinations of the output voltages V, are referred to as special levels SL. The settable gradation levels include at least one special level SL. The control unit 10 controls the single-phase inverters A to output a total output voltage Vsum of a set voltage value by selecting a combination of the output voltages V of the single-phase inverters A. When changing the gradation level to include a special level at either the front or rear end, i.e., when changing from a gradation level other than the special level SL to the special level SL or when changing from the special level SL to a gradation level other than the special level SL, the control unit 10 selects a voltage combination that does not change the output voltage V3 of at least one single-phase inverter A3, excluding the smallest single-phase inverter (single-phase inverter A1). With this configuration, the power conversion device 100 of the first embodiment includes a special level SL that can achieve the same total output voltage Vsum with a combination of the output voltages V1, V2, and V3 of the single-phase inverters A1, A2, and A3 in the gradation level. When the control unit 10 controls the power converter 50 using the special level SL, the control unit 10 selects a voltage combination that does not change at least one output voltage V3, excluding the minimum output voltage (output voltage V1) with the smallest absolute value. This allows for a compact, gradation-controlled power conversion device.

[0071] Second Embodiment. FIG. 12 is a diagram showing examples of gradation levels and output voltages in a power conversion device according to a second embodiment, and FIG. 13 is a diagram showing a first example of the operation of the power conversion device according to the second embodiment. FIG. 14 is a diagram showing an example of the operation of a power conversion device of a comparative example, and FIG. 15 is a diagram showing a second example of the operation of the power conversion device according to the second embodiment. In the first embodiment, conditions for achieving gradation levels, i.e., special levels SL, that can be achieved by combining the output voltages V of multiple single-phase inverters A were shown, and an example was shown in which i = 1 was applied to equation (2) of the second condition, setting the ratio of output voltages V1 to V3 to 1:3:8. The value of i is not limited to 1. By setting the value of i to 2 or greater, two or more special levels SL can be set. The power conversion device 100 according to the second embodiment is an example having gradation level setting data with two or more special levels SL. The gradation level setting data is stored, for example, in the control signal generating unit 39 of the control unit 10. Differences from the power conversion device 100 according to the first embodiment will be mainly described.

[0072] Applying i=2 to equation (2) results in gradation level setting data in which the ratio of the output voltages V1 to V3 is 1:3:7, and applying i=3 to equation (2) results in gradation level setting data in which the ratio of the output voltages V1 to V3 is 1:3:6. FIG. 12 shows examples of gradation levels and output voltages V1 to V3 in the power conversion device 100 of embodiment 2, i.e., examples of gradation level setting data. The gradation level setting data shown in FIG. 12 is an example in which i=2 is applied to equation (2). In FIG. 12, the ratio of the total output voltage Vsum is 0, 1 to 11, and the gradation levels are 0, 1 to 11. Gradation level 3, in which the ratio of the total output voltage Vsum is 3, is the first special level SLa, and gradation level 4, in which the ratio of the total output voltage Vsum is 4, is the second special level SLb. The gradation level for the first voltage combination at the first special level SLa is written as 3a, and the gradation level for the second voltage combination at the first special level SLa is written as 3b. Similarly, the gradation level for the first voltage combination at the second special level SLb is written as 4a, and the gradation level for the second voltage combination at the second special level SLb is written as 4b. The gradation level setting data shown in FIG. 12 is an example in which two special levels SL are set. The special levels are generally designated as SL, and SLa and SLb are used when distinguishing between them. Note that when there are three or more special levels SL and they are distinguished by adding a lowercase letter after "SL" and using the names SLa, SLb, SLc, SLd, etc.

[0073] The operation of the power conversion device 100 of the second embodiment will be described with reference to Fig. 13. Fig. 13 shows a first example of the operation of the power conversion device 100 of the second embodiment, and is an example of an operating waveform in which a time series of gradation level changes is selected so as to reduce the number of switching times of a specific single-phase inverter, i.e., a target single-phase inverter, based on the gradation level setting data in which the ratio of the output voltages V1 to V3 shown in Fig. 12 is 1:3:7. The target single-phase inverter is the single-phase inverter A3 that outputs the output voltage V3.

[0074] FIG. 13 shows voltage waveforms 43a, 43b, and 43c of the output voltages V3, V2, and V1, the period ordinal number Nc, the waveform of the total output voltage Vsum, and the waveform of the compensation signal Ocmp. In FIG. 13, the horizontal axis represents time. The vertical axes of the total output voltage Vsum and the compensation signal Ocmp represent the gradation level, and the vertical axes of the output voltages V3, V2, and V1 represent the digital voltage level. Note that the example of the output voltage V3 shown in FIG. 13 shows only "1" and "0" because the output polarity instruction signal Opol is positive, i.e., indicates a positive voltage, and the output voltage V3 in the gradation level setting data is only "1" and "0" and does not output a voltage level of "-1." Note that if the output polarity instruction signal Opol is negative, i.e., indicates a negative voltage, the voltage levels of the voltage waveforms 43b and 43c of the output voltages V2 and V1 are inverted, and the voltage level of the voltage waveform 43a of the output voltage V3 changes between "0" and "-1."

[0075] FIG. 13 shows operational waveforms when the compensation signal Ocmp monotonically increases from a voltage correction value corresponding to gradation level 2 to a voltage correction value corresponding to gradation level 5, and when gradation level switching is dependent on adjacent gradation levels. FIG. 13 also shows a case where the output polarity instruction signal Opol is positive, i.e., indicates a positive voltage. Times t0 to t18 shown in FIG. 13 are the start and end times of the cycle ordinal number Nc, or the times when the overall output voltage Vsum changes. FIG. 13 shows nine control cycles Tc, with cycle ordinal numbers Nc ranging from 1 to 9. In the gradation level setting data of FIG. 12, the gradation levels other than the special levels adjacent to special levels SLa and SLb are gradation level 2 and gradation level 5.

[0076] 13, when the compensation signal Ocmp monotonically increases, gradation levels 3a and 4a continue to be used until the voltage combination of gradation level 5 becomes necessary, that is, until the timing of time t13 in the period when the cycle ordinal number Nc is 7. Then, once gradation level 5 has been used, gradation levels 3b and 4b are used unless the voltage combination of gradation level 2 is used.

[0077] The operation example of FIG. 13 will be explained in detail. The compensation signal Ocmp is at gradation level 2 at time t0, gradation level 3 at time t6, gradation level 4 at time t12, and gradation level 5 at time t18. The gradation levels of the output voltages V3, V2, and V1 change from time t0 to t18 as follows: From time t0 to time t7, the output voltages V3, V2, and V1 are PWM-controlled with voltages set at gradation level 2 and gradation level 4a, respectively. From time t7 to time t13, the output voltages V3, V2, and V1 are PWM-controlled with voltages set at gradation level 3a and gradation level 4a, respectively. From time t13 to time t18, the output voltages V3, V2, and V1 are PWM-controlled with voltages set at gradation level 4b and gradation level 5, respectively.

[0078] The period from time t0 to time t1 is gradation level 2, the period from time t1 to time t2 is gradation level 3a, the period from time t2 to time t3 is gradation level 2, and the period from time t3 to time t4 is gradation level 3a. The period from time t4 to time t5 is gradation level 2, and the period from time t5 to time t7 is gradation level 3a. The period from time t7 to time t8 is gradation level 4a, the period from time t8 to time t9 is gradation level 3a, the period from time t9 to time t10 is gradation level 4a, and the period from time t10 to time t11 is gradation level 3a. The period from time t11 to time t13 is gradation level 4a, and the period from time t13 to time t14 is gradation level 5. The period from time t14 to time t15 is gradation level 4b, the period from time t15 to time t16 is gradation level 5, the period from time t16 to time t17 is gradation level 4b, and the period from time t17 to time t18 is gradation level 5.

[0079] As shown in FIG. 13 , the power conversion device 100 of the second embodiment, like the power conversion device 100 of the first embodiment, has gradation level setting data in which the ratios of the output voltages V1 to Vn of the single-phase inverters A1 to An are set so that there is a gradation level, i.e., a special level SL, that can be realized by a voltage combination of multiple output voltages V. Furthermore, by devising the selection of the voltage combinations of the output voltages V1 to Vn used for PWM control, the number of switching operations of a specific single-phase inverter, i.e., a target single-phase inverter, can be reduced. In the example of FIG. 13 , the target single-phase inverter is single-phase inverter A3 that outputs output voltage V3. Note that in FIG. 13 , although single-phase inverter A2 that outputs output voltage V2 is not the target single-phase inverter in the gradation level setting data, single-phase inverter A2 is an example in which the number of switching operations can be reduced.

[0080] The power conversion device 100 of the second embodiment has two or more special levels and switches between gradation levels depending on adjacent gradation levels, thereby achieving advantageous effects not described in the first embodiment. Setting a large number of special levels SL, which are gradation levels that can be achieved by voltage combinations of the output voltages V of multiple single-phase inverters A, increases the number of gradation levels that a specific single-phase inverter, i.e., a target single-phase inverter, can output without switching, compared to other cases, thereby extending the period during which the target single-phase inverter does not switch. This is advantageous when the output voltage control signal Oct is suddenly changed, for example, when large noise is applied to the output instruction value Oref output by the output instruction unit 31. Operation when the compensation signal Ocmp suddenly changes will be described using FIGS. 14 and 15 .

[0081] FIG. 14 shows an example of operation when the ratio of output voltages V1 to V3 is 1:3:8, i.e., based on the gradation level setting data of FIG. 7 , and FIG. 15 shows an example of operation when the ratio of output voltages V1 to V3 is 1:3:7, i.e., based on the gradation level setting data of FIG. 12 . FIG. 14 shows an example of operation of a comparative example of power conversion device 100 of embodiment 2, and FIG. 15 shows a second example of operation of power conversion device 100 of embodiment 2. FIGS. 14 and 15 show operational waveforms when a drop of a magnitude equivalent to gradation level 1 occurs in compensation signal Ocmp during the period from gradation level 4 to gradation level 5 while compensation signal Ocmp is rising. In FIG. 14 , compensation signal Ocmp is at gradation level 3 at time t0, gradation level 4 at time t6, and gradation level 5 at time t12. 15, the compensation signal Ocmp is at gradation level 3 at time t6, at time t12 at gradation level 4, and at time t18 at gradation level 5. Therefore, the period from time t0 to time t12 in FIG. 14 will be compared with the period from time t6 to time t18 in FIG.

[0082] In the example of operation of the comparative example in Fig. 14, when a drop in the compensation signal Ocmp occurs, that is, from time t8 to time t10, the output voltages V3 and V2 switch twice. In contrast, in the example of operation of the second embodiment in Fig. 15, when a drop in the compensation signal Ocmp occurs, that is, from time t14 to time t17, the output voltages V3 and V2 remain constant.

[0083] The operation during the period from time t7 to time t12 in FIG. 14 is as follows: from time t7 to time t8, the grayscale level is 5; from time t8 to time t9, the grayscale level is 3; from time t9 to time t11, the grayscale level is 4a; and from time t11 to time t12, the grayscale level is 5. The operation during the period from time t7 to time t12 in FIG. 14 is the operation when grayscale level switching is performed depending on the compensation signal rather than on the adjacent grayscale level. Note that, during the period from time t7 to time t12 in FIG. 14, when grayscale level switching is performed depending on the adjacent grayscale level rather than on the compensation signal, the grayscale level is 4b from time t9 to time t11. In this case, at time t9, the output voltage V3 changes from voltage level 0 to voltage level 1, the output voltage V2 changes from voltage level 1 to voltage level −1, and the output voltage V1 changes from voltage level 0 to voltage level −1. Thereafter, until time t11, the output voltage V3 remains at voltage level 1, the output voltage V2 remains at voltage level −1, and the output voltage V1 remains at voltage level −1. At time t11, the output voltage V3 remains at voltage level 1, the output voltage V2 remains at voltage level −1, and the output voltage V1 changes from voltage level −1 to voltage level 0. In the operation from time t7 to time t12 in FIG. 14, even though it is compensation signal-dependent gradation level switching and adjacent gradation level-dependent gradation level switching, the output voltages V3 and V2 switch twice.

[0084] Like the power conversion device 100 of the first embodiment, the power conversion device 100 of the second embodiment has gradation level setting data including at least one gradation level that can be realized by a voltage combination of a plurality of output voltages V, i.e., one of the special levels SLa and SLb, and therefore achieves the same effects as the power conversion device 100 of the first embodiment. Furthermore, the power conversion device 100 of the second embodiment has gradation level setting data including two or more gradation levels that can be realized by a voltage combination of a plurality of output voltages V, i.e., two or more of the special levels SLa and SLb, and therefore can reduce the number of switching operations of the target single-phase inverter even if the compensation signal Ocmp changes suddenly. Therefore, the power conversion device 100 of the second embodiment can increase the fluctuation amount of the compensation signal Ocmp, which can suppress switching of the target single-phase inverter, and can suppress the occurrence of switching losses in the target single-phase inverter and the power converter 50.

[0085] On the other hand, in the power conversion device 100 of the second embodiment, the absolute number of settable gradation levels decreases as the number of settable gradation levels increases by combining the output voltages V1 to Vn of the multiple single-phase inverters A1 to An. Therefore, it is desirable to check the degree of fluctuation in the compensation signal Ocmp and optimally design the number of settable gradation levels by combining the output voltages V1 to Vn of the single-phase inverters A1 to An.

[0086] Third Embodiment. FIG. 16 is a diagram showing an example of gradation levels and output voltages in a power conversion device according to a third embodiment. The gradation level setting data in the first and second embodiments satisfies the first and second conditions. The third embodiment provides an example of gradation level setting data that satisfies the third or fourth condition shown below. Differences from the power conversion device 100 of the first and second embodiments will be mainly described. The gradation level setting data in the first and second embodiments is suitable for most effectively increasing the number of gradation levels per single-phase inverter A among configurations that can output gradation levels for each gradation. The gradation level setting data shown in FIG. 7 is for the case where i is 1, and the number of gradation levels per single-phase inverter A is 12 / 3 = 4. The gradation level setting data shown in FIG. 12 is for the case where i is 2, and the number of gradation levels per single-phase inverter A is 11 / 3 = 3.7. In the gradation level setting data shown in FIG. 16, the number of gradation levels per number of single-phase inverters A is 7 / 3=2.3.

[0087] The power conversion device 100 of the third embodiment includes a single-phase inverter A that outputs at least three different output voltages V, and the gradation levels that can be realized by combining the output voltages V of the multiple single-phase inverters A, i.e., the gradation level setting data, need only have at least one special level SL. For example, the gradation level setting data may have at least one special level SL, and the ratio of the output voltages V1 to V3 may be 1:2:4, etc. For example, the third condition is satisfied when the minimum voltage ratio of the smallest single-phase inverter, which is the single-phase inverter that outputs the minimum output voltage Vmin, is 1, m is a natural number, the voltage ratio of the absolute value |Vm| of the output voltage Vm of the mth single-phase inverter Am, counted in ascending order of absolute value of the output voltages excluding the smallest single-phase inverter, to the minimum output voltage Vmin is J, and the sum of the voltage ratios of the single-phase inverters whose voltage ratios are smaller than J is K. Third condition: The other single-phase inverters excluding the smallest single-phase inverter satisfy Equation (5). J = K + 1 (5)

[0088] In the example shown in Figure 16 where the ratio of output voltages V1 to V3 is 1:2:4, single-phase inverter A1, whose output voltage V1 has a voltage ratio of 1, is the smallest single-phase inverter that outputs the minimum output voltage Vmin, output voltage V2, whose voltage ratio is 2, is the output voltage of single-phase inverter A2 that satisfies equation (5), and output voltage V3, whose voltage ratio is 4, is the output voltage of single-phase inverter A3 that satisfies equation (5). The voltage ratio of output voltage V2 of single-phase inverter A2 is K = 1, and from equation (5), J = 1 + 1 = 2 is set. The voltage ratio of output voltage V3 of single-phase inverter A3 is K = 1 + 2 = 3, and from equation (5), J = 3 + 1 = 4 is set.

[0089] In the gradation level setting data of the third embodiment shown in FIG. 16, unlike the first and second embodiments, it is not possible to distinguish between the target single-phase inverter and other single-phase inverters based on the difference in formula, and therefore each single-phase inverter is controlled so as to reduce the number of switching times of the target single-phase inverter by using a single-phase inverter other than the single-phase inverter that outputs the minimum output voltage Vmin as the target single-phase inverter.

[0090] The gradation level setting data shown in FIG. 16 is an example in which four special levels SLa, SLb, SLc, and SLd are set. The special level SLa is set to gradation level 1, and has three voltage combinations. The gradation level for the first voltage combination in the special level SLa is written as 1a, the gradation level for the second voltage combination in the special level SLa is written as 1b, and the gradation level for the third voltage combination in the special level SLa is written as 1c. The special level SLb is set to gradation level 2, and has two voltage combinations. The gradation level for the first voltage combination in the special level SLb is written as 2a, and the gradation level for the second voltage combination in the special level SLb is written as 2b.

[0091] The special level SLc is set to gradation level 3 and has three voltage combinations. The gradation level for the first voltage combination in the special level SLc is described as 3a, the gradation level for the second voltage combination in the special level SLc is described as 3b, and the gradation level for the third voltage combination in the special level SLc is described as 3c. The special level SLd is set to gradation level 5 and has two voltage combinations. The gradation level for the first voltage combination in the special level SLd is described as 5a, and the gradation level for the second voltage combination in the special level SLd is described as 5b.

[0092] For example, if it is desired to reduce the number of switching times of the single-phase inverter A3 of the output voltage V3, a voltage combination at a special level may be selected at the timing dependent on the adjacent gradation level as described in embodiment 2. For example, gradation levels 1a, 2a, and 3a may be used until the compensation signal Ocmp reaches gradation level 4, and once the compensation signal Ocmp reaches gradation level 4, gradation levels 1c, 2b, and 3b may be used until the compensation signal Ocmp reaches gradation level 0.

[0093] As described above, when the minimum voltage ratio of the smallest single-phase inverter that outputs the minimum output voltage Vmin is 1, m is a natural number, the voltage ratio of the absolute value |Vm| of the output voltage Vm of the mth single-phase inverter Am to the minimum output voltage Vmin is J, and the sum of the voltage ratios of the single-phase inverters whose voltage ratios are smaller than J is K, even in a configuration designed to satisfy the third condition, it is possible to achieve an operation that reduces the number of switching times of the target single-phase inverter, as in embodiment 1.

[0094] The gradation level setting data of the third embodiment may satisfy not only the third condition but also the fourth condition. For example, even if the ratio of the output voltages V1 to V3 is 1:2:6, the gradation level setting data may include at least one special level SL. The gradation level setting data may satisfy the fourth condition when the minimum voltage ratio of the smallest single-phase inverter that outputs the minimum output voltage Vmin is 1, m and i are natural numbers, the voltage ratio of the absolute value |Vm| of the output voltage Vm of the mth single-phase inverter Am to the minimum output voltage Vmin is J, and the sum of the voltage ratios of the single-phase inverters whose voltage ratios are smaller than J is K. Fourth condition: Other single-phase inverters that output an output voltage greater than the minimum output voltage Vmin include single-phase inverters that satisfy Equation (5) and single-phase inverters that satisfy Equation (2).

[0095] An example of gradation level setting data in which the ratio of output voltages V1 to V3 is 1:2:6 will be described. Single-phase inverter A1, whose output voltage V1 has a voltage ratio of 1, is the smallest single-phase inverter that outputs the minimum output voltage Vmin. Output voltage V2, whose voltage ratio is 2, is the output voltage of single-phase inverter A2 that satisfies equation (5). Output voltage V3, whose voltage ratio is 6, is the output voltage of single-phase inverter A3 that satisfies equation (2) with i set to 1. The voltage ratio of output voltage V2 of single-phase inverter A2 is K=1, and from equation (5), J=1+1=2 is set. The voltage ratio of output voltage V3 of single-phase inverter A3 is K=1+2=3, and from equation (2), J=2×3+1−1=6 is set.

[0096] As described above, the gradation level setting data of the first and second embodiments has the advantage of being able to maximize the number of gradation levels per single-phase inverter A among configurations capable of outputting gradation levels one gradation at a time. On the other hand, the gradation level setting data of the third embodiment has a smaller number of gradation levels per single-phase inverter A than the gradation level setting data of the first and second embodiments. However, the power conversion device 100 of the third embodiment, to which the gradation level setting data of the third embodiment is applied, has a larger number of special levels SL than the gradation level setting data of the first and second embodiments. Therefore, the power conversion device 100 of the third embodiment can appropriately respond to sudden changes in the compensation signal Ocmp and reduce the number of switching operations of the target single-phase inverter compared to the power conversion devices 100 of the first and second embodiments. That is, the power conversion device 100 of the third embodiment can increase the fluctuation amount of the compensation signal Ocmp, which can suppress switching of the target single-phase inverter, compared to the power conversion devices 100 of the first and second embodiments.

[0097] An example of gradation level setting data in the power conversion device 100 including two single-phase inverters A1 and A2 that satisfy formula (5) is shown in Fig. 11. In this case, only one special level SL is set for gradation level 1. Even when there is one special level SL, the power conversion device 100 of embodiment 3 to which gradation level setting data by the two single-phase inverters A1 and A2 that satisfy formula (5) is applied achieves the same effects as the power conversion device 100 of embodiment 1.

[0098] Fourth Embodiment. FIG. 17 is a diagram showing an example of gradation levels and output voltages in a power conversion device according to a fourth embodiment, and FIG. 18 is a diagram showing an example of operation of the power conversion device according to the fourth embodiment. FIG. 19 is a diagram showing an example of gradation levels and output voltages in a power conversion device of a comparative example, and FIG. 20 is a diagram showing an example of operation of the power conversion device of the comparative example. The gradation level setting data in the first to third embodiments has been described as being realized by a single-phase inverter A that outputs three types of output voltages V, i.e., output voltages V indicated as "1," "-1," and "0." That is, the power conversion device 100 in the first to third embodiments has been described as being realized by an example in which multiple single-phase inverters A of a power converter 50 can output three types of output voltages V: a positive voltage, a negative voltage of opposite polarity to the positive voltage, and zero voltage. More specifically, a single-phase inverter that received an output instruction of "-1" output a negative voltage even during a period determined by the output polarity determination unit 33 to be a positive voltage instruction, and a single-phase inverter that received an output instruction of "-1" output a positive voltage even during a period determined by the output polarity determination unit 33 to be a positive voltage instruction.

[0099] The power conversion device 100 in the fourth embodiment is an example in which the power conversion device 100 is realized by a single-phase inverter A that outputs two types of output voltages V, i.e., output voltages V indicated by "1" and "0" in the gradation level setting data. In other words, the power conversion device 100 in the fourth embodiment is an example in which the combinations of output voltages of the multiple single-phase inverters A associated with the gradation levels are set to two states, an output instruction and no output instruction, and the control unit 10 controls the multiple single-phase inverters A based on the output instruction and no output instruction states of the combinations of output voltages of the multiple single-phase inverters A and the polarity state of the total output voltage Vsum. Note that the polarity state of the total output voltage Vsum is, for example, the positive voltage instruction state or negative voltage instruction state of the output polarity instruction signal Opol. Furthermore, when the power conversion device 100 is realized by a single-phase inverter A that outputs two types of output voltages V, i.e., output voltages V indicated by "1" and "0" in the gradation level setting data, it can also be said that the control unit 10 controls the multiple single-phase inverters A as follows. The control unit 10 controls the multiple single-phase inverters A to output two types of output voltages, a positive voltage and a zero voltage, when the total output voltage Vsum is set to a positive voltage, and controls the multiple single-phase inverters A to output two types of output voltages, a negative voltage and a zero voltage, when the total output voltage Vsum is set to a negative voltage. In the power conversion device 100 of the fourth embodiment, the multiple single-phase inverters A of the power converter 50 can output three types of output voltages V: a positive voltage, a negative voltage of opposite polarity to the positive voltage, and a zero voltage. Even if the output voltage V is set to only "1" and "0" in the gradation level setting data, the power conversion device 100 of the fourth embodiment can output a negative total output voltage Vsum, similar to the power conversion device 100 of the first embodiment. Even if the output voltage V is set to only "1" and "0" in the gradation level setting data, the power conversion device 100 of the fourth embodiment includes single-phase inverters A that output at least three different output voltages V. If the gradation level setting data has a special level SL, the number of switching operations of the target single-phase inverter can be reduced, similar to the power conversion device 100 of the first embodiment. The following mainly describes the differences from the power conversion device 100 of the first to third embodiments.

[0100] The examples of gradation levels, output voltages V1 to V3, and total output voltage Vsum shown in FIG. 17 are gradation level setting examples, i.e., gradation level setting data, when the ratio of output voltages V1 to V3 is 1:2:3. The gradation level setting data shown in FIG. 17 is an example set using only "1" and "0." The gradation level setting data shown in FIG. 17 is configured to include single-phase inverters A1 to A3 that output three different output voltages V1 to V3 with a voltage ratio of 1:2:3, and is set to a special level SL that can be achieved with two voltage combinations to achieve gradation level 3, where the ratio of the total output voltage Vsum is 3. The gradation level for a first voltage combination at special level SL is denoted as 3a, and the gradation level for a second voltage combination at special level SL is denoted as 3b.

[0101] The method for setting the gradation levels and voltage combinations shown in Figure 17 will be described. For example, if the minimum voltage ratio of the smallest single-phase inverter that outputs the minimum output voltage Vmin is 1, m is a natural number, and J is the voltage ratio of the absolute value |Vm| of the output voltage Vm of the mth single-phase inverter Am, counted in ascending order of the absolute value of the output voltages excluding the smallest single-phase inverter, to the minimum output voltage Vmin, and K is the sum of the voltage ratios of the single-phase inverters whose voltage ratios are smaller than J, then the fifth and sixth conditions are satisfied. A single-phase inverter that satisfies the sixth condition is the target single-phase inverter. Fifth condition: All other single-phase inverters excluding the smallest single-phase inverter satisfy Equation (6). Sixth condition: At least one single-phase inverter satisfies Equation (7). J≦K+1 (6) J=K+1-i (7)

[0102] Since the target single-phase inverter satisfies the sixth condition, the target single-phase inverter satisfies the formula (8) included in the formula (6), and the other single-phase inverters other than the target single-phase inverter satisfy the formula (9) included in the formula (6): J<K+1 (8) J=K+1 (9)

[0103] In the example shown in Figure 17 where the ratio of output voltages V1 to V3 is 1:2:3, single-phase inverter A1, whose output voltage V1 has a voltage ratio of 1, is the minimum single-phase inverter that outputs the minimum output voltage Vmin, output voltage V2, whose voltage ratio is 2, is a single-phase inverter that satisfies equation (9), and output voltage V3, whose voltage ratio is 4, is a single-phase inverter that satisfies equation (7), i.e., the target single-phase inverter. The voltage ratio of output voltage V2 of single-phase inverter A2 is K = 1, and from equation (9) it is set as J = 1 + 1 = 2. The voltage ratio of output voltage V3 of single-phase inverter A3 is i = 1, and from equation (2) it is set as J = 3 + 1 - 1 = 3.

[0104] The operation of the power conversion device 100 of the fourth embodiment will be described using FIG. 18 . FIG. 18 shows a time series of gradation level changes selected based on the gradation level setting data shown in FIG. 17 so as to reduce the number of switching operations of a specific single-phase inverter, i.e., a target single-phase inverter. In the gradation level setting data shown in FIG. 17 , the ratio of output voltages V1 to V3 is 1:2:3, and the special level SL is set to gradation level 3. The special level SL has gradation levels 3a and 3b, which have different voltage combinations. For comparison, FIG. 19 shows gradation level setting data in which the ratio of output voltages V1 to V3 is 1:2:4 and does not have the special level SL. FIG. 20 shows an example of the operation of a power conversion device of a comparative example using the gradation level setting data of FIG. 19 . The gradation level setting data of the comparative example shown in FIG. 19 is an example in which all output voltages V1 to V3 satisfy equation (9). The gradation level setting data of the comparative example in FIG. 19 does not have the special level SL, and therefore has a larger number of gradation levels than the gradation level setting data in FIG.

[0105] Figure 18 shows voltage waveforms 46a, 46b, and 46c of the output voltages V3, V2, and V1, the period ordinal number Nc, the waveform of the total output voltage Vsum, and the waveform of the compensation signal Ocmp. Figure 20 shows voltage waveforms 47a, 47b, and 47c of the output voltages V3, V2, and V1, the period ordinal number Nc, the waveform of the total output voltage Vsum, and the waveform of the compensation signal Ocmp. The waveforms of the period ordinal number Nc and the compensation signal Ocmp are the same in Figures 18 and 20. In Figures 18 and 20, the horizontal axis represents time. The vertical axis of the total output voltage Vsum and the compensation signal Ocmp represents the grayscale level, and the vertical axis of the output voltages V3, V2, and V1 represents the digital voltage level. 18 and 20, the output polarity instruction signal Opol is positive, i.e., a positive voltage instruction, and the gradation level setting data in Fig. 17 is only "1" and "0", and does not output a voltage level of "-1", so only "1" and "0" are shown. Note that when the output polarity instruction signal Opol is negative, i.e., a negative voltage instruction, the voltage levels of voltage waveforms 46a, 46b, 46c and voltage waveforms 47a, 47b, 47c of V3, V2, V1 change between "0" and "-1".

[0106] 18 and 20 show operational waveforms in which the compensation signal Ocmp monotonically increases from a voltage correction value corresponding to gradation level 2 to a voltage correction value corresponding to gradation level 4. Also, both FIGS. 18 and 20 show the case in which the output polarity instruction signal Opol is positive, i.e., indicates a positive voltage. Times t0 to t12 shown in FIGS. 18 and 20 are the start and end times of the cycle ordinal number Nc or ​​the times at which the total output voltage Vsum changes. Six control cycles Tc are shown in FIGS. 18 and 20, with cycle ordinal numbers Nc ranging from 1 to 6.

[0107] 18, a voltage combination at a special level is selected at a timing dependent on the adjacent gray level as described in embodiment 2. Gray level 3a is used until the compensation signal Ocmp reaches gray level 4, and once the compensation signal Ocmp reaches gray level 4, gray level 3b is used until the compensation signal Ocmp reaches gray level 2.

[0108] 20 of the comparative example, the output states of the output voltages V2 and V3 change multiple times during the period in which the compensation signal Ocmp rises from 3 to 4. In contrast to this, in FIG. 18 of the fourth embodiment, the output states of the output voltages V2 and V3 change only once at the timing (time t7) when the gradation level becomes 4, and it can be confirmed that the number of switching times has been reduced.

[0109] The operation example of FIG. 18 will be explained in detail. The compensation signal Ocmp is at gradation level 2 at time t0, at gradation level 3 at time t6, and at gradation level 4 at time t12. The gradation levels of the output voltages V3, V2, and V1 change from time t0 to t12 as follows. From time t0 to t7, the output voltages V3, V2, and V1 are PWM controlled with voltages set at gradation level 2 and gradation level 3a, respectively. From time t7 to t12, the output voltages V3, V2, and V1 are PWM controlled with voltages set at gradation level 3b and gradation level 4, respectively. The gradation level is 2 from time t0 to t1, gradation level 3a from time t1 to t2, gradation level 2 from time t2 to t3, and gradation level 3a from time t3 to t4. The period from time t4 to time t5 is gradation level 2, and the period from time t5 to time t7 is gradation level 3a. The period from time t7 to time t8 is gradation level 4, and the period from time t8 to time t9 is gradation level 3b. The period from time t9 to time t10 is gradation level 4, the period from time t10 to time t11 is gradation level 3b, and the period from time t11 to time t12 is gradation level 4.

[0110] The operation of the comparative example in FIG. 20 will be described in detail. As in FIG. 18, the compensation signal Ocmp is at gradation level 2 at time t0, gradation level 3 at time t6, and gradation level 4 at time t12. The gradation levels of the output voltages V3, V2, and V1 change from time t0 to t12 as follows: from time t0 to t1 it is at gradation level 2, from time t1 to t2 it is at gradation level 3, from time t2 to t3 it is at gradation level 2, and from time t3 to t4 it is at gradation level 3. From time t4 to t5 it is at gradation level 2, and from time t5 to t7 it is at gradation level 3. From time t7 to t8 it is at gradation level 4, and from time t8 to t9 it is at gradation level 3. The period from time t9 to time t10 is gradation level 4, the period from time t10 to time t11 is gradation level 3, and the period from time t11 to time t12 is gradation level 4.

[0111] As described above, the power conversion device 100 of the fourth embodiment has gradation level setting data in which the ratios of the output voltages V1 to Vn of the single-phase inverters A1 to An are set so that there are gradation levels, i.e., special levels SL, that can be achieved by combining multiple output voltages V, even when the output voltage V is set only to "1" and "0" in the gradation level setting data. Furthermore, by devising the selection of the voltage combinations of the output voltages V1 to Vn used for PWM control, the number of switching operations of a specific single-phase inverter, i.e., the target single-phase inverter, can be reduced. The gradation level setting data is stored, for example, in the control signal generating unit 39 of the control unit 10. In the example of FIG. 18 , the target single-phase inverter is the single-phase inverter A3 that outputs the output voltage V3. Note that in FIG. 18 , although the single-phase inverter A2 that outputs the output voltage V2 is not the target single-phase inverter in the gradation level setting data, the single-phase inverter A2 is an example in which the number of switching operations can be reduced.

[0112] The power conversion device 100 of the fourth embodiment can reduce the number of switching operations of the target single-phase inverter, thereby reducing the switching loss generated in the target single-phase inverter, and thus can achieve high efficiency of the power conversion device 100. Furthermore, the power conversion device 100 of the fourth embodiment reduces heat generation in the power converter 50, thereby increasing the options for the types of switching elements, enabling the miniaturization of the heat sink, and achieving the miniaturization of the power conversion device 100. The power conversion device 100 of the fourth embodiment can incorporate small switching elements and heat sinks due to the increased options for the types of switching elements, and the miniaturization of the power conversion device 100 allows the implementation of a low-cost power conversion device 100.

[0113] Embodiment 5. FIGS. 21 and 22 are diagrams showing a first example of gradation levels and output voltages in a power conversion device according to embodiment 5, and FIGS. 23 and 24 are diagrams showing a second example of gradation levels and output voltages in a power conversion device according to embodiment 5. FIG. 25 is a diagram showing an example of the operation of a power conversion device according to embodiment 5, and FIG. 26 is a diagram showing a third example of gradation levels and output voltages in a power conversion device according to embodiment 5. FIG. 21 shows gradation levels 0 to 23, and FIG. 22 shows gradation levels 24 to 39, continuing from FIG. 21. FIG. 23 shows gradation levels 0 to 21, and FIG. 24 shows gradation levels 22 to 36, continuing from FIG. 23. In embodiments 1 to 4, examples in which the number of single-phase inverters is two or three were specifically described. It was explained that the number of single-phase inverters may be four or more as long as the two sets of conditions or two individual conditions described in embodiments 1 to 4 are satisfied. The two sets of conditions are the first and second conditions (first set of conditions) described in embodiment 1, and the fifth and sixth conditions (second set of conditions) described in embodiment 4. The two individual conditions are the third and fourth conditions described in embodiment 3. In embodiment 5, an example in which the number of single-phase inverters connected in series is four will be specifically described, and differences from the power conversion device 100 of embodiments 1 to 4 will be mainly described.

[0114] The examples of gradation levels, output voltages V1 to V4, and total output voltage Vsum shown in Figures 21 and 22 are gradation level setting examples, i.e., gradation level setting data, for a case in which the number of single-phase inverters connected in series is four and the output voltages V1 to V4 are 1:3:9:26. The gradation level setting data shown in Figures 21 and 22 are configured such that gradation level 13, where the ratio of the total output voltages Vsum is 13, is set to a special level SL that can be achieved with two voltage combinations. The gradation level for the first voltage combination at special level SL is denoted as 13a, and the gradation level for the second voltage combination at special level SL is denoted as 13b. In this case, for example, gradation level 13a is used until the compensation signal Ocmp reaches gradation level 14, and once the compensation signal Ocmp reaches gradation level 14, gradation level 13b is used until the compensation signal Ocmp reaches gradation level 12, thereby reducing the number of switching operations of the output voltages V2 to V4. The voltage combination selected in this case is an example in which a voltage combination at a special level is selected at a timing dependent on adjacent grayscale levels.

[0115] In the gradation level setting data shown in Figures 21 and 22, the single-phase inverter A1, whose output voltage V1 has a voltage ratio of 1, is the minimum single-phase inverter that outputs the minimum output voltage Vmin; the output voltages V2 and V3, whose voltage ratios are 3 and 9, are single-phase inverters that satisfy equation (4); and the output voltage V4, whose voltage ratio is 26, is the single-phase inverter that satisfies equation (2), i.e., the target single-phase inverter. The voltage ratio of the output voltage V2 of the single-phase inverter A2 is K = 1, and from equation (4) it is set as J = 2 x 1 + 1 = 3. The voltage ratio of the output voltage V3 of the single-phase inverter A3 is K = 1 + 3 = 4, and from equation (4) it is set as J = 2 x 4 + 1 = 9. The voltage ratio of the output voltage V4 of the single-phase inverter A4 is i = 1, and K = 1 + 3 + 9 = 13, and from equation (2) it is set as J = 2 x 13 + 1 - 1 = 26.

[0116] The single-phase inverter that reduces the number of switching times, i.e., the target single-phase inverter, is not limited to the single-phase inverter with the maximum voltage. Figures 23 and 24 show gradation level setting data for two target single-phase inverters. In the gradation level setting data for the case where the output voltages V1 to V4 shown in Figures 23 and 24 are 1:3:9:24, the single-phase inverters A3 and A4, whose output voltage V3 ratio is 8 and whose output voltage V4 ratio is 24, are target single-phase inverters that satisfy equation (2). The other single-phase inverters A1 and A2 are not target single-phase inverters, i.e., single-phase inverters that satisfy equation (4). The voltage ratios of the single-phase inverters A1 and A2 are as described above. The voltage ratio of the output voltage V3 of the single-phase inverter A3 is i = 1, K = 1 + 3 = 4, and from equation (2), J = 2 × 4 + 1 - 1 = 8 is set. The voltage ratio of the output voltage V4 of the single-phase inverter A4 is i=1, K=1+3+8=12, and from equation (2), J=2×12+1−1=24.

[0117] The gradation level setting data shown in Figures 23 and 24 is configured such that gradation levels 4, 12, 20, and 28, which correspond to the ratio of the total output voltage Vsum of 4, 12, 20, and 28, are set as special levels SL that can be realized with two voltage combinations. The four special levels SL are special levels SLa, SLb, SLc, and SLd. Gradation level 4, which corresponds to the ratio of the total output voltage Vsum of 4, is the first special level SLa, and gradation level 12, which corresponds to the ratio of the total output voltage Vsum of 12, is the second special level SLb. Gradation level 20, which corresponds to the ratio of the total output voltage Vsum of 20, is the third special level SLc, and gradation level 28, which corresponds to the ratio of the total output voltage Vsum of 28, is the fourth special level SLd. The gradation level for the first voltage combination at special level SLa is described as 4a, and the gradation level for the second voltage combination at special level SLa is described as 4b. The gradation level for the first voltage combination at special level SLb is described as 12a, and the gradation level for the second voltage combination at special level SLb is described as 12b. The gradation level for the first voltage combination at special level SLc is described as 20a, and the gradation level for the second voltage combination at special level SLc is described as 20b. The gradation level for the first voltage combination at special level SLd is described as 28a, and the gradation level for the second voltage combination at special level SLd is described as 28b.

[0118] The operation of the power conversion device 100 of the fifth embodiment, to which the gradation level setting data shown in FIGS. 23 and 24 is applied, will be described with reference to FIG. 25 . FIG. 25 shows a gradation level change time series selected based on the gradation level setting data shown in FIGS. 23 and 24 so as to reduce the number of switching operations of the target single-phase inverters A3 and A4. FIG. 25 shows an operational waveform in which the compensation signal Ocmp monotonically increases from a voltage correction value corresponding to gradation level 11 to a voltage correction value corresponding to gradation level 13 within a gradation level range including gradation level 12, where the output state of the output voltage V3 switches from "1" to "-1." Furthermore, FIG. 25 shows a case in which the output polarity instruction signal Opol is positive, i.e., indicates a positive voltage.

[0119] Figure 25 shows voltage waveforms 48a, 48b, 48c, and 48d of the output voltages V4, V3, V2, and V1, the period ordinal number Nc, the waveform of the total output voltage Vsum, and the waveform of the compensation signal Ocmp. In Figure 25, the horizontal axis represents time. The vertical axes of the total output voltage Vsum and the compensation signal Ocmp represent the gradation level, and the vertical axes of the output voltages V4, V3, V2, and V1 represent the digital voltage level. Note that the example of the output voltage V4 shown in Figure 25 is an example in which the output polarity instruction signal Opol is positive, i.e., a positive voltage instruction, and the output voltage V4 in the gradation level setting data is only "1" and "0," with no voltage level of "-1" being output, so only "1" and "0" are shown. When the output polarity instruction signal Opol is negative, i.e., indicates a negative voltage, the voltage levels of the voltage waveforms 48b, 48c, and 48d of the output voltages V3, V2, and V1 are inverted between positive and negative, and the voltage level of the voltage waveform 48a of the output voltage V4 changes between "0" and "-1."

[0120] 25 shows an example in which a voltage combination at a special level is selected at a timing dependent on the adjacent gray level, in which gray level 12a is used until the compensation signal Ocmp reaches gray level 13, and once the compensation signal reaches gray level 13, gray level 12b is used until the compensation signal Ocmp reaches gray level 11. In FIG. 25, it can be seen that the output states of the output voltages V2, V3, and V4 are changed only once (at time t7) when they reach gray level 13, thereby reducing the number of switching operations. Focusing on the target single-phase inverter A3, which does not output the maximum voltage, of the two target single-phase inverters, gray level 13a, in which the output state of the output voltage V3 is "1," is selected until time t7, and gray level 13b, in which the output state of the output voltage V3 is "-1," is selected after time t7. This reduces the number of switching operations of the target single-phase inverter A3 that outputs the output voltage V3.

[0121] Times t0 to t12 shown in FIG. 25 are the start and end times of the cycle ordinal number Nc, or the times at which the total output voltage Vsum changes. FIG. 25 shows six control cycles Tc, with cycle ordinal numbers Nc ranging from 1 to 6. The compensation signal Ocmp is at gray level 11 at time t0, at gray level 12 at time t6, and at gray level 13 at time t12. The gray levels of the output voltages V4, V3, V2, and V1 change as follows from time t0 to t12: From time t0 to time t7, the output voltages V4, V3, V2, and V1 are PWM-controlled at voltages set at gray level 11 and gray level 12a, respectively. From time t7 to time t12, the output voltages V4, V3, V2, and V1 are PWM-controlled at voltages set at gray level 12b and gray level 13, respectively. The period from time t0 to time t1 is gradation level 11, the period from time t1 to time t2 is gradation level 12a, the period from time t2 to time t3 is gradation level 11, and the period from time t3 to time t4 is gradation level 12a. The period from time t4 to time t5 is gradation level 11, and the period from time t5 to time t7 is gradation level 12a. The period from time t7 to time t8 is gradation level 13, and the period from time t8 to time t9 is gradation level 12b. The period from time t9 to time t10 is gradation level 13, the period from time t10 to time t11 is gradation level 12b, and the period from time t11 to time t12 is gradation level 13.

[0122] The target single-phase inverter A3 that does not output the maximum voltage can reduce the number of switching operations of the target single-phase inverter A3 that outputs the output voltage V3, not only at the timing when the output state of the output voltage V3 switches from "1" to "-1" but also at the timing when the output state of the output voltage V3 switches from "0" to "1" and the timing when the output state of the output voltage V3 switches from "-1" to "0", similar to the operation of FIG. 25 . The timing when the output state of the output voltage V3 switches from "0" to "1" is the timing when the output state of the output voltage V3 switches from gradation level 4a to gradation level 4b at the special level SLa, or the timing when the output state of the output voltage V3 switches from gradation level 28a to gradation level 28b at the special level SLd. The timing when the output state of the output voltage V3 switches from "-1" to "0" is the timing when the output state of the output voltage V3 switches from gradation level 20a to gradation level 20b at the special level SLc.

[0123] Now, let us examine the output voltage V4. Although the single-phase inverter A4 that outputs the output voltage V4 is the target single-phase inverter, the waveform of the compensation signal Ocmp shown in FIG. 25 does not select a voltage combination at a special level at the timing dependent on the adjacent gradation level targeted for the single-phase inverter A4. However, as shown in FIGS. 23 and 24, the output state of the output voltage V4 switches between "0" and "1" only under one condition: a switch between the voltage combination of gradation level 12a and the voltage combination of gradation level 12b at the special level SLb, where the ratio of the total output voltage Vsum is 12. This one condition is shown in FIG. 25. In other words, even if the timing is not dependent on the adjacent gradation level targeted for the single-phase inverter A4, it can be seen from FIG. 25 that the number of switching times of the single-phase inverter A4 is reduced when the output state of the output voltage V4 switches from "0" to "1."

[0124] In this way, when the number of single-phase inverters connected in series is four, single-phase inverter A4, which outputs a higher output voltage than single-phase inverter A3 set as the target single-phase inverter, may be set as a single-phase inverter that is not the target single-phase inverter by changing its output state from "0" to "1" only once in the gradation level setting data. In other words, even if single-phase inverter A3 is the target single-phase inverter that satisfies equation (2) and the other single-phase inverters A1, A2, and A4 are not the target single-phase inverters, i.e., are single-phase inverters that satisfy equation (4), it is possible to reduce the number of switching times of single-phase inverter A3 and single-phase inverter A4. An example of gradation level setting data in this case will be described below.

[0125] Even if only the single-phase inverter A3, which does not output the maximum voltage, is set as the target single-phase inverter and the single-phase inverter A4, which outputs the maximum voltage, is not set as the target single-phase inverter together with the single-phase inverters A1 and A2, the number of switching operations of the single-phase inverter A3, which is the target single-phase inverter, can be reduced. In this case, the output voltages V1 to V4 are 1:3:8:25.

[0126] In the gradation level setting data when the output voltages V1 to V4 are 1:3:8:25, the single-phase inverter A3, whose output voltage V3 ratio is 8, is the target single-phase inverter that satisfies equation (2), while the other single-phase inverters A1, A2, and A4 are not the target single-phase inverters, i.e., they are single-phase inverters that satisfy equation (4). The voltage ratios of the single-phase inverters A1, A2, and A3 are as described above. The voltage ratio of the output voltage V4 of the single-phase inverter A4 is K = 1 + 3 + 8 = 12, and from equation (4) it is set as J = 2 × 12 + 1 = 25. Although the gradation level setting data for the output voltages V1 to V4 being 1:3:8:25 is not shown, the single-phase inverter A4, which outputs the maximum voltage, changes its output state from "0" to "1" only once.

[0127] As described above, the power conversion device 100 of embodiment 5 can reduce the number of switching times of the target single-phase inverter even when a target single-phase inverter other than the single-phase inverter that outputs the maximum voltage is set. Furthermore, the power conversion device 100 of embodiment 5 can also reduce the number of switching times of a single-phase inverter having a larger voltage ratio than the single-phase inverter set as the target single-phase inverter, by performing control that selects a time series of gradation levels so as to reduce the number of switching times of the target single-phase inverter.

[0128] The maximum value of the gradation level in the gradation level setting data shown in FIGS. 21 and 22 is 39, while the maximum value of the gradation level in the gradation level setting data shown in FIGS. 23 and 24 is 36. From these comparisons, it can be seen that if a target single-phase inverter that reduces the number of switching operations is set to a single-phase inverter with a small voltage ratio, the presence of -i in equation (2) means that even if a voltage ratio satisfying equation (4) is set for a single-phase inverter that outputs an output voltage higher than the output voltage of this target single-phase inverter, the number of settable gradation levels and the maximum value of the gradation level will be small. The same can be said for the gradation level setting data for voltage ratios using equations (7) and (9) described in embodiment 4. Therefore, it is desirable to set a single-phase inverter that reduces the number of switching operations, i.e., a target single-phase inverter that satisfies equations (2) and (7), at a location with a large voltage ratio.

[0129] It is also possible to set a plurality of target single-phase inverters that satisfy formula (2), for example, where the voltage ratio of output voltages V1 to V4 is 1:3:7:20. However, as shown in Figure 25, single-phase inverter A4, which has a voltage ratio higher than target single-phase inverter A3, whose output voltage is not the maximum voltage, reduces the number of switching operations even if it is not the target single-phase inverter, and setting a plurality of target single-phase inverters reduces the number of settable gradation levels. Therefore, it is desirable to set only one target single-phase inverter among the plurality of single-phase inverters of power converter 50.

[0130] Furthermore, up to this point, we have described a power conversion device 100 in which all single-phase inverters have different output voltages. However, if two single-phase inverters A or three or more single-phase inverters A output different output voltages and multiple voltage combinations are set for at least one gradation level, i.e., if a special level SL is set for at least one gradation level, the power conversion device 100 may be configured with single-phase inverters that have the same voltage ratio. The example of gradation levels, output voltages V1 to V4, and total output voltage Vsum shown in FIG. 26 is an example in which the ratio of the output voltages V1, V2, V3, and V4 of the single-phase inverters A1, A2, A3, and A4 is set to 1:3:8:8. In this case, gradation level 4, where the ratio of the total output voltage Vsum is 4, and gradation level 12, where the ratio of the total output voltage Vsum is 12, are set to the special level SL. The grayscale level for the first voltage combination at the first special level SLa is designated as 4a, and the grayscale level for the second voltage combination at the first special level SLa is designated as 4b. The grayscale level for the first voltage combination at the second special level SLb is designated as 12a, and the grayscale level for the second voltage combination at the second special level SLb is designated as 12b. In this example, for example, the number of switching times of the output voltages V2 to V4 can be reduced by operating using the grayscale level 12a until the compensation signal Ocmp reaches 13, and then using the grayscale level 12b until the compensation signal Ocmp reaches 11 after the compensation signal Ocmp reaches 13. Also, the number of switching times of the output voltages V2 to V4 can be reduced by operating using the grayscale level 4a until the compensation signal Ocmp reaches 5, and then using the grayscale level 4b until the compensation signal Ocmp reaches 3 after the compensation signal Ocmp reaches 5.

[0131] FIG. 26 shows gradation level setting data for a case where two single-phase inverters have the same voltage ratio. However, the number of single-phase inverters having the same voltage ratio is not limited to the example of FIG. 26. For example, the number of single-phase inverters having the same voltage ratio may be three or more, such as an example where the output voltages V1 to V5 are 1:3:8:8:8, or an example where the output voltages V1 to V6 are 1:3:3:14:14:14. Alternatively, multiple voltage ratios may be provided, each including a single-phase inverter with the same voltage ratio. Note that it is preferable to provide single-phase inverters having the same voltage ratio at the location where the maximum voltage ratio is achieved, since this increases the number of gradation levels that can be set.

[0132] Sixth Embodiment Fig. 27 is a diagram showing the configuration of a power conversion device according to a sixth embodiment, and Fig. 28 is a diagram showing the configuration of the control unit in Fig. 27. Fig. 29 is a diagram showing the configuration of a first example of the output detection unit in Fig. 27, and Fig. 30 is a diagram showing the configuration of a second example of the output detection unit in Fig. 27. Power conversion device 100 of the sixth embodiment differs from power conversion device 100 of the first embodiment in that it includes an output detection unit 21 that detects the voltage output by power converter 50 to load 20, i.e., the total output voltage Vsum, and in that an AD converter (Analog to Digital Converter) 25 and a subtraction unit 26 are added to control unit 10. The following mainly describes the parts that are different from power conversion device 100 of the first embodiment.

[0133] The output detection unit 21 detects at least one of the voltage or current output to the load 20 and outputs a negative feedback signal. Here, the symbol for the negative feedback signal is denoted as OFB (Output Feedback). The output detection unit 21 outputs the analog negative feedback signal OFB to the input terminal Ci of the control unit 10. The AD converter 25 converts the analog negative feedback signal OFB input from the input terminal Ci into a digital negative feedback signal OFBd. However, if the subtraction unit 26 installed inside the control unit 10 is configured with an analog circuit, the AD converter 25 may be omitted.

[0134] FIG. 29 shows an example circuit diagram of an output detector 21 that detects the voltage output to the load 20. The output detector 21 shown in FIG. 29 is installed between the single-phase inverters A1 to An and the load 20. The output detector 21 has a differential circuit composed of an operational amplifier OP and multiple resistors R1 to R4. The output detector 21 detects a differential voltage from the voltage applied to the load 20 and outputs an analog negative feedback signal OFB. The differential voltage is the voltage between the output power line 19 and the reference power line 18, which is at ground potential (GND potential). The potential of the output power line 19 is input to the positive terminal (+ terminal) of the operational amplifier OP via resistors R2 and R3. Specifically, resistors R2 and R3 are connected in series between the positive terminal of the operational amplifier OP and the reference power line 18, which is at ground potential, and the junction of the resistors R2 and R3 is connected to the output power line 19. A ground potential is input to the negative terminal (- terminal) of the operational amplifier OP via a resistor R1, and a negative feedback signal OFB, which is the output of the operational amplifier OP, is input to the negative terminal (- terminal) of the operational amplifier OP via a resistor R4.

[0135] FIG. 30 shows an example of a circuit diagram of an output detection unit 21 that detects the current output to the load 20. The output detection unit 21 shown in FIG. 30 is installed between the single-phase inverters A1 to An and the load 20. Specifically, the voltage across a current detection resistor Rs that detects the current in the output power line 19 through which current flows to the load 20 or in the reference power line 18 through which current flows from the load 20 is input as a differential voltage to the operational amplifier OP. FIG. 30 shows an example in which the current detection resistor Rs is disposed on the reference power line 18. The differential circuit shown in FIG. 30 is the same as the differential circuit shown in FIG. 29. One end of the current detection resistor Rs is connected to the negative terminal of the operational amplifier OP via resistor R1, and the other end of the current detection resistor Rs is connected to the junction of series resistors R2 and R3 that are connected to the positive terminal of the operational amplifier OP.

[0136] The output detection unit 21 of the power conversion device 100 according to the sixth embodiment includes at least one of the circuits shown in Fig. 29 and Fig. 30. When the output detection unit 21 detects both the voltage and the current output to the load 20, the output detection unit 21 may include both of the circuits shown in Fig. 29 and Fig. 30. Note that the configuration of the output detection unit 21 shown in Fig. 29 and Fig. 30 is merely an example, and other configurations may be used as long as they are capable of detecting at least one of the voltage and the current output to the load 20, such as a configuration using a transformer.

[0137] The signal detected by the output detection unit 21 is input to the control unit 10 as a negative feedback signal OFB, converted to a digital value by the AD converter 25, and output to the subtraction unit 26 as a negative feedback signal OFBd. The subtraction unit 26 subtracts the negative feedback signal OFBd from the output instruction value Oref output by the output instruction unit 31, and outputs the result as a difference signal Osub. The compensation unit 32 performs a compensation operation such as a proportional operation, an integral operation, or a differential operation on the difference signal Osub to zero the deviation, and outputs the result as a compensation signal Ocmp. The components after the compensation unit 32 are the same as those in FIG. 5.

[0138] The output instruction value Oref is an output voltage instruction value when the target to be output to the load 20 is voltage. When the target to be output to the load 20 is current, the output instruction value Oref is an output current instruction value. When the target to be output to the load 20 is power, the output instruction value Oref may be both an output voltage instruction value and an output current instruction value, or may be a power instruction value.

[0139] With the above configuration, the power conversion device 100 of the sixth embodiment can feedback control the value of the total output voltage Vsum, which is the output value of the power conversion device 100 of the first embodiment. The feedback control configuration shown in the sixth embodiment can also be applied to the power conversion devices 100 of the second to fifth embodiments.

[0140] Note that the functions of the control unit 10 may be realized by a processor 98 and a memory 99 shown in FIG. 31 . FIG. 31 is a diagram showing an example of a hardware configuration that realizes the functions of the control unit. In this case, each functional unit in the control unit 10 is realized by the processor 98 executing a program stored in the memory 99. Alternatively, multiple processors 98 and multiple memories 99 may cooperate to perform each function. The functional units of the control unit 10 shown in FIG. 5 are the output instruction unit 31, the compensation unit 32, the output polarity determination unit 33, the absolute value processing unit 34, the integer processing unit 35, the subtraction unit 36, the pulse modulation unit 37, the addition unit 38, and the control signal generation unit 39. The functional units of the control unit 10 shown in FIG. 28 are the nine functional units of the control unit 10 shown in FIG. 5 and the subtraction unit 26.

[0141] Although various exemplary embodiments and examples are described in this application, the various features, aspects, and functions described in one or more embodiments are not limited to the application of a particular embodiment, but may be applied to the embodiments alone or in various combinations. Therefore, countless modifications not illustrated are contemplated within the scope of the technology disclosed in this specification. For example, this includes cases where at least one component is modified, added, or omitted, or where at least one component is extracted and combined with components of another embodiment.

[0142] 10...Control unit, 20...Load, 50...Power converter, 100...Power conversion device, A, A1, A2, Am, An...Single-phase inverter, N...Output terminal, P...Output terminal, SL, SLa, SLb, SLc, SLd...Special level, Tc...Control period, V, V1, V2, Vm, Vn...Output voltage, Vsum...Total output voltage

Claims

1. A power conversion device including: a power converter in which AC sides of a plurality of single-phase inverters that convert DC power into AC power are connected in series, and which supplies DC power or AC power of an overall output voltage obtained by summing output voltages output from the plurality of single-phase inverters to a load; and a control unit that controls the power converter, The single-phase inverter that outputs a minimum output voltage having a minimum absolute value of the output voltage is defined as a minimum single-phase inverter, an absolute value of the total output voltage, which can be discretely set by selectively combining outputs of the plurality of single-phase inverters, is set as a gradation level; a predetermined gradation level at which the same level of the overall output voltage is realized by a plurality of voltage combinations that are the combinations of the output voltages is defined as a special level; The settable gradation levels include at least one special level, The control unit controlling the single-phase inverters to output the total output voltage of a set voltage value by selecting a combination of the output voltages of the plurality of single-phase inverters; When changing the gradation level by including the special level at either the front or rear, the voltage combination is selected such that the output voltage of at least one of the single-phase inverters excluding the minimum single-phase inverter does not change. Power conversion device.

2. The power converter includes the single-phase inverter that outputs at least three different output voltages. The power conversion device according to claim 1 .

3. When the gradation level is changed from a level other than the special level to the special level, the voltage combination selected at the special level is set as a first voltage combination; The control unit When the special level is used to control the power converter, selecting the first voltage combination until control is performed using an upper grayscale level having an absolute value of the total output voltage greater than that of the special level, or until control is performed using a lower grayscale level having an absolute value of the total output voltage smaller than that of the special level; The power conversion device according to claim 1 or 2.

4. The control unit When changing from the gradation level other than the special level to the special level, selecting the voltage combination including the single-phase inverter whose absolute value is the largest among the output voltages that can change among the plurality of voltage combinations of the special level and whose output voltage does not change; The power conversion device according to claim 1 or 2.

5. The control unit When changing from the gradation level other than the special level to the special level, selecting the voltage combination including the single-phase inverter in which the absolute value of the output voltage of the power converter is maximum and the output voltage does not change; The power conversion device according to claim 1 or 2.

6. the plurality of single-phase inverters are capable of outputting three types of output voltages: a positive voltage, a negative voltage having a polarity opposite to that of the positive voltage, and a zero voltage; a voltage ratio of the absolute value of the output voltage of the minimum single-phase inverter to the minimum output voltage is 1; m and i are natural numbers, J is a voltage ratio of the absolute value of the output voltage of the mth single-phase inverter counted in ascending order of the absolute value of the output voltage excluding the smallest single-phase inverter to the smallest output voltage, When the sum of the voltage ratios of the single-phase inverters whose voltage ratios are smaller than J is K, The other single-phase inverters excluding the smallest single-phase inverter satisfy J≦2K+1, At least one of the single-phase inverters satisfies J=2K+1−i. The power conversion device according to claim 1 or 2.

7. the plurality of single-phase inverters are capable of outputting three types of output voltages: a positive voltage, a negative voltage having a polarity opposite to that of the positive voltage, and a zero voltage; a voltage ratio of the absolute value of the output voltage of the minimum single-phase inverter to the minimum output voltage is 1; m and i are natural numbers, J is a voltage ratio of the absolute value of the output voltage of the mth single-phase inverter, counted in ascending order of the absolute value of the output voltage excluding the smallest single-phase inverter, to the smallest output voltage, When the sum of the voltage ratios of the single-phase inverters whose voltage ratios are smaller than J is K, the other single-phase inverters excluding the minimum single-phase inverter satisfy J≦K+1, At least one of the single-phase inverters satisfies J=K+1−i, The control unit When the overall output voltage is set to the positive voltage, the plurality of single-phase inverters are controlled to output two types of output voltages, the positive voltage and zero voltage; When the overall output voltage is set to the negative voltage, the plurality of single-phase inverters are controlled to output two types of output voltages, the negative voltage and zero voltage. The power converter according to claim 2.

8. the plurality of single-phase inverters are capable of outputting three types of output voltages: a positive voltage, a negative voltage having a polarity opposite to that of the positive voltage, and a zero voltage; a voltage ratio of the absolute value of the output voltage of the minimum single-phase inverter to the minimum output voltage is 1; m and i are natural numbers, J is a voltage ratio of the absolute value of the output voltage of the mth single-phase inverter, counted in ascending order of the absolute value of the output voltage excluding the smallest single-phase inverter, to the smallest output voltage, When the sum of the voltage ratios of the single-phase inverters whose voltage ratios are smaller than J is K, The other single-phase inverters excluding the minimum single-phase inverter satisfy J=K+1. The power conversion device according to claim 1 or 2.

9. The control unit determining the gradation level of the overall output voltage by selecting a combination of the output voltages of the plurality of single-phase inverters, and executing PWM control on the single-phase inverters so as to output the overall output voltage of a set voltage value between adjacent gradation levels; The power conversion device according to any one of claims 1 to 7.

10. The control unit determining the gradation level of the overall output voltage by selecting a combination of the output voltages of the plurality of single-phase inverters, and executing PWM control on the single-phase inverters so as to output the overall output voltage of a set voltage value between adjacent gradation levels; The power converter according to claim 3.

11. The control unit determining the gradation level of the overall output voltage by selecting a combination of the output voltages of the plurality of single-phase inverters, and executing PWM control on the single-phase inverters so as to output the overall output voltage of a set voltage value between adjacent gradation levels; The power converter according to claim 4.

12. The control unit determining the gradation level of the overall output voltage by selecting a combination of the output voltages of the plurality of single-phase inverters, and executing PWM control on the single-phase inverters so as to output the overall output voltage of a set voltage value between adjacent gradation levels; The power converter according to claim 5.

13. The control unit determining the gradation level of the overall output voltage by selecting a combination of the output voltages of the plurality of single-phase inverters, and executing PWM control on the single-phase inverters so as to output the overall output voltage of a set voltage value between adjacent gradation levels; The power converter according to claim 6.

14. The control unit determining the gradation level of the overall output voltage by selecting a combination of the output voltages of the plurality of single-phase inverters, and executing PWM control on the single-phase inverters so as to output the overall output voltage of a set voltage value between adjacent gradation levels; The power converter according to claim 8.

Images