Memory device using semiconductor element

Abstract

Provided is a memory semiconductor device including: an n-type semiconductor layer formed on a p-type semiconductor region on a substrate; a first p-type semiconductor layer, of which a columnar surface is concave in a vertical direction from a part of the n-type semiconductor layer; an insulating layer partly covering the first p-type semiconductor layer and the n-type semiconductor layer; a first gate insulating layer in contact with the insulating layer and in contact with the first p-type semiconductor layer; a first gate conductor layer in contact with the first gate insulating layer; and an access transistor, provided along the surface of the first p-type semiconductor layer, and equipped with a second gate insulating layer, a second gate conductor layer, and n + layers on both sides thereof.

Description

[Technical Field]

[0001] The present invention relates to a memory device using a semiconductor element. [Background technology]

[0002] In recent years, in the development of LSI (Large Scale Integration) technology, there has been a demand for memory devices using semiconductor elements to have higher integration, higher performance, lower power consumption, and higher functionality.

[0003] In a typical planar MOS transistor, the channel extends horizontally along the upper surface of the semiconductor substrate. In contrast, the channel of an SGT extends perpendicularly to the upper surface of the semiconductor substrate (see, for example, Patent Document 1 and Non-Patent Document 1). Therefore, compared to planar MOS transistors, SGTs enable higher density semiconductor devices. By using SGTs as select transistors, high integration can be achieved in a variety of devices, including DRAMs (Dynamic Random Access Memory, see, for example, Non-Patent Document 2) connected to a capacitor, PCMs (Phase Change Memory, see, for example, Non-Patent Document 3) connected to a resistance change element, RRAMs (Resistive Random Access Memory, see, for example, Non-Patent Document 4), and MRAMs (Magneto-Resistive Random Access Memory, see, for example, Non-Patent Document 5), which change resistance by changing the direction of magnetic spins using current.

[0004] There are also DRAM memory cells (see Non-Patent Documents 6 to 10) that do not have a capacitor and are composed of a single MOS transistor. For example, a source-drain current in an N-channel MOS transistor generates holes and electrons in the channel by impact ionization, and some or all of the holes are retained in the channel to write logical data "1." Then, the holes are removed from the channel to write logical data "0." The challenges for this memory cell are to improve the reduction in operating margin due to fluctuations in the floating body channel voltage, and to improve the degradation of data retention characteristics caused by the removal of some of the holes, which are signal charges accumulated in the channel.

[0005] There is also a twin-transistor MOS transistor memory element in which one memory cell is formed using two MOS transistors in an SOI layer (see, for example, Patent Documents 2 and 3, and Non-Patent Document 11). Furthermore, there is a dynamic flash memory (DFM) in which one memory cell is composed of two gate electrodes without a capacitor (see Non-Patent Document 12). In this memory cell, the carrier concentration in the floating body is changed by manipulating the voltages of the four electrodes, creating a conductive or non-conductive state to enable memory operation. Furthermore, a structure in which a body that accumulates carriers is connected to the bottom of the MOS transistor has also been proposed (see Patent Document 4), and there is a demand for higher integration and higher performance in this memory. This application relates to a memory device using semiconductor elements that can be composed only of MOS transistors without a resistance change element or capacitor. [Prior art documents] [Patent documents]

[0006] [Patent Document 1] Japanese Patent Application Publication No. 2-188966 [Patent Document 2] US2008 / 0137394 A1 [Patent Document 3] US2003 / 0111681 A1

Patent document 4

Non-licensed literature

[0007]

Non-licensed literature 1

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[0008] The object of the present invention is to provide a memory element that has a MOS transistor that writes and reads data and a MOS structure connected to the substrate of this MOS transistor, and that stores signal charges that become memory data "1" and "0", with high precision, high integration, and low cost.

[0009] In order to solve the above problems, a memory device using a semiconductor element according to the first aspect of the present invention comprises: a first semiconductor region; a first impurity region on the first semiconductor region; a second semiconductor region that is in contact with the first impurity region and extends in a vertical direction, and has a concave surface vertical cross section; a first gate insulating layer covering a portion of the second semiconductor region; a first gate conductor layer in contact with the first gate insulating layer; a second gate insulating layer having a concave vertical cross section formed along at least the concave portion of the second semiconductor region; a second gate conductor layer formed inside the recess of the second gate insulating layer; The above 2 a second impurity region and a third impurity region formed so as to be in contact with the upper surface of the protruding portion of the recessed portion of the semiconductor region, an upper surface of the second gate conductor layer is located lower than upper surfaces of the second impurity region and the third impurity region; It is characterized by:

[0010] A second invention is characterized in that in the first invention, the second impurity region and the third impurity region are in contact with a second gate insulating layer.

[0011] The third invention is characterized in that, in the above-mentioned first invention, either or both of the contact surface between the second semiconductor region and the second impurity region and the contact surface between the second semiconductor region and the third impurity region are located at a position higher than the bottom of the second gate insulating layer.

[0012] A fourth invention is characterized in that in the first invention, there is a portion in the horizontal direction between the second impurity region and the third impurity region where only the insulating layer exists.

[0013] A fifth invention is characterized in that in the first invention, the minimum distance between the second impurity region and the third impurity region is longer than the horizontal length of a vertical cross section of the second gate conductor layer.

[0014] A sixth aspect of the present invention is characterized in that in the first aspect of the present invention, majority carriers in the first impurity region are different from majority carriers in the first semiconductor region.

[0015] A seventh invention is characterized in that in the first invention, majority carriers in the second semiconductor region are the same as majority carriers in the first semiconductor region.

[0016] An eighth invention is characterized in that in the first invention, majority carriers in the second impurity region and the third impurity region are the same as majority carriers in the first impurity region.

[0017] A ninth invention is characterized in that in the first invention, the first impurity region is shared by a plurality of adjacent memory cells.

[0018] A tenth aspect of the present invention is characterized in that in the first aspect, the second impurity region or the third impurity region is shared by a plurality of adjacent memory cells.

[0019] An eleventh aspect of the present invention is the first aspect of the present invention, wherein an upper surface of the first impurity region is located at a position perpendicular to the first gate insulating layer. Bottom surface It is characterized by being located at a higher position.

[0020] A twelfth invention is characterized in that, in the first invention, the lower surfaces of the second impurity region and the third impurity region are located higher in the vertical direction than the upper surface of the first gate conductor layer.

[0021] The thirteenth invention is characterized in that, in the first invention, the threshold value of a MOS transistor consisting of the second semiconductor region, the second impurity region, the third impurity region, the second gate insulating layer, and the second gate conductor layer is changed by changing the voltage applied to the first gate conductor layer.

[0022] No. 14 The invention is the first invention described above, a first wiring conductor layer connected to the second impurity region; a second wiring conductor layer connected to the third impurity region; a third wiring conductor layer connected to the second gate conductor layer; a fourth wiring conductor layer connected to the first gate conductor layer; a fifth wiring conductor layer connected to the first impurity region; voltages applied to the first wiring conductor layer, the second wiring conductor layer, the third wiring conductor layer, the fourth wiring conductor layer, and the fifth wiring conductor layer are controlled to 2 The impurity region and the 3a memory write operation is performed by performing an operation of generating electron groups and holes in the second semiconductor region by an impact ionization phenomenon or a gate-induced drain leakage current using a current flowing between the second semiconductor region and the impurity region, an operation of removing minority carriers in the second semiconductor region from the generated electron groups and hole groups, and an operation of leaving some or all of the majority carriers in the second semiconductor region in the second semiconductor region, The memory erase operation is performed by controlling the voltages applied to the first wiring conductor layer, the second wiring conductor layer, the third wiring conductor layer, the fourth wiring conductor layer, and the fifth wiring conductor layer, and removing the remaining majority carriers in the second semiconductor region or the third semiconductor region from at least one of the first impurity region, the second impurity region, and the third impurity region by recombining them with the majority carriers in the first impurity region, the second impurity region, and the third impurity region.

[0023] The fifteenth aspect of the present invention is the above-mentioned fourteenth aspect of the present invention, 2 The first wiring conductor layer connected to the impurity region is a source line, 3 the second wiring conductor layer connected to the impurity region is a bit line, the third wiring conductor layer connected to the second gate conductor layer is a word line, the fourth wiring conductor layer connected to the first gate conductor layer is a plate line, and the fifth wiring conductor layer is a control line, and the memory write operation and the memory erase operation are performed by applying voltages to the source line, bit line, plate line, word line, and control line, respectively. [Brief explanation of the drawings]

[0024] [Figure 1] 1 is a diagram showing a cross-sectional structure of a memory device using a semiconductor element according to a first embodiment. [Figure 2] 4A and 4B are diagrams for explaining the accumulation of hole carriers and the cell current during a write operation of the memory device using the semiconductor element according to the first embodiment. [Figure 3]4A to 4C are diagrams illustrating an erase operation of the memory device using the semiconductor element according to the first embodiment. [Figure 4A] 10A to 10C are diagrams illustrating a method for manufacturing a memory device according to a second embodiment. [Figure 4B] 10A to 10C are diagrams illustrating a method for manufacturing a memory device according to a second embodiment. [Figure 4C] 10A to 10C are diagrams illustrating a method for manufacturing a memory device according to a second embodiment. [Figure 4D] 10A to 10C are diagrams illustrating a method for manufacturing a memory device according to a second embodiment. [Figure 4E] 10A to 10C are diagrams illustrating a method for manufacturing a memory device according to a second embodiment. [Figure 4F] 10A to 10C are diagrams illustrating a method for manufacturing a memory device according to a second embodiment. [Figure 4G] 10A to 10C are diagrams illustrating a method for manufacturing a memory device according to a second embodiment. [Figure 4H] 10A to 10C are diagrams illustrating a method for manufacturing a memory device according to a second embodiment. [Figure 4I] 10A to 10C are diagrams illustrating a method for manufacturing a memory device according to a second embodiment. [Figure 4J] 10A to 10C are diagrams illustrating a method for manufacturing a memory device according to a second embodiment. [Figure 4K] 10A to 10C are diagrams illustrating a method for manufacturing a memory device according to a second embodiment. [Figure 4L] 10A to 10C are diagrams illustrating a method for manufacturing a memory device according to a second embodiment. [Figure 4M] 10A to 10C are diagrams illustrating a method for manufacturing a memory device according to a second embodiment. [Figure 4N] 10A to 10C are diagrams illustrating a method for manufacturing a memory device according to a second embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0025] Hereinafter, the structure, driving method, and behavior of stored carriers of a memory device using semiconductor elements according to an embodiment of the present invention will be described with reference to the drawings.

[0026] (First embodiment) The cell structure and operation of a memory using a semiconductor element according to a first embodiment of the present invention will be described with reference to Figures 1 to 3. The cell structure of a memory using a semiconductor element according to a first embodiment of the present invention will be described with reference to Figure 1. The write mechanism of a memory cell and the behavior of carriers will be described with reference to Figure 2. The erase mechanism of a memory cell and the behavior of carriers will be described with reference to Figure 3.

[0027] FIG. 1 shows a vertical cross-sectional structure of a memory using a semiconductor device according to a first embodiment of the present invention. A p-layer 1 (an example of a "first semiconductor region" in the claims) is made of silicon and has p-type conductivity, containing acceptor impurities. Adjacent to the p-layer 1 is an n-layer 3 (an example of a "first impurity region" in the claims) containing donor impurities. Adjacent to a portion of the n-layer 3 is a columnar p-layer 4 (an example of a "second semiconductor region" in the claims) containing acceptor impurities, with a rectangular horizontal cross section and a concave upper surface. A first gate insulating layer 11 (an example of a "first gate insulating layer" in the claims) covers the p-layer 1, the n-layer 3, and portions of the p-layer 4. A first gate conductor layer 21 (an example of a "first gate conductor layer" in the claims) is also in contact with the first gate insulating layer 11.

[0028] An n+ layer 5a (an example of the "second impurity region" in the claims) containing donor impurities and an n+ layer 5b (an example of the "third impurity region" in the claims) are in contact with the upper surfaces of both left and right ends of the p-layer 4 (hereinafter, the semiconductor region containing donor impurities at a high concentration will be referred to as the "n+ layer").

[0029] A second gate insulating layer 13 (an example of a "second gate insulating layer" in the claims) also has a concave upper portion, located along the upper surface of the concave portion of the p-layer 4 and along parts of the n+ layers 5a and 5b. This gate insulating layer 13 is in contact with the n+ layers 5a and 5b, respectively. A second gate conductor layer 22 (an example of a "second gate conductor layer" in the claims) is located inside the concave upper portion of the gate insulating layer 13. The upper surface of this gate conductor layer 22 is located lower than the upper surface of the n+ layer 5a or n+ layer 5b. This is to ensure that if an inversion layer is formed in the MOSFET having the gate conductor layer 22 and the gate insulating layer 13, it will be connected to the n+ layer 5a or n+ layer 5b.

[0030] 1, the top of the gate conductor layer 22 is covered with an insulating layer 15, but hereinafter the gate insulating layer 13 and the insulating layer 15 may be collectively referred to as the gate insulating layer 13. Also, in FIG. 1, the top of the gate conductor layer 22 is covered with an insulating layer 15 for electrical isolation from the wiring above it.

[0031] Furthermore, n+ layer 5b is connected to a source line SL (an example of a "source line" in the claims) which is a first wiring conductive layer, n+ layer 5a is connected to a bit line BL (an example of a "bit line" in the claims) which is a second wiring conductive layer, gate conductor layer 22 is connected to a word line WL (an example of a "word line" in the claims) which is a third wiring conductive layer, gate conductor layer 21 is connected to a plate line PL (an example of a "plate line" in the claims) which is a fourth wiring conductive layer, and n layer 3 is connected to a control line CDC (an example of a "control line" in the claims) which is a fifth wiring conductive layer. The source line SL, bit line BL, plate line PL The memory is operated by controlling the voltages applied to the word line WL and the control line CDC.

[0032] 1, the recess shapes in the vertical cross section of the p-layer 4 are shown as straight lines, but they may be partially U-shaped or semi-elliptical, with curved corners or vertical cross sections. Accordingly, the surface of the p-layer 4 becomes a curved surface. Furthermore, the bottom surfaces of the second gate insulating layer 13 and the second gate conductor layer 22, which are formed along this curved surface, may also have curved surfaces.

[0033] In addition, in FIG. 1, the memory cell has been described as having a rectangular vertical cross section of the p-layer 4 relative to the paper surface, but it may be trapezoidal, polygonal, circular, or elliptical.

[0034] 1, n+ layer 5a connected to the source line and n+ layer 5b connected to the bit line BL are in contact with each other on the top surface of p layer 4, but they may also be in contact with each other on the side surface of p layer 4. They may also be in contact with each other on both the top surface and the side surface.

[0035] In addition, in FIG. 1, the first semiconductor region 1 is a p-type semiconductor, but the memory can also operate by using an n-type semiconductor substrate as another semiconductor substrate, forming a p-well, and using this as the first semiconductor region 1 to arrange the memory cell of the present invention.

[0036] Furthermore, in the direction perpendicular to the substrate, the top of the n-layer 3 should be at the same level as or higher than the bottom of the gate conductor layer 21. When erasing memory information, it is important that the n-layer 3 is electrically connected to an inversion layer formed at the interface between the p-layer 4 and the gate insulating layer 11 when a positive voltage is applied to the gate conductor layer 21. Also, in FIG. 1, as long as the n-layer 3 is present below the memory cell, it may be present over the entire memory cell region in a plan view, or may be present in only a part of the memory cell region. Furthermore, the n-layer 3 may be formed by an n-well in the p-layer 1.

[0037] 1, the gate insulating layer 11 is described as being integrated with the bottom and inner side surfaces of the gate conductor layer 21, but the insulating layer may be formed separately for the portion in contact with the bottom of the gate conductor layer 21 and for the portion in contact with the inner side surfaces. In this case, the thickness of the gate insulating layer 11 may vary depending on the portion.

[0038] 1, p-layer 4 is a p-type semiconductor, but the optimum impurity concentration of p-layer 4 is determined by the amount of excess holes stored in the memory, which is determined by parameters such as the volume of p-layer 4, the thickness of first gate insulating layer 11, the material of first gate conductor layer 21, and the applied voltage. Furthermore, p-layer 4 may have a profile, and depending on the material and thickness of gate insulating layer 13 and the material of gate conductor layer 22, any of p-type, n-type, or i-type can be used near the surface of p-layer 4.

[0039] Any material, whether an insulator, semiconductor, or conductor, can be used to support the p-layer 1 below the p-layer 1. The present invention can also be applied to a case where memory components such as the substrate 1, p-layer 4, and gate conductor layers 21 and 22 are first formed by extending them horizontally on a separate support substrate.

[0040] There may also be a profile in the impurity concentration of n layer 3. In addition, in the direction in which n+ layers 5a and 5b are connected to p layer 4, an LDD (Lightly Doped Drain) region having a donor concentration lower than the donor impurity concentration of n+ layers 5a and 5b may be provided between p layer 4 and n+ layers 5a and 5b.

[0041] Furthermore, the first to fifth wiring conductive layers may be formed in multiple layers as long as they do not contact each other.

[0042] Furthermore, the gate insulating layers 11 and 13 may be made of any insulating film used in a normal MOS process, such as an SiO2 film, a SiON film, an HfSiON film, or a stacked film of SiO2 / SiN.

[0043] Furthermore, as long as the first gate conductor layer 21 can change the potential of part of the memory cell via the gate insulating layer 11, and the second gate conductor layer 22 can change the potential of part of the memory cell via the gate insulating layer 13, they may be made of metals such as W, Pd, Ru, Al, TiN, TaN, and WN, metal nitrides, or alloys thereof (including silicides), such as a stacked structure such as TiN / W / TaN, or may be made of a highly doped semiconductor.

[0044] 1, the first gate conductor layer 21 may surround the entire p-layer 4 via the insulating layer 11 in a plan view, or may cover only a portion of the p-layer 4. The first gate conductor layer 21 may be divided into multiple pieces in a plan view. The first gate conductor layer 21 may also be divided into multiple pieces in the vertical direction. In addition, in the cross-sectional structure of FIG. 1, the first gate conductor layer 21 is present on both sides of the p-layer 4, but the memory of the present invention can operate if it is present on either side.

[0045] Furthermore, when n+ layer 5a and n+ layer 5b are formed from a semiconductor region p+ layer containing a high concentration of acceptor impurities in which holes are the majority carriers, the memory of the present invention can operate with electrons as the write carriers by using n-type semiconductors for p layers 1 and 4 and p-type semiconductors for n layer 3.

[0046] In an actual memory device according to the first embodiment of the present invention, one or a plurality of the above-described memory cells are arranged two-dimensionally on the p-layer 1.

[0047] Referring to Figure 2, the carrier behavior, storage, and cell current during a write operation of the memory according to the first embodiment of the present invention will be described. First, the majority carriers in n layer 3, n+ layer 5a, and n+ layer 5b are electrons. For example, polysilicon containing a high concentration of donor impurities (hereinafter, polysilicon containing a high concentration of donor impurities will be referred to as "n+poly") is used for gate conductor layer 21 connected to plate line PL and gate conductor layer 22 connected to word line WL, and a p-type semiconductor is used for second semiconductor region 4. As shown in Figure 2(a), the MOSFET in this memory cell operates using n+ layer 5a as the source, n+ layer 5b as the drain, gate insulating layer 13, gate conductor layer 22 as the gate, and p layer 4 as the substrate. For example, 0 V is applied to the p-layer 1, 0.5 V is applied to the n-layer 3 connected to the control line (CDC), 0 V is input to the n+ layer 5b connected to the source line SL, 1.0 V is input to the n+ layer 5a connected to the bit line BL, and −1 V is applied to the gate conductor layer 21 connected to the plate line PL. Here, the threshold voltage of the MOSFET using the gate conductor layer 22 as the gate electrode before writing is set to 1.0 V when the voltage of the plate line PL is −1 V. Next, if 1.5 V is input to the gate conductor layer 22 connected to the word line WL, a partial inversion layer 62 is formed directly below the gate insulating layer 13 below the gate conductor layer 22, and a pinch-off point 63 is present. In this case, the MOSFET having the gate conductor layer 22 operates in the saturation region.

[0048] As a result, the electric field becomes maximum between pinch-off point 63 and n+ layer 5a in the MOSFET having gate conductor layer 22, and impact ionization occurs in this region. Due to this impact ionization, electrons accelerated from n+ layer 5b connected to source line SL toward n+ layer 5a connected to bit line BL collide with the Si lattice, and their kinetic energy generates electron-hole pairs. The generated holes diffuse toward areas with lower hole concentration due to their concentration gradient. As a result, holes 64 are accumulated in p layer 4.

[0049] In the above example, the plate line PL is set to -1V, which prevents the depletion layer from expanding into the p-layer 4, allowing holes generated by impact ionization to accumulate, and also contributes to adjusting the threshold voltage of the MOSFET in the memory cell through the substrate bias effect.

[0050] In the above example, an n+poly is used for the gate conductor layer 21 and a negative voltage is biased. However, by using a material having a higher work function than the n+poly for the gate conductor layer 21, it is possible to achieve the same effect as applying a negative voltage without applying a voltage.

[0051] As shown in FIG. 1, the width of the p-layer 4 is made wider than the width of the second gate conductor layer 22 in a plan view to increase the amount of excess holes stored.

[0052] Instead of causing the impact ionization phenomenon, a gate-induced drain leakage (GIDL) current may be passed to generate a group of holes (see, for example, Non-Patent Document 7).

[0053] Figure 2(b) shows a group of holes 64 in the p-layer 4 immediately after writing, when the plate line PL is at -1V, the word line WL, source line SL, and bit line BL are biased at 0V, and the control line CDC is biased at 0.5V. The generated group of holes 64 move uniformly throughout the p-layer 4 due to diffusion due to differences in carrier concentration. Furthermore, because a negative potential is applied to the first gate conductor layer 21, a higher concentration of holes accumulates near the first gate insulating layer 11 in the p-layer 4. The threshold voltage of the MOSFET with the gate conductor layer 22 is lowered by the positive substrate bias effect due to the holes temporarily accumulated in the p-layer 4. In this example, as shown in Figure 2(c), the threshold voltage of the MOSFET with the gate conductor layer 22 connected to the word line WL is approximately 0.6V, lower than before writing. This write state is assigned to logical storage data "1."

[0054] In addition to the above examples, if the voltages applied to the bit line BL, plate line PL, and word line WL are denoted as V-BL, V-PL, and V-WL, respectively, the voltage application conditions can be 1.0V (V-BL) / -1V (V-PL) / 2.0V (V-WL), 1.0V (V-BL) / -0.5V (V-PL) / 1.2V (V-WL), or 1.5V (V-BL) / -1V (V-PL) / 2.0V (V-WL), with SL set to 0V. The voltage relationships between the bit line BL and source line SL may also be reversed. However, if 1.0V is applied to the bit line BL, 0V to the source line SL, 2V to the word line WL, and -1V to the plate line PL, the threshold voltage will decrease during programming, gradually shifting the pinch-off point 63 toward the n+ layer 5b, and the MOSFET may operate linearly.

[0055] Next, the erase operation mechanism will be explained using Figure 3. Figure 3(a) shows the state before the erase operation, immediately after the hole group 64 generated by impact ionization in the previous cycle has been stored in the p-layer 4. The source line SL, bit line BL, and word line WL are at 0V, the voltage of the control line CDC is 0.5V, and the voltage of the plate line PL is -1V.

[0056] As shown in FIG. 3(b), during an erase operation, the source line SL, bit line BL, and word line WL are set to 0V, and the voltage of the control line CDC is set to 0.5V. The voltage of the plate line PL is set to, for example, 2V. As a result, regardless of the value of the initial potential of the p-layer 4, gate insulation layerAn electron inversion layer 65 is formed at the interface between 11 and the p-layer 4. As a result, holes 64 accumulated in the p-layer 4 flow from the p-layer 4 to the inversion layer 65 and recombine with electrons 66. Electrons lost due to recombination are replenished from the inversion layer 65, which contacts the n-layer 3. As a result of this recombination of holes and electrons, the hole concentration in the p-layer 4 decreases over time, and the threshold voltage of the MOSFET becomes higher than when a "1" was written. For example, if the plate line PL voltage is -1V, the threshold voltage of the MOSFET becomes 1.2V. As a result, as shown in Figure 3(b), the MOSFET with the gate conductor layer 22 connected to this word line WL flows very little current even when a voltage is applied, and is in the erased state. This state is referred to as the logical memory data "0" of the memory.

[0057] According to the structure of the first embodiment of the present invention, in the MOSFET region formed by the p layer 4, the gate conductor layer 22, the gate insulating layer 13, and the n+ layers 5a and 5b, the contact area between the p layer 4 and the gate insulating layer 13 is 1 / 2 times that of the gate conductor layer 22 and the gate insulating layer 13. layer The contact area is larger than the contact area of ​​the p-layer 4. As a result, the dependency of the threshold voltage of the MOSFET on the number of hole carriers in the p-layer 4 becomes larger than that of a planar MOSFET, and the operating margin of the memory is expanded.

[0058] Furthermore, since the vertical cross section of p layer 4 is concave, the effective distance between n+ layer 5a and n+ layer 5b is increased, and the leakage current of the MOSFET when logical storage data is "0" can be reduced.

[0059] As a method of erasing data other than the examples, if the voltages applied to the bit line BL, plate line PL, and word line WL are denoted as V-BL, V-PL, and V-WL, respectively, the voltage application conditions can be combinations such as 0V (V-BL) / 2V (W-PL) / -1V (V-WL), 0.4V (V-BL) / 2V (V-PL) / 0.5V (V-WL), or 1V (V-BL) / 1.5V (V-PL) / 0V (V-WL), with the source line SL at 0V and the control line CDC at 0.5V. However, the voltage conditions applied to the bit line BL, source line SL, word line WL, and plate line PL are only examples for performing a memory erase operation, and other operating conditions that allow a memory erase operation may also be used.

[0060] In addition, although the control line CDC has been described as being 0.5V in both cases of writing and erasing memory, the control line CDC can also be set to the ground voltage, i.e., 0V.

[0061] Furthermore, the bottom surfaces of n+ layers 5a and 5b are separated from the top surface of gate conductor layer 21. This prevents direct contact between n+ layers 5a and 5b and inversion layer 65 formed between p layer 4 and gate insulating layer 11 during erasing of the memory. This makes it difficult for current to flow from n layer 3, which helps to reduce power consumption during erasure.

[0062] Furthermore, according to the first embodiment of the present invention, the memory can be erased even if a positive voltage is applied to the plate line PL during erasure, which has the advantage that information from multiple cells that share the gate conductor layer 22 can be erased at once.

[0063] Furthermore, in FIG. 1, the contact area between the p layer 4 and the n layer 3 is depicted as being equal to the cross-sectional area of ​​the p layer 4. However, as long as the n layer 3 and its inversion layer are in partial contact at the time when the inversion layer 65 is formed during erasure, the contact area between the p layer 4 and the n layer 3 may be smaller than the cross-sectional area of ​​the p layer 4.

[0064] Furthermore, since the memory cell of the present invention is formed in the area of ​​one MOSFET in plan view, by sharing the source line and bit line with adjacent memory cells, a higher density memory cell array than conventional dynamic RAM can be realized.

[0065] The first embodiment of the present invention has the following features.

[0066] (Feature 1) The MOSFET, which is the access transistor of the memory according to the first embodiment of the present invention, can realize a higher density memory cell compared to a normal parallel plate (planar) type by surrounding a part of the second gate conductor layer 22 with the n+ layer 5a, the n+ layer 5b, and the p layer 4 which becomes the channel portion.

[0067] (Feature 2) The MOSFET, which is an access transistor of the memory according to the first embodiment of the present invention, is formed by n+ layer 5a, n+ layer 5b, p layer 4, second gate insulating layer 13, and second gate conductor layer 22. Because the vertical cross section near the surface of p layer 4 is concave, the electric field lines from second gate conductor layer 22 to p layer 4, which is the channel portion of the MOSFET, are dispersed rather than concentrated. As a result, the back-gate bias effect is increased, and the carrier concentration dependency of the threshold voltage of the access transistor becomes greater compared to parallel-plate (planar) type and FIN type MOSFETs, thereby expanding the margin of memory operation.

[0068] (Feature 3) In the first embodiment of the present invention, the vertical cross section of channel p layer 4 of the MOSFET consisting of n+ layers 5a, 5b, p layer 4, gate insulating layer 13, and gate conductor layer 22 has a concave structure, so that the effective distance between n+ layer 5a and n+ layer 5b can be made longer than the width of gate conductor layer 22 in a planar view, and a MOSFET with small leakage current can be realized in the off state of the memory.

[0069] (Feature 4) In the first embodiment of the present invention, as described in Feature 2, it is possible to arrange access transistors with short gate lengths in a plan view, and therefore it is possible to realize a high-density memory arrangement.

[0070] (Feature 5) The p-layer 4, one of the components of the MOSFET in the memory cell according to the first embodiment of the present invention, is connected to the n-layer 3 and p-layer 1. Furthermore, by adjusting the voltage applied to the gate conductor layer 21, the threshold voltage of the MOSFET of the access transistor can be freely set. Furthermore, because the area below the MOSFET is not fully depleted, it is not significantly affected by coupling of the floating body word line to the gate electrode, a drawback of DRAMs that do not have capacitors. In other words, according to the present invention, it is possible to design a memory with a wide operating voltage margin.

[0071] (Feature 6) In the memory according to the first embodiment of the present invention, a plurality of cells are arranged in the n layer 3, and a gate conductor layer 21 By sharing the data, a certain erase operation can be performed on multiple cells in a single operation.

[0072] (Feature 7) In the memory according to the first embodiment of the present invention, the components n+ layer 5a, n+ layer 5b, p layer 4, second gate insulating layer 13, and second gate conductor layer 22 can be formed in the same process as the peripheral CMOS, that is, the source, drain, substrate, gate oxide film, and gate electrode, and therefore it is possible to provide a high-density memory cell array and a structure compatible with the peripheral CMOS circuitry.

[0073] (Second embodiment) 4A to 4N show a method for manufacturing a memory according to the second embodiment, in which (a) is a plan view, (b) is a cross-sectional view taken along line XX' in (a), and (c) is a cross-sectional view taken along line YY'.

[0074] As shown in FIG. 4A, an n-layer 3, a p-layer 4, an insulating layer 5, and a p-layer 1 are formed on a p-type semiconductor substrate. layer14, and a mask material 41 is formed. The p-layer 4 and n-layer 3 may be well layers, or may be formed using epitaxial technology with different impurity species and concentrations. The insulating layer 14 may be a silicon oxide film, and the mask material 41 may be a silicon nitride film, for example.

[0075] Next, as shown in FIG. 4B, the mask material in the area that will become the transistor portion of the memory cell in the future is Using 41 as a mask, the insulating layer 14, p-layer 4, and part of the n-layer 3 are etched by RIE (Reactive Ion Etching). Note that in FIG. 4B, it is sufficient that the bottom of the etched groove is between the top and bottom of the n-layer 3.

[0076] Next, as shown in Figure 4C, oxidation is performed to form a layer on the sidewalls and bottom of the grooves formed above. gate insulation layer Although not shown, an oxide film may be formed on the entire surface by using, for example, an ALD (Atomic Layer Deposition) technique. In this case, an oxide film is also formed around the mask material 41. gate insulation layer 11 is formed.

[0077] 4D, the gate conductor layer 21 is formed by depositing n+poly-Si on the entire surface, for example, by CVD, and then etching back by selective RIE so that the upper surface of the gate conductor layer 21 is lower than the upper surface of the p-layer 4. Note that although an n+poly film is used in this example, other metal films, such as a single layer film of W or a laminated film of TiN / W or silicide / poly, may also be used.

[0078] 4E, an insulating layer 12 is formed on the entire surface by, for example, a CVD method. After that, the insulating layer 12 is polished by a CMP (Chemical Mechanical Polishing) technique until the surface of the mask material 41 is exposed. This may be planarized by etching back using an RIE technique that has a selectivity between the mask material 41 and the insulating layer 12.

[0079] Next, after selectively removing mask material 41, insulating layer 12 is etched to expose the surface of p-layer 4. At this time, a method may be used in which CMP technology is used to planarize mask material 41 and part of insulating layer 12 so as to expose the surface of p-layer 4. Next, insulating layer 15 and mask material 42 are formed on the entire surface, as shown in FIG. 4F.

[0080] Next, as shown in FIG. 4G, using the mask material 42 as a mask, the insulating layer 15 and a portion of the p-layer 4 in the region that will become the gate electrode of the memory cell are etched by RIE. Next, an insulating film 13 is selectively formed on the sidewalls and bottom of the trench formed above by oxidation. Although not shown, an oxide film may be formed overall using, for example, ALD technology. In this case, the insulating film 13 is also formed around the mask material 42.

[0081] Next, as shown in Figure 4H, an n+poly film is formed on the entire surface and then etched back, leaving the n+poly film in the groove, forming the gate. Conductor layer 22. In this case, the gate Conductor layer The surface of 22 must be etched back to a position lower than the surface of the insulating layer 12. In this example, an n+poly film is used, but other metal films, such as a single layer film of W or a laminated film of TiN / W or silicide / poly, may also be used. Conductor layer 22 is also used in all or part of the surrounding CMOS circuits. Conductor layer Used as.

[0082] Next, as shown in Fig. 4I, an insulating layer 15 is formed on the entire surface by, for example, a CVD method. After that, the insulating layer 15 is polished by a CMP technique until the surface of the mask material 42 is exposed. This may be planarized by etching back using an RIE technique that has a selectivity between the mask material 42 and the insulating layer 15.

[0083] Next, as shown in FIG. 4J, the insulating layer 15 and the mask material 42 are polished by CMP until the surface of the p-layer 4 is exposed. Conductive layer 22 On top of this remains the insulating layer 15.

[0084] Next, as shown in Fig. 4K, n+ layer 5a and n+ layer 5b are formed in a self-aligned manner from the surface of exposed p-layer 4. This formation method may be a commonly known method such as ion implantation, introducing impurities in a gas phase, or heat treatment or laser annealing to activate the impurities as carriers.

[0085] Next, as shown in FIG. 4L, a W film 33 is formed over the entire surface and then processed to form the desired wiring structure. As a result, adjacent n+ layers 5a or n+ layers 5b are connected to each other. While a W film is used in this example, other materials that can contact n+ layers 5a / 5b, such as metal films, silicides, polysilicon films, or single-layer or multilayer films, may also be used. Although not shown, an alternative to this wiring method may be to form a conventional insulating layer over the entire surface, open contact holes in n+ layers 5a / 5b, and then wire each layer with a metal layer.

[0086] Next, as shown in Fig. 4M, an insulating layer 55 is formed over the entire surface, and then contact holes 34 are opened for each memory cell. After that, a wiring conductor layer 35 is formed. Although the wiring layer 33 cannot be seen from above, it is shown by a two-dot chain line in Fig. 4M(a) to make the positional relationship easier to understand.

[0087] Next, as shown in FIG. 4N, an insulating layer 56 is formed on the entire surface, and then contact holes 36 are opened for each memory cell. After that, a wiring conductor layer 37 is formed. As a result, the wiring conductor layer 35 is connected to the source line SL. The wiring conductor layer 37 is also connected to the bit line BL.

[0088] In the plan view of FIG. 4N(a), the second wiring conductor layer 37 and the insulating layer 38 are actually disposed above the wiring conductor layer 37. layer Although only 56 is visible, the main lower layer, n+ layer 5a / 5b, gate Conductor layer 22, a metal layer 33, a contact hole 34, and a wiring conductor layer 35 are shown.

[0089] Furthermore, although the grooves in FIGS. 4A to 4N have been described using a rectangular vertical cross section, they may be trapezoidal or circular.

[0090] The n-layer 3 may be formed only in the area where memory cells will be located in the future. Therefore, although the n-layer 3 is shown as being formed over the entire surface of the p-layer 1 in FIG. 4A, the n-layer 3 may be formed only in a selected region on the p-layer 1.

[0091] In addition, the gate insulating layer 11 and the gate insulating layer layer Any insulating film used in a normal MOS process, such as an SiO2 film, a SiON film, an HfSiON film, or a stacked film of SiO2 / SiN, can be used for 13.

[0092] In addition, in this explanation, a method of separately forming the wiring conductor layer 35 and the wiring conductor layer 37 to connect to the BL line has been shown, but it is also possible to form the wiring conductor layers 35, 37 and the contact holes 34, 36 in a single process using a damascene method or the like.

[0093] This embodiment provides the following features: (Feature 1) The memory manufacturing method according to the second embodiment of the present invention can use wafers that are used in normal MOS processes, so no additional costs are added for materials. Furthermore, since it does not require special processes such as selective epitaxial growth as shown in Patent Document 4, it is compatible with normal, generalized MOS processes and is easy to introduce.

[0094] (Feature 2) According to the method for manufacturing a memory according to the second embodiment of the present invention, the n+ layer 5a of the memory cell shown in FIG. 4N, the wiring conductor layers 35 and 37 connected to the bit line BL, and the contact holes 34 and 36 are shared with adjacent cells. Also, the wiring conductor layer 35 and contact hole 34 connected to the source line SL are shared with adjacent cells. Therefore, the present invention can provide a miniaturized memory cell.

[0095] (Feature 3) According to the memory manufacturing method of the second embodiment of the present invention, the contact between the wiring in the memory cell and the n+ layer 5a / 5b is formed in a self-aligned manner, as shown in Figure 4L, which reduces the number of masks. Furthermore, since the lateral length of this contact is determined independently of the processing accuracy of lithography, contacts with minute dimensions can be formed, which contributes to the miniaturization of memories. [Industrial Applicability]

[0096] According to the present invention, it is possible to provide a semiconductor memory device that is denser, faster, and has a wider operating margin than conventional devices. [Explanation of symbols]

[0097] 1. First semiconductor region 3 First impurity layer 4. Second Semiconductor Region 5a, 5b n+ layer 11 First gate insulating layer 12 Insulating layer 13 Second gate insulating layer 15 Insulating layer 21 first gate conductor layer 22 second gate conductor layer 33 Wiring conductor layer 34 contact holes 35 Wiring conductor layer 36 contact holes 37 Wiring conductor layer 41 Mask material 42 Mask material 55 insulating film 56 Insulating film 62 Inversion Layer 63 Pinch-off point 64 hole group 65 Inversion Layer 66 electron group SL Source Line PL plate line WL Word Line BL bit line CDC control line

Claims

1. a first semiconductor region; a first impurity region on the first semiconductor region; a second semiconductor region that is in contact with the first impurity region and extends in a vertical direction, and has a surface that has a concave vertical cross section; a first gate insulating layer covering a portion of the second semiconductor region; a first gate conductor layer in contact with the first gate insulating layer; a second gate insulating layer having a concave vertical cross section formed along at least the concave portion of the second semiconductor region; a second gate conductor layer formed inside the recess of the second gate insulating layer; a second impurity region and a third impurity region formed so as to be in contact with an upper surface of a protruding portion of the recess of the second semiconductor region, an upper surface of the second gate conductor layer is located lower than upper surfaces of the second impurity region and the third impurity region; A memory device using a semiconductor element characterized by:

2. the second impurity region and the third impurity region are in contact with a second gate insulating layer. A memory device using the semiconductor element according to claim 1.

3. 2. A memory device using a semiconductor element as described in claim 1, characterized in that either or both of the contact surface between the second semiconductor region and the second impurity region and the contact surface between the second semiconductor region and the third impurity region are located at a higher position than the bottom of the second gate insulating layer.

4. 2. The memory device using a semiconductor element according to claim 1, wherein there is a portion in the horizontal direction between the second impurity region and the third impurity region where only the insulating layer exists.

5. 2. A memory device using a semiconductor element according to claim 1, wherein the minimum distance between the second impurity region and the third impurity region is longer than the horizontal length of a vertical cross section of the second gate conductor layer.

6. 2. The memory device according to claim 1, wherein majority carriers in said first impurity region are different from majority carriers in said first semiconductor region.

7. 2. The memory device according to claim 1, wherein majority carriers in said second semiconductor region are the same as majority carriers in said first semiconductor region.

8. 2. The memory device according to claim 1, wherein majority carriers in the second impurity region and the third impurity region are the same as majority carriers in the first impurity region.

9. 2. The memory device using a semiconductor element according to claim 1, wherein the first impurity region is shared by a plurality of adjacent memory cells.

10. 2. The memory device using a semiconductor element according to claim 1, wherein the second impurity region or the third impurity region is shared by a plurality of adjacent memory cells.

11. 2. The memory device using a semiconductor element according to claim 1, wherein the upper surface of the first impurity region is located higher than the lower surface of the first gate insulating layer in the vertical direction.

12. 2. A memory device using a semiconductor element according to claim 1, wherein the bottom surfaces of the second impurity region and the third impurity region are located higher than the top surface of the first gate conductor layer in the vertical direction.

13. changing a voltage applied to the first gate conductor layer to change a threshold value of a MOS transistor including the second semiconductor region, the second impurity region, the third impurity region, the second gate insulating layer, and the second gate conductor layer; 2. A memory device using the semiconductor element according to claim 1.

14. a first wiring conductor layer connected to the second impurity region; a second wiring conductor layer connected to the third impurity region; a third wiring conductor layer connected to the second gate conductor layer; a fourth wiring conductor layer connected to the first gate conductor layer; a fifth wiring conductor layer connected to the first impurity region; a memory write operation is performed by controlling voltages applied to the first wiring conductor layer, the second wiring conductor layer, the third wiring conductor layer, the fourth wiring conductor layer, and the fifth wiring conductor layer, and generating electron groups and holes in the second semiconductor region by impact ionization or gate-induced drain leakage current caused by a current flowing between the second impurity region and the third impurity region; removing minority carriers in the second semiconductor region from the generated electron groups and hole groups; and causing a part or all of the majority carriers in the second semiconductor region to remain in the second semiconductor region; Voltages applied to the first wiring conductor layer, the second wiring conductor layer, the third wiring conductor layer, the fourth wiring conductor layer, and the fifth wiring conductor layer are controlled to extract the remaining majority carriers in the second semiconductor region from at least one of the first impurity region, the second impurity region, and the third impurity region by recombining them with the majority carriers in the first impurity region, the second impurity region, and the third impurity region, thereby performing a memory erase operation.

2. A memory device using the semiconductor element according to claim 1.

15. the first wiring conductor layer connected to the second impurity region is a source line, the second wiring conductor layer connected to the third impurity region is a bit line, the third wiring conductor layer connected to the second gate conductor layer is a word line, the fourth wiring conductor layer connected to the first gate conductor layer is a plate line, and the fifth wiring conductor layer is a control line; voltages are applied to the source line, the bit line, the plate line, the word line, and the control line, respectively, to perform the memory write operation and the memory erase operation; A memory device using the semiconductor device according to claim 14.