Coupler, butler matrix circuit, transmission circuit, and transmission device

Abstract

This coupler is a coupling line-type coupler having a multilayer configuration in which a plurality of conductor layers are stacked, the coupler comprising first lines and a second line that are formed in the conductor layers different from one another, the first lines being formed in the plurality of conductor layers having interposed therebetween the conductor layer in which the second line is formed, and the first lines and the second line at least partially overlapping one another in the stacking direction of the conductor layers.

Description

Coupler, Butler matrix circuit, transmitting circuit and transmitting device

[0001] This application claims priority from Japanese Patent Application No. 2023-95946, filed on June 12, 2023, the disclosure of which is incorporated herein by reference in its entirety.

[0002] Patent Document 1 (WO 2008 / 018565) discloses the following high-frequency device: That is, the high-frequency device is a high-frequency device in which a high-frequency circuit including a high-frequency amplifier and an output matching circuit that receives high-frequency power output from the high-frequency amplifier is configured on a multilayer substrate formed by stacking multiple dielectric layers, the output matching circuit having a first transmission line that propagates the high-frequency power from the high-frequency amplifier side to an output terminal side, and at least a portion of the first transmission line is formed by connecting multiple conductor patterns formed across multiple dielectric layers in series in the stacking direction.

[0003] International Publication No. 2008 / 018565

[0004] The coupler disclosed herein is a coupled-line type coupler having a multilayer structure in which multiple conductive layers are stacked, and includes a first line and a second line formed in different conductive layers, the first line being formed in multiple conductive layers sandwiching the conductive layer in which the second line is formed, and the first line and the second line overlap at least partially in the stacking direction of the conductive layers.

[0005] FIG. 1 is an equivalent circuit diagram of a coupler according to an embodiment of the present disclosure. FIG. 2 is a diagram schematically illustrating a configuration of a coupler according to an embodiment of the present disclosure. FIG. 3 is a diagram schematically illustrating a configuration of a coupler according to an embodiment of the present disclosure. FIG. 4 is a diagram schematically illustrating a configuration of a coupler according to an embodiment of the present disclosure. FIG. 5 is a diagram illustrating a simulation result of the pass characteristics of a coupler according to an embodiment of the present disclosure. FIG. 6 is a diagram illustrating a simulation result of the pass characteristics of a coupler according to an embodiment of the present disclosure. FIG. 7 is a diagram illustrating a simulation result of the pass characteristics of a coupler according to an embodiment of the present disclosure. FIG. 8 is a diagram illustrating a simulation result of the phase characteristics of a coupler according to an embodiment of the present disclosure. FIG. 9 is an equivalent circuit diagram of a coupler according to a first modification of an embodiment of the present disclosure. FIG. 10 is a diagram schematically illustrating a configuration of a coupler according to the first modification of an embodiment of the present disclosure. FIG. 11 is a diagram schematically illustrating a configuration of a coupler according to the first modification of an embodiment of the present disclosure. FIG. 12 is a diagram schematically illustrating a configuration of a coupler according to the first modification of an embodiment of the present disclosure. FIG. 13 is a diagram illustrating a simulation result of the phase characteristics of a coupler according to a modified example of an embodiment of the present disclosure. FIG. 14 is a diagram illustrating a simulation result of the amplitude characteristics of a coupler according to a modified example of an embodiment of the present disclosure. FIG. 15 is an equivalent circuit diagram of a coupler according to a second modified example of an embodiment of the present disclosure. FIG. 16 is a diagram schematically illustrating a configuration of a coupler according to the second modified example of an embodiment of the present disclosure. FIG. 17 is a diagram schematically illustrating a configuration of a coupler according to the second modified example of an embodiment of the present disclosure. FIG. 18 is a diagram schematically illustrating a configuration of a coupler according to the second modified example of an embodiment of the present disclosure. FIG. 19 is an equivalent circuit diagram of a coupler according to a third modified example of an embodiment of the present disclosure. FIG. 20 is a diagram schematically illustrating a configuration of a coupler according to the third modified example of an embodiment of the present disclosure. FIG. 21 is a diagram schematically illustrating a configuration of a coupler according to the third modified example of an embodiment of the present disclosure. FIG. 22 is a diagram schematically illustrating a configuration of a coupler according to the third modified example of an embodiment of the present disclosure. FIG. 23 is a diagram illustrating a configuration of a transceiver device according to an embodiment of the present disclosure. FIG. 24 is a diagram illustrating an example of the beam direction of an RF signal transmitted by a transmission / reception device according to an embodiment of the present disclosure.

[0006] Conventionally, techniques have been developed to reduce the size of components such as couplers.

[0007] [Problem to be Solved by the Present Disclosure] In electronic components such as Butler matrix circuits and Doherty amplifiers, branch-line hybrid couplers are often used as couplers that equally distribute signals. However, branch-line hybrid couplers tend to be large in component size.

[0008] The present disclosure has been made to solve the above-mentioned problems, and its purpose is to provide a coupler, a Butler matrix circuit, a transmitting circuit, and a transmitting device that can achieve miniaturization of electronic components that include a coupler.

[0009] Effect of the Present Disclosure According to the present disclosure, it is possible to achieve miniaturization of an electronic component including a coupler.

[0010] [Description of Embodiments of the Present Disclosure] First, the contents of the embodiments of the present disclosure will be listed and described.

[0011] (1) A coupler according to an embodiment of the present disclosure is a coupled-line type coupler having a multilayer structure in which multiple conductor layers are stacked, and includes a first line and a second line formed in different conductor layers, the first line being formed in multiple conductor layers sandwiching the conductor layer in which the second line is formed, and the first line and the second line at least partially overlap in the stacking direction of the conductor layers.

[0012] In this way, in a coupled-line coupler that is smaller than a branch-line coupler, by forming the first line on multiple conductor layers sandwiching a conductor layer on which the second line is formed, even when it is difficult to process the first line and the second line close to each other within the same conductor layer, the multilayer structure can be utilized to increase the degree of coupling compared to conventional coupled-line couplers, thereby realizing a coupler that is highly coupled and compact, thereby enabling the miniaturization of electronic components that include couplers.

[0013] (2) In the above (1), the first line may have a first end connected to an input port of the coupler and a second end connected to an output port of the coupler, and the second line may have a first end connected to a coupled port of the coupler and a second end connected to an isolated port of the coupler.

[0014] With this configuration, it is possible to reduce the amplitude error compared to a configuration in which the second line is connected to the input port and the output port and the first line is connected to the coupled port and the isolated port.

[0015] (3) In the above (1) or (2), the first line may be further formed on the conductive layer on which the second line is formed.

[0016] With this configuration, the degree of coupling of the coupler can be further increased.

[0017] (4) A Butler matrix circuit according to an embodiment of the present disclosure includes a plurality of coupled-line couplers formed on the same substrate and having a multilayer structure in which a plurality of conductive layers are stacked, the couplers including first and second lines formed on different conductive layers, the first line formed across the plurality of conductive layers sandwiching the conductive layer on which the second line is formed, the first and second lines at least partially overlapping in the stacking direction of the conductive layers, the couplers including an input port, an output port, a coupled port, and an isolated port, the coupled port of a first coupler being connected to the input port of a third coupler, the coupled port of a second coupler being connected to the isolated port of the third coupler, the output port of the first coupler being connected to the input port of a fourth coupler, and the output port of the second coupler being connected to the isolated port of the fourth coupler.

[0018] In this way, by using a configuration including a plurality of coupled-line couplers in which the first lines are formed on a plurality of conductor layers sandwiching a conductor layer on which the second lines are formed, a Butler matrix circuit can be configured using highly coupled and compact couplers, thereby realizing a compact Butler matrix circuit that can distribute input signals equally with higher precision, thereby enabling miniaturization of electronic components including couplers.

[0019] (5) In the above (4), the first line and the second line may intersect in the stacking direction of the conductor layers.

[0020] This configuration makes it easier to route the wiring patterns for connecting the couplers, which allows for further miniaturization.

[0021] (6) A transmission circuit according to an embodiment of the present disclosure is a transmission circuit used to transmit signals in a frequency band of 20 GHz or higher, and includes the Butler matrix circuit of (4) or (5) above and a plurality of amplifiers mounted on the substrate, wherein the plurality of amplifiers include a first amplifier that amplifies a signal output from the coupled port of the third coupler, a second amplifier that amplifies a signal output from the output port of the third coupler, a third amplifier that amplifies a signal output from the coupled port of the fourth coupler, and a fourth amplifier that amplifies a signal output from the output port of the fourth coupler.

[0022] With this configuration, high frequency signals can be equally divided with higher precision, amplified and transmitted.

[0023] (7) A transmission circuit according to an embodiment of the present disclosure is a transmission device used for beamforming, and includes the transmission circuit of (6) above and a plurality of antennas, the plurality of antennas including a first antenna that transmits a signal amplified by the first amplifier, a second antenna that transmits a signal amplified by the second amplifier, a third antenna that transmits a signal amplified by the third amplifier, and a fourth antenna that transmits a signal amplified by the fourth amplifier.

[0024] With this configuration, it is possible to perform beamforming of high frequency signals with higher accuracy.

[0025] Hereinafter, embodiments of the present disclosure will be described with reference to the drawings. In the drawings, identical or corresponding parts are designated by the same reference numerals, and their description will not be repeated. Furthermore, at least some of the embodiments described below may be combined in any manner.

[0026] <Coupler> Fig. 1 is an equivalent circuit diagram of a coupler according to an embodiment of the present disclosure. Referring to Fig. 1, a coupler 101 includes main lines 1A and 1B, which are main lines 1, a sub-line 2, an input port P1, an output port P2, a coupled port P3, and an isolated port P4. The input port P1, the output port P2, the coupled port P3, and the isolated port P4 may be, for example, terminals or nodes on a substrate. The main line 1 is an example of a first line. The sub-line 2 is an example of a second line.

[0027] The main lines 1A and 1B have first ends connected to an input port P1 and second ends connected to an output port P2. The sub-line 2 has a first end connected to a coupled port P3 and a second end connected to an isolated port P4. For example, the main line 1 is a line that is DC-connected to a transmission line of a main signal in an electronic component including a coupler 101. That is, a main signal transmitted in the electronic component is input to the coupler 101 via the input port P1.

[0028] The coupler 101 is a hybrid coupler. More specifically, the coupler 101 receives an input signal S1 from the outside via an input port P1, outputs an output signal S2a via an output port P2, and outputs an output signal S2b via a coupled port P3. At this time, the phase of the output signal S2a is −90° with respect to the phase of the output signal S2b.

[0029] 2 to 4 are diagrams schematically illustrating the configuration of a coupler according to an embodiment of the present disclosure. FIG. 2 is a plan view of coupler 101. FIG. 3 is a cross-sectional view taken along line III-III in FIG. 2. FIG. 4 is a plan view illustrating the layer configuration of coupler 101. The solid line in FIG. 2 indicates a main line 1A. The dashed line in FIG. 2 indicates a sub-line 2.

[0030] 2 to 4, the coupler 101 is a coupled-line type coupler having a multilayer structure in which a plurality of conductor layers Lc are stacked. More specifically, the coupler 101 includes conductor layers Lc1, Lc2, Lc3, and Lc4 that are the conductor layers Lc, and dielectric layers Ld1, Ld2, and Ld3.

[0031] The conductor layers Lc1, Lc2, Lc3, and Lc4 are stacked in this order with the dielectric layers Ld1, Ld2, and Ld3 interposed therebetween. More specifically, the conductor layer Lc4 is formed on a first of the two main surfaces of the dielectric layer Ld3. The conductor layer Lc3 is formed on a second of the two main surfaces of the dielectric layer Ld3. The conductor layer Lc2 is formed on one of the two main surfaces of the dielectric layer Ld2 formed on the conductor layer Lc3, on the surface opposite the surface on the conductor layer Lc3 side. The conductor layer Lc1 is formed on one of the two main surfaces of the dielectric layer Ld1 formed on the conductor layer Lc2, on the surface opposite the surface on the conductor layer Lc2 side.

[0032] For example, the thickness of the dielectric layers Ld1 and Ld2 is 100 μm, and the thickness of the dielectric layer Ld3 is 200 μm. Furthermore, for example, the relative dielectric constant of the dielectric layers Ld1, Ld2, and Ld3 is 3.2. Furthermore, for example, the dielectric loss tangent of the dielectric layers Ld1, Ld2, and Ld3 is 0.004.

[0033] A ground pattern GND is formed on the conductor layer Lc4. The ground pattern GND is, for example, a thin copper foil conductor formed in a solid shape on the main surface of the dielectric layer Ld3. Note that a resin having the same thickness as the ground pattern GND may be provided in the area of ​​the conductor layer Lc4 where the ground pattern GND is not formed, or a resin that covers the ground pattern GND and thereby protects the first main surface of the coupler 101 may be provided.

[0034] The main line 1 and the sub-line 2 are formed on different conductor layers Lc. More specifically, the sub-line 2 is formed on the conductor layer Lc2, while the main lines 1A and 1B are formed on the conductor layers Lc1 and Lc3, respectively, sandwiching the conductor layer Lc2. A dielectric resin Rs2 is provided in the area of ​​the conductor layer Lc2 where the sub-line 2 is not formed. The resin Rs2 functions as an adhesive that bonds the dielectric layers Ld1 and Ld2 together. A dielectric resin Rs3 is provided in the area of ​​the conductor layer Lc3 where the main line 1B is not formed. The resin Rs3 functions as an adhesive that bonds the dielectric layers Ld2 and Ld3 together. Note that a resin with the same thickness as the main line 1A may be provided in the area of ​​the conductor layer Lc1 where the main line 1A is not formed, or a resin that covers the main line 1A to protect the second main surface of the coupler 101 may be provided.

[0035] For example, the main line 1 and the sub-line 2, together with the ground pattern GND, form a microstrip line. The width W1 of the main line 1 is smaller than the width W2 of the sub-line 2. As an example, to adjust the impedance of the lines, the width W1 is 200 μm and the width W2 is 320 μm. For example, the characteristic impedance of the line consisting of the main lines 1A and 1B and the characteristic impedance of the sub-line 2 is 50 Ω.

[0036] The main line 1A includes a linear coupling portion 11A, a wiring portion 12A extending from a first end of the coupling portion 11A, and a wiring portion 13A extending from a second end of the coupling portion 11A. The main line 1B includes a linear coupling portion 11B, a wiring portion 12B extending from a first end of the coupling portion 11B, and a wiring portion 13B extending from a second end of the coupling portion 11B. The sub-line 2 includes a linear coupling portion 21, a wiring portion 22 extending from the first end of the coupling portion 21, and a wiring portion 23 extending from the second end of the coupling portion 21. For example, the longitudinal directions of the coupling portions 11A, 11B, and 21 are parallel to one another. Furthermore, for example, the length L1 of the coupling portions 11A, 11B, and 21 is λ / 4, where λ is the wavelength of the input signal S1.

[0037] The main lines 1A and 1B are electrically connected via vias V1 and V2. More specifically, the wiring portions 12A and 12B of the main lines 1A and 1B are connected via via V1. The wiring portions 13A and 13B of the main lines 1A and 1B are connected via via V2.

[0038] The main line 1 and the sub-line 2 at least partially overlap in the stacking direction of the conductor layers Lc. More specifically, coupling portions 11A and 11B in the main lines 1A and 1B overlap with coupling portion 21 in a plan view. That is, when coupling portions 11A, 11B, and 21 are projected onto a plane perpendicular to the stacking direction of the conductor layers Lc, the projected coupling portions 11A and 11B overlap with the projected coupling portion 21.

[0039] For example, the main line 1 and the sub-line 2 intersect in the stacking direction of the conductor layers Lc. More specifically, in the stacking direction of the conductor layers Lc, the virtual line connecting the first and second ends of the main line 1 and the virtual line connecting the first and second ends of the sub-line 2 intersect with each other. That is, in a plan view, the virtual line connecting the first and second ends of the main line 1 and the virtual line connecting the first and second ends of the sub-line 2 intersect with each other. Furthermore, in the stacking direction of the conductor layers Lc, the virtual line connecting the vias V1 and V2 and the sub-line 2 intersect with each other. That is, in a plan view, the virtual line connecting the vias V1 and V2 and the sub-line 2 intersect with each other.

[0040] 5 to 7 are diagrams illustrating simulation results of the pass characteristics of couplers according to embodiments of the present disclosure. The solid lines in FIGS. 5 to 7 indicate the pass characteristics of coupler 101. The dashed lines in FIGS. 5 to 7 indicate the pass characteristics of coupler 101X according to a comparative example. Compared to coupler 101, coupler 101X does not include conductor layer Lc3 and dielectric layer Ld3, and the width of main line 1A is 320 μm.

[0041] 5 shows the transmission characteristics from input port P1 to output port P2 of couplers 101 and 101X. In FIG. 5, the horizontal axis represents the frequency [GHz] of input signal S1, and the vertical axis represents insertion loss [dB]. Insertion loss is the ratio of the power of output signal S2a output via output port P2 to the power of input signal S1 when input signal S1 is received via input port P1. It is preferable that the insertion loss be a value close to -3 dB.

[0042] Referring to FIG. 5, in the frequency band from 24 GHz to 32 GHz, the insertion loss of the coupler 101 is closer to −3 dB than the insertion loss of the coupler 101X.

[0043] 6 shows the transmission characteristics from input port P1 to coupled port P3 of couplers 101 and 101X. In FIG. 6, the horizontal axis represents the frequency [GHz] of input signal S1, and the vertical axis represents the degree of coupling [dB]. The degree of coupling is the ratio of the power of output signal S2b output via coupled port P3 to the power of input signal S1 when input signal S1 is received via input port P1. It is preferable that the degree of coupling be a value close to -3 dB.

[0044] Referring to FIG. 6, in the frequency band from 24 GHz to 32 GHz, the degree of coupling of the coupler 101 is closer to −3 dB than the degree of coupling of the coupler 101X.

[0045] 7 shows the transmission characteristics from input port P1 to isolation port P4 of couplers 101 and 101X. In FIG. 7, the horizontal axis represents the frequency [GHz] of input signal S1, and the vertical axis represents the isolation factor [dB]. The isolation factor is the ratio of the power of the output signal output via isolation port P4 to the power of input signal S1 when input signal S1 is received via input port P1. In practice, the isolation factor is preferably -10 dB or less.

[0046] Referring to FIG. 7, in the frequency band from 24 GHz to 32 GHz, the isolation factor of coupler 101 is about −15 dB, which is a practical value.

[0047] FIG. 8 is a diagram illustrating simulation results of the phase characteristics of a coupler according to an embodiment of the present disclosure. The solid line in FIG. 8 represents the phase characteristics of the coupler 101. The dashed line in FIG. 8 represents the phase characteristics of the coupler 101X according to a comparative example. In FIG. 8, the horizontal axis represents the frequency [GHz] of the input signal S1, and the vertical axis represents the phase error [degree]. The phase error is a value obtained by adding 90° to the phase difference between the output signal S2a output via the output port P2 and the output signal S2b output via the coupled port P3. The phase error is preferably zero degrees.

[0048] Referring to FIG. 8, in the frequency band from 24 GHz to 32 GHz, the maximum absolute value of the phase error of the coupler 101 is about 3°, which is similar to the maximum absolute value of the phase error of the coupler 101X.

[0049] (Variation 1) Fig. 9 is an equivalent circuit diagram of a coupler according to Variation 1 of the embodiment of the present disclosure. Referring to Fig. 9, compared to coupler 101, coupler 102 includes a main line 3 instead of main line 1 and sub-lines 4A and 4B that are sub-lines 4 instead of sub-line 2. Main line 3 is an example of a second line. Sub-line 4 is an example of a first line.

[0050] For example, the main line 3 has a first end connected to the input port P1 and a second end connected to the output port P2, and the sub-lines 4A and 4B have first ends connected to the coupled port P3 and second ends connected to the isolated port P4.

[0051] 10 to 12 are diagrams schematically illustrating the configuration of a coupler according to a first modification of an embodiment of the present disclosure. FIG. 10 is a plan view of a coupler 102. FIG. 11 is a cross-sectional view taken along line XI-XI in FIG. 10. FIG. 12 is a plan view illustrating a layer configuration of the coupler 102. The solid line in FIG. 10 indicates a sub-line 4A. The dashed line in FIG. 10 indicates a main line 3.

[0052] 10 to 12, compared to coupler 101, coupler 102 has a sub-line 4 arranged at the position of main line 1 in the lamination direction of conductor layers Lc, and a main line 3 arranged at the position of sub-line 2 in the lamination direction of conductor layers Lc. More specifically, the main line 3 is formed on conductor layer Lc2, while sub-lines 4A and 4B are formed on conductor layers Lc1 and Lc3, respectively, sandwiching conductor layer Lc2 therebetween.

[0053] For example, the main line 3 and the sub-line 4 form a microstrip line. The width W4 of the sub-line 4 is smaller than the width W3 of the main line 3. As an example, the width W4 is 200 μm, and the width W3 is 320 μm. For example, the characteristic impedance of the main line 3 and the characteristic impedance of the line consisting of the sub-lines 4A and 4B is 50 Ω.

[0054] The main line 3 includes a linear coupling portion 31, a wiring portion 32 extending from a first end of the coupling portion 31, and a wiring portion 33 extending from a second end of the coupling portion 31. The sub-line 4A includes a linear coupling portion 41A, a wiring portion 42A extending from a first end of the coupling portion 41A, and a wiring portion 43A extending from a second end of the coupling portion 41A. The sub-line 4B includes a linear coupling portion 41B, a wiring portion 42B extending from a first end of the coupling portion 41B, and a wiring portion 43B extending from a second end of the coupling portion 41B. For example, the length L2 of the coupling portions 31, 41A, and 41B is λ / 4, where λ is the wavelength of the input signal S1.

[0055] The sub-lines 4A and 4B are electrically connected via vias V3 and V4. More specifically, the wiring portions 42A and 42B of the sub-lines 4A and 4B are connected via via V3. The wiring portions 43A and 43B of the sub-lines 4A and 4B are connected via via V4.

[0056] The main line 3 and the sub-line 4 at least partially overlap in the stacking direction of the conductor layers Lc. More specifically, coupling portions 41A and 41B of the sub-lines 4A and 4B are parallel to the coupling portion 31 of the main line 3 and overlap with the coupling portion 31 in a plan view.

[0057] For example, the main line 3 and the sub-line 4 intersect in the stacking direction of the conductor layers Lc. More specifically, in the stacking direction of the conductor layers Lc, a virtual line connecting the first and second ends of the sub-line 4 intersects with a virtual line connecting the first and second ends of the main line 3. Furthermore, in the stacking direction of the conductor layers Lc, a virtual line connecting the vias V3 and V4 intersects with the main line 3.

[0058] Fig. 13 is a diagram showing simulation results of the phase characteristics of couplers according to the modified example of the embodiment of the present disclosure. The solid line in Fig. 13 indicates the phase characteristics of coupler 101. The dashed line in Fig. 13 indicates the phase characteristics of coupler 102. In Fig. 13, the horizontal axis represents the frequency [GHz] of input signal S1, and the vertical axis represents the phase error [degree].

[0059] 13, in the frequency band from 24 GHz to 32 GHz, the maximum absolute value of the phase error of coupler 102 is about 2°, which is smaller than the maximum absolute value of the phase error of coupler 101. Therefore, in terms of phase characteristics, coupler 102 is superior to coupler 101.

[0060] Fig. 14 is a diagram showing simulation results of amplitude characteristics of couplers according to modified examples of the embodiment of the present disclosure. The solid line in Fig. 14 indicates the amplitude characteristics of coupler 101. The dashed line in Fig. 14 indicates the amplitude characteristics of coupler 102. In Fig. 14, the horizontal axis represents the frequency [GHz] of input signal S1, and the vertical axis represents the amplitude error [dB]. The amplitude error is the absolute value of the difference between the degree of coupling and the insertion loss. It is preferable that the amplitude error be zero dB.

[0061] 14 , in the frequency band from 24 GHz to 32 GHz, the amplitude error of coupler 102 is larger than that of coupler 101 due to the influence of transmission loss of sub-line 4 in vias V3 and V4, etc. In particular, the amplitude error of coupler 101 at 24 GHz is significantly smaller than the amplitude error of coupler 102 at 24 GHz. Therefore, in terms of amplitude characteristics, coupler 101 is superior to coupler 102.

[0062] The difference in phase characteristics between the couplers 101 and 102 is smaller than the difference in amplitude characteristics between the couplers 101 and 102. Therefore, when the phase characteristics and amplitude characteristics are taken into consideration comprehensively, the coupler 101 is superior to the coupler 102.

[0063] 15 is an equivalent circuit diagram of a coupler according to a second modification of the embodiment of the present disclosure. Referring to FIG. 15 , compared to coupler 101, coupler 103 includes main lines 5A, 5B, and 5C that are main lines 5 instead of main line 1, and includes a sub-line 6 instead of sub-line 2. Main line 5 is an example of a first line. Sub-line 6 is an example of a second line.

[0064] For example, the main line 5 has a first end connected to the input port P1 and a second end connected to the output port P2, and the sub-line 6 has a first end connected to the coupled port P3 and a second end connected to the isolated port P4.

[0065] 16 to 18 are diagrams schematically illustrating the configuration of a coupler according to a second modification of the embodiment of the present disclosure. FIG. 16 is a plan view of coupler 103. FIG. 17 is a cross-sectional view taken along line XVII-XVII in FIG. 16. FIG. 18 is a plan view illustrating the layer configuration of coupler 103. The solid line in FIG. 16 indicates a main line 5A. The dashed line in FIG. 16 indicates a sub-line 6.

[0066] 16 to 18, the sub-line 6 is formed on the conductor layer Lc2, while the main lines 5A and 5C are formed on the conductor layers Lc1 and Lc3, respectively, sandwiching the conductor layer Lc2. The main line 5B is formed on the conductor layer Lc2. Resin Rs2 is provided in the area of ​​the conductor layer Lc2 where the sub-line 6 and the main line 5B are not formed. Resin Rs3 is provided in the area of ​​the conductor layer Lc3 where the main line 5C is not formed.

[0067] For example, the main line 5 and the sub-line 6 form a microstrip line. The width W5 of the main line 5 is smaller than the width W6 of the sub-line 6. For example, the characteristic impedance of the line consisting of the main lines 5A, 5B, and 5C and the characteristic impedance of the sub-line 6 are 50 Ω.

[0068] The main line 5A includes a linear coupling portion 51A, a wiring portion 52A extending from a first end of the coupling portion 51A, and a wiring portion 53A extending from a second end of the coupling portion 51A. The main line 5B includes a linear coupling portion 51B, a wiring portion 52B extending from a first end of the coupling portion 51B, and a wiring portion 53B extending from a second end of the coupling portion 51B. The main line 5C includes a linear coupling portion 51C, a wiring portion 52C extending from a first end of the coupling portion 51C, and a wiring portion 53C extending from a second end of the coupling portion 51C. For example, the length L3 of the coupling portions 51A, 51B, and 51C is λ / 4, where λ is the wavelength of the input signal S1.

[0069] The main lines 5A, 5B, and 5C are electrically connected via vias V5 and V6. More specifically, the wiring portions 52A, 52B, and 52C of the main lines 5A, 5B, and 5C are connected via via V5. Furthermore, the wiring portions 53A, 53B, and 53C of the main lines 5A, 5B, and 5C are connected via via V6.

[0070] The main line 5 and the sub-line 6 at least partially overlap in the stacking direction of the conductor layers Lc. More specifically, coupling portions 51A and 51C of the main lines 5A and 5C are parallel to the sub-line 6 and overlap the sub-line 6 in a plan view. Furthermore, the coupling portion 51B of the main line 5B is parallel to the sub-line 6. It is preferable that the distance between the coupling portion 51B and the sub-line 6 be as small as possible.

[0071] 19 is an equivalent circuit diagram of a coupler according to a third modification of the embodiment of the present disclosure. Referring to Fig. 19, a coupler 104 is different from the coupler 101 in that it includes sub-lines 8A and 8B that are sub-line 8 instead of the sub-line 2. The sub-line 8 is an example of a second line.

[0072] For example, the sub-lines 8A and 8B have first ends connected to the coupled port P3 and second ends connected to the isolated port P4.

[0073] 20 to 22 are diagrams schematically illustrating the configuration of a coupler according to a third modification of the embodiment of the present disclosure. FIG. 20 is a plan view of a coupler 104. FIG. 21 is a cross-sectional view taken along line XXI-XXI in FIG. 20. FIG. 22 is a plan view illustrating a layer configuration of the coupler 104. The solid line in FIG. 20 indicates a main line 1A. The dashed line in FIG. 20 indicates a sub-line 8A.

[0074] Compared to the coupler 101, the coupler 104 further includes a conductor layer Lc5 that is the conductor layer Lc, and a dielectric layer Ld4.

[0075] The conductor layers Lc1, Lc2, Lc3, Lc5, and Lc4 are stacked in this order with the dielectric layers Ld1, Ld2, Ld3, and Ld4 interposed therebetween. More specifically, the conductor layer Lc4 is formed on a first of the two main surfaces of the dielectric layer Ld3. The conductor layer Lc5 is formed on a second of the two main surfaces of the dielectric layer Ld3. The conductor layer Lc3 is formed on one of the two main surfaces of the dielectric layer Ld4 formed on the conductor layer Lc5, opposite the surface facing the conductor layer Lc5. The conductor layer Lc2 is formed on one of the two main surfaces of the dielectric layer Ld2 formed on the conductor layer Lc3, opposite the surface facing the conductor layer Lc3. The conductor layer Lc1 is formed on one of the two main surfaces of the dielectric layer Ld1 formed on the conductor layer Lc2, opposite the surface facing the conductor layer Lc2.

[0076] For example, the dielectric layer Ld4 has a thickness of 100 μm, a relative dielectric constant of 3.2, and a dielectric loss tangent of 0.004.

[0077] The main line 1 and the sub-line 8 are formed on different conductor layers Lc. More specifically, the sub-lines 8A and 8B are formed on conductor layers Lc2 and Lc5, respectively, while the main lines 1A and 1B are formed on conductor layers Lc1 and Lc3, respectively. Resin Rs2 is provided in the region of conductor layer Lc2 where the sub-line 8A is not formed. Resin Rs3 is provided in the region of conductor layer Lc3 where the main line 1B is not formed. Resin Rs3 functions as an adhesive that bonds together the dielectric layers Ld2 and Ld4. Dielectric resin Rs5 is provided in the region of conductor layer Lc5 where the sub-line 8B is not formed. Resin Rs5 functions as an adhesive that bonds together the dielectric layers Ld4 and Ld3.

[0078] For example, the main line 1 and the sub-line 8 form a microstrip line. The width W8 of the main line 1 and the sub-line 8 is, for example, 200 μm. For example, the characteristic impedance of the line consisting of the main lines 1A and 1B and the characteristic impedance of the line consisting of the sub-lines 8A and 8B are 50 Ω.

[0079] The sub-line 8A includes a linear coupling portion 81A, a wiring portion 82A extending from a first end of the coupling portion 81A, and a wiring portion 83A extending from a second end of the coupling portion 81A. The sub-line 8B includes a linear coupling portion 81B, a wiring portion 82B extending from a first end of the coupling portion 81B, and a wiring portion 83B extending from a second end of the coupling portion 81B. For example, the length L4 of the coupling portions 11A, 11B, 81A, and 81B is λ / 4, where λ is the wavelength of the input signal S1.

[0080] The sub-lines 8A and 8B are electrically connected via vias V9 and V10. More specifically, the wiring portions 82A and 82B of the sub-lines 8A and 8B are connected via via V9. The wiring portions 83A and 83B of the sub-lines 8A and 8B are connected via via V10.

[0081] The main line 1 and the sub-line 8 at least partially overlap in the stacking direction of the conductor layers Lc. More specifically, coupling portions 11A and 11B in the main lines 1A and 1B are parallel to coupling portions 81A and 81B in the sub-lines 8A and 8B and overlap the coupling portions 81A and 81B in a plan view.

[0082] For example, the main line 1 and the sub-line 8 intersect in the stacking direction of the conductor layers Lc. More specifically, in the stacking direction of the conductor layers Lc, a virtual line connecting the first and second ends of the main line 1 and a virtual line connecting the first and second ends of the sub-line 8 intersect with each other. Also, a virtual line connecting vias V1 and V2 intersects with the sub-line 8. Also, a virtual line connecting vias V9 and V10 intersects with the main line 1.

[0083] Although the coupler 104 has been described as having a configuration in which the main line 1 is formed across two conductor layers Lc and the sub-line 8 is formed across two conductor layers Lc, this is not limiting. The coupler 104 may also have a configuration in which the main line 1 is formed across three or more conductor layers Lc, or a configuration in which the sub-line 8 is formed across three or more conductor layers Lc. Specifically, for example, the coupler 104 further includes a main line 1C as the main line 1. The main line 1C is formed on a conductor layer Lc below the conductor layer Lc5 on which the sub-line 8B is formed. Furthermore, for example, the coupler 104 further includes a sub-line 8C as the sub-line 8. The sub-line 8C is formed on a conductor layer Lc below the conductor layer Lc on which the main line 1C is formed.

[0084] <Transmitter / Receiver> Fig. 23 is a diagram illustrating a configuration of a transmitter / receiver according to an embodiment of the present disclosure. Referring to Fig. 23, a transmitter / receiver 401 includes a signal input / output unit 111, a switch 121, a transmitter / receiver circuit 301, and antennas 221A, 221B, 221C, and 221D that are antennas 221. The transmitter / receiver 401 is an example of a transmitter. The antennas 221A, 221B, 221C, and 221D are examples of a first antenna, a second antenna, a third antenna, and a fourth antenna, respectively. The transmitter / receiver 401 is used for beamforming of RF (Radio Frequency) signals in a frequency band of 20 GHz or higher.

[0085] The transmission / reception circuit 301 includes the Butler matrix circuit 201 and the bidirectional amplifiers 211, 211A, 211B, 211C, and 211D. The transmission / reception circuit 301 is an example of a transmission circuit. The amplifiers 211A, 211B, 211C, and 211D are examples of a first amplifier, a second amplifier, a third amplifier, and a fourth amplifier, respectively. The transmission / reception circuit 301 is used to transmit and receive RF signals in a frequency band of 20 GHz or higher.

[0086] The signal input / output unit 111, the switch 121, and the amplifier 211 are mounted on a substrate 251. The Butler matrix circuit 201 is formed as a pattern on the substrate 251. For example, the antenna 221 is integrated with the substrate 251. The antenna 221 may be connected to the substrate 251 or may be formed as a pattern on the substrate 251.

[0087] The shape of the antenna 221 is, for example, rectangular. The length of the antenna 221 is equal to or greater than (0.15 × λrf) and equal to or less than (0.7 × λrf), where λrf is the wavelength of the RF signal transmitted and received by the transmission / reception circuit 301. The four antennas 221 may be arranged in a single column on a plane on which the antennas 221 are arranged, or may be arranged in two rows and two columns on the plane. The antennas 221 are spaced apart at equal intervals equal to or greater than (0.5 × λrf) and equal to or less than λrf.

[0088] The Butler matrix circuit 201 includes a plurality of couplers 101 and phase shifters 151A and 151B. For example, the Butler matrix circuit 201 includes couplers 101A, 101B, 101C, and 101D, which are the couplers 101. The couplers 101A, 101B, 101C, and 101D are examples of a first coupler, a second coupler, a third coupler, and a fourth coupler, respectively. The Butler matrix circuit 201 is a passive circuit realized using transmission lines, and therefore is less expensive than active phase shifters.

[0089] The input port P1 and the isolated port P4 of the coupler 101A are connected to nodes NB1 and NB2, respectively, of the switch 121. The input port P1 and the isolated port P4 of the coupler 101B are connected to nodes NB3 and NB4, respectively, of the switch 121. Hereinafter, each of the nodes NB1, NB2, NB3, and NB4 will also be referred to as a node NB.

[0090] The signal input / output unit 111 is connected to a node NA in the switch 121. The switch 121 is a single-pole, four-throw switch. The switch 121 receives a control signal from a control unit (not shown) and connects the node NA to one of the four nodes NB in ​​accordance with the received control signal.

[0091] The coupled port P3 of the coupler 101A is connected to the input port P1 of the coupler 101C via the phase shifter 151A. The output port P2 of the coupler 101A is connected to the input port P1 of the coupler 101D. The coupled port P3 of the coupler 101B is connected to the isolated port P4 of the coupler 101C. The output port P2 of the coupler 101B is connected to the isolated port P4 of the coupler 101D via the phase shifter 151B. The phase shifters 151A and 151B receive input signals and output output signals that have a phase difference of -45° with respect to the received input signals.

[0092] The coupled port P3 and the output port P2 of the coupler 101C are connected to the amplifiers 211A and 211B, respectively. The coupled port P3 and the output port P2 of the coupler 101D are connected to the amplifiers 211C and 211D, respectively.

[0093] The amplifiers 211A, 211B, 211C, and 211D are connected to the antennas 221A, 221B, 221C, and 221D, respectively. For example, the amplifier 211 is a GaN device configured using a GaN (gallium nitride) transistor. By using a GaN device as an amplifier, RF signals can be transmitted with higher power.

[0094] Generally, active phase shifters are configured using Si transistors, and therefore cannot be integrated in the same semiconductor IC or surface mount package as amplifier 211 using GaN devices, resulting in a problem of high costs. In contrast, the transceiver circuit 301 is configured to include Butler matrix circuit 201, which is a passive circuit, instead of active phase shifters, and therefore the phase shifters and amplifiers can be integrated on substrate 251 at lower cost than in a configuration that includes active phase shifters.

[0095] (Transmission of RF Signal) The signal input / output unit 111 receives an analog signal from a signal processing unit (not shown), and outputs an RF signal Sd based on the received analog signal to the Butler matrix circuit 201 via the switch 121 .

[0096] The Butler matrix circuit 201 receives an RF signal Sd from the signal input / output unit 111 via the switch 121 and outputs RF signals Sout1, Sout2, Sout3, and Sout4, which are RF signals Sout based on the received RF signal Sd, to the amplifiers 211A, 211B, 211C, and 211D, respectively. More specifically, the coupler 101C outputs the RF signal Sout1 to the amplifier 211A via the coupled port P3. The coupler 101C also outputs the RF signal Sout2 to the amplifier 211B via the output port P2. The coupler 101D also outputs the RF signal Sout3 to the amplifier 211C via the coupled port P3. The coupler 101D also outputs the RF signal Sout4 to the amplifier 211D via the output port P2.

[0097] The amplifier 211A amplifies the signal output from the coupled port P3 of the coupler 101C. More specifically, the amplifier 211A receives the RF signal Sout1 from the coupled port P3 of the coupler 101C, amplifies the received RF signal Sout1, and outputs the amplified signal to the antenna 221A.

[0098] The amplifier 211B amplifies the signal output from the output port P2 of the coupler 101C. More specifically, the amplifier 211B receives the RF signal Sout2 from the output port P2 of the coupler 101C, amplifies the received RF signal Sout2, and outputs the amplified signal to the antenna 221B.

[0099] The amplifier 211C amplifies the signal output from the coupled port P3 of the coupler 101D. More specifically, the amplifier 211C receives the RF signal Sout3 from the coupled port P3 of the coupler 101D, amplifies the received RF signal Sout3, and outputs the amplified signal to the antenna 221C.

[0100] The amplifier 211D amplifies the signal output from the output port P2 of the coupler 101D. More specifically, the amplifier 211D receives the RF signal Sout4 from the output port P2 of the coupler 101D, amplifies the received RF signal Sout4, and outputs the amplified signal to the antenna 221D.

[0101] The antenna 221A transmits the signal amplified by the amplifier 211A. More specifically, the antenna 221A wirelessly transmits the RF signal Sout1 received from the amplifier 211A.

[0102] The antenna 221B transmits the signal amplified by the amplifier 211B. More specifically, the antenna 221B wirelessly transmits the RF signal Sout2 received from the amplifier 211B.

[0103] The antenna 221C transmits the signal amplified by the amplifier 211C. More specifically, the antenna 221C wirelessly transmits the RF signal Sout3 received from the amplifier 211C.

[0104] The antenna 221D transmits the signal amplified by the amplifier 211D. More specifically, the antenna 221D wirelessly transmits the RF signal Sout4 received from the amplifier 211D.

[0105] 24 is a diagram illustrating an example of the beam direction of an RF signal transmitted by a transmission / reception device according to an embodiment of the present disclosure. Fig. 24 illustrates a correspondence relationship between a node NB connected to a node NA in the switch 121, a phase difference θ1 of the RF signal Sout relative to a predetermined phase, a phase difference θ2 between the RF signals Sout, and the beam direction of the RF signal Sout transmitted by the antenna 221. The beam direction is the transmission direction of the RF signal Sout based on the predetermined direction.

[0106] 24, when node NB1 is connected to node NA in switch 121, an RF signal Sout1 having a phase difference θ1 of −45°, an RF signal Sout2 having a phase difference θ1 of −90°, an RF signal Sout3 having a phase difference θ1 of −135°, and an RF signal Sout4 having a phase difference θ1 of −180° are output from Butler matrix circuit 201 to each amplifier 211. In this case, the phase difference θ2 is −45°, and the beam direction of RF signal Sout transmitted by antenna 221 is 15°.

[0107] Furthermore, when node NB2 is connected to node NA in switch 121, an RF signal Sout1 with a phase difference θ1 of −135°, an RF signal Sout2 with a phase difference θ1 of zero°, an RF signal Sout3 with a phase difference θ1 of 135°, and an RF signal Sout4 with a phase difference θ1 of −90° are output from the Butler matrix circuit 201 to each amplifier 211. In this case, the phase difference θ2 is +135°, and the beam direction of the RF signal Sout transmitted by antenna 221 is −50°.

[0108] Furthermore, when node NB3 is connected to node NA in switch 121, an RF signal Sout1 with a phase difference θ1 of −90°, an RF signal Sout2 with a phase difference θ1 of 135°, an RF signal Sout3 with a phase difference θ1 of zero°, and an RF signal Sout4 with a phase difference θ1 of −135° are output from the Butler matrix circuit 201 to each amplifier 211. In this case, the phase difference θ2 is −135°, and the beam direction of the RF signal Sout transmitted by antenna 221 is 50°.

[0109] Furthermore, when node NB4 is connected to node NA in switch 121, an RF signal Sout1 with a phase difference θ1 of −180°, an RF signal Sout2 with a phase difference θ1 of −135°, an RF signal Sout3 with a phase difference θ1 of −90°, and an RF signal Sout4 with a phase difference θ1 of −45° are output from the Butler matrix circuit 201 to each amplifier 211. In this case, the phase difference θ2 is +45°, and the beam direction of the RF signal Sout transmitted by antenna 221 is −15°.

[0110] (Reception of RF Signal) Antenna 221 receives RF signal Sin and outputs the received RF signal Sin to the corresponding amplifier 211. More specifically, antenna 221A receives RF signal Sin1, which is RF signal Sin, and outputs it to amplifier 211A. Antenna 221B receives RF signal Sin2, which is RF signal Sin, and outputs it to amplifier 211B. Antenna 221C receives RF signal Sin3, which is RF signal Sin, and outputs it to amplifier 211C. Antenna 221D receives RF signal Sin4, which is RF signal Sin, and outputs it to amplifier 211D.

[0111] The amplifier 211A receives the RF signal Sin1 from the antenna 221A, amplifies the received RF signal Sin1, and outputs it to the coupled port P3 of the coupler 101C. The amplifier 211B receives the RF signal Sin2 from the antenna 221B, amplifies the received RF signal Sin2, and outputs it to the output port P2 of the coupler 101C. The amplifier 211C receives the RF signal Sin3 from the antenna 221C, amplifies the received RF signal Sin3, and outputs it to the coupled port P3 of the coupler 101D. The amplifier 211D receives the RF signal Sin4 from the antenna 221D, amplifies the received RF signal Sin4, and outputs it to the output port P2 of the coupler 101D.

[0112] The Butler matrix circuit 201 receives an RF signal Sin from each amplifier 211 and outputs an RF signal Su based on the received RF signal Sin to the signal input / output unit 111 via the switch 121. The signal input / output unit 111 outputs an analog signal based on the RF signal Su received from the Butler matrix circuit 201 to a signal processing unit (not shown).

[0113] More specifically, when node NB1 in switch 121 is connected to node NA, coupler 101A outputs an RF signal Su based on an RF signal Sin received from each antenna 221 in a 15° beam direction and amplified in each amplifier 211 to signal input / output unit 111 via input port P1 and switch 121.

[0114] Furthermore, when node NB2 in switch 121 is connected to node NA, coupler 101A outputs an RF signal Su based on an RF signal Sin received from each antenna 221 in a beam direction of -50° and amplified in each amplifier 211 to signal input / output unit 111 via isolation port P4 and switch 121.

[0115] Furthermore, when node NB3 in switch 121 is connected to node NA, coupler 101B outputs an RF signal Su based on an RF signal Sin received from each antenna 221 in a 50° beam direction and amplified in each amplifier 211 to signal input / output unit 111 via input port P1 and switch 121.

[0116] In addition, when node NB4 in switch 121 is connected to node NA, coupler 101B outputs an RF signal Su based on an RF signal Sin received from each antenna 221 in a beam direction of -15° and amplified in each amplifier 211 to signal input / output unit 111 via isolation port P4 and switch 121.

[0117] The coupler 101 according to the embodiment of the present disclosure may be used in a Doherty amplifier as an electronic component other than the Butler matrix circuit 201 .

[0118] Furthermore, in the transceiver 401 according to the embodiment of the present disclosure, the transceiver circuit 301 is configured to include the bidirectional amplifier 211, but this is not limiting. When the transceiver 401 performs time division duplex, the transceiver circuit 301 may be configured to include a unidirectional amplifier for transmission and a unidirectional amplifier for reception that operate in a time division manner, instead of the amplifier 211.

[0119] Furthermore, although the transceiver 401 according to the embodiment of the present disclosure has been described as being configured to transmit and receive RF signals, this is not limiting. The transceiver 401 may be configured to transmit RF signals but not receive them. In this case, the transceiver 401 includes a signal input unit that receives an analog signal from a signal processing unit (not shown) instead of the signal input / output unit 111. The transceiver 401 may also be configured to receive RF signals but not transmit them. In this case, the transceiver 401 includes a signal output unit that outputs an analog signal to a signal processing unit (not shown) instead of the signal input / output unit 111.

[0120] Furthermore, although the transceiver circuit 301 according to the embodiment of the present disclosure is configured to transmit and receive RF signals, this is not limiting. The transceiver circuit 301 may be configured to transmit RF signals but not receive them. In this case, the transceiver circuit 301 includes a unidirectional amplifier that amplifies the RF signal Sout instead of the bidirectional amplifier 211. The transceiver circuit 301 may also be configured to receive RF signals but not transmit them. In this case, the transceiver circuit 301 includes a unidirectional amplifier that amplifies the RF signal Sin instead of the bidirectional amplifier 211.

[0121] In addition, in the transceiver circuit 301 according to the embodiment of the present disclosure, the Butler matrix circuit 201 is configured to include the coupler 101, but this is not limited to this. The Butler matrix circuit 201 may be configured to include the coupler 102, the coupler 103, or the coupler 104 instead of the coupler 101.

[0122] The above-described embodiments should be considered to be illustrative in all respects and not restrictive. The scope of the present invention is defined by the claims, not by the above description, and is intended to include all modifications within the meaning and scope of the claims.

[0123] The above description includes the following additional features. [Supplementary Note 1] A transmission circuit used for transmitting signals in a frequency band of 20 GHz or more, comprising: a Butler matrix circuit formed on the same substrate and including a plurality of coupled-line type couplers having a multilayer structure in which a plurality of conductor layers are stacked; and a plurality of amplifiers mounted on the substrate, wherein the couplers include a first line and a second line formed on different conductor layers, the first line being formed across a plurality of conductor layers sandwiching the conductor layer on which the second line is formed, and the first line and the second line at least partially overlap in the stacking direction of the conductor layers, the couplers including an input port, an output port, a coupled port, and an isolated port, wherein the coupled port of a first coupler is connected to the input port of a third coupler, the coupled port of the second coupler is connected to the isolated port of the third coupler, and the output port of the first coupler is connected to the input port of a fourth coupler, a transmission circuit, wherein the output port of the second coupler is connected to the isolated port of the fourth coupler, and the plurality of amplifiers include a first amplifier that amplifies a signal output from the coupled port of the third coupler, a second amplifier that amplifies a signal output from the output port of the third coupler, a third amplifier that amplifies a signal output from the coupled port of the fourth coupler, and a fourth amplifier that amplifies a signal output from the output port of the fourth coupler, and the plurality of amplifiers are configured using GaN transistors.

[0124] 1, 1A, 1B, 3, 5, 5A, 5B, 5C Main line 2, 4, 4A, 4B, 6, 8, 8A, 8B Sub line 11A, 11B, 21, 31, 41A, 41B, 51A, 51B, 51C, 81A, 81B Connection part 12A, 12B, 13A, 13B, 22, 23, 32, 33, 42A, 42B, 43A, 43B, 52A, 52B, 52C, 53A, 53B, 53C, 82A, 82B, 83A, 83B Wiring part 101, 101A, 101B, 101C, 101D, 102, 103, 104 Coupler 111 Signal input / output section 121 Switch 151A, 151B Phase shifter 201 Butler matrix circuit 211, 211A, 211B, 211C, 211D Amplifier 221, 221A, 221B, 221C, 221D Antenna 251 Substrate 301 Transmitting / receiving circuit 401 Transmitting / receiving device P1 Input port P2 Output port P3 Coupling port P4 Isolation port V1, V2, V3, V4, V5, V6, V9, V10 Vias Lc, Lc1, Lc2, Lc3, Lc4, Lc5 Conductor layer Ld1, Ld2, Ld3, Ld4 Dielectric layer Rs2, Rs3, Rs5 Resin GND Ground pattern NA, NB, NB1, NB2, NB3, NB4 Node

Claims

1. A coupled-line type coupler having a multi-layer structure in which a plurality of conductive layers are stacked, comprising a first line and a second line formed in different conductive layers, the first line being formed in a plurality of the conductive layers sandwiching the conductive layer in which the second line is formed, and the first line and the second line at least partially overlap in the stacking direction of the conductive layers.

2. A coupler as described in claim 1, wherein the first line has a first end connected to an input port of the coupler and a second end connected to an output port of the coupler, and the second line has a first end connected to a coupled port of the coupler and a second end connected to an isolated port of the coupler.

3. A coupler according to claim 1 or claim 2, wherein the first line is further formed on the conductive layer on which the second line is formed.

4. A Butler matrix circuit comprising: a plurality of coupled-line type couplers formed on the same substrate and having a multi-layer structure in which a plurality of conductive layers are stacked, the couplers comprising first and second lines formed in different conductive layers, the first line being formed across a plurality of conductive layers sandwiching the conductive layer in which the second line is formed, the first and second lines overlap at least partially in the stacking direction of the conductive layers, the couplers including an input port, an output port, a coupled port and an isolated port, the coupled port of a first coupler being connected to the input port of a third coupler, the coupled port of a second coupler being connected to the isolated port of the third coupler, the output port of the first coupler being connected to the input port of a fourth coupler, and the output port of the second coupler being connected to the isolated port of the fourth coupler.

5. The Butler matrix circuit according to claim 4, wherein the first line and the second line cross each other in a lamination direction of the conductive layers.

6. A transmission circuit used for transmitting signals in a frequency band of 20 GHz or more, comprising: a Butler matrix circuit as defined in claim 4 or 5; and a plurality of amplifiers mounted on the substrate, the plurality of amplifiers including a first amplifier that amplifies a signal output from the coupled port of the third coupler, a second amplifier that amplifies a signal output from the output port of the third coupler, a third amplifier that amplifies a signal output from the coupled port of the fourth coupler, and a fourth amplifier that amplifies a signal output from the output port of the fourth coupler.

7. A transmitting device used for beamforming, comprising: a transmitting circuit as described in claim 6; and a plurality of antennas, the plurality of antennas including a first antenna for transmitting a signal amplified by the first amplifier, a second antenna for transmitting a signal amplified by the second amplifier, a third antenna for transmitting a signal amplified by the third amplifier, and a fourth antenna for transmitting a signal amplified by the fourth amplifier.