Epitaxial silicon carbide substrate, method for producing epitaxial silicon carbide substrate, and method for producing silicon carbide semiconductor device

Abstract

This epitaxial silicon carbide substrate comprises a silicon carbide substrate and an epitaxial silicon carbide layer. The epitaxial silicon carbide layer has a first main surface. The first main surface has a projection made of silicon carbide. The first main surface is composed of an outer edge, a peripheral region, and a central region. When the central region is divided into a plurality of square regions each having a side length of 10 mm, the plurality of square regions are composed of a first square region, which is nearest to the projection, and second square regions, which are a plurality of square regions other than the first square regions. The first square region has an LTV greater than the LTV of each of the plurality of square regions constituting the second square regions. The LTV of the first square region is 2 μm or less.

Description

Silicon carbide epitaxial substrate, method for manufacturing silicon carbide epitaxial substrate, and method for manufacturing silicon carbide semiconductor device

[0001] The present disclosure relates to a silicon carbide epitaxial substrate, a method for manufacturing a silicon carbide epitaxial substrate, and a method for manufacturing a silicon carbide semiconductor device. This application claims priority to Japanese Patent Application No. 2023-107032, filed on June 29, 2023. The entire contents of this Japanese patent application are incorporated herein by reference.

[0002] Japanese Patent Laid-Open Publication No. 2019-151543 (Patent Document 1) discloses a method for manufacturing a silicon carbide epitaxial wafer, which includes the steps of preparing a silicon carbide substrate having a first main surface and a second main surface opposing the first main surface, polishing the second main surface so that the surface roughness is 20 nm or more, and epitaxially growing a silicon carbide layer on the first main surface.

[0003] Japanese Patent Application Laid-Open No. 2019-151543

[0004] A silicon carbide epitaxial substrate according to the present disclosure includes a silicon carbide substrate and a silicon carbide epitaxial layer. The silicon carbide epitaxial layer is provided on the silicon carbide substrate. The silicon carbide epitaxial layer includes a first main surface. The first main surface is opposite to the interface between the silicon carbide substrate and the silicon carbide epitaxial layer. A protrusion made of silicon carbide is present on the first main surface. The first main surface is composed of an outer edge, an outer peripheral region, and a central region. The outer peripheral region is a region within 3 mm from the outer edge. The central region is surrounded by the outer peripheral region. When the central region is divided into a plurality of square regions with a side length of 10 mm, the plurality of square regions are composed of a first square region closest to the protrusion and second square regions which are a plurality of square regions other than the first square region. The LTV of the first square region is greater than the LTV of each of the plurality of square regions that make up the second square region, and the LTV of the first square region is 2 μm or less.

[0005] FIG. 1 is a plan view schematic diagram showing the configuration of a silicon carbide substrate according to this embodiment. FIG. 2 is a cross-sectional view schematic diagram taken along line II-II in FIG. 1. FIG. 3 is an enlarged cross-sectional view schematic diagram taken along line III-III in FIG. 1. FIG. 4 is a plan view schematic diagram showing a measurement region for LTV. FIG. 5 is a schematic diagram for explaining the definition of LTV. FIG. 6 is a partial cross-sectional view schematic diagram showing the configuration of an apparatus for manufacturing a silicon carbide epitaxial substrate. FIG. 7 is a flow chart outlining a method for manufacturing a silicon carbide epitaxial substrate according to this embodiment. FIG. 8 is a cross-sectional view schematic diagram showing a step of adhering silicon carbide particles to a first rear surface. FIG. 9 is a cross-sectional view schematic diagram showing a step of forming a silicon carbide epitaxial layer on a first silicon carbide substrate. FIG. 10 is a bottom view schematic diagram showing the configuration of a triangular defect. FIG. 11 is a cross-sectional view schematic diagram showing a step of forming a silicon carbide epitaxial layer on a second silicon carbide substrate. FIG. 12 is a cross-sectional view schematically illustrating a step of removing the fourth silicon carbide epitaxial layer by polishing. FIG. 13 is a cross-sectional view schematically illustrating a configuration of a mechanical polishing apparatus. FIG. 14 is a flow diagram generally illustrating a method for manufacturing a silicon carbide semiconductor device according to this embodiment. FIG. 15 is a cross-sectional view schematically illustrating a step of preparing a silicon carbide epitaxial substrate. FIG. 16 is a cross-sectional view schematically illustrating a step of forming a body region. FIG. 17 is a cross-sectional view schematically illustrating a step of forming a source region. FIG. 18 is a cross-sectional view schematically illustrating a step of forming a trench in a first main surface of the silicon carbide epitaxial layer. FIG. 19 is a cross-sectional view schematically illustrating a step of forming a gate insulating film. FIG. 20 is a cross-sectional view schematically illustrating a step of forming a gate electrode and an interlayer insulating film. FIG. 21 is a cross-sectional view schematically illustrating a configuration of the silicon carbide semiconductor device according to this embodiment. FIG. 22 is a cross-sectional view schematically illustrating a state in which a protrusion is in contact with a polishing head. 23 and 24 are schematic diagrams showing measurement results of the LTV of each of the plurality of square regions after the step of forming a silicon carbide epitaxial layer on the second silicon carbide substrate and before the step of removing the fourth silicon carbide epitaxial layer by polishing, respectively.

[0006] [Problem to be Solved by the Present Disclosure] An object of the present disclosure is to provide a silicon carbide epitaxial substrate, a method for manufacturing a silicon carbide epitaxial substrate, and a method for manufacturing a silicon carbide semiconductor device, which are capable of improving the yield of silicon carbide semiconductor devices.

[0007] Effect of the Present Disclosure The present disclosure can provide a silicon carbide epitaxial substrate, a method for manufacturing a silicon carbide epitaxial substrate, and a silicon carbide semiconductor device that can improve the yield of silicon carbide semiconductor devices.

[0008] [Description of Embodiments of the Present Disclosure] First, embodiments of the present disclosure will be listed and described.

[0009] (1) A silicon carbide epitaxial substrate according to the present disclosure includes a silicon carbide substrate and a silicon carbide epitaxial layer. The silicon carbide epitaxial layer is provided on the silicon carbide substrate. The silicon carbide epitaxial layer has a first main surface. The first main surface is opposite to the interface between the silicon carbide substrate and the silicon carbide epitaxial layer. A protrusion made of silicon carbide is present on the first main surface. The first main surface is composed of an outer edge, an outer peripheral region, and a central region. The outer peripheral region is a region within 3 mm from the outer edge. The central region is surrounded by the outer peripheral region. When the central region is divided into a plurality of square regions with a side length of 10 mm, the plurality of square regions are composed of a first square region closest to the protrusion and second square regions that are a plurality of square regions other than the first square region. The LTV of the first square region is greater than the LTV of each of the plurality of square regions that make up the second square region, and the LTV of the first square region is 2 μm or less.

[0010] (2) In the silicon carbide epitaxial substrate according to (1) above, the LTV of the first square region may be 1.5 μm or less.

[0011] (3) In the silicon carbide epitaxial substrate according to (1) or (2) above, the silicon carbide epitaxial layer may have a thickness of 10 μm or more and 30 μm or less.

[0012] (4) A silicon carbide epitaxial substrate according to the present disclosure includes a silicon carbide substrate and a silicon carbide epitaxial layer. The silicon carbide epitaxial layer is provided on the silicon carbide substrate. The silicon carbide epitaxial layer has a first main surface. The first main surface is located opposite an interface between the silicon carbide substrate and the silicon carbide epitaxial layer. The silicon carbide substrate has a second main surface. The second main surface is located opposite the interface. The first main surface is composed of an outer edge, a peripheral region, and a central region. The peripheral region is a region within 3 mm from the outer edge. The central region is surrounded by the outer edge region. When the central region is divided into a plurality of square regions with a side length of 10 mm, the maximum LTV value in the plurality of square regions is 2 μm or less.

[0013] (5) In the silicon carbide epitaxial substrate according to (4) above, the maximum value of the LTV in the plurality of square regions may be 1.5 μm or less.

[0014] (6) A method for manufacturing a silicon carbide epitaxial substrate according to the present disclosure includes the steps of: preparing a first silicon carbide substrate having a first back surface and a first front surface opposite the first back surface; attaching silicon carbide particles to the first back surface; and forming a first silicon carbide epitaxial layer in contact with the first front surface and in contact with the first back surface and the silicon carbide particles. In the steps of forming the first silicon carbide epitaxial layer and the second silicon carbide epitaxial layer, triangular defects are formed in the second silicon carbide epitaxial layer, starting from the silicon carbide particles. The method for manufacturing a silicon carbide epitaxial substrate according to the present disclosure further includes the steps of measuring the thickness of the second silicon carbide epitaxial layer using triangular defects in the second silicon carbide epitaxial layer, determining a polishing amount based on the measured thickness of the second silicon carbide epitaxial layer, preparing a second silicon carbide substrate having a second back surface and a second front surface opposite the second back surface, forming a third silicon carbide epitaxial layer in contact with the second front surface and forming a fourth silicon carbide epitaxial layer in contact with the second back surface, and removing the fourth silicon carbide epitaxial layer by polishing based on the polishing amount.

[0015] (7) In the method for manufacturing a silicon carbide epitaxial substrate according to (6), the second silicon carbide epitaxial layer may have a thickness of less than 1 μm. The polishing amount may be 8.5 μm or more and 12.5 μm or less.

[0016] (8) In the method for manufacturing a silicon carbide epitaxial substrate according to (6), the second silicon carbide epitaxial layer may have a thickness of 1 μm or more and 2 μm or less. The polishing amount may be 11 μm or more and 16.5 μm or less.

[0017] (9) A method for manufacturing a silicon carbide semiconductor device according to the present disclosure includes the following steps: preparing a silicon carbide epitaxial substrate according to any one of (1) to (5) above; and forming an electrode on the silicon carbide epitaxial layer.

[0018] [Details of the Embodiments of the Present Disclosure] Hereinafter, details of the embodiments of the present disclosure will be described with reference to the drawings. Note that the same or corresponding parts in the following drawings are given the same reference numerals, and their description will not be repeated. In the crystallographic descriptions in this specification, individual orientations are indicated by [ ], collective orientations by < >, individual planes by ( ), and collective planes by {}. Furthermore, for negative indices, in crystallography, a "-" (bar) is placed before the number, but in this specification, a negative sign is placed before the number.

[0019] First, the configuration of the silicon carbide substrate according to this embodiment will be described. Fig. 1 is a plan view schematically showing the configuration of the silicon carbide substrate according to this embodiment. Fig. 2 is a cross-sectional view schematically showing the configuration of the silicon carbide substrate according to this embodiment taken along line II-II in Fig. 1.

[0020] 1 and 2 , silicon carbide epitaxial substrate 100 according to this embodiment mainly has a first main surface 1, a second main surface 2, and a peripheral side surface 9. Second main surface 2 is opposite first main surface 1. Peripheral side surface 9 is continuous with both first main surface 1 and second main surface 2. First main surface 1 is continuous with peripheral side surface 9 at an outer edge 6.

[0021] As shown in Fig. 1, the first main surface 1 is composed of an outer edge 6, an outer peripheral region 11, and a central region 12. The outer peripheral region 11 is a region within 3 mm from the outer edge 6. When viewed along a line perpendicular to the first main surface 1, the distance E between the outer edge 6 and the boundary between the outer peripheral region 11 and the central region 12 is 3 mm. From another perspective, the width (distance E) of the outer peripheral region 11 in the direction extending radially from the center O of the first main surface 1 (radial direction) is 3 mm.

[0022] Central region 12 is surrounded by peripheral region 11. Central region 12 is continuous with peripheral region 11. Central region 12 is a region whose distance from outer edge 6 is greater than 3 mm. Silicon carbide epitaxial substrate 100 is made of, for example, hexagonal silicon carbide. The polytype of the hexagonal silicon carbide is, for example, 4H.

[0023] As shown in Fig. 1 , the outer peripheral side surface 9 has, for example, an orientation flat portion 7 and an arc-shaped portion 8. As shown in Fig. 1 , the orientation flat portion 7 is linear when viewed along a line perpendicular to the first main surface 1. When viewed along a line perpendicular to the first main surface 1, the orientation flat portion 7 may extend along a first direction 101. The arc-shaped portion 8 is continuous with the orientation flat portion 7. When viewed along a line perpendicular to the first main surface 1, the arc-shaped portion 8 has an arc shape. When viewed along a line perpendicular to the first main surface 1, the center O of the first main surface 1 is the center of a circle that includes an arc along the arc-shaped portion 8.

[0024] 1 , when viewed along a line perpendicular to the first main surface 1, the first main surface 1 extends along each of a first direction 101 and a second direction 102. When viewed along a line perpendicular to the first direction 101, the second direction 102 is a direction perpendicular to the first direction 101.

[0025] The first direction 101 is, for example, the <11-20> direction. The first direction 101 may be, for example, the [11-20] direction. The first direction 101 may be a direction obtained by projecting the <11-20> direction onto the first main surface 1. From another perspective, the first direction 101 may be, for example, a direction including a <11-20> direction component.

[0026] The second direction 102 is, for example, the <1-100> direction. The second direction 102 may be, for example, the [1-100] direction. The second direction 102 may be, for example, a direction obtained by projecting the <1-100> direction onto the first main surface 1. From another perspective, the second direction 102 may be, for example, a direction including a <1-100> direction component.

[0027] The maximum diameter W of the first main surface 1 is not particularly limited, but is, for example, 100 mm (4 inches) or more. The maximum diameter W may be 125 mm (5 inches) or more, 150 mm (6 inches) or more, or 200 mm (8 inches) or more. The maximum diameter W may be, for example, 400 mm (16 inches) or less. When viewed along a line perpendicular to the first main surface 1, the maximum diameter W is the longest linear distance between two different points on the outer edge 6.

[0028] As used herein, 4 inches refers to 100 mm or 101.6 mm (4 inches x 25.4 mm / inch). 6 inches refers to 150 mm or 152.4 mm (6 inches x 25.4 mm / inch). 8 inches refers to 200 mm or 203.2 mm (8 inches x 25.4 mm / inch). 16 inches refers to 400 mm or 406.4 mm (16 inches x 25.4 mm / inch).

[0029] As shown in Fig. 2 , the third direction 103 is a direction from the second main surface 2 toward the first main surface 1. The third direction 103 is perpendicular to both the first direction 101 and the second direction 102. The cross section shown in Fig. 2 is perpendicular to the first main surface 1 and parallel to the first direction 101.

[0030] 2 , silicon carbide epitaxial substrate 100 has a silicon carbide substrate 30 and a silicon carbide epitaxial layer 40. Silicon carbide substrate 30 has a second main surface 2 and a third main surface 3.

[0031] The second main surface 2 is the back surface of the silicon carbide epitaxial substrate 100. The second main surface 2 is opposite to the interface 5 between the silicon carbide substrate 30 and the silicon carbide epitaxial layer 40. The second main surface 2 is a polished surface. For example, scratches (not shown) are formed on the second main surface 2. The scratches are marks formed during mechanical polishing and chemical mechanical polishing. When viewed along a line perpendicular to the second main surface 2, the shape of the scratches is, for example, linear. When viewed along a line perpendicular to the second main surface 2, the value obtained by dividing the length of the scratch in the longitudinal direction of the scratch by the length of the scratch in the lateral direction of the scratch may be, for example, 7 or more, 10 or more, or 15 or more. Triangular defects may not be formed on the second main surface 2. The detailed configuration of the triangular defects will be described later.

[0032] Third main surface 3 is opposite second main surface 2. At third main surface 3, silicon carbide substrate 30 is in contact with silicon carbide epitaxial layer 40. Silicon carbide substrate 30 contains n-type impurities such as nitrogen. The conductivity type of silicon carbide substrate 30 is, for example, n-type. The polytype of silicon carbide constituting silicon carbide substrate 30 is, for example, 4H.

[0033] Silicon carbide substrate 30 has a thickness (second thickness H2) in third direction 103 of, for example, 200 μm or more and 600 μm or less. Second thickness H2 is not particularly limited. Second thickness H2 may be, for example, 500 μm or less, or 350 μm or less.

[0034] Silicon carbide epitaxial layer 40 is provided on silicon carbide substrate 30. Silicon carbide epitaxial layer 40 has first main surface 1. First main surface 1 is the surface of silicon carbide epitaxial substrate 100. First main surface 1 is opposite interface 5.

[0035] In third direction 103, silicon carbide epitaxial layer 40 has a thickness (first thickness H1) of, for example, 10 μm or more and 30 μm or less. First thickness H1 may be, for example, 13 μm or more, or 18 μm or more. First thickness H1 may be, for example, 27 μm or less, or 22 μm or less.

[0036] The first thickness H1 can be measured using, for example, an FTIR (Fourier Transform InfraRed spectrometer). The measuring device is, for example, a Fourier transform infrared spectrophotometer (IRPrestige-21) manufactured by Shimadzu Corporation. The thickness of the silicon carbide epitaxial layer using FTIR is determined by utilizing the difference in optical constants caused by the difference in carrier concentration between the silicon carbide epitaxial layer 40 and the silicon carbide substrate 30. The measurement wavenumber range is, for example, 3400 cm －１ From 2400 cm －１ The wave number interval is, for example, 4 cm －１ That's about it.

[0037] Silicon carbide epitaxial layer 40 has a buffer layer 41 and a drift layer 42. Drift layer 42 may be a single layer or may be two or more layers. The polytype of silicon carbide constituting silicon carbide epitaxial layer 40 is, for example, 4H.

[0038] Buffer layer 41 is provided on silicon carbide substrate 30. Buffer layer 41 is in contact with silicon carbide substrate 30. Buffer layer 41 contains an n-type impurity such as nitrogen. The conductivity type of buffer layer 41 is, for example, n-type. The thickness of buffer layer 41 in third direction 103 is, for example, 1 μm or more.

[0039] The drift layer 42 is provided on the buffer layer 41. The drift layer 42 is in contact with the buffer layer 41. The drift layer 42 constitutes the first main surface 1. The drift layer 42 contains n-type impurities such as nitrogen. The conductivity type of the drift layer 42 is, for example, n-type. The concentration of the n-type impurities in the drift layer 42 is, for example, lower than the concentration of the n-type impurities in the buffer layer 41. The thickness of the drift layer 42 in the third direction 103 is, for example, 10 μm or more.

[0040] As shown in FIG. 2 , the first main surface 1 is a surface inclined with respect to the {0001} plane. The off angle θ of the first main surface 1 with respect to the {0001} plane is, for example, greater than 0° and equal to or less than 8°. Specifically, the first main surface 1 may be a surface inclined with respect to the (0001) plane by the off angle θ. The first main surface 1 may be a surface inclined with respect to the (000-1) plane by the off angle θ. The inclination direction (off direction) of the first main surface 1 with respect to the {0001} plane is, for example, the <11-20> direction. The off angle θ is not particularly limited. The off angle θ may be, for example, 7° or less, 6° or less, or 5° or less. The off angle θ may be, for example, 1° or more, or 2° or more.

[0041] Fig. 3 is an enlarged schematic cross-sectional view taken along line III-III in Fig. 1. The cross section shown in Fig. 3 is parallel to both the third direction 103 and the radial direction. As shown in Figs. 1 and 3, protrusions 60 are present on the first main surface 1. The protrusions 60 are located, for example, in the outer peripheral region 11. The protrusions 60 may also be located in the central region 12. For ease of explanation, the protrusions 60 are indicated by black circles in Fig. 1.

[0042] As shown in FIG. 3 , the protrusion 60 is convex along the third direction 103. A portion of the protrusion 60 may be located radially outward from the outer peripheral side surface 9. The protrusion 60 may cover a portion of the outer edge 6 (see FIG. 1 ). The protrusion 60 is made of silicon carbide. The protrusion 60 is, for example, an epi-crown or a particle. When viewed in a direction from the first main surface 1 toward the second main surface 2, the shape of the protrusion 60 is, for example, a circular shape. In a cross section parallel to each of the third direction 103 and the radial direction, the width of the protrusion 60 in the radial direction is defined as a first width F1.

[0043] The protrusion 60 forms a convex surface 66. The convex surface 66 is convex along the third direction 103. The convex surface 66 forms a part of the first main surface 1. The convex surface 66 may be continuous with the outer peripheral side surface 9. The first main surface 1 has a first flat surface 81 and a second flat surface 82. The first flat surface 81 is continuous with the convex surface 66. The first flat surface 81 extends along each of the first direction 101 and the second direction 102.

[0044] The second flat surface 82 is continuous with the first flat surface 81. The second flat surface 82 is spaced apart from the convex surface 66. When viewed in the direction from the first main surface 1 to the second main surface 2, the first flat surface 81 is provided between the second flat surface 82 and the protrusion 60.

[0045] The point on the convex surface 66 that is the greatest distance from the first flat surface 81 and the second flat surface 82 in the third direction 103 is defined as the vertex 61. The vertex 61 is the vertex of the protrusion 60. The height D1 of the protrusion 60 is, for example, 5 μm or more, and there is no particular upper limit to the height D1. The height D1 is the distance in the third direction 103 between the vertex 61 and the first flat surface 81 and the second flat surface 82.

[0046] 3, the second major surface 2 has a concave surface 69 and a third flat surface 83. The concave surface 69 is opposite the protrusion 60. The concave surface 69 is opposite the first flat surface 81. From another perspective, the first flat surface 81 is the portion of the first major surface 1 opposite the concave surface 69.

[0047] An imaginary straight line 99 that passes through the vertex 61 and extends along the third direction 103 passes through the concave surface 69. When viewed in the third direction 103, the concave surface 69 surrounds the imaginary straight line 99. In a cross section parallel to each of the third direction 103 and the radial direction, the concave surface 69 is inclined in the third direction 103 with respect to the radial direction. The concave surface 69 forms a recess 67. A depth D2 of the concave surface 69 in the third direction 103 may be greater than a height D1 of the protrusion 60.

[0048] 3, in a cross section parallel to both the third direction 103 and the radial direction, the width of the concave surface 69 in the radial direction is defined as a second width F2. The second width F2 is greater than the first width F1. The value obtained by dividing the second width F2 by the first width F1 is, for example, 10 to 1000. The second width F2 is, for example, 5 mm. The second width F2 may be, for example, 1 mm to 20 mm.

[0049] The third flat surface 83 is continuous with the concave surface 69. The third flat surface 83 extends along each of the first direction 101 and the second direction 102. The third flat surface 83 is opposite the second flat surface 82. From another perspective, the second flat surface 82 is a portion of the first main surface 1 opposite the third flat surface 83. The concave surface 69 is inclined in the third direction 103 with respect to the third flat surface 83. In a cross section perpendicular to the radial direction and parallel to the third direction 103, the concave surface 69 is concave along the third direction 103.

[0050] <LTV of Silicon Carbide Epitaxial Substrate> Next, a description will be given of a method for measuring the LTV (Local Thickness Variation) of silicon carbide epitaxial substrate 100. The LTV can be measured using, for example, a "Tropel FlatMaster (trademark)" manufactured by Corning Tropel.

[0051] FIG. 4 is a plan view schematic diagram showing the LTV measurement region. For ease of explanation, protrusions 60 are indicated by black circles in FIG. 4 . As shown in FIG. 4 , central region 12 of silicon carbide epitaxial substrate 100 is divided into a plurality of square regions 50. When viewed along a line perpendicular to first main surface 1, each of the plurality of square regions 50 is substantially square in shape. The length of one side of each of the plurality of square regions 50 is set to a first length C1. First length C1 is 10 mm. The maximum diameter W of first main surface 1 (see FIG. 1 ) is, for example, 150 mm. First, a 150 mm × 150 mm square circumscribing outer peripheral side surface 9 is assumed. The 150 mm × 150 mm square is divided into 10 mm × 10 mm square regions (15 × 15 = 225).

[0052] When viewed along a line perpendicular to the first main surface 1, the number of square regions 50 within the central region 12 is, for example, 141. When viewed along a line perpendicular to the first main surface 1, a square region that intersects with the boundary between the peripheral region 11 and the central region 12 is missing a portion and is not a complete square region. Therefore, the square region that intersects with the boundary between the peripheral region 11 and the central region 12 is not considered to be a square region 50 that constitutes the central region 12. When viewed along a line perpendicular to the first main surface 1, one side of each of the multiple square regions 50 is parallel to the extension direction of the orientation flat portion 7. The LTV is measured in each of the multiple square regions 50.

[0053] The plurality of square regions 50 are composed of a first square region 51 and a plurality of second square regions 52. The first square region 51 is the square region 50 closest to the protrusion 60. Specifically, the square region 50 closest to the vertex 61 (see FIG. 3 ) of the protrusion 60 when viewed along a line perpendicular to the first main surface 1 is defined as the first square region 51. When the vertex 61 is inside one of the plurality of square regions 50 when viewed along a line perpendicular to the first main surface 1, the square region 50 in which the vertex 61 is located is defined as the first square region 51. Note that when there are a plurality of protrusions on the first main surface 1, the protrusion with the highest height D1 is identified as the above-mentioned protrusion 60.

[0054] The first square region 51 may include at least a part of the first flat surface 81 (see FIG. 3 ). The first square region 51 may include at least a part of the convex surface 66 (see FIG. 3 ). In FIG. 4 , the hatched region indicates the first square region 51.

[0055] The second square regions 52 are square regions 50 other than the first square region 51. The number of the second square regions 52 is, for example, 140. The second square regions 52 are contiguous to the first square region 51.

[0056] Next, the definition of LTV will be explained. Fig. 5 is a schematic diagram for explaining the definition of LTV.

[0057] LTV=|T1-T2| (Formula 1) LTV is measured, for example, by the following procedure. First, silicon carbide epitaxial substrate 100 is prepared. Either first main surface 1 or second main surface 2 is used as attraction surface B to be attracted to a flat chuck surface. The surface opposite to attraction surface B is used as measurement surface A.

[0058] The entire chucking surface B is chucked onto the chuck surface. Next, an image of the measurement surface A, which is located opposite the chucking surface B, is optically acquired. As shown in FIG. 5 and Equation 1, the LTV is the value obtained by subtracting the height from the chucking surface B to the lowest point P2 of the measurement surface A (minimum height T2) from the height from the chucking surface B to the highest point P1 of the measurement surface A (maximum height T1) when the chucking surface B is entirely chucked onto the flat chuck surface. In other words, the LTV is the value obtained by subtracting the shortest distance between the measurement surface A and the chucking surface B from the longest distance between the measurement surface A and the chucking surface B in a direction perpendicular to the chucking surface B. In other words, the LTV is the distance between a plane (first plane L1) that passes through the highest point P1 and is parallel to the chucking surface B and a plane (second plane L2) that passes through the lowest point P2 and is parallel to the chucking surface B.

[0059] The maximum value of the LTV in the plurality of square regions 50 is 2 μm or less. The maximum value of the LTV in the plurality of square regions 50 may be, for example, 1.5 μm or less, 1.3 μm or less, or 1.1 μm or less. The maximum value of the LTV in the plurality of square regions 50 may be, for example, 0.1 μm or more, or 0.5 μm or more.

[0060] The LTV of the first square region 51 is 2 μm or less. The LTV of the first square region 51 may be, for example, 1.5 μm or less, 1.3 μm or less, or 1.1 μm or less. The LTV of the first square region 51 may be, for example, 0.1 μm or more, or 0.5 μm or more.

[0061] The LTV of each of the second square regions 52 is, for example, not less than 0.1 μm and not more than 1.0 μm. The LTV of the first square region 51 is greater than the LTV of each of the second square regions 52. From another perspective, among the multiple square regions 50, the first square region 51 is the square region 50 with the largest LTV.

[0062] (Apparatus for Manufacturing Silicon Carbide Epitaxial Substrate) Next, the configuration of an apparatus for manufacturing silicon carbide epitaxial substrate 100 will be described. FIG. 6 is a partial cross-sectional schematic diagram showing the configuration of an apparatus for manufacturing silicon carbide epitaxial substrate 100. Apparatus 200 for manufacturing silicon carbide epitaxial substrate 100 is, for example, a hot-wall horizontal CVD (Chemical Vapor Deposition) apparatus. As shown in FIG. 6, apparatus 200 for manufacturing silicon carbide epitaxial substrate 100 mainly includes a reaction chamber 201, a gas supply unit 235, a control unit 245, a heating element 203, a quartz tube 204, a heat insulating material (not shown), and an induction heating coil (not shown).

[0063] The heating element 203 has, for example, a cylindrical shape, and defines a reaction chamber 201 therein. The heating element 203 is made of, for example, graphite. The heating element 203 is provided inside a quartz tube 204. A heat insulating material surrounds the outer periphery of the heating element 203. The induction heating coil is wound, for example, along the outer periphery of the quartz tube 204. The induction heating coil is configured so that an alternating current can be supplied to it from an external power source (not shown). This causes the heating element 203 to be induction heated. As a result, the reaction chamber 201 is heated by the heating element 203.

[0064] The reaction chamber 201 is a space surrounded by an inner wall surface 205 of a heating element 203. A susceptor 210 that holds a silicon carbide substrate 30 is provided in the reaction chamber 201. The susceptor 210 is made of silicon carbide. The silicon carbide substrate 30 is placed on the susceptor 210. The susceptor 210 is placed on a stage 202. The stage 202 is rotatably supported by a rotation shaft 209. The rotation of the stage 202 causes the susceptor 210 to rotate.

[0065] Manufacturing apparatus 200 for silicon carbide epitaxial substrate 100 further includes gas inlet 207 and gas outlet 208. Gas outlet 208 is connected to an exhaust pump (not shown). Arrows in FIG. 6 indicate the flow of gas. Gas is introduced into reaction chamber 201 from gas inlet 207 and exhausted from gas exhaust outlet 208. The pressure inside reaction chamber 201 is adjusted by balancing the amount of gas supplied and the amount of gas exhausted.

[0066] The gas supply unit 235 is configured to be able to supply a mixed gas containing a source gas, a dopant gas, and a carrier gas to the reaction chamber 201. Specifically, the gas supply unit 235 includes, for example, a first gas supply unit 231, a second gas supply unit 232, a third gas supply unit 233, and a fourth gas supply unit 234.

[0067] The first gas supply unit 231 is configured to be able to supply a first gas containing, for example, carbon (C) atoms. The first gas supply unit 231 is, for example, a gas cylinder filled with the first gas. The first gas is, for example, propane (C3H8) gas. The first gas may also be, for example, methane (CH4) gas, ethane (C2H6) gas, acetylene (C2H2) gas, etc.

[0068] The second gas supply unit 232 is configured to be able to supply a second gas containing, for example, silane (SiH) gas. The second gas supply unit 232 is, for example, a gas cylinder filled with the second gas. The second gas is, for example, silane gas. The second gas may be a mixed gas of silane gas and a gas other than silane.

[0069] The third gas supply unit 233 is configured to be able to supply a third gas containing, for example, nitrogen atoms. The third gas supply unit 233 is, for example, a gas cylinder filled with the third gas. The third gas is a doping gas. The third gas is, for example, ammonia gas. Ammonia gas is more susceptible to thermal decomposition than nitrogen gas, which has a triple bond.

[0070] The fourth gas supply unit 234 is configured to be able to supply a fourth gas (carrier gas) such as hydrogen. The fourth gas supply unit 234 is, for example, a gas cylinder filled with hydrogen. The fourth gas supply unit 234 may also be, for example, a gas cylinder filled with argon.

[0071] The control unit 245 is configured to be able to control the flow rate of the mixed gas supplied from the gas supply unit 235 to the reaction chamber 201. Specifically, the control unit 245 may include a first gas flow rate control unit 241, a second gas flow rate control unit 242, a third gas flow rate control unit 243, and a fourth gas flow rate control unit 244. Each control unit may be, for example, an MFC (Mass Flow Controller). The control unit 245 is disposed between the gas supply unit 235 and the gas inlet 207.

[0072] <Method for Manufacturing Silicon Carbide Epitaxial Substrate> Next, a method for manufacturing silicon carbide epitaxial substrate 100 according to this embodiment will be described. Fig. 7 is a flow chart schematically showing the method for manufacturing silicon carbide epitaxial substrate 100 according to this embodiment. As shown in FIG. 7 , the method for manufacturing silicon carbide epitaxial substrate 100 according to this embodiment mainly includes a step of preparing a first silicon carbide substrate (S10), a step of attaching silicon carbide particles to the first back surface (S20), a step of forming a silicon carbide epitaxial layer on the first silicon carbide substrate (S30), a step of measuring the thickness of the second silicon carbide epitaxial layer (S40), a step of determining the amount of polishing (S50), a step of preparing a second silicon carbide substrate (S60), a step of forming a silicon carbide epitaxial layer on the second silicon carbide substrate (S70), and a step of removing the fourth silicon carbide epitaxial layer by polishing (S80).

[0073] First, a step (S10) of preparing a first silicon carbide substrate is performed. Specifically, an ingot made of a silicon carbide single crystal produced by, for example, sublimation is sliced ​​with a wire saw to prepare a plurality of silicon carbide substrates 30. Each of the plurality of silicon carbide substrates 30 has a diameter of, for example, 100 mm or more. Silicon carbide substrate 30 has a thickness (second thickness H2) of, for example, 200 μm or more and 600 μm or less.

[0074] Of each of the plurality of silicon carbide substrates 30, one silicon carbide substrate 30 is prepared as a first silicon carbide substrate 31. The first silicon carbide substrate 31 is a dummy silicon carbide substrate 30. The first silicon carbide substrate 31 is a silicon carbide substrate 30 different from a second silicon carbide substrate 32 described later.

[0075] Next, a step (S20) of adhering silicon carbide particles to the first rear surface is carried out. Fig. 8 is a cross-sectional schematic diagram showing the step (S20) of adhering silicon carbide particles to the first rear surface. As shown in Fig. 8, first silicon carbide substrate 31 has first rear surface 62 and first front surface 63. First surface 63 is opposite first rear surface 62.

[0076] As shown in Fig. 8 , silicon carbide particles 90 are attached to first back surface 62. Specifically, silicon carbide particles 90 are attached to second main surface 2 using, for example, tweezers. Silicon carbide particles 90 have a diameter of, for example, about 20 µm. Silicon carbide particles 90 adhere to, for example, the vicinity of the center of second main surface 2.

[0077] Next, the step (S30) of forming a silicon carbide epitaxial layer on the first silicon carbide substrate is carried out. FIG. 9 is a cross-sectional schematic view showing the step (S30) of forming a silicon carbide epitaxial layer on the first silicon carbide substrate. First silicon carbide substrate 31 is placed on susceptor 210 of manufacturing apparatus 200 (see FIG. 6 ) for silicon carbide epitaxial substrate 100. Specifically, first silicon carbide substrate 31 is placed on susceptor 210 so that first back surface 62 is in contact with susceptor 210. Next, reaction chamber 201 is depressurized. Specifically, the pressure in reaction chamber 201 is reduced from atmospheric pressure to, for example, 1×10 -6 The pressure is reduced to about 100 Pa. Next, the temperature of the first silicon carbide substrate 31 starts to increase. During the temperature increase, hydrogen (H 2 ) gas, which is a carrier gas, is introduced into the reaction chamber 201 from the fourth gas supply unit 234.

[0078] A buffer layer 41 is formed on the first surface 63. Specifically, a source gas, a dopant gas, and a carrier gas are supplied to the reaction chamber 201. More specifically, a mixed gas containing, for example, silane, propane, ammonia, and hydrogen is introduced into the reaction chamber 201. In the reaction chamber 201, each gas is thermally decomposed.

[0079] In the step of forming buffer layer 41 on first surface 63, the flow rate of the first gas (propane gas) is, for example, 29 sccm. The flow rate of the second gas (silane gas) is, for example, 46 sccm. The flow rate of the third gas (ammonia gas) is, for example, 1.5 sccm. The flow rate of the fourth gas (hydrogen gas) is, for example, 100 slm. The pressure inside reaction chamber 201 is maintained, for example, at least 2 kPa and not more than 6 kPa. The growth temperature is, for example, at least 1500°C and not more than 1700°C. As a result, buffer layer 41 is formed on first surface 63 as shown in FIG. 9 . The thickness of buffer layer 41 in third direction 103 is, for example, 5 μm or more.

[0080] Next, a drift layer 42 is formed on the buffer layer 41. In the step of forming the drift layer 42 on the buffer layer 41, the flow rate of the first gas (propane gas) is, for example, 29 sccm. The flow rate of the second gas (silane gas) is, for example, 46 sccm. The flow rate of the third gas (ammonia gas) is, for example, 1.5 sccm. The flow rate of the fourth gas (hydrogen gas) is, for example, 100 slm. The growth temperature is, for example, 1500°C or higher and 1700°C or lower.

[0081] Buffer layer 41 and drift layer 42 constitute first silicon carbide epitaxial layer 71. In this manner, first silicon carbide epitaxial layer 71 in contact with first surface 63 is formed. The step flow growth direction (off-direction of first main surface 1) of first silicon carbide epitaxial layer 71 is, for example, first direction 101. The configuration of first silicon carbide epitaxial layer 71 is substantially the same as the configuration of silicon carbide epitaxial layer 40.

[0082] 9 , a step of forming buffer layer 41 on first surface 63 and a step of forming drift layer 42 on buffer layer 41 are performed, thereby forming second silicon carbide epitaxial layer 72 in contact with first back surface 62 and silicon carbide particles 90. Second silicon carbide epitaxial layer 72 is formed, for example, by sublimating a portion of silicon carbide susceptor 210 (see FIG. 6 ) and depositing it on second main surface 2 of silicon carbide substrate 30. The step flow growth direction of second silicon carbide epitaxial layer 72 is, for example, the direction opposite to first direction 101. The thickness of second silicon carbide epitaxial layer 72 in third direction 103 is set to a third thickness H3.

[0083] A triangular defect 91 is present in second silicon carbide epitaxial layer 72. In the process of forming second silicon carbide epitaxial layer 72, triangular defect 91 is formed starting from silicon carbide particle 90. The polytype of silicon carbide constituting triangular defect 91 is, for example, 3C. Triangular defect 91 has a bottom surface portion 92. Bottom surface portion 92 is connected to silicon carbide particle 90. Bottom surface portion 92 is located on the basal plane. Bottom surface portion 92 is inclined with respect to first back surface 62 in a direction opposite to third direction 103. The inclination angle of first back surface 62 with respect to bottom surface portion 92 is an off angle θ.

[0084] FIG. 10 is a schematic bottom view illustrating the configuration of a triangular defect 91. As shown in FIG. 10 , the triangular defect 91 has a first side 95, a second side 96, and a bottom 94. The second side 96 is continuous with the first side 95. The boundary between the second side 96 and the first side 95 is an end point 93. From another perspective, the first side 95 and the second side 96 branch into two at the end point 93. The bottom 94 is located in the direction opposite the first direction 101 with respect to the end point 93. The bottom 94 is continuous with each of the first side 95 and the second side 96. The first side 95 is continuous with one end (first end) of the bottom 94, and the second side 96 is continuous with the other end (second end) of the bottom 94.

[0085] When viewed along the third direction 103, the first side portion 95 is inclined with respect to each of the first direction 101 and the second direction 102. The first side portion 95 may be inclined from a straight line parallel to the first direction 101 toward the second direction 102. The second side portion 96 may be inclined from a straight line parallel to the first direction 101 in a direction opposite to the second direction 102. When viewed along the third direction 103, the base portion 94 extends along the second direction 102. When viewed along the third direction 103, the width of the triangular defect 91 in the second direction 102 may increase from the end point 93 toward the base portion 94.

[0086] When viewed along third direction 103, the length of triangular defect 91 in the step flow growth direction of second silicon carbide epitaxial layer 72 (the direction opposite to first direction 101) is defined as second length C2. Second length C2 is the maximum distance between end point 93 and base 94 in first direction 101.

[0087] H3 = C2 × tan θ (Equation 2) Next, a step (S40) of measuring the thickness of the second silicon carbide epitaxial layer is performed. Specifically, first, second length C2 is measured. In measuring second length C2, for example, a confocal scanning device is used. As the confocal scanning device, for example, a WASAVI series "SICA 6X" manufactured by Lasertec Corporation can be used. The magnification of the objective lens is, for example, 10x. Based on the measured second length C2, third thickness H3 is calculated using Equation 2. In this way, the thickness (third thickness H3) of second silicon carbide epitaxial layer 72 is measured using triangular defect 91.

[0088] The thickness of the fourth silicon carbide epitaxial layer 74 is smaller than the thickness of the silicon carbide epitaxial layer 40. Therefore, it is difficult to measure the thickness of the fourth silicon carbide epitaxial layer 74 using a measurement method such as a Fourier Transform InfraRed spectrometer (FTIR).

[0089] Next, a polishing amount determining step (S50) is performed. A back surface polishing amount H4 is determined based on the third thickness H3 measured in the second silicon carbide epitaxial layer thickness measuring step (S40). The back surface polishing amount H4 is the amount by which fourth silicon carbide epitaxial layer 74 and second silicon carbide substrate 32 are polished in a fourth silicon carbide epitaxial layer removing step (S80) described below.

[0090] The third thickness H3 may be, for example, less than 1 μm. When the third thickness H3 is less than 1 μm, the back surface polishing amount H4 may be, for example, 9 μm. When the third thickness H3 is less than 1 μm, the back surface polishing amount H4 may be, for example, 8.5 μm or more and 12.5 μm or less. When the third thickness H3 is less than 1 μm, the back surface polishing amount H4 may be, for example, 9 μm or more, or 9.5 μm or more. When the third thickness H3 is less than 1 μm, the back surface polishing amount H4 may be, for example, 11 μm or less, or 10 μm or less.

[0091] The third thickness H3 may be, for example, 1 μm or more and 2 μm or less. When the third thickness H3 is 1 μm or more and 2 μm or less, the back surface polishing amount H4 may be, for example, 13.5 μm. When the third thickness H3 is 1 μm or more and 2 μm or less, the back surface polishing amount H4 may be, for example, 11 μm or more and 16.5 μm or less. When the third thickness H3 is 1 μm or more and 2 μm or less, the back surface polishing amount H4 may be, for example, 11.5 μm or more, or 12 μm or more. When the third thickness H3 is 1 μm or more and 2 μm or less, the back surface polishing amount H4 may be, for example, 15 μm or less, or 14 μm or more.

[0092] Next, the step (S60) of preparing a second silicon carbide substrate is performed. Specifically, one silicon carbide substrate 30 of the plurality of silicon carbide substrates 30 fabricated in the step (S10) of preparing a first silicon carbide substrate is prepared as second silicon carbide substrate 32. The configuration of second silicon carbide substrate 32 is substantially the same as the configuration of first silicon carbide substrate 31. Second silicon carbide substrate 32 is epitaxially grown under the same growth conditions as in the step (S30) of forming a silicon carbide epitaxial layer on the first silicon carbide substrate, and may be a silicon carbide substrate 30 used for epitaxial growth in a separate batch from the step (S30) of forming a silicon carbide epitaxial layer on the first silicon carbide substrate.

[0093] Next, the step (S70) of forming a silicon carbide epitaxial layer on the second silicon carbide substrate is performed. Figure 11 is a cross-sectional schematic view showing the step (S70) of forming a silicon carbide epitaxial layer on the second silicon carbide substrate. As shown in Figure 11, second silicon carbide substrate 32 has second back surface 64 and second front surface 65. Second surface 65 is opposite second back surface 64. Second back surface 64 corresponds to first back surface 62 (see Figure 9). Second surface 65 corresponds to first surface 63 (see Figure 9).

[0094] In the step (S70) of forming a silicon carbide epitaxial layer on the second silicon carbide substrate, a third silicon carbide epitaxial layer 73 and a fourth silicon carbide epitaxial layer 74 are formed under substantially the same conditions as in the step (S30) of forming a silicon carbide epitaxial layer on the first silicon carbide substrate.

[0095] 11 , third silicon carbide epitaxial layer 73 is formed in contact with second surface 65. Third silicon carbide epitaxial layer 73 has buffer layer 41 and drift layer 42. The configuration of third silicon carbide epitaxial layer 73 is substantially the same as the configuration of silicon carbide epitaxial layer 40 (see FIG. 2 ) and first silicon carbide epitaxial layer 71 (see FIG. 9 ).

[0096] 11 , a fourth silicon carbide epitaxial layer 74 is formed in contact with the second back surface 64. The fourth silicon carbide epitaxial layer 74 corresponds to the second silicon carbide epitaxial layer 72 (see FIG. 9 ). The fourth silicon carbide epitaxial layer 74 may not have triangular defects 91. The thickness of the fourth silicon carbide epitaxial layer 74 in the third direction 103 may be substantially the third thickness H3.

[0097] Next, the step (S80) of removing the fourth silicon carbide epitaxial layer by polishing is performed. Figure 12 is a schematic cross-sectional view showing the step (S80) of removing the fourth silicon carbide epitaxial layer by polishing. The portion indicated by the dashed line in Figure 12 shows the state of silicon carbide epitaxial substrate 100 before polishing. The portion indicated by the solid line in Figure 12 shows the state of silicon carbide epitaxial substrate 100 after chemical mechanical polishing. As shown in Figure 12, fourth silicon carbide epitaxial layer 74 and second silicon carbide substrate 32 are mechanically polished.

[0098] Fig. 13 is a cross-sectional schematic diagram showing the configuration of a mechanical polishing apparatus. As shown in Fig. 13, mechanical polishing apparatus 300 has a surface plate 301 and a polishing head 302. As shown in Fig. 13, silicon carbide epitaxial substrate 100 is attached to polishing head 302. First main surface 1 of silicon carbide epitaxial substrate 100 contacts polishing head 302. Fourth silicon carbide epitaxial layer 74 faces surface plate 301. Polishing head 302 is made of, for example, ceramic or stainless steel.

[0099] Slurry 310 is supplied between silicon carbide epitaxial substrate 100 and surface plate 301. Slurry 310 contains, for example, abrasive grains 312. Abrasive grains 312 are, for example, diamond or cubic boron nitride (cBN). Abrasive grains 312 have a diameter of, for example, 1 μm or more and 3 μm or less.

[0100] Platen 301 rotates. Polishing head 302 presses silicon carbide epitaxial substrate 100 against platen 301. This mechanically polishes fourth silicon carbide epitaxial layer 74 and second silicon carbide substrate 32. As a result, fourth silicon carbide epitaxial layer 74 is removed. The amount of polishing in the mechanical polishing is, for example, not less than 7 μm and not more than 16.5 μm.

[0101] Next, chemical mechanical polishing is performed. Specifically, silicon carbide epitaxial substrate 100 is placed so that second back surface 64 faces a polishing cloth (not shown). A polishing liquid (not shown) is supplied between second back surface 64 and the polishing cloth. The polishing liquid contains, for example, abrasive grains and an oxidizer. The abrasive grains are, for example, colloidal silica, fumed silica, alumina, or the like. The oxidizer is, for example, hydrogen peroxide solution.

[0102] The polishing cloth is rotated. Second back surface 64 is pressed against the polishing cloth. This causes second silicon carbide substrate 32 to be chemically mechanically polished. As a result, the portion of second silicon carbide substrate 32 that has been damaged by mechanical polishing is removed. The amount of polishing in the chemical mechanical polishing is, for example, not less than 0.05 μm and not more than 1 μm.

[0103] 12 , the sum of the amount polished by mechanical polishing and the amount polished by chemical mechanical polishing is the back surface polishing amount H4. From another perspective, the back surface polishing amount H4 is the sum of the amount of fourth silicon carbide epitaxial layer 74 removed and the amount of second silicon carbide substrate 32 removed. After the step (S80) of removing the fourth silicon carbide epitaxial layer by polishing, the thickness of second silicon carbide substrate 32 in third direction 103 is second thickness H2. After the step (S80) of removing the fourth silicon carbide epitaxial layer by polishing, silicon carbide epitaxial substrate 100 may be cleaned using a cleaning liquid such as pure water, an acid, or an alkali. In this manner, silicon carbide epitaxial substrate 100 according to this embodiment is manufactured.

[0104] The correspondence between silicon carbide epitaxial substrate 100 shown in Fig. 12 and silicon carbide epitaxial substrate 100 shown in Fig. 2 will be described. Second silicon carbide substrate 32 corresponds to silicon carbide substrate 30. Third silicon carbide epitaxial layer 73 corresponds to silicon carbide epitaxial layer 40. Second back surface 64 corresponds to second main surface 2. Second front surface 65 corresponds to third main surface 3.

[0105] In the above, the step (S30) of forming a silicon carbide epitaxial layer on the first silicon carbide substrate is followed by the step (S70) of forming a silicon carbide epitaxial layer on the second silicon carbide substrate. From another perspective, in the step (S70) of forming a silicon carbide epitaxial layer on the second silicon carbide substrate, epitaxial growth is performed on a batch separate from that performed in the step (S30) of forming a silicon carbide epitaxial layer on the first silicon carbide substrate. However, the configuration of the method for manufacturing silicon carbide epitaxial substrate 100 according to the present disclosure is not limited to the above configuration.

[0106] Specifically, the step (S30) of forming a silicon carbide epitaxial layer on the first silicon carbide substrate and the step (S70) of forming a silicon carbide epitaxial layer on the second silicon carbide substrate may be performed by epitaxial growth of the same batch. From another perspective, the step (S60) of preparing a second silicon carbide substrate may be performed simultaneously with the step (S10) of preparing a first silicon carbide substrate. The step (S70) of forming a silicon carbide epitaxial layer on the second silicon carbide substrate may be performed simultaneously with the step (S30) of forming a silicon carbide epitaxial layer on the first silicon carbide substrate.

[0107] (Method of manufacturing silicon carbide semiconductor device) Next, a method of manufacturing silicon carbide semiconductor device 400 according to this embodiment will be described. Fig. 14 is a flow diagram that schematically shows the method of manufacturing silicon carbide semiconductor device 400 according to this embodiment. As shown in Fig. 14, the method of manufacturing silicon carbide semiconductor device 400 according to this embodiment mainly includes a step (S1) of preparing silicon carbide epitaxial substrate 100 and a step (S2) of processing silicon carbide epitaxial substrate 100.

[0108] First, a step (S1) is performed of preparing silicon carbide epitaxial substrate 100. Fig. 15 is a cross-sectional schematic view showing the step of preparing silicon carbide epitaxial substrate 100. As shown in Fig. 15, in the step (S1) of preparing silicon carbide epitaxial substrate 100, silicon carbide epitaxial substrate 100 according to the present embodiment is prepared (see Figs. 1 and 2).

[0109] Next, a step (S2) is performed of processing silicon carbide epitaxial substrate 100. Specifically, silicon carbide epitaxial substrate 100 is processed as follows: First, ions are implanted into silicon carbide epitaxial substrate 100.

[0110] 16 is a schematic cross-sectional view showing a step of forming a body region. In the step of forming the body region, p-type impurities such as aluminum are ion-implanted into second main surface 2 of silicon carbide epitaxial layer 40. This forms body region 113 having p-type conductivity. Portions where body region 113 is not formed become drift layer 42 and buffer layer 41. The thickness of body region 113 is, for example, 0.9 μm. Silicon carbide epitaxial layer 40 includes buffer layer 41, drift layer 42, and body region 113.

[0111] Next, a step of forming a source region is performed. FIG. 17 is a schematic cross-sectional view showing the step of forming the source region. Specifically, n-type impurities such as phosphorus are ion-implanted into the body region 113. This forms a source region 114 having n-type conductivity. The thickness of the source region 114 is, for example, 0.4 μm. The concentration of the n-type impurities in the source region 114 is higher than the concentration of the p-type impurities in the body region 113.

[0112] Next, a p-type impurity such as aluminum is ion-implanted into the source region 114 to form a contact region 118. The contact region 118 is formed to penetrate the source region 114 and the body region 113 and to be in contact with the drift layer 42. The concentration of the p-type impurity in the contact region 118 is higher than the concentration of the n-type impurity in the source region 114.

[0113] Next, activation annealing is performed to activate the implanted impurities. The temperature of the activation annealing is, for example, 1500° C. or higher and 1900° C. or lower. The activation annealing time is, for example, about 30 minutes. The atmosphere of the activation annealing is, for example, an argon atmosphere.

[0114] Next, a step of forming trenches in first main surface 1 of silicon carbide epitaxial layer 40 is performed. FIG. 18 is a cross-sectional schematic diagram showing the step of forming trenches in first main surface 1 of silicon carbide epitaxial layer 40. A mask 117 having openings is formed on first main surface 1 including source region 114 and contact region 118. Using mask 117, source region 114, body region 113, and a portion of drift layer 42 are removed by etching. As an etching method, for example, inductively coupled plasma reactive ion etching can be used. Specifically, for example, inductively coupled plasma reactive ion etching using SF or a mixed gas of SF and O as a reactive gas is used. A recess is formed in first main surface 1 by etching.

[0115] Next, thermal etching is performed on the recesses. Thermal etching can be performed, for example, by heating the first main surface 1 with the mask 117 formed thereon in an atmosphere containing a reactive gas having at least one type of halogen atom. The at least one type of halogen atom includes at least one of chlorine (Cl) atoms and fluorine (F) atoms. The atmosphere can include, for example, Cl2, BCl3, SF6, or CF4. For example, thermal etching is performed using a mixed gas of chlorine gas and oxygen gas as the reactive gas, with the heat treatment temperature set to, for example, 700°C or higher and 1000°C or lower. The reactive gas may contain a carrier gas in addition to the above-mentioned chlorine gas and oxygen gas. Examples of the carrier gas that can be used include nitrogen gas, argon gas, and helium gas.

[0116] 18 , a trench 56 is formed in the first main surface 1 by thermal etching. The trench 56 is defined by a sidewall surface 53 and a bottom wall surface 54. The sidewall surface 53 is formed by the source region 114, the body region 113, and the drift layer 42. The bottom wall surface 54 is formed by the drift layer 42. Next, the mask 117 is removed from the first main surface 1.

[0117] Next, a step of forming a gate insulating film is performed. FIG. 19 is a schematic cross-sectional view showing the step of forming a gate insulating film. Specifically, silicon carbide epitaxial substrate 100 having trench 56 formed in first main surface 1 is heated in an oxygen-containing atmosphere at a temperature of, for example, 1300° C. or higher and 1400° C. or lower. This forms gate insulating film 115 that is in contact with drift layer 42 at bottom wall surface 54, in contact with drift layer 42, body region 113, and source region 114 at sidewall surface 53, and in contact with source region 114 and contact region 118 at first main surface 1.

[0118] Next, a step of forming a gate electrode is performed. FIG. 20 is a cross-sectional view showing a step of forming a gate electrode and an interlayer insulating film. The gate electrode 127 is formed inside the trench 56 so as to contact the gate insulating film 115. The gate electrode 127 is disposed inside the trench 56 and is formed on the gate insulating film 115 so as to face each of the sidewall surface 53 and the bottom wall surface 54 of the trench 56. The gate electrode 127 is formed by, for example, a low pressure chemical vapor deposition (LPCVD) method.

[0119] Next, an interlayer insulating film 126 is formed. The interlayer insulating film 126 is formed so as to cover the gate electrode 127 and to be in contact with the gate insulating film 115. The interlayer insulating film 126 is formed by, for example, chemical vapor deposition. The interlayer insulating film 126 is made of, for example, a material containing silicon dioxide. Next, the interlayer insulating film 126 and part of the gate insulating film 115 are etched so as to form openings over the source region 114 and the contact region 118. As a result, the contact region 118 and the source region 114 are exposed from the gate insulating film 115.

[0120] Next, a step of forming a source electrode is performed. The source electrode 116 is formed so as to be in contact with each of the source region 114 and the contact region 118. The source electrode 116 is formed by, for example, a sputtering method. The source electrode 116 is made of a material containing, for example, Ti (titanium), Al (aluminum), and Si (silicon).

[0121] Next, alloying annealing is performed. Specifically, the source electrode 116 in contact with each of the source region 114 and the contact region 118 is maintained at a temperature of, for example, 900° C. or higher and 1100° C. or lower for about 5 minutes. As a result, at least a portion of the source electrode 116 is silicided. This forms the source electrode 116 in ohmic contact with the source region 114. The source electrode 116 may also form an ohmic contact with the contact region 118.

[0122] Next, the source wiring 119 is formed. The source wiring 119 is electrically connected to the source electrode 116. The source wiring 119 is formed so as to cover the source electrode 116 and the interlayer insulating film 126.

[0123] Next, a step of forming a drain electrode is carried out. First, silicon carbide substrate 30 is polished at second main surface 2. This reduces the thickness of silicon carbide substrate 30. Next, drain electrode 123 is formed. Drain electrode 123 is formed so as to be in contact with second main surface 2. In this manner, silicon carbide semiconductor device 400 according to this embodiment is manufactured.

[0124] 21 is a cross-sectional schematic diagram showing the configuration of a silicon carbide semiconductor device 400 according to this embodiment. The silicon carbide semiconductor device 400 is, for example, a MOSFET (Metal Oxide Semiconductor Field Effect Transistor). The silicon carbide semiconductor device 400 mainly includes a silicon carbide epitaxial substrate 100, a gate electrode 127, a gate insulating film 115, a source electrode 116, a drain electrode 123, a source wiring 119, and an interlayer insulating film 126. The silicon carbide epitaxial substrate 100 includes a buffer layer 41, a drift layer 42, a body region 113, a source region 114, and a contact region 118. Silicon carbide semiconductor device 400 may be, for example, an IGBT (Insulated Gate Bipolar Transistor).

[0125] Next, the effects of this embodiment will be described. When forming silicon carbide epitaxial layer 40 on silicon carbide substrate 30, a portion of susceptor 210 made of silicon carbide may sublimate, resulting in the deposition of a silicon carbide layer on the back surface (second main surface 2) of silicon carbide epitaxial substrate 100. In this case, roughness occurs on the back surface, deteriorating the flatness of silicon carbide epitaxial substrate 100. As a result, the yield of silicon carbide semiconductor devices 400 decreases. In order to improve the flatness of silicon carbide epitaxial substrate 100, the back surface of silicon carbide epitaxial substrate 100 may be polished after forming silicon carbide epitaxial layer 40 on silicon carbide substrate 30.

[0126] However, even when silicon carbide semiconductor device 400 is manufactured using silicon carbide epitaxial substrate 100 with its back surface polished, the yield of silicon carbide semiconductor device 400 has sometimes been lower than expected. Specifically, the LTV has sometimes been larger than expected in a part of silicon carbide epitaxial substrate 100.

[0127] The inventors focused on the amount of polishing when polishing the back surface of silicon carbide epitaxial substrate 100. FIG. 22 is a schematic cross-sectional view showing a state in which protrusion 60 is in contact with polishing head 302. In the manufacture of silicon carbide epitaxial substrate 100, protrusion 60 may be formed on the front surface (first main surface 1) of silicon carbide epitaxial substrate 100. In this case, as shown in FIG. 22 , protrusion 60 comes into contact with polishing head 302 in the step (S80) of removing the fourth silicon carbide epitaxial layer by polishing. Therefore, the portion of the back surface of silicon carbide epitaxial substrate 100 opposite protrusion 60 approaches surface plate 301. The pressure received from surface plate 301 by the portion of the back surface opposite protrusion 60 is greater than the pressure received from surface plate 301 by other portions of the back surface. As a result, the amount of polishing of the portion of the back surface opposite protrusion 60 is greater than the amount of polishing of other portions of the back surface. In particular, if the amount of back surface polishing H4 is excessively large, the difference between the amount of polishing of the portion of the back surface opposite protrusion 60 and the amount of polishing of the other portion of the back surface becomes excessively large, resulting in a deterioration in the flatness of silicon carbide epitaxial substrate 100.

[0128] Fig. 23 is a schematic diagram showing the measurement results of the LTV of each of a plurality of square regions 50 after the step (S70) of forming a silicon carbide epitaxial layer on the second silicon carbide substrate and before the step (S80) of removing the fourth silicon carbide epitaxial layer by polishing. Fig. 24 is a schematic diagram showing the measurement results of the LTV of each of a plurality of square regions 50 after the step (S80) of removing the fourth silicon carbide epitaxial layer by polishing. In the production of silicon carbide epitaxial substrate 100 shown in Fig. 24, the back surface polishing amount H4 was set to 20 µm.

[0129] In silicon carbide epitaxial substrate 100 shown in Fig. 23, the maximum LTV was 1.8 µm. In silicon carbide epitaxial substrate 100 shown in Fig. 23, the maximum LTV was 5.1 µm. As shown in Fig. 23 and Fig. 24, when backside polishing amount H4 is excessively large, the LTV may deteriorate in part of silicon carbide epitaxial substrate 100.

[0130] On the other hand, if the amount of back surface polishing H4 is excessively small, the layer (fourth silicon carbide epitaxial layer 74) deposited on the back surface of silicon carbide epitaxial substrate 100 may not be sufficiently removed. In this case, the flatness of silicon carbide epitaxial substrate 100 is not sufficiently improved. Therefore, it is desirable to set a suitable amount of back surface polishing H4 based on the thickness of fourth silicon carbide epitaxial layer 74.

[0131] According to the method for manufacturing silicon carbide epitaxial substrate 100 of this embodiment, silicon carbide particles 90 are attached to first back surface 62 of first silicon carbide substrate 31. In the step (S30) of forming a silicon carbide epitaxial layer on first silicon carbide substrate 31, triangular defects 91 are formed in second silicon carbide epitaxial layer 72, starting from silicon carbide particles 90. Thickness H3 of second silicon carbide epitaxial layer 72 is measured using triangular defects 91 in second silicon carbide epitaxial layer 72. A back surface polishing amount H4 is determined based on the measured thickness H3 of second silicon carbide epitaxial layer 72. Fourth silicon carbide epitaxial layer 74 is removed by polishing based on back surface polishing amount H4. Therefore, back surface polishing amount H4 can be determined substantially based on the thickness of fourth silicon carbide epitaxial layer 74. This can improve the flatness of silicon carbide epitaxial substrate 100. As a result, the yield of silicon carbide semiconductor devices 400 can be improved.

[0132] According to the silicon carbide epitaxial substrate 100 of this embodiment, there is a protrusion 60 on the first main surface 1. The plurality of square regions 50 is composed of a first square region 51 that is closest to the protrusion 60 and a second square region 52 that is a plurality of square regions 50 other than the first square region 51. The LTV of the first square region 51 is larger than the LTV of each of the plurality of square regions 50 that make up the second square region 52. The LTV of the first square region 51 is 2 μm or less. In this way, the flatness is improved even in the silicon carbide epitaxial substrate 100 having the protrusion 60. This enables the yield of the silicon carbide semiconductor device 400 to be improved.

[0133] In silicon carbide epitaxial substrate 100 according to this embodiment, second main surface 2 is a polished surface. The maximum value of LTV in a plurality of square regions 50 is 2 μm or less. In this manner, flatness is improved in silicon carbide epitaxial substrate 100 whose back surface (second main surface 2) is polished. This enables the yield of silicon carbide semiconductor devices 400 to be improved.

[0134] <Sample Preparation> Silicon carbide epitaxial substrates 100 according to Samples 1 to 22 were prepared. Silicon carbide epitaxial substrates 100 according to Samples 1 to 4, 11, 21, and 22 are comparative examples. Silicon carbide epitaxial substrates 100 according to Samples 5 to 10 and 12 to 20 are examples. The diameter (maximum diameter W) of silicon carbide epitaxial substrates 100 according to Samples 1 to 22 was set to 150 mm.

[0135] Silicon carbide epitaxial substrates 100 according to Samples 1 to 22 were manufactured according to the manufacturing method shown in Fig. 7. In the process of manufacturing silicon carbide epitaxial substrates 100 according to Samples 1 to 22, third thickness H3 was measured according to the method described above. A WASAVI series "SICA 6X" manufactured by Lasertec Corporation was used to measure third thickness H3.

[0136] In silicon carbide epitaxial substrates 100 according to Samples 1 to 11, third thickness H3 was less than 1 μm. In silicon carbide epitaxial substrates 100 according to Samples 12 to 22, third thickness H3 was not less than 1 μm and not more than 2 μm.

[0137] The amount H4 of back surface polishing was changed in the production of silicon carbide epitaxial substrates 100 according to Samples 1 to 22. Specifically, the amount H4 of back surface polishing was set to 6.5 μm or more and 21 μm or less in the production of silicon carbide epitaxial substrates 100 according to Samples 1 to 11. The amount H4 of back surface polishing was set to 11 μm or more and 18 μm or less in the production of silicon carbide epitaxial substrates 100 according to Samples 12 to 22.

[0138] (Measurement Method) In silicon carbide epitaxial substrates 100 according to Samples 1 to 22, the maximum value of LTV in a plurality of square regions 50 was measured using a "Tropel FlatMaster (trademark)" manufactured by Corning Tropel. The length of one side of each of the plurality of square regions 50 (first length C1) was set to 10 mm. Second main surface 2 was used as adsorption surface B.

[0139] (Measurement results)

[0140]

[0141] Table 1 shows the maximum LTV values ​​for silicon carbide epitaxial substrates 100 in which the third thickness H3 was less than 1 μm. As shown in Table 1, when the third thickness H3 was less than 1.0 μm, the maximum LTV values ​​for silicon carbide epitaxial substrates 100 (samples 5 to 10) in which the backside polishing amount H4 was 8.5 μm or more and 12.5 μm or less were 2.0 μm or less. Specifically, the maximum LTV values ​​for silicon carbide epitaxial substrates 100 in samples 5 to 10 were 1.45 μm or less. On the other hand, when the third thickness H3 was less than 1.0 μm, the maximum LTV values ​​for silicon carbide epitaxial substrates 100 (samples 1 to 4 and 11) in which the backside polishing amount H4 was 6.5 μm or more or 14.5 μm or more were greater than 2.0 μm.

[0142]

[0143] Table 2 shows the maximum LTV values ​​for silicon carbide epitaxial substrates 100 in which the third thickness H3 was 1 μm or more and 2 μm or less. As shown in Table 2, when the third thickness H3 was 1 μm or more and 2 μm or less, the maximum LTV values ​​for silicon carbide epitaxial substrates 100 (samples 12 to 20) in which the backside polishing amount H4 was 11 μm or more and 16.5 μm or less were 2.0 μm or less. Specifically, the maximum LTV values ​​for silicon carbide epitaxial substrates 100 in samples 12 to 20 were 1.7 μm or less. When the third thickness H3 was 1 μm or more and 2 μm or less, the maximum LTV values ​​for silicon carbide epitaxial substrates 100 (samples 12 to 16) in which the backside polishing amount H4 was 11 μm or more and 13.5 μm or less were 1.44 μm or less. On the other hand, when third thickness H3 was 1 μm or more and 2 μm or less, the maximum value of LTV in silicon carbide epitaxial substrates 100 (samples 21 and 22) in which backside polishing amount H4 was 17.5 μm or more was 2.1 μm or more.

[0144] From the above results, it was confirmed that the maximum value of LTV was reduced in silicon carbide epitaxial substrate 100 of the example compared to silicon carbide epitaxial substrate 100 of the comparative example.

[0145] The embodiments and examples disclosed herein are illustrative in all respects and should not be considered limiting. The scope of the present invention is defined by the claims, not by the above-described embodiments, and is intended to include meanings equivalent to the claims and all modifications within the scope thereof.

[0146] REFERENCE SIGNS LIST 1 First main surface, 2 Second main surface, 3 Third main surface, 5 Interface, 6 Outer edge, 7 Orientation flat portion, 8 Arc-shaped portion, 9 Outer peripheral side surface, 11 Outer peripheral region, 12 Central region, 30 Silicon carbide substrate, 31 First silicon carbide substrate, 32 Second silicon carbide substrate, 40 Silicon carbide epitaxial layer, 41 Buffer layer, 42 Drift layer, 50 Square region, 51 First square region, 52 Second square region, 53 Side wall surface, 54 Bottom wall surface, 56 Trench, 60 Protrusion, 61 Vertex, 62 First back surface, 63 First front surface, 64 Second back surface, 65 Second front surface, 66 Convex surface, 67 Concave portion, 69 Concave surface, 71 First silicon carbide epitaxial layer, 72 Second silicon carbide epitaxial layer, 73 Third silicon carbide epitaxial layer, 74 Fourth silicon carbide epitaxial layer, 81 First flat surface, 82 Second flat surface, 83 Third flat surface, 90 Silicon carbide particle, 91 Triangular defect, 92 Bottom surface, 93 End point, 94 Bottom, 95 First side, 96 Second side, 99 Virtual line, 100 Silicon carbide epitaxial substrate, 101 First direction, 102 Second direction, 103 Third direction, 113 Body region, 114 Source region, 115 Gate insulating film, 116 Source electrode, 117 Mask, 118 Contact region, 119 Source wiring, 123 Drain electrode, 126 Interlayer insulating film, 127 Gate electrode (electrode), 200 Manufacturing apparatus, 201 Reaction chamber, 202 Stage, 203 Heating element, 204 Quartz tube, 205 Inner wall surface, 207 gas inlet, 208 gas exhaust port, 209 rotating shaft, 210 susceptor, 231 first gas supply unit, 232 second gas supply unit, 233 third gas supply unit, 234 fourth gas supply unit, 235 gas supply unit, 241 first gas flow rate control unit, 242 second gas flow rate control unit, 243 third gas flow rate control unit, 244 fourth gas flow rate control unit, 245 control unit, 300 mechanical polishing apparatus, 301 surface plate, 302 polishing head, 310 slurry, 312 abrasive grains, 400 silicon carbide semiconductor device, A measurement surface, B suction surface, C1 first length, C2 second length, D1 height, D2 depth, E distance, F1 first width, F2 second width, H1 first thickness, H2 second thickness, H3 third thickness (thickness), H4 Back surface grinding amount (grinding amount), L1 first plane, L2 second plane, O center, P1 highest point, P2 lowest point, T1 highest height, T2 lowest height, W maximum diameter,θ is the off angle.

Claims

1. Silicon carbide substrate and The silicon carbide substrate comprises a silicon carbide epitaxial layer provided on the silicon carbide substrate, The silicon carbide epitaxial layer includes a first main surface opposite the interface between the silicon carbide substrate and the silicon carbide epitaxial layer. On the first main surface, there are protrusions made of silicon carbide, The first main surface is composed of an outer edge, an outer peripheral region which is the area within 3 mm from the outer edge, and a central region surrounded by the outer peripheral region. When the central region is divided into a plurality of square regions with a side length of 10 mm, the plurality of square regions are composed of a first square region closest to the protrusion and a plurality of second square regions which are the plurality of square regions other than the first square region. The LTV of the first square region is greater than the LTV of each of the plurality of second square regions. A silicon carbide epitaxial substrate wherein the LTV of the first square region is 2 μm or less.

2. The silicon carbide epitaxial substrate according to claim 1, wherein the LTV of the first square region is 1.5 μm or less.

3. The silicon carbide epitaxial substrate according to claim 1 or claim 2, wherein the thickness of the silicon carbide epitaxial layer is 10 μm or more and 30 μm or less.

4. Silicon carbide substrate and The silicon carbide substrate comprises a silicon carbide epitaxial layer provided on the silicon carbide substrate, The silicon carbide epitaxial layer includes a first main surface opposite the interface between the silicon carbide substrate and the silicon carbide epitaxial layer. The silicon carbide substrate includes a second main surface opposite to the interface, The second main surface is a polished surface, The first main surface is composed of an outer edge, an outer peripheral region which is the area within 3 mm from the outer edge, and a central region surrounded by the outer peripheral region. When the aforementioned central region is divided into multiple square regions with sides of 10 mm in length, A silicon carbide epitaxial substrate in which the maximum LTV in the aforementioned plurality of square regions is 2 μm or less.

5. The silicon carbide epitaxial substrate according to claim 4, wherein the maximum LTV in the plurality of square regions is 1.5 μm or less.

6. A step of preparing a first silicon carbide substrate including a first back surface and a first front surface opposite the first back surface, The process of attaching silicon carbide particles to the first back surface, The process includes the steps of forming a first silicon carbide epitaxial layer in contact with the first surface and forming a second silicon carbide epitaxial layer in contact with the first back surface and the silicon carbide particles, In the process of forming the first silicon carbide epitaxial layer and the second silicon carbide epitaxial layer, triangular defects are formed in the second silicon carbide epitaxial layer starting from the silicon carbide particles. A step of measuring the thickness of the second silicon carbide epitaxial layer using the triangular defects in the second silicon carbide epitaxial layer, A step of determining the amount of polishing based on the measured thickness of the second silicon carbide epitaxial layer, A step of preparing a second silicon carbide substrate including a second back surface and a second front surface opposite to the second back surface, A step of forming a third silicon carbide epitaxial layer in contact with the second surface and a fourth silicon carbide epitaxial layer in contact with the second back surface, A method for manufacturing a silicon carbide epitaxial substrate, further comprising the step of removing the fourth silicon carbide epitaxial layer by polishing based on the amount of polishing.

7. The thickness of the second silicon carbide epitaxial layer is less than 1 μm. The method for producing a silicon carbide epitaxial substrate according to claim 6, wherein the amount of polishing is 8.5 μm or more and 12.5 μm or less.

8. The thickness of the second silicon carbide epitaxial layer is 1 μm or more and 2 μm or less. The method for producing a silicon carbide epitaxial substrate according to claim 6, wherein the amount of polishing is 11 μm or more and 16.5 μm or less.

9. A step of preparing a silicon carbide epitaxial substrate according to any one of claims 1, 2, 4, and 5, A method for manufacturing a silicon carbide semiconductor device, comprising the step of forming an electrode on the silicon carbide epitaxial layer.