Chip resistor

Abstract

This chip resistor is provided with an insulating substrate, a resistor, a back-surface electrode, and a side-surface electrode. The insulating substrate includes a front surface, a back surface, and a side surface. The resistor is disposed on the back surface. The back-surface electrode is disposed on the back surface. The side-surface electrode is disposed on the side surface and the back-surface electrode. A direction perpendicular to the back surface is defined as a Z direction. The side-surface electrode has a lowermost point. The lowermost point is disposed at a position farthest from the back surface in the Z direction. The side-surface electrode has a lowermost surface. The lowermost surface is a region from the side surface to the lowermost point. The lowermost surface is inclined with respect to the back surface. The lowermost surface has a first region. The first region includes the lowermost point. In the first region, the inclination angle of the lowermost surface with respect to the back surface is 1° or more and 10° or less.

Description

Chip Resistors

[0001] The present disclosure relates to chip resistors.

[0002] Japanese Patent Laid-Open Publication No. 2022-105204 (Patent Document 1) discloses a chip resistor including a substrate, a resistor layer, a protective layer, a conductor layer, a back electrode layer, and a plating layer. The chip resistor is mounted on a wiring board via a conductive bonding material such as solder.

[0003] Japanese Patent Application Laid-Open No. 2022-105204

[0004] [Summary] However, in such chip resistors, there is a risk that cracks may occur in the conductive bonding material between the electrodes and the wiring board due to thermal fatigue caused by temperature cycling.

[0005] A chip resistor according to one aspect of the present disclosure comprises an insulating substrate, a resistor, a back electrode, and a side electrode. The insulating substrate includes a front surface, a back surface, and a side surface. The back surface is located on the opposite side of the front surface. The side surface connects the front surface and the back surface. The resistor is located on at least one of the front surface and the back surface. The back electrode is located on the back surface. The side electrode is located on the side surface and the back surface electrode. The direction perpendicular to the back surface is defined as the Z direction. The side electrode has a lowest point. The lowest point is located at a position farthest from the back surface in the Z direction. The side electrode has a lowest surface. The lowest surface is a region from the side surface to the lowest point. The lowest surface is inclined with respect to the back surface. The lowest surface has a first region. The first region includes the lowest point. In the first region, the inclination angle of the lowest surface with respect to the back surface is greater than or equal to 1° and less than or equal to 10°.

[0006] FIG. 1 is a schematic plan view of a chip resistor according to a first embodiment. FIG. 2 is a schematic cross-sectional view taken along line II-II in FIG. 1 . FIG. 3 is a partially enlarged cross-sectional view of region III in FIG. 2 . FIG. 4 is a partially enlarged cross-sectional view of a modified example of the chip resistor according to the first embodiment. FIG. 5 is a partially enlarged cross-sectional view of a modified example of the chip resistor according to the first embodiment. FIG. 6 is a partial cross-sectional view of a chip resistor according to a comparative example after a temperature cycle test. FIG. 7 is a partial cross-sectional view of a chip resistor according to an example after a temperature cycle test. FIG. 8 is a schematic cross-sectional view of a chip resistor according to a second embodiment. FIG. 9 is a schematic cross-sectional view of a chip resistor according to a third embodiment. FIG. 10 is a schematic cross-sectional view of a chip resistor according to a fourth embodiment. FIG. 11 is a schematic cross-sectional view of a chip resistor according to a fifth embodiment. FIG. 12 is a schematic cross-sectional view of a chip resistor according to a sixth embodiment. FIG. 13 is a schematic cross-sectional view of a chip resistor according to a seventh embodiment. FIG. 14 is a schematic cross-sectional view of a chip resistor according to an eighth embodiment. FIG. 15 is a schematic cross-sectional view of a chip resistor according to a ninth embodiment. Fig. 16 is a schematic cross-sectional view of a chip resistor according to a tenth embodiment. Fig. 17 is a schematic cross-sectional view of a chip resistor according to an eleventh embodiment. Fig. 18 is a schematic cross-sectional view of a chip resistor according to a twelfth embodiment.

[0007] [Detailed Description] The details of the embodiments of the present disclosure will be described with reference to the drawings. In the following drawings, the same or corresponding parts are designated by the same reference numerals, and the description thereof will not be repeated. At least some of the configurations of the embodiments described below may be combined in any manner.

[0008] Embodiment 1. <Configuration of Chip Resistor> Fig. 1 is a schematic plan view of a chip resistor according to embodiment 1. Fig. 2 is a schematic cross-sectional view taken along line II-II in Fig. 1. Fig. 3 is a partially enlarged cross-sectional view of region III in Fig. 2.

[0009] The chip resistor 1a includes an insulating substrate 10, a resistor element 3, an insulating protective film 4, a surface electrode 2a, a back electrode 2b, and a side electrode 5. The insulating substrate 10 is made of, for example, alumina (Al ２ O ３). The insulating substrate 10 includes a front surface 11, a back surface 12, and a side surface 13. The back surface 12 is the surface opposite to the front surface 11. The side surface 13 connects the front surface 11 and the back surface 12. The side surface 13 includes a first side surface 13a and a second side surface 13b. The second side surface 13b is the surface opposite to the first side surface 13a. In other words, the first side surface 13a and the second side surface 13b each connect the front surface 11 and the back surface 12.

[0010] The direction perpendicular to the side surface 13 is defined as the X direction. The direction perpendicular to the front surface 11 and the back surface 12 is defined as the Z direction. The direction perpendicular to both the X direction and the Z direction is defined as the Y direction. The X direction is the longitudinal direction of the insulating substrate 10 in FIG. 2. The Z direction is the thickness direction of the insulating substrate 10. The front surface 11 and the back surface 12 are both end surfaces of the insulating substrate 10 in the thickness direction (Z direction). The back surface 12 is the surface (mounting surface) that faces a circuit board (not shown) when the chip resistor 1a is mounted on the circuit board. The first side surface 13a and the second side surface 13b are both end surfaces of the insulating substrate 10 in the longitudinal direction (X direction).

[0011] The resistor 3 is disposed on at least one of the front surface 11 and the back surface 12. In the first embodiment, the resistor 3 includes a first resistor 31 and a second resistor 32. The resistor 3 is, for example, a CuNi resistor.

[0012] The first resistor 31 is disposed on the surface 11. A center 31c of the first resistor 31 in the longitudinal direction (X direction) of the insulating substrate 10 does not have to coincide with, for example, a center 10c of the insulating substrate 10 in the longitudinal direction of the insulating substrate 10.

[0013] The second resistor 32 is disposed on the rear surface 12. A center 32c of the second resistor 32 in the longitudinal direction (X direction) of the insulating substrate 10 does not have to coincide with, for example, a center 10c of the insulating substrate 10 in the longitudinal direction of the insulating substrate 10. A center 31c of the first resistor 31 does not have to coincide with a center 32c of the second resistor 32 in the longitudinal direction (X direction).

[0014] The surface electrode 2a is disposed on the surface 11. The surface electrode 2a includes a first surface electrode 20 and a second surface electrode 21. The first surface electrode 20 and the second surface electrode 21 are connected to the first resistor 31. In a plan view of the surface 11, the second surface electrode 21 is disposed spaced apart from the first surface electrode 20 in the X direction. The first surface electrode 20 is disposed closer to the first side surface 13a than the second surface electrode 21. The second surface electrode 21 is disposed closer to the second side surface 13b than the first surface electrode 20. In other words, the first surface electrode 20 and the second surface electrode 21 are disposed so as to sandwich the first resistor 31 in the X direction. The surface electrode 2a is, for example, a Cu electrode or an Ag electrode.

[0015] The back surface electrode 2b is disposed on the back surface 12. The back surface electrode 2b includes a first back surface electrode 23 and a second back surface electrode 24. The first back surface electrode 23 and the second back surface electrode 24 are connected to the second resistor 32. In a plan view of the back surface 12, the second back surface electrode 24 is disposed spaced apart from the first back surface electrode 23 in the X direction. The first back surface electrode 23 is disposed closer to the first side surface 13a than the second back surface electrode 24. The second back surface electrode 24 is disposed closer to the second side surface 13b than the first back surface electrode 23. In other words, the first back surface electrode 23 and the second back surface electrode 24 are disposed so as to sandwich the second resistor 32 in the X direction.

[0016] The back surface electrode 2b is, for example, a Cu electrode or an Ag electrode. The first back surface electrode 23 and the second back surface electrode 24 are formed of, for example, the same conductive material as the first surface electrode 20 and the second surface electrode 21.

[0017] As will be described later, the front electrode 2a and the back electrode 2b may be made up of a plurality of layers, for example, two or three layers.

[0018] The insulating protective film 4 is disposed on the resistor 3. The insulating protective film 4 includes a first insulating protective film 41 and a second insulating protective film 42. The first insulating protective film 41 is disposed on the first resistor 31. The first insulating protective film 41 is also disposed on the first front surface electrode 20 and the second front surface electrode 21. The second insulating protective film 42 is disposed on the second resistor 32. The second insulating protective film 42 is also disposed on the first back surface electrode 23 and the second back surface electrode 24. The insulating protective film 4 contains, for example, an epoxy resin, a phenolic resin, or a mixture of an epoxy resin and a phenolic resin.

[0019] It is sufficient that the second resistor 32 and the second insulating protective film 42 are formed on the rear surface 12, and as will be described later, the first resistor 31 and the first insulating protective film 41 do not have to be arranged on the front surface 11.

[0020] The side electrodes 5 are disposed on the side surfaces 13, the front surface electrodes 2a, and the rear surface electrodes 2b. The side electrodes 5 include a first side electrode 51 and a second side electrode 52.

[0021] The first side electrode 51 is disposed on the first side surface 13a of the insulating substrate 10, the first surface electrode 20, and the first back surface electrode 23. The first surface electrode 20 is electrically connected to the first back surface electrode 23 through the first side surface electrode 51. The first side surface electrode 51 includes a first layer 51a, a second layer 51b, a third layer 51c, and a fourth layer 51d.

[0022] The first layer 51a is disposed on the first side surface 13a of the insulating substrate 10, the first front surface electrode 20, and the first back surface electrode 23. The first layer 51a is formed, for example, of a conductive material that is difficult to sulfurize. The first layer 51a is formed, for example, of a Ni—Cr alloy. The first layer 51a is, for example, a sputtered layer. The first layer 51a may be disposed on the first insulating protective film 41 and the second insulating protective film 42, but in the first embodiment, the first layer 51a is not disposed on the first insulating protective film 41 and the second insulating protective film 42.

[0023] The second layer 51b is disposed on the first surface electrode 20, the first back surface electrode 23, and the first layer 51a. The second layer 51b is, for example, a copper layer. The second layer 51b is connected to the first insulating protective film 41 and the second insulating protective film 42.

[0024] The third layer 51c is disposed on the second layer 51b. The third layer 51c protects the first front surface electrode 20, the first back surface electrode 23, the first layer 51a, and the second layer 51b from heat and impact. The third layer 51c is, for example, a nickel layer. The third layer 51c is connected to the first insulating protective film 41 and the second insulating protective film 42.

[0025] The fourth layer 51d is disposed on the third layer 51c. The fourth layer 51d is formed of a material to which a conductive bonding member 200 (not shown), such as solder, is easily attached. The fourth layer 51d is, for example, a tin layer. The fourth layer 51d is connected to the first insulating protective film 41 and the second insulating protective film 42.

[0026] The second side surface electrode 52 is disposed on the second side surface 13b of the insulating substrate 10, the second front surface electrode 21, and the second rear surface electrode 24. The second front surface electrode 21 is electrically connected to the second rear surface electrode 24 through the second side surface electrode 52. The second side surface electrode 52 includes a first layer 52a, a second layer 52b, a third layer 52c, and a fourth layer 52d.

[0027] The first layer 52a is disposed on the second side surface 13b of the insulating substrate 10, the second front surface electrode 21, and the second back surface electrode 24. The first layer 52a is formed, for example, of a conductive material that is difficult to sulfurize. The first layer 52a is formed, for example, of a Ni—Cr alloy. The first layer 52a is, for example, a sputtered layer. The first layer 52a may be disposed on the first insulating protective film 41 and the second insulating protective film 42, but in the first embodiment, the first layer 52a is not disposed on the first insulating protective film 41 and the second insulating protective film 42.

[0028] The second layer 52b is disposed on the second front surface electrode 21, the second rear surface electrode 24, and the first layer 52a. The second layer 52b is, for example, a copper layer. The second layer 52b is connected to the first insulating protective film 41 and the second insulating protective film 42.

[0029] The third layer 52c is disposed on the second layer 52b. The third layer 52c protects the second front surface electrode 21, the second rear surface electrode 24, the first layer 52a, and the second layer 52b from heat and shock. The third layer 52c is, for example, a nickel layer. The third layer 52c is connected to the first insulating protective film 41 and the second insulating protective film 42.

[0030] The fourth layer 52d is disposed on the third layer 52c. The fourth layer 52d is formed of a material to which the conductive bonding member 200, such as solder, easily adheres. The fourth layer 52d is, for example, a tin layer. The fourth layer 52d is connected to the first insulating protective film 41 and the second insulating protective film 42. The conductive bonding member 200 (not shown) adheres to the fourth layers 51d and 52d and the electrical wiring (not shown) of the wiring substrate 100 (not shown), and the chip resistor 1a is mounted on the wiring substrate 100.

[0031] Here, a feature of the chip resistor 1a according to the first embodiment is that the bottom surface 50s of the side electrode 5 is inclined with respect to the back surface 12. Specifically, as shown in FIG. 3 , the side electrode 5 has a lowest point P1. The lowest point P1 is located at a position farthest from the back surface 12 in the Z direction. The side electrode 5 has a bottom surface 50s. The bottom surface 50s is a region from the side surface 13 to the lowest point P1. The bottom surface 50s is inclined with respect to the back surface 12. The bottom surface 50s has a first region L1. The first region L1 is a region away from the side surface 13 in the X direction and includes the lowest point P1. In the first region L1, the inclination angle θ1 of the bottom surface 50s with respect to the back surface 12 is greater than or equal to 1° and less than or equal to 10°.

[0032] When the chip resistor 1a is mounted on the wiring substrate 100 via the conductive bonding member 200, the chip resistor 1a is mounted so that the back surface 12 is parallel to the mounting surface of the wiring substrate 100. When the chip resistor 1a is mounted on the wiring substrate 100 via such a conductive bonding member 200, there is a risk that a crack 400 will occur between the bottom surface 50s and the wiring substrate 100 due to thermal fatigue such as a temperature cycle.

[0033] However, by mounting the chip resistor 1a on the wiring substrate 100 so that the bottom surface 50s is inclined relative to the mounting surface of the wiring substrate 100, as in the case of the chip resistor 1a according to the first embodiment, stress concentration on the conductive bonding member 200 caused by thermal fatigue is alleviated. In other words, the occurrence of cracks 400 caused by thermal fatigue between the bottom surface 50s and the wiring substrate 100 is suppressed. As a result, the long-term reliability of the chip resistor 1a is improved.

[0034] FIGS. 4 and 5 show modified examples of the chip resistor 1a shown in FIGS. 1 to 3. Each of FIGS. 4 and 5 corresponds to FIG. 3. The chip resistors 1b and 1c shown in FIGS. 4 and 5 basically have the same configuration as the chip resistor 1a shown in FIGS. 1 to 3, but differ in that the bottom surface 50s has multiple inclination angles θ that are different from one another. Specifically, the bottom surface 50s may have a second region L2. The second region L2 is located at a position closest to the side surface 13 in the X direction. In the second region L2, the inclination angle θ2 of the bottom surface 50s with respect to the back surface 12 may be 1° or more, but is preferably 5° or more.

[0035] In the chip resistor 1b according to the modified example of the first embodiment shown in Figure 4, the second region L2 of the bottom surface 50s is adjacent to the first region L1. In the X direction, the width of the first region L1 is preferably at least half the distance from the side surface 13 to the lowest point P1. The width of the first region L1 is the distance in the X direction from the lowest point P1 to the point where the first region L1 connects to the second region L2.

[0036] The bottom surface 50s may have a third region L3. In the chip resistor 1c according to the modified example of the first embodiment shown in FIG. 5, the third region L3 is disposed between the first region L1 and the second region L2 in the X direction. That is, the first region L1 is disposed between the lowest point P1 and the third region L3 in the X direction. The second region L2 is disposed between the side surface 13 and the third region L3 in the X direction. In the third region L3, the inclination angle θ3 of the bottom surface 50s with respect to the back surface 12 is preferably 1° or more and 5° or less. In the X direction, the width of each of the first region L1, the second region L2, and the third region L3 is preferably ¼ or more and ½ or less of the distance from the side surface 13 to the lowest point P1.

[0037] In this way, if the chip resistors 1a, 1b, and 1c are mounted on the wiring substrate 100 so that the bottom surface 50s is inclined relative to the mounting surface of the wiring substrate 100, stress concentration on the conductive bonding member 200 caused by temperature cycles is alleviated. In other words, the occurrence of cracks 400 due to thermal fatigue between the bottom surface 50s and the wiring substrate 100 is suppressed. As a result, the long-term reliability of the chip resistor 1a is improved.

[0038] The inclination angle θ will now be described. As shown in Figures 3 to 5, the inclination angle θ is the angle formed between each of the approximation lines A1, A2, and A3 and each of the parallel lines B1, B2, and B3. The inclination angle θ is a narrow angle. The parallel lines B1, B2, and B3 are lines parallel to the back surface 12.

[0039] The approximation line A1 is a linear line calculated from consecutive points on the bottom surface 50s in the first region L1. The approximation line A2 is a linear line calculated from consecutive points on the bottom surface 50s in the second region L2. The approximation line A3 is a linear line calculated from consecutive points on the bottom surface 50s in the third region L3. The consecutive points are captured from a cross-sectional photograph of the chip resistor 1a. The approximation lines A1, A2, and A3 are calculated from the consecutive points using, for example, the least squares method.

[0040] The angles formed by the approximate lines A1, A2, A3 thus calculated and the parallel lines B1, B2, B3, respectively, are calculated to calculate the inclination angles θ1, θ2, θ3.

[0041] If the surface electrode 2a extends to the side surface 13, burrs may occur on the side surface 13 during the manufacturing process of the chip resistor 1a. Therefore, it is preferable that the surface electrode 2a does not extend to the side surface 13 in a plan view seen from the Z direction.

[0042] On the other hand, if the back electrode 2b does not extend to the side surface 13, stress concentration occurs at the corners of the insulating substrate 10 due to temperature cycling. As a result, cracks 400 due to thermal fatigue may occur at the corners of the insulating substrate 10. In order to reduce stress concentration at the corners of the insulating substrate 10, it is preferable that the back electrode 2b extend to the side surface 13 in a plan view seen from the Z direction.

[0043] In order to reduce stress concentration at the corners of the insulating substrate 10, the width W1 of the sputtered layer in the X direction is preferably 10 nm or more. Specifically, as shown in Fig. 3, for example, the width W1 of the first layer 51a in the X direction is preferably 10 nm or more.

[0044] In order to reduce stress concentration at the corners of the insulating substrate 10, the width W2 of the side electrode 5 in the X direction is preferably 15 μm or more. Specifically, as shown in FIG. 3 , for example, the width W2 of the first side electrode 51 in the X direction is preferably 15 μm or more.

[0045] 3, in order to reduce stress concentration at the corners of insulating substrate 10, it is preferable that back surface electrode 2b have a thickness T1 of 5 μm or more in the Z direction. Thickness T1 is, for example, the distance from back surface 12 to the point on back surface electrode 2b that is located at the farthest position in the Z direction.

[0046] <Effects> The chip resistor 1a according to the present disclosure includes an insulating substrate 10, a resistive element 3, a back surface electrode 2b, and a side electrode 5. The insulating substrate 10 includes a front surface 11, a back surface 12, and a side surface 13. The back surface 12 is located on the opposite side of the front surface 11. The side surface 13 connects the front surface 11 and the back surface 12. The resistive element 3 is located on at least one of the front surface 11 and the back surface 12. The back surface electrode 2b is located on the back surface 12. The side electrode 5 is located on the side surface 13 and the back surface electrode 2b. The direction perpendicular to the back surface 12 is defined as the Z direction. The side electrode 5 has a lowest point P1. The lowest point P1 is located at the farthest position from the back surface 12 in the Z direction. The side electrode 5 has a lowest surface 50s. The lowest surface 50s is the region from the side surface 13 to the lowest point P1. The lowest surface 50s is inclined with respect to the back surface 12. The bottom surface 50s has a first region L1. The first region L1 includes a lowest point P1. In the first region L1, the bottom surface 50s has an inclination angle θ1 of 1° or more and 10° or less with respect to the rear surface 12.

[0047] In this way, by mounting the chip resistor 1a on the wiring substrate 100 so that the bottom surface 50s is inclined relative to the mounting surface of the wiring substrate 100, stress concentration on the conductive bonding member 200 caused by temperature cycles is alleviated. In other words, the occurrence of cracks 400 due to thermal fatigue between the bottom surface 50s and the wiring substrate 100 is suppressed. As a result, the long-term reliability of the chip resistor 1a can be improved.

[0048] In the chip resistor 1a, the direction perpendicular to the side surface 13 is defined as the X direction. The bottom surface 50s has a second region L2. The second region L2 is located closest to the side surface 13 in the X direction. In the second region L2, the inclination angle θ2 of the bottom surface 50s with respect to the back surface 12 is 5° or greater.

[0049] In this way, even if the bottom surface 50s includes a plurality of different inclination angles θ, stress concentration on the conductive bonding member 200 caused by temperature cycles is alleviated. In other words, the occurrence of cracks 400 due to thermal fatigue between the bottom surface 50s and the wiring substrate 100 is suppressed. As a result, the long-term reliability of the chip resistor 1a can be improved.

[0050] In the chip resistor 1a, the bottom surface 50s has a third region L3. The third region L3 is disposed between the first region L1 and the second region L2 in the X direction. In the third region L3, the inclination angle θ3 of the bottom surface 50s with respect to the back surface 12 is 1° or more and 5° or less.

[0051] In this way, even if the bottom surface 50s includes a plurality of different inclination angles θ, stress concentration on the conductive bonding member 200 caused by temperature cycles is alleviated. In other words, the occurrence of cracks 400 due to thermal fatigue between the bottom surface 50s and the wiring substrate 100 is suppressed. As a result, the long-term reliability of the chip resistor 1a can be improved.

[0052] In the chip resistor 1a, the width of the first region L1 in the X direction is at least half the distance from the side surface 13 to the lowest point P1. This reduces stress concentration on the conductive bonding member 200 caused by temperature cycles, even if the lowest surface 50s includes multiple different inclination angles θ. In other words, the occurrence of cracks 400 due to thermal fatigue between the lowest surface 50s and the wiring substrate 100 is suppressed. As a result, the long-term reliability of the chip resistor 1a can be improved.

[0053] In the chip resistor 1a, the back electrode 2b extends to the side surface 13 in a plan view seen from the Z direction. This reduces stress concentration at the corners of the insulating substrate 10. As a result, the long-term reliability of the chip resistor 1a can be improved.

[0054] In the chip resistor 1a, the thickness T1 in the Z direction of the back electrode 2b is 5 μm or more. This reduces stress concentration at the corners of the insulating substrate 10. As a result, the long-term reliability of the chip resistor 1a can be improved.

[0055] In the chip resistor 1a, the width W2 in the X direction of the side electrode 5 is 15 μm or more. This reduces stress concentration at the corners of the insulating substrate 10. As a result, the long-term reliability of the chip resistor 1a can be improved.

[0056] The chip resistor 1a further includes a surface electrode 2a and an insulating protective film 4. The surface electrode 2a is disposed on the surface 11. The insulating protective film 4 includes a first insulating protective film 41 and a second insulating protective film 42. The side surface 13 includes a first side surface 13a and a second side surface 13b. The second side surface 13b is disposed on the opposite side to the first side surface 13a. The resistor 3 includes a first resistor 31 and a second resistor 32. The first resistor 31 is disposed on the surface 11. The second resistor 32 is disposed on the back surface 12. The surface electrode 2a includes a first surface electrode 20 and a second surface electrode 21. The second surface electrode 21 is disposed spaced apart from the first surface electrode 20 in the X direction. The back surface electrode 2b includes a first back surface electrode 23 and a second back surface electrode 24. The second back surface electrode 24 is disposed spaced apart from the first back surface electrode 23 in the X direction. The side electrode 5 includes a first side electrode 51 and a second side electrode 52. The first side electrode 51 is disposed on the first side surface 13a, the first back surface electrode 23, and the first surface electrode 20. The second side electrode 52 is disposed on the second side surface 13b, the second back surface electrode 24, and the second surface electrode 21. The first insulating protective film 41 is disposed on the first resistor 31, the first surface electrode 20, and the second surface electrode 21. The second insulating protective film 42 is disposed on the second resistor 32, the first back surface electrode 23, and the second back surface electrode 24.

[0057] In this way, if the chip resistor 1a is mounted on the wiring substrate 100 so that the bottom surface 50s is inclined relative to the mounting surface of the wiring substrate 100, stress concentration on the conductive bonding member 200 caused by temperature cycles is alleviated. In other words, the occurrence of cracks 400 due to thermal fatigue between the bottom surface 50s and the wiring substrate 100 is suppressed. As a result, the long-term reliability of the chip resistor 1a can be improved.

[0058] In order to verify the effects of the chip resistors 1a, 1b, and 1c according to the first embodiment as described above, the occurrence of cracks 400 was investigated by a temperature cycle test.

[0059] <Temperature Cycle Test> The temperature cycle test involves repeatedly placing the chip resistor in a low-temperature environment of -55°C for 30 minutes and then in a high-temperature environment of 150°C for 30 minutes. The temperature cycle test was conducted on the chip resistors of Examples 1 to 9 and Comparative Example 1. Tables 1 to 3 show the inclination angles θ of the chip resistors of Examples 1 to 9 and Comparative Example 1. Examples 1 to 4 have the same configuration as the chip resistor 1a according to the first embodiment. Examples 5 to 7 have the same configuration as the chip resistor 1b according to the first embodiment. Examples 8 and 9 have the same configuration as the chip resistor 1c according to the first embodiment. That is, the inclination angle θ1 in Examples 1 to 9 is 1° or more and 10° or less. The inclination angle θ2 in Examples 5 to 9 is 5° or more. The inclination angle θ3 in Examples 8 and 9 is 1° or more and 5° or less. Note that in Comparative Example 1, the bottom surface 50s of the chip resistor is parallel to the back surface 12. That is, the inclination angle θ in Comparative Example 1 is 0°. The inclination angles θ shown in Tables 1 to 3 are those on the first side surface 13a side.

[0060]

[0061]

[0062]

[0063] <Test Results> In the above temperature cycle test, no cracks 400 occurred between the bottom surface 50s and the wiring substrate 100 near the bottom surface 50s in Examples 1 to 9. On the other hand, in Comparative Example 1, cracks 400 occurred between the bottom surface 50s and the wiring substrate 100 near the bottom surface 50s. When cracks 400 occur, the resistance value of the chip resistor changes significantly. Therefore, the long-term reliability of the chip resistor may be confirmed by measuring the amount of change in the resistance value of the chip resistor.

[0064] 6 and 7 show chip resistors after the temperature cycle test. Fig. 6 is a partial cross-sectional view of the chip resistor in Comparative Example 1 after the temperature cycle test. Fig. 7 is a partial cross-sectional view of the chip resistor in Example 1 after the temperature cycle test.

[0065] 6, in Comparative Example 1, cracks 400 occur between the bottom surface 50s and the wiring substrate 100. On the other hand, as shown in Fig. 7, in Example 1, cracks 400 do not occur between the bottom surface 50s and the wiring substrate 100. In other words, by inclining the bottom surface 50s with respect to the back surface 12, the long-term reliability of the chip resistor can be improved.

[0066] Second Embodiment. <Configuration of Chip Resistor> FIG. 8 is a schematic cross-sectional view of a chip resistor 1a according to a second embodiment. FIG. 8 corresponds to FIG. 2. The chip resistor 1a shown in FIG. 8 basically has the same configuration as the chip resistor 1a shown in FIGS. 1 to 3 and can achieve the same effects. However, it differs in that the surface electrode 2a and the back electrode 2b are each configured with two layers. This configuration facilitates control of the inclination angle θ. Furthermore, since the surface electrode 2a and the back electrode 2b are each configured with two layers, the resistance values ​​of the surface electrode 2a and the back electrode 2b are reduced. This reduces the temperature coefficient of resistance of the chip resistor 1a. Furthermore, the low resistance value of the chip resistor 1a improves the measurement accuracy of the resistance value during probing.

[0067] Specifically, for example, the first surface electrode 20 includes a first electrode layer 20a and a second electrode layer 20b. The first surface electrode 20 is a laminate of the first electrode layer 20a and the second electrode layer 20b. The first electrode layer 20a is disposed on the surface 11. A portion of the first resistor 31 is disposed on the first electrode layer 20a. The second electrode layer 20b is disposed on the first electrode layer 20a. A portion of the second electrode layer 20b is disposed on the first resistor 31.

[0068] The second surface electrode 21 includes a first electrode layer 21a and a second electrode layer 21b. The second surface electrode 21 is a laminate of the first electrode layer 21a and the second electrode layer 21b. The first electrode layer 21a is disposed on the surface 11. A portion of the first resistor 31 is disposed on the first electrode layer 21a. The second electrode layer 21b is disposed on the first electrode layer 21a. A portion of the second electrode layer 21b is disposed on the first resistor 31.

[0069] The first back surface electrode 23 includes a first electrode layer 23a and a second electrode layer 23b. The first back surface electrode 23 is a laminate of the first electrode layer 23a and the second electrode layer 23b. The first electrode layer 23a is disposed on the back surface 12. A portion of the second resistor 32 is disposed on the first electrode layer 23a. The second electrode layer 23b is disposed on the first electrode layer 23a. A portion of the second electrode layer 23b is disposed on the second resistor 32.

[0070] The second back surface electrode 24 includes a first electrode layer 24a and a second electrode layer 24b. The second back surface electrode 24 is a laminate of the first electrode layer 24a and the second electrode layer 24b. The first electrode layer 24a is disposed on the back surface 12. A portion of the second resistor 32 is disposed on the first electrode layer 24a. The second electrode layer 24b is disposed on the first electrode layer 24a. A portion of the second electrode layer 24b is disposed on the second resistor 32.

[0071] Third Embodiment <Configuration of Chip Resistor> FIG. 9 is a schematic cross-sectional view of a chip resistor 1a according to a third embodiment. FIG. 9 corresponds to FIG. 2. The chip resistor 1a shown in FIG. 9 basically has the same configuration as the chip resistor 1a shown in FIGS. 1 to 3 and can achieve the same effects. However, it differs in that the surface electrode 2a and the back electrode 2b are each composed of three layers. This configuration makes it easier to control the inclination angle θ. Furthermore, because the surface electrode 2a and the back electrode 2b are each composed of three layers, the resistance values ​​of the surface electrode 2a and the back electrode 2b are reduced. This reduces the temperature coefficient of resistance of the chip resistor 1a. Furthermore, the low resistance value of the chip resistor 1a improves the measurement accuracy of the resistance value during probing.

[0072] Specifically, for example, the first surface electrode 20 includes a first electrode layer 20a, a second electrode layer 20b, and a third electrode layer 20c. The first surface electrode 20 is a laminate of the first electrode layer 20a, the second electrode layer 20b, and the third electrode layer 20c. The first electrode layer 20a is disposed on the surface 11. A portion of the first resistor 31 is disposed on the first electrode layer 20a. The second electrode layer 20b is disposed on the first electrode layer 20a. A portion of the second electrode layer 20b is disposed on the first resistor 31. The third electrode layer 20c is disposed on the second electrode layer 20b.

[0073] The second surface electrode 21 includes a first electrode layer 21a, a second electrode layer 21b, and a third electrode layer 21c. The second surface electrode 21 is a laminate of the first electrode layer 21a, the second electrode layer 21b, and the third electrode layer 21c. The first electrode layer 21a is disposed on the surface 11. A portion of the first resistor 31 is disposed on the first electrode layer 21a. The second electrode layer 21b is disposed on the first electrode layer 21a. A portion of the second electrode layer 21b is disposed on the first resistor 31. The third electrode layer 21c is disposed on the second electrode layer 21b.

[0074] The first back surface electrode 23 includes a first electrode layer 23a, a second electrode layer 23b, and a third electrode layer 23c. The first back surface electrode 23 is a laminate of the first electrode layer 23a, the second electrode layer 23b, and the third electrode layer 23c. The first electrode layer 23a is disposed on the back surface 12. A portion of the second resistor 32 is disposed on the first electrode layer 23a. The second electrode layer 23b is disposed on the first electrode layer 23a. A portion of the second electrode layer 23b is disposed on the second resistor 32. The third electrode layer 23c is disposed on the second electrode layer 23b.

[0075] The second back surface electrode 24 includes a first electrode layer 24a, a second electrode layer 24b, and a third electrode layer 24c. The second back surface electrode 24 is a laminate of the first electrode layer 24a, the second electrode layer 24b, and the third electrode layer 24c. The first electrode layer 24a is disposed on the back surface 12. A portion of the second resistor 32 is disposed on the first electrode layer 24a. The second electrode layer 24b is disposed on the first electrode layer 24a. A portion of the second electrode layer 24b is disposed on the second resistor 32. The third electrode layer 24c is disposed on the second electrode layer 24b.

[0076] Embodiment 4. <Configuration of Chip Resistor> Figure 10 is a schematic cross-sectional view of a chip resistor 1a according to embodiment 4. Figure 10 corresponds to Figure 2. The chip resistor 1a shown in Figure 10 basically has the same configuration as the chip resistor 1a shown in Figures 1 to 3 and can achieve the same effects, but differs in that a sputtered layer is also formed on the insulating protective film 4. Specifically, as shown in Figure 10, the first layers 51a and 52a are disposed on the first insulating protective film 41 and the second insulating protective film 42. In this manner, the side electrode 5 can be formed on the insulating protective film 4. As a result, the region in which the side electrode 5 extends in the X direction can be adjusted.

[0077] Fifth Embodiment <Configuration of Chip Resistor> FIG. 11 is a schematic cross-sectional view of a chip resistor 1a according to a fifth embodiment. FIG. 11 corresponds to FIG. 8. The chip resistor 1a shown in FIG. 11 basically has the same configuration as the chip resistor 1a shown in FIG. 8 and can achieve the same effects. However, it differs in that the sputtered layers disposed on the two-layered front and back electrodes 2a and 2b are also formed on the insulating protective film 4. Specifically, as shown in FIG. 11, the first layers 51a and 52a are disposed on the first and second insulating protective films 41 and 42. This allows the side electrode 5 to be formed on the insulating protective film 4. As a result, the region in which the side electrode 5 extends in the X direction can be adjusted. Furthermore, since the front and back electrodes 2a and 2b are each formed of two layers, the inclination angle θ can be easily controlled.

[0078] Sixth Embodiment. <Configuration of Chip Resistor> FIG. 12 is a schematic cross-sectional view of a chip resistor 1a according to a sixth embodiment. FIG. 12 corresponds to FIG. 9. The chip resistor 1a shown in FIG. 12 basically has the same configuration as the chip resistor 1a shown in FIG. 9 and can achieve the same effects. However, it differs in that the sputtered layers disposed on the three-layered front and back electrodes 2a and 2b are also disposed on the insulating protective film 4. Specifically, as shown in FIG. 12, the first layers 51a and 52a are disposed on the first and second insulating protective films 41 and 42. This allows the side electrode 5 to be formed on the insulating protective film 4. As a result, the region in which the side electrode 5 extends in the X direction can be adjusted. Furthermore, since the front and back electrodes 2a and 2b are each formed of three layers, the inclination angle θ can be easily controlled.

[0079] Seventh Embodiment <Configuration of Chip Resistor> Figure 13 is a schematic cross-sectional view of a chip resistor 1a according to a seventh embodiment. Figure 13 corresponds to Figure 2. The chip resistor 1a shown in Figure 13 basically has the same configuration as the chip resistor 1a shown in Figures 1 to 3 and can achieve the same effects, but differs in that the first resistive element 31 and the first insulating protective film 41 are not disposed on the surface 11. This ensures that the resistance value of the chip resistor 1a is stable over the long term.

[0080] Eighth Embodiment. <Configuration of Chip Resistor> FIG. 14 is a schematic cross-sectional view of a chip resistor 1a according to the eighth embodiment. FIG. 14 corresponds to FIG. 8. The chip resistor 1a shown in FIG. 14 basically has the same configuration as the chip resistor 1a shown in FIG. 8 and can achieve the same effects, but differs in that the first resistive element 31 and the first insulating protective film 41 are not disposed on the front surface 11. Furthermore, the front surface electrode 2a is configured as a single layer, while the back surface electrode 2b is configured as two layers. The two-layer configuration of the back surface electrode 2b makes it easier to control the inclination angle θ. Furthermore, because the resistive element 3 is disposed only on the back surface 12, the resistance value of the chip resistor 1a is stable over the long term.

[0081] Ninth Embodiment. <Configuration of Chip Resistor> FIG. 15 is a schematic cross-sectional view of a chip resistor 1a according to a ninth embodiment. FIG. 15 corresponds to FIG. 10. The chip resistor 1a shown in FIG. 15 basically has the same configuration as the chip resistor 1a shown in FIG. 10 and can achieve the same effects, but differs in that the first resistive element 31 and the first insulating protective film 41 are not disposed on the front surface 11. Because the resistive element 3 is disposed only on the back surface 12, the resistance value of the chip resistor 1a is stable over the long term. Furthermore, the first layers 51a and 52a are disposed on the second insulating protective film 42. Therefore, the side electrode 5 can be formed on the insulating protective film 4. As a result, the area in which the side electrode 5 extends in the X direction can be adjusted.

[0082] Tenth Embodiment <Configuration of Chip Resistor> FIG. 16 is a schematic cross-sectional view of a chip resistor 1a according to a tenth embodiment. FIG. 16 corresponds to FIG. 11. The chip resistor 1a shown in FIG. 16 basically has the same configuration as the chip resistor 1a shown in FIG. 11 and can achieve the same effects. However, it differs in that the first resistive element 31 and the first insulating protective film 41 are not disposed on the front surface 11. Furthermore, the front surface electrode 2a is configured as a single layer, while the back surface electrode 2b is configured as two layers. The two-layer configuration of the back surface electrode 2b facilitates control of the inclination angle θ. Furthermore, because the resistive element 3 is disposed only on the back surface 12, the resistance value of the chip resistor 1a is stable over the long term. Furthermore, the first layers 51a and 52a are disposed on the second insulating protective film 42. Therefore, the side electrode 5 can be formed on the insulating protective film 4. As a result, the area in which the side electrode 5 extends in the X direction can be adjusted.

[0083] Eleventh Embodiment. <Configuration of Chip Resistor> FIG. 17 is a schematic cross-sectional view of a chip resistor 1a according to an eleventh embodiment. FIG. 17 corresponds to FIG. 13. The chip resistor 1a shown in FIG. 17 basically has the same configuration as the chip resistor 1a shown in FIG. 13 and can achieve the same effects. However, it differs in that a conductive resin layer 60 is disposed on the back electrode 2b and the second insulating protective film 42. The conductive resin layer 60 includes a first conductive resin layer 61 and a second conductive resin layer 62. This configuration allows the region in which the side electrode 5 extends in the X direction to be adjusted. Furthermore, the conductive resin layer 60 suppresses the occurrence of cracks 400. As a result, the resistance value of the chip resistor 1a is stable over the long term.

[0084] The first conductive resin layer 61 is disposed on the first back surface electrode 23 and the second insulating protective film 42. The second conductive resin layer 62 is disposed on the second back surface electrode 24 and the second insulating protective film 42. The second conductive resin layer 62 is electrically insulated from the first conductive resin layer 61 by the second insulating protective film 42.

[0085] The first conductive resin layer 61 and the second conductive resin layer 62 contain a resin such as an epoxy resin, a phenolic resin, or a mixture of an epoxy resin and a phenolic resin, and conductive particles, such as metal particles such as silver particles or copper particles, carbon particles, or a combination thereof.

[0086] Embodiment 12. <Configuration of Chip Resistor> FIG. 18 is a schematic cross-sectional view of a chip resistor 1a according to embodiment 12. FIG. 18 corresponds to FIG. 14. The chip resistor 1a shown in FIG. 18 basically has the same configuration as the chip resistor 1a shown in FIG. 14 and can achieve the same effects. However, it differs in that a conductive resin layer 60 is disposed on the back surface electrode 2b and the second insulating protective film 42. This configuration allows the region in which the side electrode 5 extends in the X direction to be adjusted. Furthermore, the conductive resin layer 60 suppresses the occurrence of cracks 400. As a result, the resistance value of the chip resistor 1a is stable over the long term. Furthermore, the back surface electrode 2b is configured as two layers, making it easier to control the inclination angle θ.

[0087] The first conductive resin layer 61 is disposed on the second electrode layer 23b and the second insulating protective film 42. The second conductive resin layer 62 is disposed on the second electrode layer 24b and the second insulating protective film 42. The second conductive resin layer 62 is electrically insulated from the first conductive resin layer 61 by the second insulating protective film 42.

[0088] The various aspects of the present disclosure are summarized below as appendices. (Appendix 1) A chip resistor comprising: an insulating substrate including a front surface, a back surface disposed opposite the front surface, and a side surface connecting the front surface and the back surface, a resistor disposed on at least one of the front surface and the back surface, a back electrode disposed on the back surface, and a side electrode disposed on the side surface and the back surface electrode, wherein, when a direction perpendicular to the back surface is defined as a Z direction, the side electrode has a lowest point disposed at a position farthest from the back surface in the Z direction, the side electrode has a lowest surface which is a region from the side surface to the lowest point, the lowest surface is inclined with respect to the back surface, and the lowest surface has a first region including the lowest point, and in the first region, an inclination angle of the lowest surface with respect to the back surface is 1° to 10°. (Supplementary Note 2) The chip resistor according to Supplementary Note 1, wherein, when a direction perpendicular to the side surface is defined as the X direction, the bottom surface has a second region located at a position closest to the side surface in the X direction, and in the second region, an inclination angle of the bottom surface with respect to the back surface is 5° or more. (Supplementary Note 3) The chip resistor according to Supplementary Note 2, wherein the bottom surface has a third region located between the first region and the second region in the X direction, and in the third region, an inclination angle of the bottom surface with respect to the back surface is 1° or more and 5° or less. (Supplementary Note 4) The chip resistor according to Supplementary Note 2, wherein, in the X direction, a width of the first region is ½ or more of a distance from the side surface to the lowest point. (Supplementary Note 5) The chip resistor according to any one of Supplementary Notes 1 to 4, wherein, in a plan view seen from the Z direction, the back surface electrode extends to the side surface. (Supplementary Note 6) The chip resistor according to any one of Supplementary Notes 1 to 5, wherein the thickness of the back electrode in the Z direction is 5 μm or more. (Supplementary Note 7) The chip resistor according to any one of Supplementary Notes 2 to 4, wherein the width of the side electrode in the X direction is 15 μm or more.(Supplementary Note 8) The semiconductor device further includes a surface electrode disposed on the surface; and an insulating protective film including a first insulating protective film and a second insulating protective film, wherein the side surface includes a first side surface and a second side surface disposed opposite to the first side surface, the resistor includes a first resistor disposed on the surface and a second resistor disposed on the back surface, the surface electrode includes a first surface electrode and a second surface electrode disposed spaced apart from the first surface electrode in the X direction, the back surface electrode includes a first back surface electrode and a second back surface electrode disposed spaced apart from the first back surface electrode in the X direction, the side electrode includes a first side surface electrode and a second side surface electrode, the first side surface electrode is disposed on the first side surface, the first back surface electrode, and the first surface electrode, the second side surface electrode is disposed on the second side surface, the second back surface electrode, and the second surface electrode, and the first insulating protective film is disposed on the first resistor, the first surface electrode, and the second surface electrode, 5. The chip resistor according to claim 2, wherein the second insulating protective film is disposed on the second resistor, the first back surface electrode, and the second back surface electrode.

[0089] The first to twelfth embodiments disclosed herein should be considered to be illustrative in all respects and not restrictive. The scope of the present disclosure is defined by the claims, not the above description, and is intended to include all modifications within the meaning and scope of the claims.

[0090] 1a, 1b, 1c Chip resistor, 2a Surface electrode, 2b Back electrode, 3 Resistor, 4 Insulation protection film, 5 Side electrode, 10 Insulation substrate, 10c, 31c, 32c Center, 11 Surface, 12 Back, 13 Side, 13a 1st side, 13b 2nd side, 20 1st surface electrode, 20a, 21a, 23a, 24a 1st electrode layer, 20b, 21b, 23b, 24b 2nd electrode layer, 20c, 21c, 23c, 24c 3rd electrode layer, 21 2nd surface electrode, 23 1st back electrode, 24 2nd back electrode, 31 1st resistor, 32 2nd resistor, 41 1st insulation protection film, 42 2nd insulation protection film, 50s Bottom, 51 1st side electrode, 51a, 52a 1st layer, 51b, 52b 2nd layer, 51c, 52c 3rd layer, 51d, 52d 4th layer, 52 2nd side electrode, 60 Conductive resin layer, 61 1st conductive resin layer, 62 2nd conductive resin layer, 100 Wiring substrate, 200 Conductive bonding member, 400 Cluck, A1, A2, A3 Approximate lines, B1, B2, B3 Parallel lines, L1 1st area, L2 2nd area, L3 3rd area, P1 Lowermost point, T1 Thickness, W1, W2 Width.

Claims

1. An insulating substrate including a surface, a back surface located on the opposite side of the surface, and a side surface connecting the surface and the back surface, A resistor disposed on at least one of the aforementioned surface and the aforementioned back surface, The back surface electrode arranged on the back surface, The system comprises side electrodes arranged on the aforementioned side and back electrodes, If the direction perpendicular to the aforementioned back surface is defined as the Z direction, The side electrode has a lowest point located at the position furthest from the back surface in the Z direction, The side electrode has a bottom surface which is the region from the side to the bottom point, The bottom surface is inclined with respect to the back surface, The lowest surface has a first region including the lowest point, A chip resistor in which, in the first region, the inclination angle of the bottom surface with respect to the back surface is 1° or more and 10° or less.

2. If we define the direction perpendicular to the aforementioned side surface as the X direction, The lowest surface has a second region located closest to the side surface in the X direction, The chip resistor according to claim 1, wherein in the second region, the inclination angle of the bottom surface with respect to the back surface is 5° or more.

3. The lowest surface has a third region located between the first region and the second region in the X direction. The chip resistor according to claim 2, wherein in the third region, the inclination angle of the bottom surface with respect to the back surface is 1° or more and 5° or less.

4. The chip resistor according to claim 2, wherein in the X direction, the width of the first region is 1 / 2 or more of the distance from the side surface to the lowest point.

5. The chip resistor according to any one of claims 1 to 4, wherein in a plan view taken from the Z direction, the back electrode extends to the side surface.

6. The chip resistor according to any one of claims 1 to 4, wherein the thickness of the back electrode in the Z direction is 5 μm or more.

7. The chip resistor according to any one of claims 2 to 4, wherein the width of the side electrode in the X direction is 15 μm or more.

8. A surface electrode disposed on the aforementioned surface, The insulating protective film further comprises a first insulating protective film and a second insulating protective film, The aforementioned side includes a first side and a second side located on the opposite side from the first side. The resistor includes a first resistor disposed on the surface and a second resistor disposed on the back surface. The surface electrode includes a first surface electrode and a second surface electrode that is spaced apart from the first surface electrode in the X direction. The back electrode includes a first back electrode and a second back electrode that is spaced apart from the first back electrode in the X direction. The side electrode includes a first side electrode and a second side electrode. The first side electrode is arranged on the first side, the first back electrode, and the first front electrode. The second side electrode is arranged on the second side, the second back electrode, and the second front electrode. The first insulating protective film is disposed on the first resistor, the first surface electrode, and the second surface electrode. The chip resistor according to any one of claims 2 to 4, wherein the second insulating protective film is disposed on the second resistor, the first back electrode, and the second back electrode.