Semiconductor Device

Abstract

The semiconductor device (100a) includes a semiconductor substrate (1) and a mounting substrate (2). The semiconductor substrate (1) has a first surface (1s1). The mounting substrate (2) has a main surface (20s1). The main surface (20s1) faces the first surface (1s1). An electric field intensity mitigating portion (12) and an electrode (11) are formed on the first surface (1s1). The electrode (11) is connected to the mounting substrate (2). A recess (21) is formed on the main surface (20s1). The recess (21) is disposed at a position overlapping the electric field intensity mitigating portion (12) in a plan view of the first surface (1s1).

Description

[Technical field]

[0001] The present disclosure relates to a semiconductor device. [Background technology]

[0002] Conventionally, there is known a semiconductor device using flip-chip mounting in which a mounting substrate is connected to an electrode of a semiconductor substrate so that the back surface of the semiconductor substrate faces the mounting substrate (see, for example, JP 2013-89948 A). In JP 2013-89948 A, the semiconductor substrate has a guard ring as an electric field strength mitigation section that mitigates a high electric field generated in an active region. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] JP 2013-89948 A Summary of the Invention [Problem to be solved by the invention]

[0004] However, in the above-described semiconductor device, if the mounting substrate and the guard ring are close to each other, the electric field in the active region of the semiconductor substrate is not alleviated, and the breakdown voltage of the semiconductor device deteriorates.

[0005] The present disclosure has been made to solve the above-mentioned problems, and an object of the present disclosure is to provide a semiconductor device with improved voltage resistance. [Means for solving the problem]

[0006] A semiconductor device according to the present disclosure includes a semiconductor substrate and a mounting substrate. The semiconductor substrate has a first surface. The mounting substrate has a main surface. The main surface faces the first surface. An electric field intensity mitigating portion and an electrode are formed on the first surface. The electrode is connected to the mounting substrate. A recess is formed on the main surface. The recess is disposed at a position overlapping the electric field intensity mitigating portion in a plan view of the first surface. Effect of the Invention

[0007] According to the above, a semiconductor device with improved voltage resistance can be obtained. [Brief description of the drawings]

[0008] [Figure 1] 1 is a schematic cross-sectional view of a semiconductor device according to a first embodiment. [Diagram 2] 2 is a schematic bottom view of a semiconductor substrate in the semiconductor device according to the first embodiment. FIG. [Diagram 3] 2 is a schematic plan view of a mounting substrate in the semiconductor device according to the first embodiment. [Figure 4] FIG. 4 is a schematic cross-sectional view taken along line IV-IV in FIG. [Diagram 5] 4 is a schematic cross-sectional view taken along line VV in FIG. 3. [Figure 6] 3 is a schematic partial cross-sectional view of a recess in the semiconductor device according to the first embodiment. [Figure 7] 6 is a schematic partial cross-sectional view of a modified example of a recess in the semiconductor device according to the first embodiment. FIG. [Figure 8] 6 is a schematic partial cross-sectional view of a modified example of a recess in the semiconductor device according to the first embodiment. FIG. [Figure 9] 6 is a schematic partial cross-sectional view of a modified example of a recess in the semiconductor device according to the first embodiment. FIG. [Figure 10] 2 is a schematic plan view showing a conductive portion in the semiconductor device according to the first embodiment. [Figure 11] 11 is a schematic cross-sectional view taken along line XI-XI in FIG. 10. [Figure 12] 1 is a schematic bottom view of a semiconductor substrate in a first modified example of the semiconductor device according to the first embodiment. FIG. [Figure 13] 1 is a schematic plan view of a mounting substrate in a first modified example of the semiconductor device according to the first embodiment. FIG. [Figure 14] 11 is a schematic plan view of a mounting board in a second modified example of the semiconductor device according to the first embodiment. FIG. [Figure 15] FIG. 11 is a schematic cross-sectional view of a semiconductor device according to a second embodiment. [Figure 16] 11 is a schematic plan view of a mounting substrate in a semiconductor device according to a second embodiment. FIG. [Figure 17] 17 is a schematic cross-sectional view taken along line XVII-XVII in FIG. 16. [Figure 18] FIG. 11 is a schematic cross-sectional view of a semiconductor device according to a third embodiment. [Figure 19] FIG. 11 is a schematic cross-sectional view of a semiconductor device according to a fourth embodiment. [Figure 20] FIG. 13 is a schematic cross-sectional view of a semiconductor device according to a fifth embodiment. [Figure 21] FIG. 13 is a schematic cross-sectional view of a modified example of the semiconductor device according to the fifth embodiment. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0009] Hereinafter, embodiments of the present disclosure will be described. Note that unless otherwise specified, the same or corresponding parts in the following drawings are given the same reference numerals, and the description thereof will not be repeated.

[0010] Embodiment 1 <Configuration of Semiconductor Device> FIG. 1 is a schematic cross-sectional view of the semiconductor device 100a according to the first embodiment. FIG. 2 is a schematic bottom view of the semiconductor substrate 1 in the semiconductor device 100a according to the first embodiment. FIG. 3 is a schematic plan view of the mounting substrate 2 in the semiconductor device 100a according to the first embodiment. FIG. 4 is a schematic cross-sectional view taken along line IV-IV in FIG. 3. FIG. 5 is a schematic cross-sectional view taken along line VV in FIG. 3. FIG. 6 is a schematic partial cross-sectional view of the electric field intensity mitigating portion 12 and the recess 21 in the semiconductor device 100a according to the first embodiment.

[0011] 1 to 6 is, for example, a power semiconductor device 100a, and mainly includes a semiconductor substrate 1, a mounting substrate 2, a joint 5, a wiring circuit 6, and a sealing resin 7. The joint 5 includes a first joint 5a, a second joint 5b, a third joint 5c, a fourth joint 5d, and a fifth joint 5e. The wiring circuit 6 includes a first wiring circuit 6a, a second wiring circuit 6b, and a third wiring circuit 6c.

[0012] The semiconductor substrate 1 has a first surface 1s1, a second surface 1s2, and a third surface 1s3. The first surface 1s1 is a surface facing the main surface 20s1 of the mounting substrate 2. The second surface 1s2 is a surface opposite to the first surface 1s1. The third surface 1s3 connects the first surface 1s1 and the second surface 1s2. In the semiconductor device 100a according to the first embodiment, the first surface 1s1 is a back surface of the semiconductor substrate 1. In the semiconductor device 100a according to the first embodiment, the second surface 1s2 is a front surface of the semiconductor substrate 1. In the semiconductor device 100a according to the first embodiment, the third surface 1s3 is a side surface of the semiconductor substrate 1.

[0013] The first surface 1s1 and the second surface 1s2 extend in the x direction and the y direction perpendicular to the x direction. The x direction is the direction in which the wiring circuit extends. The y direction is the direction perpendicular to the x direction. The z direction is the thickness direction of the semiconductor substrate 1. The normal direction of the first surface 1s1 is the z direction. The second surface 1s2 faces the +z direction. The first surface 1s1 faces the -z direction.

[0014] As shown in FIG. 1 and FIG. 2, an electric field intensity mitigating portion 12 and an electrode 11 are formed on the first surface 1s1. The electric field intensity mitigating portion 12 mitigates the electric field intensity formed on the rear surface of the semiconductor substrate 1. For this reason, the electric field intensity mitigating portion 12 is disposed on the first surface 1s1 at a distance from the electrode 11. As shown in FIG. 2, the electric field intensity mitigating portion 12 may be disposed so as to surround the electrode 11. The shape of the electric field intensity mitigating portion 12 may be, for example, annular. Specifically, the electric field intensity mitigating portion 12 may be a termination structure called a guard ring.

[0015] The shape of the electric field intensity mitigating portion 12 does not have to be annular. Specifically, the electric field intensity mitigating portion 12 may be a termination structure called a JTE (Junction Termination Extension) structure. The electric field intensity mitigating portion 12 may be, for example, a p-type region formed by ion implantation.

[0016] As shown in Fig. 2, the electrode 11 includes a first electrode 11a and a second electrode 11b. The first electrode 11a is a main electrode. A main current flows through the main electrode. The second electrode 11b is a control electrode. The control electrode controls the main current. The first electrode 11a and the second electrode 11b are disposed spaced apart from each other on the first surface 1s1.

[0017] The first electrode 11a is connected to the mounting board 2 via a first joint portion 5a. The second electrode 11b is connected to the mounting board 2 via a second joint portion 5b.

[0018] As shown in Fig. 1, an upper electrode 11u is formed on the second surface 1s2 of the semiconductor substrate 1. A main current flows through the upper electrode 11u. A third wiring circuit 6c is connected to the upper electrode 11u via a fifth joint 5e. The third wiring circuit 6c extends in the x-direction.

[0019] The semiconductor substrate 1 is a so-called power semiconductor substrate 1 that controls electric power. Any material may be used as a material constituting the semiconductor substrate 1. Materials such as silicon (Si), silicon carbide (SiC), gallium nitride (GaN), and gallium oxide (GaO) may be used as a material constituting the semiconductor substrate 1.

[0020] The type of semiconductor element formed on the semiconductor substrate 1 is not particularly limited, but may be, for example, a vertical semiconductor element. In this case, a main current flows in the z direction (thickness direction) of the semiconductor substrate 1. The semiconductor substrate 1 in the first embodiment is a transistor having a control electrode, but may be a diode or have other functions as long as it is a vertical semiconductor element. For example, an IGBT (Insulated Gate Bipolar Transistor), a MOSFET (Metal Oxide Semiconductor Field Effect Transistor), etc. may be used as the semiconductor substrate 1.

[0021] The material constituting the electrode 11 is preferably a material having high electrical and thermal conductivity. The material constituting the electrode 11 may include, for example, any one of aluminum (Al), an aluminum alloy, copper (Cu), and a copper alloy. The electrode 11 may have a two-layer structure of Al / Cu, or a multi-layer structure including any one of gold (Au) and silver (Ag).

[0022] The electrode 11 may include a diffusion prevention layer. The diffusion prevention layer may include, for example, titanium (Ti) or the like. Nickel (Ni) silicide may be used as an underlayer of the electrode 11 to make ohmic contact with the semiconductor substrate 1. The electrode 11 may include a thin surface layer to prevent oxidation of the electrode 11 or to improve the bondability. The material constituting the surface layer is, for example, a precious metal such as gold.

[0023] In the semiconductor device 100a according to the first embodiment, there is no particular restriction on the electrode 11. For example, there is no particular restriction on the locations of the first electrode 11a and the second electrode 11b. Specifically, as shown in Fig. 2, the second electrode 11b as a control electrode may be disposed at a corner on the first surface 1s1, or may be disposed at the center of the first surface 1s1.

[0024] The shape of the second electrode 11b may be any shape. For example, the shape of the second electrode 11b may be a rectangle as shown in Fig. 2, or may be a circle, an ellipse, or a combination of an ellipse and a rectangle. The shape of the second electrode 11b may be a hexagon.

[0025] As shown in FIG. 1, the mounting board 2 has a conductive part 20, a thermally conductive insulating layer 30, and a support layer 40. The conductive part 20 has a front surface, a back surface 20s2, and a side surface 20s3. The front surface faces the first surface 1s1 of the semiconductor substrate 1. In other words, the main surface 20s1 of the mounting board 2 is composed of the front surface of the conductive part 20. The back surface 20s2 is the surface opposite to the front surface of the conductive part 20. The side surface 20s3 is a surface that connects the front surface and the back surface 20s2.

[0026] 1, the thermally conductive insulating layer 30 is connected to the back surface 20s2 of the conductive portion 20. The support layer 40 is connected to the surface of the thermally conductive insulating layer 30 opposite to the surface to which the conductive portion 20 is connected. The surface of the support layer 40 opposite to the surface to which the thermally conductive insulating layer 30 is connected is exposed from the sealing resin 7.

[0027] The conductive portion 20 includes a first conductive portion 20a and a second conductive portion 20b. The first conductive portion 20a is disposed apart from the second conductive portion 20b. The first conductive portion 20a and the second conductive portion 20b may be insulated from each other. As shown in FIG. 1, the space between the first conductive portion 20a and the second conductive portion 20b is preferably filled with an insulating material such as silicone gel or epoxy resin. In the semiconductor device 100a according to the first embodiment, the insulating material filled between the first conductive portion 20a and the second conductive portion 20b may be, for example, a sealing resin 7 as shown in FIG. 1.

[0028] An insulating material may be filled between the first conductive portion 20a and the second conductive portion 20b at any stage in the manufacturing process of the semiconductor device 100a. For example, an insulating material may be filled between the first conductive portion 20a and the second conductive portion 20b at an early stage in the manufacturing process of the semiconductor device 100a. For example, an insulating material may be filled between the first conductive portion 20a and the second conductive portion 20b at a stage close to the final process in the manufacturing process of the semiconductor device 100a.

[0029] From the standpoint of heat resistance, if the insulating material filled between the first conductive portion 20a and the second conductive portion 20b is silicone gel, it is preferable to fill the insulating material after the semiconductor device 100a has undergone a process in which it is treated at high temperature.

[0030] 3, a recess 21 is formed on the main surface 20s1 of the mounting substrate 2. That is, the recess 21 is formed on the surface of the conductive portion 20. In the first conductive portion 20a, the main surface 20s1 includes a first electrode side surface 20as1 and a first wiring circuit side surface 20as2. The recess 21 is formed between the first electrode side surface 20as1 and the first wiring circuit side surface 20as2. The recess 21 is preferably filled with a sealing resin 7.

[0031] In the second conductive portion 20b, the main surface 20s1 includes a second electrode side surface 20bs1 and a second wiring circuit side surface 20bs2. A recess 21 is formed between the second electrode side surface 20bs1 and the second wiring circuit side surface 20bs2.

[0032] The conductive portion 20 is connected to the electrode 11. Specifically, the first electrode 11a is connected to the first electrode side surface 20as1 of the first conductive portion 20a via a first joint portion 5a. The second electrode 11b is connected to the second electrode side surface 20bs1 of the second conductive portion 20b via a second joint portion 5b.

[0033] That is, in plan view from the z direction, the first electrode 11a is disposed at a position overlapping the first electrode side surface 20as1 of the first conductive portion 20a, and the second electrode 11b is disposed at a position overlapping the second electrode side surface 20bs1 of the second conductive portion 20b.

[0034] As shown in FIG. 1, the first wiring circuit 6a is connected to the first wiring circuit side surface 20as2 via the third joint 5c. The first wiring circuit 6a extends in the x direction. The second wiring circuit 6b is connected to the second wiring circuit side surface 20bs2 via the fourth joint 5d. The second wiring circuit 6b extends in the -x direction. In this manner, the first electrode 11a, which is the main electrode, is electrically and mechanically connected to the first conductive portion 20a, and the second electrode 11b, which is the control electrode, is electrically and mechanically connected to the second conductive portion 20b.

[0035] The material constituting the conductive portion 20 is preferably a material having high electrical conductivity and thermal conductivity. The material constituting the conductive portion 20 may include, for example, any one of aluminum (Al), an aluminum alloy, copper (Cu), and a copper alloy.

[0036] The thermally conductive insulating layer 30 is preferably made of a material having adhesive, electrical insulating, and thermally conductive functions. The material constituting the thermally conductive insulating layer 30 may be, for example, a thermosetting resin sheet containing an inorganic filler, an inorganic molded body sheet impregnated with a thermosetting resin, or a coating film. The thermally conductive insulating layer 30 fixes the first conductive portion 20a and the second conductive portion 20b that are spaced apart from each other.

[0037] A cooler (not shown) may be connected to the lower surface of the support layer 40. The support layer 40 may be made of a material capable of conducting heat to the cooler. Specifically, the material constituting the support layer 40 may be a thin metal plate or metal foil containing copper, aluminum, or an alloy thereof, which have high thermal conductivity. The support layer 40 accounts for most of the mechanical strength of the semiconductor device 100a. Therefore, it is preferable that the support layer 40 has high mechanical strength.

[0038] In the mounting substrate 2, the conductive section 20, the thermally conductive insulating layer 30, and the support layer 40 are bonded together by the adhesive function of the thermally conductive insulating layer 30. Specifically, the conductive section 20, the thermally conductive insulating layer 30, and the support layer 40 are bonded together by applying pressure and heat.

[0039] The members constituting the first wiring circuit 6a, the second wiring circuit 6b, and the third wiring circuit 6c may be, for example, conductive lead frames. The first wiring circuit 6a, the second wiring circuit 6b, and the third wiring circuit 6c are preferably arranged parallel to the main surface 20s1. In particular, the first wiring circuit 6a and the third wiring circuit 6c are preferably shaped like a flat plate. In this way, parasitic inductance is reduced.

[0040] The sealing resin 7 covers the semiconductor substrate 1, the mounting substrate 2, a part of the first wiring circuit 6a, a part of the second wiring circuit 6b, and a part of the third wiring circuit 6c. This improves the insulation of the semiconductor device 100a and reduces the influence of the external environment such as humidity and contamination.

[0041] The first wiring circuit 6a extends from the first wiring circuit side surface 20as2 of the first conductive portion 20a to the outside of the sealing resin 7. The second wiring circuit 6b extends from the second wiring circuit side surface 20bs2 of the second conductive portion 20b to the outside of the sealing resin 7. The third wiring circuit 6c extends from the second surface 1s2 of the semiconductor substrate 1 to the outside of the sealing resin 7.

[0042] To enable connection to an external device outside the sealing resin 7, a portion of each of the first wiring circuit 6a, the second wiring circuit 6b, and the third wiring circuit 6c extends outward from the surface of the sealing resin 7. The first wiring circuit 6a, the second wiring circuit 6b, and the third wiring circuit 6c may be bent in the portions extending outward from the sealing resin 7, for example, by forming.

[0043] An example of a material constituting the joint 5 is solder. However, since solder has a relatively high thermal resistance, materials other than solder may be used as the material constituting the joint 5 of the semiconductor device 100a according to the first embodiment. Also, from the viewpoint of long-term reliability of the joint 5, materials other than solder may be used. The thermal resistance is determined by the thermal conductivity, the joint thickness in the z direction, and the cross-sectional area of ​​the joint 5 in the x and y directions.

[0044] In particular, when the third joint portion 5c, the fourth joint portion 5d, and the fifth joint portion 5e are formed using solder, remelting of the solder may occur depending on the process temperature and temperature profile in the manufacturing process of the semiconductor device 100a. Therefore, a material other than solder may be used to form the third joint portion 5c, the fourth joint portion 5d, and the fifth joint portion 5e of the semiconductor device 100a according to the first embodiment.

[0045] For example, a sintered material containing fine particles of silver (Ag) or copper (Cu) is preferable as a material for forming the joint 5 of the semiconductor device 100a according to the first embodiment. By forming the joint 5 using a sintered material, the joint thickness becomes thin. In addition, the sintered material has high thermal conductivity. As a result, the joint 5 has low thermal resistance. When forming the joint 5, there are no particular conditions for pressurization or non-pressurization, process temperature, or temperature profile.

[0046] The joint 5 may be formed by liquid phase diffusion of Cu-Sn or the like. In this way, the joint thickness is reduced, so that the thermal resistance at the joint 5 can be further reduced.

[0047] To further suppress the thermal resistance, the joint 5 may not be formed. The members constituting the semiconductor device 100a may be directly joined by a solid-state reaction. Specifically, the first electrode 11a and the first conductive portion 20a may be directly connected by a solid-state reaction without the first joint 5a.

[0048] During operation of the semiconductor device 100a, the semiconductor substrate 1 generates heat. The heat generated in the semiconductor substrate 1 passes through the electrode 11. The amount of heat passing through the second electrode 11b, which is a control electrode, is smaller than the amount of heat passing through the first electrode 11a, which is a main electrode. Therefore, when forming the first bonding portion 5a and the second bonding portion 5b, the first bonding portion 5a and the second bonding portion 5b do not need to be made of the same material. However, from the viewpoint of shortening the manufacturing process, it is preferable that the first bonding portion 5a and the second bonding portion 5b are made of the same material.

[0049] From the viewpoint of shortening the manufacturing process, the material constituting the third bonding portion 5c, the fourth bonding portion 5d, and the fifth bonding portion 5e may be the same material as that of the first bonding portion 5a and the second bonding portion 5b. The lead frame may be directly bonded by ultrasonic bonding or laser welding without forming the third bonding portion 5c, the fourth bonding portion 5d, and the fifth bonding portion 5e.

[0050] The material constituting the sealing resin 7 may be, for example, a thermosetting resin such as an epoxy resin. The sealing resin 7 is formed, for example, by transfer molding. As will be described later, the sealing resin 7 may also be formed by case molding.

[0051] 1 and 3, the semiconductor device 100a according to the first embodiment is characterized in that a recess 21 is formed in the main surface 20s1 of the mounting substrate 2. The recess 21 is disposed at a position overlapping the electric field intensity mitigating portion 12 in a plan view of the first surface 1s1.

[0052] As described above, the electric field intensity mitigating section 12 mitigates the electric field intensity formed on the back surface of the semiconductor substrate 1. However, when the mounting substrate 2 is disposed near the electric field intensity mitigating section 12, the mounting substrate 2 affects the electric field intensity of the electric field intensity mitigating section 12. As a result, the voltage resistance of the semiconductor device 100a may be deteriorated.

[0053] In the semiconductor device 100a according to the first embodiment, the recess 21 is formed on the main surface 20s1 of the mounting substrate 2, thereby suppressing the influence of the mounting substrate 2 on the electric field intensity mitigating portion 12. As a result, the voltage resistance of the semiconductor device 100a is improved.

[0054] 3, the recess 21 is preferably formed along the shape of the electric field intensity mitigating portion 12. Specifically, the shape of the recess 21 may be annular in a plan view of the main surface 20s1.

[0055] This reduces the influence of the mounting substrate 2 on the electric field intensity mitigating portion 12. In addition, the rear surface (first surface 1s1) of the semiconductor substrate 1 serves as a heat dissipation surface to reduce thermal resistance. As a result, the heat dissipation performance of the semiconductor device 100a is improved.

[0056] 4 and 5, the recess 21 has a bottom surface 21s1 and a side surface 21s2. The bottom surface 21s1 is the surface of the recess 21 that is the farthest in the z direction from the first surface 1s1 and the electric field intensity mitigating portion 12. The side surface 21s2 is a surface that connects the main surface 20s1 and the bottom surface 21s1.

[0057] As shown in FIG. 4 and FIG. 5, the distance t1 from the main surface 20s1 to the bottom surface 21s1 is smaller than the thickness t2 of the conductive portion 20. The thickness t2 of the conductive portion 20 is the distance in the z direction from the front surface 20s2 of the conductive portion 20 to the back surface 20s2. In other words, the inner circumferential surface of the recess 21 is made of a conductor, and the inner circumferential surface is electrically continuous. From a different perspective, for example, in the first conductive portion 20a, the first electrode side surface 20as1 and the first wiring circuit side surface 20as2 are electrically connected via the recess 21. In the second conductive portion 20b, the second electrode side surface 20bs1 and the second wiring circuit side surface 20bs2 are electrically connected via the recess 21.

[0058] The recess 21 has an opening 21a formed on the main surface 20s1. As shown in Figs. 4 and 5, in a cross section along the z direction, the shape of the recess 21 may be narrowed from the opening 21a toward the bottom surface 21s1. Specifically, as shown in Fig. 4, the width w1 of the bottom surface 21s1 is smaller than the width w2 of the opening 21a. In this way, the flow path width of the heat generated in the semiconductor substrate 1 and passing through the electrode 11 is widened, and the thermal resistance of the semiconductor device 100a is reduced.

[0059] As shown in Fig. 6, the shape of the side surface 21s2 may be a linear taper shape in a cross section taken along the z direction. Specifically, the shape of the side surface 21s2 may have a linear portion L in a cross section taken along the z direction. As will be described later, the side surface 21s2 may have an arc shape or an elliptical shape in a cross section taken along the z direction. Specifically, the side surface 21s2 may have a curved portion R in a cross section taken along the z direction.

[0060] The side surface 21s2 may be a surface that combines a straight line portion L and a curved line portion R. In this way, in a cross section in the z direction, the shape of the recess 21 may be a shape that narrows from the opening 21a toward the bottom surface 21s1.

[0061] 6, the width w1 of the recess 21 is preferably larger than the width d of the electric field intensity mitigating portion 12. It is more preferable that the width w1 of the recess 21 is larger than the distance l from the third surface 1s3 to the inner circumferential surface of the electric field intensity mitigating portion 12.

[0062] Figures 7 to 9 are schematic partial cross-sectional views of modified examples of the recess 21 in the semiconductor device 100a according to the first embodiment. Figures 7 to 9 correspond to Figure 6. The semiconductor device 100a shown in Figures 7 to 9 basically has the same configuration as the semiconductor device 100a shown in Figures 1 to 6 and can obtain the same effects, but the shape of the recess 21 is different.

[0063] 7, the bottom surface 21s1 may extend to the side surface 20s3 of the mounting substrate 2. As shown in Fig. 7, the width w1 of the recess 21 is the distance in the x direction from the side surface 21s2 of the recess 21 to the side surface 20s3 of the mounting substrate 2.

[0064] The lead frames of the first wiring circuit 6a, the second wiring circuit 6b, etc. may be connected to the bottom surface 21s1 of the recess 21. However, the surface morphology of the main surfaces 20s1, such as the first wiring circuit side surface 20as2 and the second wiring circuit side surface 20bs2, is superior to that of the bottom surface 21s1 of the recess 21. For this reason, it is preferable that the lead frames of the first wiring circuit 6a, the second wiring circuit 6b, etc. are connected to the main surfaces 20s1, such as the first wiring circuit side surface 20as2 and the second wiring circuit side surface 20bs2.

[0065] 8, in a cross section along the z direction, the side surface 21s2 may have a curved portion R. The side surface 21s2 may be a surface in which a straight portion L and a curved portion R are combined.

[0066] In the recess 21, the shape of the inner side surface 21s2 and the outer side surface 21s2 may be different from each other. Specifically, as shown in FIG. 9, the cross-sectional shape of the inner side surface 21s2 may be a curved shape such as an arc shape or an ellipse shape, and the cross-sectional shape of the outer side surface 21s2 may be a straight line shape. In addition, the outer side surface 21s2 may be inclined in a tapered shape with respect to the bottom surface 21s1. Specifically, the inner side surface 21s2 may have a curved portion R, and the outer side surface 21s2 may have a straight line portion L. In this way, the shape of the recess 21 may be narrowed from the opening 21a toward the bottom surface 21s1 in the cross section in the z direction.

[0067] The recess 21 as described above is preferably filled with an insulating material such as silicone gel or epoxy resin. In the semiconductor device 100a according to the first embodiment, the insulating material filled in the recess 21 may be, for example, a sealing resin 7 as shown in FIG.

[0068] The recess 21 may be formed by any method such as mechanical processing or chemical processing. Specific examples of mechanical processing include removal processing such as cutting, grinding, and milling, and molding processing such as pressing, casting, and forging. Specific examples of chemical processing include etching.

[0069] <Method of Manufacturing Semiconductor Device> In the method for manufacturing the semiconductor device 100a according to the present embodiment, first, a step (S1a) of preparing a semiconductor substrate 1 and a conductive portion 20 is performed. A recess 21 is formed on a surface of the conductive portion 20. The conductive portion 20 includes a first conductive portion 20a and a second conductive portion 20b. The first conductive portion 20a and the second conductive portion 20b are disposed spaced apart from each other.

[0070] If the first conductive portion 20a and the second conductive portion 20b are separated from each other, it becomes difficult to handle the conductive portion 20 during the manufacturing process of the semiconductor device 100a. Therefore, as shown in Fig. 10 and Fig. 11, the first conductive portion 20a and the second conductive portion 20b may be connected via an insulating portion 3 as an insulating material. Fig. 10 is a schematic plan view showing the conductive portion 20 in the semiconductor device 100a according to the first embodiment. Fig. 11 is a schematic cross-sectional view taken along line XI-XI in Fig. 10.

[0071] The insulating section 3 has an adhesive function of connecting the first conductive section 20a and the second conductive section 20b, and an electrical insulating function of insulating the first conductive section 20a and the second conductive section 20b. The material constituting the insulating section 3 is, for example, a thermosetting resin such as an epoxy resin. In this way, by using the insulating section 3, the first conductive section 20a and the second conductive section 20b can be handled as one unit during the manufacturing process of the semiconductor device 100a. In addition, since the first conductive section 20a and the second conductive section 20b are integrated, the mechanical strength of the conductive section 20 is ensured.

[0072] Next, a step (S2a) is performed of mounting semiconductor substrate 1 on conductive portion 20. Specifically, electrode 11 formed on first surface 1s1 of semiconductor substrate 1 and conductive portion 20 are connected via joint 5.

[0073] Next, a step (S3a) of connecting the lead frames is performed. Specifically, the first wiring circuit 6a is connected to the first conductive portion 20a via the joint 5. The second wiring circuit 6b is connected to the second conductive portion 20b via the joint 5. The third wiring circuit 6c is connected to the upper electrode 11u of the semiconductor substrate 1 via the joint 5.

[0074] Next, a step (S4a) of forming sealing resin 7 is performed. Specifically, support layer 40, thermally conductive insulating layer 30, and conductive portion 20 carrying semiconductor substrate 1 described above are arranged in a metal mold for transfer molding. Then, sealing resin 7 is formed by transfer molding.

[0075] In this manner, the semiconductor device 100a according to the first embodiment shown in FIGS. 1 to 6 can be obtained.

[0076] <Modification of the manufacturing method of the semiconductor device> In the modified manufacturing method of the semiconductor device 100a according to the first embodiment, first, a step (S1b) of preparing a semiconductor substrate 1 and a mounting substrate 2 is performed. The mounting substrate 2 has a conductive portion 20, a thermally conductive insulating layer 30, and a support layer 40. A recess 21 is formed on the surface of the conductive portion 20.

[0077] In this manner, during the manufacturing process of the semiconductor device 100a, the conductive portion 20, the thermally conductive insulating layer 30, and the support layer 40 are integrated as the mounting substrate 2, thereby ensuring mechanical strength of the conductive portion 20. Furthermore, since the conductive portion 20, the thermally conductive insulating layer 30, and the support layer 40 are integrated as the mounting substrate 2, the handleability of the conductive portion 20 during the manufacturing process of the semiconductor device 100a is improved. Therefore, it is preferable that the conductive portion 20, the thermally conductive insulating layer 30, and the support layer 40 are manufactured as a single unit into the mounting substrate 2 during the manufacturing process of the semiconductor device 100a.

[0078] Next, a step (S2b) is performed of mounting semiconductor substrate 1 on conductive portion 20. Specifically, electrode 11 formed on first surface 1s1 of semiconductor substrate 1 and conductive portion 20 are connected via joint 5.

[0079] Next, a step (S3b) of connecting the lead frames is performed. Specifically, the first wiring circuit 6a is connected to the first conductive portion 20a via the joint 5. The second wiring circuit 6b is connected to the second conductive portion 20b via the joint 5. The third wiring circuit 6c is connected to the upper electrode 11u of the semiconductor substrate 1 via the joint 5.

[0080] Next, a step (S4b) of forming sealing resin 7 is performed. Specifically, mounting substrate 2 on which semiconductor substrate 1 is mounted is placed in a metal mold for transfer molding. After that, sealing resin 7 is formed by transfer molding.

[0081] In this step (S4b), there is no need to use pressure from the resin to generate the adhesive and electrical insulating functions of the thermally conductive insulating layer 30. Therefore, the conditions for forming the sealing resin 7 by transfer molding in this step (S4b) are relaxed.

[0082] In this manner, the semiconductor device 100a according to the first embodiment shown in FIGS. 1 to 6 can be obtained.

[0083] <Action and effect> A semiconductor device 100a according to the present disclosure includes a semiconductor substrate 1 and a mounting substrate 2. The semiconductor substrate 1 has a first surface 1s1. The mounting substrate 2 has a main surface 20s1. The main surface 20s1 faces the first surface 1s1. An electric field intensity mitigating portion 12 and an electrode 11 are formed on the first surface 1s1. The electrode 11 is connected to the mounting substrate 2. A recess 21 is formed on the main surface 20s1. The recess 21 is disposed at a position overlapping the electric field intensity mitigating portion 12 in a plan view of the first surface 1s1.

[0084] In this manner, the recess 21 is formed, so that the distance between the electric field intensity mitigating portion 12 and the mounting substrate 2 can be made sufficiently large. This reduces the influence of the mounting substrate 2 on the electric field intensity mitigating portion 12. As a result, the voltage resistance of the semiconductor device 100a is improved.

[0085] In the semiconductor device 100a, the direction perpendicular to the first surface 1s1 is defined as the z-direction. The recess 21 has an opening 21a and a bottom surface 21s1. The opening 21a is formed on the main surface 20s1. The bottom surface 21s1 is the furthest from the first surface 1s1 in the z-direction. The width w1 of the bottom surface 21s1 is smaller than the width w2 of the opening 21a.

[0086] This increases the width of the flow path of heat generated in the semiconductor substrate 1 and passing through the electrode 11, thereby reducing the thermal resistance in the semiconductor device 100a.

[0087] In the semiconductor device 100a, the recess 21 has a side surface 21s2. The side surface 21s2 connects the main surface 20s1 and the bottom surface 21s1. The side surface 21s2 has a straight line portion L in a cross section along the z direction.

[0088] In this way, in a cross section in the z direction, the shape of the recess 21 becomes narrower from the opening 21a toward the bottom surface 21s1. As a result, the width of the flow path of the heat generated in the semiconductor substrate 1 and passing through the electrode 11 increases, and the thermal resistance of the semiconductor device 100a decreases.

[0089] In the semiconductor device 100a, the recess 21 has a side surface 21s2. The side surface 21s2 connects the main surface 20s1 and the bottom surface 21s1. The side surface 21s2 has a curved portion R in a cross section along the z direction.

[0090] In this way, in a cross section in the z direction, the shape of the recess 21 becomes narrower from the opening 21a toward the bottom surface 21s1. As a result, the width of the flow path of the heat generated in the semiconductor substrate 1 and passing through the electrode 11 increases, and the thermal resistance of the semiconductor device 100a decreases.

[0091] In the above semiconductor device 100a, the electrode 11 includes a first electrode 11a and a second electrode 11b. The first electrode 11a is a main electrode. The second electrode 11b is a control electrode. The mounting substrate 2 has a conductive portion 20. The conductive portion 20 includes a first conductive portion 20a and a second conductive portion 20b. The first conductive portion 20a is connected to the first electrode 11a. The second conductive portion 20b is connected to the second electrode 11b. The first conductive portion 20a and the second conductive portion 20b are connected via an insulating portion.

[0092] In this way, the first conductive portion 20a and the second conductive portion 20b can be handled as a single unit during the manufacturing process of the semiconductor device 100a. That is, the handleability of the conductive portion 20 during the manufacturing process of the semiconductor device 100a is improved. In addition, since the first conductive portion 20a and the second conductive portion 20b are integrated, the mechanical strength of the conductive portion 20 is ensured.

[0093] In the semiconductor device 100a, the mounting substrate 2 has a thermally conductive insulating layer 30. The thermally conductive insulating layer 30 is connected to the conductive portion 20.

[0094] This ensures the mechanical strength of the conductive portion 20. Furthermore, since the conductive portion 20, the thermally conductive insulating layer 30, and the support layer 40 are integrated into the mounting substrate 2, the handleability of the conductive portion 20 in the manufacturing process of the semiconductor device 100a is improved.

[0095] <Configuration of Modification 1> FIG. 12 is a schematic bottom view of the semiconductor substrate 1 in the first modification of the semiconductor device according to the first embodiment. FIG. 12 corresponds to FIG. 2. FIG. 13 is a schematic plan view of the mounting substrate 2 in the first modification of the semiconductor device 100a according to the first embodiment. FIG. 13 corresponds to FIG. 3. The semiconductor device 100a shown in FIG. 12 and FIG. 13 basically has the same configuration as the semiconductor device 100a shown in FIG. 1 to FIG. 6 and can obtain the same effect, but is different in that the third electrode 11c is formed on the first surface 1s1 of the semiconductor substrate 1 as shown in FIG. 12. In addition to the first electrode 11a and the second electrode 11b, at least one or more third electrodes 11c may be formed on the first surface 1s1. The number of the third electrodes 11c may be one or more.

[0096] 12, the third electrode 11c is disposed on the first surface 1s1 at a distance from the first electrode 11a and the second electrode 11b. In this way, when the third electrode 11c is at the same potential as the first electrode 11a, which is a main electrode, the conductive portion 20 includes the third conductive portion 20c that can be wired in parallel to the second electrode 11b, which is a control electrode. As a result, a semiconductor device 100a with improved noise resistance can be obtained.

[0097] As described above, when the third electrode 11c is formed on the first surface 1s1, the conductive portion 20 further includes a third conductive portion 20c, as shown in Fig. 13. The third conductive portion 20c is connected to the third electrode 11c via a joint portion 5 (not shown).

[0098] As shown in FIG. 13, the third conductive portion 20c is disposed apart from the first conductive portion 20a and the second conductive portion 20b. The first conductive portion 20a, the second conductive portion 20b, and the third conductive portion 20c may be insulated from each other. The spaces between the first conductive portion 20a, the second conductive portion 20b, and the third conductive portion 20c are preferably filled with an insulating material such as silicone gel or epoxy resin. The insulating material filled between the first conductive portion 20a, the second conductive portion 20b, and the third conductive portion 20c may be, for example, the sealing resin 7 shown in FIG. 1.

[0099] In the third conductive portion 20c, the main surface 20s1 includes a third electrode side surface 20cs1 and a third wiring circuit side surface 20cs2. A recess 21 is formed between the third electrode side surface 20cs1 and the third wiring circuit side surface 20cs2.

[0100] In a plan view seen from the z direction, the third electrode 11c is disposed at a position overlapping the third electrode side surface 20cs1 of the third conductive portion 20c. Either a current sense line or a temperature sense line, which is a line from an on-chip diode, may be connected to the third wiring circuit side surface 20cs2. In this manner, the third electrode 11c and the third conductive portion 20c may be electrically and mechanically connected.

[0101] <Action and effect> In the semiconductor device 100a, the electrode 11 includes at least one third electrode 11c. The conductive portion 20 includes a third conductive portion 20c. The third conductive portion 20c is connected to the third electrode 11c.

[0102] In this way, either a current sensing line or a temperature sensing line that is a wiring from an on-chip diode may be connected to the third conductive portion 20c.

[0103] In the semiconductor device 100a, the third electrode 11c has the same potential as the first electrode 11a.

[0104] In this way, it is possible to obtain the semiconductor device 100a with improved noise resistance.

[0105] <Configuration of Modification 2> Fig. 14 is a schematic bottom view of the mounting board 2 in Modification 2 of the semiconductor device 100a according to the first embodiment. Fig. 14 corresponds to Fig. 3. The mounting board 2 shown in Fig. 14 basically has the same configuration as the mounting board 2 in the semiconductor device 100a shown in Figs. 1 to 6, and can obtain the same effects, but is different in that the semiconductor device 100a according to the first embodiment has a plurality of semiconductor substrates 1, as shown in Fig. 14.

[0106] 1 to 6 has one semiconductor substrate 1, the semiconductor device 100a may have a plurality of semiconductor substrates 1. The semiconductor device 100a may have a plurality of semiconductor substrates 1 that are different from each other, or may have a plurality of semiconductor substrates 1 that have different structures. As long as the type of semiconductor substrate 1 has a structure called a vertical type, there are no particular restrictions on the number of parallel substrates and combinations.

[0107] In the second modification of the semiconductor device 100a according to the first embodiment, the circuit configuration of the semiconductor device 100a is a so-called 2-in-1 type in which two semiconductor substrates 1 are mounted on one module. FIG. 14 shows a mounting substrate 2 that configures a half bridge. As shown in FIG. 14, the four first electrode side surfaces 20as1 arranged at both the left and right ends of the mounting substrate 2 may be connected to the semiconductor substrate 1 for the transistor. The four first electrode side surfaces 20as1 arranged in the center of the mounting substrate 2 may be connected to the semiconductor substrate 1 for the transistor.

[0108] Embodiment 2 <Configuration of Semiconductor Device> FIG. 15 is a schematic cross-sectional view of the semiconductor device 100b according to the second embodiment. FIG. 15 corresponds to FIG. 1. FIG. 16 is a schematic plan view of the mounting substrate 2 in the semiconductor device 100b according to the second embodiment. FIG. 16 corresponds to FIG. 3. FIG. 17 is a schematic cross-sectional view taken along line XVII-XVII in FIG. 16. FIG. 17 corresponds to FIG. 4. The semiconductor device 100b shown in FIGS. 15 to 17 basically has the same configuration as the semiconductor device 100a shown in FIGS. 1 and 6 and can achieve the same effects, but is different in that the member connected to the rear surface 20s2 of the conductive portion 20 is an insulating substrate 31, not a thermally conductive insulating layer 30.

[0109] Specifically, in the semiconductor device 100b according to the second embodiment, the mounting substrate 2 has a conductive portion 20, an insulating substrate 31, and a lower electrode 41. As described above, the insulating substrate 31 is connected to the rear surface 20s2 of the conductive portion 20. The lower electrode 41 is connected to the surface of the insulating substrate 31 opposite to the surface to which the conductive portion 20 is connected. The surface of the lower electrode 41 opposite to the surface to which the insulating substrate 31 is connected is exposed from the sealing resin 7.

[0110] The material constituting the insulating substrate 31 may be, for example, any material, and may be a ceramic containing either Si—N or Al—N as a main component. The insulating substrate 31 insulates the conductive portion 20 and the lower electrode 41.

[0111] In the semiconductor device 100b according to the second embodiment, no current flows through the lower electrode 41. However, it is preferable that the lower electrode 41 has high thermal conductivity. In order to suppress warping in the semiconductor device 100b, the linear expansion coefficient of the lower electrode 41 is preferably the same as the linear expansion coefficient of the conductive portion 20. In other words, the material constituting the lower electrode 41 is preferably the same as the material constituting the conductive portion 20. The material constituting the lower electrode may include, for example, any one of aluminum (Al), an aluminum alloy, copper (Cu), and a copper alloy.

[0112] The conductive part 20, the insulating substrate 31, and the lower electrode 41 may be bonded by a direct bonding method or an active metal brazing method. The direct bonding method is a method of bonding two constituent materials by a direct reaction. The active metal brazing method is a method of bonding two constituent materials by a brazing material to which an active metal such as titanium or zirconium is added.

[0113] As shown in FIG. 17, the conductive portion 20, insulating substrate 31, and lower electrode 41 are integrated into the mounting substrate 2, which improves the handleability of the conductive portion 20 in the manufacturing process of the semiconductor device 100b.

[0114] <Action and effect> In the semiconductor device 100b, the mounting substrate 2 has an insulating substrate 31 and a lower electrode 41. The insulating substrate 31 is connected to the conductive portion 20. The lower electrode 41 is connected to the insulating substrate 31. The lower electrode 41 is disposed on the side of the insulating substrate 31 opposite to the side on which the conductive portion 20 is disposed.

[0115] In this manner, the conductive portion 20, the insulating substrate 31, and the lower electrode 41 are integrated into the mounting substrate 2. As a result, the handleability of the conductive portion 20 in the manufacturing process of the semiconductor device 100b is improved.

[0116] Embodiment 3 <Configuration of Semiconductor Device> Fig. 18 is a schematic cross-sectional view of a semiconductor device 100c according to a third embodiment. Fig. 18 corresponds to Fig. 1. The semiconductor device 100c shown in Fig. 18 basically has the same configuration as the semiconductor device 100a shown in Figs. 1 and 6, and can obtain the same effects, but is different in that a sealing resin 7 is formed by a case mold. For example, a potting resin is used as the sealing resin 7. The material constituting the potting resin is, for example, a silicone gel.

[0117] 18, a case 8 is disposed on a support layer 40. The case 8 is disposed so as to surround the semiconductor substrate 1. The case 8 is fixed to the support layer 40 by an adhesive or the like. The case 8 and the support layer 40 fixed by an adhesive or the like are sealed.

[0118] The material constituting the case 8 is preferably, for example, a material that can be injection molded and has high heat resistance and insulating properties. Any material may be used as the material constituting the case 8, and may be, for example, an engineering plastic such as polyphenylene sulfide (PPS).

[0119] <Method of Manufacturing Semiconductor Device> In the manufacturing method of the semiconductor device 100c according to the third embodiment, first, a step (S1c) of preparing a semiconductor substrate 1 and a mounting substrate 2 is performed. The mounting substrate 2 has a conductive portion 20, a thermally conductive insulating layer 30, and a support layer 40. A recess 21 is formed on the surface of the conductive portion 20.

[0120] Next, a step (S2c) is performed of mounting semiconductor substrate 1 on conductive portion 20. Specifically, electrode 11 formed on first surface 1s1 of semiconductor substrate 1 and conductive portion 20 are connected via joint 5.

[0121] Next, a step (S3c) of connecting the lead frames is performed. Specifically, the first wiring circuit 6a is connected to the first conductive portion 20a via the joint 5. The second wiring circuit 6b is connected to the second conductive portion 20b via the joint 5. The third wiring circuit 6c is connected to the upper electrode 11u of the semiconductor substrate 1 via the joint 5.

[0122] Next, a step (S4c) of forming sealing resin 7 is performed. Specifically, case 8 is fixed to support layer 40 by adhesive or the like. Thereafter, case 8 is filled with potting resin or the like.

[0123] In the next step, for example, a lid (not shown) may be mounted on the semiconductor device 100c. Furthermore, the wiring circuit extending outside the sealing resin 7 may be subjected to terminal processing such as bending.

[0124] In this manner, the semiconductor device 100c according to the third embodiment shown in FIG. 18 can be obtained.

[0125] <Action and effect> The semiconductor device 100c further includes a case 8. The case 8 surrounds the sealing resin .

[0126] In this way, a semiconductor device 100c in which the sealing resin 7 is formed by the case molding can be obtained.

[0127] Embodiment 4 <Configuration of Semiconductor Device> Fig. 19 is a schematic cross-sectional view of a semiconductor device 100d according to embodiment 4. Fig. 19 corresponds to Fig. 1. The semiconductor device 100d shown in Fig. 19 basically has a similar configuration to the semiconductor device 100a shown in Fig. 1 to Fig. 6 and can obtain similar effects, but differs in that it includes a cooler 9.

[0128] Specifically, the cooler 9 is connected to the rear surface of the support layer 40 exposed from the sealing resin 7 via the sixth bonding portion 5f. A flow path is formed inside the cooler 9 for circulating a liquid as a refrigerant. The cooler 9 in the semiconductor device 100d according to the fourth embodiment is a cooler 9 for liquid cooling, but may be a cooler 9 for air cooling. In this way, the heat dissipation performance of the semiconductor device 100d is improved.

[0129] The sixth joint portion 5f may be made of solder, and it is particularly preferable that the material has high thermal conductivity and can ensure long-term reliability even when the joint thickness is thin.

[0130] The material constituting the cooler 9 may be any material having high thermal conductivity, and may include, for example, any of aluminum (Al), an aluminum alloy, copper (Cu), and a copper alloy.

[0131] In the semiconductor device 100d according to the fourth embodiment, when the sealing resin 7 is formed by case molding, it is preferable to fill the case 8 with a potting resin after joining the cooler 9 to the mounting substrate 2.

[0132] <Action and effect> The semiconductor device 100d further includes a cooler 9. The cooler 9 is connected to the mounting board 2.

[0133] In this way, the heat dissipation properties of the semiconductor device 100d are improved. Embodiment 5. <Configuration of Semiconductor Device> Fig. 20 is a schematic cross-sectional view of a semiconductor device 100e according to embodiment 5. Fig. 20 corresponds to Fig. 1. The semiconductor device 100e shown in Fig. 20 basically has a similar configuration to the semiconductor device 100a shown in Fig. 1 to Fig. 6, and can obtain similar effects, but differs in that the sealing resin 7 seals a part of the cooler 9.

[0134] The cooler 9 plays the role of the support layer 40 of the mounting substrate 2. Therefore, the heat conductive insulating layer 30 is connected to the cooler 9. Therefore, the cooler 9 does not have to be connected to the heat conductive insulating layer 30 via the sixth joint 5f shown in Fig. 19. In this way, the heat dissipation performance of the semiconductor device 100e is further improved.

[0135] Fig. 21 is a schematic cross-sectional view of a modified example of the semiconductor device 100e according to the fifth embodiment. Fig. 21 corresponds to Fig. 1. The semiconductor device 100e shown in Fig. 21 basically has a similar configuration to the semiconductor device 100e shown in Fig. 20 and can obtain similar effects, but differs in that the sealing resin 7 seals the entire cooler 9.

[0136] <Action and effect> The semiconductor device 100e has at least a part of the cooler 9 sealed therein.

[0137] In this way, the heat dissipation properties of the semiconductor device 100e are further improved. The embodiments disclosed herein should be considered to be illustrative and not restrictive in all respects. Unless inconsistent, at least two of the embodiments disclosed herein may be combined. The basic scope of the present disclosure is indicated by the claims, not the above description, and is intended to include all modifications within the meaning and scope of the claims. [Explanation of symbols]

[0138] 1 semiconductor substrate, 1s1 first surface, 1s2 second surface, 1s3 third surface, 2 mounting substrate, 3 insulating portion, 5 joint portion, 5a first joint portion, 5b second joint portion, 5c third joint portion, 5d fourth joint portion, 5e fifth joint portion, 5f sixth joint portion, 6 wiring circuit, 6a first wiring circuit, 6b second wiring circuit, 6c third wiring circuit, 7 sealing resin, 8 case, 9 cooler, 11 electrode, 11a first electrode, 11b second electrode, 11c third electrode, 11u upper electrode, 12 electric field intensity mitigation portion, 20 conductive portion, 20a first conductive portion, 20as1 first electrode side, 20as2 first wiring circuit side, 20b second conductive portion, 20bs1 second electrode side, 20bs2 second wiring circuit side, 20c third conductive portion, 20cs1 third electrode side, 20cs2 Third wiring circuit side surface, 20s1 main surface, 20s2 back surface, 20s3 side surface, 21 recess, 21a opening, 21s1 bottom surface, 21s2 side surface, 30 thermally conductive insulating layer, 31 insulating substrate, 40 support layer, 41 lower electrode 100a, 100b, 100c, 100d, 100e semiconductor device, d width, l distance, L straight portion, R curved portion, t1 distance, w1 width, w2 width.

Claims

1. a semiconductor substrate having a first surface; a mounting substrate having a main surface facing the first surface, an electric field intensity mitigating portion and an electrode surrounded by the electric field intensity mitigating portion and connected to the mounting substrate are formed on the first surface; the main surface includes a first region in which a recess is formed and a second region other than the first region, the recess is disposed at a position overlapping the electric field intensity mitigating portion in a plan view of the first surface, The second region is connected to the electrode.

2. If the direction perpendicular to the first surface is the z direction, the recess has an opening formed on the main surface and a bottom surface farthest from the first surface in the z direction, The semiconductor device according to claim 1 , wherein the width of said bottom surface is smaller than the width of said opening.

3. the recess has a side surface connecting the main surface and the bottom surface, The semiconductor device according to claim 2 , wherein the side surface has a straight portion in a cross section along the z direction.

4. the recess has a side surface connecting the main surface and the bottom surface, 4. The semiconductor device according to claim 2, wherein the side surface has a curved portion in a cross section along the z direction.

5. The electrodes include a first electrode that is a main electrode and a second electrode that is a control electrode; the mounting substrate has a conductive portion, the conductive portion includes a first conductive portion connected to the first electrode and a second conductive portion connected to the second electrode; The semiconductor device according to claim 1 , wherein the first conductive portion and the second conductive portion are connected via an insulating portion.

6. the electrodes include at least one third electrode; The semiconductor device according to claim 5 , wherein said conductive portion includes a third conductive portion connected to said third electrode.

7. The semiconductor device according to claim 6 , wherein said third electrode is at the same potential as said first electrode.

8. The semiconductor device according to claim 5 , wherein the mounting substrate has a thermally conductive insulating layer connected to the conductive portion.

9. the mounting substrate has an insulating substrate connected to the conductive portion and a lower electrode connected to the insulating substrate, 6. The semiconductor device according to claim 5, wherein the lower electrode is disposed on the side of the insulating substrate opposite to the side on which the conductive portion is disposed.

10. The semiconductor device according to claim 1 , further comprising a sealing resin that seals the semiconductor substrate therein.

11. The semiconductor device according to claim 10 , further comprising a case surrounding the sealing resin.

12. The semiconductor device according to claim 10 , further comprising a cooler connected to the mounting substrate.

13. The semiconductor device according to claim 12 , wherein the sealing resin seals at least a part of the cooler therein.

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