Semiconductor device and semiconductor module

Abstract

A chip-size package type semiconductor device (1) includes a semiconductor layer (40), a plurality of pads (50), and a plurality of metal rewirings (20) located above an upper surface of the semiconductor layer (40), each connected to one or more pads (50). The plurality of metal rewirings (20) includes a first portion (24A) and a second portion (24B) located above the first portion (24A), and in a plan view, the second portion (24B) is located above the first portion (24A). The wiring pattern includes a plurality of first metal rewirings (21) that are contained within a first portion (24A) and whose second portion (24B) has an area smaller than that of the first portion (24A), and each of the plurality of first metal rewirings (21) has one or more linear bends (25) at the boundary between the first portion (24A) and the second portion (24B) on the surface of the first metal rewiring (21), the interior angle of which in the cross section of the first metal rewiring (21) is greater than 180 degrees.

Description

[Technical Field]

[0001] The present disclosure relates to a semiconductor device and a semiconductor module. [Background technology]

[0002] 2. Description of the Related Art Conventionally, a technique for mounting a chip-size package type semiconductor device on a mounting substrate via a solder member is known.

[0003] Furthermore, in the past, in semiconductor devices in which a semiconductor chip is sealed with resin, a base member, etc., a technique has been known in which, when mounting the semiconductor device on a mounting substrate, the terminals of the semiconductor device and the land pattern of the mounting substrate are joined via solder fillets made of solder joining material, at least a portion of which protrudes outside the semiconductor device when viewed in plan (see, for example, Patent Document 1).

[0004] By utilizing this technology, when a semiconductor device in which a semiconductor chip is sealed with resin, a base material, etc. is mounted on a mounting board, it is possible to visually check whether the terminals of the semiconductor device and the land pattern of the mounting board are joined via solder joining material. [Prior art documents] [Patent documents]

[0005] [Patent Document 1] Japanese Patent Publication No. 2020-043236 Summary of the Invention [Problem to be solved by the invention]

[0006] On the other hand, in the past, in chip-size package type semiconductor devices, when mounting the semiconductor device on a mounting substrate, a technology has not been realized in which the terminals of the semiconductor device and the land pattern of the mounting substrate are joined via solder fillets made of solder joining material at least part of which protrudes outside the semiconductor device when viewed in plan.

[0007] For this reason, in conventional chip-size package type semiconductor devices, when the semiconductor device is mounted on a mounting board, it is not possible to visually check whether the terminals of the semiconductor device and the land pattern of the mounting board are joined via a solder joining material.

[0008] Therefore, an object of the present disclosure is to provide a semiconductor device or the like that, when mounting a chip-size package type semiconductor device on a mounting substrate, enables visual confirmation of whether or not the terminals of the semiconductor device and the land pattern of the mounting substrate are joined via a solder joining material. [Means for solving the problem]

[0009] A semiconductor device according to one aspect of the present disclosure is a chip-size package type semiconductor device, comprising: a semiconductor layer; one or more vertical MOS transistors formed in the semiconductor layer; a protective film located above an upper surface of the semiconductor layer and having a plurality of openings; a plurality of pads exposed to the outside of the protective film in each of the plurality of openings, each of the pads functioning as a terminal of one of the one or more vertical MOS transistors; and a plurality of metal rewirings located above the upper surface of the semiconductor layer, each of the metal rewirings being connected to one or more pads that do not overlap one another among the plurality of pads, in a plan view of the semiconductor device, the protective film being included in the semiconductor layer, and each of the plurality of metal rewirings being connected to a front surface of the semiconductor layer. The semiconductor device includes a semiconductor layer including one or more pads connected to the metal rewiring, and the plurality of metal rewirings include a plurality of first metal rewirings each consisting of a first portion and a second portion located above the first portion, wherein, in the planar view, the second portion is included in the first portion and the area of ​​the second portion is smaller than the area of ​​the first portion, and each of the plurality of first metal rewirings has one or more linear bends at the boundary between the first portion and the second portion on the surface of the first metal rewiring, the interior angle of which in a cross section of the first metal rewiring is greater than 180 degrees, and in the planar view, the one or more linear bends have a portion facing the outer periphery of the semiconductor device.

[0010] A semiconductor module according to one embodiment of the present disclosure comprises the above-described semiconductor device and a mounting substrate on which the semiconductor device is mounted face-down, wherein the mounting substrate has a plurality of land patterns corresponding one-to-one to each of a plurality of metal rewirings provided in the semiconductor device, each of the plurality of land patterns being joined to one of the plurality of metal rewirings corresponding to the land pattern via a solder fillet made of a solder bonding material, wherein, in the planar view, the area of ​​each of the plurality of land patterns is larger than the area of ​​the one of the plurality of metal rewirings corresponding to the land pattern, each of the plurality of land patterns having a portion that is not included in the semiconductor device, and the one or more linear bend portions in each of the plurality of first metal rewirings are filled with the solder fillet corresponding to the first metal rewiring.

[0011] A semiconductor module according to one aspect of the present disclosure includes the semiconductor device described above and a mounting substrate on which the semiconductor device is mounted face-down, the mounting substrate having a plurality of land patterns corresponding one-to-one to a plurality of metal rewirings included in the semiconductor device, each of the plurality of land patterns being joined to one of the plurality of metal rewirings corresponding to the land pattern via a solder fillet made of a solder joining material corresponding to the land pattern, in the planar view, an area of ​​each of the plurality of land patterns being larger than an area of ​​the one of the plurality of metal rewirings corresponding to the land pattern, each of the plurality of land patterns having a portion not included in the semiconductor device, the one or more linear bent portions in each of the plurality of first metal rewirings being filled with the solder fillet, in the planar view, Among the land patterns, a first land pattern corresponding to the first specific metal rewiring has a region that extends beyond the first side and outside the semiconductor device, and a region that extends beyond the second side and outside the semiconductor device; among the plurality of land patterns, a second land pattern corresponding to the second specific metal rewiring has a region that extends beyond the second side and outside the semiconductor device, and a region that extends beyond the third side and outside the semiconductor device; among the plurality of land patterns, a third land pattern corresponding to the third specific metal rewiring has a region that extends beyond the third side and outside the semiconductor device, and a region that extends beyond the fourth side and outside the semiconductor device; and among the plurality of land patterns, a fourth land pattern corresponding to the fourth specific metal rewiring has a region that extends beyond the fourth side and outside the semiconductor device, and a region that extends beyond the first side and outside the semiconductor device. [Effects of the Invention]

[0012] According to one aspect of the present disclosure, a semiconductor device or the like is provided that, when mounting a chip-size package type semiconductor device on a mounting substrate, makes it possible to visually check whether or not the terminals of the semiconductor device and the land pattern of the mounting substrate are joined via a solder joining material. [Brief explanation of the drawings]

[0013] [Figure 1A] FIG. 1A is a plan view showing an example of the structure of a semiconductor device according to an embodiment. [Figure 1B] FIG. 1B is a plan view showing an example of the structure of the semiconductor device according to the embodiment. [Figure 2] FIG. 2 is a schematic cross-sectional view showing an example of the structure of the semiconductor device according to the embodiment. [Figure 3] FIG. 3 is a circuit diagram of the semiconductor device according to the embodiment. [Figure 4A] FIG. 4A is a plan view illustrating an example of the structure of a semiconductor module according to an embodiment. [Figure 4B] FIG. 4B is a plan view showing an example of the positional relationship of components of the semiconductor module in a plan view of the semiconductor module according to the embodiment. [Figure 5] FIG. 5 is a cross-sectional view illustrating an example of the structure of a semiconductor module according to an embodiment. [Figure 6A] FIG. 6A is a schematic cross-sectional view showing an example of the structure of the semiconductor device according to the embodiment. [Figure 6B] FIG. 6B is a schematic cross-sectional view showing an example of the structure of the semiconductor device according to the embodiment. [Figure 7] FIG. 7 is a schematic cross-sectional view showing an example of the structure of the semiconductor device according to the embodiment. [Figure 8A] FIG. 8A is a plan view showing an example of the structure of the semiconductor device according to the embodiment. [Figure 8B] FIG. 8B is a plan view showing an example of the structure of the semiconductor device according to the embodiment. [Figure 8C] FIG. 8C is a plan view illustrating an example of the structure of the semiconductor device according to the embodiment. [Figure 8D] FIG. 8D is a plan view illustrating an example of the structure of the semiconductor device according to the embodiment. [Figure 8E] FIG. 8E is a plan view illustrating an example of the structure of the semiconductor device according to the embodiment. [Figure 9] FIG. 9 is a schematic cross-sectional view showing an example of the structure of a semiconductor device according to an embodiment. [Figure 10] FIG. 10 is a schematic cross-sectional view showing an example of the structure of a semiconductor module according to an embodiment. [Figure 11] FIG. 11 is a plan view showing an example of the structure of the semiconductor device according to the embodiment. [Figure 12] FIG. 12 is a plan view showing an example of the structure of the semiconductor device according to the embodiment. [Figure 13] FIG. 13 is a plan view showing an example of the structure of the semiconductor device according to the embodiment. [Figure 14] FIG. 14 is a plan view showing an example of the structure of the semiconductor device according to the embodiment. [Figure 15] FIG. 15 is a plan view showing an example of the structure of the semiconductor device according to the embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0014] (How one aspect of the present disclosure was achieved) As described above, in conventional chip-size package semiconductor devices, when the semiconductor device is mounted on a mounting board, it is not possible to visually check whether the terminals of the semiconductor device and the land pattern of the mounting board are joined via a solder joining material.

[0015] Therefore, in the case of a chip-size package type semiconductor device, in order to check whether the terminals of the semiconductor device and the land pattern of the mounting board are joined via a solder joint material, it is necessary to use, for example, an X-ray transmission device.

[0016] For this reason, in a chip-size package type semiconductor device, it is difficult to efficiently check whether or not the terminals of the semiconductor device and the land pattern of the mounting board are joined via a solder joint material.

[0017] In contrast, in a chip-size package type semiconductor device, if it is possible to visually confirm whether or not the terminals of the semiconductor device and the land pattern of the mounting board are joined via a solder joint material, it is possible to efficiently confirm whether or not the terminals of the semiconductor device and the land pattern of the mounting board are joined via a solder joint material by using, for example, a board visual inspection device that performs automated optical inspection (AOI).

[0018] Therefore, the inventors conducted extensive experiments and studies to realize a technology that can visually check whether or not the terminals of a chip-size package type semiconductor device and the land pattern of a mounting board are joined via a solder joining material.

[0019] As a result, the inventors have come up with the following semiconductor device and the like according to the present disclosure.

[0020] A semiconductor device according to one aspect of the present disclosure is a chip-size package type semiconductor device, comprising: a semiconductor layer; one or more vertical MOS transistors formed in the semiconductor layer; a protective film located above an upper surface of the semiconductor layer and having a plurality of openings; a plurality of pads exposed to the outside of the protective film in each of the plurality of openings, each of the pads functioning as a terminal of one of the one or more vertical MOS transistors; and a plurality of metal rewirings located above the upper surface of the semiconductor layer, each of the metal rewirings being connected to one or more pads that do not overlap one another among the plurality of pads, in a plan view of the semiconductor device, the protective film being included in the semiconductor layer, and each of the plurality of metal rewirings being connected to a front surface of the semiconductor layer. The semiconductor device includes a semiconductor layer including one or more pads connected to the metal rewiring, and the plurality of metal rewirings include a plurality of first metal rewirings each consisting of a first portion and a second portion located above the first portion, wherein, in the planar view, the second portion is included in the first portion and the area of ​​the second portion is smaller than the area of ​​the first portion, and each of the plurality of first metal rewirings has one or more linear bends at the boundary between the first portion and the second portion on the surface of the first metal rewiring, the interior angle of which in a cross section of the first metal rewiring is greater than 180 degrees, and in the planar view, the one or more linear bends have a portion facing the outer periphery of the semiconductor device.

[0021] According to the semiconductor device having the above configuration, when the chip-size package type semiconductor device having the above configuration is mounted on a mounting substrate having a plurality of land patterns corresponding to each of the plurality of metal rewirings, a plurality of solder fillets can be formed, which are made of solder bonding material and at least a portion of which protrudes outside the semiconductor device in a planar view of the semiconductor device, and which are bonded to each of the plurality of metal rewirings and each of the plurality of land patterns.

[0022] Therefore, with the semiconductor device having the above configuration, when the chip-size package type semiconductor device having the above configuration is mounted on a mounting substrate, the multiple pads that function as terminals of the semiconductor device can be joined to the multiple land patterns of the mounting substrate via the multiple solder fillets.

[0023] Therefore, according to the semiconductor device having the above configuration, when mounting a chip-size package type semiconductor device on a mounting substrate, it is possible to visually check whether the terminals of the semiconductor device and the land pattern of the mounting substrate are joined via a solder joining material.

[0024] Furthermore, as described above, according to the semiconductor device having the above configuration, when the chip-size package type semiconductor device having the above configuration is mounted on a mounting substrate, the terminals of the semiconductor device and the land pattern of the mounting substrate can be joined via the solder fillets.

[0025] Therefore, with a semiconductor device having the above configuration, excessive concentration of stress in the bonding area between the terminal of the semiconductor device and the land pattern of the mounting substrate can be suppressed compared to a semiconductor device in which the terminal of the semiconductor device and the land pattern of the mounting substrate are bonded via a solder bonding material in a state in which the solder fillet is not formed.

[0026] Therefore, the semiconductor device having the above configuration can improve the reliability of the semiconductor module formed by joining the semiconductor device and the mounting substrate.

[0027] Generally, a metal rewiring having a linear bent portion is more firmly bonded to a bonding material than a metal rewiring having no linear bent portion.

[0028] In the semiconductor device having the above configuration, a plurality of the metal rewirings are first metal rewirings having one or more linear bent portions.

[0029] Therefore, in the semiconductor device having the above configuration, the bonding between the metal rewiring and the solder fillet can be made relatively strong.

[0030] Therefore, the semiconductor device having the above configuration can further improve the reliability of the semiconductor module formed by joining the semiconductor device and the mounting substrate.

[0031] Furthermore, the length of the second portion in a direction in which a normal line extends from the upper surface of the semiconductor layer may be longer than the length of the first portion in the direction in which the normal line extends.

[0032] This allows the solder fillets joined to each of the plurality of first metal redistribution lines to be relatively high.

[0033] This further reduces excessive stress concentration in the bonding area between the terminals of the semiconductor device and the land pattern of the mounting board.

[0034] Therefore, the semiconductor device having the above configuration can further improve the reliability of the semiconductor module formed by joining the semiconductor device and the mounting substrate.

[0035] Furthermore, a region of the side surface of the second portion that faces the outer periphery of the semiconductor device in the plan view may have an elevation angle of less than 90 degrees with respect to the top surface of the semiconductor layer.

[0036] This can improve the bonding strength between the solder fillet and the first metal rewiring.

[0037] Furthermore, in the planar view, the outer periphery of the protective film may be located inside the outer periphery of the semiconductor layer, and the bottom surface of the first portion may be closer to the top surface of the semiconductor layer than the pad in the direction in which the normal extends, and may be contained within the semiconductor layer but not contained within the outer periphery of the protective film in the planar view.

[0038] This allows the solder fillets joined to each of the plurality of first metal redistribution lines to be made even taller.

[0039] This further reduces excessive stress concentration in the bonding area between the terminals of the semiconductor device and the land pattern of the mounting board.

[0040] Therefore, the semiconductor device having the above configuration can further improve the reliability of the semiconductor module formed by joining the semiconductor device and the mounting substrate.

[0041] Furthermore, in the plan view, the first portion may have an outer periphery that is not included in the outer periphery of the protective film, and the second portion may be included in the outer periphery of the protective film.

[0042] Furthermore, each of the plurality of metal rewirings may have a multilayer structure including a first metal layer made of a first metal that does not contain gold and a second metal layer made of a second metal that contains gold, and a first region that coincides with a side surface of the semiconductor layer in the planar view may be present on the side surface of the first portion, and the first metal may be exposed in at least a portion of the first region.

[0043] Generally, when the solder joint material is a gold-tin solder, the solder joint material does not join to metals that do not contain gold.

[0044] Therefore, in the semiconductor device having the above configuration, when the solder joint material is gold-tin solder, it is possible to prevent the solder joint material from coming into contact with the side surface of the semiconductor layer.

[0045] Furthermore, each of the plurality of metal rewirings may have a multilayer structure including a first metal layer made of a first metal that does not contain gold and a second metal layer made of a second metal that contains gold, and the side surface of the first portion may be located inside the side surface of the semiconductor layer in the planar view, and the first metal may not be exposed over the entire side surface of the first portion, but the second metal may be exposed.

[0046] Generally, when the solder joint material is a gold-tin solder, the metal containing gold and the solder joint material are well joined.

[0047] Therefore, in the semiconductor device having the above configuration, when the solder joint material is gold-tin solder, the joint between the metal rewiring and the solder fillet can be made relatively strong.

[0048] Therefore, the semiconductor device having the above configuration can further improve the reliability of the semiconductor module formed by joining the semiconductor device and the mounting substrate.

[0049] Furthermore, in the planar view, the one or more linear bend portions may further have a portion facing the center of the semiconductor device, and the shortest distance between the portion of the one or more linear bend portions facing the outer periphery of the semiconductor device and the outer periphery of the first portion may be longer than the shortest distance between the portion of the one or more linear bend portions facing the center of the semiconductor device and the outer periphery of the first portion.

[0050] This makes it possible to further strengthen the bond between the first metal rewiring and the solder fillet.

[0051] Therefore, the semiconductor device having the above configuration can further improve the reliability of the semiconductor module formed by joining the semiconductor device and the mounting substrate.

[0052] The number of the plurality of metal rewirings may be equal to the number of the plurality of pads.

[0053] This allows all of the pads of the semiconductor device to be effectively utilized in a semiconductor module formed by bonding the semiconductor device to a mounting board.

[0054] Therefore, with the semiconductor device having the above configuration, it is possible to realize a semiconductor module with better characteristics than when not all of the plurality of pads of the semiconductor device can be effectively utilized in the semiconductor module.

[0055] Furthermore, all of the plurality of metal rewirings may be the plurality of first metal rewirings.

[0056] This makes it possible to make the bonding between the metal rewirings and the solder fillets relatively strong in all of the multiple metal rewirings.

[0057] Therefore, the semiconductor device having the above configuration can further improve the reliability of the semiconductor module formed by joining the semiconductor device and the mounting substrate.

[0058] Further, in the planar view, the semiconductor layer is rectangular, and the plurality of pads include a first pad that does not have any other pads between a first side of the semiconductor layer and a second side of the semiconductor layer that is perpendicular to the first side, a second pad that does not have any other pads between the second side and a third side of the semiconductor layer that is perpendicular to the second side, a third pad that does not have any other pads between the third side and a fourth side of the semiconductor layer that is perpendicular to the third side, and a fourth pad that does not have any other pads between the fourth side and the first side, and among the plurality of metal rewirings, a first specific metal rewiring connected to the first pad, a second specific metal rewiring connected to the second pad, a third specific metal rewiring connected to the third pad, and a fourth specific metal rewiring connected to the fourth pad may each be any of the plurality of first metal rewirings.

[0059] This makes it possible to make the bonding between the metal rewirings and the solder fillets relatively strong in the four metal rewirings located at the four corners of the rectangular semiconductor device when viewed from above.

[0060] Therefore, the semiconductor device having the above configuration can further improve the reliability of the semiconductor module formed by joining the semiconductor device and the mounting substrate.

[0061] Furthermore, each of the first specific metal redistribution line, the second specific metal redistribution line, the third specific metal redistribution line, and the fourth specific metal redistribution line may be connected to two or more pads among the plurality of pads.

[0062] Furthermore, at least one of the one or more specific pads among the plurality of pads, excluding the first pad, the second pad, the third pad, and the fourth pad, may not be connected to any of the plurality of metal rewirings.

[0063] This allows at least one pad to be left unconnected to the metal rewiring, while still making it possible to achieve relatively strong bonds between the metal rewirings and the solder fillets in the four metal rewirings located at the four corners of the semiconductor device, which is rectangular in plan view.

[0064] Therefore, with the semiconductor device having the above configuration, it is possible to reduce the cost of forming the metal rewiring while maintaining the reliability of the semiconductor module formed by bonding the semiconductor device and the mounting substrate.

[0065] Furthermore, at least one of the one or more specific pads among the plurality of pads, excluding the first pad, the second pad, the third pad, and the fourth pad, may be connected to a second metal rewiring among the plurality of metal rewirings that is not one of the plurality of first metal rewirings and does not have the one or more linear bend portions.

[0066] This allows the metal rewiring connected to at least one of the one or more specific pads to be a second metal rewiring that is smaller than the first metal rewiring in a plan view of the semiconductor device.

[0067] Therefore, according to the semiconductor device having the above configuration, it is possible to suppress an increase in the area of ​​the semiconductor device in a plan view.

[0068] A semiconductor module according to one embodiment of the present disclosure comprises the above-described semiconductor device and a mounting substrate on which the semiconductor device is mounted face-down, wherein the mounting substrate has a plurality of land patterns corresponding one-to-one to each of a plurality of metal rewirings provided in the semiconductor device, each of the plurality of land patterns being joined to one of the plurality of metal rewirings corresponding to the land pattern via a solder fillet made of a solder bonding material, wherein, in the planar view, the area of ​​each of the plurality of land patterns is larger than the area of ​​the one of the plurality of metal rewirings corresponding to the land pattern, each of the plurality of land patterns having a portion that is not included in the semiconductor device, and the one or more linear bend portions in each of the plurality of first metal rewirings are filled with the solder fillet corresponding to the first metal rewiring.

[0069] According to the semiconductor module having the above configuration, each of the plurality of metal rewirings and each of the plurality of land patterns are joined via a solder fillet made of a solder joining material, at least a portion of which extends outside the semiconductor device when viewed in a plane.

[0070] Therefore, according to the semiconductor module of the above configuration, when mounting a chip-size package type semiconductor device on a mounting substrate, a semiconductor module is provided that makes it possible to visually check whether the terminals of the semiconductor device and the land pattern of the mounting substrate are joined via solder joining material.

[0071] Furthermore, as described above, according to the semiconductor module having the above configuration, when the chip-size package type semiconductor device having the above configuration is mounted on a mounting substrate, the terminals of the semiconductor device and the land pattern of the mounting substrate are joined via the solder fillets.

[0072] Therefore, with the semiconductor module having the above configuration, it is possible to suppress excessive concentration of stress in the bonding area between the terminal of the semiconductor device and the land pattern of the mounting board, compared to conventional semiconductor modules in which the terminal of the semiconductor device and the land pattern of the mounting board are bonded via a solder bonding material that does not form the solder fillet.

[0073] Therefore, the semiconductor module having the above configuration can improve the reliability of the semiconductor module.

[0074] Generally, a metal rewiring having a linear bent portion is more firmly bonded to a bonding material than a metal rewiring having no linear bent portion.

[0075] In the semiconductor module having the above configuration, a plurality of the metal rewirings are first metal rewirings having one or more linear bent portions.

[0076] Therefore, according to the semiconductor module having the above configuration, the bonding between the metal rewiring and the solder fillet can be made relatively strong.

[0077] Therefore, the semiconductor module having the above configuration can further improve the reliability of the semiconductor module.

[0078] A semiconductor module according to one aspect of the present disclosure includes the semiconductor device described above and a mounting substrate on which the semiconductor device is mounted face-down, the mounting substrate having a plurality of land patterns corresponding one-to-one to a plurality of metal rewirings included in the semiconductor device, each of the plurality of land patterns being joined to one of the plurality of metal rewirings corresponding to the land pattern via a solder fillet made of a solder joining material corresponding to the land pattern, in the planar view, an area of ​​each of the plurality of land patterns being larger than an area of ​​the one of the plurality of metal rewirings corresponding to the land pattern, each of the plurality of land patterns having a portion not included in the semiconductor device, the one or more linear bent portions in each of the plurality of first metal rewirings being filled with the solder fillet, in the planar view, Among the land patterns, a first land pattern corresponding to the first specific metal rewiring has a region that extends beyond the first side and outside the semiconductor device, and a region that extends beyond the second side and outside the semiconductor device; among the plurality of land patterns, a second land pattern corresponding to the second specific metal rewiring has a region that extends beyond the second side and outside the semiconductor device, and a region that extends beyond the third side and outside the semiconductor device; among the plurality of land patterns, a third land pattern corresponding to the third specific metal rewiring has a region that extends beyond the third side and outside the semiconductor device, and a region that extends beyond the fourth side and outside the semiconductor device; and among the plurality of land patterns, a fourth land pattern corresponding to the fourth specific metal rewiring has a region that extends beyond the fourth side and outside the semiconductor device, and a region that extends beyond the first side and outside the semiconductor device.

[0079] According to the semiconductor module having the above configuration, each of the plurality of metal rewirings and each of the plurality of land patterns are joined via a solder fillet made of a solder joining material, at least a portion of which extends outside the semiconductor device when viewed in a plane.

[0080] Therefore, according to the semiconductor module of the above configuration, when mounting a chip-size package type semiconductor device on a mounting substrate, a semiconductor module is provided that makes it possible to visually check whether the terminals of the semiconductor device and the land pattern of the mounting substrate are joined via solder joining material.

[0081] Furthermore, as described above, according to the semiconductor module having the above configuration, when the chip-size package type semiconductor device having the above configuration is mounted on a mounting substrate, the terminals of the semiconductor device and the land pattern of the mounting substrate are joined via the solder fillets.

[0082] Therefore, with a semiconductor module having the above configuration, excessive concentration of stress in the bonding area between the terminal of the semiconductor device and the land pattern of the mounting board can be suppressed compared to a semiconductor device in which the terminal of the semiconductor device and the land pattern of the mounting board are bonded via a solder bonding material that does not form the solder fillet.

[0083] Therefore, the semiconductor module having the above configuration can improve the reliability of the semiconductor module.

[0084] Generally, a metal rewiring having a linear bent portion is more firmly bonded to a bonding material than a metal rewiring having no linear bent portion.

[0085] In the semiconductor module having the above configuration, a plurality of the metal rewirings are first metal rewirings having one or more linear bent portions.

[0086] Therefore, according to the semiconductor module having the above configuration, the bonding between the metal rewiring and the solder fillet can be made relatively strong.

[0087] Therefore, the semiconductor module having the above configuration can further improve the reliability of the semiconductor module.

[0088] Furthermore, with the semiconductor module having the above configuration, the bond between the metal rewiring and the solder fillet can be made relatively strong even if a force is applied to the semiconductor device in either the direction in which the first and third sides extend or the direction in which the second and fourth sides extend, or in both directions.

[0089] Therefore, the semiconductor module having the above configuration can further improve the reliability of the semiconductor module.

[0090] Specific examples of semiconductor devices and the like according to one embodiment of the present disclosure will be described below with reference to the drawings. Each embodiment shown here illustrates one specific example of the present disclosure. Therefore, the numerical values, shapes, components, arrangement and connection of the components, steps (processes), and order of steps shown in the following embodiments are merely examples and are not intended to limit the present disclosure. Furthermore, each figure is a schematic diagram and is not necessarily an exact illustration. In each figure, substantially identical components are assigned the same reference numerals, and redundant explanations are omitted or simplified.

[0091] (Embodiment) <Structure of semiconductor device> FIG. 1A is a plan view showing an example of the structure of a semiconductor device 1 according to an embodiment.

[0092] In FIG. 1A, pads 50A (described later), 50B (described later), 50C (described later), and 50D (described later) are shown with dashed lines as if they could be seen from outside the semiconductor device 1, but in reality, they cannot be seen directly from outside the semiconductor device 1.

[0093] In addition, in Figure 1A, the portions of the protective film 35 (described later) that are hidden by the metal rewiring 20A (described later), the portions that are hidden by the metal rewiring 20B (described later), the portions that are hidden by the metal rewiring 20C (described later), and the portions that are hidden by the metal rewiring 20D (described later) are shown with dashed lines as if they could be seen from outside the semiconductor device 1, but in reality, these portions cannot be seen directly from outside the semiconductor device 1.

[0094] 1B is a plan view showing an example of the structure of the semiconductor device 1 in the case where it is assumed that metal rewirings 20A (described later), 20B (described later), 20C (described later), and 20D (described later) are removed from the semiconductor device 1. In FIG. 1B, electrodes 60A (described later), 60B (described later), and 60C (described later) are shown by dashed lines as if they could be seen from the outside of the semiconductor device 1 in the case where it is assumed that metal rewirings 20A, 20B, 20C, and 20D are removed, but in reality, these electrodes cannot be seen directly from the outside of the semiconductor device 1 in the case where it is assumed that metal rewirings 20A, 20B, 20C, and 20D are removed.

[0095] FIG. 2 is a schematic cross-sectional view showing an example of the structure of the semiconductor device 1, and is a schematic cross-sectional view showing a cross section of the semiconductor device 1 taken along line II in FIG. 1A.

[0096] As shown in Figures 1A, 1B, and 2, the semiconductor device 1 includes a semiconductor layer 40, an oxide film 34, a protective film 35, a metal layer 30, a plurality of electrodes 60 (here, electrodes 60A, 60B, and 60C correspond to each other), a plurality of pads 50 (here, pads 50A, 50B, 50C, and 50D correspond to each other), and a plurality of metal rewirings 20 (here, metal rewirings 20A, 20B, 20C, and 20D correspond to each other).

[0097] Here, we will explain an example in which the multiple electrodes 60 include three electrodes: electrode 60A, electrode 60B, and electrode 60C, but this is just one example, and the multiple electrodes 60 do not necessarily have to be limited to a configuration of three.

[0098] In the following description, except when it is necessary to explicitly distinguish between electrodes 60A, 60B, and 60C, electrodes 60A, 60B, and 60C will also be referred to simply as electrodes 60.

[0099] In addition, here, we will explain an example in which the multiple pads 50 include four pads: pad 50A, pad 50B, pad 50C, and pad 50D, but this is just one example, and the multiple pads 50 do not necessarily have to be limited to a configuration of four.

[0100] In the following description, unless it is necessary to explicitly distinguish between pads 50A, 50B, 50C, and 50D, pads 50A, 50B, 50C, and 50D will also be referred to simply as pads 50.

[0101] Here, the description will be given using an example of a configuration in which the multiple metal rewirings 20 are four, namely, metal rewirings 20A, metal rewirings 20B, metal rewirings 20C, and metal rewirings 20D, but this is just one example, and the multiple metal rewirings 20 do not necessarily have to be limited to a configuration of four.

[0102] In the following description, unless it is necessary to explicitly distinguish between metal rewiring 20A, metal rewiring 20B, metal rewiring 20C, and metal rewiring 20D, metal rewiring 20A, metal rewiring 20B, metal rewiring 20C, and metal rewiring 20D will also be simply referred to as metal rewiring 20.

[0103] The semiconductor layer 40 is configured by stacking a semiconductor substrate 32 and a low concentration impurity layer 33.

[0104] The semiconductor layer 40 may be rectangular in plan view of the semiconductor device 1, as an example that does not necessarily need to be limited to this shape.

[0105] In the following description, the semiconductor layer 40 is assumed to have a rectangular shape when the semiconductor device 1 is seen in a plan view.

[0106] The semiconductor substrate 32 is disposed on the back surface side of the semiconductor layer 40 and is made of silicon of a first conductivity type containing impurities at a first concentration.

[0107] The low-concentration impurity layer 33 is disposed on the front surface side of the semiconductor layer 40, is formed in contact with the semiconductor substrate 32, and is made of silicon of the first conductivity type containing impurities at a second concentration lower than the first concentration. The low-concentration impurity layer 33 may be formed on the semiconductor substrate 32 by, for example, epitaxial growth.

[0108] Generally, there are two types of conductivity types for semiconductors: P type and N type. The first conductivity type may be P type or N type. For convenience of explanation, the first conductivity type will be described as N type and the second conductivity type described below as P type. However, the first conductivity type may be P type and the second conductivity type may be N type.

[0109] The oxide film 34 is disposed on the upper surface of the semiconductor layer 40 and is formed in contact with the low-concentration impurity layer 33 .

[0110] The protective film 35 is located above the semiconductor layer 40, is contained in the semiconductor layer 40 in a plan view of the semiconductor device 1, and has a plurality of openings. More specifically, the protective film 35 is a protective film that covers the upper surfaces of the oxide film 34, the electrode 60A, the electrode 60B, and the electrode 60C, and has an opening that exposes the pad 50A to the outside of the protective film 35, an opening that exposes the pad 50B to the outside of the protective film 35, an opening that exposes the pad 50C to the outside of the protective film 35, and an opening that exposes the pad 50D to the outside of the protective film 35.

[0111] Here, we will explain an example in which the multiple openings are the above-mentioned four openings, but this is just one example, and the multiple openings do not necessarily have to be limited to a configuration in which there are four openings.

[0112] Here, the phrase "protective film 35 covers the oxide film 34 and the upper surfaces of electrode 60A, electrode 60B, and electrode 60C" refers to a state in which protective film 35 is formed on almost the entire surface of semiconductor device 1 except for the openings when viewed from above. "Almost the entire surface of semiconductor device 1" refers to the entire surface of semiconductor device 1, excluding a small peripheral region that remains on each side of semiconductor device 1 after dicing, within the wafer region reserved as a dicing margin when semiconductor device 1 is diced from the wafer. Therefore, in this peripheral region, oxide film 34 is exceptionally exposed to the outside of protective film 35.

[0113] Furthermore, the opening in the protective film 35 in the present disclosure refers to a shape in which the entire periphery of the opening is closed by the protective film 35 in a plan view of the semiconductor device 1. For this reason, a shape in which a part of the periphery overlaps with the exceptional peripheral region where the oxide film 34 is exposed to the outside of the protective film 35 in a plan view of the semiconductor device 1 does not correspond to the opening in the protective film 35 in the present disclosure.

[0114] The metal layer 30 is disposed in contact with the entire rear surface of the semiconductor layer 40 .

[0115] As a non-limiting example, the metal layer 30 may have a multi-layer structure including a layer made of silver or copper. Note that the metal layer 30 may contain trace amounts of other elements that are mixed in as impurities during the manufacturing process.

[0116] Although the semiconductor device 1 is described here as including the metal layer 30, the semiconductor device 1 is not necessarily limited to a configuration including the metal layer 30.

[0117] The metal layer 30 functions as a drain electrode of the vertical MOS transistor 10, which will be described later.

[0118] In a plan view of the semiconductor device 1, a body region 18 of a second conductivity type different from the first conductivity type is formed in the region of the low-concentration impurity layer 33 enclosed by the electrode 60A, ranging from the upper surface of the semiconductor layer 40 to a first predetermined depth.

[0119] In the body region 18, a source region 14 of the first conductivity type containing impurities is formed in a range from the upper surface of the semiconductor layer 40 to a second predetermined depth that does not penetrate the body region 18.

[0120] In addition, in a plan view of the semiconductor device 1, a plurality of gate trenches 17 are formed in the region of the low-concentration impurity layer 33 contained within the body region 18, in a range from the upper surface of the semiconductor layer 40 to a third predetermined depth that penetrates through the source region 14 and the body region 18 to a part of the low-concentration impurity layer 33.

[0121] A gate conductor 15 surrounded by a gate insulating film 16 is formed inside each of the gate trenches 17 .

[0122] Each of the gate conductors 15 is electrically connected to an electrode 60C.

[0123] Gate conductor 15 is made of, by way of example and not limitation, impurity-doped polysilicon.

[0124] In a plan view of the semiconductor device 1, a drain pull-up region 36 of the first conductivity type containing impurities at a third concentration higher than the second concentration is formed in the region of the low-concentration impurity layer 33 that is contained within the electrode 60B, and that extends from the upper surface of the semiconductor layer 40 through the low-concentration impurity layer 33 to the semiconductor substrate 32.

[0125] With the above configuration, the semiconductor device 1 includes the vertical MOS transistor 10 formed in the semiconductor layer 40.

[0126] The electrode 60A is an electrode connected to the source region 14 and the body region 18, and functions as a source electrode of the vertical MOS transistor 10.

[0127] The electrode 60B is an electrode connected to the drain pull-up region 36 and functions as the drain electrode of the vertical MOS transistor 10.

[0128] In the embodiment, the semiconductor device 1 has drain electrodes on both the front and back sides. That is, the semiconductor device 1 has an electrode 60B functioning as a drain electrode on the front side and a metal layer 30 functioning as a drain electrode on the back side.

[0129] The electrode 60C is connected to the gate conductor 15 and functions as the gate electrode of the vertical MOS transistor 10.

[0130] That is, each of the plurality of electrodes 60 functions as an electrode of the vertical MOS transistor 10 .

[0131] Here, the vertical MOS transistor provided in the semiconductor device 1 is explained as an example of a configuration in which the vertical MOS transistor is one of the vertical MOS transistors 10, but this is just one example, and the vertical MOS transistor provided in the semiconductor device 1 does not necessarily have to be limited to a configuration in which there is one or more.

[0132] In addition, here, the configuration will be described as an example in which each of the multiple electrodes 60 functions as an electrode of the vertical MOS transistor 10, but this is one example in which the semiconductor device 1 has one vertical MOS transistor 10. If the semiconductor device 1 has one or more vertical MOS transistors 10, each of the multiple electrodes 60 will function as an electrode of one of the one or more vertical MOS transistors 10.

[0133] The electrode 60A is exposed to the outside of the protective film 35 through two openings in the protective film 35. The upper surface of the electrode 60A exposed to the outside of the protective film 35 through the two openings in the protective film 35 serves as the pads 50A and 50D.

[0134] That is, pad 50A is the portion of the upper surface of electrode 60A that is exposed to the outside of protective film 35 at the opening, and pad 50D is the portion of the upper surface of electrode 60A that is exposed to the outside of protective film 35 at the opening.

[0135] Therefore, the pad 50A functions as the source terminal of the vertical MOS transistor 10. The pad 50D also functions as the source terminal of the vertical MOS transistor 10.

[0136] The electrode 60B is exposed to the outside of the protective film 35 through an opening in the protective film 35. The upper surface of the electrode 60B exposed to the outside of the protective film 35 through the opening in the protective film 35 serves as a pad 50B.

[0137] That is, the pad 50B is a portion of the upper surface of the electrode 60B that is exposed to the outside of the protective film 35 at the opening.

[0138] Therefore, the pad 50B functions as the drain terminal of the vertical MOS transistor 10.

[0139] The electrode 60C is exposed to the outside of the protective film 35 through an opening in the protective film 35. The upper surface of the electrode 60C exposed to the outside of the protective film 35 through the opening in the protective film 35 serves as a pad 50C.

[0140] That is, the pad 50C is a portion of the upper surface of the electrode 60C that is exposed to the outside of the protective film 35 at the opening.

[0141] Therefore, the pad 50C functions as the gate terminal of the vertical MOS transistor 10.

[0142] That is, each of the pads 50 functions as a terminal of the vertical MOS transistor 10 .

[0143] Here, the description will be given taking as an example a configuration in which each of the multiple pads 50 functions as a terminal of the vertical MOS transistor 10, but this is one example in which the semiconductor device 1 has one vertical MOS transistor 10. In the case where the semiconductor device 1 has one or more vertical MOS transistors 10, each of the multiple pads 50 functions as a terminal of one of the one or more vertical MOS transistors 10.

[0144] If the semiconductor device 1 further includes one or more elements other than the vertical MOS transistor, the pads 50 may include some that function as terminals of the elements.

[0145] FIG. 3 is a circuit diagram of the semiconductor device 1. As shown in FIG.

[0146] As shown in FIG. 3, the semiconductor device 1 includes a vertical MOS transistor 10, a pad 50A and a pad 50D that function as the source terminal of the vertical MOS transistor 10, a pad 50B that functions as the drain terminal of the vertical MOS transistor 10, and a pad 50C that functions as the gate terminal of the vertical MOS transistor 10.

[0147] 1A, 1B, and 2, the structure of the semiconductor device 1 will be described further.

[0148] The metal rewiring 20A is located above the upper surface of the semiconductor layer 40 and is connected to the pad 50A.

[0149] The metal rewiring 20A is contained in the semiconductor layer 40 in a plan view of the semiconductor device 1, and contains the pad 50A.

[0150] The metal rewiring 20B is located above the upper surface of the semiconductor layer 40 and is connected to the pad 50B.

[0151] The metal rewiring 20B is contained in the semiconductor layer 40 in a plan view of the semiconductor device 1, and contains the pad 50B.

[0152] The metal rewiring 20C is located above the upper surface of the semiconductor layer 40 and is connected to the pad 50C.

[0153] The metal rewiring 20C is contained in the semiconductor layer 40 in a plan view of the semiconductor device 1, and contains the pad 50C.

[0154] The metal rewiring 20D is located above the upper surface of the semiconductor layer 40 and is connected to the pad 50D.

[0155] The metal rewiring 20D is contained in the semiconductor layer 40 in a plan view of the semiconductor device 1, and contains the pad 50D.

[0156] The multiple metal rewirings 20 include multiple first metal rewirings 21 (here, first metal rewirings 21A, first metal rewirings 21B, first metal rewirings 21C, and first metal rewirings 21D) each consisting of a first portion 24A (here, first portion 24AA, first portion 24BA, first portion 24CA, and first portion 24DA correspond to each other) and a second portion 24B (here, second portion 24AB, second portion 24BB, second portion 24CB, and second portion 24DB correspond to each other) located above the first portion 24A, and in a planar view of the semiconductor device 1, the second portion 24B is included in the first portion 24A, and the area of ​​the second portion 24B is smaller than the area of ​​the first portion 24A.

[0157] That is, at least some of the metal rewirings 20 are first metal rewirings 21.

[0158] Here, we will explain an example of a configuration in which all of the multiple metal rewirings 20 are first metal rewirings 21, but this does not necessarily have to be limited to a configuration in which all of the metal rewirings 20 are first metal rewirings 21.

[0159] In the following description, unless it is necessary to explicitly distinguish between first portion 24AA, first portion 24BA, first portion 24CA, and first portion 24DA, first portion 24AA, first portion 24BA, first portion 24CA, and first portion 24DA will also be referred to simply as first portion 24A.

[0160] Furthermore, in the following description, unless second portion 24AB, second portion 24BB, second portion 24CB, and second portion 24DB are explicitly distinguished from one another, second portion 24AB, second portion 24BB, second portion 24CB, and second portion 24DB will also be simply referred to as second portion 24B.

[0161] Furthermore, in the following description, except when it is necessary to explicitly distinguish between the first metal rewiring 21A, the first metal rewiring 21B, the first metal rewiring 21C, and the first metal rewiring 21D, the first metal rewiring 21A, the first metal rewiring 21B, the first metal rewiring 21C, and the first metal rewiring 21D will also be simply referred to as the first metal rewiring 21.

[0162] Each of the multiple first metal rewirings 21 has one or more linear bends 25 (here, linear bends 25A, 25B, 25C, and 25D correspond to each other) at the boundary between the first portion 24A and the second portion 24B on the surface of the first metal rewiring 21, and the interior angle in the cross section of the first metal rewiring 21 is greater than 180 degrees.

[0163] In the following description, linear bending portion 25A, linear bending portion 25B, linear bending portion 25C, and linear bending portion 25D will also be simply referred to as linear bending portion 25, except when it is necessary to explicitly distinguish between them.

[0164] In a plan view of the semiconductor device 1, the linear bent portion 25 has a portion facing the outer periphery of the semiconductor device 1. However, it is not necessarily required that the linear bent portion 25 exists in all portions of each of the plurality of first metal redistribution lines 21 facing the outer periphery of the semiconductor device 1.

[0165] The height of the first portion 24A (length in the Z direction in Figures 1A, 1B, and 2) may be, as an example that does not necessarily have to be limited, approximately 20 μm, and the height of the second portion 24B may be, as an example that does not necessarily have to be limited, approximately 50 to 90 μm.

[0166] As an example, which is not necessarily limited to this, each of the multiple metal rewirings 20 may be a multilayer structure including a first metal layer 22A made of a first metal that does not contain gold (in FIG. 2, first metal layer 22AA corresponds to first metal layer 22BA) and a second metal layer 22B made of a second metal that contains gold (in FIG. 2, second metal layer 22AB corresponds to second metal layer 22BB).

[0167] Here, each of the multiple metal rewirings 20 is described as having a multilayer structure including a first metal layer 22A and a second metal layer 22B, but each of the multiple metal rewirings 20 does not necessarily have to be limited to a configuration that is a multilayer structure including a first metal layer 22A and a second metal layer 22B.

[0168] In the following description, unless it is necessary to explicitly distinguish between the first metal layer 22AA and the first metal layer 22BA, the first metal layer 22AA and the first metal layer 22BA will also be simply referred to as the first metal layer 22A.

[0169] In addition, in the following description, unless it is necessary to explicitly distinguish between the second metal layer 22AB and the second metal layer 22BB, the second metal layer 22AB and the second metal layer 22BB will also be simply referred to as the second metal layer 22B.

[0170] The first metal layer 22A may be made of, for example and without limitation, copper, aluminum, or titanium. The first metal layer 22A may contain trace amounts of other elements that are mixed in as impurities during the manufacturing process.

[0171] The first metal layer 22A is formed by, for example, plating.

[0172] As a non-limiting example, the second metal layer 22B may be made of gold. Note that the second metal layer 22B may contain trace amounts of other elements that are mixed in as impurities during the manufacturing process.

[0173] The second metal layer 22B is formed by, for example, plating.

[0174] As shown in FIG. 2, each of the plurality of metal redistribution lines 20 may have a multi-layer structure in which the outer layer of the metal redistribution line 20 is the second metal layer 22B and the inner layer is the first metal layer 22A.

[0175] Generally, when the solder joint material is a gold-tin solder, the gold and the solder joint material are well joined.

[0176] Generally, copper, aluminum, and titanium can be plated to form relatively tall structures.

[0177] Therefore, by configuring each of the multiple metal rewirings 20 as described above, when the solder bonding material is gold-tin solder, the bond between the metal rewirings 20 and the solder bonding material can be made relatively strong, and the metal rewirings 20 can be made relatively tall.

[0178] Furthermore, each of the multiple metal redistribution lines 20 may be configured to include, in addition to the first metal layer 22A and the second metal layer 22B, a third metal layer (not shown) sandwiched between the first metal layer 22A and the second metal layer 22B.

[0179] In this case, the third metal layer may be, for example, a metal layer that functions as a barrier metal that prevents the metal of the second metal layer 22B from diffusing into the first metal layer 22A.

[0180] In this case, the third metal layer may be made of nickel, as a non-limiting example, and may contain trace amounts of other elements that are mixed in as impurities during the manufacturing process.

[0181] The third metal layer is formed by, for example, plating.

[0182] <Semiconductor module structure> FIG. 4A is a plan view showing an example of the structure of the semiconductor module 100 according to the embodiment.

[0183] In Figure 4A, the first portion 24AA and the second portion 24AB of the metal rewiring 20A, the first portion 24BA and the second portion 24BB of the metal rewiring 20B, the first portion 24CA and the second portion 24CB of the metal rewiring 20C, and the first portion 24DA and the second portion 24DB of the metal rewiring 20D are shown with dashed lines as if they could be seen in a planar view of the semiconductor module 100, but in reality they cannot be directly seen in a planar view of the semiconductor module 100.

[0184] In addition, in Figure 4A, the portions of solder fillet 70A (described later) that are hidden by semiconductor device 1, the portions of solder fillet 70B (described later) that are hidden by semiconductor device 1, the portions of solder fillet 70C (described later) that are hidden by semiconductor device 1, and the portions of solder fillet 70D (described later) that are hidden by semiconductor device 1 are shown with dashed lines as if they could be seen in a planar view of semiconductor module 100, but in reality, these portions that are hidden by semiconductor device 1 cannot be directly seen in a planar view of semiconductor module 100.

[0185] 4B is a plan view showing an example of the positional relationship between the first portion 24AA, the second portion 24AB, and the linear bend portion 25A of the metal rewiring 20A, the first portion 24BA, the second portion 24BB, and the linear bend portion 25B of the metal rewiring 20B, the first portion 24CA, the second portion 24CB, and the linear bend portion 25C of the metal rewiring 20C, the first portion 24DA, the second portion 24DB, and the linear bend portion 25D of the metal rewiring 20D, the land pattern 80A (described later), the land pattern 80B (described later), the land pattern 80C (described later), the land pattern 80D (described later), and the semiconductor device 1 in a plan view of the semiconductor module 100.

[0186] FIG. 5 is a schematic cross-sectional view showing an example of the structure of the semiconductor module 100, and is a schematic cross-sectional view showing a cross section of the semiconductor module 100 taken along line II-II in FIG. 4A.

[0187] As shown in Figures 4A, 4B, and 5, the semiconductor module 100 includes a semiconductor device 1, a mounting substrate 90, and a plurality of solder fillets 70 (here, solder fillet 70A, solder fillet 70B, solder fillet 70C, and solder fillet 70D).

[0188] In the following description, unless it is necessary to explicitly distinguish between solder fillet 70A, solder fillet 70B, solder fillet 70C, and solder fillet 70D, solder fillet 70A, solder fillet 70B, solder fillet 70C, and solder fillet 70D will also be referred to simply as solder fillet 70.

[0189] The semiconductor device 1 is mounted face down on a mounting substrate 90.

[0190] The mounting substrate 90 has a plurality of land patterns 80 (here, land pattern 80A, land pattern 80B, land pattern 80C, and land pattern 80D correspond one-to-one to each of the plurality of metal rewirings 20 provided in the semiconductor device 1).

[0191] More specifically, the mounting substrate 90 has a land pattern 80A corresponding to the metal rewiring 20A, a land pattern 80B corresponding to the metal rewiring 20B, a land pattern 80C corresponding to the metal rewiring 20C, and a land pattern 80D corresponding to the metal rewiring 20D.

[0192] In the following description, unless it is necessary to explicitly distinguish between land patterns 80A, 80B, 80C, and 80D, land patterns 80A, 80B, 80C, and 80D will also be referred to simply as land patterns 80.

[0193] In a plan view of the semiconductor device 1, the area of ​​each of the plurality of land patterns 80 is larger than the area of ​​the metal rewiring 20 corresponding to that land pattern 80.

[0194] In a plan view of the semiconductor device 1, each of the plurality of land patterns 80 has a portion that is not included in the semiconductor device 1.

[0195] Each of the plurality of solder fillets 70 is made of a solder bonding material, and corresponds one-to-one to each of the plurality of land patterns 80 and each of the plurality of metal rewirings 20, and bonds the corresponding land pattern 80 and the corresponding metal rewiring 20.

[0196] Here, solder fillet 70A corresponds to land pattern 80A and metal rewiring 20A and joins land pattern 80A and metal rewiring 20A, solder fillet 70B corresponds to land pattern 80B and metal rewiring 20B and joins land pattern 80B and metal rewiring 20B, solder fillet 70C corresponds to land pattern 80C and metal rewiring 20C and joins land pattern 80C and metal rewiring 20C, and solder fillet 70D corresponds to land pattern 80D and metal rewiring 20D and joins land pattern 80D and metal rewiring 20D.

[0197] That is, land pattern 80A is joined to metal rewiring 20A via solder fillet 70A, land pattern 80B is joined to metal rewiring 20B via solder fillet 70B, land pattern 80C is joined to metal rewiring 20C via solder fillet 70C, and land pattern 80D is joined to metal rewiring 20D via solder fillet 70D.

[0198] One or more linear bends 25 in each of the plurality of first metal rewirings 21 (here, all of the plurality of metal rewirings 20 are first metal rewirings 21) among the plurality of metal rewirings 20 are filled with a solder fillet 70 corresponding to the first metal rewiring 21.

[0199] Here, the linear bend 25A of the first metal rewiring 21A is filled with a solder fillet 70A, the linear bend 25B of the first metal rewiring 21B is filled with a solder fillet 70B, the linear bend 25C of the first metal rewiring 21C is filled with a solder fillet 70C, and the linear bend 25D of the first metal rewiring 21D is filled with a solder fillet 70D.

[0200] <Consideration> According to the semiconductor device 1 having the above configuration, when the chip-size package type semiconductor device 1 having the above configuration is mounted on a mounting substrate 90 having a plurality of land patterns 80 corresponding to each of the plurality of metal rewirings 20, a plurality of solder fillets 70 can be formed, which are made of solder bonding material and at least a portion of which protrudes outside the semiconductor device 1 in a planar view of the semiconductor device 1, and which are bonded to each of the plurality of metal rewirings 20 and each of the plurality of land patterns 80.

[0201] Therefore, with the semiconductor device 1 having the above configuration, when the chip-size package type semiconductor device 1 having the above configuration is mounted on a mounting substrate 90, the multiple pads 50 that function as terminals of the semiconductor device 1 and the multiple land patterns 80 of the mounting substrate 90 can be joined via the multiple solder fillets 70.

[0202] Therefore, according to the semiconductor device 1 having the above configuration, when mounting the chip-size package type semiconductor device 1 on the mounting substrate 90, it is possible to visually check whether the terminals of the semiconductor device 1 and the land pattern 80 of the mounting substrate 90 are joined via a solder joining material.

[0203] Furthermore, as described above, with the semiconductor device 1 having the above configuration, when the chip-size package type semiconductor device 1 having the above configuration is mounted on a mounting substrate 90, the terminals of the semiconductor device 1 and the land pattern 80 of the mounting substrate 90 can be joined via the solder fillets 70.

[0204] Therefore, with the semiconductor device 1 having the above configuration, excessive concentration of stress in the bonding area between the terminal of the semiconductor device 1 and the land pattern 80 of the mounting substrate 90 can be suppressed compared to a semiconductor device 1 in which the terminal of the semiconductor device 1 and the land pattern 80 of the mounting substrate 90 are bonded via a solder bonding material in a state in which the solder fillet 70 is not formed.

[0205] Therefore, according to the semiconductor device 1 having the above configuration, the reliability of the semiconductor module 100 formed by joining the semiconductor device 1 and the mounting substrate 90 can be improved.

[0206] In general, the metal rewiring 20 having the linear bent portion 25 is bonded to the bonding material more firmly than the metal rewiring 20 having no linear bent portion 25 .

[0207] In the semiconductor device 1 configured as described above, a plurality of the metal rewirings 20 are first metal rewirings 21 having one or more linear bent portions 25 .

[0208] Therefore, according to the semiconductor device 1 having the above configuration, the bonding between the metal rewiring 20 and the solder fillet 70 can be made relatively strong.

[0209] Therefore, according to the semiconductor device 1 having the above configuration, the reliability of the semiconductor module 100 formed by joining the semiconductor device 1 and the mounting substrate 90 can be further improved.

[0210] As shown in FIG. 2, the length of the second portion 24B in the direction in which a normal extends from the upper surface of the semiconductor layer 40 (the Z direction in FIGS. 1A, 1B, and 2) may be longer than the length of the first portion 24A in the direction in which the normal extends.

[0211] This allows the solder fillets 70 joined to each of the plurality of first metal redistribution lines 21 to be relatively high.

[0212] Therefore, excessive concentration of stress in the bonding region between the terminals of the semiconductor device 1 and the land pattern 80 of the mounting substrate 90 can be further suppressed.

[0213] Therefore, according to the semiconductor device 1 having the above configuration, the reliability of the semiconductor module 100 formed by joining the semiconductor device 1 and the mounting substrate 90 can be further improved.

[0214] Incidentally, the shape of the second portion 24B is not necessarily limited to the shapes exemplified in FIGS. 1A, 1B, and 2.

[0215] 6A and 6B are schematic cross-sectional views showing an example of the structure of the semiconductor device 1 when the second portion 24B has another shape.

[0216] As illustrated in Figures 6A and 6B, the second portion 24B may have a shape in which there is a region of the side surface of the second portion 24B that faces the outer periphery of the semiconductor device 1 in a planar view of the semiconductor device 1, where the elevation angle with respect to the top surface of the semiconductor layer 40 is less than 90 degrees.

[0217] This makes it possible to improve the bonding strength between the solder fillet 70 and the first metal rewiring 21.

[0218] As shown in Figures 1A, 1B, and 2, in a planar view of the semiconductor device 1, the outer periphery of the protective film 35 is located inside the outer periphery of the semiconductor layer 40, and the bottom surface of the first portion 24A is closer to the top surface of the semiconductor layer 40 than the pad 50 in the direction in which the normal extends from the top surface of the semiconductor layer 40 (the Z direction in Figures 1A, 1B, and 2), and may be contained within the semiconductor layer 40 but not contained within the outer periphery of the protective film 35 in a planar view of the semiconductor device 1.

[0219] This allows the solder fillets 70 joined to each of the plurality of first metal redistribution lines 21 to be made even higher.

[0220] In this case, as shown in Figures 1A, 1B, and 2, in a planar view of the semiconductor device 1, there may be a portion on the outer periphery of the first portion 24A that is not enclosed within the outer periphery of the protective film 35, and the second portion 24B may be enclosed within the outer periphery of the protective film 35.

[0221] Incidentally, the shape of the first portion 24A is not necessarily limited to the shapes exemplified in FIGS. 1A, 1B, and 2.

[0222] FIG. 7 is a schematic cross-sectional view showing another example of the structure of the semiconductor device 1 when the first portion 24A has another shape.

[0223] As illustrated in FIG. 7, the shape of the first portion 24A may be such that a first region 23 (here, first region 23A corresponds to first region 23B) is present on the side of the first portion 24A and coincides with the side of the semiconductor layer 40 in a planar view of the semiconductor device 1, and the first metal is exposed in at least a part of the first region 23.

[0224] Generally, when the solder joint material is a gold-tin solder, the solder joint material does not join to metals that do not contain gold.

[0225] Therefore, according to the semiconductor device 1 having the above configuration, when the solder joint material is a gold-tin solder, contact between the solder joint material and the side surface of the semiconductor layer 40 can be prevented.

[0226] The shape of the first portion 24A illustrated in FIG. 7 is realized, for example, when dicing the semiconductor device 1 from a wafer, by simultaneously cutting the first portion 24A, the oxide film 34, the semiconductor layer 40, and the metal layer 30 using a dicing blade or the like.

[0227] Conversely, the shape of the first portion 24A may be such that, as shown in Figures 1A, 1B, and 2, the side surface of the first portion 24A is located inside the side surface of the semiconductor layer 40 in a plan view of the semiconductor device 1, and the first metal is not exposed throughout the first portion 24A.

[0228] As described above, in general, when the solder joint material is a gold-tin solder, the metal containing gold and the solder joint material are well joined.

[0229] Therefore, in the semiconductor device 1 having the above configuration, when the solder bonding material is gold-tin solder, the bonding between the metal rewiring 20 and the solder fillet 70 can be made relatively strong.

[0230] Therefore, according to the semiconductor device 1 having the above configuration, the reliability of the semiconductor module 100 formed by joining the semiconductor device 1 and the mounting substrate 90 can be further improved.

[0231] Incidentally, the positional relationship between the first portion 24A and the second portion 24B does not necessarily have to be limited to the shapes exemplified in FIGS. 1A, 1B, and 2.

[0232] Figures 8A to 8E are plan views showing an example of the structure of the semiconductor device 1 when the first portion 24A and the second portion 24B are in a different positional relationship, and Figure 9 is a schematic cross-sectional view showing an example of the structure of the semiconductor device 1 when the first portion 24A and the second portion 24B are in a different positional relationship, and is a schematic cross-sectional view showing a cut surface of the semiconductor device 1 at III-III in Figure 8A.

[0233] 10 is a schematic cross-sectional view showing an example of the structure of the semiconductor module 100 when the semiconductor device 1 has the structure shown in FIG. 8A and FIG.

[0234] In Figures 8A to 8E, the portions of the protective film 35 that are hidden by each first metal rewiring 21 are shown with dashed lines as if they could be seen from outside the semiconductor device 1, but in reality, these portions cannot be seen directly from outside the semiconductor device 1.

[0235] As illustrated in Figures 8A to 8E and Figure 9, in a planar view of the semiconductor device 1, in each first metal rewiring 21, one or more linear bend portions 25 further have a portion facing the center of the semiconductor device 1, and the shortest distance between the portion of one or more linear bend portions 25 facing the outer periphery of the semiconductor device 1 and the outer periphery of the first portion 24A may be longer than the shortest distance between the portion of one or more linear bend portions 25 facing the center of the semiconductor device 1 and the outer periphery of the first portion 24A.

[0236] As a result, as shown in Figure 10, in each first metal rewiring 21, in addition to the portion of the linear bend portion 25 facing the outer periphery of the semiconductor device 1, the portion facing the center of the semiconductor device 1 is also filled with solder fillet 70.

[0237] This makes it possible to make the bond between the first metal rewiring 21 and the solder fillet 70 stronger.

[0238] Therefore, according to the semiconductor device 1 having the above configuration, the reliability of the semiconductor module 100 formed by joining the semiconductor device 1 and the mounting substrate 90 can be further improved.

[0239] As illustrated in Figures 8A to 8C, if one or more linear bend portions 25 have portions facing the outer periphery of each of two different outer peripheries of the semiconductor device 1, the shortest distance between each of those portions and the outer periphery of the first portion 24A may be equal.

[0240] As shown in FIGS. 1A, 1B, and 2, the number of the metal rewirings 20 may be equal to the number of the pads 50.

[0241] This allows all of the pads 50 of the semiconductor device 1 to be used effectively in the semiconductor module 100 formed by joining the semiconductor device 1 and the mounting substrate 90 together.

[0242] Therefore, with the semiconductor device 1 having the above configuration, it is possible to realize a semiconductor module 100 with better characteristics than when it is not possible to effectively utilize all of the multiple pads 50 of the semiconductor device 1.

[0243] FIG. 11 is a plan view showing another example of the structure of the semiconductor device 1 in which the number of the plurality of metal rewirings 20 is equal to the number of the plurality of pads 50. In FIG.

[0244] FIG. 11 is a plan view of the semiconductor device 1 in which the number of the plurality of metal rewirings 20 included in the semiconductor device 1 is 10, and the number of the plurality of pads 50 is also 10, the same number as the number of the plurality of metal rewirings 20.

[0245] In FIG. 11, the pads 50 are shown by dashed lines as if they could be seen from outside the semiconductor device 1, but in reality, they cannot be seen directly from outside the semiconductor device 1.

[0246] In addition, in Figure 11, the parts of the protective film 35 that are hidden by each metal rewiring 20 are shown with dashed lines as if they could be seen from outside the semiconductor device 1, but in reality, these parts cannot be seen directly from outside the semiconductor device 1.

[0247] As shown in FIGS. 1A, 1B, and 2, all of the plurality of metal rewirings 20 may be the plurality of first metal rewirings 21.

[0248] This makes it possible to make the bonding between the metal rewirings 20 and the solder fillets 70 relatively strong in all of the metal rewirings 20 .

[0249] Therefore, according to the semiconductor device 1 having the above configuration, the reliability of the semiconductor module 100 formed by joining the semiconductor device 1 and the mounting substrate 90 can be further improved.

[0250] Figure 12 is a plan view showing an example of the structure of a semiconductor device 1 in which the number of metal rewirings 20 provided in the semiconductor device 1 is 10, all of which are multiple first metal rewirings 21, and the number of pads 50 is 10, the same number as the number of metal rewirings 20.

[0251] In FIG. 12, the pads 50 are shown by dashed lines as if they could be seen from outside the semiconductor device 1, but in reality, they cannot be seen directly from outside the semiconductor device 1.

[0252] 1A, 1B, and 2, the semiconductor layer 40 is rectangular in plan view of the semiconductor device 1, and the plurality of pads 50 include a pad 50A (hereinafter also referred to as a first pad 50A) that does not include any other pad 50 between a first side 61 of the semiconductor layer 40 and a second side 62 of the semiconductor layer 40 perpendicular to the first side 61, a pad 50B (hereinafter also referred to as a second pad 50B) that does not include any other pad 50 between a second side 62 and a third side 63 of the semiconductor layer 40 perpendicular to the second side 62, a pad 50C (hereinafter also referred to as a third pad 50C) that does not include any other pad 50 between the third side 63 and a fourth side 64 of the semiconductor layer 40 perpendicular to the third side 63, and a pad 50D (hereinafter also referred to as a fourth pad 50D) that does not include any other pad 50 between the fourth side 64 and the fourth side 65 of the semiconductor layer 40. and a pad 50D (hereinafter also referred to as the fourth pad 50D) that does not include any other pad 50 between the first side 61 and the first side 61, and among the plurality of metal rewirings 20, the metal rewiring 20A connected to the first pad 50A (hereinafter also referred to as the first specific metal rewiring 20A), the metal rewiring 20B connected to the second pad 50B (hereinafter also referred to as the second specific metal rewiring 20B), the metal rewiring 20C connected to the third pad 50C (hereinafter also referred to as the third specific metal rewiring 20C), and the metal rewiring 20D connected to the fourth pad 50D (hereinafter also referred to as the fourth specific metal rewiring 20D) may each be any of the plurality of first metal rewirings 21.

[0253] This allows the four metal rewirings 20 located at the four corners of the rectangular semiconductor device 1 to have relatively strong bonds between the metal rewirings 20 and the solder fillets 70 when viewed from above.

[0254] Therefore, according to the semiconductor device 1 having the above configuration, the reliability of the semiconductor module 100 formed by joining the semiconductor device 1 and the mounting substrate 90 can be further improved.

[0255] The semiconductor device 1 illustrated in FIG. 12 is another example of the semiconductor device 1 having the above configuration.

[0256] In addition, in this case, the first specific metal rewiring 20A, the second specific metal rewiring 20B, the third specific metal rewiring 20C, and the fourth specific metal rewiring 20D may be connected to two or more pads 50 among the multiple pads 50.

[0257] FIG. 13 is a plan view showing an example of the structure of a semiconductor device 1 in which a first specific metal redistribution line 20A, a second specific metal redistribution line 20B, a third specific metal redistribution line 20C, and a fourth specific metal redistribution line 20D are connected to two or more pads 50 out of a plurality of pads 50.

[0258] In FIG. 13, the pads 50 are shown by dashed lines as if they could be seen from outside the semiconductor device 1, but in reality, they cannot be seen directly from outside the semiconductor device 1.

[0259] In addition, in Figure 13, the parts of the protective film 35 that are hidden by each metal rewiring 20 (including the first specific metal rewiring 20A, the second specific metal rewiring 20B, the third specific metal rewiring 20C, and the fourth specific metal rewiring 20D) are shown with dashed lines as if they could be seen from outside the semiconductor device 1, but in reality, these parts cannot be seen directly from outside the semiconductor device 1.

[0260] The semiconductor device 1 illustrated in Figure 13 is an example of a configuration in which a first specific metal rewiring 20A, a second specific metal rewiring 20B, a third specific metal rewiring 20C, and a fourth specific metal rewiring 20D are each connected to two pads 50.

[0261] Figure 14 is a plan view showing an example of the structure of a semiconductor device 1 in which at least one of the one or more specific pads 50, excluding the first pad 50A, the second pad 50B, the third pad 50C, and the fourth pad 50D, is not connected to any of the multiple metal rewirings 20.

[0262] In Figure 14, of the multiple pads 50, the first pad 50A, the second pad 50B, the third pad 50C, the fourth pad 50D, and the two circular pads 50 are shown with dashed lines as if they could be seen from outside the semiconductor device 1, but in reality, these cannot be seen directly from outside the semiconductor device 1.

[0263] In addition, in Figure 14, the parts of the protective film 35 that are hidden by each metal rewiring 20 are shown with dashed lines as if they could be seen from outside the semiconductor device 1, but in reality, these parts cannot be seen directly from outside the semiconductor device 1.

[0264] As illustrated in FIG. 14, at least one of the one or more specific pads may not be connected to any of the plurality of metal redistribution lines 20.

[0265] This allows at least one pad 50 to be left unconnected to the metal rewiring 20, while making it possible to make the bond between the metal rewiring 20 and the solder fillet 70 relatively strong in the four metal rewirings 20 located at the four corners of the semiconductor device 1, which is rectangular in plan view.

[0266] Therefore, with the semiconductor device 1 having the above configuration, it is possible to reduce the cost of forming the metal rewiring 20 while maintaining the reliability of the semiconductor module 100 formed by joining the semiconductor device 1 and the mounting substrate 90.

[0267] 14 is an example of a configuration in which six of the eight specific pads (in FIG. 14, six oval pads 50 that are not included in any of the metal rewirings 20 in a plan view of the semiconductor device 1) are not connected to any of the multiple metal rewirings 20. Here, these six specific pads are not connected to any of the multiple metal rewirings 20, and therefore are not connected to any of the land patterns 80 on the mounting substrate 90.

[0268] FIG. 15 is a plan view showing another example of the structure of the semiconductor device 1. As shown in FIG.

[0269] In Figure 15, of the multiple pads 50, the first pad 50A, the second pad 50B, the third pad 50C, the fourth pad 50D, and the two circular pads 50 are shown with dashed lines as if they could be seen from outside the semiconductor device 1, but in reality, these cannot be seen directly from outside the semiconductor device 1.

[0270] As shown in FIG. 15, in the semiconductor device 1, at least one of the multiple pads 50 (two circular pads 50 in FIG. 15) among one or more specific pads excluding the first pad 50A, the second pad 50B, the third pad 50C, and the fourth pad 50D may be connected to a second metal rewiring 26 among the multiple metal rewirings 20 that is not the first metal rewiring 21 and does not have a linear bend portion 25.

[0271] This allows the metal rewiring 20 connected to at least one of the one or more specific pads to be the second metal rewiring 26 that is smaller than the first metal rewiring 21 in a plan view of the semiconductor device 1.

[0272] Therefore, according to the semiconductor device 1 having the above configuration, an increase in the area of ​​the semiconductor device 1 in plan view can be suppressed.

[0273] According to the semiconductor module 100 having the configuration disclosed in the embodiment, each of the plurality of metal rewirings 20 and each of the plurality of land patterns 80 are joined via a solder fillet 70 made of a solder joining material, at least a portion of which protrudes outside the semiconductor device 1 when viewed in a plane.

[0274] Therefore, according to the semiconductor module 100 having the above configuration, when mounting the chip-size package type semiconductor device 1 on the mounting substrate 90, it is possible to visually check whether the terminals of the semiconductor device 1 and the land pattern 80 of the mounting substrate 90 are joined via a solder joining material.

[0275] Furthermore, as described above, according to the semiconductor module 100 having the above configuration, when the chip-size package type semiconductor device 1 having the above configuration is mounted on the mounting substrate 90, the terminals of the semiconductor device 1 and the land pattern 80 of the mounting substrate 90 are joined via the solder fillets 70.

[0276] Therefore, with the semiconductor module 100 having the above configuration, it is possible to suppress excessive concentration of stress in the bonding area between the terminal of the semiconductor device 1 and the land pattern 80 of the mounting substrate 90, compared to conventional semiconductor modules in which the terminal of the semiconductor device 1 and the land pattern 80 of the mounting substrate 90 are bonded via a solder bonding material that does not form the solder fillet 70.

[0277] Therefore, according to the semiconductor module 100 having the above configuration, the reliability of the semiconductor module 100 can be improved.

[0278] In general, the metal rewiring 20 having the linear bent portion 25 is bonded to the bonding material more firmly than the metal rewiring 20 having no linear bent portion 25 .

[0279] According to the semiconductor module 100 having the above configuration, a plurality of the metal rewirings 20 are first metal rewirings 21 having one or more linear bent portions 25 .

[0280] Therefore, according to the semiconductor module 100 having the above configuration, the bonding between the metal rewiring 20 and the solder fillet 70 can be made relatively strong.

[0281] Therefore, according to the semiconductor module 100 having the above configuration, the reliability of the semiconductor module 100 can be further improved.

[0282] 4B , when the semiconductor layer 40 is a rectangle having a first side 61, a second side 62 perpendicular to the first side 61, a third side 63 perpendicular to the second side 62, and a fourth side 64 perpendicular to the third side 63 in a plan view of the semiconductor device 1, the land pattern 80A corresponding to the first specific metal redistribution 20A among the plurality of land patterns 80 has a region that extends beyond the first side 61 to the outside of the semiconductor device 1 and a region that extends beyond the second side 62 to the outside of the semiconductor device 1 in a plan view of the semiconductor device 1, and the land pattern 80B corresponding to the second specific metal redistribution 20B among the plurality of land patterns 80 has a region that extends beyond the first side 61 to the outside of the semiconductor device 1 and a region that extends beyond the second side 62 to the outside of the semiconductor device 1. 0B may have an area extending beyond the second side 62 to the outside of the semiconductor device 1 and an area extending beyond the third side 63 to the outside of the semiconductor device 1, and among the multiple land patterns 80, land pattern 80C corresponding to the third specific metal rewiring 20C may have an area extending beyond the third side 63 to the outside of the semiconductor device 1 and an area extending beyond the fourth side 64 to the outside of the semiconductor device 1, and among the multiple land patterns 80, land pattern 80D corresponding to the fourth specific metal rewiring 20D may have an area extending beyond the fourth side 64 to the outside of the semiconductor device 1 and an area extending beyond the first side 61 to the outside of the semiconductor device 1.

[0283] This makes it possible to make the bond between the metal rewiring 20 and the solder fillet 70 relatively strong even when a force is applied to the semiconductor device 1 in either the direction in which the first side 61 and the third side 63 extend (the Y-axis direction in Figure 4B) or the direction in which the second side 62 and the fourth side 64 extend (the X-axis direction in Figure 4B), or in both directions.

[0284] Therefore, according to the semiconductor module 100 having the above configuration, the reliability of the semiconductor module 100 can be further improved.

[0285] (supplement) While the semiconductor device and the like according to one aspect of the present disclosure have been described above based on the embodiment, the present disclosure is not limited to the embodiment. Various modifications conceivable by those skilled in the art may also be included within the scope of one or more aspects of the present disclosure, as long as they do not deviate from the spirit of the present disclosure. [Industrial Applicability]

[0286] The present disclosure is widely applicable to chip-size package type semiconductor devices and the like. [Explanation of symbols]

[0287] 1. Semiconductor device 10 Vertical MOS transistor 14 Source Region 15 Gate conductor 16 Gate insulating film 17 Gate Trench 18 Body Region 20 Metal rewiring 20A Metal Rewiring, First Specific Metal Rewiring 20B Metal rewiring, second specific metal rewiring 20C Metal Rewiring, Third Specific Metal Rewiring 20D Metal Rewiring, 4th Specific Metal Rewiring 21, 21A, 21B, 21C, 21D First metal rewiring 22A, 22AA, 22BA First metal layer 22B, 22AB, 22BB Second metal layer 23, 23A, 23B First Area 24A, 24AA, 24BA, 24CA, 24DA First part 24B, 24AB, 24BB, 24CB, 24DB Second part 25, 25A, 25B, 25C, 25D Linear bend 26 Second Metal Redistribution 30 metal layer 32 Semiconductor substrate 33 Low concentration impurity layer 34 Oxide film 35 Protective film 36 Drain pull-up region 40 Semiconductor layer 50 pads 50A pad, first pad 50B pad, second pad 50C pad, third pad 50D pad, 4th pad 60, 60A, 60B, 60C electrode 61 First Side 62 Second Side 63 Third Side 64 Fourth Side 70, 70A, 70B, 70C, 70D Solder fillet 80, 80A, 80B, 80C, 80D land patterns 90 Mounting board 100 semiconductor modules

Claims

1. A chip size package type semiconductor device, a semiconductor layer; one or more vertical MOS transistors formed in the semiconductor layer; a protective film located above an upper surface of the semiconductor layer and having a plurality of openings; a plurality of pads exposed to the outside of the protective film in each of the plurality of openings, each of the pads functioning as a terminal of one of the one or more vertical MOS transistors; a plurality of metal rewirings located above an upper surface of the semiconductor layer, each of the metal rewirings being connected to one or more non-overlapping pads among the plurality of pads; In a plan view of the semiconductor device, the protective film is encapsulated in the semiconductor layer, each of the plurality of metal redistribution lines is contained in the semiconductor layer and contains the one or more pads connected to the metal redistribution line; the plurality of metal rewirings include a plurality of first metal rewirings each having a first portion and a second portion located above the first portion, wherein, in the plan view, the second portion is included in the first portion and an area of ​​the second portion is smaller than an area of ​​the first portion; Each of the plurality of first metal redistribution lines has one or more linear bends at a boundary between the first portion and the second portion on a surface of the first metal redistribution line, the interior angle of which in a cross section of the first metal redistribution line is greater than 180 degrees; In the plan view, the one or more linear bent portions have a portion facing an outer periphery of the semiconductor device, The length of the second portion in a direction in which a normal line extends from the upper surface of the semiconductor layer is longer than the length of the first portion in the direction in which the normal line extends. Semiconductor device.

2. a region of the side surface of the second portion that faces the outer periphery of the semiconductor device in the plan view has an elevation angle of less than 90 degrees with respect to the top surface of the semiconductor layer; The semiconductor device according to claim 1 .

3. In the plan view, an outer periphery of the protective film is located inside an outer periphery of the semiconductor layer, The lowermost surface of the first portion is closer to the upper surface of the semiconductor layer than the pad in the direction in which the normal line extends, and is included in the semiconductor layer and is not included in the outer periphery of the protective film in the plan view. The semiconductor device according to claim 1 .

4. In the plan view, a portion of the first portion that is not enclosed within the outer periphery of the protective film exists on the outer periphery of the first portion; The second portion is enclosed within the outer periphery of the protective film. The semiconductor device according to claim 3 .

5. Each of the plurality of metal rewirings has a multilayer structure including a first metal layer made of a first metal not containing gold and a second metal layer made of a second metal containing gold; a first region is present on a side surface of the first portion, the first region coinciding with a side surface of the semiconductor layer in the plan view; The first metal is exposed in at least a portion of the first region. The semiconductor device according to claim 1 .

6. Each of the plurality of metal rewirings has a multilayer structure including a first metal layer made of a first metal not containing gold and a second metal layer made of a second metal containing gold; a side surface of the first portion is located inside a side surface of the semiconductor layer in the plan view; The first metal is not exposed and the second metal is exposed over the entire side surface of the first portion. The semiconductor device according to claim 1 .

7. In the plan view, the one or more linear bent portions further include a portion facing a center side of the semiconductor device, The shortest distance between a portion of the one or more linear bent portions facing the outer periphery of the semiconductor device and the outer periphery of the first portion is longer than the shortest distance between a portion of the one or more linear bent portions facing the center of the semiconductor device and the outer periphery of the first portion. The semiconductor device according to claim 1 .

8. The number of the plurality of metal rewirings is equal to the number of the plurality of pads. The semiconductor device according to claim 1 .

9. All of the plurality of metal redistribution lines are the plurality of first metal redistribution lines. The semiconductor device according to claim 8 .

10. In the plan view, the semiconductor layer is rectangular; The plurality of pads include a first pad that does not include any other pad between a first side of the semiconductor layer and a second side of the semiconductor layer that is orthogonal to the first side, a second pad that does not include any other pad between the second side and a third side of the semiconductor layer that is orthogonal to the second side, a third pad that does not include any other pad between the third side and a fourth side of the semiconductor layer that is orthogonal to the third side, and a fourth pad that does not include any other pad between the fourth side and the first side, Among the plurality of metal rewirings, a first specific metal rewiring connected to the first pad, a second specific metal rewiring connected to the second pad, a third specific metal rewiring connected to the third pad, and a fourth specific metal rewiring connected to the fourth pad are each one of the plurality of first metal rewirings. The semiconductor device according to claim 1 .

11. Each of the first specific metal redistribution line, the second specific metal redistribution line, the third specific metal redistribution line, and the fourth specific metal redistribution line is connected to two or more pads among the plurality of pads. The semiconductor device according to claim 10.

12. At least one of the one or more specific pads excluding the first pad, the second pad, the third pad, and the fourth pad among the plurality of pads is not connected to any of the plurality of metal rewirings. The semiconductor device according to claim 10.

13. At least one of the one or more specific pads excluding the first pad, the second pad, the third pad, and the fourth pad among the plurality of pads is connected to a second metal rewiring among the plurality of metal rewirings that is not one of the plurality of first metal rewirings and does not have the one or more linear bent portions. The semiconductor device according to claim 10.

14. A semiconductor device according to any one of claims 1 to 13; a mounting substrate on which the semiconductor device is mounted face down, the mounting substrate has a plurality of land patterns that correspond one-to-one to a plurality of metal rewirings provided in the semiconductor device, Each of the plurality of land patterns is joined to one of the plurality of metal rewirings corresponding to the land pattern via a solder fillet made of a solder joining material; In the plan view, an area of ​​each of the plurality of land patterns is larger than an area of ​​one metal rewiring among the plurality of metal rewirings corresponding to the land pattern; each of the plurality of land patterns has a portion that is not included in the semiconductor device; The one or more linear bent portions in each of the plurality of first metal rewirings are filled with the solder fillet corresponding to the first metal rewiring. Semiconductor module.

15. A semiconductor device according to any one of claims 10 to 13; a mounting substrate on which the semiconductor device is mounted face down, the mounting substrate has a plurality of land patterns that correspond one-to-one to a plurality of metal rewirings provided in the semiconductor device, Each of the plurality of land patterns is joined to one metal rewiring of the plurality of metal rewirings corresponding to the land pattern via a solder fillet made of a solder joining material corresponding to the land pattern; In the plan view, an area of ​​each of the plurality of land patterns is larger than an area of ​​one metal rewiring among the plurality of metal rewirings corresponding to the land pattern; each of the plurality of land patterns has a portion that is not included in the semiconductor device; the one or more linear bent portions in each of the plurality of first metal redistribution lines are filled with the solder fillet; In the plan view, a first land pattern corresponding to the first specific metal rewiring among the plurality of land patterns has a region extending beyond the first side to the outside of the semiconductor device and a region extending beyond the second side to the outside of the semiconductor device; a second land pattern corresponding to the second specific metal rewiring among the plurality of land patterns has a region extending beyond the second side to the outside of the semiconductor device and a region extending beyond the third side to the outside of the semiconductor device; a third land pattern corresponding to the third specific metal rewiring among the plurality of land patterns has a region extending beyond the third side to the outside of the semiconductor device and a region extending beyond the fourth side to the outside of the semiconductor device; Among the plurality of land patterns, a fourth land pattern corresponding to the fourth specific metal rewiring has a region extending beyond the fourth side to the outside of the semiconductor device and a region extending beyond the first side to the outside of the semiconductor device. Semiconductor module.

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