Soft processor

Abstract

A soft processor (11) constitutes an integrated circuit. The soft processor (11) comprises: a normal circuit (111) that realizes implemented functions; and a debug circuit (112) that realizes debug functions. The normal circuit (111) comprises: a calculating circuit (113) that performs calculations for realizing the implemented functions; and a general-purpose register file (114) that is realized by a block memory and that stores calculation data obtained by the calculating circuit (113). In the general-purpose register file (114), a debug register (116) that allows the debug circuit (112) to access data is provided in a free area of the block memory excluding an area required for the calculating circuit (113).

Description

soft processor

[0001] The present disclosure relates to a technique for storing data for debugging in a soft processor that constitutes a logic circuit device.

[0002] The debug log for the arithmetic unit on the ASIC needs to be written to a dedicated memory. The debug log is a CPU operation history such as a register write history and a branch history. ASIC stands for Application Specific Integrated Circuit. CPU stands for Central Processing Unit. As the debug log becomes more comprehensive, the required memory capacity increases. This increases the memory capacity, which poses a problem of an increase in circuit size.

[0003] Patent Document 1 describes using free space in multiple memories provided inside an ASIC for storing image data to store log data. In Patent Document 1, a series of log data is stored in the free space in the multiple memories using a DMAC. DMAC stands for Direct Memory Access Controller. In this way, Patent Document 1 prevents the expansion of memory dedicated to storing log data. As a result, the circuit size of the ASIC is prevented from increasing.

[0004] JP 2013-225291 A

[0005] The method of storing log data by appropriately utilizing free space in existing memory, as in Patent Document 1, is not suitable for storing addresses and data in pairs, as in debug registers. When storing log data as in Patent Document 1, it is necessary to separately store the correspondence between addresses and data, which requires the memory to be correspondingly larger. The present disclosure aims to make it possible to store addresses and data in pairs while suppressing an increase in circuit size.

[0006] The soft processor according to the present disclosure is a soft processor constituting an integrated circuit, and comprises a normal circuit for realizing an implementation function and a debug circuit for realizing a debug function, wherein the normal circuit comprises an arithmetic circuit for performing calculations to realize the implementation function, and a general-purpose register file realized by a block memory for storing calculation data by the arithmetic circuit, and the general-purpose register file is provided with a debug register that enables the debug circuit to access data in an empty area of ​​the block memory excluding an area required for the arithmetic circuit.

[0007] In the present disclosure, a debug register that enables data access by a debug circuit is provided in a free area of ​​the block memory in a general-purpose register file realized by a block memory, excluding the area required for the arithmetic circuit. The block memory has a relatively large free area other than the area required for the arithmetic circuit. By providing the debug register in this free area, it is possible to store addresses and data in pairs without providing a separate block memory.

[0008] 1 is a configuration diagram of an existing FPGA user circuit 90. FIG. 1 is a configuration diagram of an FPGA user circuit 10 according to a first embodiment. FIG. 2 is an explanatory diagram of the required capacity of a general-purpose register file 114. FIG. 3 is an explanatory diagram of the minimum unit of a block memory. FIG. 4 is an explanatory diagram of free space in a block memory. FIG. 5 is an explanatory diagram of double buffering. FIG. 6 is an explanatory diagram of free space in a block memory when double buffering is performed. FIG. 7 is a configuration diagram of an FPGA user circuit 10 according to a second embodiment. FIG. 8 is an explanatory diagram of an example in which free bandwidth occurs. FIG. 9 is an explanatory diagram of an example in which free bandwidth occurs. FIG. 10 is a configuration diagram of an FPGA user circuit 10 according to a third embodiment. FIG. 11 is an explanatory diagram of a general-purpose register file 114 according to the third embodiment.

[0009] First Embodiment In the first embodiment, an FPGA user circuit will be used as an example of an integrated circuit. FPGA is an abbreviation for Field Programmable Gate Array.

[0010] ***Description of Configuration*** The configuration of an existing FPGA user circuit 90 will be described with reference to Figure 1. The FPGA user circuit 90 includes a soft processor 91, a debug control unit 92, and a debug IF 93. The soft processor 91 includes a normal circuit 911 and a debug circuit 912. IF is an abbreviation for Interface.

[0011] The normal circuit 911 is a circuit that realizes the implemented functions implemented in the FPGA user circuit 90. The normal circuit 911 includes an arithmetic circuit 913 and a general-purpose register file 914. The arithmetic circuit 913 is a circuit that performs calculations to realize the implemented functions. The general-purpose register file 914 is a memory for storing calculation data by the arithmetic circuit 913.

[0012] The debugging circuit 912 is a circuit that realizes a debugging function. The debugging circuit 912 includes a debugging register 915 for storing debugging information such as a debug log. The debugging circuit 912 is connected to the debug IF 93 via the debug control unit 92. The debug IF 93 is connected to the outside of the FPGA user circuit 90.

[0013] Increasing the amount of debugging information increases the capacity of the debugging register 915. As a result, the circuit size of the FPGA user circuit 90 increases.

[0014] 2, the configuration of the FPGA user circuit 10 according to the first embodiment will be described. The FPGA user circuit 10 includes a soft processor 11, a debug control unit 12, and a debug IF 13. The soft processor 11 includes a normal circuit 111 and a debug circuit 112.

[0015] The normal circuit 111, like the normal circuit 911, is a circuit that realizes an implementation function implemented in the FPGA user circuit 10. The normal circuit 111 includes an arithmetic circuit 113, a general-purpose register file 114, and an access selection circuit 115. Like the arithmetic circuit 913, the arithmetic circuit 113 is a circuit that performs calculations to realize the implementation function. Like the general-purpose register file 914, the general-purpose register file 114 is a memory for storing calculation data by the arithmetic circuit. In the general-purpose register file 114, a debug register 116 is provided in an empty area after an area for storing calculation data is reserved. The access selection circuit 115 is a circuit that controls access to the general-purpose register file 114.

[0016] The debugging circuit 112 is a circuit that realizes a debugging function, similar to the debugging circuit 912. The debugging circuit 112 uses a debugging register 116 to store debugging information such as a debug log. The debugging circuit 112 is connected to the debug IF 13 via the debug control unit 12. The debug IF 13 is connected to the outside of the FPGA user circuit 10.

[0017] The general-purpose register file 114 is implemented using block memory. Depending on the user's purpose, block memory can be connected to create a large-capacity memory, or a single block memory can be divided to use as a small-capacity memory. Block memory capacity has a minimum unit (lower limit). When a memory with a capacity smaller than the minimum unit is implemented using block memory, free space is generated. As will be described in detail later, the required capacity of the general-purpose register file 14 is smaller than the minimum unit of block memory. Therefore, when block memory is used to implement the general-purpose register file 114, the required capacity of the general-purpose register file 114 is smaller than the minimum unit, resulting in free space. The debug register 116 is provided in this free space. Therefore, there is no need to increase the capacity of the block memory to accommodate the debug register 116. In other words, even if the debug register 116 is provided, the circuit scale of the normal circuit 111 can be the same as that of the normal circuit 911.

[0018] By providing the debug register 116 in the general-purpose register file 114, the general-purpose register file 114 is accessed not only by the arithmetic circuit 113 but also by the debug circuit 112. The number of read and write ports to the general-purpose register file 114 is limited. Therefore, the access selection circuit 115 controls access to the general-purpose register file 114. When there is no access to the general-purpose register file 114 from the arithmetic circuit 113, the access selection circuit 115 permits access to the general-purpose register file 114 from the debug circuit 112. Generally, the bandwidth for the general-purpose register file 114 is occupied by the arithmetic circuit 113 so as not to impede the operation of the arithmetic circuit 113. However, in principle, the debug function operates only when the arithmetic circuit 113 is stopped. In other words, in principle, the debug circuit 112 accesses the general-purpose register file 114 only when the arithmetic circuit 113 is stopped. Therefore, the debug circuit 112 can share the general-purpose register file 114 with the arithmetic circuit 113 and use it.

[0019] The debug register 116 is set with data stored for each address. In other words, it is configured to be suitable for storing debug information in which addresses and data are paired. For example, the debug register 116 stores a copy of the calculation data stored in the general-purpose register file 114 by the calculation circuit 113. The debug circuit 112 reads and edits the copy of the calculation data stored in the debug register 116 as necessary. This realizes the debug function.

[0020] The required capacity of the general-purpose register file 114 will be described with reference to Figure 3. The required capacity of the general-purpose register file 114 is the size of the area required to store operation data. The required capacity of the general-purpose register file 114 is determined according to the combination of the number of bits for integer operation and the number of bits for decimal operation. For example, if the integer operation is 32 + 64 bits and the decimal operation is 32 + 64 bits, the required capacity of the general-purpose register file 114 is 6 kilobits.

[0021] The minimum unit of block memory will be described with reference to FIG. 4 . The minimum unit of block memory is determined by the FPGA vendor. For example, if the FPGA vendor is Lattice SEMICONDUCTOR, the minimum unit of embedded SRAM, which is block memory, is 240 kbits. In this case, assuming that the required capacity of general-purpose register file 114 is 6 kbits, a free space of 234 kbits will be created. That is, as shown in FIG. 5 , a total of 6 kbits is reserved as the required capacity of general-purpose register file 114: 1 kbit for 32-bit integer arithmetic registers, 1 kbit for 32-bit decimal arithmetic registers, 2 kbit for 64-bit integer arithmetic registers, and 2 kbit for 64-bit decimal arithmetic registers. Therefore, 6 kbits of the 240 kbits, which is the minimum unit of block memory, are reserved, resulting in a free space of 234 kbits.

[0022] As shown in FIG. 6 , when implementing a pipeline processor with one operation per cycle, it is necessary to ensure a bandwidth for the general-purpose register file 114 of 2 reads and 1 write per cycle. Therefore, when implementing a pipeline processor with one operation per cycle, it is necessary to double-buffer the general-purpose register file 114. Double-buffering means that the general-purpose register file 114 is configured using two block memories. Then, as shown in FIG. 7 , the required capacity for the general-purpose register file 114 is secured in each of the two block memories. In other words, free space is created in each of the two block memories. Therefore, if the FPGA vendor is Lattice SEMICONDUCTOR and the required capacity of the general-purpose register file 114 is 6 kbits, a free space of 468 kbits is created.

[0023] Here, instead of implementing the general-purpose register file 114 using block memory, it is also possible to implement it as part of a combinational circuit through logic synthesis and wiring placement. The advantages and disadvantages of implementing the general-purpose register file 114 as part of a combinational circuit compared to implementing it using block memory are as follows. There are two advantages. The first is that the amount of block memory usage is not reduced. The second is that resources are consumed in proportion to the required capacity, eliminating waste. There are three disadvantages. The first is that as the required capacity increases, the operating speed is likely to decrease. The second is that as the required capacity increases, the difficulty of logic synthesis and placement and wiring increases. The third is that the amount of combinational circuit usage increases, potentially putting pressure on the combinational circuit. Considering these factors, it is desirable to implement the general-purpose register file 114 using block memory in a software processor 11 that requires stable operating speed and ease of logic synthesis and placement and wiring.

[0024] ***Effects of First Embodiment*** As described above, in the FPGA user circuit 10 according to the first embodiment, the debug registers 116 are provided in the free space of the general-purpose register file 114. In other words, free space that would otherwise be wasted is effectively utilized as the debug registers 116. This eliminates the need to implement a memory circuit separate from the general-purpose register file 114 for the debug registers 116. As a result, the circuit size can be reduced. Also, power consumption can be reduced. The debug registers 116 are configured to be suitable for storing debug information consisting of pairs of addresses and data, and there is no need to unnecessarily increase their capacity.

[0025] Second Embodiment The second embodiment differs from the first embodiment in that the debug log 21 is written to a free area of ​​the general-purpose register file 114 by utilizing the free bandwidth of the access by the arithmetic circuit 113 to the general-purpose register file 114. In the second embodiment, this difference will be explained, and the explanation of the same points will be omitted.

[0026] ***Description of Configuration*** The configuration of FPGA user circuit 10 according to the second embodiment will be described with reference to Figure 8. FPGA user circuit 10 differs from FPGA user circuit 10 shown in Figure 2 in that normal circuit 111 includes debug log generation circuit 117. Debug log generation circuit 117 generates debug log 21, which is a log related to the operations of arithmetic circuit 113. Debug log generation circuit 117 then writes debug log 21 to general-purpose register file 114 at a time when no access to general-purpose register file 114 from arithmetic circuit 113 occurs.

[0027] The arithmetic circuit 113 generates free bandwidth for reading or writing from or to the general-purpose register file 114 depending on the type of instruction to be executed. This will be described in detail with reference to Figures 9 and 10. Figures 9 and 10 show a 5-stage pipeline operation as an example.

[0028] As shown in FIG. 9 , an available bandwidth is always generated immediately after the arithmetic circuit 113 executes a branch instruction. Immediately after the execution of a branch instruction refers to immediately after the program counter is updated. Therefore, the debug log generation circuit 117 generates, as the debug log 21, the minimum amount of information regarding the branch instruction that can be written within the available bandwidth. As a specific example, the debug log generation circuit 117 generates, as the debug log 21, stall information when a branch occurs. For example, the debug log generation circuit 117 generates, as the debug log 21, at least one of the program counter value of the jump destination of the branch instruction, the time the branch instruction occurred, the program counter value of the branch instruction itself, and the operand value that served as the basis for the branch. Then, using the available bandwidth immediately after the execution of the branch instruction, the debug log generation circuit 117 writes the debug log 21 to the general-purpose register file 114. At this time, the debug log generation circuit 117 writes the debug log 21 to the debug register 116 in the general-purpose register file 114. The debug register 116 may be secured so that data other than the debug log 21 can also be stored.

[0029] 10 , immediately after a memory access instruction (referred to as MEM access in FIG. 10 ) is executed, an available bandwidth is always generated. Therefore, the debug log generation circuit 117 generates the minimum amount of information regarding the memory access instruction that can be written in the available bandwidth as the debug log 21. As a specific example, the debug log generation circuit 117 generates, as the debug log 21, at least one of the address information of the access destination, the time of the access, the time required for the access, the program counter value of the instruction that executed the access, and the address of the register used for the address or data.

[0030] As with branch instructions, executing an interrupt instruction and a jump instruction always results in an available bandwidth. Therefore, even when an interrupt instruction is executed, the debug log generation circuit 117 generates the minimum amount of information about the interrupt instruction that can be written in the available bandwidth as the debug log 21, and writes it to the general-purpose register file 114. Similarly, even when a jump instruction is executed, the debug log generation circuit 117 generates the minimum amount of information about the jump instruction that can be written in the available bandwidth as the debug log 21, and writes it to the general-purpose register file 114.

[0031] In the above description, the debug log generation circuit 117 generates data related to commands that generate available bandwidth as the debug log 21. However, the debug log generation circuit 117 is not limited to data related to commands that generate available bandwidth, and can generate any data as the debug log 21.

[0032] ***Effects of Second Embodiment*** As described above, the FPGA user circuit 10 according to the second embodiment uses the available bandwidth of the arithmetic circuit 113's access to the general-purpose register file 114 to write the debug log 21 to an available area of ​​the general-purpose register file 114. By using the available bandwidth of the arithmetic circuit 113's access to the general-purpose register file 114, it is possible to save the debug log 21 in the general-purpose register file 114 without degrading the performance of the soft processor 11.

[0033] Furthermore, the FPGA user circuit 10 according to the second embodiment stores data relating to instructions that generate free bandwidth as the debug log 21. As a result, when an instruction that generates free bandwidth is executed, data relating to the instruction that generates free bandwidth is stored as the debug log 21. Therefore, it is possible to store data that is easy to use for debugging as the debug log 21.

[0034] Embodiment 3. Embodiment 3 differs from embodiments 1 and 2 in that a word size larger than the word size per word required to store operation data as one word is set in the general-purpose register file 114, and additional information 22 is stored therein. In embodiment 3, this difference will be described, and a description of the same points will be omitted. In embodiment 3, a case where embodiment 1 is modified will be described. However, embodiment 2 can also be modified.

[0035] ***Description of Configuration*** The configuration of FPGA user circuit 10 according to embodiment 3 will be described with reference to Figure 11. FPGA user circuit 10 differs from FPGA user circuit 10 shown in Figure 2 in that normal circuit 111 includes additional information generation circuit 118 and data concatenation circuit 119. Additional information generation circuit 118 generates additional information 22 related to operation data generated by operation circuit 113. Data concatenation circuit 119 concatenates additional information 22 to the operation data and writes the concatenated data to general-purpose register file 114 as one word.

[0036] The general-purpose register file 114 according to the third embodiment will be described with reference to FIG. 12 . The word size of the general-purpose register file 114 is generally set to the size required to store operation data as one word. This allows for efficient use of memory space. In FIG. 12 , the size required to store operation data as one word is set to 32 bits. Therefore, 32 bits are allocated to each address from 0 to 31. In the general-purpose register file 114 according to the third embodiment, the word size is set to a size larger than the size required to store operation data as one word. In FIG. 12 , the word size is set to 64 bits, which is 32 bits larger than the 32 bits required to store operation data as one word. Therefore, 64 bits are allocated to each address from 0 to 31. In other words, an area of ​​32 bits is added to each address. The additional information 22 is stored in this added area. This added area is the debug register 116. Note that a debug register 116 may be allocated in addition to the added area so that data other than the additional information 22 can be stored.

[0037] When the arithmetic circuit 113 executes an instruction and generates operation data, the additional information generation circuit 118 generates additional information 22 related to the operation data. As a specific example, the additional information generation circuit 118 generates at least one of the program counter value of the instruction that generated the operation data, the instruction code of the instruction that generated the operation data, and the time when the operation data was generated, as the additional information 22. The data concatenation circuit 119 concatenates the additional information 22 generated by the additional information generation circuit 118 to the operation data to generate concatenated data 23. Then, the data concatenation circuit 119 writes the concatenated data 23 to the general-purpose register file 114. In other words, when writing the operation data to the general-purpose register file 114, the data concatenation circuit 119 also writes the additional information 22 at the same time.

[0038] ***Effects of Third Embodiment*** As described above, the FPGA user circuit 10 according to the third embodiment sets a word size in the general-purpose register file 114 that is larger than the word size per word required to store operation data as one word, and stores the additional information 22. This makes it possible to store the additional information 22 related to the operation data in pairs with the addresses of the general-purpose register file 114.

[0039] The embodiments and modifications of the present disclosure have been described above. Some of these embodiments and modifications may be combined and implemented. Furthermore, one or more of them may be implemented partially. Note that the present disclosure is not limited to the above embodiments and modifications, and various modifications are possible as needed.

[0040] 10 FPGA user circuit, 11 soft processor, 12 debug control unit, 13 debug IF, 111 normal circuit, 112 debug circuit, 113 arithmetic circuit, 114 general-purpose register file, 115 access selection circuit, 116 debug register, 117 debug log generation circuit, 118 additional information generation circuit, 119 data concatenation circuit, 21 debug log, 22 additional information, 23 concatenated data, 90 FPGA user circuit, 91 soft processor, 92 debug control unit, 93 debug IF, 911 normal circuit, 912 debug circuit, 913 arithmetic circuit, 914 general-purpose register file, 915 debug register.

Claims

1. A soft processor constituting an integrated circuit, comprising: a normal circuit for realizing an implementation function; and a debug circuit for realizing a debug function, wherein the normal circuit comprises: an arithmetic circuit for performing calculations to realize the implementation function; and a general-purpose register file implemented by block memory for storing calculation data by the arithmetic circuit, wherein the general-purpose register file is provided with a debug register that enables access to data by the debug circuit in free space within the area of ​​the block memory excluding the area required for the arithmetic circuit.

2. The soft processor according to claim 1, wherein the debug register pairs an address in the block memory with data to be written to an area indicated by the address.

3. A soft processor according to claim 1 or 2, wherein the general-purpose register file is realized by dividing the block memory into the smallest unit area possible, and the debug register is provided in an empty area remaining after removing an area required for the arithmetic circuit from the smallest unit area.

4. A soft processor according to any one of claims 1 to 3, wherein the normal circuit further comprises an access selection circuit that permits access to the general-purpose register file from the debug circuit when there is no access to the general-purpose register file from the arithmetic circuit.

5. A soft processor according to any one of claims 1 to 4, wherein the normal circuit further comprises a debug log generation circuit that generates a debug log, which is a log related to the operations of the arithmetic circuit, and writes the debug log to the general-purpose register file at a timing when the arithmetic circuit does not access the general-purpose register file.

6. The soft processor according to claim 5, wherein a timing occurs in which no access to the general-purpose register file occurs from the arithmetic circuit after execution of a specific type of instruction among a plurality of types of instructions executed in the arithmetic circuit, and when the specific type of instruction is executed, the debug log generation circuit generates data corresponding to the specific type of instruction as the debug log.

7. A soft processor as claimed in any one of claims 1 to 6, wherein the general-purpose register file has a word size set larger than the word size per word required to store the operation data as one word, and the normal circuit further comprises: an additional information generation circuit that generates additional information related to the operation data by the operation circuit; and a data concatenation circuit that concatenates the additional information generated by the additional information generation circuit to the operation data and writes the concatenated information to the general-purpose register file as one word.