Display panel and electronic device

The display panel design addresses high-resolution and diverse shape challenges by using pixel electrodes, bank layers, and intermediate layers to enhance light emission efficiency and lifespan.

KR1020260112896APending Publication Date: 2026-07-21SAMSUNG DISPLAY CO LTD
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Patent Information

Application Number
KR1020250004374
Authority / Receiving Office
KR · KR
Patent Type
Applications
Current Assignee / Owner
Filing Date
2025-01-10
Publication Date
2026-07-21

AI Technical Summary

Technical Problem

Existing display panels face challenges in achieving high-resolution and diverse shapes while ensuring a long lifespan and high-quality images.

Method used

A display panel design comprising a first and second pixel electrode, a bank layer with openings, a counter electrode, and intermediate layers emitting different colors, with a hole injection layer and charge generation layers to enhance light emission efficiency and lifespan.

Benefits of technology

The design improves display quality and lifespan through a relatively simple structure, enhancing light efficiency and color purity.

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Abstract

One embodiment of the present invention comprises a first substack including mutually spaced first pixel electrodes and second pixel electrodes, a bank layer including a first opening corresponding to the first pixel electrode and a second opening corresponding to the second pixel electrode, a counter electrode disposed on the bank layer and overlapping with the first pixel electrode and the second pixel electrode, and a first intermediate layer interposed between the first pixel electrode and the counter electrode, wherein the first intermediate layer overlaps with the first pixel electrode and includes a first subluminescent layer emitting light of a first color; A display panel is disclosed that includes a second substack disposed on the first substack and including a second substack that emits light of the same color as the first sub-emissive layer, and further includes a second intermediate layer that is interposed between the second pixel electrode and the counter electrode, overlaps with the second pixel electrode through the second opening, and emits light of a second color different from the first color, wherein a portion of the second intermediate layer is interposed between the first substack and the second substack on a first portion of the bank layer between the first pixel electrode and the second pixel electrode.
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Description

Technology Field

[0001] Embodiments of the present invention provide a display panel and an electronic device including the same. Background Technology

[0002] Recently, display panels have been used in electronic devices for various purposes. As the scope of display panel applications expands, the demand for high-resolution and diversely shaped display panels is increasing, and research on space utilization within display panels is continuing to realize high-resolution displays. The problem to be solved

[0003] Embodiments of the present invention provide a display panel that enables a long lifespan and high-quality images, and an electronic device including the same. However, these are exemplary and do not limit the scope of the present invention. means of solving the problem

[0004] One embodiment of the present invention comprises: a first pixel electrode and a second pixel electrode spaced apart from each other; a bank layer including a first opening corresponding to the first pixel electrode and a second opening corresponding to the second pixel electrode; a counter electrode disposed on the bank layer and overlapping with the first pixel electrode and the second pixel electrode; a first intermediate layer interposed between the first pixel electrode and the counter electrode, wherein the first intermediate layer overlaps with the first pixel electrode and includes a first sub-emissive layer emitting light of a first color; and a second sub-stack disposed on the first sub-stack and including a second sub-emissive layer emitting light of the same color as the first sub-emissive layer. A display panel is disclosed comprising: a second intermediate layer interposed between the second pixel electrode and the counter electrode, overlapping with the second pixel electrode, and emitting light of a second color different from the first color; wherein a portion of the second intermediate layer is interposed between the first substack and the second substack on a first portion of the bank layer between the first pixel electrode and the second pixel electrode.

[0005] The hole injection layer is further included, wherein the hole injection layer overlaps the first pixel electrode, the first portion of the bank layer, and the second pixel electrode, and may be interposed between the first pixel electrode and the first intermediate layer, and between the second pixel electrode and the second intermediate layer.

[0006] The first intermediate layer is interposed between the first sub-emissive layer and the second sub-emissive layer and includes a charge generation layer comprising an electron generation layer and a hole generation layer, wherein the electron generation layer is a sublayer of the first substack and the hole generation layer may be a sublayer of the second substack.

[0007] The first substack may include: the first sub-emissive layer; a first sub-hole transport layer between the first pixel electrode and the first sub-emissive layer; the electron generation layer located on the opposite side of the first sub-hole transport layer with the first sub-emissive layer in between; and a first sub-electron transport layer between the first sub-emissive layer and the electron generation layer.

[0008] The second substack may include: the second subluminescent layer; the hole generation layer between the first substack and the second subluminescent layer; and the second sub-hole transport layer between the hole generation layer and the second subluminescent layer.

[0009] The width of each of the electron generation layer and the first sub-electron transport layer of the first sub-stack may be smaller than the width of the second sub-hole transport layer.

[0010] It may further include an electron transport layer interposed between the above-mentioned counter electrode and the above-mentioned second substack of the above-mentioned first intermediate layer.

[0011] The electron transport layer is extended to be interposed between the counter electrode and the second intermediate layer, and may overlap with the second substack of the first intermediate layer, the second intermediate layer, and the first portion of the bank layer.

[0012] The first color above is blue, and the second color above may be red or green.

[0013] The display panel further comprises: a third pixel electrode spaced apart from the first pixel electrode; and a third intermediate layer interposed between the third pixel electrode and the counter electrode, overlapping with the third pixel electrode, and emitting light of a third color different from the first color and the second color; wherein a portion of the third intermediate layer may be interposed between the first substack and the second substack on a second portion of the bank layer between the first pixel electrode and the third pixel electrode.

[0014] An embodiment of the present invention is an electronic device comprising a display panel including a first pixel, a second pixel, and a third pixel, wherein the display panel comprises: a first pixel electrode corresponding to the first pixel; a second pixel electrode corresponding to the second pixel and spaced apart from the first pixel electrode; a bank layer including a first opening corresponding to the first pixel electrode and a second opening corresponding to the second pixel electrode; a counter electrode disposed on the bank layer and overlapping with the first pixel electrode and the second pixel electrode; a first intermediate layer interposed between the first pixel electrode and the counter electrode, wherein the first intermediate layer is interposed between the first pixel electrode and the counter electrode, and the first intermediate layer is a first sub-emissive layer that overlaps with the first pixel electrode and emits light of a first color; An electronic device is disclosed comprising: a second substack disposed on the first substack and including a second sub-emissive layer that emits light of the same color as the first sub-emissive layer; a second intermediate layer interposed between the second pixel electrode and the counter electrode, overlapping with the second pixel electrode, and including a second light-emitting layer that emits light of a second color different from the first color; wherein the first substack comprises an electron generating layer and the second substack comprises a hole generating layer, and a portion of the second intermediate layer is interposed between the electron generating layer and the hole generating layer on a first portion of the bank layer between the first pixel electrode and the second pixel electrode.

[0015] The above display panel further includes a hole injection layer, wherein the hole injection layer overlaps with the first pixel electrode, the first portion of the bank layer, and the second pixel electrode, and may be interposed between the first pixel electrode and the first intermediate layer, and between the second pixel electrode and the second intermediate layer.

[0016] The first substack may include: the first sub-emissive layer; a first sub-hole transport layer between the first pixel electrode and the first sub-emissive layer; the electron generation layer located on the opposite side of the first sub-hole transport layer with the first sub-emissive layer in between; and a first sub-electron transport layer between the first sub-emissive layer and the electron generation layer.

[0017] The second substack may include: the second subluminescent layer; the hole generation layer between the first substack and the second subluminescent layer; and the second sub-hole transport layer between the hole generation layer and the second subluminescent layer.

[0018] The width of each of the electron generation layer and the first sub-electron transport layer of the first sub-stack may be smaller than the width of the second sub-hole transport layer.

[0019] The above display panel may further include an electron transport layer interposed between the opposing electrode and the second substack of the first intermediate layer.

[0020] The electron transport layer is extended to be interposed between the counter electrode and the second intermediate layer, and may overlap with the second substack of the first intermediate layer, the second intermediate layer, and the first portion of the bank layer.

[0021] The first color above is blue, and the second color above may be red or green.

[0022] The display panel further comprises: a third pixel electrode corresponding to the third pixel and spaced apart from the first pixel electrode; and a third intermediate layer interposed between the third pixel electrode and the counter electrode, overlapping with the third pixel electrode, and emitting light of a third color different from the first color and the second color; wherein a portion of the third intermediate layer may be interposed between the first substack and the second substack on a second portion of the bank layer between the first pixel electrode and the third pixel electrode. Effects of the invention

[0023] According to some embodiments of the present invention, a display panel and an electronic device that improve display quality lifespan through a relatively simple structure can be provided. The aforementioned effects are exemplary, and the effects of the present invention are not limited to those described above. Brief explanation of the drawing

[0024] FIG. 1a is a block diagram of an electronic device according to one embodiment. FIG. 1b is a schematic diagram of an electronic device according to various embodiments. FIG. 2 is a plan view schematically illustrating a display panel according to one embodiment of the present invention. FIG. 3 is a cross-sectional view schematically illustrating a display panel according to one embodiment of the present invention. FIG. 4 is an enlarged cross-sectional view of a portion corresponding to the first pixel and the second pixel of a display panel according to an embodiment of the present invention, and is an enlarged cross-sectional view of portion IV of FIG. 3. FIG. 5 is an enlarged cross-sectional view of a portion corresponding to the first pixel and the third pixel of a display panel according to an embodiment of the present invention, and is an enlarged cross-sectional view of portion V of FIG. 3. FIG. 6 is a schematic diagram showing the stacking structure of each pixel of a display panel according to one embodiment of the present invention. FIG. 7 is an enlarged cross-sectional view of a portion corresponding to a first pixel of a display panel according to an embodiment of the present invention, which may correspond to portion VII of FIG. 3. Specific details for implementing the invention

[0025] The present invention is capable of various modifications and may have various embodiments; specific embodiments are illustrated in the drawings and described in detail in the detailed description. The effects and features of the present invention, and the methods for achieving them, will become clear by referring to the embodiments described below in detail together with the drawings. However, the present invention is not limited to the embodiments disclosed below but can be implemented in various forms.

[0026] Hereinafter, embodiments of the present invention will be described in detail with reference to the attached drawings. When describing with reference to the drawings, identical or corresponding components are given the same reference numerals, and redundant descriptions thereof will be omitted.

[0027] In the following embodiments, terms such as first, second, etc. are used not in a limiting sense, but for the purpose of distinguishing one component from another component.

[0028] In the following examples, singular expressions include plural expressions unless the context clearly indicates otherwise.

[0029] In the following embodiments, terms such as "include" or "have" mean that the features or components described in the specification are present, and do not preclude the possibility that one or more other features or components may be added.

[0030] In the following embodiments, when a part such as a film, region, or component is described as being on or above another part, it includes not only cases where it is directly on top of another part, but also cases where another film, region, or component is interposed in between.

[0031] In the drawings, the size of components may be exaggerated or reduced for convenience of explanation. For example, the size and thickness of each component shown in the drawings are depicted arbitrarily for convenience of explanation, so the present invention is not necessarily limited to what is illustrated.

[0032] Where an embodiment can be implemented differently, a specific process sequence may be performed differently from the order described. For example, two processes described consecutively may be performed substantially simultaneously or proceed in the reverse order of the description.

[0033] In the following embodiments, when it is stated that a membrane, region, component, etc. is connected, it includes not only cases where the membrane, region, or component is directly connected, but also cases where other membranes, regions, or components are interposed between them to form an indirect connection. For example, when it is stated in this specification that a membrane, region, component, etc. is electrically connected, it includes not only cases where the membrane, region, or component, etc. are directly electrically connected, but also cases where other membranes, regions, or components are interposed between them to form an indirect electrical connection.

[0034] FIG. 1a is a block diagram of an electronic device according to one embodiment. FIG. 1b is a schematic diagram of an electronic device according to various embodiments.

[0035] Referring to FIG. 1a, an electronic device (1) according to one embodiment may include a display module (11), a processor (12), a memory (13), and a power module (14). The display module (11) may include a display panel (10, FIG. 2) according to one embodiment of the present invention. In some embodiments, the display module (11) may include a display panel (10, FIG. 2), a gate driver (not shown), and a data driver (not shown). In one embodiment, the display panel (10, FIG. 2), the gate driver (not shown), and / or the data driver (not shown) may be formed together in a process of forming the display panel (10, FIG. 2). In one embodiment, the gate driver (not shown) and / or the data driver (not shown) may be disposed on the display panel (10, FIG. 2) and may be electrically connected to the display panel (10, FIG. 2) through a bonding structure.

[0036] The processor (12) may include at least one of a central processing unit (CPU), an application processor (AP), a graphic processing unit (GPU), a communication processor (CP), an image signal processor (ISP), and a controller.

[0037] The memory (15) may store data information necessary for the operation of the processor (12) or the display module (11). When the processor (12) executes an application stored in the memory (15), a video data signal and / or an input control signal is transmitted to the display module (11), and the display module (11) can process the received signal and output video information through a display screen.

[0038] The power module (14) may include a power supply module, such as a power adapter or battery device, and a power conversion module that converts the power supplied by the power supply module to generate power required for the operation of the electronic device (1).

[0039] At least one of each component of the electronic device (1) described above may be included within a display device that includes a display module (11). Additionally, some of the individual modules that are functionally included within a single module may be included within the display device, while others may be provided separately from the display device. For example, the display device may include a display module (11), and the processor (12), memory (13), and power module (14) may be provided in the form of other devices within the electronic device (1) that are not the display device.

[0040] Referring to FIG. 1b, an electronic device including a display panel (10, FIG. 2) according to embodiments may include an image display electronic device such as a smartphone (1a), tablet PC (1b), laptop (1c), TV (1d), and desk monitor (1e), as well as a wearable electronic device including a display module such as smart glasses (1f), head-mounted display (1g), and smart watch (1h), and an automotive electronic device (1i) including a display module such as a CID (Center Information Display) and a room mirror display placed on the instrument panel, center fascia, and dashboard of a car.

[0041] FIG. 2 is a plan view schematically illustrating a display panel (10) according to one embodiment of the present invention.

[0042] Referring to FIG. 2, a display panel (10) may include a display area (DA) and a non-display area (NDA) located outside the display area (DA). The display area (DA) may display an image through pixels (P) placed in the display area (DA). Each pixel (P) may include a display element such as a light-emitting element. Each pixel (P) may emit light, for example, red, green, blue, or white light.

[0043] The non-display area (NDA) is positioned outside the display area (DA) and is a non-display area that does not display an image, and can completely surround the display area (DA). Drivers, etc., for providing electrical signals or power to the display area (DA) may be placed in the non-display area (NDA). Pads, which are areas where electronic components or printed circuit boards can be electrically connected, may be placed in the non-display area (NDA).

[0044] As one embodiment, FIG. 2 illustrates a polygon (e.g., a square) in which the length of the first direction (e.g., x direction) of the display area (DA) is smaller than the length of the second direction (e.g., y direction); however, in another embodiment, the polygon (e.g., a square) in which the length of the second direction (e.g., y direction) of the display area (DA) is smaller than the length of the first direction (e.g., x direction). FIG. 2 illustrates that the display area (DA) is approximately a square, but the present invention is not limited thereto. As another embodiment, the display area (DA) may have various shapes such as an N-gon (N is a natural number greater than or equal to 3), a circle, or an ellipse. As illustrated in FIG. 2, the display area (DA) may be a polygon with rounded corners; however, as another embodiment, the corners of the display area (DA) may be a shape that includes vertices where straight lines meet.

[0045] As a display element included in the display panel (10), the light-emitting diode may be an organic light-emitting diode including an organic light-emitting layer. The light-emitting diode may be an inorganic light-emitting diode including an inorganic light-emitting layer. The size of the light-emitting diode may be a micro scale or a nano scale. For example, the light-emitting diode may be a micro light-emitting diode. The light-emitting diode may be a quantum dot light-emitting diode including a quantum dot light-emitting layer.

[0046] FIG. 3 is a cross-sectional view schematically illustrating a display panel (10) according to one embodiment of the present invention. A display panel (10) according to one embodiment may include light-emitting diodes, such as first to third light-emitting diodes (LED1, LED2, LED3), disposed on a substrate (100).

[0047] The substrate (100) may comprise glass, metal, or polymer resin. If at least a portion of the display device is bendable or the display device has flexible characteristics, the substrate (100) may comprise polymer resin. The substrate (100) may comprise polymer resins such as polyethersulfone, polyacrylate, polyetherimide, polyethylene naphthalate, polyethylene terephthalate, polyphenylene sulfide, polyarylate, polyimide, polycarbonate, or cellulose acetate propionate. In one embodiment, the substrate (100) may have a multilayer structure comprising at least two base layers each comprising such polymer resins and an inorganic layer interposed between the base layers.

[0048] A buffer layer (201) may be disposed on a substrate (100). The buffer layer (101) may include an inorganic material such as silicon oxide, silicon nitride and / or silicon oxynitride. The buffer layer (101) may increase the smoothness of the upper surface of the substrate (100) or prevent or minimize the penetration of impurities from the direction of the substrate (100) into the semiconductor layer (ACT) of the transistor (TFT).

[0049] A transistor (TFT) may be placed on a buffer layer (201). The transistor (TFT) may include a semiconductor layer (ACT), a gate electrode (GE), a source electrode (SE), and a drain electrode (DE).

[0050] A semiconductor layer (ACT) may be disposed on a buffer layer (201). The semiconductor layer (ACT) may include amorphous silicon or polysilicon. The semiconductor layer (ACT) may include an oxide semiconductor material. The oxide semiconductor material may include an oxide of at least one material selected from the group comprising indium (In), gallium (Ga), tin (Sn), zirconium (Zr), vanadium (V), hafnium (Hf), cadmium (Cd), germanium (Ge), chromium (Cr), titanium (Ti), and zinc (Zn). The semiconductor layer (ACT) may include an organic semiconductor material. The semiconductor layer (ACT) may include a channel region, a source region, and a drain region.

[0051] The gate electrode (GE) may include a metal, an alloy, a conductive metal oxide, or a transparent conductive material. For example, the gate electrode (GE) may include silver (Ag), an alloy containing silver, molybdenum (Mo), an alloy containing molybdenum, aluminum (Al), an alloy containing aluminum, aluminum nitride (AlN), tungsten (W), tungsten nitride (WN), copper (Cu), nickel (Ni), chromium (Cr), chromium nitride (CrN), titanium (Ti), tantalum (Ta), platinum (Pt), scandium (Sc), indium tin oxide (ITO), or indium zinc oxide (IZO). The gate electrode (GE) may have a single-layer or multi-layer structure including the aforementioned materials.

[0052] The source electrode (SE) and drain electrode (DE) may include metals, alloys, conductive metal oxides, or transparent conductive materials. For example, the source electrode (SE) and drain electrode (DE) may include silver (Ag), a silver-containing alloy, molybdenum (Mo), a molybdenum-containing alloy, aluminum (Al), an aluminum-containing alloy, aluminum nitride (AlN), tungsten (W), tungsten nitride (WN), copper (Cu), nickel (Ni), chromium (Cr), chromium nitride (CrN), titanium (Ti), tantalum (Ta), platinum (Pt), scandium (Sc), indium tin oxide (ITO), or indium zinc oxide (IZO). The source electrode (SE) and drain electrode (DE) may have a single-layer or multi-layer structure comprising the aforementioned materials. For example, the source electrode (SE) and drain electrode (DE) may have a two-layer structure of Ti / Al or a three-layer structure of Ti / Al / Ti.

[0053] A gate insulating layer (203) may be interposed between a semiconductor layer (ACT) and a gate electrode (GE). The gate insulating layer (203) may include an inorganic insulating material such as silicon oxide, silicon nitride and / or silicon oxynitride.

[0054] The interlayer insulating layer (205) may be disposed on the gate electrode (GE). The source electrode (SE) and the drain electrode (DE) may be disposed on the interlayer insulating layer (205). The interlayer insulating layer (205) may include an inorganic insulating material such as silicon oxide, silicon nitride and / or silicon oxynitride.

[0055] FIG. 3 illustrates a transistor (TFT) having both a source electrode (SE) and a drain electrode (DE), but the present invention is not limited thereto. In one embodiment, a pixel circuit electrically connected to each of the first to third light-emitting diodes (LED1, LED2, LED3) may include a plurality of transistors, and the drain region of the first transistor, which is one of the plurality of transistors, may be electrically connected to the source region of the second transistor, which is another. In this case, the drain region of the first transistor and the source region of the second transistor may be integral, the first transistor may not have a drain electrode (DE), and the second transistor may not have a source electrode (SE).

[0056] The flattening layer (207) may be placed on a transistor (TFT). The flattening layer (207) may provide a flat surface. The flattening layer (207) may include an organic insulating material. FIG. 3 illustrates that the flattening layer (207) is a single layer, but the present invention is not limited thereto. In other embodiments, the flattening layer (207) may have a multilayer structure.

[0057] The first to third light-emitting diodes (LED1, LED2, LED3) may be disposed on the flattening layer (207). The first light-emitting diode (LED1) may include a first pixel electrode (310), a counter electrode (500), and a first intermediate layer (410) between the first pixel electrode (310) and the counter electrode (500). The second light-emitting diode (LED2) may include a second pixel electrode (320), a counter electrode (500), and a second intermediate layer (420) between the second pixel electrode (320) and the counter electrode (500). The third light-emitting diode (LED3) may include a third pixel electrode (330), a counter electrode (500), and a third intermediate layer (420) between the third pixel electrode (330) and the counter electrode (500).

[0058] The first pixel electrode (310), the second pixel electrode (320), and the third pixel electrode (330) may be spaced apart from each other. The counter electrode (500) may be shared among the first to third light-emitting diodes (LED1, LED2, LED3). The counter electrode (500) may be formed on the substrate (100) to overlap the first pixel electrode (310), the second pixel electrode (320), and the third pixel electrode (330).

[0059] In one embodiment, the first functional layer (405) and the second functional layer (450) may be shared among the first to third light-emitting diodes (LED1, LED2, LED3). The first functional layer (405) may be a common layer and may be disposed between the first to third pixel electrodes (310, 320, 330) and the counter electrode (500). For example, the first functional layer (405) may be interposed between the first to third pixel electrodes (310, 320, 330) and the first to third intermediate layers (410, 420, 430). The first functional layer (405) may be a hole injection layer (HIL). For example, the first functional layer (405) may be a p-hole injection layer (p-HIL) containing p-type impurities. The second functional layer (450) is a type of common layer and can be disposed between the first to third intermediate layers (410, 420, 430) and the counter electrode (500). In one embodiment, the second functional layer (450) may include an electron transfer layer (ETL). In one embodiment, the second functional layer (450) may include an electron transfer layer (ETL) and an electron injection layer (EIL).

[0060] Each of the first pixel electrode (310), the second pixel electrode (320), and the third pixel electrode (330) may be a (semi)transparent electrode or a reflective electrode. Each of the first pixel electrode (310), the second pixel electrode (320), and the third pixel electrode (330) may include a reflective layer comprising Ag, Mg, Al, Pt, Pd, Au, Ni, Nd, Ir, Cr, and compounds thereof, and a transparent or semitransparent electrode layer located on the reflective layer. The transparent or semitransparent electrode layer may include at least one selected from the group comprising indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), indium oxide (In2O3), indium gallium oxide (IGO), and aluminum zinc oxide (AZO). Each of the first pixel electrode (310), the second pixel electrode (320), and the third pixel electrode (330) may have a three-layer structure of ITO / Ag / ITO.

[0061] The bank layer (209) covers the edges of each of the first pixel electrode (310), the second pixel electrode (320), and the third pixel electrode (330). The bank layer (209) can increase the distance between the edges of each of the first pixel electrode (310), the second pixel electrode (320), and the third pixel electrode (330) and the opposing electrode (500). Thus, it can serve to prevent arcs, etc. from occurring at the edges of each of the first pixel electrode (310), the second pixel electrode (320), and the third pixel electrode (330).

[0062] The bank layer (209) may include an insulating material. In one embodiment, the bank layer (209) may include one or more organic insulating materials selected from the group consisting of polyimide, polyamide, acrylic resin, benzocyclobutene, and phenolic resin. In one embodiment, the bank layer (209) may have a colored material. For example, the bank layer (209) may have a colored pigment, such as a pigment of a predetermined color such as white or black. In one embodiment, the bank layer (209) may have black. For example, the bank layer (209) may include a polyimide (PI)-based binder and a pigment mixed with red, green, and blue. Alternatively, the bank layer (209) may include a cardo-based binder resin and a mixture of a lactam-based black pigment and a blue pigment. Alternatively, the bank layer (209) may include carbon black.

[0063] The bank layer (209) may include a first opening (OP1), a second opening (OP2), and a third opening (OP3) that overlap each of the first pixel electrode (310), the second pixel electrode (320), and the third pixel electrode (330). The first opening (OP1), the second opening (OP2), and the third opening (OP3) of the bank layer (209) may each expose a portion of the first pixel electrode (310), the second pixel electrode (320), and the third pixel electrode (330). The first opening (OP1), the second opening (OP2), and the third opening (OP3) of the bank layer (209) may each correspond to a light-emitting region of the first to third light-emitting diodes (LED1, LED2, LED3), and the light-emitting region of the first to third light-emitting diodes (LED1, LED2, LED3) may each correspond to a light-emitting region of the first to third pixels (P1, P2, P3) (or a pixel region of the first to third pixels (P1, P2, P3)).

[0064] The first intermediate layer (410) is interposed between the first pixel electrode (310) and the counter electrode (500) and may overlap with the first pixel electrode (310) and the counter electrode (500). The first intermediate layer (410) has a width (or size) greater than the width (or size) of the first opening (OP1) of the bank layer (209), and the edge of the first intermediate layer (410) may be located on the upper surface of the bank layer (209).

[0065] The first intermediate layer (410) includes a plurality of sublayers, wherein the sublayers may include a plurality of light-emitting layers (hereinafter referred to as sub-light-emitting layers) that emit light of a first color. In this regard, FIG. 3 illustrates that the first intermediate layer (410) includes a first substack (4110) including a first sub-light-emitting layer and a second substack (4120) including a second sub-light-emitting layer.

[0066] The first substack (4110) may overlap with the first pixel electrode (310) and extend onto the bank layer (209). The edge of the first substack (4110) may be located on the upper surface of the bank layer (209). One side (e.g., lower surface) of the first substack (4110) facing the first pixel electrode (310) may be in direct contact with the first functional layer (405). For example, the first substack (4110) that is in direct contact with the first functional layer (405) as a whole may include a plurality of sublayers including a first sub-light-emitting layer, and the specific structure of the first substack (4110) will be described later with reference to FIG. 4.

[0067] The second substack (4120) overlaps with the first pixel electrode (310) on the first substack (4110) and may extend onto the bank layer (209). The edge of the second substack (4120) may be located on the upper surface of the bank layer (209).

[0068] A part of the second substack (4120), for example, the inner region of the second substack (4120), may be in direct contact with the first substack (4110). The edge of the second substack (4120) is spaced apart from the edge of the first substack (4110). The outer region including the edge of the second substack (4120) is spaced apart from the outer region including the edge of the first substack (4110). For example, a part of the second intermediate layer (420) (e.g., the outer region of the second intermediate layer (420)) or a part of the third intermediate layer (430) (e.g., the outer region of the third intermediate layer (430)) may be interposed between the outer region of the second substack (4120) and the outer region of the first substack (4110). The outer region of the second substack (4120) does not come into direct contact with the outer region of the first substack (4110) disposed on the bank layer (209). The second substack (4120) may include a plurality of sublayers including a second sub-luminescent layer, and the specific structure of the second substack (4120) will be described later with reference to FIG. 4.

[0069] The second intermediate layer (420) may include a plurality of sublayers. The second intermediate layer (420) may include a light-emitting layer that emits light of a second color. The process of forming the second intermediate layer (420) may be carried out between the process of forming the first substack (4110) of the first intermediate layer (410) and the process of forming the second substack (4120), and thus a portion of the second intermediate layer (420) may be interposed between the first substack (4110) and the second substack (4120) on the bank layer (209).

[0070] The third intermediate layer (430) may include a plurality of sublayers. The third intermediate layer (430) may include a light-emitting layer that emits light of a third color. The process of forming the third intermediate layer (430) may be carried out between the process of forming the first substack (4110) of the first intermediate layer (410) and the process of forming the second substack (4120), and thus a portion of the third intermediate layer (430) may be interposed between the first substack (4110) and the second substack (4120) on the bank layer (209).

[0071] The light-emitting layers included in each of the first to third intermediate layers (410, 420, 430) may emit light of different colors. For example, the first color of light emitted from the first and second sub-light-emitting layers included in the first and second sub-stacks (4110, 4120) of the first intermediate layer (410) may be blue light. The second color of light emitted from the light-emitting layer included in the second intermediate layer (420) may be green (or red) light, or the third color of light emitted from the light-emitting layer included in the third intermediate layer (430) may be red (or green) light. In the case of the first intermediate layer (410) emitting blue light, it may be a kind of tandem structure including the first and second sub-stacks (4110, 4120), which can improve light efficiency and lifespan.

[0072] FIG. 4 is an enlarged cross-sectional view of a portion corresponding to the first pixel (P1) and the second pixel (P2) of a display panel (10) according to an embodiment of the present invention, which is an enlarged cross-sectional view of portion IV of FIG. 3. FIG. 5 is an enlarged cross-sectional view of a portion corresponding to the first pixel and the third pixel of a display panel (10) according to an embodiment of the present invention, which is an enlarged cross-sectional view of portion V of FIG. 3. FIG. 6 is a schematic diagram showing the stacking structure for each pixel of a display panel (10) according to an embodiment of the present invention.

[0073] Referring to FIG. 4, the bank layer (209) is disposed on the first and second pixel electrodes (310, 320), and the first functional layer (405) may be disposed on the bank layer (209). The first functional layer (405) may overlap with the first pixel electrode (310), the second pixel electrode (320), and the bank layer (209), and may be interposed between the first pixel electrode (310) and the first intermediate layer (410), and between the second pixel electrode (320) and the second intermediate layer (420). The first functional layer (405) may include a hole injection layer (e.g., p-HIL) or an electron injection layer (e.g., p-HIL) and an electron transport layer.

[0074] The first functional layer (405) can be in direct contact with the first pixel electrode (310) through the first opening (OP1) and can be in direct contact with the second pixel electrode (320) through the second opening (OP2). The first functional layer (405) can be in direct contact with the upper surface of the bank layer (209), and in this regard, FIG. 4 illustrates that the first functional layer (405) is in direct contact with a part of the bank layer (209) between the first and second pixel electrodes (310, 320) (hereinafter referred to as the first part (209A)).

[0075] The first intermediate layer (410) may include a first sub-emissive layer (4113) and a second sub-emissive layer (4124). The first intermediate layer (410) may include a charge generating layer between the first sub-emissive layer (4113) and the second sub-emissive layer (4124), and in this regard, FIG. 4 illustrates an electron generating layer (4115) as a negative charge generating layer and a hole generating layer (4121) as a positive charge generating layer between the first sub-emissive layer (4113) and the second sub-emissive layer (4124).

[0076] The electron generation layer (4115) may be an n-type charge generation layer. The electron generation layer (4115) may supply electrons. The electron generation layer (4115) may include an n-type host material and an n-type dopant. It may include an n-type dopant material and an n-type host material. The n-type dopant material may be a metal of Group 1 or Group 2 on the periodic table, or an organic material capable of injecting electrons, or a mixture thereof. For example, the n-type dopant material may be either an alkali metal or an alkaline earth metal. The electron generation layer (4115) may be composed of an organic layer doped with an alkali metal such as lithium (Li), sodium (Na), potassium (K), or cesium (Cs), or an alkaline earth metal such as magnesium (Mg), strontium (Sr), barium (Ba), or radium (Ra), but the present invention is not limited thereto. The n-type host material may include an organic material capable of transferring electrons. For example, the n-type host material may be composed of one or more of Alq3 (tris(8-hydroxyquinolino)aluminum), Liq (8-hydroxyquinolinolato-lithium), PBD (2-(4-biphenylyl)-5-(4-tert-butylphenyl)-1,3,4-oxadiazole), TAZ (3-(4-biphenyl)4-phenyl-5-tert-butylphenyl-1,2,4-triazole), spiro-PBD, and BAlq (bis(2-methyl-8-quinolinolate)-4-(phenylphenolato)aluminum), SAlq, TPBi (2,2',2-(1,3,5-benzinetriyl)-tris(1-phenyl-1-H-benzimidazole), oxadiazole, triazole, phenanthroline, benzoxazole, or benzthiazole, and the present The invention is not limited to this.

[0077] The hole generation layer (4121) may be a p-type charge generation layer. The hole generation layer (4121) may supply holes. The hole generation layer (4121) may include a p-type host material and a p-type dopant material. The p-type dopant material may be an organic material such as a metal oxide, tetrafluoro-tetracyanoquinodimethane (F4-TCNQ), HAT-CN (Hexaazatriphenylene-hexacarbonitrile), hexaazatriphenylene, or V2O5, MoO2 x The p-type host material may be composed of metal materials such as WO3, but is not limited thereto. The p-type host material may be composed of one or more organic materials capable of transmitting holes, such as NPD (N,N-dinaphthyl-N,N'-diphenyl benzidine) (N,N'-bis(naphthalene-1-yl)-N,N'-bis(phenyl)-2,2'-dimethylbenzidine), TPD (N,N'-bis-(3-methylphenyl)-N,N'-bis-(phenyl)-benzidine), and MTDATA (4,4',4-Tris(N-3-methylphenyl-N-phenyl-amino)-triphenylamine), but the present invention is not limited thereto.

[0078] The electron generation layer (4115) and the hole generation layer (4121) may be in direct contact with each other in an area corresponding to the first aperture (OP1), for example, an area corresponding to the first pixel (P1). The electron generation layer (4115) and the hole generation layer (4121) may be spaced apart from each other in a non-pixel area (NP). The electron generation layer (4115) is a sublayer of the first substack (4110), and the hole generation layer (4121) is a sublayer of the second substack (4120). The outer region of the electron generation layer (4115), including the edge of the electron generation layer (4115), and the outer region of the hole generation layer (4121), including the edge of the hole generation layer (4121), may be spaced apart from each other along the stacking direction (e.g., z-direction) of the electron generation layer (4115) and the hole generation layer (4121) without direct contact.

[0079] The first substack (4110) of the first intermediate layer (410) may include a first sub-emissive layer (4113) that emits light of a first color (e.g., blue), a first sub-hole transport layer (4111) which is a hole transport layer (HTL) between the first pixel electrode (310) and the first sub-emissive layer (4113), an electron generation layer (4115) located on the opposite side of the first sub-hole transport layer (4111) with the first sub-emissive layer (4113) in between, and a first sub-electron transport layer (4114) between the first sub-emissive layer (4113) and the electron generation layer (4115).

[0080] In one embodiment, the first substack (4110) may include a first auxiliary layer (4112) between the first subhole transport layer (4111) and the first subluminescent layer (4113). The first auxiliary layer (4112) can improve the light generation efficiency of the first subluminescent layer (4113) by adjusting the hole charge balance. The first auxiliary layer (4112) may have a thickness determined according to the resonance period of the light emitted from the first subluminescent layer (4113) and can improve the color purity of the light emitted from the first subluminescent layer (4113).

[0081] The second substack (4120) of the first intermediate layer (410) may include a second sub-emissive layer (4124) that emits light of a first color, a hole generating layer (4121) between the first substack (4110) and the second sub-emissive layer (4124), and a second sub-hole transport layer (4122) which is a hole transport layer (HTL) between the hole generating layer (4121) and the second sub-emissive layer (4124).

[0082] In one embodiment, the second substack (4120) may include a second auxiliary layer (4123) between the second subhole transport layer (4122) and the second subluminescent layer (4124). The second auxiliary layer (4123) can improve the light generation efficiency of the second subluminescent layer (4124) by adjusting the hole charge balance.

[0083] The second functional layer (450), such as an electron transport layer, may be interposed between the second substack (4120) and the opposing electrode (500) and may overlap with the second substack (4120). The second functional layer (450), such as an electron transport layer, may be extended to the second intermediate layer (420) located at the second pixel (P2) as a common layer and may overlap with the second intermediate layer (420) and the first part (209A) of the bank layer (209) between the first pixel (P1) and the second pixel (P2).

[0084] The second intermediate layer (420) may include a second light-emitting layer (4204) that emits light of a second color (e.g., green), a second hole transport layer (4201) between the second pixel electrode (320) and the second light-emitting layer (4204), and a resonance assist layer (4202) between the second hole transport layer (4201) and the second light-emitting layer (4204). The resonance assist layer (4202) is a layer for matching the resonance distance of the second color and may be a type of assist hole transport layer.

[0085] The second intermediate layer (420) may include a second auxiliary layer (4203) between the resonant auxiliary layer (4202) and the second light-emitting layer (4204). The second auxiliary layer (4203) can improve the light generation efficiency of the second light-emitting layer (4204) by adjusting the hole charge balance. It can also improve the color purity of the light emitted from the second light-emitting layer (4204).

[0086] Referring to FIG. 5, the bank layer (209) is disposed on the first to third pixel electrodes (310, 330), and the first functional layer (405) may be disposed on the bank layer (209). The first functional layer (405) may overlap with the first pixel electrode (310), the third pixel electrode (330), and the bank layer (209), and may be interposed between the first pixel electrode (310) and the first intermediate layer (410), and between the third pixel electrode (330) and the third intermediate layer (430).

[0087] The first functional layer (405) can be in direct contact with the first pixel electrode (310) through the first opening (OP1) and can be in direct contact with the third pixel electrode (330) through the third opening (OP3). The first functional layer (405) can be in direct contact with the upper surface of the bank layer (209), and in this regard, FIG. 5 illustrates that the first functional layer (405) is in direct contact with a part of the bank layer (209) between the first and third pixel electrodes (310, 330) (hereinafter referred to as the second part (209B)). The specific structure of the first intermediate layer (410) shown in FIG. 5 is as described above with reference to FIG. 4.

[0088] The third intermediate layer (430) may include a third light-emitting layer (4304) that emits light of a third color (e.g., red), a third hole transport layer (4301) between the third pixel electrode (330) and the third light-emitting layer (4304), and a resonance assist layer (4302) between the third hole transport layer (4301) and the third light-emitting layer (4304). The resonance assist layer (4202) is a layer for matching the resonance distance of the third color and may be a type of assist hole transport layer.

[0089] The third intermediate layer (430) may include a third auxiliary layer (4303) between the resonant auxiliary layer (4302) and the third light-emitting layer (4304). The third auxiliary layer (4303) can improve the light generation efficiency of the third light-emitting layer (4304) by adjusting the hole charge balance.

[0090] Referring to FIGS. 4, 5 and 6, a portion of each of the second intermediate layer (420) and the third intermediate layer (430) in the non-pixel area (NP) may be interposed between the first substack (4110) and the second substack (4120).

[0091] As illustrated in FIGS. 4 and 6, on the first portion (209A) of the bank layer (209) corresponding to the non-pixel area (NP), a portion of the second intermediate layer (420) may be interposed between the first substack (4110) and the second substack (4120). For example, a portion of each of the sublayers (e.g., 4201, 4202, 4203, 4204) of the second intermediate layer (420) may be interposed between the electron generation layer (4115) of the first substack (4110) and the hole generation layer (4121) of the second substack (4120).

[0092] As illustrated in FIGS. 5 and 6, on the second portion (209B) of the bank layer (209) corresponding to the non-pixel area (NP), a portion of the third intermediate layer (430) may be interposed between the first substack (4110) and the second substack (4120). For example, a portion of each of the sublayers (e.g., 4301, 4302, 4303, 4304) of the third intermediate layer (430) may be interposed between the electron generation layer (4115) of the first substack (4110) and the hole generation layer (4121) of the second substack (4120).

[0093] In some embodiments, through a structure in which the second intermediate layer (420) and the third intermediate layer (430) are each interposed between the first substack (4110) and the second substack (4120), unintended light emission in some areas of the display panel (10) can be prevented.

[0094] As a comparative example of the present invention, a case is described in which a second substack (4120) is placed below a second intermediate layer (420) and a third intermediate layer (430), and a first light-emitting diode (LED1) is ON and a second and third light-emitting diode (LED2, LED3) is OFF. In this case, some of the holes of the first pixel electrode (210) move toward the second and third pixels (P2, P3) through the first functional layer (405), and some of the holes generated in the hole generation layer (4121) of the second substack (4120) move past the second substack (4120) to the second intermediate layer (420) and the third intermediate layer (430), and unintended light may be emitted in the area corresponding to the second and third pixels (P2, P3) and / or non-pixel area (NP).

[0095] As another comparative example of the present invention, a case is described in which a first substack (4110) is placed on top of a second intermediate layer (420) and a third intermediate layer (430), and a first light-emitting diode (LED1) is ON and the second and third light-emitting diodes (LED2, LED3) are OFF. In this case, some electrons that did not form excitons in the first sub-light-emitting layer (4113) of the first substack (4110) may move along the -z direction and flow into the second intermediate layer (420) and the third intermediate layer (430), and some holes of the first pixel electrode (310) may move to a non-pixel area (NP) through the first functional layer (405). In this case, light corresponding to a second color or a third color may be unintentionally emitted from the non-pixel area (NP). The aforementioned phenomenon may be prominently displayed in low grayscale.

[0096] However, according to an embodiment of the present invention, unintended light emission as described above can be prevented by the structure described with reference to FIGS. 3 to 5.

[0097] For example, as illustrated in FIG. 6, when the first light-emitting diode (LED1) is ON and the second and third light-emitting diodes (LED2, LED3) are OFF, electrons in the electron generation layer (4115) of the first substack (4110) corresponding to the first light-emitting diode (LED1) move in the -z direction, and holes in the hole generation layer (4115) of the second substack (4120) move in the z direction, so that light corresponding to the second color and the third color is not unintendedly emitted in the non-pixel area (NP) even though the first and second substacks (4110, 4120) overlap with the second and third intermediate layers (420, 430) in the non-pixel area (NP).

[0098] As illustrated in FIG. 6, when the first light-emitting diode (LED1) is ON and the second and third light-emitting diodes (LED2, LED3) are OFF, some holes of the first pixel electrode (310) may move toward the second and third pixels (P2, P3) by passing through the non-pixel area (NP) via the first functional layer (405), but the movement of the aforementioned holes may be prevented by the first substack (4110) on the first functional layer (405) in the non-pixel area (NP). For example, electrons that do not form excitons in the first sub-emissive layer (4113) of the first substack (4110) can be accumulated below the first sub-emissive layer (4113) (e.g., in the -z direction), and holes directed toward the second and third pixels (P2, P3) through the first functional layer (405) by the aforementioned electrons can be trapped. In other words, the path of holes directed toward the second and third pixels (P2, P3) through the first functional layer (405) can be blocked. Thus, the phenomenon in which the second color light and / or the third color light is dimly lit in the second and third pixels (P2, P3) even though the second and third light-emitting diodes (LED2, LED3) are off can be prevented.

[0099] FIG. 7 is an enlarged cross-sectional view of a portion corresponding to a first pixel of a display panel (10) according to one embodiment of the present invention, which may correspond to portion VII of FIG. 3.

[0100] Referring to FIG. 7, the first intermediate layer (410) includes a first substack (4110) and a second substack (4120), and a second intermediate layer (420) or a third intermediate layer (430) may be interposed between the first substack (4110) and the second substack (4120) in a non-pixel area (NP). The specific configuration of the first intermediate layer (410), the second intermediate layer (420), and the third intermediate layer (430) is as described above with reference to FIG. 4 to 6, and will be described below focusing on the differences.

[0101] In one embodiment, the width (W4115, W4114) of the electron generation layer (4115) and / or the first sub-electron transport layer (4114) of the first intermediate layer (410) may be smaller than the width of the hole transport layer of the first intermediate layer (410). For example, the width (W4115) of the electron generation layer (4115) and the width (W4114) of the first sub-electron transport layer (4114) may be smaller than the width (W4122) of the second sub-hole transport layer (4122). The width (W4111) of the first sub-hole transport layer (4111) may be relatively larger than the width (W4115) of the electron generation layer (4115) and the width (W4114) of the first sub-electron transport layer (4114).

[0102] As explained with reference to FIG. 6, when the first pixel (P1) is ON and the second and third pixels (P2, P3) are OFF, electrons moving from the counter electrode (500) toward the first intermediate layer (410) that do not form excitons in the second sub-emissive layer (4124) can proceed toward the second sub-hole transport layer (4122). As a comparative example, if the width (W4115) of the electron generation layer (4115) and the width (W4114) of the first sub-electron transport layer (4114) are larger than that of the second sub-emissive layer (4124), the second sub-hole transport layer (4122) may come into contact with the electron generation layer (4115) and / or the first sub-electron transport layer (4114) due to a process error. In this case, the light emission from the first sub-stack (4110) may deviate from the intended brightness range or affect surrounding layers, such as the second and third intermediate layers (420, 430), but this can be prevented if the structure described above is provided.

[0103] Although the present invention has been described above with reference to an embodiment illustrated in the drawings, this is merely illustrative, and those skilled in the art will understand that various modifications and variations of the embodiments are possible therefrom. Accordingly, the true technical scope of protection of the present invention should be determined by the technical spirit of the appended claims. Explanation of the symbols

[0104] 1: Electronic device 10: Display panel 310, 320, 330: 1st to 3rd pixel electrodes 405: First functional layer 410, 420, 430: 1st to 3rd intermediate layers 450: Second functional layer 500: Counter electrode 4110: 1st substack 4120: 2nd substack

Claims

Claim 1 A first pixel electrode and a second pixel electrode spaced apart from each other; a bank layer comprising a first opening corresponding to the first pixel electrode and a second opening corresponding to the second pixel electrode; a counter electrode disposed on the bank layer and overlapping with the first pixel electrode and the second pixel electrode; a first intermediate layer interposed between the first pixel electrode and the counter electrode, wherein the first intermediate layer comprises a first sub-emissive layer that overlaps with the first pixel electrode and emits light of a first color; A display panel comprising: a second substack disposed on the first substack and including a second sub-emissive layer emitting light of the same color as the first sub-emissive layer; a second intermediate layer interposed between the second pixel electrode and the counter electrode, overlapping with the second pixel electrode, and including a second light-emitting layer emitting light of a second color different from the first color; wherein a portion of the second intermediate layer is interposed between the first substack and the second substack on a first portion of the bank layer between the first pixel electrode and the second pixel electrode. Claim 2 A display panel according to claim 1, further comprising a hole injection layer, wherein the hole injection layer overlaps the first pixel electrode, the first portion of the bank layer, and the second pixel electrode, and is interposed between the first pixel electrode and the first intermediate layer and between the second pixel electrode and the second intermediate layer. Claim 3 A display panel according to claim 1, wherein the first intermediate layer is interposed between the first sub-emissive layer and the second sub-emissive layer and includes a charge generating layer comprising an electron generating layer and a hole generating layer, wherein the electron generating layer is a sublayer of the first substack and the hole generating layer is a sublayer of the second substack. Claim 4 In claim 3, the first substack comprises: the first sub-emissive layer; the first sub-hole transport layer between the first pixel electrode and the first sub-emissive layer; the electron generation layer located opposite the first sub-hole transport layer with the first sub-emissive layer in between; and the first sub-electron transport layer between the first sub-emissive layer and the electron generation layer; a display panel. Claim 5 In claim 4, the second substack comprises: the second subluminescent layer; the hole generating layer between the first substack and the second subluminescent layer; and the second sub-hole transport layer between the hole generating layer and the second subluminescent layer; a display panel. Claim 6 In claim 5, the width of each of the electron generation layer and the first sub-electron transport layer of the first sub-stack is smaller than the width of the second sub-hole transport layer, a display panel. Claim 7 A display panel according to claim 5, further comprising an electron transport layer interposed between the counter electrode and the second substack of the first intermediate layer. Claim 8 In claim 7, the electron transport layer extends to be interposed between the counter electrode and the second intermediate layer, and overlaps with the second substack of the first intermediate layer, the second intermediate layer, and the first portion of the bank layer, a display panel. Claim 9 A display panel according to claim 1, wherein the first color is blue and the second color is red or green. Claim 10 A display panel according to claim 1, further comprising: a third pixel electrode spaced apart from the first pixel electrode; and a third intermediate layer interposed between the third pixel electrode and the counter electrode, overlapping with the third pixel electrode, and emitting light of a third color different from the first color and the second color, wherein a portion of the third intermediate layer is interposed between the first substack and the second substack on a second portion of the bank layer between the first pixel electrode and the third pixel electrode. Claim 11 An electronic device comprising a display panel including a first pixel, a second pixel, and a third pixel, wherein the display panel, A first pixel electrode corresponding to the first pixel; A second pixel electrode corresponding to a second pixel and spaced apart from the first pixel electrode; a bank layer comprising a first opening corresponding to the first pixel electrode and a second opening corresponding to the second pixel electrode; a counter electrode disposed on the bank layer and overlapping with the first pixel electrode and the second pixel electrode; a first substack comprising a first intermediate layer interposed between the first pixel electrode and the counter electrode, wherein the first intermediate layer is interposed between the first pixel electrode and the counter electrode, and the first intermediate layer is overlapped with the first pixel electrode and includes a first subluminescent layer emitting light of a first color; An electronic device comprising: a second substack disposed on the first substack and including a second sub-emissive layer emitting light of the same color as the first sub-emissive layer; a second intermediate layer interposed between the second pixel electrode and the counter electrode, overlapping with the second pixel electrode, and including a second emissive layer emitting light of a second color different from the first color; wherein the first substack includes an electron generating layer and the second substack includes a hole generating layer, and a portion of the second intermediate layer is interposed between the electron generating layer and the hole generating layer on a first portion of the bank layer between the first pixel electrode and the second pixel electrode. Claim 12 An electronic device according to claim 11, wherein the display panel further comprises a hole injection layer, the hole injection layer overlaps the first pixel electrode, the first portion of the bank layer, and the second pixel electrode, and is interposed between the first pixel electrode and the first intermediate layer and between the second pixel electrode and the second intermediate layer. Claim 13 In claim 11, the first substack comprises: the first sub-emissive layer; the first sub-hole transport layer between the first pixel electrode and the first sub-emissive layer; the electron generation layer located opposite the first sub-hole transport layer with the first sub-emissive layer in between; and the first sub-electron transport layer between the first sub-emissive layer and the electron generation layer; a display panel. Claim 14 An electronic device according to claim 13, wherein the second substack comprises: the second subluminescent layer; the hole generating layer between the first substack and the second subluminescent layer; and the second sub-hole transport layer between the hole generating layer and the second subluminescent layer. Claim 15 An electronic device according to claim 14, wherein the width of each of the electron generation layer and the first sub-electron transport layer of the first sub-stack is smaller than the width of the second sub-hole transport layer. Claim 16 An electronic device according to claim 11, wherein the display panel further comprises an electron transport layer interposed between the opposing electrode and the second substack of the first intermediate layer. Claim 17 An electronic device according to claim 16, wherein the electron transport layer extends to be interposed between the counter electrode and the second intermediate layer, and overlaps with the second substack of the first intermediate layer, the second intermediate layer, and the first portion of the bank layer. Claim 18 An electronic device according to claim 11, wherein the first color is blue and the second color is red or green. Claim 19 The electronic device according to claim 11, wherein the display panel further comprises: a third pixel electrode corresponding to the third pixel and spaced apart from the first pixel electrode; and a third intermediate layer interposed between the third pixel electrode and the counter electrode, overlapping with the third pixel electrode, and emitting light of a third color different from the first color and the second color, wherein a portion of the third intermediate layer is interposed between the first substack and the second substack on a second portion of the bank layer between the first pixel electrode and the third pixel electrode.