System and method for interleaved power converter

Abstract

A method comprising an interleaved power converter system, an interleaved power converter module, and a control system is disclosed. The converter module comprises a DC link node, a first pair of transistors and a second pair of transistors coupled between the DC link nodes, an LC filter circuit, and an AC node. The control system comprises a central controller and one or more local controllers. Each local controller receives a respective reference target from the central controller and generates a variable frequency soft switching (VFSS) control signal to drive the first pair of transistors to output a first AC signal, and generates a phase-shifted VFSS control signal to drive the second pair of transistors to output a second AC signal that is phase-shifted with respect to the first AC signal. The interleaved power converter module outputs an interleaved signal comprising the first AC signal interleaved with the second AC signal through the LC filter circuit.

Description

Technology Field

[0001] Cross-reference regarding related applications

[0002] This application claims priority to U.S. Provisional Application No. 63 / 544,739, filed October 18, 2023, titled “SYSTEMS AND METHODS FOR INTERLEAVED POWER CONVERTERS,” the entirety of which is incorporated by reference into this specification.

[0003] Statement regarding federal government-funded research

[0004] Not applicable. Background Technology

[0005] Various types of power converters have been produced and used in many industries and situations. Exemplary power converters include AC-to-DC rectifiers, DC-to-AC inverters, and DC-to-DC converters. AC-to-DC rectifiers, also referred to as AC / DC rectifiers, convert AC power into DC power. DC-to-AC inverters, also referred to as DC / AC inverters, convert DC power into AC power. Power converters can be used for various purposes, such as rectifying AC power from an AC grid power source into DC power to charge a battery, or inverting DC power from a battery into AC power to drive a motor or supply AC power to the AC grid. Additionally, power converters can be used in various situations, such as in or related to electric vehicles, engine generators, and solar panels.

[0006] Power converters can be described in terms of power conversion efficiency, power density, and cost, among other characteristics. Generally, it is desirable to have power converters with higher power efficiency, higher power density, and lower cost. High-efficiency power converters are capable of converting power without significant energy loss (e.g., AC to DC, DC to AC, and / or DC to DC). Low-efficiency power converters experience higher energy loss during power conversion. This energy loss can manifest, for example, as heat generated by the power converter during power conversion. The power efficiency of a power converter, inductor, or other electronic component can be expressed as a percentage from 0 to 100%, based on the power input to the component and the power output from the component, using the formula: It can be determined using [the formula]. A power converter with high power density has a high power output ratio relative to the physical space occupied by the power converter. Power density is given by the formula: It can be calculated using .

[0007] Energy costs, including monetary and environmental costs, remain a significant factor across many industries involving power converters. Accordingly, even a slight increase in power efficiency for power converters (e.g., one-tenth of a percent) can be substantial and highly desirable. Similarly, a reduction in the size and materials of power converters can be substantial and highly desirable, allowing for a reduction in the physical space and cost required to accommodate power converters in systems containing them.

[0008] Some embodiments disclosed herein address these or other problems. For example, some embodiments disclosed herein relate to interleaved power converters. By interleaving power converters, the efficiency and / or power density of the power converters can ultimately be improved.

[0009] In one embodiment, an interleaved power converter system is provided. The system includes an interleaved power converter module and a control system. The interleaved power converter module includes a direct current (DC) link node, a first pair of transistors and a second pair of transistors coupled between the DC link nodes, an LC filter circuit, and an alternating current (AC) node. The control system controls the interleaved power converter module and includes a central controller and a local controller. The central controller is configured to generate a reference target based on the sensed characteristics of the interleaved power converter module. The local controller is configured to: receive the reference target and, based on the reference target and the sensed characteristics, generate a variable frequency soft switching (VFSS) control signal to drive the first pair of transistors to output a first AC signal, and, based on the reference target and the sensed characteristics, generate a phase-shifted VFSS control signal to drive the second pair of transistors to output a second AC signal that is phase-shifted relative to the first AC signal. The interleaved power converter module outputs an interleaved signal including the first AC signal interleaved with the second AC signal through the LC filter circuit.

[0010] In one embodiment, an interleaved power converter method is provided. The method includes the step of receiving a reference target generated by a local controller from a central controller based on a detected characteristic of an interleaved power converter module, wherein the interleaved power converter module includes a direct current (DC) link node, a first pair of transistors and a second pair of transistors coupled between the DC link nodes, an LC filter circuit, and an alternating current (AC) node. The method further includes the step of generating a variable frequency soft switching (VFSS) control signal for driving a first pair of transistors to output a first AC signal based on the reference target and the detected characteristic, and the step of generating a phase-shifted VFSS control signal for driving a second pair of transistors to output a second AC signal phase-shifted with respect to the first AC signal based on the reference target and the detected characteristic. The method further includes the step of outputting an interleaved signal comprising a first AC signal interleaved with a second AC signal through an LC filter circuit.

[0011] The aforementioned aspects and other aspects and advantages of the present disclosure will become apparent from the following description. In the description, reference is made to the accompanying drawings, which form part of the specification and in which one or more embodiments are illustrated as examples. However, these embodiments do not necessarily represent the entire scope of the invention, and therefore, the claims and the specification are referenced to interpret the scope of the invention. In the following description, similar reference numbers will be used to refer to similar parts between the drawings. Brief explanation of the drawing

[0012] Figure 1a illustrates a half-bridge power converter. Figure 1b shows the inductor current waveform of the half-bridge power converter of Figure 1a. FIG. 2 illustrates a power converter system according to some embodiments. FIGS. 3a to 3c illustrate an exemplary configuration of the power converter system of FIG. 2. FIGS. 4a and 4b illustrate a control system diagram implemented by a power converter (e.g., the power converter of FIG. 1, FIG. 3a, FIG. 3b, or FIG. 3c) according to some embodiments. FIGS. 5a through 5h illustrate examples of switching circuits of one or more interleaved power converter modules of a power converter (e.g., the power converter of FIG. 1, FIG. 3a, FIG. 3b, or FIG. 3c) according to some embodiments. FIG. 6a illustrates an inductor current waveform for an interleaved converter module according to some embodiments. FIG. 6b illustrates a constant power curve and a soft switching operation region for an interleaved converter module according to some embodiments. FIG. 7 illustrates an inductor current plot, a phase current plot, and a frequency plot for an interleaved converter module according to some embodiments. FIG. 8 illustrates a method for interleaved power conversion according to some embodiments. FIG. 9 illustrates a model of a coupled inductor interleaved converter according to some embodiments. FIG. 10 illustrates an example of a local controller of FIG. 4b implementing model predictive control according to some embodiments. Specific details for implementing the invention

[0013] One or more embodiments are described and illustrated in the following description and the accompanying drawings. These embodiments are not limited to the specific details provided herein and may be modified in various ways. Furthermore, other embodiments not described herein may exist. Additionally, functions performed by multiple components may be integrated and performed by a single component. Similarly, functions described herein as being performed by a single component may be performed by multiple components in a distributed manner. Additionally, a component described as performing a specific function may also perform additional functions not described herein. For example, a device or structure "configured" in a specific manner may be configured at least in that manner, but may also be configured in a manner not enumerated.

[0014] As used in this application, "non-transient computer-readable media" includes all computer-readable media but is not composed of transient radio signals. Accordingly, non-transient computer-readable media may include, for example, a hard disk, a CD-ROM, an optical storage device, a magnetic storage device, ROM (Read Only Memory), RAM (Random Access Memory), a register memory, a processor cache, or any combination thereof.

[0015] Furthermore, the grammar and terminology used in this specification are for illustrative purposes only and should not be construed as restrictive. For example, the use of “comprising,” “comprising,” “containing,” or “having,” and variations thereof in this specification is intended to include additional items as well as the items and their equivalents listed below. Additionally, the terms “connection” and “combination” are used broadly and include both direct and indirect connections and combinations, and may denote physical or electrical connections or combinations. Furthermore, the phrase “and / or,” when used with two or more items, is intended to cover items individually and to cover both items together. For example, “a and / or b” is intended to cover a (not b); b (not a); and a and b.

[0016] In active power converters, power switching elements (also referred to as transistors) are switched on and off at high frequencies according to control signals to implement conversion. The control technology used to control these power switching elements can be referred to as hard switching or soft switching technology. In hard switching, when switching from an on state to an off state, or from an off state to an on state, both the current and voltage can be relatively high in the power switching element during the transition. This scenario causes high power loss during the transition. As the switching frequency increases, power loss and electromagnetic interference (EMI) can increase because each additional switching event causes power loss and noise. Accordingly, when controlling power switching elements, hard switching should generally be avoided at all operating points of the converter to prevent or reduce large switching losses and EMI issues.

[0017] Soft switching refers to a switching control technique in which a power switching element is controlled to have zero (or near-zero) voltage at the point of switching on or off. In some instances, hard switching turn-on of a switch (as opposed to turning off the switch) causes most of the switching losses. Accordingly, in some instances, soft switching to generate zero-voltage turn-on is of greater interest to reduce power loss and EMI noise.

[0018] Referring to FIG. 1a, a power converter (100) is illustrated. In the power converter (100), before the top switch is turned on, the inductor current (i L When ) switches polarity (to a sufficient degree), zero voltage turn-on (soft switching) occurs. This can be achieved by a large current ripple within the inductor. If the peak-to-peak ripple exceeds twice the average output current, this ripple will reverse the polarity in each cycle, as shown in FIG. 1b. To achieve this situation, a controller controlling the switching of the upper and lower switching elements controls the output current (i o It guarantees that this holds true as ) changes. This can always be achieved by having a large ripple, but excessive ripple increases resistance loss. Therefore, generally, the ripple should be controlled to be large enough to guarantee soft switching, but not larger.

[0019] Generally, the controller cannot control the rising and falling slopes of the current because these slopes are fixed by input and output voltages that the controller has not selected. However, the controller can adjust the switching frequency. Reducing the frequency allows the current to ramp up and down for a longer period, thereby increasing the ripple amplitude. This capability enables the controller to maintain the desired ripple across all operating points. An exemplary waveform is shown in Fig. 1b. The solid sine curve represents the average inductor current (average i L ) and after ripples are removed by the filter i o As shown by the output node. As illustrated, the actual inductor current (i L ) ensures soft switching by crossing the x-axis by a fixed amount in each cycle.

[0020] Zero-voltage switching occurs during the dead time when both switches are off and the current is reversed. During this time (and when the average current is positive), the inductor current (i L ) charges the output capacitance of the lower switch while discharging the output capacitance of the upper switch. Once the capacitance of the upper switch is completely discharged, the upper switch has zero voltage across it, and the upper switch can be turned on without loss. When the average current is negative, the same process can occur where the upper and lower switches switch roles and the lower switch turns on with zero voltage.

[0021] The switching frequency that causes such zero-voltage switching can be calculated from the geometric shape of the current waveform. Solving for the switching frequency yields the following equation:

[0022]

[0023] Here, i ois the output current, α is the ripple magnitude that must be greater than 2 (e.g., 2.2 to 2.4 is typical), and αI o =Δi L , that is, peak-to-peak inductor current ripple. The controller driving the switch uses this determined switching frequency (f SW This equation can be implemented to control the switching of the switch in ) (e.g., f SW (to determine).

[0024] f SW The maximum and minimum switching frequencies have practical limits. For example, the switching frequency (f SW The upper limit of ) can be set by losses. Switching at higher speeds at lower currents reduces resistance losses but increases switching losses. At some frequencies, the additional switching losses from higher-speed switching are greater than the reduction in resistance losses. Another upper limit for switching frequency comes from the dead time when both switches are off. At high frequencies and high or low duty cycles, the average switch node voltage may be distorted.

[0025] Switching frequency (f) SW The lower limit of ) can be set by the resonant frequency of the output LC filter. For example, the control equation may depend on a triangular current waveform. When the switching frequency approaches the resonant frequency too closely (approximately twice), the triangular shape of the current waveform begins to appear as a segment of a sine curve (having rounded peaks and valleys). Once this occurs, the converter may no longer function properly.

[0026] Reducing the switching frequency increases the ripple magnitude, and therefore the average inductor current (average i LIt increases the average inductor current. This average inductor current is shown by the load after the output filter. Therefore, the minimum switching frequency also corresponds to the maximum load current. If this limit is too low for the desired implementation of a particular converter, several options exist.

[0027] First, the inductance of the inductor can be reduced. This reduction in inductance increases the slope of the current waveform, thereby increasing the ripple for a given frequency and consequently the output current. However, reducing the inductance also increases the resonant frequency by the square root of the inductance, and thus reduces the gain. This has the effect of increasing the switching frequency across all operating points, which can reduce overall efficiency. Therefore, the amount by which the inductance can actually be reduced is limited.

[0028] An additional option for reducing the minimum switching frequency and, consequently, increasing the maximum load current is to implement a power converter with interleaving. In a power converter with interleaving, typically, the output of at least one pair of transistors is interleaved with the output of at least one other pair of transistors. To produce the interleaved output, the control signals for the transistor pairs can be phase-shifted with respect to each other.

[0029] Interleaving can be counterintuitive for converter design because it is typically desirable to reduce ripple within the inductor as much as possible. However, to implement soft switching, the ripple must exceed a certain level. Therefore, the interleaving concept provided herein can be configured to maintain sufficient current ripple within the inductor at each operating point to maintain soft switching, and to (primarily) offset the ripple within the capacitor.

[0030] Various converter circuit topologies that enable such control and generation of interleaved outputs are provided herein. Accordingly, systems and methods related to interleaved power converters, also referred to as voltage converters, are disclosed herein, which can provide power conversion having increased power efficiency, increased power density, and / or reduced cost, among other advantages.

[0031] FIG. 2 illustrates a power converter system (100) according to some embodiments. The power converter system (100) includes a control system (105), a first direct current (DC) source (110), a power converter (115), an alternating current (AC) load (130), and one or more sensors (140). The control system (105) includes a central controller (150) having an electronic processor (155) and a memory (157), and optionally, in some embodiments, includes one or more local controllers (160) each having an electronic processor (165) and a memory (167). The power converter system (100), as well as other power converter systems provided herein, may be non-isolated power converter systems. That is, the power converter system may be coupled to an AC source (e.g., a single-phase or three-phase power grid) or an AC load (e.g., a single-phase or three-phase motor) without a transformer. The use of a transformer is common in electrical circuits to provide isolation between the power converter and the AC source or load. However, such transformers can add inefficiency and size or volume to the power converter. Accordingly, the power converter system provided herein may be non-isolated, also referred to as transformerless, to increase efficiency and / or reduce the size of the power converter system. Since the power converter is provided without insulation by a transformer, the power converter may include additional features to prevent the transmission of unwanted signals or currents (e.g., leakage current) between the power converter and other circuit components (e.g., DC source, DC load, AC source, AC load, and other structures in contact with or supporting the power converter). These additional features may include LC filters, zero-sequence control of common-mode voltage, harmonic injection, model predictive control, variable frequency threshold soft switching, etc. However, in some examples, a transformer is used to couple one of the disclosed power converters to another circuit component and to provide isolation.

[0032] In operation, generally, the control system (105) controls the power switching elements of the power converter (115) with control signaling (e.g., pulse width modulation (PWM) signal) to convert power from a DC source (110) functioning as a source to an AC load (130) functioning as a load. In some examples, the power converter system (100) operates as a rectifier, and the control system (105) controls the power switching elements of the power converter (115) with control signaling (e.g., PWM signal) to convert power from an AC load (130) functioning as a source to a DC source (110) functioning as a load. In some examples, the power converter system (100) operates as a DC-DC converter, and the control system (105) controls the power switching element of the power converter (115) with a control signaling (e.g., a PWM signal) to convert power from a DC source (110) that functions as a source into a DC load that functions as a load (located instead of the AC load (130) in FIG. 2).

[0033] In some examples, the DC source (110) is a battery. In other examples, the DC source (110) may be a capacitor, an ultracapacitor, a DC power source from a rectified AC source (e.g., AC grid power converted into DC power by a diode bridge rectifier). In some examples, the AC load (130) may be an electric (AC) motor, an AC power grid, etc. The AC load (130) may be a single-phase AC load, a three-phase AC load, or an AC load having a different number of phases.

[0034] A DC source (110) is coupled to the power converter (115) on the first (DC) side or section of the power converter (115), and an AC load (130) is coupled to the power converter (115) on the second (AC) side or section of the power converter (115). The first side may also be referred to as the input side or DC side of the power converter (115). The second side may also be referred to as the input side or AC side of the power converter (115). In some embodiments, the AC side of the power converter (115) may be an AC side having single-phase AC power, three-phase AC power, or AC power having a different number of phases.

[0035] In some embodiments, the power converter (115) operates at a high DC voltage level. For example, at operation, the DC side of the power converter (115) has at least 200 V, at least 600 V, at least 800 V, at least 1000 V, at least 1200 V, 200 V to 1200 V, 600 V to 1200 V, 800 V to 1200 V, or other ranges of DC voltage (e.g., across the input terminal of the power converter (115)). Such high DC voltage levels may be desirable in some situations, such as with some electric vehicles. For example, some current electric vehicles (e.g., passenger cars and hybrid electric vehicles) operate at a DC bus voltage of about 200 V to 400 V. This DC bus voltage for passenger electric vehicles may be increased in the future. In addition, some current electric vehicles (e.g., Class 4 to 8, off-road, or other larger electric vehicles) can operate at a DC bus voltage of more than 1000 V.

[0036] The sensor(s) (140) include, for example, one or more current sensors and / or one or more voltage sensors. For example, the sensor(s) (140) may include each current sensor and / or voltage sensor for monitoring current and / or voltage of one or more of the DC load source (110), each phase of the AC load (130), or other nodes or components of the power converter (115). For example, when the interleaved power converter (115) includes an LC filter for each phase or leg of the converter, the sensor (140) may include one or more current sensors for each phase or leg to detect current at each phase or leg (e.g., at an inductor and / or output node for each phase or leg). In some embodiments, additional or fewer sensors (140) are included within the system (100). For example, the sensor (140) may also include one or more vibration sensors, temperature sensors, etc. In some examples, the control system (105) infers characteristics (e.g., current or voltage) of the power converter (115) rather than directly detecting characteristics. Sensor(s) (140) may provide sensor data to the control system (105) that indicates the detected characteristics of the system (100). Accordingly, such sensor data may indicate the electrical operation characteristics of the system (100). In some examples, the control system (105) infers or estimates characteristics (e.g., current or voltage) at one or more nodes of the power converter (115) based on sensor data from sensors (140) that detect different types of characteristics or even different components rather than directly detecting characteristics. However, unless otherwise noted, the detected characteristics may refer to the characteristics directly detected or inferred from other detected characteristics.

[0037] The input-output (I / O) interface (142) is configured to include or receive input from one or more inputs (e.g., one or more buttons, switches, touchscreens, keyboards, etc.) and / or to include or be configured to provide output to one or more outputs (e.g., LEDs, display screens, speakers, haptic generators, etc.). Other electronic devices and / or users may communicate with the system (100) and, in particular, the control system (105) through the I / O interface (142). For example, the control system (105) may receive commands to the power converter system (100) indicating a target torque, target speed, target power level, conversion type, etc. (e.g., from a user or other device). In response to this, the control system (105) may drive the power converter (115) to achieve the target and / or conversion type indicated by the command.

[0038] A control system (105) generally monitors a system (100) including a power converter (115) (e.g., based on sensor data from sensor(s) (140), receives a command (e.g., via an input / output interface (142)), and controls a power switching element of the power converter (115) with control signaling (e.g., pulse width modulation (PWM) signal) to convert power (e.g., according to sensor data and / or a command). In some embodiments, the control system (105) is a cascade control system including a central controller (150) and one or more local controllers (160). The cascade control system can communicate monitoring information (e.g., sensor data) and control information in real time (e.g., each control cycle) between the central controller (150) and one or more local controllers (160). In some examples, the local controller(s) (160) each implement Model Predictive Control (MPC) or other control schemes (e.g., PID control, PI control, etc.). In some examples, the central controller implements non-MPC control techniques such as Proportional-Integral-Derivative (PID) control or Proportional-Integral (PI) control.

[0039] Each controller of the control system (105), comprising a central controller (150) and local controllers (160), is an electronic controller that may include an electronic processor. Such electronic controllers may further include memory (e.g., memory (157 or 167)). The memory is, for example, one or more read-only memory (ROM), random access memory (RAM), or other non-transient computer-readable media. The electronic processor (155, 165) is configured to receive instructions and data from the memory (157, 167) and to execute instructions to perform the functions of the associated controller described herein, for example, including the processes described herein. For example, the memory may include control software. In some embodiments, instead of or in addition to executing software from the memory to perform the functions of the controller described herein, the electronic processor includes one or more hardware circuit elements configured to perform some or all of these functions. Additionally, while specific controllers, electronic processors, and memory may each be referred to as a single unit in this specification, in some embodiments, one or more of these components are distributed components. For example, in some embodiments, the electronic processor comprises one or more microprocessors and / or hardware circuit elements. In some examples, the central controller (150) and the local controller (160) are both implemented by a shared electronic processor (e.g., electronic processor (155)).

[0040] FIGS. 3a through 3c illustrate exemplary configurations of a power converter system (100) identified as power converters (300, 330, 360), respectively. In other examples, the power converter system (100) is implemented in a different configuration. In FIGS. 3a through 3c, the DC source (110), sensor (140), and input / output (145) are not illustrated for the sake of diagram simplification. In FIG. 3a, the power converter (300) is a half-bridge single-phase converter. The power converter (300) includes a central controller (150), one local controller (160), and an interleaved power converter (115). In this example, the interleaved power converter (115) includes one interleaved power converter module (305). In this example, the interleaved power converter module (305) includes a half-bridge single-phase converter circuit and is coupled to two terminals of a (single-phase) AC load (130). The interleaved power converter module (305) may be implemented, for example, as one of the switching circuits shown in FIGS. 5a through 5h, which will be described in more detail below.

[0041] In FIG. 3b, the power converter (330) is a full-bridge single-phase converter. The power converter (330) includes a central controller (150), two local controllers (160), and an interleaved power converter (115). In this example, the interleaved power converter (115) includes two interleaved power converter modules (305). In this example, each interleaved power converter module (305) includes a half-bridge single-phase converter circuit coupled to each terminal of a (single-phase) AC load (130). Generally, each of the two interleaved power converter modules (305) is driven to output an AC signal that is 180 degrees out of phase with respect to the other interleaved power converter module (305). Each interleaved power converter module (305) may be implemented as one of the switching circuits shown in FIG. 5a through 5h, which will be described in more detail below, for example.

[0042] In FIG. 3c, the power converter (360) is a three-phase converter. The power converter (360) includes a central controller (150), three local controllers (160), and an interleaved power converter (115). In this example, the interleaved power converter (115) includes three interleaved power converter modules (305). In this example, each interleaved power converter module (305) includes a half-bridge single-phase converter circuit coupled to each phase leg (130a, 130b, 130c) of a (three-phase) AC load (130). Typically, each of the interleaved power converter modules (305) is driven to output an AC signal that is 120 degrees out of phase with respect to the other interleaved power converter modules (305). Each interleaved power converter module (305) can be implemented as one of the switching circuits shown in FIGS. 5a through 5h, which will be described in more detail below, for example.

[0043] Referring to FIGS. 4a and 4b, a control system diagram that can be implemented by power converters, such as a power converter system (100), a power converter (300), a power converter (330) and / or a power converter (360), is shown.

[0044] FIG. 4a illustrates a control system (400) comprising a central controller (150), three local controllers (160a, 160b, 160c) (each being an example of a previously introduced local controller (160)), and interleaved power converter modules (305a, 305b, 305c) (each being an example of a previously introduced interleaved power converter module (305)). The local controllers (160a to 160c) may generally be referred to as the local controller (160) or each local controller (160). The interleaved power converter modules (305a to 305c) may generally be referred to as the interleaved power converter module (305) or each interleaved power converter module (305). When implemented by a power converter (300) (half-bridge, single-phase), the control system (400) may include a local controller (160a) and an interleaved power converter module (305a), while the dashed line components of the control system (local controllers (160b to 160c) and modules (305b to 305c)) may not exist. When implemented by a power converter (330) (full-bridge, single-phase), the control system (400) may include local controllers (160a, 160b) and interleaved power converter modules (305a, 305b), while the remaining dashed line components of the control system (local controller (160c) and modules (305c)) may not exist. When implemented by a power converter (360) (3-phase), the control system (400) may include local controllers (160a, 160b, 160c) and interleaved power converter modules (305a, 305b, 305c).

[0045] The diagram in FIG. 4a illustrates communication between components of the control system (400) during operation (e.g., when a power converter using the control system (400) is operating to convert power). As illustrated, each interleaved power converter module (305) sends sensor data (e.g., Sensor Data) to each local controller (160). abc It provides ). The interleaved power converter module (305) may incorporate one or more of the aforementioned sensors (140) (see FIG. 1) within it. In some examples, the sensor data includes one or more of the inductor current for the LC filter of the module interleaved power converter (305), the capacitor voltage for the capacitor of the LC filter of the interleaved power converter module (305), and / or the output current output by the LC filter of the interleaved power converter module (305). Each local controller (160) also provides the sensor data to the central controller (150). Accordingly, the central controller (150) receives the sensor data for each interleaved power converter module (305) present within the control system (400). The central controller (150) then provides a reference target (e.g., Ref) for each local controller (160). abc Generates ). The reference goal is specified for each local controller (160).

[0046] The central controller (150) may be a PID controller that generates reference target(s) based on received sensor data and total power demand or commands (e.g., received via the I / O interface (142) or memory). In some examples, the central controller (150) converts the sensor data from a fixed reference frame (e.g., abc reference frame) to a rotating reference frame (e.g., a direct-orthogonal (DQ or DQN) reference frame). To perform the conversion, the central controller (150) may use Park and Clarke transformations. The central controller (150) may then generate reference targets for each leg of the rotating reference frame (e.g., a voltage target for D, a voltage target for Q, a voltage target for N (null element)). The reference target can be set based on the detected value (i.e., the value indicated by the sensor data) for the desired value for these characteristics so that the detected value approaches the desired value (e.g., using PID technology). In some examples, the N factor is set to half the DC link voltage to control leakage current within the system. In some embodiments, the central controller also injects a harmonic (e.g., a sine wave or triangular wave voltage signal as harmonic injection) into the N factor (e.g., summed with half the DC link voltage). The harmonic may be the third harmonic of the fundamental frequency of the output AC signal to which the converter is coupled or the AC grid. The central controller (150) can then convert the reference target from the DQN reference frame to a fixed (abc) reference frame using the Park and Clark inverse transformation. The central controller (150) can then output a reference target (Ref) for each local controller (160) present in the system (400) (e.g., Ref to local controllers (160a, 160b, 160c)a , Ref b , Ref c ).

[0047] In some examples, the reference target is a voltage value for the voltage across the capacitor of the LC filter of the interleaved power converter module (305). In other examples, the reference target is another electrical characteristic of the interleaved power converter module (305) (e.g., another voltage target or current target).

[0048] Each local controller (160) receives a corresponding reference target from the central controller (150). Each local controller (160) then generates a control signal to control the corresponding interleaved power converter module (305) based on the received reference target. By generating an appropriate control signal, each local controller (160) can thereby adjust the electrical characteristics of the reference target (e.g., capacitor voltage) to approach the value indicated by the reference target.

[0049] Referring to FIG. 4b, a more detailed diagram (415) of a local controller (160a) and an interleaved power converter module (305a) is provided. This diagram applies similarly to other local controllers (160b, 160c) and interleaved power converter modules (305b, 305c).

[0050] As illustrated, the local controller (160a) includes an electronic processor (165) and a gate driver (410), and the interleaved power converter module (305a) includes a switching circuit (420) and a sensor (430). During operation, the electronic processor (165) receives a reference target (Ref) from the central controller (150). a ) and sensor data (435) from the sensor (430) (Sensor Data a) receives. The sensor data (435) may be as described above for FIG. 4a. From the reference target and the sensor data, the electronic processor (165) determines the duty cycle reference (d a *), phase-shifted duty cycle standard (d shift_a *), and switching frequency (f SW Determines ). Phase-shifted duty cycle reference (d shift_a *) is a duty cycle reference (d) by, for example, directly indicating the amount of phase shift (e.g., as an amount from 0 to 360 degrees) or by becoming a phase-shifted duty cycle reference. a Displays the phase shift amount for *). These values ​​(d a *, d shift_a *, f SW The calculation of ) is explained in more detail below.

[0051] The gate driver (410) is based on the duty cycle (d a *), phase-shifted duty cycle standard (d shift_a *) and switching frequency (f SW It receives ) and generates a variable frequency soft switching (VFSS) control signal (450) and a phase-shifted VFSS control signal (455). The VFSS control signal (450) is a switching frequency (f SW Same frequency and duty cycle reference as ) (d a It may include a first pulse width modulation (PWM) signal having the same duty cycle as *) and a second PWM signal which is the inverse of the first PWM signal. The VFSS control signal (450) has a switching frequency (f SW Same frequency and duty cycle reference as ) (d a A first pulse width modulation (PWM) signal (450a) having the same duty cycle as *) and the reciprocal of the first PWM signal (450a), and accordingly, also the same switching frequency (f SW ) and duty cycle (d a It may include a second PWM signal (450b) having *).

[0052] The phase-shifted VFSS control signal (455) is (i) switching frequency (f SW Same frequency and duty cycle reference as ) (d a It has the same duty cycle as *), but the phase-shifted duty cycle reference (d shift_a A first PWM signal (455a) phase-shifted with respect to the VFSS control signal (450a) by the amount of phase shift indicated by *), and (ii) the reciprocal of the first PWM signal (455a), and accordingly, also the same switching frequency (f SW ) and duty cycle (d a It has *), and also has a phase-shifted duty cycle reference (d shift_a It may include a second PWM signal (455b) that is phase-shifted with respect to the VFSS control signal (450b) by the amount of phase shift indicated by *). Although the inverter gate providing the signals (450b and 455b) is shown outside the gate driver (410) in FIG. 4b, the inverter gate may be inside the gate driver (410).

[0053] As described in more detail below, each of the VFSS control signal (450) and the phase-shifted VFSS control signal (455) controls the switching of each pair of power switching elements of the switching circuit (420) such that each pair of power switching elements is controlled by a PWM signal having a selected switching frequency to achieve soft switching (zero voltage switching) and the outputs of the pair of power switching elements are interleaved. Generally, as illustrated in FIGS. 5a through 5h, each pair of power switching elements is controlled by a first control signal (e.g., PWM or PWM shift A first transistor receiving ) and a first control signal (e.g., inverted PWM or inverted PWM shiftIt includes a second transistor that receives the reciprocal of ). Accordingly, during operation, when the first transistor of the pair is enabled (ON), the second transistor of the pair is disabled (OFF), and vice versa. The terms power switching element and transistor are used interchangeably herein. In some examples, the transistor may be a type of field effect transistor (FET), such as, for example, a metal oxide semiconductor (MOS) field effect transistor (FET), a silicon carbide (SiC) FET, or a gallium nitride transistor (GaN) FET.

[0054] FIGS. 5a through 5h illustrate examples of switching circuits that can serve as switching circuits (420) in one or more of interleaved power converter modules (305) that may exist within a power converter (e.g., power converter system (100), power converter (300, 330, 360)).

[0055] FIG. 5a illustrates a multi-inductor interleaved converter (500). The converter (500) includes a DC link node (502), a first pair of transistors (504a, 504b) and a second pair of transistors (506a, 506b) coupled between the DC link node (502), an LC filter circuit (508), and AC nodes (510a, 510b). The first pair of transistors includes a first upper transistor (504a) coupled to a first lower transistor (504b) through a first midpoint node (512). The second pair of transistors includes a second upper transistor (506a) coupled to a second lower transistor (506b) through a second midpoint node (514). The LC filter (508) includes a first inductor (516a) coupled between the first midpoint node (512) and the output node (510a) of the AC node, and a second inductor (516b) coupled between the second midpoint node (514) and the output node (510a) of the AC node. The LC filter (508) further includes an upper capacitor (518a) coupled between the output node (510a) and the positive DC node (502), and a lower capacitor (518b) coupled between the output node (510a) and the negative DC node (502).

[0056] Since the inductors (516a, 516b) are connected in parallel to the output node (510a), the two inductors (i L1 , i L2 The current from ) is summed at the output node (510a). When the two transistor pairs operate 180 degrees out of phase, the triangle inductor current is also 180 degrees out of phase. The two inductor currents (i L1 , i L2When ) are added together at the output node (510a), one peak aligns with another low point, causing cancellation of the ripple current (while the average is not affected by this cancellation). This results in a lower current ripple size that is filtered by the output capacitors (518a, 518b), allowing the capacitors to be smaller.

[0057] An additional effect is frequency doubling. Two currents (i L1 and i L2 The fundamental frequency of the sum of the ) is twice the fundamental frequency of each individual current (or n times for n interleaved inductors). The ripple reduction provided by the output filter capacitors (518a, 518b) increases with the frequency of the filtered current. Accordingly, the frequency doubling effect allows for a further reduction in the filter size.

[0058] FIG. 6a provides a diagram of these effects. Two inductor currents (i1, i2) (inductor current (i L1 , i L2 (corresponding to ) is illustrated and has a 180° phase shift. In this example, each inductor has an average current of 0.5 A and is illustrated by a dashed line. The sum of two currents (i1 + i2) proceeding to the output filter capacitor and having an average of 1.0 A is also illustrated. The average of 1.0 A is the individual inductor current (i L1 , i L2 It is the sum of the averages of ). However, the peak-to-peak ripple for the summed current was reduced from 1 A to approximately 0.4 A in this example. Furthermore, the summed current has a frequency that is twice the frequency of the individual currents.

[0059] By using interleaving, the soft-switching operating region for an inverter having interleaving is extended, increasing the current and voltage, and the resulting peak power that can be obtained by the converter. Referring to FIG. 6b, a plot is provided showing the soft-switching operating region defined by the curve (605) for an inverter having interleaving (e.g., the converter (500) of FIG. 5a), and a constant power curve (610) for the peak power of the inverter. In this example, the use of interleaving pushes the top-right corner of the boundary to the right (as indicated by the arrow), causing the power demand indicated by the power curve (610) to exceed. In this example, in a converter (500) having soft switching, a 640 V battery (as a DC source coupled to the DC node (502)), and third harmonic injection into the generation of a null sequence target reference by a central controller (150), a 240 kW power curve (610) overlaps with the switching boundary curve (605) and thus is achievable by the power converter.

[0060] To implement variable frequency soft switching, a control system (105) (e.g., an electronic processor (165)) can determine the switching frequency to achieve soft switching using the following equation:

[0061]

[0062] Here, I L,thr is the boundary threshold current for soft switching that can be induced with a given dead time (Td), and I L is the switching side inductor current, where d is the reference duty cycle (a value between 0 and 1).

[0063] Referring to FIG. 5b, a coupled inductor interleaved converter (520) is illustrated. The converter (520) of FIG. 5b has several components similar to the converter (500) of FIG. 5a, which is similarly given the reference numeral. In contrast to the converter (500), the converter (520) includes an LC filter (522) comprising a coupled inductor (524), an upper capacitor (518a), and a lower capacitor (518b). The coupled inductor (524) includes windings (524a, 524b) wound on a single magnetic core. The coupled inductor (524) is provided by a transformer (coupling transformer) having a winding ratio of 1:-1. The coupled inductor (524) is coupled between a first midpoint node (512), a second midpoint node (514), and an output node (510a).

[0064] Similar to the converter (500), in the converter (520), the first and second pairs of transistors (504, 506) can be driven by a PWM signal and a phase-shifted PWM signal (e.g., 180 degrees out of phase with respect to each other), respectively. Similar to the multi-inductor interleaved converter (500), the coupled inductor interleaved converter (520) provides an interleaved output with double the frequency and reduced current ripple, allowing for benefits similar to those mentioned above for the converter (500). Accordingly, the diagrams of FIGS. 6a and 6b are applied similarly. Furthermore, the core of the coupled inductor (524) of the LC filter (522) sees an interleaved output of a higher frequency. This result is in contrast to the converter (500) of FIG. 5a, where each inductor sees a (lower) base switching frequency. Accordingly, compared to the inductors (516a, 516b) of the LC filter (508) of the converter (500), the coupling inductor (524) of the LC filter (522) of the converter (520) may have a reduced size.

[0065] In some examples, individual discrete inductors (not shown) are provided between the coupling inductor (524) and each midpoint (512, 514). In some examples, the leakage inductance of the coupling inductor (524) on these connections to each midpoint (512, 514) performs a similar function to create a single magnetic structure.

[0066] In this topology, the switching frequency (f SW A new equation for inductor ripple has been discovered that includes both ) and the normalized phase shift (φ) varying from 0 to 1. For the case where duty cycle D > 0.5 and phase shift (φ) < 0.5:

[0067]

[0068] For the set of four equations covering all cases, similar equations are found when D < 0.5 and / or φ > 0.5. For simplification, this equation is written in terms of a duty cycle (D) varying between 0 and 1. In the steady state, V out - DV in is. Ripple(Δi L ) is zero when φ = D. Therefore, if φ is fixed at 0.5 (or 180°), the ripple will go to zero when D passes 0.5. This means that both the switching frequency and phase are adjusted by the controller (e.g., by the local controller (160) controlling the converter (520)) to ensure sufficient ripple across all operating points.

[0069] This equation can then be solved for either the switching frequency or the phase to show how each of them affects the ripple.

[0070]

[0071]

[0072] One possible such control scheme is to set φ = 0.5 and f for all conditions where sufficient ripple is achievable. SW It is to control. When the required switching frequency drops below the minimum value, then f SW is f min It is fixed to and φ is controlled instead. In experimental tests, this technique was applied to a simulation and was found to work, and the results are shown in the inductor current plot (700), phase current plot (705), and frequency plot (710) of FIG. 7. More specifically, the frequency plot (710) shows the calculated required switching frequency for soft switching as the curve (715) and the selected actual frequency as the step line (720). This simulation uses frequencies that are integer multiples of 50 kHz, but in other examples, the frequency is not limited in this way. In this example, the minimum switching frequency is 100 kHz. Desired frequency (f SW When ) falls below the minimum value (see plot (710)), the phase (φ) is adjusted to maintain the desired ripple (see plot (705)) (see plot (700)). The ripple envelope (722) for the inductor current is shown in plot (700), the average current is shown as a sinusoidal signal (725), and the ripple inverse boundaries (730, 735) are shown as straight lines slightly offset from the x-axis. Boundary (730) is below the x-axis when the average current is positive, and boundary (735) is above the x-axis when the average current is negative. In some examples, other control schemes, such as controlling the phase until the minimum value is reached and then controlling the frequency, provide sufficient ripple (Δi L To maintain ), phase (φ) and switching frequency (f SW It is used to control ).

[0073] In some examples, the phase (φ) is generally static during operation rather than being dynamically controlled. For example, a control scheme can set the phase (φ) = 0.5 and f to achieve sufficient ripple for soft switching. SW It can be controlled. Additionally, the inductance of the coupled inductor (524) can be intentionally designed to have characteristics that enable sufficient ripple and thus soft switching even at low switching frequencies. For example, FIG. 9 illustrates a model (900) of a coupled inductor interleaved converter (520) that can be used to select the characteristics of the coupled inductor (524) that enable sufficient ripple. In the model (900), the coupled inductor (524) has an ideal inductance (L), a magnetization inductance (L m ), and leakage inductance (L lk It is modeled as having ), where the ideal inductance (L) is equal to the inductance (L1) of the winding (524a) of the coupled inductor, and is equal to the inductance (L2) of the winding (524b) of the coupled inductor. The relationship between these inductances can be defined by the following equation:

[0074]

[0075]

[0076] Here, k is a coupling factor of the coupling inductor (524) that can be a value less than 0.

[0077] As mentioned, the model (900) can be used to select characteristics of a coupled inductor (524) that enable sufficient ripple to achieve soft switching even at low switching frequencies. For example, to select characteristics, leakage inductance and magnetization inductance may be selected, and then the above equation may be used to derive an inductance (L) equal to the inductance of the windings (524a, 524b) of the coupled inductor (524). leakage inductance (L lk) can be selected to deliver maximum AC current at the minimum (and maximum) duty cycle, minimum DC voltage, and minimum switching frequency. In addition, the magnetizing inductance (L m ) can be selected to deliver a maximum AC current, a minimum DC voltage, and a minimum switching frequency ≥ 0.5 at a duty cycle of 0.5. For example, the following equation is the leakage inductance (L lk ) and magnetizing inductance (L m It can be used to calculate ):

[0078]

[0079]

[0080] When the desired switching frequency drops below the minimum allowable frequency, the current ripple due to leakage inductance may be too small for soft switching to occur. However, while the ripple current at these low switching frequencies approaches zero, the ripple within the magnetizing inductance is at its maximum value. Therefore, by selecting the magnetizing inductance to be small enough to allow for a sufficient ripple amplitude with a minimum bus voltage at low switching frequencies, the converter will be soft-switched through zero crossing.

[0081] In this example, the switching frequency can be calculated using the following equation (e.g., by the local controller (160)):

[0082]

[0083] The variable m represents the inductor current slope, and the equation to solve for m can take three different forms depending on the state of the switch. More specifically, the inductor current slope (m i ) can take three forms corresponding to the top switch (i=1), diagonal switch (i=2), and bottom switch (i=3) being turned on.

[0084]

[0085]

[0086]

[0087] As mentioned above, the multi-inductor interleaved converter (500) and the coupled inductor interleaved converter (520) can increase the power density of these power converters by enabling a reduction in the size of the inductors and capacitors of the LC filters of these converters. The results of experiments with exemplary embodiments of these converters (500, 520) shown in Table 1 below demonstrate this size reduction. More specifically, Table 1 shows parameters for an example of a multi-inductor interleaved converter (500) ("interleaved"), an example of a coupled inductor interleaved converter (520) ("coupled inductor"), and an example of a non-interleaved, non-coupled inductor converter including a parallel inductor coupled between a power switching element and an output node. In these examples, a maximum switching frequency of 500 kHz is assigned, the selectable switching frequency is limited to a 50 kHz bin, the converter is designed to provide 80 kW of three-phase power with 128 Amps per phase and a 700 V DC input, and the output capacitance is selected for the same worst-case output voltage ripple. Although not shown in the table, the inductance (L) is reduced for the interleaved converter compared to the parallel inverter, and further reduced for the coupled inductor converter (4.5 times smaller than the parallel converter).

[0088]

[0089] Referring to FIG. 5c, a flying capacitor multilevel interleaved converter (530) is illustrated. The converter (530) of FIG. 5c has several components similar to the converter (500) of FIG. 5a, which is similarly referenced. In contrast to the converter (500), the converter (530) includes an LC filter (532) comprising an inductor (534), an upper capacitor (518a), and a lower capacitor (518b). Additionally, the first pair of transistors (504a, 504b) and the second pair of transistors (506a, 506b) are interconnected differently within the circuit. More specifically, the first transistor pair (504a, 504b) is an internal pair connected at the midpoint node (536), and the second transistor pair (506a, 506b) is an output pair coupled between the DC link node (502) and the first (internal) transistor pair (504a, 504b). For example, the upper transistor (506a) is coupled between the (positive) DC link node (502) and the upper transistor (504a), and the lower transistor (506b) is coupled between the (negative) DC link node (502) and the lower transistor (504b). Additionally, the converter (530) includes a flying capacitor (538) coupled across the first (internal) transistor pair (504a, 504b) at (i) the connection node (539a) of the upper transistor (504a) and the upper transistor (506a), and (ii) the connection node (539b) of the lower transistor (504b) and the lower transistor (506b). The inductor (534) of the LC filter is coupled between the first midpoint node (536) and the output node (510a).

[0090] Similar to the converter (500), in the converter (520), the first and second transistor pairs (504, 506) can be driven by a PWM signal and a phase-shifted PWM signal (e.g., 180 degrees out of phase with respect to each other), respectively. Similar to the multi-inductor interleaved converter (500), the flying capacitor multilevel interleaved converter (530) provides an interleaved output with double the frequency and reduced current ripple, allowing for benefits similar to those mentioned above for the converter (500). Accordingly, the diagrams of FIGS. 6a and 6b are applied similarly. Furthermore, the inductor (534) of the LC filter (532) sees an interleaved output of a higher frequency. This result is in contrast to the converter (500) of FIG. 5a, where each inductor sees a (lower) base switching frequency. Accordingly, the coupling inductor (534) of the LC filter (532) of the converter (530) may have a reduced size compared to the inductor (516a, 516b) of the LC filter (508) of the converter (500). Additionally, connecting the upper transistors (504a, 506a) in series enables the sharing of voltage across these transistors, thereby enabling a reduction in the transistor size and / or voltage rating for the transistors of the converter (500, 520). A similar benefit can be achieved by connecting the lower transistors (504b, 506b) in series.

[0091] Referring to FIG. 5d, a neutral-point connected multilevel interleaved converter (540) is illustrated. The converter (540) of FIG. 5d has several components similar to the converter (530) of FIG. 5c, which is similarly given a reference numeral. In contrast to the converter (530), the converter (540) includes a neutral-point connection (542) between the upper and lower capacitors and the DC link node (502). Additionally, instead of a flying capacitor, diodes (544a, 544b) are connected between the connection nodes (539a, 539b), where the neutral-point connection (542) is an intermediate node between the diodes (544a, 544b).

[0092] Similar to the multi-inductor interleaved converter (500), the neutral-point connected multi-level interleaved converter (540) provides an interleaved output with twice the frequency and reduced current ripple, allowing for benefits similar to those mentioned above for the converter (500). Accordingly, the diagrams of FIGS. 6a and 6b are similarly applied. Furthermore, the inductor (534) of the LC filter (532) sees an interleaved output of a higher frequency. This result is in contrast to the converter (500) of FIG. 5a, where each inductor sees a (lower) base switching frequency. Accordingly, compared to the inductors (516a, 516b) of the LC filter (508) of the converter (500), the coupled inductor (534) of the LC filter (532) of the converter (540) can have a reduced size. Additionally, connecting the upper transistors (504a, 506a) in series, such as in the converter (530), enables the sharing of voltage across these transistors, thereby enabling a reduction in the transistor size and / or voltage rating for the transistors of the converter (500, 520). A similar benefit can be achieved by connecting the lower transistors (504b, 506b) in series.

[0093] In some examples, the interleaved converter (500, 520, 530, and / or 540) is modified to include additional pairs of transistors (or levels), either horizontally or vertically. For example, for the converter (500), two pairs of transistors are shown, and each pair is typically driven 180 degrees out of phase with respect to the other pair. In some examples, the converter (500) of FIG. 5a includes one or more additional levels, for example, a third pair of transistors, a fourth pair of transistors, etc., where each pair of transistors includes a midpoint node coupled across a DC node (502) (similar to transistor pairs (504, 506)) and coupled to an output node (510a) through individual inductors. In these examples, each pair of transistors can receive a PWM control signal that is phase-shifted relative to the other pair of transistors. The phase shift between pairs of transistors can be set to 360 degrees per pair (e.g., 360 / 2 pairs = 180 degrees; 360 / 3 pairs = 120 degrees; 360 / 4 pairs = 90 degrees, etc.). This example can be referred to as adding pairs of transistors horizontally.

[0094] Similarly, for the converter (520), two pairs of transistors are illustrated, and each pair is typically driven 180 degrees out of phase with respect to the other pair. In some examples, the converter (520) of FIG. 5b includes one or more additional levels, e.g., a third pair of transistors, a fourth pair of transistors, etc., where each pair of transistors includes a midpoint node coupled across a DC node (502) (similar to transistor pairs (504, 506)) and coupled to an output node (510a) through the winding of a coupling inductor (524). In these examples, each pair of transistors can receive a PWM control signal that is phase-shifted relative to the other pair of transistors. The phase shift between pairs of transistors can be set to a number of 360 degrees per pair (e.g., 360 / 2 pairs = 180 degrees; 360 / 3 pairs = 120 degrees; 360 / 4 pairs = 90 degrees, etc.). This example can also be referred to as adding a pair of transistors horizontally.

[0095] For the converter (530), two pairs of transistors are shown, and each pair is typically driven 180 degrees out of phase with respect to the other pair. In some examples, the converter (530) of FIG. 5c includes one or more additional levels, e.g., a third pair of transistors, a fourth pair of transistors, etc., where each pair of transistors is combined as an additional output pair for the existing pairs and an additional flying capacitor is provided across each internal pair of transistors. For example, when a third pair of transistors is added to the converter (530), the upper transistors of the third pair are combined between transistor (506a) and the (positive) DC link node (502), and the lower transistors of the third pair are combined between transistor (506b) and the (negative) DC link node (502). Additionally, in this example, another flying capacitor is coupled across the transistors (506a, 506b) (in a manner similar to how the flying capacitor (538) is coupled across the transistors (504a, 504b)). In this example, each pair of transistors of the converter (530) can receive a PWM control signal that is phase-shifted relative to the other pair of transistors. The phase shift between pairs of transistors can be set to 360 degrees per pair (e.g., 360 / 2 pairs = 180 degrees; 360 / 3 pairs = 120 degrees; 360 / 4 pairs = 90 degrees, etc.). This example may be referred to as adding pairs of transistors vertically.

[0096] For the converter (540), two pairs of transistors are shown, and each pair is typically driven 180 degrees out of phase with respect to the other pair. In some examples, the converter (540) of FIG. 5d includes one or more additional levels, e.g., a third pair of transistors, a fourth pair of transistors, etc., where each pair of transistors is combined as an additional output pair for the existing pairs and an additional flying capacitor is provided across each internal pair of transistors. For example, when a third pair of transistors is added to the converter (540), the upper transistors of the third pair are combined between transistor (506a) and the (positive) DC link node (502), and the lower transistors of the third pair are combined between transistor (506b) and the (negative) DC link node (502). Additionally, in this example, another set of diodes is coupled across the transistors (506a, 506b) (in a manner similar to how diode (544) is coupled across the transistors (504a, 504b)), where the midpoint of the diode is also coupled to the neutral point (542). In this example, each pair of transistors of the converter (540) can receive a PWM control signal that is phase-shifted relative to the other pair of transistors. The phase shift between pairs of transistors can be set to 360 degrees per pair (e.g., 360 / 2 pairs = 180 degrees; 360 / 3 pairs = 120 degrees; 360 / 4 pairs = 90 degrees, etc.). This example may also be referred to as adding pairs of transistors vertically.

[0097] Referring to FIGS. 5e through 5h, a hybrid topology combining the features of the converter topologies described in FIGS. 5a through 5d is illustrated. Starting with FIG. 5e, a flying capacitor multilevel, multi-inductor interleaved converter (550), which is a hybrid of converters (500, 530), is illustrated. FIG. 5f, a neutral-point connected multilevel, multi-inductor interleaved converter (560), which is a hybrid of converters (500, 540), is illustrated. FIG. 5g, a flying capacitor multilevel, coupled inductor interleaved converter (570), which is a hybrid of converters (520, 530), is illustrated. FIG. 5h, a neutral-point multilevel, coupled inductor interleaved converter (580), which is a hybrid of converters (520, 540), is illustrated.

[0098] In the topology of FIGS. 5e through 5h, the hybrid converters (550 through 580) have four pairs of transistors, rather than two pairs of transistors as shown in FIGS. 5a through 5d. By this grouping, as illustrated, the first pair of transistors receives a PWM signal (which may be a VFSS control signal (450), see FIG. 4b), and the second pair of transistors receives a first phase-shifted PWM signal (PWM shift_1 ) receives, and the third transistor pair receives the second phase-shifted PWM signal (PWM shift_2 ) receives, and the fourth transistor pair receives the third phase-shifted PWM signal (PWM shift_3 Receives ). PWM of FIGS. 5e to 5h, PWM shift_1 , PWM shift_2 , and PWM shift_3The signals are generally similar to those described for FIGS. 4a, 4b, and FIGS. 5a through 5d; more specifically, each pair of transistors driven by one of these signals comprises a first transistor receiving a signal (e.g., a non-inverting PWM signal) and a second transistor receiving the inverse of that signal (e.g., an inverting PWM signal). Additionally, the phase shift between each PWM signal can be set to a value obtained by dividing 360 degrees by the number of transistor pairs (e.g., 90 degrees in the examples of FIGS. 5e through 5h). For example, the PWM signal may have a phase of 0 degrees, and the PWM shift_1 The signal can be phase-shifted 90 degrees with respect to the PWM signal, and the PWM shift_2 The signal is PWM shift_1 The signal can be phase-shifted by an additional 90 degrees (e.g., 180 degrees phase-shifted for a PWM signal), and the PWM shift_3 is PWM shift_2 The signal can be phase-shifted by an additional 90 degrees (e.g., 270 degrees for a PWM signal). By increasing the number of transistor pairs and signal phases to 4, the output frequency can be four times the fundamental frequency and provide additional cancellation of ripple current. Various phase-shifted VFSS control signals (e.g., PWM shift_1 , PWM shift_2 , PWM shift_3 As described above, it has different phase shifts, but can be generated by a local controller (160a) (e.g., by a gate driver (410)) similar to a phase-shifted VFSS control signal (455) (see FIG. 4b).

[0099] FIG. 8 illustrates a method (800) for interleaved power conversion. The method (800) may be implemented by a system (100). For example, the method (800) may be implemented by a system (100) having an interleaved power converter (115) comprising one or more interleaved power converter modules (305) (see FIG. 3a through 3c and FIG. 4a and 4b). In some examples, these interleaved power converter modules (305) include a switching circuit (420) having a converter circuit topology as illustrated and described for one or more of FIG. 5a through 5h. In other examples, the method (800) is implemented by a different power converter system or by a power converter system (100) implementing a different converter circuit topology. In some examples, the system (100) implementing the method (800) may be configured as a control system as illustrated in FIG. 4a and / or FIG. 4b. Additionally, although the blocks of the method (800) are illustrated in a specific order, in some embodiments, one or more of the blocks may be executed in parallel, partially or wholly, in a different order than illustrated in FIG. 8, or bypassed.

[0100] In block (805), the local controller receives a reference target from the central controller, and the central controller generates a reference target based on the sensed characteristics of an interleaved power converter module having a DC link node, a first pair of transistors and a second pair of transistors coupled between the DC link nodes, an LC filter circuit, and an AC node. For example, referring to FIGS. 4a and 4b, the local controller (160a) receives a reference target (Ref from the central controller (150). a) can be received. Here, as described above, the central controller (150) receives sensor data (e.g., Sensor Data) generated by the sensor (430) of the interleaved power converter module (305) and provided through the local controller (160). a , Sensor Data b , and / or Sensor Data c You can create a standard goal based on ).

[0101] In block (810), the local controller generates a variable frequency soft switching (VFSS) control signal to drive a first pair of transistors to output a first AC signal based on a reference target and a detected characteristic. For example, referring to FIG. 4b, the local controller (160a) generates a VFSS control signal (450) and provides the VFSS control signal (450) to an interleaved power converter module (305a). The VFSS control signal (450) may include a first PWM signal (450a) and a second PWM signal (450b). The first PWM signal (450a) is a switching frequency (f SW Same frequency and duty cycle reference as ) (d a It can have the same duty cycle as *). The second PWM signal (450b) is the reciprocal of the first PWM signal (450a), and accordingly also has the same switching frequency (f SW ) and duty cycle (d a It has *). The first PWM signal (450a) can drive the first transistor of the first transistor pair (e.g., transistor (504a)), and the second PWM signal (450b) can drive the second transistor of the first transistor pair (e.g., transistor (504b)).

[0102] The VFSS control signal (450) may be referred to as a variable frequency soft switching control signal because the switching frequencies of the first and second PWM signals (450a, 450b) can change or be altered over time to ensure soft switching by a pair of transistors driven by the PWM signals. For example, as previously described, the switching frequency can be changed. Decreasing the switching frequency allows the current to ramp up and down for a longer period, thereby increasing the ripple, whereas increasing the switching frequency provides less time for the inductor current to ramp up or down, thereby reducing the ripple. This controllability allows the local controller to maintain the desired ripple by crossing the x-axis by a fixed amount (e.g., see FIG. 7 and boundaries (730, 735)) to ensure soft switching of the first pair of transistors. In some examples, the local controller may determine a maximum switching frequency that will still enable soft switching, which is potentially limited by a maximum switching frequency associated with high switching losses. Generally, the duty cycle of a PWM control signal controls the output voltage of a converter, but the phase and frequency do not. Accordingly, the duty cycle can be determined based on the desired voltage conversion ratio to achieve the desired output voltage, whereas the frequency and / or phase can be used to adjust current ripple.

[0103] Referring to FIG. 4b, the electronic processor (165) can determine the switching frequency and duty cycle for the PWM signals (450a, 450b) of the VFSS control signal (450) (e.g., can determine them continuously during operation). As previously mentioned, the first pair of transistors may be part of an interleaved power converter module as illustrated in any of FIG. 5a through 5g. Examples of specific expressions available to the electronic processor (165) for determining the switching frequency and duty cycle for the VFSS control signal (450) are provided above for the description of the coupled inductor interleaved converter (520) of FIG. 5b. In some examples, the electronic processor (165) using the aforementioned technique determines the switching frequency for the VFSS control signal (450) with the aim of minimizing switching losses, so that the control technique may be referred to as critical variable frequency soft switching.

[0104] In block (815), the local controller generates a phase-shifted VFSS control signal to drive a second pair of transistors to output a second AC signal that is phase-shifted relative to the first AC signal, based on a reference target and a detected characteristic. For example, referring to FIG. 4b, the local controller (160a) generates a phase-shifted VFSS control signal (455) and provides the phase-shifted VFSS control signal (455) to the interleaved power converter module (305a). The phase-shifted VFSS control signal (455) is a first phase-shifted PWM signal (PWM shift )(455a) and second phase-shifted PWM (PWM shift It may include a ) signal (455b). The first PWM shift The signal (455a) is the switching frequency (f SW Same frequency and duty cycle reference as ) (d a It can have the same duty cycle as *). 2nd PWM shiftThe signal (455b) is the first PWM shift It is the reciprocal of the signal (455a), and accordingly also the same switching frequency (f SW ) and duty cycle (d a It has *). The first PWM shift The signal (455a) can drive the first transistor (e.g., transistor (506a)) of the second transistor pair, and the second PWM shift The signal (455b) can drive the second transistor of the second transistor pair (e.g., transistor (506b)). Additionally, the VFSS control signal (450) and the phase-shifted VFSS control signal (455) have the same switching frequency (f SW ) and duty cycle (d a Can have *)

[0105] The phase-shifted VFSS control signal (455) is the first and second PWM shift The switching frequency of signals (455a, 455b) is PWM shift A variable frequency soft switching control signal may be referred to as such because it can change or be modified over time to ensure soft switching by a pair of transistors driven by the signal. For example, as previously described, the switching frequency can be changed to ensure soft switching without excessive switching loss. Referring to FIG. 4b, the electronic processor (165) [describes] the PWM of the phase-shifted VFSS control signal (450). shift The switching frequency and duty cycle for the signals (455a, 455b) can be determined (e.g., continuously during operation). Additionally, in some examples, the phase shift (α) (d shift_a(Indicated by *) can be varied to ensure soft switching by the first and second pair of transistors. In some examples, the phase shift can be set, at least initially, to a value of 360 divided by the number of levels of the interleaved power converter module (e.g., 180 degrees for the converter (500) as shown in FIG. 5a and the converter (520) as shown in FIG. 5b, and 90 degrees for the converters (550, 560, 570, 580) in FIG. 5e through 5h). During operation, the phase shift can be varied from this initial setting, for example, in converters including a coupled inductor (e.g., see FIG. 5b), and as illustrated in plot (705) of FIG. 7. For example, the phase shift can be reduced as the switching frequency decreases.

[0106] As previously mentioned, the second pair of transistors may be part of an interleaved power converter module as illustrated in any of FIGS. 5a through 5g. Examples of specific expressions available to the electronic processor (165) for determining the switching frequency, duty cycle, and phase shift for the phase-shifted VFSS control signal (455) are provided above for the description of the coupled inductor interleaved converter (520) of FIG. 5b. In some examples, the electronic processor (165) using the aforementioned technique determines the switching frequency for the phase-shifted VFSS control signal (455) with the aim of minimizing switching losses, so that the control technique may be referred to as critical variable frequency soft switching.

[0107] In block (820), the interleaved power converter module outputs an interleaved signal including a first AC signal interleaved with a second AC signal through an LC filter circuit. For example, referring to FIGS. 5a through 5d, the converters (500, 520, 530, 540) output an interleaved signal at the output node (510a) through one of an LC filter (508) (converter (500)), an LC filter (522) (converter (520)), or an LC filter (532) (converter (530) and converter (540)). An example of such an interleaved signal is shown in FIG. 7 as a sinusoidal signal (725) (plot (700)), and an example of a pre-filtered version of the interleaved signal is shown in FIG. 6a (i1+i2). Similarly, referring to FIGS. 5e through 5h, the converters (550, 560, 570, 580) output an interleaved signal at an output node through each LC filter (illustrated but not individually labeled) of each converter (550, 560, 570, 580).

[0108] The method (800) has been described for a single local controller and interleaved power converter module; however, in some examples, a system (100) implementing the method (800) includes additional local controllers and interleaved power converter modules. For example, in some examples, the system (100) implementing the method (800) includes two local controllers (160) and two interleaved power converter modules (305) as shown in FIG. 3b and / or FIG. 4a (when local controllers (160a, 160b) and interleaved power converter modules (305a, 305b) are included), or three local controllers (1260) and three interleaved power converter modules (305) as shown in FIG. 3c and / or FIG. 4a (when local controllers (160a, 160b, 160c) and interleaved power converter modules (305a, 305b, 305c) are included). In this example, each local controller executes blocks (805, 810, 815, 820) to ultimately output each interleaved signal through its LC filter (e.g., each local controller operates in parallel with each other or at least partially in parallel).

[0109] Accordingly, in some examples, the method (800) is provided by the second local controller (e.g., local controller (160b), FIG. 4a) from the central controller (150) with the sensed characteristics (e.g., Sensor Data) of the second interleaved power converter module b A second reference objective generated based on ) (e.g., Ref bThe method further includes the step of receiving a second interleaved power converter module, wherein the second interleaved power converter module includes a second DC link node, a third pair of transistors and a fourth pair of transistors coupled between the DC link nodes, a second LC filter circuit, and a second AC node. The method may further include a second local controller that generates a second variable frequency soft switching (VFSS) control signal to drive the third pair of transistors to output a third AC signal based on a second reference target and a detected characteristic (using a technique similar to that described for block (810)), and generates a second phase-shifted VFSS control signal to drive the fourth pair of transistors to output a fourth AC signal phase-shifted with respect to the third AC signal based on a second reference target and a detected characteristic (using a technique similar to that described for block (815). Additionally, the method may include a second interleaved power converter module (e.g., module (305b)) that outputs a second interleaved signal including a third AC signal interleaved with a fourth AC signal through an LC filter circuit.

[0110] In some additional examples, the method (800) is provided by the central controller (150) to the third local controller (e.g., local controller (160c), FIG. 4a) to detect the characteristics of the third interleaved power converter module (e.g., Sensor Data). c A third criterion objective generated based on ) (e.g., Ref cThe method further includes the step of receiving a third interleaved power converter module, and the third interleaved power converter module includes a third DC link node, a fifth pair of transistors and a sixth pair of transistors coupled between the third DC link node, a third LC filter circuit, and a third AC node. The method may further include a third local controller that generates a third variable frequency soft switching (VFSS) control signal to drive the fifth pair of transistors to output a fifth AC signal based on a third reference target and a detected characteristic (using a technique similar to that described for block (810)), and generates a third phase-shifted VFSS control signal to drive the sixth pair of transistors to output a sixth AC signal phase-shifted with respect to the fifth AC signal based on a third reference target and a detected characteristic (using a technique similar to that described for block (815). Additionally, the method (800) may include a third interleaved power converter module (e.g., module (305b)) that outputs a third interleaved signal including a fifth AC signal interleaved with a sixth AC signal through a third LC filter circuit.

[0111] In some examples, the interleaved power converter system (100) optionally implements interleaving. For example, a control system (105) may determine whether to control the interleaved power converter (115) to implement interleaving based on the operating characteristics of the system (100). For example, the control system (105) (e.g., a central controller (150) or local controller(s) (160)) may determine whether the power converter system (100) has one or more power characteristics (e.g., output voltage, current, and / or power) that are above each threshold(s). When one or more of the power characteristics are above each threshold(s), the control system (105) decides to implement interleaving. When one or more of the power characteristics are below each threshold(s), the control system (105) decides not to implement interleaving.

[0112] In response to a decision to implement interleaving, the control system (105) may control the system (100) to implement interleaving by operating as described herein (e.g., by executing the method of FIG. 8). In response to a decision not to implement interleaving, the control system (105) may control the system to output non-interleaved signal(s) (e.g., from each power converter module (305) of the interleaved power converter (115). For example, each topology of FIG. 5a through 5h includes at least two pairs of transistors described as capable of being controlled to output interleaved signals. To output a non-interleaved signal, the control system (105) (e.g., local controller (160) for each converter module (305)) controls one pair of transistors as described above (e.g., supplying PWM control signals (450a, 450b)) and controls the other pair of transistors (e.g., PWM shiftBy keeping the control signal (455a, 455b)) at zero, switching of other transistor pairs can be prevented.

[0113] By selectively disabling interleaving (e.g., when soft switching can be obtained without interleaving or low current, voltage, or power conditions), the power converter system (100) can reduce switching losses by not switching a specific transistor (e.g., a transistor that would otherwise be controlled via a phase-shifted PWM control signal). By selectively enabling interleaving, the power converter system (100) can achieve an additional voltage margin compared to non-interleaving operation and non-interleaving design. Additionally, by having the ability to selectively enable interleaving, the inductor and capacitor size settings of the LC filter can be reduced compared to a non-interleaving design. In some examples, the transition between interleaving and non-interleaving operations (and vice versa) may involve a transition phase that smoothly transitions between them (e.g., ramping down (or up) the switching frequency and / or duty cycle at which the transistor pair(s) turn off (or on) rather than rapidly disabling (or enabling) the transistor pair(s) from turning off (or on).

[0114] In some examples, the interleaved power converter system (100) may optionally operate in additional conversion modes. For example, in some examples, the power converter system (100) may optionally be controlled to be selected and operated in one of the following modes: parallel (non-interleaved), cascade (non-interleaved), parallel-interleaved, and cascade-interleaved. The aforementioned modes include parallel (non-interleaved) and parallel (interleaved). In a parallel non-interleaved mode, each converter module (305) present in the power converter system (100) operates in a non-interleaved manner. For example, referring to FIG. 3c, each interleaved power converter module (305) is controlled to operate in a non-interleaved manner. In this example, referring to the topology of FIG. 5a through 5h, the first pair of transistors is operated with a PWM control signal, while the other pair of transistors is disabled. In a parallel interleaved mode, each converter module (305) present within the power converter system (100) operates in an interleaved manner. For example, referring to FIG. 3c, each interleaved power converter module (305) is controlled to operate in an interleaved manner. In this example, referring to the topology of FIG. 5a through 5h, the first pair of transistors may be operated by a PWM control signal, and each other pair of transistors may be operated by a respective phase-shifted PWM control signal (for example, as described for the method (800) of FIG. 8).

[0115] In a cascade-interleaved mode, converter modules (305) may be optionally enabled and disabled (e.g., based on power demand). Each converter module (305) present in and enabled within the power converter system (100) operates in an interleaved manner (e.g., as described herein for the method (800) of FIG. 8). The number of enabled converter modules (305) may be controlled based on power demand in the system. For example, if low power demand exists, one or more converter modules (305) may be disabled. By disabling them, the converter system may have higher efficiency resulting from the fact that some converter modules are not actively switched and the enabled converter modules (305) operate closer to their capacity. If power demand increases, the disabled converter modules (305) may be brought online and enabled to meet the demand. Such cascading of converter modules can lead to a more efficient power converter system.

[0116] In cascade (non-interleaved) mode, converter modules (305) can again be selectively enabled and disabled (e.g., based on power demand). Each converter module (305) present in and enabled within the power converter system (100) operates in a non-interleaved manner. The number of enabled converter modules (305) can be controlled based on the power demand in the system. For example, if there is low power demand, one or more converter modules (305) may be disabled. By disabling them, the converter system may have higher efficiency resulting from the fact that some converter modules are not actively switched and the enabled converter modules (305) operate closer to their capacity. If power demand increases, the disabled converter modules (305) can be brought online and enabled to meet the demand. This cascading of converter modules can result in a more efficient power converter system.

[0117] In some examples, the control system (105) may determine which of the four operating modes to operate based, for example, on power demand. As power demand progresses from low to high, the control system (105) may control the power converter system (100) to transition between the four modes. For example, the control system (105) may control the power converter system to transition from a cascade non-interleaved mode to a cascade interleaved mode (when a first threshold is exceeded), and then, when a second threshold is exceeded, to enable another converter module (305) and transition back to a cascade non-interleaved mode. The control system (105) may continue to cycle back and forth between these cascade modes as the converter modules (305) are enabled until eventually all converter modules (305) are enabled and the control system (105) transitions to a parallel non-interleaved mode (when another threshold is exceeded). Finally, the control system (105) may transition to a parallel interleaved mode to achieve the maximum power output level of the power converter system (when another threshold is exceeded). Similarly, as power demand progresses from high to low, the control system (105) may transition between four modes, for example, from a parallel interleaved mode to a parallel non-interleaved mode (when demand falls below a first threshold), then from a cascade interleaved mode to a cascade interleaved mode (when demand falls below a second threshold), then to a cascade non-interleaved mode (when demand falls below a third threshold), and then cycle between cascade modes as each converter module (305) is disabled (reversal of control as power demand ramps up), ultimately controlling the power converter system (100) to operate in a cascade non-interleaved mode for low-power operation.In another example, the control system (105) switches between these four operating modes according to a different algorithm and / or based on additional or other parameters other than power demand. This switching between operating modes can increase the efficiency of the power converter system (100) across a wide range of power output levels.

[0118] Although described herein primarily as a DC-AC inverter, a power converter system (100) comprising various examples and topologies described with respect to FIGS. 3a through 5h may additionally or alternatively function as an AC-DC rectifier and / or a DC-DC converter. In some examples, the power converter system (100) operates only as an inverter, only as a rectifier, or only as a DC-DC converter. In other examples, the power converter system (100) operates as two or more of an inverter, a rectifier, or a DC-DC converter. In some examples, at various time moments, the power converter system may operate in an inverter mode for converting DC to AC, in a rectifier mode for converting AC to DC, or in a DC converter mode for converting DC from one voltage level to another voltage level. Accordingly, in some examples (e.g., when used in an electric vehicle), the power converter system (100) operates in one or more of the following modes: in an inverter mode for driving a motor with an AC signal generated from a DC signal received from a battery; It can be used in a rectifier mode to implement regenerative braking and converter AC power from a (braking) motor to charge the battery; in a rectifier mode to charge converter AC power from an external source (e.g., grid) to charge the battery; and in an inverter mode to invert DC power from the battery into an AC signal to output to another AC load (e.g., on a local microgrid or utility grid).

[0119] Referring to the method (800) of FIG. 8, in some examples (e.g., after block (820)), and when the power converter system (100) (Fig. 2) is bidirectional, the control system (105) transitions the power converter system (100) to operate in rectifier mode. In this example, the local controller (160) can generate a second variable frequency soft switching (VFSS) control signal to drive a first pair of transistors to convert a first input AC signal received through the LC filter of the converter module (305) into a first DC output on the DC link node of the converter module (305), based on a reference target (Ref) from the central controller (150) and a detected characteristic for the corresponding converter module (305). The local controller (160) may also generate a second phase-shifted VFSS control signal to drive a second pair of transistors to convert a second input AC signal received through an LC filter into a second DC output on a DC link node, based on a reference target and a detected characteristic. The converter module (and thus the power converter system (100)) may then output a DC signal including a first DC output summed with the second DC output through the DC link node.

[0120] Referring to the method (800) of FIG. 8, in some examples (e.g., after block (820)), the control system (105) (Fig. 2) transitions the power converter system (100) to operate in a DC-DC conversion mode. In this example, the local controller (160) generates a second variable frequency soft switching (VFSS) control signal to drive a first pair of transistors to output a first variable signal based on a reference target (Ref) and a detected characteristic for the corresponding converter module (305). The local controller (160) also generates a second phase-shifted VFSS control signal to drive a second pair of transistors to output a second variable signal that is phase-shifted relative to the first variable signal based on the reference target and the detected characteristic. Additionally, the converter module (305) outputs a DC signal containing the first variable signal interleaved with the second variable signal through an LC filter. The capacitors of an LC filter (potentially combined with one or more additional capacitors) can serve to smooth a variable signal to provide a DC output.

[0121] In some examples, the power converter system (100) of FIG. 1 (e.g., control system (105)) includes additional methods and control techniques for implementing soft switching for a given converter module topology, which entails enforcing boundaries of operation within the constraints of a given converter module design. During operation, the control system (105) enforces these constraints using, for example, continuous variable frequency soft switching, variable frequency threshold soft switching, and / or variable frequency discrete soft switching. These control techniques may be deployed as firmware protection in the converter system (100) (e.g., as part of the control system (105)) to provide additional soft switching guarantees for a given converter module design (interleaved or other methods).

[0122] In some examples, the power converter system (100) (e.g., the control system (105)) controls the interleaved power converter (115) without dynamically changing the switching frequency during operation to achieve soft switching. For example, the control system (105) may have or select a predetermined switching frequency for operation that will cause soft switching for most or all potential operating points of the interleaved power converter (115). In such examples, when executing the method (800) of FIG. 8, the control system (105) may generate a soft switching (SS) control signal that drives a first pair of transistors to output a first AC signal (block (810)), and may generate a phase-shifted SS control signal that drives a second pair of transistors to output a second AC signal (block (815)). The control system (105) may perform these modified blocks (810, 815) similarly to those described for other examples, except that it uses a predetermined or static switching frequency.

[0123] FIG. 10 illustrates a local controller (1000) which is an example of a local controller (160). In the drawing, the local controller (1000) acts as a local controller (160a); additional local controllers (1000) may act as local controllers (160b) and local controllers (160c) in a similar manner, respectively.

[0124] Duty cycle (d) from reference target and sensor data aTo generate *), a local controller (1000) (e.g., via an electronic processor (165)) may implement or use Model Predictive Control (MPC) by using a Model Predictive Controller (1005). As used herein, MPC may refer to a control algorithm that predicts input commands or reference values ​​to control the behavior of a system through calculations based on the electrical characteristics of a converter and a dynamic model that depends on or recognizes system dynamics (e.g., implementing or using a dynamic model representing a converter under control). Thus, MPC may refer to other dynamic prediction algorithms (e.g., Linear Quadratic Controller (LQR) control algorithms) as well as Model Predictive Control algorithms (as described in more detail below) in a stricter use of the term as used herein.

[0125] In one example, to implement the MPC algorithm, the model predictive controller (1005) can solve a cost function using control reference goals for electrical characteristics and their phases for each control period. By solving the cost function, the model predictive controller (1005) can obtain control reference goals (Ref a A duty cycle (d) to operate a power switching element to control the power conversion of a corresponding interleaved power converter (305) toward ) a The future stage of *) can be predicted. The model prediction controller (1005) then predicts the duty cycle (d a Based on the first stage of the future stages of *) the duty cycle (d) for that specific interleaved power converter (305) aIt can generate *). Accordingly, in contrast to the PI control algorithm, the MPC algorithm derives an optimal duty cycle by processing state variables and tracking errors linearly with specific coefficients. Since the integration procedure is not required in MPC, the dynamic performance of MPC can be improved compared to PI technology, which has less overshoot and a higher tracking speed. Additionally, because MPC has a higher control bandwidth, the model predictive controller (1005) can provide an active damping term to mitigate (reduce or eliminate) LC or LCL resonances that might otherwise exist within the filter circuit of the controlled interleaved power converter (305).

[0126] In some examples, to implement MPC, the model prediction controller (1005) uses Sensor Data a (For example, inductor current(i L,a ), lower capacitor voltage (v cf,a ), grid current(i g,a ) and standard targets (Ref a )) receives. The model prediction controller (1005) receives the desired duty cycle (d a *) The MPC algorithm can be explicitly executed with a pre-configured piecewise affine function to generate switching modulation. For the digital execution of the MPC algorithm, a general state-space form may be described as described below and may be applied to work with the various embodiments described herein.

[0127]

[0128]

[0129] The standardized matrix format can be expressed as follows.

[0130]

[0131] Here , and am.

[0132] The cost function can consist of two items.

[0133]

[0134] Here, And, Q and R represent the weight matrix for tracking error and the input variable terms within the cost function. In some examples, at The weighting of can be configured to be 100 to 500 times greater than other terms to more accurately track the lower output capacitor voltage reference.

[0135] In another example, the local controller (160a) implements a non-MPC control technique, such as a PID control technique, for example.

[0136] The model prediction controller (1005) also has a duty cycle reference (d) as described above for FIG. 4b. a Phase-shifted duty cycle reference (d) based on *) shift_a ) can be generated. The model prediction controller (1005), as described above with respect to FIG. 4b, gives the duty cycle reference (d) to the gate driver (410a). a *) and phase-shifted duty cycle reference (d shift_a ) can be provided. The model prediction controller (1005) can also provide the duty cycle reference (d) to the frequency generation controller (1010). a The frequency generation controller (1010) can provide a duty cycle reference (d) generated by the model prediction controller (1005). a *) and Sensor Data a Based on switching frequency (f SW ) can be generated or calculated (e.g., using one of the aforementioned switching frequency equations). The frequency generation controller (1010) gives the switching frequency (f) to the gate driver (410a). SWIt can provide ).

[0137] This specification describes one or more electronic controllers (e.g., a central controller (150), local controller(s) (160)). An electronic controller includes one or more processors (e.g., one or more microprocessors) configured to facilitate power conversion (e.g., by controlling switching devices of an interleaved power converter system as described herein, e.g., as described herein) and one or more memory or storage devices. Accordingly, the storage device(s) may include computer program products that, when executed on an electronic controller (which may be a processor-based device as mentioned), cause the processor-based device to perform operations that facilitate the implementation of the procedures and operations described herein. An electronic controller may further include peripheral devices that enable input / output functions. Such peripheral devices may include, for example, a flash drive (e.g., a removable flash drive) or a network connection (e.g., implemented using a USB port and / or a wireless transceiver) to download relevant content to a connected system. These peripheral devices may also be used to download software containing computer instructions that enable the general operation of each system / device. Alternatively and / or additionally, in some embodiments, special-purpose logic circuits, such as a Field Programmable Gate Array (FPGA), an Application-Specific Integrated Circuit (ASIC), a DSP processor, a Graphics Processing Unit (GPU), an Application Processing Unit (APU), a Complex Programmable Logic Device (CPLD), etc., may be used in the implementation of the electronic controller. Other modules that may be included in the electronic controller may include a user interface for providing or receiving input and output data. The electronic controller may include an operating system.

[0138] A computer program (also known as a program, software, software application, or code) comprises machine instructions for a programmable processor and may be implemented in a high-level procedural and / or object-oriented programming language, and / or assembly / machine language. As used herein, the term “machine-readable medium” refers to any non-transient computer program product, device, and / or device (e.g., magnetic disk, optical disk, memory, programmable logic device (PLD)) used to provide machine instructions and / or data to a programmable processor, including a non-transient machine-readable medium that receives machine instructions as machine-readable signals.

[0139] In some embodiments, any suitable computer-readable medium may be used to store instructions for performing the process / operation / procedure described herein. For example, in some embodiments, the computer-readable medium may be transient or non-transient. For example, a non-transient computer-readable medium may include a magnetic medium (such as a hard disk, floppy disk, etc.), an optical medium (such as a compact disk, digital video disc, Blu-ray disc, etc.), a semiconductor medium (such as a flash memory, an electrically programmable read-only memory (EPROM), an electrically erasable programmable read-only memory (EEPROM), etc.), any suitable medium that is not fleeting during transmission or has no semblance of permanence, and / or any suitable type of medium. As another example, a transient computer-readable medium may contain a signal on a network, a wire, a conductor, an optical fiber, a circuit, any suitable medium that is not fleeting during transmission or has no semblance of permanence, and / or any suitable intangible medium.

[0140] Although specific embodiments are disclosed in detail herein, they are provided merely for illustrative purposes and are not intended to limit the scope of the following appended claims. Features of the disclosed embodiments may be combined, rearranged, etc., within the scope of the invention to create more embodiments. Some other aspects, advantages, and modifications are considered to be within the scope of the claims provided below. The presented claims represent at least some of the embodiments and features disclosed herein. Other unclaimed embodiments and features are also considered.

[0141] Additional example

[0142] Example 1: A method, device, and / or non-transient computer-readable medium for storing processor-executable instructions for a power converter system, and includes an interleaved power converter module and a control system for controlling the interleaved power converter module. The interleaved power converter module includes a direct current (DC) link node, a first pair of transistors and a second pair of transistors coupled between the DC link nodes, an LC filter circuit, and an alternating current (AC) node. The control system includes a central controller and a local controller. The central controller is configured to generate a reference target based on the sensed characteristics of the interleaved power converter module. The local controller is configured to: receive the reference target and, based on the reference target and the sensed characteristics, generate a variable frequency soft switching (VFSS) control signal for driving the first pair of transistors to output a first AC signal, and, based on the reference target and the sensed characteristics, generate a phase-shifted VFSS control signal for driving the second pair of transistors to output a second AC signal that is phase-shifted relative to the first AC signal. The interleaved power converter module outputs an interleaved signal including a first AC signal interleaved with a second AC signal through an LC filter circuit.

[0143] Example 2: The method, apparatus, and / or non-transient computer-readable medium of Example 1, for generating a VFSS control signal to drive a first pair of transistors, a local controller is configured to: determine a duty cycle for the VFSS control signal and determine a frequency for the VFSS control signal; and the phase-shifted VFSS control signal has the same duty cycle and frequency as the VFSS control signal.

[0144] Example 3: Any one of the methods, devices, and / or non-transient computer-readable media of Examples 1 and 2, and a local controller is configured to generate a duty cycle for a VFSS control signal using model predictive control.

[0145] Example 4: Any one of the methods, devices, and / or non-transient computer-readable media of Examples 1 to 3, wherein the VFSS control signal comprises a first PWM signal for the upper transistor of the first pair of transistors and a second PWM signal for the lower transistor of the first pair of transistors, and the second PWM signal is the reciprocal of the first PWM signal.

[0146] Example 5: Any one of the methods, devices, and / or non-transient computer-readable media of Examples 1 to 4, wherein the phase shift of the VFSS control signal is set to a value obtained by dividing 360 degrees by the number of levels of the interleaved power converter module.

[0147] Example 6: A method, apparatus, and / or non-transient computer-readable medium of any one of Examples 1 through 5, comprising a second interleaved power converter module including a second DC link node, a third pair of transistors and a fourth pair of transistors coupled between the DC link node, a second LC filter circuit, and a second AC node; and further comprising a second local controller, wherein the second local controller is configured to receive a second reference target from a central controller, generate a second variable frequency soft switching (VFSS) control signal for driving the third pair of transistors to output a third AC signal based on the second reference target, and generate a second phase-shifted VFSS control signal for driving the fourth pair of transistors to output a fourth AC signal phase-shifted with respect to the third AC signal based on the second reference target, and the second interleaved power converter module outputs a second interleaved signal including the third AC signal interleaved with the fourth AC signal through the second LC filter circuit.

[0148] Example 7: The method, apparatus, and / or non-transient computer-readable medium of Example 6, comprising a third interleaved power converter module including a third direct current (DC) link node, a fifth pair of transistors and a sixth pair of transistors coupled between the DC link nodes, a third LC filter circuit, and a third alternating current (AC) node; and further comprising a third local controller, wherein the third local controller is configured to receive a third reference target from a central controller, and based on the third reference target, generate a third variable frequency soft switching (VFSS) control signal for driving a fifth pair of transistors to output a fifth AC signal, and based on the third reference target, generate a third phase-shifted VFSS control signal for driving a sixth pair of transistors to output a sixth AC signal phase-shifted with respect to the fifth AC signal, and the third interleaved power converter module outputs a third interleaved signal including a fifth AC signal interleaved with the sixth AC signal through a third LC filter circuit, and the first, second, and third interleaved signals provide a three-phase AC output.

[0149] Example 8: A method, apparatus, and / or non-transient computer-readable medium of any one of Examples 1 to 7, wherein the first transistor pair comprises a first upper transistor coupled to a first lower transistor through a first midpoint node, the second transistor pair comprises a second upper transistor coupled to a second lower transistor through a second midpoint node, and the LC filter circuit comprises a first inductor coupled between the first midpoint node and the output node of the AC node, and a second inductor coupled between the second midpoint node and the output node of the AC node.

[0150] Example 9: A method, apparatus, and / or non-transient computer-readable medium of any one of Examples 1 to 8, wherein the first pair of transistors comprises a first upper transistor coupled to a first lower transistor through a first midpoint node, the second pair of transistors comprises a second upper transistor coupled to a second lower transistor through a second midpoint node, and the LC filter circuit comprises a coupling inductor coupled between the first midpoint node, the second midpoint node and the output node of the AC node.

[0151] Example 10: A method, apparatus, and / or non-transient computer-readable medium of any one of Examples 1 through 9, wherein the first transistor pair comprises a first upper transistor coupled to a first lower transistor through a first midpoint node, the second transistor pair comprises a second upper transistor coupled to a second lower transistor through a second midpoint node, the first midpoint node is coupled to the second midpoint node by a capacitor, the first lower transistor is coupled to the second upper transistor by a third midpoint node, and the LC filter circuit comprises an inductor coupled between the third midpoint node and the output node of the AC node.

[0152] Example 11: Any one of the methods, apparatus, and / or non-transient computer-readable media of Examples 1 to 10, wherein the interleaved power converter module further comprises a pair of diodes coupled to a neutral point connection, the first pair of transistors comprises a first upper transistor coupled to a first lower transistor through a first connection node, the second pair of transistors comprises a second upper transistor coupled to a second lower transistor through a second connection node, the pair of diodes is connected between the first connection node and the second connection node, the first lower transistor is coupled to the second upper transistor by a midpoint node, and the LC filter circuit comprises an inductor coupled between the midpoint node and the output node of the AC node.

[0153] Example 12: Any one of the methods, devices, and / or non-transient computer-readable media of Examples 1 to 11, and the interleaved power converter module is a hybrid topology comprising a combination of (i) a multi-inductor interleaved converter or a coupled inductor interleaved converter and (ii) a flying capacitor multilevel interleaved converter or a neutral-point connected multilevel interleaved converter.

[0154] Example 13: A method, apparatus, and / or non-transient computer-readable medium of any one of Examples 1 through 12, wherein the interleaved power converter module is bidirectional and, in rectifier mode, the local controller is configured to: generate a second variable frequency soft switching (VFSS) control signal for driving a first pair of transistors to convert a first input AC signal received through an LC filter circuit into a first DC output on a DC link node based on a reference target and a detected characteristic, and to generate a second phase-shifted VFSS control signal for driving a second pair of transistors to convert a second input AC signal received through an LC filter circuit into a second DC output on a DC link node based on a reference target and a detected characteristic, and the interleaved power converter module outputs a DC signal including a first DC output summed with a second DC output through a DC link node.

[0155] Example 14: A method, apparatus, and / or non-transient computer-readable medium of any one of Examples 1 through 13, wherein an interleaved power converter module operates in a DC-DC conversion mode, and a local controller is configured to: generate a second variable frequency soft switching (VFSS) control signal for driving a first pair of transistors to output a first variable signal based on a reference target and a detected characteristic, and to generate a second phase-shifted VFSS control signal for driving a second pair of transistors to output a second variable signal phase-shifted with respect to the first variable signal based on a reference target and a detected characteristic, and the interleaved power converter module outputs a DC signal including a first variable signal interleaved with the second variable signal through an LC filter circuit.

[0156] Example 15: A method, device, and / or non-transient computer-readable medium for storing processor-executable instructions for a power converter system, and includes an interleaved power converter module and a control system for controlling the interleaved power converter module. The interleaved power converter module includes a DC link node on a first side, a first pair of transistors and a second pair of transistors coupled between the DC link nodes, an LC filter circuit, and a second side node on a second side. The control system includes a central controller and a local controller. The central controller is configured to generate a reference target based on the sensed characteristics of the interleaved power converter module. The local controller is configured to: receive the reference target and, based on the reference target and the sensed characteristics, generate a variable frequency soft switching (VFSS) control signal for driving the first pair of transistors to output a first variable signal, and, based on the reference target and the sensed characteristics, generate a phase-shifted VFSS control signal for driving the second pair of transistors to output a second variable signal that is phase-shifted relative to the first variable signal. The interleaved power converter module outputs a DC signal including a first variable signal interleaved with a second variable signal through an LC filter circuit.

[0157] Example 16: A method, device, and / or non-transient computer-readable medium for storing processor-executable instructions for a power converter system, and includes an interleaved power converter module and a control system for controlling the interleaved power converter module. The interleaved power converter module includes a direct current (DC) link node on a first side, a first pair of transistors and a second pair of transistors coupled between the DC link nodes, an LC filter circuit, and a second side node on a second side. The control system includes a central controller and local controllers. The central controller is configured to generate a reference target based on the sensed characteristics of the interleaved power converter module. The local controller is configured to generate a variable frequency soft switching (VFSS) control signal to drive a first pair of transistors to convert a first input AC signal received through an LC filter circuit into a first DC output on a DC link node based on a reference target and a detected characteristic, and to generate a phase-shifted VFSS control signal to drive a second pair of transistors to convert a second input AC signal received through an LC filter circuit into a second DC output on a DC link node based on a reference target and a detected characteristic, and the interleaved power converter module outputs a DC signal including a first DC output summed with a second DC output through the DC link node.

Claims

Claim 1 An interleaved power converter system comprising: a direct current (DC) link node, a first pair of transistors and a second pair of transistors coupled between the DC link nodes, an LC filter circuit, and an alternating current (AC) node; an interleaved power converter module comprising; and a control system for controlling the interleaved power converter module, wherein the control system comprises: A central controller configured to generate a reference target based on the detected characteristics of the interleaved power converter module; and It includes a local controller, and the local controller is: Receive the baseline target, Based on a reference target and a detected characteristic, a variable frequency soft switching (VFSS) control signal is generated to drive a first pair of transistors to output a first AC signal, and An interleaved power converter system configured to generate a phase-shifted VFSS control signal to drive a second pair of transistors to output a second AC signal phase-shifted with respect to a first AC signal based on a reference target and detected characteristics, and the interleaved power converter module outputs an interleaved signal including a first AC signal interleaved with the second AC signal through an LC filter circuit. Claim 2 In claim 1, to generate a VFSS control signal to drive a first pair of transistors, a local controller is configured to determine a duty cycle for the VFSS control signal and a frequency for the VFSS control signal, and the phase-shifted VFSS control signal has the same duty cycle and frequency as the VFSS control signal, an interleaved power converter system. Claim 3 An interleaved power converter system according to paragraph 2, wherein the local controller is configured to generate a duty cycle for a VFSS control signal using model predictive control. Claim 4 An interleaved power converter system according to claim 1, wherein the VFSS control signal includes a first PWM signal for the upper transistor of the first transistor pair and a second PWM signal for the lower transistor of the first transistor pair, and the second PWM signal is the inverse of the first PWM signal. Claim 5 An interleaved power converter system according to claim 1, wherein the phase shift of the VFSS control signal is set to a value obtained by dividing 360 degrees by the number of levels of the interleaved power converter module. Claim 6 In claim 1, a second interleaved power converter module comprising a second DC link node, a third pair of transistors and a fourth pair of transistors coupled between the DC link nodes, a second LC filter circuit, and a second AC node; and further comprising a second local controller, wherein the second local controller: Receive a second reference target from the central controller, and Based on the second reference target, a second VFSS control signal is generated to drive a third transistor pair to output a third AC signal, and An interleaved power converter system configured to generate a second phase-shifted VFSS control signal to drive a fourth transistor pair to output a fourth AC signal phase-shifted with respect to a third AC signal based on a second reference target, and the second interleaved power converter module outputs a second interleaved signal including a third AC signal interleaved with the fourth AC signal through a second LC filter circuit. Claim 7 In claim 6, a third interleaved power converter module comprising a third DC link node, a fifth pair of transistors and a sixth pair of transistors coupled between the DC link nodes, a third LC filter circuit, and a third AC node; and further comprising a third local controller, wherein the third local controller comprises: Receive a third reference target from the central controller, and Based on the third reference target, a third VFSS control signal is generated to drive the fifth transistor pair to output a fifth AC signal, and An interleaved power converter system configured to generate a third phase-shifted VFSS control signal to drive a sixth transistor pair to output a sixth AC signal phase-shifted with respect to a fifth AC signal based on a third reference target, and the third interleaved power converter module outputs a third interleaved signal including a fifth AC signal interleaved with the sixth AC signal through a third LC filter circuit, and the first, second, and third interleaved signals provide a three-phase AC output. Claim 8 An interleaved power converter system according to claim 1, wherein the first transistor pair includes a first upper transistor coupled to a first lower transistor through a first midpoint node, the second transistor pair includes a second upper transistor coupled to a second lower transistor through a second midpoint node, and the LC filter circuit includes a first inductor coupled between the first midpoint node and the output node of the AC node, and a second inductor coupled between the second midpoint node and the output node of the AC node. Claim 9 An interleaved power converter system according to claim 1, wherein the first transistor pair includes a first upper transistor coupled to a first lower transistor through a first midpoint node, the second transistor pair includes a second upper transistor coupled to a second lower transistor through a second midpoint node, and the LC filter circuit includes a coupling inductor coupled between the first midpoint node, the second midpoint node, and the output node of the AC node. Claim 10 An interleaved power converter system according to claim 1, wherein the first transistor pair comprises a first upper transistor coupled to a first lower transistor through a first midpoint node, the second transistor pair comprises a second upper transistor coupled to a second lower transistor through a second midpoint node, the first midpoint node is coupled to the second midpoint node by a capacitor, the first lower transistor is coupled to the second upper transistor by a third midpoint node, and the LC filter circuit comprises an inductor coupled between the third midpoint node and the output node of the AC node. Claim 11 In claim 1, the interleaved power converter module further comprises a pair of diodes coupled at a neutral point connection, the first pair of transistors comprises a first upper transistor coupled to a first lower transistor through a first connection node, the second pair of transistors comprises a second upper transistor coupled to a second lower transistor through a second connection node, the pair of diodes is connected between the first connection node and the second connection node, the first lower transistor is coupled to the second upper transistor by an intermediate point node, and the LC filter circuit comprises an inductor coupled between the intermediate point node and the output node of the AC node, the interleaved power converter system. Claim 12 An interleaved power converter system according to claim 1, wherein the interleaved power converter module is a hybrid topology comprising a combination of (i) a multi-inductor interleaved converter or a coupled inductor interleaved converter and (ii) a flying capacitor multilevel interleaved converter or a neutral point-connected multilevel interleaved converter. Claim 13 In claim 1, the interleaved power converter module is bidirectional, and in rectifier mode, the local controller is configured to: generate a second VFSS control signal to drive a first pair of transistors to convert a first input AC signal received through an LC filter circuit into a first DC output on a DC link node based on a reference target and a detected characteristic, and to generate a second phase-shifted VFSS control signal to drive a second pair of transistors to convert a second input AC signal received through an LC filter circuit into a second DC output on a DC link node based on a reference target and a detected characteristic, and the interleaved power converter module outputs a DC signal including a first DC output summed with a second DC output through a DC link node, an interleaved power converter system. Claim 14 In claim 1, the interleaved power converter module operates in a DC-DC conversion mode, and the local controller is configured to generate a second VFSS control signal to drive a first pair of transistors to output a first variable signal based on a reference target and a detected characteristic, and to generate a second phase-shifted VFSS control signal to drive a second pair of transistors to output a second variable signal phase-shifted with respect to the first variable signal based on a reference target and a detected characteristic, and the interleaved power converter module outputs a DC signal including a first variable signal interleaved with the second variable signal through an LC filter circuit, an interleaved power converter system. Claim 15 An interleaved power conversion method comprising: receiving a reference target generated based on a detected characteristic of an interleaved power converter module from a central controller by a local controller, wherein the interleaved power converter module comprises a direct current (DC) link node, a first transistor pair and a second transistor pair coupled between the DC link nodes, an LC filter circuit, and an alternating current (AC) node; generating a variable frequency soft switching (VFSS) control signal to drive a first transistor pair to output a first AC signal based on the reference target and the detected characteristic; generating a phase-shifted VFSS control signal to drive a second transistor pair to output a second AC signal phase-shifted with respect to the first AC signal based on the reference target and the detected characteristic; and outputting an interleaved signal comprising a first AC signal interleaved with the second AC signal through an LC filter circuit. Claim 16 In claim 15, the step of generating a VFSS control signal to drive a first pair of transistors comprises: a step of determining a duty cycle for the VFSS control signal and a step of determining a frequency for the VFSS control signal, wherein the phase-shifted VFSS control signal has the same duty cycle and frequency as the VFSS control signal. Claim 17 In claim 16, the step of generating a duty cycle for a VFSS control signal includes the step of generating a duty cycle using model predictive control. Claim 18 In claim 15, the method further comprises the step of providing a first PWM signal of a VFSS control signal to the upper transistor of the first transistor pair and a second PWM signal of a VFSS control signal to the lower transistor of the first transistor pair, wherein the second PWM signal is the inverse of the first PWM signal. Claim 19 In paragraph 15, the phase shift of the VFSS control signal is set to a value obtained by dividing 360 degrees by the number of levels of the interleaved power converter module. Claim 20 A method according to claim 15, further comprising the step of receiving a second reference target from a central controller by means of a second local controller, wherein the second reference target is generated by the central controller based on the sensed characteristics of a second interleaved power converter module comprising a second DC link node, a third transistor pair and a fourth transistor pair coupled between the DC link node, a second LC filter circuit, and a second AC node; the step of generating a second VFSS control signal to drive a third transistor pair to output a third AC signal based on the second reference target; the step of generating a second phase-shifted VFSS control signal to drive a fourth transistor pair to output a fourth AC signal phase-shifted with respect to the third AC signal based on the second reference target; and the step of outputting a second interleaved signal comprising a third AC signal interleaved with the fourth AC signal by means of a second interleaved power converter module through a second LC filter circuit. Claim 21 In paragraph 20, the step of receiving a third reference goal from a central controller by a third local controller, wherein the third reference goal is generated by the central controller based on the sensed characteristics of a third interleaved power converter module comprising a third DC link node, a fifth transistor pair and a sixth transistor pair coupled between the DC link nodes, a third LC filter circuit, and a third AC node; the step of generating a third VFSS control signal to drive a fifth transistor pair to output a fifth AC signal based on the third reference goal; and the step of generating a third phase-shifted VFSS control signal to drive a sixth transistor pair to output a sixth AC signal phase-shifted with respect to the fifth AC signal based on the third reference goal. A method further comprising the step of outputting a third interleaved signal including a fifth AC signal interleaved with a sixth AC signal by a third interleaved power converter module through a third LC filter circuit, wherein the first, second, and third interleaved signals provide a three-phase AC output. Claim 22 In claim 15, the first transistor pair comprises a first upper transistor coupled to a first lower transistor through a first midpoint node, the second transistor pair comprises a second upper transistor coupled to a second lower transistor through a second midpoint node, and the LC filter circuit comprises a first inductor coupled between the first midpoint node and the output node of the AC node, and a second inductor coupled between the second midpoint node and the output node of the AC node. Claim 23 In claim 15, the first transistor pair comprises a first upper transistor coupled to a first lower transistor through a first midpoint node, the second transistor pair comprises a second upper transistor coupled to a second lower transistor through a second midpoint node, and the LC filter circuit comprises a coupling inductor coupled between the first midpoint node, the second midpoint node, and the output node of the AC node. Claim 24 In claim 15, the first transistor pair comprises a first upper transistor coupled to a first lower transistor through a first midpoint node, the second transistor pair comprises a second upper transistor coupled to a second lower transistor through a second midpoint node, the first midpoint node is coupled to the second midpoint node by a capacitor, the first lower transistor is coupled to the second upper transistor by a third midpoint node, and the LC filter circuit comprises an inductor coupled between the third midpoint node and the output node of the AC node. Claim 25 In claim 15, the interleaved power converter module further comprises a pair of diodes coupled to a neutral point connection, the first pair of transistors comprises a first upper transistor coupled to a first lower transistor through a first connection node, the second pair of transistors comprises a second upper transistor coupled to a second lower transistor through a second connection node, the pair of diodes is connected between the first connection node and the second connection node, the first lower transistor is coupled to the second upper transistor by an intermediate point node, and the LC filter circuit comprises an inductor coupled between the intermediate point node and the output node of the AC node. Claim 26 In paragraph 15, the method comprises a hybrid topology comprising a combination of (i) a multi-inductor interleaved converter or a coupled inductor interleaved converter and (ii) a flying capacitor multilevel interleaved converter or a neutral-point connected multilevel interleaved converter. Claim 27 In claim 15, the interleaved power converter module is bidirectional, and in rectifier mode, the method further comprises: generating a second VFSS control signal to drive a first pair of transistors to convert a first input AC signal received through an LC filter circuit into a first DC output on a DC link node based on a reference target and a detected characteristic; generating a second phase-shifted VFSS control signal to drive a second pair of transistors to convert a second input AC signal received through an LC filter circuit into a second DC output on a DC link node based on a reference target and a detected characteristic; and outputting a DC signal including a first DC output summed with a second DC output through a DC link node. Claim 28 In claim 15, the interleaved power converter module operates in a DC-DC conversion mode, and the method further comprises: generating a second VFSS control signal to drive a first pair of transistors to output a first variable signal based on a reference target and a detected characteristic; and generating a second phase-shifted VFSS control signal to drive a second pair of transistors to output a second variable signal phase-shifted with respect to the first variable signal based on a reference target and a detected characteristic; and outputting a DC signal including a first variable signal interleaved with the second variable signal through an LC filter circuit.

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