Substrate processing method and substrate processing structure

Abstract

A substrate processing structure according to one aspect of the present invention comprises: a low dielectric thin film formed as an insulator for a metal film formed on a substrate; and an amorphous boron nitride thin film that is adhered to the low dielectric thin film and formed as a diffusion barrier to prevent metal diffusion from the metal film.

Description

Technology Field

[0001] The present invention relates to semiconductor manufacturing, and more specifically, to a substrate processing method and a substrate processing structure. Background Technology

[0002] To manufacture semiconductor devices, various substrate processing steps are performed on a substrate. For example, processes such as loading a substrate into a process chamber, depositing a thin film on the substrate, and etching may be carried out. Recently, as semiconductor devices have become highly integrated, signal transmission delay caused by the wiring structure is becoming important in device performance, in addition to the performance of the transistor itself.

[0003] In this regard, there is a growing demand for improvements to wiring structures. Within the wiring structure, there is a need for the development of substrate processing methods and substrate processing structures utilizing insulating materials to reduce the resistance of metal wiring, as well as to reduce dielectric constant and prevent metal diffusion. Prior art literature

[0004] Korean Patent Publication No. 2004-0022995 The problem to be solved

[0005] The present invention aims to solve various problems, including the aforementioned issues, by providing a substrate processing method and a substrate processing structure using an insulating material for reducing dielectric constant within a wiring structure and preventing metal diffusion.

[0006] However, these tasks are exemplary and do not limit the scope of the invention. means of solving the problem

[0007] A substrate processing method according to one aspect of the present invention is provided to solve the above problem.

[0008] The above substrate processing method comprises the steps of: forming an amorphous boron nitride thin film on a metal film on a substrate; and forming a low dielectric thin film on the amorphous boron nitride thin film.

[0009] In the above substrate processing method, the low dielectric thin film may be a SiOC thin film.

[0010] In the above substrate processing method, the amorphous boron nitride thin film may have a thickness of 120 to 200 Å.

[0011] A substrate processing structure according to another aspect of the present invention is provided to solve the above problem.

[0012] The above substrate processing structure comprises: a substrate; a low dielectric thin film formed as an insulator for a metal film formed on the substrate; and an amorphous boron nitride thin film that is adhered to the low dielectric thin film and formed as a diffusion barrier to prevent metal diffusion from the metal film.

[0013] In the above substrate processing structure, the low dielectric thin film may be a SiOC thin film.

[0014] In the above substrate processing structure, the amorphous boron nitride thin film may have a thickness of 120 to 200 Å.

[0015] In the above substrate processing structure, the low dielectric thin film and the amorphous boron nitride thin film may constitute at least a part of the intermetallic dielectric (IMD) structure. Furthermore, the metal film may include a copper thin film, the copper thin film may form a metal wiring, and may further include a barrier pattern containing tantalum that surrounds the sidewall of the metal wiring between the metal wiring and the low dielectric thin film, and the amorphous boron nitride thin film may be interposed between the first intermetallic dielectric (IMD) structure and the second intermetallic dielectric (IMD) structure. Effects of the invention

[0016] According to some embodiments of the present invention as described above, a substrate processing method and a substrate processing structure using an insulating material for reducing dielectric constant within a wiring structure and preventing metal diffusion can be implemented.

[0017] Of course, the scope of the present invention is not limited by these effects. Brief explanation of the drawing

[0018] FIG. 1 is a schematic cross-sectional view illustrating a substrate processing structure according to a comparative example of the present invention. FIG. 2 is a flowchart illustrating a substrate processing method according to one embodiment of the present invention. FIG. 3 is a schematic cross-sectional view illustrating a substrate processing structure according to one embodiment of the present invention. FIG. 4 is a schematic cross-sectional view illustrating a substrate processing structure according to a modified embodiment of the present invention. Figure 5 shows the nano-scratch evaluation results of a thin film in a substrate treatment structure according to an embodiment and a comparative example of the present invention. Specific details for implementing the invention

[0019] Hereinafter, several preferred embodiments of the present invention will be described in detail with reference to the attached drawings.

[0020] The embodiments of the present invention are provided to more fully explain the invention to those skilled in the art, and the following embodiments may be modified in various different forms, and the scope of the invention is not limited to the following embodiments. Rather, these embodiments are provided to make the disclosure more faithful and complete and to fully convey the spirit of the invention to those skilled in the art. In addition, the thickness or size of each layer in the drawings is exaggerated for convenience and clarity of explanation.

[0021] FIG. 1 is a schematic cross-sectional view illustrating a substrate processing structure according to a comparative example of the present invention.

[0022] Referring to FIG. 1, a substrate processing structure is disclosed comprising a metal film (20) formed on a substrate (10) and a SiOC thin film (50) formed as an insulator for the metal film (20).

[0023] The above substrate processing structure includes a SiCN thin film (30) that is adhered to the SiOC thin film (50) and formed as a diffusion barrier to prevent metal diffusion from the metal film (20). The SiCN thin film (30) is interposed between the metal film (20) and the SiOC thin film (50).

[0024] In order to perform the function of a diffusion barrier to prevent metal diffusion, the thickness of the SiCN thin film (30) must be at least 700 Å, and in this case, the dielectric constant k value is confirmed to be about 5.3.

[0025] In Inter Metal Dielectric (IMD) structures, low dielectric constant characteristics play a crucial role in improving the RC delay problem in semiconductor devices. RC delay is the delay caused by resistance (R) and capacitance (C), and it is one of the major factors limiting circuit speed. High dielectric constant characteristics increase capacitance, thereby increasing RC delay, which slows down the signal transmission speed.

[0026] In particular, when the metal wiring material in an intermetallic insulation (IMD) structure includes copper, a new thin film is introduced that performs the function of a diffusion barrier to prevent copper diffusion while simultaneously having low dielectric constant characteristics, and a substrate processing method and a substrate processing structure are required to ensure sufficient adhesion of the new thin film to other surrounding materials.

[0027] The technical concept of the present invention, which can implement this, is explained below.

[0028] FIG. 2 is a flowchart illustrating a substrate processing method according to one embodiment of the present invention.

[0029] Referring to FIG. 2, a substrate processing method according to one embodiment of the present invention includes the step of forming an amorphous boron nitride thin film on a metal film (S20); and the step of forming a low dielectric thin film on the amorphous boron nitride thin film (S30).

[0030] The above metal film may include, for example, a copper thin film.

[0031] The above amorphous boron nitride thin film and the above low-dielectric thin film can constitute at least a part of the intermetallic insulation structure formed on the metal film.

[0032] The process of forming an amorphous boron nitride thin film may include the step of forming an amorphous boron nitride thin film on a substrate through a substrate processing system that supplies a boron-containing precursor gas into a reaction space within a process chamber using a boron-containing precursor supply device.

[0033] The above substrate processing system may include a chemical vapor deposition (CVD) device or a plasma enhanced chemical vapor deposition (PECVD) device for depositing a thin film on a substrate.

[0034] Boron-containing precursors may include borazine precursors. For example, borazine may refer to an inorganic compound defined by the chemical formula B3H6N3.

[0035] In a substrate processing method according to one embodiment of the present invention, the amorphous boron nitride thin film may have a thickness of 120 to 200 Å.

[0036] The above low-dielectric thin film may be a silicon-oxycarbide (SiOC) thin film. For example, a plasma CVD (Chemical Vapor Deposition) method may be used for the process of forming the SiOC thin film. After performing plasma treatment using oxygen molecules (O2) to activate the substrate surface, a source gas for SiOC deposition (e.g., octamethylcyclotetrasiloxane (OMCTS), trimethylsilane (TMS)) and a reactive gas (e.g., oxygen (O2)) are supplied onto the substrate, and the SiOC thin film may be deposited during the process of activating it using plasma.

[0037] Meanwhile, as illustrated in FIG. 2, the step of forming an amorphous boron nitride thin film on a metal film (S20); and the step of forming a low dielectric thin film (S30); may be performed sequentially, but in a modified embodiment of the present invention, the steps described above may be performed in a different order.

[0038] For example, in a process in which metal wiring is formed first and then an intermetallic insulating layer is formed, the step of forming a metal film can be performed before the step of forming a low-dielectric thin film (S30), but in a process in which metal wiring is formed using the damascene method after forming an intermetallic insulating layer first, the step of forming a low-dielectric thin film (S30) can be performed before the step of forming a metal film (S10).

[0039] Meanwhile, the step (S20) of forming an amorphous boron nitride thin film so that the amorphous boron nitride thin film and the low dielectric thin film are attached to each other can be performed before or after the step (S30) of forming a low dielectric thin film.

[0040] In particular, in the process of stacking multiple intermetallic insulation (IMD) structures, the order of performing the steps of forming a metal film; forming an amorphous boron nitride thin film (S20); and forming a low dielectric thin film (S30) can be arbitrarily selected.

[0041] Hereinafter, a substrate processing structure (semiconductor device) according to various embodiments of the present invention implemented by applying the substrate processing method described above with reference to FIG. 2 will be described.

[0042] FIG. 3 is a schematic cross-sectional view illustrating a substrate processing structure according to one embodiment of the present invention.

[0043] Referring to FIG. 3, a substrate processing structure according to one embodiment of the present invention comprises a metal film (20) formed on a substrate (10) and a low dielectric thin film (50) formed as an insulator for the metal film (20); and an amorphous boron nitride thin film (40) formed as a diffusion barrier to prevent metal diffusion from the metal film (20) while adhering to the low dielectric thin film (50).

[0044] In the present invention, the metal film (20) may include, for example, a copper thin film. In this case, the metal diffusion may include copper diffusion.

[0045] The amorphous boron nitride film (40) can not only serve as a diffusion barrier to prevent metal diffusion from the metal film (20) but also serve to absorb moisture.

[0046] In addition, the amorphous boron nitride thin film (40) can also serve as an etch stopper during the patterning process of the upper low-dielectric thin film (e.g., SiOC thin film). This is because fine control of the etching is possible through BN detection during the etching process.

[0047] The etch stop layer is a layer that serves as a reference to stop etching in order to prevent damage to the underlying layer. BN is a very stable compound and can serve as an etch stop layer used in semiconductor manufacturing processes. That is, when etching reaches the amorphous boron nitride thin film (40), further etching can be prevented because BN has very high stability.

[0048] The above low-dielectric thin film (50) may be a SiOC thin film, and in this case, it was confirmed that there is no problem with the adhesion of the amorphous boron nitride thin film (40) to the upper low-dielectric thin film (50), which is a SiOC thin film. A detailed explanation of this will be provided later with reference to FIG. 5.

[0049] According to one aspect, a substrate processing structure (semiconductor device) according to one embodiment of the present invention may include a substrate (10); a metal film (20) on the substrate (10); an amorphous boron nitride thin film (40) on the metal film (20); and a low dielectric thin film (50) on the amorphous boron nitride thin film (40).

[0050] The substrate processing structure illustrated in FIG. 3 is implemented by replacing the SiCN thin film (30) of the substrate processing structure illustrated in FIG. 1 with an amorphous boron nitride thin film (40). The amorphous boron nitride thin film (40) may have a thickness of 120 to 200 Å.

[0051] The inventor can implement the function of a diffusion barrier to prevent metal diffusion (e.g., copper diffusion) from a metal film (e.g., copper film) by securing the thickness of the amorphous boron nitride film (40) to a level of 120 to 200 Å, and in this case, it was confirmed that the dielectric constant k value of the amorphous boron nitride film (40) is about 3.8 or less. In addition, the dielectric constant k value of the SiOC film is about 2.9. Therefore, the amorphous boron nitride film and the SiOC film are provided together to realize low dielectric constant characteristics in an intermetallic insulation (IMD) structure.

[0052] As described above, in the substrate processing structure shown in FIG. 1, the thickness of the SiCN thin film (30) must be at least 700 Å to perform the function of a diffusion barrier to prevent metal diffusion, and in this case, the dielectric constant k value was confirmed to be about 5.3.

[0053] According to this, in a substrate processing structure according to one embodiment of the present invention, the thickness (120 to 200 Å) of the amorphous boron nitride thin film (40) can be reduced compared to the thickness (700 Å) of the conventional SiCN thin film (30) in order to perform the function of a diffusion barrier to prevent metal diffusion from the metal film (20), and the advantage of being able to achieve low dielectric constant characteristics due to the reduction in thickness can be expected.

[0054] In other words, when an amorphous boron nitride thin film is applied to perform the function of a diffusion barrier to prevent metal diffusion, the thickness can be reduced compared to conventional SiCN thin films, and film quality of equivalent or superior quality can be secured through this thickness reduction.

[0055] FIG. 4 is a schematic cross-sectional view illustrating a substrate processing structure according to a modified embodiment of the present invention.

[0056] Referring to FIG. 4, a substrate processing structure according to a modified embodiment of the present invention comprises a metal film (20) formed on a substrate (10) and a low dielectric thin film (50) formed as an insulator for the metal film (20); and an amorphous boron nitride thin film (40) that is adhered to the low dielectric thin film (50) and formed as a diffusion barrier to prevent metal diffusion from the metal film (20).

[0057] In the present invention, the metal film (20) may include, for example, a copper thin film. In this case, the metal diffusion may include copper diffusion.

[0058] According to one aspect, a substrate processing structure (semiconductor device) according to a modified embodiment of the present invention may include a lower structure (200); an amorphous boron nitride thin film (40) on the lower structure (200); a low dielectric thin film (50) on the amorphous boron nitride thin film (40); and a metal film (20) formed to fill a concave portion within the low dielectric thin film (50).

[0059] The low-dielectric thin film (50) and the amorphous boron nitride thin film (40) may constitute at least a part of the inter-metal dielectric (IMD) structure forming the wiring structure. In this case, the metal film (20) may form the metal wiring, and may further include a barrier pattern (22) containing tantalum that surrounds the sidewall of the metal film (20) which is the metal wiring between the metal film (20) which is the metal wiring and the low-dielectric thin film (50).

[0060] The barrier pattern (22) containing tantalum may be, for example, a barrier pattern in which a tantalum pattern and a tantalum nitride pattern are sequentially stacked.

[0061] Both the barrier pattern (22) containing tantalum and the amorphous boron nitride thin film (40) serve as diffusion barriers to prevent metal diffusion from the metal film (20), but the barrier pattern (22) containing tantalum has a shape that surrounds the sidewall of the metal film (20), which is the metal wiring, whereas the amorphous boron nitride thin film (40) has a shape that covers the entire low-dielectric thin film (50) at the top or bottom of the intermetallic insulation (IMD) structure, so they can be distinguished in that.

[0062] The substructure (200) may include a substrate and / or a semiconductor device formed on the substrate. The semiconductor device may include at least one selected from a gate structure, a capacitor structure, and a wiring structure.

[0063] For example, the lower structure (200) may be a wiring structure including metal wiring and an intermetal dielectric (IMD) structure. In this case, the amorphous boron nitride thin film (40) shown in FIG. 4 can be understood as being interposed between the lower first intermetal dielectric (IMD) structure and the upper second intermetal dielectric (IMD) structure. Here, the lower first intermetal dielectric (IMD) structure corresponds to the lower structure (200) shown in FIG. 4, and the upper second intermetal dielectric (IMD) structure may correspond to the low dielectric thin film (50) shown in FIG. 4.

[0064] Meanwhile, the amorphous boron nitride film (40) can not only serve as a diffusion barrier to prevent metal diffusion from the metal film (20) but also serve to absorb moisture.

[0065] The above low-dielectric thin film (50) may be a SiOC thin film, and in this case, it was confirmed that there is no problem with the adhesion of the above amorphous boron nitride thin film (40) to the upper low-dielectric thin film (50), which is a SiOC thin film.

[0066] Figure 5 shows the nano scratch evaluation results of a thin film in a substrate treatment structure according to an embodiment and a comparative example of the present invention.

[0067] In FIG. 5, item (a) corresponds to a structure in which a silicon substrate; a SiCN thin film on the silicon substrate; and a SiOC thin film on the SiCN thin film are sequentially stacked, item (b) corresponds to a structure in which a silicon substrate; an amorphous boron nitride thin film (a-BN) on the silicon substrate; and a SiOC thin film on the amorphous boron nitride thin film (a-BN) are sequentially stacked, and item (c) corresponds to a structure in which a silicon substrate; and a SiOC thin film on the silicon substrate are sequentially stacked.

[0068] The measured critical load for each item is plotted. In nano-scratch evaluation, the critical load is an important concept when measuring surface friction strength. It refers to the maximum pressure applied to a surface at which failure or deformation occurs at a specific point on the surface. In other words, as an indicator of the maximum frictional force the surface can withstand, a higher critical load may imply higher adhesion of the thin film.

[0069] Referring to Fig. 5, it can be seen that the adhesion force (b) between the a-BN thin film and the SiOC thin film in the substrate processing structure shown in Fig. 3 is higher than the adhesion force (a) between the SiCN thin film and the SiOC thin film in the substrate processing structure shown in Fig. 1.

[0070] So far, a substrate processing method and a substrate processing structure (semiconductor device) according to the technical concept of the present invention have been described.

[0071] In particular, when the metal wiring material in an intermetallic insulation (IMD) structure contains copper, a novel amorphous boron nitride thin film is introduced to perform the function of a diffusion barrier to prevent copper diffusion while simultaneously possessing low dielectric constant characteristics, and a substrate processing method and a substrate processing structure are implemented to ensure sufficient adhesion between the novel thin film and a surrounding low dielectric thin film, SiOC thin film.

[0072] The present invention has been described with reference to the embodiments illustrated in the drawings, but this is merely illustrative, and those skilled in the art will understand that various modifications and equivalent alternative embodiments are possible therefrom. Accordingly, the true technical scope of protection of the present invention should be determined by the technical spirit of the appended claims. Explanation of the symbols

[0073] 10: Substrate 20: Metal film 30: SiCN thin film 40: Amorphous boron nitride thin film 50: Low-dielectric thin film

Claims

Claim 1 A substrate processing method comprising: a step of forming an amorphous boron nitride thin film on a metal film; and a step of forming a low dielectric thin film on the amorphous boron nitride thin film. Claim 2 A substrate processing method according to claim 1, characterized in that the low dielectric thin film is a SiOC thin film. Claim 3 A substrate processing method according to claim 1, characterized in that the amorphous boron nitride thin film has a thickness of 120 to 200 Å. Claim 4 A substrate processing structure comprising: a low dielectric thin film formed as an insulator for a metal film formed on a substrate; and an amorphous boron nitride thin film that is adhered to the low dielectric thin film and formed as a diffusion barrier to prevent metal diffusion from the metal film. Claim 5 A substrate processing structure according to claim 4, characterized in that the low dielectric thin film is a SiOC thin film. Claim 6 A substrate treatment structure according to claim 4, characterized in that the amorphous boron nitride thin film has a thickness of 120 to 200 Å. Claim 7 In claim 4, the substrate processing structure wherein the low dielectric thin film and the amorphous boron nitride thin film constitute at least a part of the intermetal dielectric (IMD) structure. Claim 8 In claim 7, the metal film comprises a copper thin film, the copper thin film forms a metal wiring, and further comprises a barrier pattern containing tantalum surrounding the sidewall of the metal wiring between the metal wiring and the low dielectric thin film, and the amorphous boron nitride thin film is interposed between a first intermetallic insulation (IMD) structure and a second intermetallic insulation (IMD) structure, a substrate processing structure.

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