Semiconductor package

Abstract

A semiconductor package according to an embodiment of the present invention may include a semiconductor chip, a lead frame provided on a lower surface of the semiconductor chip and extending over a first side of the semiconductor chip, a wire extending from a first region on the upper surface of the semiconductor chip, the wire being connected to the lead frame on the first side of the semiconductor chip, and a shielding structure covering a second region on the upper surface of the semiconductor chip and exposing the first region. The shielding structure may include a contact portion covering the second region on the upper surface of the semiconductor chip, a protrusion connected to the lead frame on the second side of the semiconductor chip, and a connecting portion connecting the contact portion and the protrusion. The shielding structure may include tungsten (W).

Description

Technology Field

[0001] The technical field of the present invention relates to semiconductor packages, and more specifically, to semiconductor packages capable of protecting semiconductor devices from radiation. Background Technology

[0002] With the advancement of science and technology, the need for aerospace semiconductor devices for satellite communication and space research is increasing. However, a problem exists in that aerospace semiconductor devices exhibit performance degradation caused by radiation, which does not occur when used in conventional Earth environments.

[0003] Various semiconductor packaging technologies are being proposed to protect semiconductor devices from such radiation. For example, ceramic and metal-based sealed packaging technology has been proposed.

[0004] However, these packages have the problem of being heavy and bulky. Accordingly, there is a demand for technology to manufacture miniaturized and lightweight radiation-resistant semiconductor packages. The problem to be solved

[0005] The technical problem that the present invention aims to solve is to provide a semiconductor package capable of shielding radiation.

[0006] The problems that the present invention aims to solve are not limited to those mentioned, and other unmentioned problems will be clearly understood by a person skilled in the art from the description below. means of solving the problem

[0007] A semiconductor package according to an embodiment of the present invention comprises: a semiconductor chip; a lead frame provided on a lower surface of the semiconductor chip and extending over a first side of the semiconductor chip; a wire extending from a first region on the upper surface of the semiconductor chip, said wire being connected to the lead frame on the first side of the semiconductor chip; and a shielding structure covering a second region on the upper surface of the semiconductor chip and exposing the first region, wherein the shielding structure may include a contact portion covering the second region on the upper surface of the semiconductor chip; a protrusion connected to the lead frame on the second side of the semiconductor chip; and a connecting portion connecting the contact portion and the protrusion. The shielding structure may include tungsten (W).

[0008] A semiconductor package according to an embodiment of the present invention comprises a semiconductor chip, wherein the semiconductor chip includes a gate terminal protruding onto an upper surface of the semiconductor chip; a lead frame provided on a lower surface of the semiconductor chip and extending onto one side of the semiconductor chip; and a shielding structure covering at least a portion of the upper surface of the semiconductor chip, wherein the shielding structure may include a contact portion covering at least a portion of the upper surface of the semiconductor chip; a protrusion connected to the lead frame; and a connecting portion connected to the contact portion and the protrusion and bent from the contact portion. The contact portion may surround at least three of the sides of the gate terminal.

[0009] A semiconductor package according to an embodiment of the present invention comprises: a substrate including a wiring layer; a semiconductor chip disposed on an upper surface of the substrate; a first lead and a second lead spaced apart from the semiconductor chip on the upper surface of the substrate; and a shielding structure covering the entire upper surface of the semiconductor chip, wherein each of the first and second leads may extend in a direction parallel to the upper surface of the substrate and extend onto one side of the substrate. The shielding structure includes a first lower surface and a second lower surface located at different vertical levels, wherein the first lower surface covers the upper surface of the semiconductor chip and the second lower surface may be connected to the upper surface of the substrate. The semiconductor chip includes a semiconductor substrate and a drain terminal provided on the upper surface of the semiconductor substrate, and the shielding structure may electrically connect the drain terminal and the first lead. Effects of the invention

[0010] A semiconductor package according to an embodiment of the present invention may be provided, which includes a clip-shaped radiation shielding structure covering a part of a semiconductor device, thereby protecting the semiconductor device from radiation.

[0011] According to an embodiment of the present invention, a semiconductor package with improved heat dissipation characteristics can be provided as a radiation shielding structure composed of a material with high thermal conductivity covers a part of the semiconductor device. Brief explanation of the drawing

[0012] FIG. 1 is a perspective view for illustrating a semiconductor package according to one embodiment of the present invention. FIG. 2 is a cross-sectional view illustrating a semiconductor package according to one embodiment of the present invention, cut along the line A-A' of FIG. 1. FIG. 3 is a plan view illustrating a semiconductor package according to one embodiment of the present invention. FIG. 4 is an enlarged view illustrating a semiconductor package according to one embodiment of the present invention. FIGS. 5 and FIGS. 6 are perspective views for illustrating a semiconductor package according to an embodiment of the present invention. FIG. 7 is a cross-sectional view illustrating a semiconductor package according to one embodiment of the present invention, cut along the line B-B' of FIG. 6. FIG. 8 is a perspective view illustrating a semiconductor package according to one embodiment of the present invention. FIG. 9 is a plan view for explaining a semiconductor package according to an embodiment of the present invention, showing the semiconductor package of FIG. 8. FIG. 10 is a perspective view illustrating a semiconductor package according to one embodiment of the present invention. FIG. 11 is a plan view for explaining a semiconductor package according to one embodiment of the present invention, showing the semiconductor package of FIG. 10. FIGS. 12 to 15 are perspective views for illustrating a semiconductor package according to an embodiment of the present invention. Specific details for implementing the invention

[0013] In order to fully understand the structure and effects of the present invention, preferred embodiments of the present invention are described with reference to the attached drawings. However, the present invention is not limited to the embodiments disclosed below, but can be implemented in various forms and various modifications can be made. The description of these embodiments is provided merely to ensure that the disclosure of the present invention is complete and to fully inform those skilled in the art of the scope of the invention.

[0014] The terms used herein are for describing the embodiments and are not intended to limit the invention. In this specification, the singular form includes the plural form unless specifically stated otherwise in the text. As used herein, "comprises" and / or "comprising" do not exclude the presence or addition of one or more other components, steps, actions, and / or elements of the mentioned components, steps, actions, and / or devices. As they are based on preferred embodiments, the reference numerals presented in the order of description are not necessarily limited to that order.

[0015] Unless otherwise defined, technical and scientific terms used in this specification have the meanings commonly understood by those skilled in the art to which this invention pertains, and descriptions of known functions and configurations that could unnecessarily obscure the essence of the invention are omitted in the following description and accompanying drawings.

[0016] In the various embodiments of this specification, terms such as first, second, etc., have been used to describe various regions, membranes (or layers), etc., but these regions and membranes should not be limited by such terms. These terms are used merely to distinguish one specific region or membrane (or layer) from another region or membrane (or layer). Throughout the entire specification, the same reference numerals may refer to the same components. Unless otherwise defined, the terms used in the embodiments of the invention may be interpreted in the sense commonly known to those skilled in the art.

[0017] Hereinafter, a semiconductor package according to the concept of the present invention will be described with reference to the drawings. FIG. 1 is a perspective view for describing a semiconductor package according to an embodiment of the present invention. FIG. 2 is a cross-sectional view for describing a semiconductor package according to an embodiment of the present invention, cut along the line A-A' of FIG. 1. FIG. 3 is a plan view for describing a semiconductor package according to an embodiment of the present invention, showing the semiconductor package of FIG. 1. FIG. 4 is an enlarged view for describing a semiconductor package according to an embodiment of the present invention, showing an enlarged view of the P1 portion of FIG. 2.

[0018] Referring to FIGS. 1 to 3, a semiconductor package (1) may include a lead frame (100) and a semiconductor chip (200) on the lead frame (100). The lead frame (100) may include leads (101) and a pad (102). The pad (102) may be in the form of a plate. The pad (102) may provide a mounting surface on which the semiconductor chip (200) is mounted. In this specification, the mounting surface of the pad (102) may refer to the upper surface of the pad (102). That is, the semiconductor chip (200), which will be described later, may be mounted on the upper surface of the pad (102). The pad (102) may include a conductive material. For example, the pad (102) may be composed of a metal or an alloy thereof that has relatively good electrical conductivity, such as copper (Cu), iron-nickel (Fe-Ni), aluminum (Al), or stainless steel.

[0019] Leads (101) may be disposed on the first side (102s1) of the pad (102). The leads (101) may extend outward from the first side (102s1) of the pad (102). The leads (101) may be spaced horizontally apart on the first side (102s1) of the pad (102). Each of the leads (101) may be in the form of a line extending in one direction parallel to the upper surface of the pad (102) from the first side (102s1) of the pad (102).

[0020] The leads (101) may include a first lead (101a), a second lead (101b), and a third lead (101c). The leads (101) may serve to transmit electrical signals to the outside of the package. In this case, the first lead (101a) may refer to a lead that transmits current input or output from the drain electrode of the semiconductor chip (200) described later to the outside. The second lead (101b) may refer to a lead that transmits current input or output from the gate electrode of the semiconductor chip (200) described later to the outside. The third lead (101c) may refer to a lead that transmits current input or output from the source electrode of the semiconductor chip (200) described later to the outside.

[0021] The first lead (101a) may come into contact with the first side (102s1) of the pad (102). The first lead (101a) may be electrically connected to the pad (102). In a planar view, the second and third leads (101b, 101c) may be spaced horizontally apart from the first side (102s1) of the pad (102). In a planar view, of the two ends of the second and third leads (101b, 101c), the end closer to the first side (102s1) of the pad (102) may be wider than the other end.

[0022] The leads (101) may include a conductive material. For example, the leads (101) may be composed of a metal with relatively good electrical conductivity, such as copper (Cu), iron-nickel (Fe-Ni), aluminum (Al), or stainless steel, or an alloy thereof. The material constituting the leads (101) and the material constituting the pad (102) may be the same. However, the present invention is not limited thereto, and the material constituting the pad (102) may be different from the material constituting the leads (101).

[0023] Although FIG. 1 illustrates that leads (101) are provided on only one side of the pad (102), the present invention is not limited thereto. Leads (101) may protrude on two or more sides of the pad (102). For example, leads (101) may protrude outwardly from the left and right sides of the pad (102). Additionally, FIG. 1 describes that some leads (101b, 101c) of the leads (101) are spaced apart from the first side (102s1) of the pad (102) and the remaining leads (101a) are in contact with the first side (102s1) of the pad (102), but the present invention is not limited thereto. All leads (101) may be spaced horizontally apart from the sides of the pad (102). Furthermore, the number of leads (101) may vary as needed. The following description will be based on the embodiment of FIG. 1.

[0024] A semiconductor chip (200) may be provided on the mounting surface of the pad (102). A lead frame (100) may extend from the lower surface of the semiconductor chip (200) onto a second side (200s2) of the semiconductor chip (200). At this time, the second side (200s2) of the semiconductor chip (200) may refer to the side closest to the first side (102s1) of the pad (102) among the sides of the semiconductor chip (200). The semiconductor chip (200) may be attached to the pad (102) through a first adhesive layer (210). A first adhesive layer (210) may be interposed between the semiconductor chip (200) and the mounting surface of the pad (102). The first adhesive layer (210) may fill at least a portion between the lower surface of the semiconductor chip (200) and the mounting surface of the pad (102). The first adhesive layer (210) may include a conductive material. The first adhesive layer (210) may include a solder material. For example, the first adhesive layer (210) may include a lead-tin or indium-tin solder. Alternatively, the first adhesive layer (210) may include a conductive polymer adhesive. For example, the first adhesive layer (210) may include a conductive epoxy adhesive.

[0025] The semiconductor chip (200) may include vertical or horizontal elements. In this specification, a vertical element may refer to a semiconductor element through which current flows vertically. The vertical element may have at least one input on one side of the vertical element and an output on the other side of the vertical element. In this specification, a horizontal element may refer to a semiconductor element through which current flows horizontally. The horizontal element may have at least one input and at least one output on one side of the horizontal element. The type of semiconductor chip (200) mounted on the lead frame (100) may not be limited. However, for convenience of explanation below, the semiconductor chip (200) will be described as being a vertical power transistor.

[0026] A semiconductor chip (200) may include a semiconductor substrate (201). The semiconductor substrate (201) may include a semiconductor material. For example, the semiconductor substrate (201) may include silicon (Si). Although not illustrated, the semiconductor chip (200) may include a source electrode, a drain electrode, a gate electrode, and a channel layer formed on the semiconductor substrate (201). The channel layer may serve as a passage for electrons to move. Electrons may move from the source electrode to the drain electrode through the channel layer. Additionally, although not illustrated, the semiconductor chip (200) may include a gate insulating film. The gate insulating film may serve to insulate between the gate electrode and the channel layer. The gate insulating film may include an insulating material. For example, the gate insulating film may be made of a material containing silicon. More specifically, it may include at least one of silicon oxide (SiO2), silicon nitride, silicon nitride, and silicon nitride.

[0027] A source terminal (not shown), a drain terminal (not shown), and a gate terminal (202) may be disposed on the upper or lower surface of a semiconductor substrate (201). In this specification, a terminal may refer to a portion to which an electrode for input or output of current can be connected. The source terminal and the drain terminal may be disposed on surfaces facing each other on the semiconductor chip (200). For example, the source terminal may be provided on the upper surface of the semiconductor chip (200). The source terminal may protrude from the upper surface of the semiconductor chip (200). The drain terminal may be disposed on the lower surface of the semiconductor chip (200). The drain terminal may protrude from the lower surface of the semiconductor chip (200). The drain terminal may be electrically connected to a first lead (101a) through a first adhesive layer (210) and a pad (102) on the lower surface of the semiconductor chip (200).

[0028] The gate terminal (202) may be provided on the same plane as the source terminal. The gate terminal (202) may be provided on the upper surface of the semiconductor chip (200). The gate terminal (202) may protrude onto the upper surface of the semiconductor chip (200). However, the present invention is not limited thereto, and the source terminal, the drain terminal, and the gate terminal (202) may be exposed onto the upper surface of the semiconductor chip (200). From a planar perspective, the gate terminal (202) and the source terminal may be horizontally spaced apart.

[0029] The upper surface of the semiconductor chip (200) may include a first region (A1) and a second region (A2). In terms of planar perspective, the first region (A1) and the second region (A2) may be horizontally spaced apart. The first region (A1) of the semiconductor chip (200) may include an area where a gate terminal (202) protrudes from the upper surface of the semiconductor chip (200). The entire portion of the upper surface of the semiconductor chip (200) including the area where the gate terminal (202) protrudes may be defined as the first region (A1). The second region (A2) may include an area where the source terminal protrudes onto the upper surface of the semiconductor chip (200). The second region (A2) may refer to the remaining area of ​​the upper surface of the semiconductor chip (200) excluding the first region (A1). The planar area of ​​the first region (A1) may be narrower than the planar area of ​​the second region (A2).

[0030] On the semiconductor chip (200), a wire (400) extending from a first region (A1) of the semiconductor chip (200) may be provided. The wire (400) may be connected to a lead frame (100) on a second side (200s2) of the semiconductor chip (200). More specifically, the wire (400) may extend from a gate terminal (202) and be connected to a second lead (101b). One end of the wire (400) may be in contact with the gate terminal (202). The other end of the wire (400) may be in contact with the second lead (101b). The wire (400) may electrically connect the gate terminal (202) of the semiconductor chip (200) to the lead frame (100).

[0031] A shielding structure (300) may be provided on the upper surface of the semiconductor chip (200). The shielding structure (300) may cover a portion of the upper surface of the semiconductor chip (200). The shielding structure (300) may cover the entire second region (A2) of the semiconductor chip (200). The shielding structure (300) may expose the first region (A1) of the semiconductor chip (200). The shielding structure (300) may connect the second region (A2) of the semiconductor chip (200) with the lead frame (100). The shielding structure (300) may electrically connect the source terminal of the semiconductor chip (200) to the third lead (101c) of the lead frame (100). The shielding structure (300) may be spaced apart from the gate terminal (202) of the semiconductor chip (200).

[0032] The shielding structure (300) may include a contact portion (300a) covering the upper surface of the semiconductor chip (200), a protrusion (300b) connected to the lead frame (100), and a connecting portion (300c) connecting the contact portion (300a) and the protrusion (300b). The shielding structure (300) may be connected to the protrusion (300b) through the connecting portion (300c) extending from the contact portion (300a). The shielding structure (300) may have a clip shape. The shielding structure (300) may have a stepped structure or a zigzag structure. Below, the structures of the contact portion (300a), the protrusion (300b), and the connecting portion (300c) of the shielding structure (300) will be described in more detail.

[0033] The contact portion (300a) may cover the source terminal of the semiconductor chip (200). The contact portion (300a) may overlap vertically with the second region (A2) of the semiconductor chip (200). On the second region (A2), the contact portion (300a) may cover the upper surface of the semiconductor chip (200). The contact portion (300a) may be spaced horizontally from the gate terminal (202) of the semiconductor chip (200). The contact portion (300a) may not overlap vertically with the gate terminal (202) of the semiconductor chip (200). The planar shape of the contact portion (300a) may be rectangular.

[0034] The protrusion (300b) may protrude onto the third side (200s3) of the semiconductor chip (200). The third side (200s3) may refer to the side adjacent to the protrusion (300b) and the connection part (300c) of the shielding structure (300) among the two sides adjacent to the second side (200s2) of the semiconductor chip (200). The protrusion (300b) may extend along the direction in which the leads (101) extend on the third side (200s3) of the semiconductor chip (200) and may be connected to the third lead (101c). The protrusion (300b) may have a line shape in a planar view. The lower surface of the protrusion (300b) may face the upper surface of the lead frame (100). More specifically, a portion of the lower surface of the protrusion (300b) may face the mounting surface of the pad (102). A portion of the lower surface of the protrusion (300b) may be spaced vertically away from the mounting surface of the pad (102). The remaining portion of the lower surface of the protrusion (300b) may face the upper surface of the third lead (101c). If necessary, the protrusion (300b) may have at least one step. For example, the protrusion (300b) may have the step in an area adjacent to the third lead (101c). By the step, the protrusion (300b) may be spaced away from the mounting surface of the pad (102) and connected to the upper surface of the third lead (101c).

[0035] The level of the lower surface of the protrusion (300b) may be lower than the level of the lower surface of the contact portion (300a). In a planar view, the protrusion (300b) may be horizontally spaced from the semiconductor chip (200). The level of the lower surface of the protrusion (300b) may be lower than the level of the upper surface of the semiconductor chip (200). In other words, the shielding structure (300) may include a first lower surface and a second lower surface. The first lower surface may refer to the lower surface of the contact portion (300a). The second lower surface may refer to the lower surface of the protrusion (300b). The level of the first lower surface may be higher than the level of the second lower surface. The first lower surface may cover the upper surface of the semiconductor chip (200). At least a portion of the second lower surface may be connected to the lead frame (100).

[0036] The shielding structure (300) may include a connecting portion (300c) connecting the contact portion (300a) and the protrusion (300b). The connecting portion (300c) may extend from one side of the contact portion (300a). The connecting portion (300c) may be in a bent shape from the upper surface of the contact portion (300a). One end of the connecting portion (300c) may be connected to the one side of the contact portion (300a), and the other end of the connecting portion (300c) may be connected to the upper surface of the protrusion (300b). The connecting portion (300c) may be in a bent shape from the upper surface of the protrusion (300b). The connecting portion (300c) may be spaced apart from the third side (200s3) of the semiconductor chip (200). The lower surface of the contact portion (300a) and the inner surface of the connection portion (300c) may form an obtuse angle. The inner surface of the connection portion (300c) may be spaced apart from the third side (200s3) of the semiconductor chip (200). At this time, the inner surface of the connection portion (300c) may refer to the side closest to the third side (200s3) of the semiconductor chip (200) among the sides of the connection portion (300c).

[0037] The contact portion (300a) may be attached to the semiconductor chip (200) via a second adhesive layer (220). A second adhesive layer (220) may be provided between the semiconductor chip (200) and the lower surface of the contact portion (300a). In the second region (A2), the second adhesive layer (220) may fill at least a portion between the upper surface of the semiconductor chip (200) and the lower surface of the contact portion (300a). The second adhesive layer (220) may include a conductive material. The second adhesive layer (220) may include a solder material. For example, the second adhesive layer (220) may include a lead-tin or indium-tin solder. However, the present invention is not limited thereto, and the second adhesive layer (220) may include a conductive polymer adhesive. For example, the second adhesive layer (220) may include a conductive epoxy adhesive. The material constituting the second adhesive layer (220) may be the same as the material constituting the first adhesive layer (210), but the present invention is not limited thereto.

[0038] A third adhesive layer (330) may be provided between the protrusion (300b) and the third lead (101c). The protrusion (300b) may be attached to the third lead (101c) through the third adhesive layer (330). The third adhesive layer (330) may electrically connect the protrusion (300b) and the third lead (101c). The third adhesive layer (330) may include a conductive material. The third adhesive layer (330) may include a solder material. For example, the third adhesive layer (330) may include a lead-tin or indium-tin solder. However, the present invention is not limited thereto, and the third adhesive layer (330) may include a conductive polymer adhesive. For example, the third adhesive layer (330) may include a conductive epoxy adhesive.

[0039] The shielding structure (300) may include a conductive material. For example, the contact portion (300a), protrusion (300b), and connection portion (300c) of the shielding structure (300) may include metal. Referring to FIG. 4, the contact portion (300a) of the shielding structure (300) may include a first metal layer (310) and a second metal layer (320) that are stacked along a direction perpendicular to the upper surface of the semiconductor chip (200). For example, the second metal layer (320) may be stacked on the upper surface of the first metal layer (310). The first metal layer (310) may include copper (Cu). The second metal layer (320) may include tungsten (W). However, the present invention is not limited thereto, and the second metal layer (320) may include a material that shields radiation. For example, the second metal layer (320) may include lead (Pb), bismuth (Bi), gold (Au), silver (Ag), etc.

[0040] In FIG. 4, the contact portion (300a) is illustrated as being composed of a first metal layer (310) and a second metal layer (320), but the present invention is not limited thereto. The contact portion (300a) of the shielding structure (300) may further include a third metal layer covering the lower surface of the first metal layer (310). The third metal layer may include a material that shields radiation. For example, the third metal layer may include tungsten (W), lead (Pb), bismuth (Bi), gold (Au), silver (Ag), etc. The material constituting the third metal layer and the material constituting the second metal layer (320) may be the same.

[0041] Additionally, although FIG. 4 describes the contact portion (300a) of the shielding structure (300) as including a first metal layer (310) and a second metal layer (320), the present invention is not limited thereto. The shielding structure (300) may include a first metal layer (310) and a second metal layer (320) in its entire area. Specifically, the protrusion (300b) and the connection portion (300c) may also include a first metal layer (310) and a second metal layer (320). Alternatively, as needed, the shielding structure (300) may include a first metal layer (310), a second metal layer (320), and the third metal layer in its entire area.

[0042] As the shielding structure (300) includes a radiation-shielding material, the shielding structure (300) can protect the semiconductor chip (200) from radiation transmitted from the outside. More specifically, the shielding structure (300) can reduce the area of ​​the gate insulating film of the radiation-vulnerable semiconductor chip (200) that is exposed to radiation. Accordingly, a semiconductor package with improved structural stability can be provided.

[0043] Additionally, as the shielding structure (300) is composed of a highly thermally conductive conductive material, heat generated from the semiconductor chip (200) can be rapidly discharged upward from the semiconductor package through the shielding structure (300). More specifically, as the shielding structure (300) covers a portion of the upper surface of the semiconductor chip (200), heat generated from the semiconductor chip (200) can be transferred to the outside along the shielding structure (300). Accordingly, a semiconductor package with improved heat dissipation characteristics can be provided.

[0045] FIG. 5 is a perspective view illustrating a semiconductor package according to an embodiment of the present invention. Referring to FIG. 5, the semiconductor package (1, see FIG. 1) may further include a molding film (500) covering a semiconductor chip (200), a wire (400), and a shielding structure (300) on the upper surface of a lead frame (100). The molding film (500) may surround the semiconductor chip (200), the wire (400), and the shielding structure (300) on the mounting surface of a pad (102). The molding film (500) may protrude in the direction in which the leads (101) extend on the mounting surface of the pad (102). The molding film (500) may cover a portion of the upper surface of the leads (101) and fill a portion of the space between the leads (101). In other words, the molding film (500) may cover a portion of the leads (101) adjacent to the first side (102s1) of the pad (102). For example, the end of the second lead (101b) connected to the wire (400) and the end of the third lead (101c) connected to the shielding structure (300) may be covered by the molding film (500). The portions of the leads (101) that are not covered by the molding film (500) may be utilized as outer leads to electrically connect the semiconductor package (1) to an external electrical device such as a printed circuit board (PCB), a main board, or a module board. The molding film (500) may include an insulating polymer material. For example, the molding film (500) may include an epoxy molding compound (EMC).

[0047] In FIG. 2, the connection portion (300c) of the shielding structure (300) is shown as being spaced apart from the third side (200s3) of the semiconductor chip (200), but the present invention is not limited thereto. FIG. 6 is a perspective view for explaining a semiconductor package according to an embodiment of the present invention. FIG. 7 is a cross-sectional view for explaining a semiconductor package according to an embodiment of the present invention, cut along the line B-B' of FIG. 6. Referring to FIG. 6 and FIG. 7, a semiconductor chip (200) and a shielding structure (300) may be provided on a lead frame (100). The lead frame (100), the semiconductor chip (200), and the shielding structure (300) may be substantially the same as those described with reference to FIG. 1 to FIG. 4. For example, on the second region (A2), the contact portion (300a) may cover the upper surface of the semiconductor chip (200). The contact portion (300a) may overlap vertically with the second region (A2) of the semiconductor chip (200). However, unlike FIG. 1, the shielding structure (300) may come into contact with the third side (200s3) of the semiconductor chip (200). The connection portion (300c) may extend in a direction perpendicular to the upper surface of the contact portion (300a). For example, the angle formed by the inner surface of the connection portion (300c) and the lower surface of the contact portion (300a) may be 90°. A portion of the inner surface of the connection portion (300c) may come into contact with the third side (200s3) of the semiconductor chip (200).

[0048] From a planar perspective, the connection portion (300c) may overlap perpendicularly with at least a portion of the protrusion (300b). The inner surface of the connection portion (300c) and the inner surface of the protrusion (300b) may form a co-plane. A portion of the inner surface of the protrusion (300b) may come into contact with the third side (200s3) of the semiconductor chip (200). In other words, the cross-section of the shielding structure (300) cut along the BB' line may have an L-shape. The protrusion (300b) may extend from the connection portion (300c) toward the direction in which the third lead (101c) extends.

[0049] As the shielding structure (300) covers at least a portion of the upper surface and third side (200s3) of the semiconductor chip (200), the semiconductor chip (200) can be more effectively protected from radiation transmitted from the outside. That is, the shielding structure (300) can reduce the area of ​​the semiconductor chip (200) exposed to radiation. Accordingly, a semiconductor package with improved structural stability can be provided.

[0051] FIG. 8 is a perspective view for illustrating a semiconductor package according to an embodiment of the present invention. FIG. 9 is a plan view for illustrating a semiconductor package according to an embodiment of the present invention, showing the semiconductor package of FIG. 8. With reference to FIG. 8 and FIG. 9, a semiconductor chip (200) and a shielding structure (300) may be provided on a lead frame (100). The lead frame (100), the semiconductor chip (200), and the shielding structure (300) may be substantially the same as those described with reference to FIG. 1 to FIG. 4. However, unlike FIG. 1, the shielding structure (300) may surround three sides of the gate terminal (202) of the semiconductor chip (200). The planar shape of the contact portion (300a) of the shielding structure (300) may be a 'C' shape.

[0052] In other words, the contact portion (300a) may include a recess area (RS). The recess area (RS) may refer to an area recessed from one side of the contact portion (300a) toward the interior of the contact portion (300a). The one side of the contact portion (300a) may refer to a side facing the side of the contact portion (300a) that contacts the connection portion (300c). The inner sides of the recess area (RS) may surround the three sides of the gate terminal (202). The inner sides of the recess area (RS) may be spaced apart from the three sides of the gate terminal (202). The upper surface of the gate terminal (202) may be exposed onto the upper surface of the contact portion (300a) of the shielding structure (300) by the recess area (RS).

[0053] In other words, the first region (A1) of the upper surface of the semiconductor chip (200) may refer to a portion of the upper surface of the semiconductor chip (200) that is exposed over the recess area (RS) of the contact portion (300a). The second region (A2) of the upper surface of the semiconductor chip (200) may refer to the remaining portion of the upper surface of the semiconductor chip (200) excluding the portion. The shielding structure (300) may cover the second region (A2) of the semiconductor chip (200) and expose the first region (A1). As the contact portion (300a) of the shielding structure (300) surrounds the three sides of the gate terminal (202), the area of ​​the semiconductor chip (200) protected by the shielding structure (300) may be increased.

[0055] FIG. 10 is a perspective view for illustrating a semiconductor package according to an embodiment of the present invention. FIG. 11 is a plan view for illustrating a semiconductor package according to an embodiment of the present invention, showing the semiconductor package of FIG. 10. With reference to FIG. 10 and FIG. 11, a semiconductor chip (200) and a shielding structure (300) may be provided on a lead frame (100). The lead frame (100), the semiconductor chip (200), and the shielding structure (300) may be substantially the same as those described with reference to FIG. 1 to FIG. 4. However, unlike FIG. 1, the shielding structure (300) may surround the four sides of the gate terminal (202) of the semiconductor chip (200).

[0056] The contact portion (300a) may include a hole (H). The hole (H) may penetrate the contact portion (300a) in a direction perpendicular to the upper surface of the lead frame (100). The planar shape of the hole (H) may be the same as the planar shape of the gate terminal (202), but the present invention is not limited thereto. The planar shape of the hole (H) may be a square, polygonal, or circular shape. The planar area of ​​the hole (H) may be larger than the planar area of ​​the gate terminal (202). In terms of planar aspect, the gate terminal (202) may be placed inside the hole (H). The contact portion (300a) of the shielding structure (300) may surround the sides of the gate terminal (202). The contact portion (300a) of the shielding structure (300) may be spaced apart from the said sides of the gate terminal (202). The upper surface of the gate terminal (202) can be exposed to the upper surface of the contact portion (300a) of the shielding structure (300) through the hole (H).

[0057] In other words, the first region (A1) of the upper surface of the semiconductor chip (200) may refer to a portion of the upper surface of the semiconductor chip (200) that is exposed over the hole (H) of the contact portion (300a). The second region (A2) of the upper surface of the semiconductor chip (200) may refer to the remaining portion of the upper surface of the semiconductor chip (200) excluding the portion. The shielding structure (300) may cover the second region (A2) of the semiconductor chip (200) and expose the first region (A1). As the contact portion (300a) of the shielding structure (300) surrounds all four sides of the gate terminal (202), the area of ​​the semiconductor chip (200) protected by the shielding structure (300) may be increased.

[0059] FIG. 12 is a perspective view illustrating a semiconductor package according to an embodiment of the present invention. Referring to FIG. 12, the semiconductor package (2) may include a substrate (600), leads (610) on the substrate (600), a semiconductor chip (200), and a shielding structure (300). The semiconductor chip (200) and the shielding structure (300) may be substantially similar to those described with reference to FIG. 1.

[0060] A substrate (600) may include a core portion (not shown) and a substrate wiring layer (not shown) disposed on the core portion. The core portion may include an insulating material. For example, the core portion may include a ceramic material. The substrate wiring layer may be provided on the upper surface of the core portion. The substrate wiring layer may include at least one insulating pattern and a wiring pattern within the insulating pattern. In this specification, the term "substrate wiring layer" may refer to a wiring layer formed by patterning one insulating material layer and one conductive material layer, respectively. That is, the wiring patterns within a substrate wiring layer may be horizontally extended wirings and may not overlap vertically with one another.

[0061] The above insulation pattern is silicon oxide (SiO₂).x ) or silicon nitride (SiN x It may include an inorganic insulating layer such as ). Alternatively, the insulating pattern may include a polymer material. The insulating pattern may include an insulating polymer or a photoimageable dielectric (PID). For example, the photoimageable polymer may include at least one of photoimageable polyimide, polybenzoxazole (PBO), a phenol-based polymer, or a benzocyclobutene-based polymer. The wiring pattern may be provided on the upper surface of the insulating pattern. The wiring pattern may protrude onto the upper surface of the insulating pattern. The wiring pattern may extend horizontally on the upper surface of the insulating pattern. The wiring pattern may be a pad portion or a wiring portion of the substrate wiring layer. The wiring pattern may include a conductive material. For example, the wiring pattern may include copper (Cu).

[0062] A first substrate pad (601), a second substrate pad (602), and a third substrate pad (603) may be provided on the upper surface of the substrate (600). The first to third substrate pads (601, 602, 603) may be part of the wiring pattern exposed from the substrate wiring layer onto the upper surface of the substrate (600). The first substrate pad (601), the second substrate pad (602), and the third substrate pad (603) may be horizontally spaced apart on the upper surface of the substrate (600).

[0063] Substrate leads (610) may be provided on the upper surface of the substrate (600). The substrate leads (610) may serve to transmit electrical signals to the outside of the package, similar to the leads (101, see FIG. 1) described with reference to FIG. 1. The substrate leads (610) may be electrically connected to the substrate (600). One end of each substrate lead (610) may be in contact with the upper surface of the substrate (600). Each substrate lead (610) may be in the form of a line extending in one direction parallel to the upper surface of the substrate (600). The substrate leads (610) may extend in the one direction and protrude onto one side of the substrate (600). If necessary, the substrate leads (610) may have at least one step. Each substrate lead (610) may be horizontally spaced from the upper surface of the substrate (600). The substrate leads (610) may include a conductive material. For example, the substrate leads (610) may be composed of a metal or an alloy thereof that has relatively good electrical conductivity, such as copper (Cu), iron-nickel (Fe-Ni), aluminum (Al), or stainless steel.

[0064] Each of the substrate leads (610) can be electrically connected to each of the first to third substrate pads (601, 602, 603). For example, the substrate leads (610) may be provided on the upper surface of each of the first substrate pad (601), the second substrate pad (602), and the third substrate pad (603). Hereinafter, for convenience of explanation, the substrate lead provided on the upper surface of the first substrate pad (601) will be referred to as the first substrate lead (610a), the substrate lead provided on the upper surface of the second substrate pad (602) as the second substrate lead (610b), and the substrate lead provided on the upper surface of the third substrate pad (603) as the third substrate lead (610c). At this time, the first substrate lead (610a) may be a lead that transmits current input or output from the drain electrode of the semiconductor chip (200) to the outside. The second substrate lead (610b) may be a lead that transmits current input or output from the gate electrode of the semiconductor chip (200) to the outside. The third substrate lead (610c) may be a lead that transmits current input or output from the source electrode of the semiconductor chip (200) to the outside.

[0065] A semiconductor chip (200) may be placed on a first substrate pad (601) of a substrate (600). On the first substrate pad (601), the semiconductor chip (200) may be placed horizontally spaced apart from the first substrate lead (610a). The semiconductor chip (200) may be attached to the first substrate pad (601) through a first adhesive layer (210) provided on the lower surface of the semiconductor chip (200). A drain terminal (not shown) exposed on the lower surface of the semiconductor chip (200) may be electrically connected to the first substrate lead (610a) through the first adhesive layer (210).

[0066] The upper surface of the semiconductor chip (200) may include a first region (A1) and a second region (A2). The first region (A1) and the second region (A2) may be substantially the same as described with reference to FIGS. 1 to 3. The first region (A1) of the semiconductor chip (200) may include a region where a gate terminal (202) protrudes from the upper surface of the semiconductor chip (200). The entire portion of the upper surface of the semiconductor chip (200) including the region where the gate terminal (202) protrudes may be defined as the first region (A1). The second region (A2) may include a region where the source terminal protrudes onto the upper surface of the semiconductor chip (200). The second region (A2) may refer to the remaining area of ​​the upper surface of the semiconductor chip (200) excluding the first region (A1).

[0067] A wire (400) may be provided to electrically connect the semiconductor chip (200) and the second substrate pad (602). The wire (400) may extend from the gate terminal (202) of the semiconductor chip (200) and be connected to the second substrate pad (602). Current input or output from the gate region of the semiconductor chip (200) may be transmitted externally through the gate terminal (202), the wire (400), the second substrate pad (602), and the second substrate lead (610b).

[0068] A shielding structure (300) may be provided on the upper surface of the semiconductor chip (200). The contact portion (300a) of the shielding structure (300) may cover at least a portion of the upper surface of the semiconductor chip (200). The contact portion (300a) of the shielding structure (300) may cover a second region (A2) of the semiconductor chip (200). The lower surface of the protrusion (300b) may be connected to the upper surface of the substrate (600). The protrusion (300b) of the shielding structure (300) may be connected to a third substrate pad (603). The protrusion (300b) may be positioned horizontally spaced apart from the third substrate lead (610c) on the third substrate pad (603). The shielding structure (300) may electrically connect the source terminal and the third substrate lead (610c) through the substrate (600). The connecting portion (300c) can connect the contact portion (300a) and the protrusion (300b). If necessary, the connecting portion (300c) may have at least one curved portion.

[0069] The protrusion (300b) can be attached to the third substrate pad (603) through a third adhesive layer (330) provided on the lower surface of the protrusion (300b). Current input or output from the source terminal of the semiconductor chip (200) can be transmitted to the outside through the shielding structure (300), the third substrate pad (603), and the third substrate lead (610c).

[0071] FIG. 13 is a perspective view illustrating a semiconductor package according to an embodiment of the present invention. Referring to FIG. 13, the semiconductor package (2, see FIG. 12) may further include a molding film (500) covering a semiconductor chip (200), a wire (400), and a shielding structure (300) on the upper surface of a substrate (600). The molding film (500) may cover a portion of the substrate leads (610) that overlap vertically with the first to third substrate pads (601, 602, 603). The portions of the substrate leads (610) that are not covered by the molding film (500) and protrude outward from one side of the molding film (500) may be utilized as outer leads to electrically connect the semiconductor package (2) to an external electrical device such as a printed circuit board (PCB), a main board, or a module board. The molding film (500) may include an insulating polymer material. For example, the molding film (500) may include an epoxy molding compound (EMC).

[0073] FIG. 14 is a perspective view illustrating a semiconductor package according to an embodiment of the present invention. Referring to FIG. 14, a semiconductor chip (200) and a shielding structure (300) may be provided on a substrate (600). The substrate (600), the semiconductor chip (200), and the shielding structure (300) may be substantially the same as those described with reference to FIG. 12. However, unlike FIG. 12, the shielding structure (300) may surround three sides of the gate terminal (202) of the semiconductor chip (200). The planar shape of the contact portion (300a) may be substantially similar to the planar shape of the contact portion (300a, see FIG. 8) described with reference to FIG. 8. For example, the planar shape of the contact portion (300a) may be a 'C' shape.

[0074] The contact portion (300a) may include a recess area (RS). The recess area (RS) may refer to an area recessed from one side of the contact portion (300a) toward the interior of the contact portion (300a). The one side of the contact portion (300a) may refer to a side of the contact portion (300a) that is adjacent to the connecting portion (300c) and faces the connecting portion (300c). The inner sides of the recess area (RS) may surround the sides of the gate terminal (202). The inner sides of the recess area (RS) may be spaced apart from the sides of the gate terminal (202). The upper surface of the gate terminal (202) may be exposed onto the upper surface of the contact portion (300a) of the shielding structure (300) by the recess area (RS).

[0075] At this time, although not illustrated, the first region (A1) of the upper surface of the semiconductor chip (200) may refer to a part of the upper surface of the semiconductor chip (200) that is exposed onto the recess region (RS) of the contact portion (300a). The second region (A2) of the upper surface of the semiconductor chip (200) may refer to the remaining part of the upper surface of the semiconductor chip (200) excluding the part of the above region. The shielding structure (300) may cover the second region (A2) of the semiconductor chip (200) and expose the first region (A1).

[0076] In FIG. 14, the contact portion (300a) is shown to include a recess region (RS), but the present invention is not limited thereto. Similar to the description with reference to FIG. 10, the contact portion (300a) may include a hole (H, see FIG. 10) and may surround the four sides of the gate terminal (202).

[0078] FIG. 15 is a perspective view illustrating a semiconductor package according to an embodiment of the present invention. Referring to FIG. 15, a semiconductor chip (200) and a shielding structure (300) may be provided on a substrate (600). The substrate (600) and the semiconductor chip (200) may be substantially the same as described with reference to FIG. 12. However, unlike FIG. 12, the semiconductor chip (200) may be mounted face-down on the substrate (600). The semiconductor chip (200) may be mounted in a flip-chip manner. The gate terminal (202, see FIG. 12) and source terminal (not shown) of the semiconductor chip (200) may be disposed on the lower surface of the semiconductor chip (200). A drain terminal (not shown) may be disposed on the upper surface of the semiconductor chip (200).

[0079] The arrangement and planar shape of the first to third substrate pads (601, 602, 603) may vary as needed. Substrate leads (610) may be disposed on the first to third substrate pads (601, 602, 603). Each of the first to third substrate leads (610a, 610b, 610c) may be appropriately disposed on the first to third substrate pads (601, 602, 603) so that the drain terminal, gate terminal (202), and source terminal of the semiconductor chip (200), respectively, may be electrically connected to the outside. The gate terminal (202) and the source terminal may be electrically connected to each of the corresponding substrate leads (610) through the substrate wiring layer of the substrate (600). As the gate terminal (202) is electrically connected to the second substrate lead (610b) through the substrate (600), a wire (400, see FIG. 12) connecting the gate terminal (202) and the second substrate lead (610b) may not be provided.

[0080] A shielding structure (300) may be provided on the upper surface of the semiconductor chip (200). The shielding structure (300) may cover the entire upper surface of the semiconductor chip (200). The contact portion (300a) of the shielding structure (300) may overlap vertically with the semiconductor chip (200). The upper surface of the semiconductor chip (200) may not be exposed on the shielding structure (300). Some sides of the contact portion (300a) may be aligned with the sides of the semiconductor chip (200). The some sides of the contact portion (300a) may refer to sides of the contact portion (300a) excluding the sides connected to the connection portion (300c). However, the present invention is not limited thereto, and the contact portion (300a) may protrude onto the sides of the semiconductor chip (200). For example, the planar area of ​​the contact portion (300a) may be larger than the planar area of ​​the semiconductor chip (200). Although not illustrated, a molding film (500, see FIG. 13) covering the semiconductor chip (200) and the shielding structure (300) on the upper surface of the substrate (600) may be further included as needed.

[0081] The shielding structure (300) can electrically connect the drain terminal to the first substrate lead (610a). The shielding structure (300) can prevent radiation transmitted from the outside from being incident on the upper surface of the semiconductor chip (200). As the contact portion (300a) of the shielding structure (300) covers the entire upper surface of the semiconductor chip (200), the area of ​​the semiconductor chip (200) protected by the shielding structure (300) can be increased. A semiconductor package with an enhanced radiation shielding effect can be provided. Explanation of the symbols

[0083] 100 : Lead frame 101 : Leads 200 : Semiconductor device 300 : Shielding structure 400 : Wire 500 : Molding film

Claims

Claim 1 A semiconductor chip; a lead frame provided on a lower surface of the semiconductor chip and extending over a first side of the semiconductor chip; a wire extending from a first region on the upper surface of the semiconductor chip, said wire connected to the lead frame on the first side of the semiconductor chip; and a shielding structure covering a second region on the upper surface of the semiconductor chip and exposing the first region, wherein the shielding structure comprises: a contact portion covering the second region on the upper surface of the semiconductor chip; a protrusion connected to the lead frame on the second side of the semiconductor chip; and a connecting portion connecting the contact portion and the protrusion, said shielding structure comprising tungsten (W). Claim 2 A semiconductor package according to claim 1, wherein the first region and the second region of the upper surface of the semiconductor chip are horizontally spaced apart from each other, the semiconductor chip includes a gate terminal provided on the first region and a source terminal provided on the second region, the gate terminal is exposed on the upper surface of the semiconductor chip, and the wire extends from the gate terminal and contacts the lead frame. Claim 3 In claim 2, the semiconductor chip further comprises a drain terminal exposed on the lower surface of the semiconductor chip, wherein the drain terminal is electrically connected to the lead frame by a first adhesive layer provided on the lower surface of the semiconductor chip. Claim 4 A semiconductor package according to claim 2, wherein the lead frame comprises a pad and a plurality of leads extending in one direction parallel to the upper surface of the pad on one side of the pad, the semiconductor chip is disposed on the upper surface of the pad, the wire electrically connects the gate terminal to one of the leads, and the protrusion electrically connects the source terminal to the other of the leads. Claim 5 In claim 4, the level of the lower surface of the protrusion is lower than the level of the lower surface of the contact portion, the protrusion extends in one direction and is connected to the other lead, and the connection portion is a semiconductor package bent from the upper surface of the contact portion. Claim 6 A semiconductor package according to claim 1, wherein the semiconductor chip includes a gate terminal provided on the first region, the gate terminal is exposed on the upper surface of the semiconductor chip, and the second region corresponds to the remaining region of the upper surface of the semiconductor chip excluding the region where the gate terminal is exposed. Claim 7 A semiconductor package according to claim 1, further comprising a molding film covering the semiconductor chip and the shielding structure on the lead frame, wherein the molding film comprises an epoxy-based polymer. Claim 8 A semiconductor package according to claim 1, further comprising a second adhesive layer interposed between the upper surface of the semiconductor chip and the lower surface of the contact portion, wherein the second adhesive layer comprises a conductive material. Claim 9 A semiconductor package according to claim 1, wherein the lower surface of the contact portion and the inner surface of the connection portion form an obtuse angle, and the inner surface of the connection portion is spaced apart from the second side of the semiconductor chip. Claim 10 In claim 1, the connecting portion of the shielding structure extends in a direction perpendicular to the upper surface of the contact portion, and the connecting portion contacts the second side of the semiconductor chip in a semiconductor package. Claim 11 A semiconductor package according to claim 1, wherein the contact portion of the shielding structure comprises a first metal layer and a second metal layer stacked in sequence, wherein the first metal layer comprises copper (Cu) and the second metal layer comprises tungsten (W). Claim 12 A semiconductor chip, wherein the semiconductor chip comprises a gate terminal protruding onto an upper surface of the semiconductor chip; a lead frame provided on a lower surface of the semiconductor chip and extending onto one side of the semiconductor chip; and a shielding structure covering at least a portion of the upper surface of the semiconductor chip, wherein the shielding structure comprises: a contact portion covering at least a portion of the upper surface of the semiconductor chip; a protrusion connected to the lead frame; and a connecting portion connected to the contact portion and the protrusion and bent from the contact portion, wherein the contact portion surrounds at least three of the sides of the gate terminal. Claim 13 A semiconductor package according to claim 12, wherein the contact portion includes a first hole penetrating the contact portion, and the gate terminal is exposed onto the upper surface of the shielding structure by the first hole. Claim 14 A semiconductor package according to claim 12, further comprising a molding film surrounding the semiconductor chip and the shielding structure on the lead frame, wherein the molding film comprises an epoxy-based polymer. Claim 15 A semiconductor package according to claim 12, wherein the contact portion comprises a first metal layer and a second metal layer stacked in sequence, wherein the first metal layer comprises copper (Cu) and the second metal layer comprises tungsten (W). Claim 16 In claim 15, the contact portion further comprises a third metal layer covering the lower surface of the first metal layer, wherein the third metal layer comprises tungsten (W). Claim 17 A semiconductor package comprising: a substrate including a wiring layer; a semiconductor chip disposed on an upper surface of the substrate; a first lead and a second lead spaced apart from the semiconductor chip on the upper surface of the substrate; and a shielding structure covering the entire upper surface of the semiconductor chip, wherein each of the first and second leads extends in a direction parallel to the upper surface of the substrate and extends onto one side of the substrate, and the shielding structure includes a first lower surface and a second lower surface located at different vertical levels, wherein the first lower surface covers the upper surface of the semiconductor chip and the second lower surface is connected to the upper surface of the substrate, and the semiconductor chip includes a semiconductor substrate and a drain terminal provided on the upper surface of the semiconductor substrate, and the shielding structure electrically connects the drain terminal and the first lead. Claim 18 In claim 17, the semiconductor chip further comprises a gate terminal provided on the lower surface of the semiconductor substrate, and the wiring layer electrically connects the gate terminal and the second lead in a semiconductor package. Claim 19 In claim 17, the shielding structure comprises a first metal layer and a second metal layer laminated on the first metal layer, wherein the second metal layer comprises tungsten (W). Claim 20 In claim 17, the substrate further comprises a core layer provided on the lower surface of the wiring layer, wherein the core layer comprises a ceramic semiconductor package.

Images