Image sensor

Abstract

An image sensor is disclosed. The image sensor comprises a first pixel region and a second pixel region formed within a semiconductor substrate and each forming a photoelectric conversion element, a first element isolation layer formed to surround the first pixel region and the second pixel region, a second element isolation layer formed between the first pixel region and the second pixel region, and a single microlens disposed on the first pixel region and the second pixel region, wherein the second element isolation layer includes at least one first open region that opens a portion between the first pixel region and the second pixel region.

Description

Technology Field

[0001] The technical concept of the present invention relates to an image sensor, and more specifically, to an image sensor comprising a device isolation film. Background Technology

[0002] Image sensors, which capture images and convert them into electrical signals, are used not only in general consumer electronic devices such as digital cameras, mobile phone cameras, and portable camcorders, but also in cameras mounted in automobiles, security devices, and robots.

[0003] Recently, autofocus (AF) methods that automatically detect the focus of image sensors are being widely utilized. In particular, various studies are being conducted on phase difference autofocus (PAF) technology due to its characteristic of fast focus detection speed. In PAF, light transmitted through the imaging lens is split and detected by different focus detection pixels; the focusing lens is then automatically driven to adjust the focal length so that the detected signals have the same intensity and phase. The problem to be solved

[0004] The technical problem that the technical concept of the present invention aims to solve is to provide an image sensor having a device isolation film formed therein that includes an open region. means of solving the problem

[0005] An image sensor according to the technical concept of the present invention for achieving the above technical problem comprises a first pixel region and a second pixel region formed inside a semiconductor substrate and each forming a photoelectric conversion element, a first element isolation layer formed to surround the first pixel region and the second pixel region, a second element isolation layer formed between the first pixel region and the second pixel region, and a single microlens disposed on the first pixel region and the second pixel region, wherein the second element isolation layer may include at least one first open region that opens a portion between the first pixel region and the second pixel region.

[0006] An image sensor according to the technical concept of the present invention for achieving the above technical problem comprises a semiconductor substrate having a first surface and a second surface facing the first surface, a first pixel area and a second pixel area formed inside the semiconductor substrate and each forming a photoelectric conversion element, a first element isolation layer formed to surround the first pixel area and the second pixel area, and a second element isolation layer formed between the first pixel area and the second pixel area, wherein the first element isolation layer and the second element isolation layer are formed to extend from the first surface to the second surface, and the second element isolation layer may include a first open area that opens a portion between the first pixel area and the second pixel area.

[0007] An image sensor according to the technical concept of the present invention for achieving the above technical problem comprises a first pixel region and a second pixel region formed within a semiconductor substrate and each forming a photoelectric conversion element, a first element isolation layer formed to surround the first pixel region and the second pixel region, a second element isolation layer formed between the first pixel region and the second pixel region, and a floating diffusion region that accumulates photoelectric charges formed from the photoelectric conversion elements formed in the first pixel region and the second pixel region, respectively, and the second element isolation layer may include an open region that opens a portion between the first pixel region and the second pixel region. Effects of the invention

[0008] An image sensor according to the technical concept of the present disclosure includes a pixel group for performing an AF function, and a first pixel and a second pixel included in the pixel group can be separated from each other by a device isolation film including an open region. Since an open region is formed in the device isolation film, light scattering by the device isolation film can be reduced, and the light-receiving area within the pixel group can be increased. Brief explanation of the drawing

[0009] FIG. 1 is a block diagram showing the configuration of an image sensor according to an exemplary embodiment of the present disclosure. Figure 2 is a circuit diagram for a group of pixels included in the pixel array of Figure 1. FIGS. 3a and 3b are drawings of a group of pixels included in an image sensor according to an exemplary embodiment of the present disclosure. Figure 4 is a cross-sectional view of Figure 3a II'. Figure 5 is a cross-sectional view taken along line II-II' of Figure 3a. FIG. 6 is a drawing of a group of pixels included in an image sensor according to an exemplary embodiment of the present disclosure. Figure 7 is a cross-sectional view of line III-IIII' of Figure 6. FIG. 8 is a drawing of a group of pixels included in an image sensor according to an exemplary embodiment of the present disclosure. FIG. 9 is a drawing of a group of pixels included in an image sensor according to an exemplary embodiment of the present disclosure. FIG. 10 is a drawing of a group of pixels included in an image sensor according to an exemplary embodiment of the present disclosure. FIGS. 11a and FIGS. 11b are drawings of a group of pixels included in an image sensor according to an exemplary embodiment of the present disclosure. FIG. 12 is a drawing of a group of pixels included in an image sensor according to an exemplary embodiment of the present disclosure. Fig. 13 is a cross-sectional view taken along IV-IV' of Fig. 12. FIG. 14 is a drawing of a group of pixels included in an image sensor according to an exemplary embodiment of the present disclosure. Fig. 15 is a cross-sectional view of VV' of Fig. 14. FIG. 16 is a block diagram of an electronic device including a multi-camera module. Figure 17 is a detailed block diagram of the camera module of Figure 16. Specific details for implementing the invention

[0010] Hereinafter, preferred embodiments of the technical concept of the present invention will be described in detail with reference to the attached drawings.

[0011] FIG. 1 is a block diagram showing the configuration of an image sensor according to an exemplary embodiment of the present disclosure.

[0012] Referring to FIG. 1, the image sensor (100) may include a pixel array (110), a control unit (120), a signal processing unit (130), a row driver (140), and a signal readout unit (150). The signal readout unit (150) may include a Correlated-Double Sampling (hereinafter CDS; 151), an Analog-Digital Converter (hereinafter ADC; 153), and a buffer (155).

[0013] The pixel array (110) may include a plurality of pixels. Each of the plurality of pixels may generate image signals corresponding to an object. The pixel array (110) may output pixel signals to the CDS (151) through corresponding first to n-1 column output lines (CLO_0 to CLO_n-1).

[0014] The pixel array (110) may include a plurality of pixel groups (PG). Each of the plurality of pixel groups (PG) may be defined by a first element isolation layer. An exemplary circuit corresponding to a pixel group (PG) will be described later in FIG. 2.

[0015] Each of the pixel groups (PG) may include a plurality of pixels, for example, a first pixel (PX1) and a second pixel (PX2). The first pixel (PX1) and the second pixel (PX2) may be separated from each other by a second device isolation layer and may be defined by the first device isolation layer and the second device isolation layer.

[0016] In an exemplary embodiment, each pixel group (PG) may include two pixels, or in an exemplary embodiment, each pixel group (PG) may include four pixels. However, the number of pixels included in one pixel group (PG) may vary.

[0017] Each of the first pixel (PX1) and the second pixel (PX2) may include a corresponding photoelectric conversion element and may absorb light to generate photoelectric charge. For example, the photoelectric conversion element may be a photodiode. In an exemplary embodiment, the first pixel (PX1) and the second pixel (PX2) included in the same pixel group (PG) may share a floating diffusion region in which photoelectric charge generated by the photoelectric conversion element is accumulated. However, this is not limited thereto, and the first pixel (PX1) and the second pixel (PX2) may each include a separate floating diffusion region.

[0018] The second device isolation layer may be formed between a first photoelectric conversion region where the photoelectric conversion element of the first pixel (PX1) is formed and a second photoelectric conversion region where the photoelectric conversion element of the second pixel (PX2) is formed. The second device isolation layer may include an open region that opens a portion between the first photoelectric conversion region and the second photoelectric conversion region. Since the image sensor (100) according to the present disclosure is formed in the open region of the second device isolation layer, it is possible to prevent a reduction in light sensing sensitivity due to the second device isolation layer. Additionally, the linearity of the full wells of the first pixel (PX1) and the second pixel (PX2) may be improved by a passivation film formed in the open region of the second device isolation layer and doped with P-type impurities.

[0019] In an exemplary embodiment, a first pixel (PX1) and a second pixel (PX2) included in the same pixel group (PG) may be arranged side by side in a first direction (e.g., row direction). Based on a first pixel signal output from the first pixel (PX1) and a second pixel signal output from the second pixel (PX2), an AF function in a second direction (e.g., column direction) may be performed.

[0020] Alternatively, in an exemplary embodiment, a first pixel (PX1) and a second pixel (PX2) included in the same pixel group (PG) may be arranged side by side in a second direction. Based on a first pixel signal output from the first pixel (PX1) and a second pixel signal output from the second pixel (PX2), an AF function in the first direction may be performed. However, the image sensor (100) according to the present disclosure is not limited thereto, or in an exemplary embodiment, a first pixel (PX1) and a second pixel (PX2) included in the same pixel group (PG) may be arranged side by side in a direction between the first direction and the second direction (diagonal direction).

[0021] In an exemplary embodiment, each of the first pixel (PX1) and the second pixel (PX2) included in each of the pixel groups (PG) may be a phase detection pixel and may generate phase signals used to calculate the phase difference between images. The pixel groups (PG) may be used to focus on an object. The phase signals may include information regarding the positions of images formed on the image sensor (100), and the phase signals may be used to calculate the phase differences between images. Based on the calculated phase differences, the focal position of the lens of the electronic device equipped with the image sensor (100) may be calculated. For example, the position of the lens that makes the phase difference zero may be the focal position.

[0022] Pixel groups (PGs) can be used not only for focusing on an object but also for measuring the distance between the object and the image sensor (100). To measure the distance between the object and the image sensor (100), additional information such as phase differences between images formed on the image sensor (100), the distance between the lens and the image sensor (100), the size of the lens, and the focal position of the lens may be referenced.

[0023] The control unit (120) can control the row driver (140) so that the pixel array (110) absorbs light to accumulate photocharges, temporarily stores the accumulated photocharges, and outputs a pixel signal corresponding to the stored photocharges to the outside of the pixel array (110). Additionally, the control unit (120) can control the signal readout unit (150) to measure the level of the pixel signal provided by the pixel array (110).

[0024] The row driver (140) can generate signals (RSs, TSs, SELSs) for controlling the pixel array (110) and provide them to pixel groups (PG). In an exemplary embodiment, the row driver (140) can determine the activation and deactivation timing of the reset control signals (RSs), transmission control signals (TSs), and selection signals (SELSs) provided to the pixel groups (PG) based on whether to perform an AF function or a distance measurement function.

[0025] The CDS (151) can sample and hold the pixel signal provided by the pixel array (110). The CDS (151) can double-sample the level of a specific noise and the level corresponding to the pixel signal, and output a level corresponding to the difference. Additionally, the CDS (151) can receive a ramp signal generated by the ramp signal generator (157), compare them, and output a comparison result. The analog-to-digital converter (153) can convert the analog signal corresponding to the level received from the CDS (151) into a digital signal. The buffer (155) can latch the digital signal, and the latched signal can be sequentially output to the signal processing unit (130) or to the outside of the image sensor (100).

[0026] The signal processing unit (130) can perform signal processing based on pixel signals output from received pixel groups (PG). For example, the signal processing unit (130) can perform noise reduction processing, gain adjustment, waveform shaping processing, interpolation processing, white balance processing, gamma processing, edge enhancement processing, etc. Additionally, the signal processing unit (130) can output the signal-processed information to a processor of an electronic device including an image sensor during AF operation to perform phase difference calculations for AF operation. In an exemplary embodiment, the signal processing unit (130) may be provided in a processor outside the image sensor (100).

[0027] FIG. 2 is a circuit diagram of a pixel group (PG) included in the pixel array of FIG. 1. FIG. 2 shows two pixels included in one pixel group (PG), but one pixel group (PG) may include two or more pixels.

[0028] Referring to FIG. 2, a pixel group (PG) may include a first photoelectric conversion element (PD1), a second photoelectric conversion element (PD2), a first transfer transistor (TX1), a second transfer transistor (TX2), a reset transistor (RX), an amplifier transistor (SF), and a select transistor (SX). Unlike what is shown in FIG. 2, at least one of the reset transistor (RX), the amplifier transistor (SF), and the select transistor (SX) may be omitted.

[0029] The first photoelectric conversion element (PD1) and the second photoelectric conversion element (PD2) can generate photoelectric charges that vary according to the intensity of light. For example, the first photoelectric conversion element (PD1) and the second photoelectric conversion element (PD2) are PN junction diodes and can generate charges, namely electrons, which are negative charges, and holes, which are positive charges, in proportion to the amount of incident light. The first photoelectric conversion element (PD1) and the second photoelectric conversion element (PD2) may be at least one of a phototransistor, a photogate, a pinned photodiode (PPD), and combinations thereof, as examples of photoelectric conversion elements.

[0030] The first transmission transistor (TX1) can transmit photocharges generated in the first photoelectric conversion element (PD1) to the floating diffusion region (FD) according to the first transmission control signal (TS1), and the second transmission transistor (TX2) can transmit photocharges generated in the second photoelectric conversion element (PD2) to the floating diffusion region (FD) according to the second transmission control signal (TS2). When each of the first transmission transistors (TX1) and the second transmission transistor (TX2) is turned on, the photocharges generated in each of the first photoelectric conversion element (PD1) and the second photoelectric conversion element (PD2) can be transmitted to a single floating diffusion region (FD) and can be accumulated and stored in the floating diffusion region (FD).

[0031] The reset transistor (RX) can periodically reset the charges accumulated in the floating diffusion region (FD). The drain electrode of the reset transistor (RX) is connected to the floating diffusion region (FD), and the source electrode can be connected to the power supply voltage (VPIX). When the reset transistor (RX) is turned on according to the reset control signal (RS), the power supply voltage (VPIX) connected to the source electrode of the reset transistor (RX) is delivered to the floating diffusion region (FD). When the reset transistor (RX) is turned on, the charges accumulated in the floating diffusion region (FD) are discharged, and the floating diffusion region (FD) can be reset.

[0032] The amplification transistor (SF) can be controlled according to the amount of photocharges accumulated in the floating diffusion region (FD). The amplification transistor (SF) can act as a buffer amplifier to buffer signals based on the charges in the floating diffusion region (FD). The amplification transistor (SF) can amplify potential changes in the floating diffusion region (FD) and output them as a pixel signal (VOUT) to a column output line (one of CLO_0 to CLO_n-1).

[0033] The select transistor (SX) has its drain terminal connected to the source terminal of the amplifier transistor (SF) and can output a pixel signal (VOUT) to the CDS (151) through the column output line in response to the select signal (SELS).

[0034] A first pixel (PX1) may include a first photoelectric conversion element (PD1) and a first transfer transistor (TX1), and a second pixel (PX2) may include a second photoelectric conversion element (PD2) and a second transfer transistor (TX2). In an exemplary embodiment, the first pixel (PX1) and the second pixel (PX2) included in a single pixel group (PG) may share a floating diffusion region (FD) and may share at least one of a reset transistor (RX), an amplifier transistor (SF), and a select transistor (SX). However, this is merely an example, and other image sensors (100) of the present disclosure may have the first pixel (PX1) and the second pixel (PX2) each included in a single pixel group (PX) include a separate floating diffusion region (FD), a reset transistor (RX), an amplifier transistor (SF), and a select transistor (SX).

[0035] FIGS. 3a and 3b are drawings of a pixel group included in an image sensor according to an exemplary embodiment of the present disclosure, illustrating an example of a pixel group included in a pixel array of FIG. 1. FIGS. 4 and 5 are drawings of a pixel group of an image sensor according to an exemplary embodiment of the present disclosure, where FIG. 4 is a cross-sectional view II' of FIG. 3a and FIG. 5 is a cross-sectional view II-II' of FIG. 3a.

[0036] Referring to FIGS. 3a, 4 and 5, a pixel group (PG) may include a semiconductor substrate (100) having a first surface (101) and a second surface (102) opposite to each other, a first pixel region (PXR1) and a second pixel region (PXR2) formed on the semiconductor substrate (100), and a first device isolation layer (DTI1) formed to separate the pixel group (PG) from other pixel groups. Additionally, the pixel group (PG) may include a second device isolation layer (DTI2) to separate the first pixel region (PXR1) and the second pixel region (PXR2) from each other. The first pixel region (PXR1) refers to an area on the semiconductor substrate (100) where at least some components (e.g., photoelectric conversion element and transfer transistor) of the first pixel (e.g., PX1 of FIG. 1) included in the pixel group (PG) are formed, and the second pixel region (PXR2) refers to an area on the semiconductor substrate (100) where at least some components (e.g., photoelectric conversion element and transfer transistor) of the second pixel (e.g., PX2 of FIG. 1) included in the pixel group (PG) are formed.

[0037] The semiconductor substrate (100) may include at least one selected from, for example, Si, Ge, SiGe, SiC, GaAs, InAs, and InP. In an exemplary embodiment, the semiconductor substrate (210) may have a first conductivity type. For example, the first conductivity type may be p-type. A well region may be further formed within the semiconductor substrate (100), and the well region may be formed by doping the semiconductor substrate (100) with an impurity having the first conductivity type. The impurity concentration of the well region may have a value greater than the impurity concentration of the portion of the semiconductor substrate (100) other than the well region.

[0038] For example, the first surface (101) of the semiconductor substrate (100) may be the front surface of the semiconductor substrate (100), and the second surface (102) of the semiconductor substrate (100) may be the rear surface of the semiconductor substrate (100). Circuits may be arranged on the first surface (1001), and light may be incident on the second surface (102).

[0039] The first pixel area (PXR1) and the second pixel area (PXR2) may be arranged side by side in the first direction (X). In each of the first pixel area (PXR1) and the second pixel area (PXR2), one photoelectric conversion area (PCR1 or PCR2) may be formed. The photoelectric conversion areas (PCR1 or PCR2) may be arranged in a matrix form along the first direction (X) and the second direction (Y) within a pixel array (e.g., 110 in FIG. 1) in a planar view.

[0040] The first photoelectric conversion region (PCR1) and the second photoelectric conversion region (PCR2) may have a second conductivity type. For example, the second conductivity type may be n-type. In an exemplary embodiment, a first photoelectric conversion element (e.g., PD1 of FIG. 2) may be formed by a junction between a semiconductor substrate (100) of the first conductivity type and a first photoelectric conversion region (PCR1) of the second conductivity type, and a second photoelectric conversion element (e.g., PD2 of FIG. 2) may be formed by a junction between a semiconductor substrate (100) of the first conductivity type and a second photoelectric conversion region (PCR2) of the second conductivity type. However, not limited thereto, a first photoelectric conversion device (PD1) may be formed by the junction of a well region doped with a first conductivity type and a first photoelectric conversion region (PCR1) of a second conductivity type, or a second photoelectric conversion device (PD2) may be formed by the junction of a well region doped with a first conductivity type and a second photoelectric conversion region (PCR2) of a second conductivity type.

[0041] A first device isolation layer (DTI1) and a second device isolation layer (DTI2) may be formed within the semiconductor substrate (100). In an exemplary embodiment, the first device isolation layer (DTI1) and the second device isolation layer (DTI2) may be formed to extend vertically from a first surface (101) of the semiconductor substrate (100) toward a second surface (102). For example, the first width (W1) of one surface of the second device isolation layer (DTI2) in contact with the first surface (101) may be wider than the second width (W2) of the other surface of the second device isolation layer (DTI2) in contact with the second surface (102). Additionally, for example, the first width of one side of the first device isolation film (DTI1) in contact with the first surface (101) may be wider than the second width of the other side of the first device isolation film (DTI1) in contact with the second surface (102). However, the image sensor according to the present disclosure is not limited thereto, and in an exemplary embodiment, the first device isolation film (DTI1) and the second device isolation film (DTI2) may be formed to extend vertically from the first surface (101) of the semiconductor substrate (100) toward the second surface (102). The shape and manufacturing process of the first device isolation film (DTI1) and the second device isolation film (DTI2) may be configured in various ways.

[0042] The first device isolation layer (DTI1) and the second device isolation layer (DTI2) may be formed of an insulating material having a lower refractive index than the semiconductor substrate (100). For example, the first device isolation layer (DTI1) and the second device isolation layer (DTI2) may be made of undoped polysilicon, silicon oxide, silicon nitride, air, or a combination thereof. In an exemplary embodiment, the first device isolation layer (DTI1) and the second device isolation layer (DTI2) may be formed to include the same material.

[0043] The first device isolation layer (DTI1) and the second device isolation layer (DTI2) can refract incident light incident on the respective first pixel region (PXR1) and second pixel region (PXR2). The first device isolation layer (DTI1) and the second device isolation layer (DTI2) can prevent photocharges generated by the incident light from moving to adjacent pixel regions by random drift.

[0044] The first device isolation layer (DTI1) is formed to surround the first pixel region (PXR1) and the second pixel region (PXR2), thereby separating a pixel group (PG) from other pixel groups. That is, a single pixel group (PG) can be defined by the first device isolation layer (DTI1). The first device isolation layer (DTI1) can be extended in a first direction (X) or a second direction (Y) and formed in a grid shape.

[0045] The second device isolation layer (DTI2) may be formed to extend in a second direction (Y) between the first pixel area (PXR1) and the second pixel area (PXR2). However, this is exemplary, and the second device isolation layer (DTI2) may be formed to extend in a first direction (X) unlike that shown in FIG. 3a, and for example, the first device isolation layer (DTI1) and the second device isolation layer (DTI2) may be formed in a shape similar to that rotated 90 degrees based on the shape of the first device isolation layer (DTI1) and the second device isolation layer (DTI2) shown in FIG. 3a.

[0046] The second device isolation layer (DTI2) may include an open area (OP) that partially opens the space between the first pixel area (PXR1) and the second pixel area (PXR2). In this case, the open area (OP) may refer to an area where the second device isolation layer (DTI2) is not formed, and the width (OW) of the open area (OP) may be configured in various ways.

[0047] By including an open region (OP) in the second device isolation layer (DTI2), light scattering caused by the second device isolation layer (DTI2) can be reduced and the light receiving area within the pixel group (PG) can be increased. In an exemplary embodiment, the open region (OP) may be positioned in the center within the pixel group (PG). By forming the open region (OP) of the second device isolation layer (DTI2) in the central region where a large amount of light is incident on the pixel group (PG), the light receiving area can be increased.

[0048] In an exemplary embodiment, a floating diffusion region (FD) shared by the first pixel (PX1) and the second pixel (PX2) may be formed in the open region (OP) of the second device isolation film (DTI2).

[0049] A pixel group (PG) may include a passivation film (PL). The passivation film (PL) may be formed to surround a first device isolation film (DTI1) and a second device isolation film (DTI2). The passivation film (PL) may also be formed to surround a first pixel region (PXR1) and a second pixel region (PXR2). The passivation film (PL) may be disposed between the first pixel region (PXR1) and the second pixel region (PXR2). In an exemplary embodiment, the passivation film (PL) may include silicon doped with a first conductivity type, e.g., p-type.

[0050] A passivation film (PL) may also be formed in an open region (OP) of a second device isolation film (DTI2). In the open region (OP) of the second device isolation film (DTI2), the passivation film (PL) may be extended by a specific depth (PLD) in a vertical direction (Z) perpendicular to the semiconductor substrate (100) from the second surface (102) of the semiconductor substrate (100). The depth (PLD) of the passivation film (PL) in the open region (OP) may be shallower than the depth (PLD) of the passivation film (PL) in a region other than the open region (OP). A floating diffusion region (FD) included in a pixel group (PG) may be disposed below the passivation film (PL) in the open region (OP) (e.g., in the reverse direction of the Z direction).

[0051] The depth (PLD) of the passivation film (PL) formed in the open region (OP) of the second device isolation film (DTI2) can be varied in many ways. In an exemplary embodiment, the depth (PLD) of the passivation film (PL) can be reduced by implanting ions of a second conductivity type (n-type) opposite to the first conductivity type into the first surface (101) of the semiconductor substrate (100). Alternatively, in an exemplary embodiment, the depth (PLD) of the passivation film (PL) can be increased by implanting ions of the first conductivity type.

[0052] The passivation film (PL) can provide a potential barrier between the first photoelectric conversion region (PCR1) and the second photoelectric conversion region (PCR2) by having a conductivity type opposite to that of the first photoelectric conversion region (PCR1) and the second photoelectric conversion region (PCR2). That is, a potential well between the first photoelectric conversion region (PCR1) and the second photoelectric conversion region (PCR2) can be formed by the passivation film (PL), and the linearity of the full well of the first pixel (PX1) and the second pixel (PX2) can be improved.

[0053] A pixel group (PG) may include a first transfer transistor (TX1) and a second transfer transistor (TX2) formed to penetrate a semiconductor substrate (100). The first transfer transistor (TX1) and the second transfer transistor (TX2) may be vertical transistors. As the first transfer transistor (TX1) and the second transfer transistor (TX2) are each turned on, photocharges generated in the first photoelectric conversion region (PCR1) and the second photoelectric conversion region (PCR2), respectively, may be accumulated in the floating diffusion region (FD).

[0054] A color filter layer (CF) and a microlens (ML) may be disposed on the second surface (102) of the semiconductor substrate (100). A color filter layer (CF) may be disposed on the first pixel area (PXR1) and the second pixel area (PXR2) included in a pixel group (PG), and a microlens (ML) may be disposed.

[0055] The pixel array (110) may include a color filter layer (CF) so that pixel groups (PG) can sense various colors. In an exemplary embodiment, the color filter layer (CF) may be one of a filter that senses red (R), green (G), and blue (B), and the color filter layer (CF) may be arranged to correspond to a Bayer pattern. However, this is merely an exemplary embodiment, and the pixel array (110) according to an embodiment of the present disclosure may include various types of color filters, for example, the color filters may include filters for sensing yellow, cyan, and magenta colors.

[0056] A plurality of interlayer insulating films and wiring structures may be further included on the first surface (101) of the semiconductor substrate (100). The wiring structures may be wiring structures for connecting transistors constituting the first pixel (PX1) and the second pixel (PX2).

[0057] Referring to FIG. 3b, a ground contact (GND) for applying a ground voltage to the first pixel (PX1) and the second pixel (PX2) may be formed in the open region (OP) of the second device isolation layer (DTI2). For example, unlike as shown in FIG. 3a, FIG. 4, and FIG. 5, the first pixel (PX1) and the second pixel (PX2) included in the pixel group (PG') may each include a floating diffusion region that is separated from each other, without sharing a floating diffusion region (FD). A ground contact (GND) for applying a ground voltage to the first pixel (PX1) and the second pixel (PX2) may be formed in the open region (OP) of the second device isolation layer (DTI2).

[0058] Alternatively, unlike as illustrated in FIG. 3a and 3b, in an exemplary embodiment, at least one of the transistors shared by the first pixel (PX1) and the second pixel (PX2), such as a reset transistor (RX in FIG. 2), an amplifier transistor (SF in FIG. 2), and a select transistor (SX in FIG. 2), may be formed in the open region (OP) of the second device isolation layer (DTI2).

[0059] As illustrated in FIGS. 3a and 3b, at least one of a floating diffusion region (FD) included in a pixel group (PG'), transistors included in a pixel group (PG), and a ground contact applying a ground voltage to the pixel group (PG) may be disposed in the lower part of the passivation film (PL) in the open region (OP) (e.g., in the reverse direction of the Z direction).

[0060] FIG. 6 is a drawing of a pixel group included in an image sensor according to an exemplary embodiment of the present disclosure, illustrating an example of a pixel group included in the pixel array of FIG. 1. FIG. 7 is a drawing of a pixel group of an image sensor according to an exemplary embodiment of the present disclosure, FIG. 7 is a cross-sectional view taken along III-IIII' of FIG. 6. In the description of FIG. 6 and FIG. 7, redundant descriptions of reference numerals identical to those in FIG. 3a through FIG. 5 will be omitted.

[0061] Referring to FIGS. 6 and 7, a pixel group (PGa) may include a semiconductor substrate (100), a first pixel region (PXR1) and a second pixel region (PXR2) formed on the semiconductor substrate (100) and arranged parallel to each other in a first direction (X), and a first device isolation layer (DTI1) formed to separate the pixel group (PGa) from other pixel groups. Additionally, the pixel group (PGa) may include a second device isolation layer (DTI2a) to separate the first pixel region (PXR1) and the second pixel region (PXR2) from each other. The first pixel area (PXR1) refers to an area where at least a portion of the configuration of the first pixel (e.g., PX1 of FIG. 1) included in the pixel group (PGa) is formed on the substrate (100), and the second pixel area (PXR2) refers to an area where at least a portion of the configuration of the second pixel (e.g., PX2 of FIG. 1) included in the pixel group (PGa) is formed on the substrate (100).

[0062] The second device isolation layer (DTI2a) may include an open area (OPa) that partially exposes the space between the first pixel area (PXR1) and the second pixel area (PXR2). In an exemplary embodiment, at least one of a floating diffusion area (FD) shared by the first pixel (PX1) and the second pixel (PX2), transistors shared by the first pixel (PX1) and the second pixel (PX2), and a ground contact (GND) for applying a ground voltage to the first pixel (PX1) and the second pixel (PX2) may be formed in the open area (OPa). For example, the floating diffusion area (FD) shared by the first pixel (PX1) and the second pixel (PX2) and the ground contact (GND) may be formed in the open area (OPa).

[0063] The passivation film (PLa) may be formed to surround the first device isolation film (DTI1) and the second device isolation film (DTI2). In an exemplary embodiment, the passivation film (PLa) may include an open area (OPP) that partially exposes the space between the first pixel area (PXR1) and the second pixel area (PXR2). In this case, the open area (OPP) may refer to an area where the passivation film (PLa) is not formed.

[0064] The open region (OPP) of the passivation film (PLa) may overlap with the open region (OPa) of the second device isolation film (DTI2a). Accordingly, the first pixel region (PXR1) and the second pixel region (PXR2) may come into contact with each other at the open region (OPP) of the passivation film (PLa). However, the passivation film (PLa) included in the image sensor according to the present disclosure is not limited to that shown in FIG. 6, and the passivation film (PLa) may not include an open region (OPP) as described in the description of FIG. 5, and the passivation film (PLa) may be formed to surround the first pixel region (PXR1) and may be formed to surround the second pixel region (PXR2).

[0065] FIG. 8 is a drawing of a pixel group included in an image sensor according to an exemplary embodiment of the present disclosure, illustrating an example of a pixel group included in the pixel array of FIG. 1. In the description of FIG. 8, redundant descriptions of reference numerals identical to those in FIG. 3a through FIG. 5 will be omitted.

[0066] Referring to FIG. 8, a pixel group (PGb) may include a first pixel region (PXR1) and a second pixel region (PXR2) arranged parallel to each other in a first direction (X), and a first device isolation layer (DTI1) formed to separate the pixel group (PGb) from other pixel groups. Additionally, the pixel group (PGb) may include a second device isolation layer (DTI2b) to separate the first pixel region (PXR1) and the second pixel region (PXR2) from each other.

[0067] The second device isolation layer (DTI2b) may include an open area (OPb) that partially exposes the space between the first pixel area (PXR1) and the second pixel area (PXR2). The open area (OPb) may not be positioned at the center of the pixel group (PGb) but may be positioned at a location shifted from the center in the second direction (Y). The position of the open area (OPb) shown in FIG. 8 is for illustrative purposes only, and the position of the open area (OPb) may be varied.

[0068] In an exemplary embodiment, a floating diffusion region (FDb) included in a pixel group (PGb) may be formed in the open region (OPb). Or, in an exemplary embodiment, at least one of transistors included in the pixel group (PGb), such as a reset transistor (RX in FIG. 2), an amplifier transistor (SF in FIG. 2), and a select transistor (SX in FIG. 2), may be formed in the open region (OPb). Or, in an exemplary embodiment, a ground contact for applying a ground voltage to the pixel group (PGb) may be formed in the open region (OPb).

[0069] The pixel group (PGb) may further include a passivation film (PLb). The passivation film (PLb) may be formed to surround the first device isolation film (DTI1) and the second device isolation film (DTI2b). The passivation film (PLb) may include an open area that partially exposes the first pixel region (PXR1) and the second pixel region (PXR2), or the passivation film (PLb) may not include an open area and may be formed to surround the first pixel region (PXR1) and the second pixel region (PXR2).

[0070] FIG. 9 is a drawing of a pixel group included in an image sensor according to an exemplary embodiment of the present disclosure, illustrating an example of a pixel group included in the pixel array of FIG. 1. In the description of FIG. 9, redundant descriptions of reference numerals identical to those in FIG. 3a through FIG. 5 will be omitted.

[0071] Referring to FIG. 9, a pixel group (PGc) may include a first pixel region (PXR1) and a second pixel region (PXR2) arranged parallel to each other in a first direction (X), and a first device isolation layer (DTI1) formed to separate the pixel group (PGc) from other pixel groups. Additionally, the pixel group (PGc) may include a second device isolation layer (DTI2bc) to separate the first pixel region (PXR1) and the second pixel region (PXR2) from each other.

[0072] The second device isolation layer (DTI2bc) may include a plurality of open regions that partially expose the space between the first pixel region (PXR1) and the second pixel region (PXR2), for example, a first open region (OPc1) and a second open region (OPc2). The first open region (OPc1) and the second open region (OPc2) may be arranged side by side in the second direction (Y). Although FIG. 9 illustrates a second device isolation layer (DTI2bc) including two open regions (OPc1, OPc2), the present disclosure is not limited thereto, and the number of open regions formed in the second device isolation layer (DTI2bc) may be configured in various ways.

[0073] In an exemplary embodiment, at least one selected from a floating diffusion region (FDc) included in a pixel group (PGb), transistors included in the pixel group (PGb) (e.g., a reset transistor (RX in FIG. 2), an amplifier transistor (SF in FIG. 2), and a select transistor (SX in FIG. 2)), and a ground contact (GNDc) for applying a ground voltage to the pixel group (PGb) may be formed in each of the first open region (OPc1) and the second open region (OPc2). FIG. 9 illustrates an example in which a floating diffusion region (FDc) is formed in the first open region (OPc1) and a ground contact (GNDc) is formed in the second open region (OPc2), but this is for illustrative purposes only and the image sensor according to the present disclosure is not limited thereto.

[0074] The pixel group (PGc) may further include a passivation film (PLc). The passivation film (PLc) may be formed to surround the first device isolation film (DTI1) and the second device isolation film (DTI2bc). In an exemplary embodiment, the passivation film (PLc) may include an open area that partially exposes the first pixel region (PXR1) and the second pixel region (PXR2), and may include at least one open area that overlaps, for example, the first open area (OPc1) and the second open area (OPc2) of the second device isolation film (DTI2bc), respectively. Alternatively, in an exemplary embodiment, the passivation film (PLc) may not include an open area and may be formed to extend continuously in the second direction (Y) and abut the first device isolation film (DTI1) at both ends.

[0075] FIG. 10 is a drawing of a pixel group included in an image sensor according to an exemplary embodiment of the present disclosure, illustrating an example of a pixel group included in the pixel array of FIG. 1. In the description of FIG. 10, redundant descriptions of reference numerals identical to those in FIG. 3a through FIG. 5 will be omitted.

[0076] Referring to FIG. 10, a pixel group (PGd) may include a first pixel area (PXR1d) and a second pixel area (PXR2d) separated from each other in a diagonal axis direction (XY) tilted at a certain angle from a first direction (X) and a second direction (Y). In an exemplary embodiment, the first pixel area (PXR1d) and the second pixel area (PXR2d) may be formed symmetrically with respect to each other in the diagonal axis direction (XY). Based on a first pixel signal and a second pixel signal according to photocharges formed in each of the first pixel area (PXR1d) and the second pixel area (PXR2d) of the pixel group (PGd), an AF function in a direction perpendicular to the diagonal axis direction (XY) may be performed.

[0077] A pixel group (PGd) may include a first device isolation layer (DTI1) formed to separate the pixel group (PGd) from other pixel groups. The first device isolation layer (DTI1) may have a grid pattern extending in each of the first direction (X) and the second direction (Y) in a plane formed by the first direction (X) and the second direction (Y).

[0078] A pixel group (PGd) may include a second device isolation layer (DTI2d) for separating a first pixel region (PXR1d) and a second pixel region (PXR2d) from each other. The second device isolation layer (DTI2d) is disposed between the first pixel region (PXR1d) and the second pixel region (PXR2d), and the second device isolation layer (DTI2d) may be formed to extend in the diagonal axis direction (XY).

[0079] The second device isolation layer (DTI2d) may include an open area (OPd) that partially exposes the space between the first pixel area (PXR1d) and the second pixel area (PXR2d). In an exemplary embodiment, the open area (OPd) may be positioned at the center of the pixel group (PGd). However, it is not limited thereto, and the open area (OPd) may be positioned at a location moved along the diagonal axis direction (XY) from the center.

[0080] In an exemplary embodiment, at least one of a floating diffusion region (FDd) included in a pixel group (PGd), transistors included in a pixel group (PGb), and a ground contact for applying a ground voltage to the pixel group (PGb) may be formed in the open region (OPd).

[0081] A pixel group (PGd) may further include a passivation film (PLd). The passivation film (PLd) may be formed to surround a first device isolation film (DTI1) and a second device isolation film (DTI2d). The passivation film (PLd) may include an open area that partially exposes the first pixel region (PXR1d) and the second pixel region (PXR2d), or the passivation film (PLd) may not include an open area and may be formed to extend continuously along the diagonal axis direction (XY) to abut the first device isolation film (DTI1) at both ends.

[0082] FIGS. 11a and 11b are drawings of a pixel group included in an image sensor according to an exemplary embodiment of the present disclosure, illustrating an example of a pixel group included in the pixel array of FIG. 1. In the description of FIGS. 11a and 11b, redundant descriptions of reference numerals identical to those in FIGS. 3a through 5 will be omitted.

[0083] Referring to FIG. 11a, a pixel group (PGe) may include first to fourth pixel regions (PXR1e to PXR4e) and a first device isolation layer (DTI1) formed to separate the pixel group (PGe) from other pixel groups. Additionally, the pixel group (PGe) may include a second device isolation layer (DTI2e) to separate each of the first to fourth pixel regions (PXR1e to PXR4e) from one another.

[0084] Each of the first to fourth pixel regions (PXR1e~PXR4e) may mean a region in which at least a portion of the configurations of the first to fourth pixels included in the pixel group (PGe) are formed on a semiconductor substrate, and, for example, may mean a region in which each of the photoelectric conversion elements included in the first to fourth pixels is formed and transfer transistors are formed.

[0085] In an exemplary embodiment, the same color filter may be disposed on the first to fourth pixels included in the pixel group (PGe), and a single microlens may be disposed. Additionally, in an exemplary embodiment, the first to fourth pixels included in the pixel group (PGe) may share at least one of a floating diffusion region (FDe), a reset transistor (RX in FIG. 2), an amplification transistor (SF in FIG. 2), and a selection transistor (SX in FIG. 2). However, the image sensor according to the present disclosure is not limited thereto, and the first to fourth pixels included in the pixel group (PGe) may each individually include a floating diffusion region, a reset transistor (RX), an amplification transistor (SF), and a selection transistor (SX).

[0086] The first pixel area (PXR1e) and the second pixel area (PXR2e) may be arranged side by side in the first direction (X), and the third pixel area (PXR3e) and the fourth pixel area (PXR4e) may be arranged side by side in the first direction (X). The first pixel area (PXR1e) and the third pixel area (PXR3e) may be arranged side by side in the second direction (Y) which is perpendicular to the first direction (X), and the second pixel area (PXR2e) and the fourth pixel area (PXR4e) may be arranged side by side in the second direction (Y). Accordingly, an AF function in the second direction (Y) can be performed based on pixel signals corresponding to photocharges formed in each of the first pixel area (PXR1e) and the second pixel area (PXR2e), and an AF function in the first direction (X) can be performed based on pixel signals corresponding to photocharges formed in each of the first pixel area (PXR1e) and the third pixel area (PXR3e).

[0087] The second device isolation layer (DTI2e) may be formed to extend in a second direction (Y) between the first pixel area (PXR1e) and the second pixel area (PXR2e), and may be formed to extend in a second direction (Y) between the third pixel area (PXR3e) and the fourth pixel area (PXR4e). Additionally, the second device isolation layer (DTI2e) may be formed to extend in a first direction (X) between the first pixel area (PXR1e) and the third pixel area (PXR3e), and may be formed to extend in a first direction (X) between the second pixel area (PXR2e) and the fourth pixel area (PXR4e).

[0088] The second device isolation layer (DTI2e) may include at least one open area (OPe) that partially exposes the space between the first pixel area (PXR1e) and the second pixel area (PXR2e), and partially exposes the space between the third pixel area (PXR3e) and the fourth pixel area (PXR4e). Additionally, the second device isolation layer (DTI2e) may include at least one open area (OPe) that partially exposes the space between the first pixel area (PXR1e) and the third pixel area (PXR3e), and partially exposes the space between the third pixel area (PXR3e) and the fourth pixel area (PXR4e). In an exemplary embodiment, at least one open area (OPe) may be positioned at the center of a pixel group (PGe).

[0089] In an exemplary embodiment, a floating diffusion region (FDe) included in a pixel group (PGe) may be formed in an open region (OPe). For example, if the first to fourth pixels included in the pixel group (PGe) share a single floating diffusion region (FDe), the floating diffusion region (FDe) may be placed in the open region (OPe).

[0090] A pixel group (PGe) may further include a passivation film (PLe). The passivation film (PLe) may be formed to surround a first device isolation film (DTI1) and a second device isolation film (DTI2e). The passivation film (PLe) may include an open area that partially exposes each of the first to fourth pixel regions (PXR1e to PXR4e), or the passivation film (PLe) may be formed to extend continuously along a first direction (X) or a second direction (Y) without including an open area, so as to be in contact with the first device isolation film (DTI1) at both ends.

[0091] Referring to FIG. 11b, a ground contact (GNDe) for applying a ground voltage to a pixel group (PGe') may be formed in an open area (OPe). The ground voltage applied through the ground contact (GND) may be applied to the first to fourth pixels formed in each of the first to fourth pixel areas (PXR1e~PXR4e).

[0092] Referring to FIG. 11a and FIG. 11b, in an exemplary embodiment, at least one of a floating diffusion region (FDe) included in a pixel group (PGe, PGe'), transistors included in the pixel group (PGe), and a ground contact (GNDe) for applying a ground voltage to the pixel group (PGe) may be formed in the open region (OPe).

[0093] FIG. 12 is a drawing of a pixel group included in an image sensor according to an exemplary embodiment of the present disclosure, illustrating an example of a pixel group included in the pixel array of FIG. 1. FIG. 13 is a drawing of a pixel group of an image sensor according to an exemplary embodiment of the present disclosure, FIG. 13 is a cross-sectional view taken along IV-IV' of FIG. 12. In the description of FIG. 12 and FIG. 13, redundant descriptions of reference numerals identical to those in FIG. 3a through FIG. 5 will be omitted.

[0094] Referring to FIGS. 12 and 13, a pixel group (PGf) may include a semiconductor substrate (100), a first pixel region (PXR1) and a second pixel region (PXR2) formed on the semiconductor substrate (100) and arranged parallel to each other in a first direction (X), and a first device isolation layer (DTI1) formed to separate the pixel group (PGf) from other pixel groups. Additionally, the pixel group (PGf) may include a second device isolation layer (DTI2) to separate the first pixel region (PXR1) and the second pixel region (PXR2) from each other.

[0095] A third device isolation layer (DTI3) may be formed in the open region (OP) of the second device isolation layer (DTI2). In an exemplary embodiment, the third device isolation layer (DTI3) may be in contact with the second device isolation layer (DTI2).

[0096] The third device isolation layer (DTI3) may be formed to extend in a vertical direction (Z) from the second surface (102) of the semiconductor substrate (100) toward the first surface (101). The third device isolation layer (DTI3) may be spaced apart from the first surface (101). In an exemplary embodiment, the width of the third device isolation layer (DTI3) may decrease as it moves away from the second surface (102).

[0097] The third device isolation layer (DTI3) may be formed of an insulating material having a lower refractive index than the semiconductor substrate (100). For example, the first device isolation layer (DTI1) and the second device isolation layer (DTI2) may be made of undoped polysilicon, silicon oxide, silicon nitride, air, or a combination thereof. In an exemplary embodiment, the third device isolation layer (DTI3) may be formed to include the same material as the first device isolation layer (DTI1) and the second device isolation layer (DTI2).

[0098] In an exemplary embodiment, the first device isolation layer (DTI1) and the second device isolation layer (DTI2) are in contact with the first surface (101) and the second surface (102), respectively, while the third device isolation layer (DTI3) may not be in contact with the first surface (101). That is, the depth to which the third device isolation layer (DTI3) extends in the vertical direction (Z) from the second surface (102) may be shallower than the depth to which the first device isolation layer (DTI1) and the second device isolation layer (DTI2) each extend from the second surface (102). A passivation layer (PLf) may be disposed on the lower side of the third device isolation layer (DTI3) (e.g., in the reverse direction of the Z direction). The linearity of the full well of the first pixel (PX1) and the second pixel (PX2) may be improved by the passivation layer (PLf) in the open area (OP).

[0099] A passivation film (PLf) may also be formed in an open region (OP) of a second device isolation film (DTI2). In the open region (OP) of the second device isolation film (DTI2), the passivation film (PLf) may be extended to a specific depth in a direction (Z) perpendicular to the semiconductor substrate (100) from the second surface (102) of the semiconductor substrate (100). In the open region (OP), at least one of a floating diffusion region (FD) included in a pixel group (PGf), transistors included in a pixel group (PGf), and a ground contact that applies a ground voltage to the pixel group (PGf) may be disposed below the passivation film (PLf) and the third device isolation film (DTI3).

[0100] The passivation film (PLf) may be formed to surround the first to third device isolation films (DTI1 to DTI3). In an exemplary embodiment, the passivation film (PLf) may include an open area that partially exposes the first pixel region (PXR1) and the second pixel region (PXR2), and, for example, may include an open area that overlaps with the open area (OP) of the second device isolation film (DTI2). Alternatively, in an exemplary embodiment, the passivation film (PLf) may not include an open area and may be formed to extend continuously in the second direction (Y) so as to be in contact with the first device isolation film (DTI1) at both ends.

[0101] FIG. 14 is a drawing of a pixel group included in an image sensor according to an exemplary embodiment of the present disclosure, illustrating an example of a pixel group included in the pixel array of FIG. 1. FIG. 15 is a drawing of a pixel group of an image sensor according to an exemplary embodiment of the present disclosure, FIG. 15 is a cross-sectional view of VV' of FIG. 13. In the description of FIG. 14 and FIG. 15, redundant descriptions of reference numerals identical to those in FIG. 3a through FIG. 5 will be omitted.

[0102] Referring to FIGS. 14 and 15, a doping region (DL) may be formed in the open region (OP) of the second device isolation film (DTI2) of the pixel group (PGg). The doping region (DL) may be formed by implanting a first conductivity type, e.g., p-type ion, into the semiconductor substrate (100) after forming a trench, and subsequently, a passivation film (PLg) and a second device isolation film (DTI2) may be formed in sequence in the trench. The doping region (DL) may be positioned closer to the second surface (102) than to the first surface (101) of the semiconductor substrate (100).

[0103] The doping region (DL) may contain doped silicon. The doping concentration in the doping region (DL) may be higher than the doping concentration in the passivation membrane (PLg).

[0104] The passivation film (PLg) may be formed to surround the first device isolation film (DTI1) and the second device isolation film. The passivation film (PLg) may also be formed in the open region (OP) of the second device isolation film (DTI2) and may be positioned below the doping region (DL) (e.g., in the reverse direction of the vertical direction (Z)).

[0105] FIG. 16 is a block diagram of an electronic device including a multi-camera module. FIG. 17 is a detailed block diagram of the camera module of FIG. 16. FIG. 17 describes the detailed configuration of the camera module (1100b), but the following description may be applied equally to other camera modules (1100a, 1100b) according to the embodiment.

[0106] Referring to FIG. 16, the electronic device (1000) may include a camera module group (1100), an application processor (1200), a PMIC (1300), and an external memory (1400). The camera module group (1100) may include a plurality of camera modules (1100a, 1100b, 1100c). Although an embodiment in which three camera modules (1100a, 1100b, 1100c) are arranged is shown in the drawing, the embodiments are not limited thereto.

[0107] Referring to FIGS. 16 and 17, the camera module (1100b) may include a prism (1105), an optical path folding element (OPFE, hereinafter referred to as "OPFE") (1110), an actuator (1130), an image sensing device (1140), and a storage unit (1150).

[0108] The prism (1105) may modify the path of light (L) incident from the outside by including a reflective surface (1107) of a light-reflecting material. The OPFE (1110) may include, for example, groups of m (where m is a natural number) optical lenses. The actuator (1130) may move the OPFE (1110) or the optical lenses (hereinafter referred to as optical lenses) to a specific position.

[0109] The image sensing device (1140) may include an image sensor (1142), control logic (1144), and memory (1146). The image sensor (1142) may sense an image of a sensing target using light (L) provided through an optical lens. The image sensor (1142) may be an image sensor comprising at least one of the pixel groups (PG, PG', PGa, PGb, PGc, PGd, PGe, PGe', PGf, PGg) described in FIGS. 1 to 15.

[0110] The control logic (1144) can control the overall operation of the camera module (1100b). For example, the control logic (1144) can control the operation of the camera module (1100b) according to a control signal provided through the control signal line (CSLb).

[0111] In an exemplary embodiment, one of the plurality of camera modules (1100a, 1100b, 1100c) camera module (e.g., 1100b) is a camera module in the form of a folded lens including the previously described prism (1105) and OPFE (1110), and the remaining camera modules (e.g., 1100a, 1100b) may be camera modules in the form of a vertical camera module that do not include the prism (1105) and OPFE (1110), but the embodiments are not limited thereto.

[0112] In an exemplary embodiment, one of the plurality of camera modules (1100a, 1100b, 1100c) (e.g., 1100c) may be a vertical depth camera that extracts depth information using, for example, IR (Infrared Ray). In this case, the application processor (1200) may generate a 3D depth image by merging image data provided from this depth camera with image data provided from another camera module (e.g., 1100a or 1100b).

[0113] In an exemplary embodiment, at least two of the plurality of camera modules (1100a, 1100b, 1100c) may have different field of view angles. In this case, for example, the optical lenses of at least two of the plurality of camera modules (1100a, 1100b, 1100c) may be different from each other, but are not limited thereto.

[0114] In addition, in an exemplary embodiment, the viewing angles of each of the plurality of camera modules (1100a, 1100b, 1100c) may differ from one another. In this case, the optical lenses included in each of the plurality of camera modules (1100a, 1100b, 1100c) may also differ from one another, but are not limited thereto.

[0115] In an exemplary embodiment, each of the plurality of camera modules (1100a, 1100b, 1100c) may be physically separated from one another. That is, instead of the plurality of camera modules (1100a, 1100b, 1100c) dividing and using the sensing area of ​​a single image sensor (1142), an independent image sensor (1142) may be placed inside each of the plurality of camera modules (1100a, 1100b, 1100c).

[0116] Referring again to FIG. 16, the application processor (1200) may include an image processing device (1210), a memory controller (1220), and an internal memory (1230). The application processor (1200) may be implemented separately from a plurality of camera modules (1100a, 1100b, 1100c). For example, the application processor (1200) and the plurality of camera modules (1100a, 1100b, 1100c) may be implemented separately from each other as separate semiconductor chips.

[0117] The image processing device (1210) may include a plurality of sub-image processors (1212a, 1212b, 1212c), an image generator (1214), and a camera module controller (1216).

[0118] The image processing device (1210) may include a plurality of sub-image processors (1212a, 1212b, 1212c) corresponding to the number of camera modules (1100a, 1100b, 1100c).

[0119] Image data generated from each camera module (1100a, 1100b, 1100c) can be provided to corresponding sub-image processors (1212a, 1212b, 1212c) via separate image signal lines (ISLa, ISLb, ISLc). For example, image data generated from camera module (1100a) can be provided to sub-image processor (1212a) via image signal line (ISLa), image data generated from camera module (1100b) can be provided to sub-image processor (1212b) via image signal line (ISLb), and image data generated from camera module (1100c) can be provided to sub-image processor (1212c) via image signal line (ISLc). Such image data transmission can be performed, for example, using a Camera Serial Interface (CSI) based on MIPI (Mobile Industry Processor Interface), but the embodiments are not limited thereto.

[0120] Image data provided to each sub-image processor (1212a, 1212b, 1212c) may be provided to an image generator (1214). The image generator (1214) may generate an output image using image data provided from each sub-image processor (1212a, 1212b, 1212c) according to image generating information or a mode signal.

[0121] Specifically, the image generator (1214) can generate an output image by merging at least some of the image data generated from camera modules (1100a, 1100b, 1100c) having different viewing angles according to image generation information or a mode signal. Additionally, the image generator (1214) can generate an output image by selecting any one of the image data generated from camera modules (1100a, 1100b, 1100c) having different viewing angles according to image generation information or a mode signal.

[0122] The camera module controller (1216) can provide control signals to each camera module (1100a, 1100b, 1100c). The control signals generated from the camera module controller (1216) can be provided to the corresponding camera modules (1100a, 1100b, 1100c) through separate control signal lines (CSLa, CSLb, CSLc).

[0123] The application processor (1200) stores the received image signal, that is, the encoded image signal, in a memory (1230) provided internally or in a storage (1400) outside the application processor (1200), and subsequently reads the encoded image signal from the memory (1230) or the storage (1400) to decode it, and can display image data generated based on the decoded image signal. For example, a corresponding sub-processor among a plurality of sub-processors (1212a, 1212b, 1212c) of the image processing device (1210) can perform decoding and can also perform image processing on the decoded image signal.

[0124] The PMIC (1300) can supply power, for example, power voltage, to each of the plurality of camera modules (1100a, 1100b, 1100c). For example, the PMIC (1300) can supply first power to the camera module (1100a) through a power signal line (PSLa), supply second power to the camera module (1100b) through a power signal line (PSLb), and supply third power to the camera module (1100c) through a power signal line (PSLc), under the control of the application processor (1200).

[0125] Up to this point, the present invention has been described with reference to the embodiments illustrated in the drawings, but this is merely illustrative, and those skilled in the art will understand that various modifications and equivalent alternative embodiments are possible therefrom. Accordingly, the true technical scope of protection of the present invention should be determined by the technical spirit of the appended claims.

Claims

Claim 1 An image sensor comprising: a first pixel region and a second pixel region formed inside a semiconductor substrate and each forming a photoelectric conversion element; a first element isolation layer formed to completely surround the first pixel region and the second pixel region; a second element isolation layer formed between the first pixel region and the second pixel region; a passivation layer formed to surround the first element isolation layer and the second element isolation layer; and a single microlens disposed on the first pixel region and the second pixel region, wherein the second element isolation layer includes at least one first open region that opens a portion between the first pixel region and the second pixel region, and a portion of the passivation layer is formed in the first open region. Claim 2 delete Claim 3 delete Claim 4 An image sensor according to claim 1, wherein the passivation film comprises a second open region that opens a portion between the first pixel region and the second pixel region. Claim 5 An image sensor according to claim 1, wherein the passivation film comprises silicon doped with P-type impurities. Claim 6 An image sensor according to claim 1, wherein at least one of a floating diffusion region in which photocharge is accumulated, a ground contact to which a ground voltage is applied, a reset transistor for resetting the photocharge accumulated in the floating diffusion region, an amplification transistor for amplifying a signal according to the photocharge accumulated in the floating diffusion region, and a selection transistor connected to the amplification transistor for outputting a pixel signal is formed in the first open region. Claim 7 An image sensor according to claim 1, characterized in that the first open region is positioned in the center of the region surrounded by the first element isolation film. Claim 8 An image sensor according to claim 1, wherein the second element isolation layer comprises a plurality of first open regions that open a portion between the first pixel region and the second pixel region. Claim 9 An image sensor according to claim 1, wherein the first element separator has a grid shape extending in a first direction and a second direction perpendicular to the first direction, and the second element separator extends in a direction inclined at a certain angle from the first direction and the second direction. Claim 10 An image sensor according to claim 1, further comprising a third pixel region and a fourth pixel region formed inside the substrate and each forming a photoelectric conversion element, wherein the microlens is disposed on the third pixel region and the fourth pixel region, the first element isolation layer is formed to surround the third pixel region and the fourth pixel region, the second element isolation layer is disposed between the third pixel region and the fourth pixel region, and the first open region opens a portion of the first to fourth pixel regions. Claim 11 An image sensor comprising: a semiconductor substrate having a first surface and a second surface facing the first surface; a first pixel region and a second pixel region formed inside the semiconductor substrate and each forming a photoelectric conversion element; a first element isolation film formed to completely surround the first pixel region and the second pixel region; a second element isolation film formed between the first pixel region and the second pixel region; and a passivation film formed to surround the first element isolation film and the second element isolation film, wherein the first element isolation film and the second element isolation film are formed to extend from the first surface to the second surface, and the second element isolation film includes a first open region that opens a portion between the first pixel region and the second pixel region, and a portion of the passivation film is formed in the first open region. Claim 12 delete Claim 13 delete Claim 14 An image sensor according to claim 11, wherein the passivation film comprises a second open region that opens a portion between the first pixel region and the second pixel region. Claim 15 An image sensor according to claim 11, wherein at least one of a floating diffusion region in which photocharge is accumulated, a ground contact to which a ground voltage is applied, a reset transistor for resetting the photocharge accumulated in the floating diffusion region, an amplification transistor for amplifying a signal according to the photocharge accumulated in the floating diffusion region, and a selection transistor connected to the amplification transistor for outputting a pixel signal is formed in the first open region. Claim 16 An image sensor according to claim 11, wherein a third element isolation film is formed in the first open region, extending from the second surface and spaced apart from the first surface, and the passivation film is formed to surround the third element isolation film. Claim 17 An image sensor according to claim 11, wherein a doping region doped with P-type impurities is formed in the first open region, and the doping region is positioned closer to the second surface than to the first surface. Claim 18 An image sensor comprising: a first pixel region and a second pixel region formed inside a semiconductor substrate and each forming a photoelectric conversion element; a first element isolation layer formed to completely surround the first pixel region and the second pixel region; a second element isolation layer formed between the first pixel region and the second pixel region; and a floating diffusion region for accumulating photoelectric charges formed from the photoelectric conversion elements formed in the first pixel region and the second pixel region, wherein the second element isolation layer includes an open region that opens a portion between the first pixel region and the second pixel region, and a ground contact that provides a ground voltage to the first pixel region and the second pixel region is disposed in the open region. Claim 19 An image sensor according to claim 18, characterized in that the floating diffusion region is disposed in the open region. Claim 20 delete

Images