Semiconductor device having heat insulating layer

Abstract

A semiconductor device according to one aspect of the present disclosure comprises a substrate, a device pattern structure disposed on top of the substrate, and a heat insulating layer disposed on the device pattern structure and comprising a metal-organic framework.

Description

Technology Field

[0001] The present disclosure relates to a semiconductor device having an insulating layer. Background Technology

[0002] A phase change memory device is a non-volatile memory device that utilizes the physical property of a phase change layer changing its crystal state due to heat applied to the phase change layer for storing signal information. Specifically, in the phase change memory device, the crystal state of the phase change layer can reversibly change between an amorphous state and a crystalline state due to heat generated in the phase change layer when an external voltage is applied. At this time, since the electrical resistance of the phase change layer is distinguishable from the amorphous state and the crystalline state, the crystal state information of the phase change layer can be applied as signal information.

[0003] As described above, since the operation of changing the crystal state of the phase change layer corresponds to the recording operation of the phase change memory device, whether the heat of the phase change layer is effectively controlled may be related to the operational reliability of the phase change memory device. The problem to be solved

[0004] One embodiment of the present disclosure provides a semiconductor device that improves the operational reliability of a device pattern structure. means of solving the problem

[0005] A semiconductor device according to one aspect of the present disclosure comprises a substrate, a device pattern structure disposed on top of the substrate, and a heat insulating layer disposed on the device pattern structure and comprising a metal-organic framework.

[0006] A semiconductor device according to another aspect of the present disclosure comprises: a substrate; and a plurality of unit cells spaced apart from each other on the substrate. Each of the plurality of unit cells comprises a device pattern structure extending in a direction perpendicular to the surface of the substrate and comprising a phase change layer, and an insulating layer disposed on the device pattern structure and comprising a metal-organic structure.

[0007] In a method for manufacturing a semiconductor device according to another aspect of the present disclosure, a substrate is prepared. A device structure is formed comprising a first electrode material layer, a phase change material layer, and a second electrode material layer sequentially disposed on the upper surface of the substrate. The device structure is optionally etched to form a device pattern structure having a first electrode layer, a phase change layer, and a second electrode layer on the upper surface of the substrate. An insulating layer comprising a metal-organic structure is formed on the device pattern structure on the upper surface of the substrate. Effects of the invention

[0008] In a semiconductor device according to one embodiment of the present disclosure described above, heat can be effectively preserved within a device pattern structure by means of an insulating layer. Accordingly, the efficiency of the write operation can be improved by increasing the thermal efficiency during a write operation on the device pattern structure. In addition, the operational reliability of the semiconductor device can be improved by blocking the propagation of heat generated in one unit cell to an adjacent unit cell by means of the insulating layer. Brief explanation of the drawing

[0009] FIG. 1 is a plan view schematically showing a semiconductor device according to one embodiment of the present disclosure. Figure 2 is a cross-sectional view of the semiconductor device of Figure 1 taken along I-I'. FIG. 3 is a cross-sectional view of the semiconductor device of FIG. 1 taken along II-II'. FIG. 4a is a schematic diagram showing a metal-organic structure of an insulating layer according to one embodiment of the present disclosure. Figure 4b is a schematic diagram showing the stacked form of the metal-organic structure of Figure 4a. FIG. 5 is a cross-sectional view schematically illustrating a semiconductor device according to another embodiment of the present disclosure. FIGS. 6a to 10a are plan views schematically illustrating a method for manufacturing a semiconductor device according to one embodiment of the present disclosure. FIGS. 6b to 10b are cross-sectional views of the semiconductor devices of FIGS. 6a to 10a taken along A-A', respectively. FIGS. 6c to 10c are cross-sectional views of the semiconductor devices of FIGS. 6a to 10a taken along B-B', respectively. Specific details for implementing the invention

[0010] Hereinafter, embodiments of the present application will be described in more detail with reference to the attached drawings. In the drawings, the dimensions, such as the width or thickness of the components of each device, are shown slightly enlarged to clearly represent the components. When one element is described as being positioned above another element, this includes both the meaning that the one element is positioned directly above the other element and that an additional element may be interposed between the elements. In a plurality of drawings, the same reference numerals refer to substantially identical elements.

[0011] Furthermore, singular expressions should be understood to include plural expressions unless the context clearly indicates otherwise, and terms such as 'include' or 'have' are intended to specify the existence of the described features, numbers, steps, actions, components, parts, or combinations thereof, and should not be understood as precluding the existence or addition of one or more other features, numbers, steps, actions, components, parts, or combinations thereof.

[0012] In carrying out the method, each process constituting the method may occur differently from the specified order unless a specific order is clearly indicated in the context. That is, each process may occur in the same order as specified, may be performed substantially simultaneously, or may be performed in the reverse order.

[0013] In this specification, "a predetermined direction" may encompass a direction parallel to a predetermined direction in a coordinate system. For example, in an xyz coordinate system, the x-direction may mean a direction parallel to the x-axis. That is, it may mean both a direction proceeding in a positive direction along the x-axis from a predetermined starting point and a direction proceeding in a negative direction along the x-axis from said predetermined starting point. The y-direction and the z-direction may also be interpreted as directions in the xyz coordinate system in substantially the same way.

[0014] FIG. 1 is a plan view schematically showing a semiconductor device according to one embodiment of the present disclosure. FIG. 2 is a cross-sectional view taken along I-I' of the semiconductor device of FIG. 1. FIG. 3 is a cross-sectional view taken along II-II' of the semiconductor device of FIG. 1. FIG. 4a is a diagram schematically showing a metal-organic structure of an insulating layer according to one embodiment of the present disclosure. FIG. 4b is a diagram schematically showing a stacked form of the metal-organic structure of FIG. 4a.

[0015] Referring to FIGS. 1 to 3, the semiconductor device (1) may include a plurality of unit cells (UC1, UC2, UC3, UC4) disposed on a substrate (101). Each of the plurality of unit cells (UC1, UC2, UC3, UC4) may include a device pattern structure (20) disposed on the upper surface of the substrate (101) and an insulating layer (210) disposed on the side wall surface of the device pattern structure (20). The device pattern structure (20) may include a first electrode layer (135), a selection element layer (145), a second electrode layer (155), a phase change layer (165), and a third electrode layer (175).

[0016] Additionally, each of the plurality of unit cells (UC1, UC2, UC3, UC4) may include a lower contact structure (10) disposed between the substrate (10) and the device pattern structure (20). Additionally, each of the plurality of unit cells (UC1, UC2, UC3, UC4) may include an upper contact structure (30) disposed on the upper side of the device pattern structure (20). Meanwhile, in FIGS. 1 to 3, first to fourth unit cells (UC1, UC2, UC3, UC4) are illustrated as an example of a plurality of unit cells, but the inventive concept of the present disclosure is not necessarily limited thereto, and various other numbers of unit cells are possible.

[0017] The substrate (101) may include a semiconductor material. Specifically, the semiconductor material may include, as an example, silicon, germanium, gallium arsenide, molybdenum sulfide (MoS2), molybdenum selenide (MoSe2), hafnium selenide (HfSe2), indium selenide (InSe), gallium selenide (GaSe), black phosphous, indium-gallium-zinc oxide (IGZO), or a combination of two or more of these. Although not illustrated, the substrate (101) may include an integrated circuit. The integrated circuit may be a circuit that drives and controls unit cells (UC1, UC2, UC3, UC4). The integrated circuit may include, as an example, components such as diodes and transistors.

[0018] The lower contact structure (10) may include a lower contact pattern (115) disposed on a substrate (101) and a lower bonding layer (125) disposed on the lower contact pattern (115). The lower contact pattern (115) may be a rectangular column-shaped structure having a predetermined width (W) in a first direction (e.g., x-direction), a predetermined length (L) in a second direction (e.g., y-direction), and a predetermined thickness (not shown) in a third direction (e.g., z-direction).

[0019] The lower contact pattern (115) can be electrically connected to the substrate (101). The lower contact pattern (115) may include a conductive material. The conductive material may include, as an example, doped silicon, tungsten, tungsten silicide, tungsten nitride, titanium nitride, tantalum nitride, or a combination of two or more of these.

[0020] The lower bonding layer (125) can function as an adhesive layer between the lower contact pattern (115) and the device pattern structure (20). Specifically, it can improve the adhesion between the lower contact pattern (115) and the first electrode layer (135) of the device pattern structure (20). The lower bonding layer (125) may have a predetermined width (W) in a first direction (e.g., x-direction) and a predetermined length (L) in a second direction (e.g., y-direction). The lower bonding layer (125) may include a metal silicide, as an example. If the lower contact pattern (115) includes tungsten, the lower bonding layer (125) may include tungsten silicide.

[0021] An element pattern structure (20) may be disposed on the upper part of the lower contact structure (10). The element pattern structure (20) may be a column structure extending in a direction substantially perpendicular to the surface (101S) of the substrate (101) (i.e., the z-direction). As an example, the element pattern structure (20) may be a square column structure.

[0022] In one embodiment, the device pattern structure (20) may be a resistance change memory device having a phase change layer (165). Additionally, the device pattern structure (20) may have a selection element layer (145) electrically connected in series with the phase change layer (165) as a selection element.

[0023] Referring to FIGS. 1 to 3, the device pattern structure (20) may include a first electrode layer (135), a selection element layer (145), a second electrode layer (155), a phase change layer (165), and a third electrode layer (175) that are sequentially stacked on a lower bonding layer (125). The first electrode layer (135), the selection element layer (145), the second electrode layer (155), the phase change layer (165), and the third electrode layer (175) may be arranged to overlap each other in a direction substantially perpendicular to the surface (101S) of the substrate (101) (i.e., the z-direction). That is, each of the first electrode layer (135), the selection element layer (145), the second electrode layer (155), the phase change layer (165), and the third electrode layer (175) may have the predetermined width (W) in the first direction (i.e., the x-direction) and the predetermined length (L) in the second direction (i.e., the y-direction) in a plane substantially parallel to the surface (101S) of the substrate (101). That is, the first electrode layer (135), the selection element layer (145), the second electrode layer (155), the phase change layer (165), and the third electrode layer (175) may have substantially the same cross-sectional area.

[0024] Additionally, the element pattern structure (20) may be positioned to overlap the lower contact structure (10) in a direction substantially perpendicular to the surface (101S) of the substrate (101) (i.e., the z-direction). That is, on a plane substantially parallel to the surface (101S) of the substrate (101) (for example, a cross-section parallel to the xy plane), the element pattern structure (20) may have substantially the same cross-sectional area as the lower contact structure (10).

[0025] Each of the first to third electrode layers (135, 155, 175) may include a conductive material. The conductive material may include, as an example, a doped semiconductor, a metal, a conductive metal nitride, a conductive metal carbide, a conductive metal silicide, or a conductive metal oxide. The conductive material may include, as an example, silicon, tungsten, titanium, copper, aluminum, ruthenium, platinum, iridium, iridium oxide, tungsten nitride, titanium nitride, tantalum nitride, tungsten carbide, titanium carbide, tungsten silicide, titanium silicide, tantalum silicide, ruthenium oxide, or a combination of two or more of these, doped with an n-type or p-type dopant. In one embodiment, the first to third electrode layers (135, 155, 175) may be made of the same material. In another embodiment, at least one of the first to third electrode layers (135, 155, 175) may be made of a material different from the other two.

[0026] The selection element layer (145) can control electrical access to the phase change memory layer (165) when an external voltage is applied. For example, if the magnitude of the voltage applied to both ends of the selection element layer (145) (i.e., the voltage applied between the first and second electrode layers (135, 155)) is less than a predetermined threshold value, the current flowing through the selection element layer (145) may be a low current at the level of leakage current. Conversely, if the magnitude of the voltage applied to both ends of the selection element layer (145) is greater than or equal to a predetermined threshold value, the current flowing through the selection element layer (145) may increase rapidly in substantial proportion to the magnitude of the applied voltage. The selection element layer (145) may include, for example, a metal insulator transition (MIT) element layer, a mixed ion-electron conduction (MIEC) element layer, etc. The above MIT device layer may include, as an example, niobium oxide (NbO2), titanium oxide (TiO2), etc. The above MIEC device layer may include, as an example, ZrO2(Y2O3), Bi2O3-BaO, (La2O3)x(CeO2) 1-x (0 <x<1)을 포함할 수 있다. 다른 예로서, 선택 소자층(145)은 실리콘 산화물, 실리콘 질화물 등을 포함할 수 있다.

[0027] The phase change layer (165) can function as a resistance change memory layer of the device pattern structure (20). Depending on the operating voltage applied to both ends of the phase change layer (165) (i.e., the voltage applied between the second and third electrode layers (155, 175)), the crystal state of the phase change layer (165) may change. As an example, heat may be generated within the phase change layer (165) by the operating voltage applied to both ends of the phase change layer (165). As an example, the heat may be Joule heat generated by Joule heating within the phase change layer (165).

[0028] When the generated heat increases above a predetermined threshold value, the heat can reversibly change the crystalline state of the phase change layer (165) from either an amorphous state or a crystalline state to the other. After the applied operating voltage is removed, the phase change layer (165) can maintain the changed crystalline state.

[0029] When the phase change layer (165) is in an amorphous state, the electrical resistance of the phase change layer (165) is in a relatively high resistance state, and when the phase change layer (165) is in a crystalline state, the electrical resistance of the phase change layer (165) may be in a relatively low resistance state. In this way, by utilizing electrical resistances that are distinguished from each other depending on the crystalline state of the phase change layer (165), the semiconductor device (1) can store signal information.

[0030] The phase change layer (165) may include a phase change material. The phase change material may include a chalcogen compound. The chalcogen compound may include, as an example, a compound of Ge, Sb, and Te (GST), a compound of Ge, Bi, and Te (GBT), a compound of As, Sb, and Te, a compound of As, Ge, Sb, and Te, a compound of Sn, Sb, and Te, a compound of In, Sn, Sb, and Te, a compound of Ag, In, Sb, and Te, or a combination of two or more of these. The chalcogen compound may include a dopant. The dopant may include, as an example, nitrogen, oxygen, silicon, or a combination of two or more of these.

[0031] Referring to FIGS. 1 to 3, an insulating layer (210) may be disposed on the side wall surface of the lower contact structure (10) and the element pattern structure (20). In one embodiment, when the lower contact structure (10) and the element pattern structure (20) are column structures, the insulating layer (210) may be disposed to surround the outer surface of the lower contact structure (10) and the element pattern structure (20). Meanwhile, referring to FIGS. 2 and 3, the insulating layer (210) may be partially disposed on the upper surface (101S) of the substrate (101).

[0032] The insulating layer (210) can perform the function of suppressing heat generated inside the phase change layer (165) of the device pattern structure (20) from propagating to the outside of the device pattern structure (20). As described above, heat may be generated in the phase change layer (165) by the operating voltage applied to both ends of the phase change layer (165). A portion of the heat may be consumed by propagating to the outside of the phase change layer (165) rather than being used in the phase change process of the phase change layer (165). As the amount of heat consumed increases, the efficiency of the recording operation by the operating voltage may decrease.

[0033] The insulating layer (210) can reduce heat propagating to the outside of the device pattern structure (20), thereby preventing a decrease in the efficiency of the recording operation. That is, the insulating layer (210) can help to preserve the heat generated by the operating voltage inside the device pattern structure (20). Additionally, the insulating layer (210) can prevent heat generated in any one of the multiple unit cells (UC1, UC2, UC3, UC4) from propagating to an adjacent unit cell. In the absence of the insulating layer (210) compared to the embodiment of the present disclosure, heat generated in any one of the unit cells can propagate to the adjacent unit cell, thereby changing the crystal state of the phase change layer of the other unit cell. Accordingly, a recording error may occur in the other unit cell.

[0034] The insulating layer (210) may include a metal-organic framework. The metal-organic framework may have heat insulating properties. Referring to FIG. 4a, the metal-organic framework (M) may be a material formed by the coordination bonding of a metal-containing node (Ma) and an organic ligand (Mb). The metal-organic framework (M) may exhibit low thermal conductivity by having a porous structure with a cavity (C) inside. As an example, the metal-organic framework (M) may have a thermal conductivity of less than 0.1 W / mK.

[0035] The node (Ma) containing the metal may be, as an example, a metal ion or a metal cluster. The metal may include, as an example, zinc (Zn), chromium (Cr), indium (In), gallium (Ga), copper (Cu), iron (Fe), molybdenum (Mo), cobalt (Co), ruthenium (Ru), manganese (Mn), lanthanum (La), titanium (Ti), hafnium (Hf), cadmium (Cd), zirconium (Zr), etc. The organic ligand (Mb) may include, as an example, oxalic acid, fumaric acid, benzenehexathiol, triphenylenehexathiol, 1,4-benzene dicarboxylic acid, hexaaminobenzene, tetrakis(4-carboxyphenyl)-porphyrinato-cobalt(II), tetrakis(4-carboxyphenyl)-porphyrin, etc. As other examples, the above organic ligand may include H2BDC, H2BDC-Br, H2BDC-OH, H2BDC-NO2, H2BDC-NH2, H4DOT, H2BDC-(Me)2, It may include H2BDC-(Cl)2, etc.

[0036] In one embodiment, the metal-organic structure (M) may have a physically and chemically stable two-dimensional network bonding structure. As shown in FIG. 4a, in the metal-organic structure (M), coordination bonding between the metal-containing node (Ma) and the organic ligand (Mb) may be regularly formed in two dimensions. As a result, the metal-organic structure (M) may exist in the form of a sheet having a thickness of nano-size (for example, 1 nm to 100 nm).

[0037] Referring to FIG. 4b, the insulating layer (210) may comprise a laminate (N) of a plurality of metal-organic structures (M1, M2, M3, M4). Each of the plurality of metal-organic structures (M1, M2, M3, M4) may be substantially identical to the two-dimensional metal-organic structure (M) described above in relation to FIG. 4a. The plurality of metal-organic structures (M1, M2, M3, M4) may be joined at a certain distance (d) by van der Waals forces. The plurality of metal-organic structures (M1, M2, M3, M4) may be joined to each other in a direction perpendicular to the surface of the two-dimensional sheet (i.e., the z-direction). In addition, since each of the multiple metal-organic structures (M1, M2, M3, M4) has a stable two-dimensional network bonding structure, the stack (N) of the multiple metal-organic structures (M1, M2, M3, M4) can maintain a structurally stable state.

[0038] In some other embodiments not illustrated in FIG. 4a and 4b, the metal-organic structure may have a three-dimensional structure. In this case, the nodes and organic ligands constituting the metal-organic structure may be positioned at fixed locations within the three-dimensional unit cell. The metal-organic structure having the three-dimensional structure may include, as an example, zeolitic imidazolate frameworks named ZIF-N (N is 1 to 12). The metal-organic structure having the three-dimensional structure may be a porous structure having a cavity inside. Through this, the metal-organic structure may have thermal insulating properties.

[0039] Referring again to FIGS. 1 to 3, an insulating layer (220) in contact with an insulating layer (210) may be disposed on the upper surface of a substrate (101). The insulating layer (220) may insulate a plurality of unit cells (UC1, UC2, UC3, UC4) from one another. The insulating layer (220) may include an insulating material. As an example, the insulating material may include an oxide, a nitride, an oxynitride, or a combination of two or more of these.

[0040] Referring again to FIGS. 1 to 3, an upper contact structure (30) may be disposed on a device pattern structure (20). The upper contact structure (30) may include an upper bonding layer (235) disposed on a third electrode layer (175) of the device pattern structure (20), and an upper contact pattern (245) disposed on the upper bonding layer (235).

[0041] The upper bonding layer (235) can function as an adhesive layer between the device pattern structure (20) and the upper contact pattern (245). Specifically, it can improve the adhesion between the third electrode layer (175) and the upper contact pattern (245). As an example, the upper bonding layer (235) may include a metal silicide. If the upper contact pattern (245) includes tungsten, the upper bonding layer (235) may include tungsten silicide.

[0042] The upper contact pattern (245) may include a conductive material. The conductive material may include, as an example, doped silicon, tungsten, tungsten silicide, tungsten nitride, titanium nitride, tantalum nitride, or a combination of two or more of these.

[0043] The upper contact pattern (245) may be electrically connected to a predetermined upper conduction line (not shown). The upper conduction line may provide a voltage to the upper contact pattern (245) to drive the device pattern structure (20). The upper conduction line may be arranged as a plurality of conduction lines to correspond to each of the plurality of unit cells (UC1, UC2, UC3, UC4). Alternatively, the upper conduction line may be arranged as a single conduction line to correspond commonly to the plurality of unit cells (UC1, UC2, UC3, UC4). However, it is not necessarily limited to this, and the configuration and arrangement of the upper conduction line may be varied according to the design form of the semiconductor device (1).

[0044] In some other embodiments, the lower bonding layer (125) of the lower contact structure (10) and the upper bonding layer (235) of the upper contact structure (30) may be omitted. In this case, the lower contact pattern (115) and the first electrode layer (135) may have sufficient adhesion at the interface. Likewise, the third electrode layer (175) and the upper contact pattern (245) may have sufficient adhesion at the interface.

[0045] In some other embodiments, the first electrode layer (135) and the selection layer (145) of the element pattern structure (20) may be omitted. Accordingly, the second electrode layer (155) and the lower bonding layer (125) may be arranged to be in contact.

[0046] In some other embodiments, the second electrode layer (155) and the third electrode layer (175) disposed at both ends of the phase change layer (165) may each include two or more conductive layers to efficiently generate and maintain the heat required for the phase change within the phase change layer (165).

[0047] In some other embodiments, a lower conductive line (not shown) may be disposed between the substrate (101) and the lower contact pattern (115). In this case, instead of the lower contact pattern (115) being in contact with the substrate (101), the lower contact pattern (115) may be disposed to be in contact with the lower conductive line. The lower conductive line may provide a voltage to the lower contact pattern (115) for driving the device pattern structure (20).

[0048] The lower conductive line may be arranged as a plurality of conductive lines to correspond to each of the plurality of unit cells (UC1, UC2, UC3, UC4). Alternatively, the lower conductive line may be arranged as a single conductive line to correspond commonly to the plurality of unit cells (UC1, UC2, UC3, UC4). However, it is not necessarily limited to this, and the configuration and arrangement of the upper conductive line can be varied in various ways depending on the design form of the semiconductor device (1).

[0049] In some other embodiments, the positions of the selection element layer (145) and the phase change layer (165) may be interchanged. That is, the phase change layer (165) may be placed between the first electrode layer (135) and the second electrode layer (155), and the selection element layer (145) may be placed between the second electrode layer (155) and the third electrode layer (175).

[0050] As described above, a semiconductor device according to one embodiment of the present disclosure may include a substrate, a device pattern structure disposed on top of the substrate, and an insulating layer disposed on the material pattern structure. The insulating layer may include a metal-organic structure having thermal insulating properties.

[0051] The above insulation layer can enable heat generated by the operating voltage to be effectively preserved within the device pattern structure. Accordingly, the thermal efficiency during the recording operation on the device pattern structure is increased, thereby improving the efficiency of the recording operation. In addition, the operation reliability of the semiconductor device can be improved by the insulation layer blocking the propagation of heat generated in one unit cell of the semiconductor device to an adjacent unit cell.

[0052] FIG. 5 is a cross-sectional view schematically illustrating a semiconductor device according to another embodiment of the present disclosure. The semiconductor device (2) of FIG. 5 may be distinguished from the semiconductor device (1) described in relation to FIG. 1 to 3, FIG. 4a and FIG. 4b in that the insulating layer (222) has an air gap. The remaining configuration of the semiconductor device (2), excluding the insulating layer (222), is substantially the same as the configuration of the semiconductor device (1).

[0053] The above-mentioned voids can reduce the thermal conductivity of heat passing through the insulating layer (222). That is, they can improve the thermal insulation properties of the insulating layer (222). Accordingly, the above-mentioned voids can improve the thermal separation properties of a plurality of unit cells (UC1, UC2, UC3, UC4) from one another. In one embodiment, the above-mentioned voids within the insulating layer (222) may contain various gases found in the atmosphere. In another embodiment, the above-mentioned voids within the insulating layer (222) may contain at least one of a gas provided for a semiconductor process and a byproduct gas generated from the semiconductor process.

[0054] The insulating layer (222) may include, as an example, an oxide, a nitride, an oxynitride, or a combination of two or more of these. As described below, by controlling the process conditions during the formation of the insulating layer (222), an air gap may be formed inside the insulating layer (222).

[0055] FIGS. 6a to 10a are plan views schematically illustrating a method for manufacturing a semiconductor device according to one embodiment of the present disclosure. FIGS. 6b to 10b are cross-sectional views taken along A-A' of the semiconductor device of FIGS. 6a to 10a, respectively. FIGS. 6c to 10c are cross-sectional views taken along B-B' of the semiconductor device of FIGS. 6a to 10a, respectively.

[0056] Referring to FIGS. 6A, 6B, and 6C, a substrate (101) is provided. The substrate (101) may include a semiconductor material. Specifically, the semiconductor material may include silicon, germanium, gallium arsenide, molybdenum sulfide (MoS2), molybdenum selenide (MoSe2), hafnium selenide (HfSe2), indium selenide (InSe), gallium selenide (GaSe), black phosphous, indium-gallium-zinc oxide (IGZO), or a combination of two or more of these. Although not illustrated, the substrate (101) may include an integrated circuit. The integrated circuit may be a circuit that drives and controls unit cells (UC1, UC2, UC3, UC4). The integrated circuit may include, as an example, components such as diodes and transistors.

[0057] A stacked structure (1000) can be formed by sequentially stacking a lower contact material layer (110), a lower bonding material layer (120), a first electrode material layer (130), a selection element material layer (140), a second electrode material layer (150), a phase change material layer (160), and a third electrode material layer (170) on a substrate (101). Each of the lower contact material layer (110), the lower bonding material layer (120), the first electrode material layer (130), the selection element material layer (140), the second electrode material layer (150), the phase change material layer (160), and the third electrode material layer (170) can be formed by, for example, sputtering, chemical vapor deposition, or atomic layer deposition.

[0058] Each of the lower contact material layer (110), the first electrode material layer (130), the second electrode material layer (150), and the third electrode material layer (170) may include a conductive material. The conductive material may include, as an example, doped silicon, tungsten, tungsten silicide, tungsten nitride, titanium nitride, tantalum nitride, or a combination of two or more of these.

[0059] In some embodiments, the second electrode material layer (150) and the third electrode material layer (170) disposed at both ends of the phase change material layer (160) may each be formed to include two or more conductive layers.

[0060] The lower bonding material layer (120) may include a metal silicide. As an example, when the lower contact material layer (110) includes tungsten, the lower bonding material layer (120) may include tungsten silicide.

[0061] The selection element material layer (140) may include, as an example, a metal oxide such as niobium oxide (NbO2) or titanium oxide (TiO2). As another example, the selection element material layer (140) may include ZrO2 (Y2O3), Bi2O3-BaO, or (La2O3)x(CeO2). 1-x (0 <x<1)과 같은 금속 산화물을 포함할 수 있다. 선택 소자 물질층(140)은 또다른 예로서, 실리콘 산화물, 실리콘 질화물 등을 포함할 수 있다.

[0062] The phase change material layer (160) may include a chalcogen compound. The chalcogen compound may include, as an example, a compound of Ge, Sb, and Te (GST), a compound of Ge, Bi, and Te (GBT), a compound of As, Sb, and Te, a compound of As, Ge, Sb, and Te, a compound of Sn, Sb, and Te, a compound of In, Sn, Sb, and Te, a compound of Ag, In, Sb, and Te, or a combination of two or more of these. The chalcogen compound may include a dopant. The dopant may include, as an example, nitrogen, oxygen, silicon, or a combination of two or more of these.

[0063] Referring to FIGS. 7a, 7b, and 7c, the stacked structure (1000) of FIGS. 6a, 6b, and 6c is selectively etched to form a lower contact structure (10) and a device pattern structure (20) on the upper surface of a substrate (101).

[0064] The lower contact structure (10) may include a lower contact pattern (115) disposed on a substrate (101) and a lower bonding layer (125) disposed on the lower contact pattern (115). The device pattern structure (20) may include a first electrode layer (135) disposed on the lower bonding layer (125), a selection device layer (145) disposed on the first electrode layer (135), a second electrode layer (155) disposed on the selection device layer (145), a phase change layer (165) disposed on the second electrode layer (155), and a third electrode layer (175) disposed on the phase change layer (165).

[0065] The lower contact structure (10) and the element pattern structure (20) may be formed to overlap each other in a direction substantially perpendicular to the surface (101S) of the substrate (101) (e.g., the z-direction). Accordingly, the lower contact structure (10) and the element pattern structure (20) may have a predetermined width (W) in a first direction (i.e., the x-direction) and a predetermined length (L) in a second direction (i.e., the y-direction) on a cross section substantially parallel to the surface (101S) of the substrate (101) (e.g., a plane parallel to the xy plane).

[0066] Referring to FIGS. 8A, 8B, and 8C, an insulating layer (210) is formed on the lower contact structure (10) and the element pattern structure (20) on the upper surface of the substrate (101). The insulating layer (210) may be formed to cover a portion of the upper surface of the substrate (101) (upper surface (101S) in FIGS. 7B and 7C), the side wall surface of the lower contact structure (10), and the side wall surface and upper surface of the element pattern structure (20).

[0067] The above metal-organic structure may have heat insulating properties. As described in relation to FIG. 4a, the metal-organic structure (M) may be a material formed by the coordination bonding of a metal-containing node (Ma) and an organic ligand (Mb). The metal-organic structure (M) may have a porous structure having a cavity (C). As an example, the metal-organic structure (M) may have a low thermal conductivity of less than 0.1 W / mK.

[0068] In one embodiment, the process of forming the insulating layer (210) may proceed to a process of forming the metal-organic structure by atomic layer deposition or chemical vapor deposition using a first precursor containing a metal constituting a metal node and a second precursor containing an organic ligand. In the case of the atomic layer deposition, as shown in FIG. 4b, the process may proceed to a process of forming a two-dimensional metal-organic structure (M1, M2, M3, M4) including a cavity layer by layer.

[0069] In another embodiment, the process of forming the insulating layer (210) may be carried out to include the process of synthesizing the metal-organic structure using a first precursor containing a metal constituting a metal node and a second precursor containing an organic ligand, and the process of coating the synthesized metal-organic structure on the ferroelectric layer.

[0070] Referring to FIGS. 9a, 9b, and 9c, an insulating layer (220) is formed on the upper surface of the substrate (101) in contact with the insulating layer (210). The insulating layer (220) may be formed to fill the space between adjacent lower contact structures (10) and the space between adjacent element pattern structures (20). The insulating layer (220) may be formed, as an example, by chemical vapor deposition or atomic layer deposition.

[0071] Referring to FIGS. 10a, 10b, and 10c, the insulating layer (210) covering the upper surface of the third electrode layer (175) of the device pattern structure (20) is removed to expose the third electrode layer (175). Subsequently, an upper bonding material layer (not shown) and an upper contact material layer (not shown) are sequentially formed on the third electrode layer (175). The upper bonding material layer and the upper contact material layer may be formed by, for example, chemical vapor deposition or atomic layer deposition. Subsequently, the upper bonding material layer and the upper contact material layer are sequentially patterned to form an upper bonding layer (235) and an upper contact pattern (245).

[0072] The upper bonding layer (235) may include a metal silicide as an example. The upper contact pattern (245) may include a conductive material. The conductive material may include, as an example, doped silicon, tungsten, tungsten silicide, tungsten nitride, titanium nitride, tantalum nitride, or a combination of two or more of these.

[0073] A semiconductor device according to one embodiment of the present disclosure can be manufactured by applying the method described above.

[0074] In some embodiments, an upper conductive line electrically connected to an upper contact pattern (245) may be additionally formed on the upper part of the substrate (101). The upper conductive line may include a conductive material.

[0075] In some other embodiments, when forming an insulating layer (220) in relation to FIGS. 9a, 9b, and 9c, process conditions such as process pressure, reaction gas partial pressure, and process temperature can be controlled to form an air gap inside the insulating layer (220). As a result, an insulating layer (222) having an air gap (225) inside can be formed, as described in relation to FIG. 5.

[0076] In some other embodiments, when forming the stacked structure (1000) in relation to FIGS. 6a, 6b, and 6c, the first electrode material layer (130) and the selection element material layer (140) may be omitted. Accordingly, the second electrode material layer (150) may be formed on the lower bonding material layer (120). As a result, the element pattern structure (20) may not have a selection element.

[0077] In some other embodiments, when forming a stacked structure (1000) in relation to FIGS. 6a, 6b, and 6c, a lower conductive line (not shown) may be formed between a substrate (101) and a lower contact material layer (110). Subsequently, when forming a lower contact structure (10) and a device pattern structure (20) in relation to FIGS. 7a, 7b, and 7c, a lower contact pattern (115) may be formed on the lower conductive line. The lower conductive line may include a conductive material. The lower conductive line may provide a voltage for driving the device pattern structure (20).

[0078] In some other embodiments, when forming a stacked structure (1000) in relation to FIGS. 6a, 6b, and 6c, the order of formation of the selection element material layer (140) and the phase change material layer (160) may be interchanged. That is, the phase change material layer (160) may be formed between the first electrode material layer (130) and the second electrode material layer (150), and the selection element material layer (140) may be formed between the second electrode material layer (150) and the third electrode material layer (170). Accordingly, when forming a device pattern structure (20) in relation to FIGS. 7a, 7b, and 7c, the phase change layer (165) may be formed between the first electrode layer (135) and the second electrode layer (155), and the selection element layer (145) may be formed between the second electrode layer (155) and the third electrode layer (175).

[0079] Although the foregoing has been described with reference to the drawings and embodiments, those skilled in the art will understand that various modifications and changes can be made to the embodiments disclosed in this application without departing from the technical spirit of the application as set forth in the following claims. Explanation of the symbols

[0080] 1, 2: Semiconductor device, UC1, UC2, UC3, IC4: 1st to 4th unit cells, 10: Lower contact structure, 20: Device pattern structure, 30: Upper contact structure 101: Substrate, 110: Lower contact material layer, 115: Lower contact pattern, 120: Lower bonding material layer, 125: Lower bonding layer, 130: First electrode material layer, 135: First electrode layer, 140: Selective element material layer, 145: Selective element layer, 150: Second electrode material layer, 155: Second electrode layer, 160: Phase change material layer, 165: Phase change layer, 170: Third electrode material layer, 175: Third electrode layer, 210: Insulation layer, 220: Insulation layer, 235: Upper bonding layer, 245: Upper contact pattern.

Claims

Claim 1 A semiconductor device comprising: a substrate; a device pattern structure disposed on the upper surface of the substrate; a heat insulating layer disposed on the sidewall surface of the device pattern structure and comprising a metal-organic framework; and an insulating layer disposed on the upper surface of the substrate and contacting the heat insulating layer in a lateral direction, wherein the insulating layer comprises an insulating material different from the metal-organic framework. Claim 2 A semiconductor device according to claim 1, wherein the element pattern structure comprises a first electrode layer; a phase change layer disposed on the first electrode layer; and a second electrode layer disposed on the phase change layer. Claim 3 A semiconductor device according to claim 2, wherein the element pattern structure further comprises: a third electrode layer disposed spaced apart from the first electrode layer or the second electrode layer; and a selection element layer disposed between the first electrode layer and the third electrode layer or between the second electrode layer and the third electrode layer. Claim 4 A semiconductor device according to claim 1, wherein the element pattern structure comprises a pillar structure extending in a direction substantially perpendicular to the surface of the substrate. Claim 5 In claim 4, the semiconductor device wherein the insulation layer is arranged to surround the outer surface of the column structure. Claim 6 In claim 1, the metal-organic structure is a semiconductor device having a porous structure. Claim 7 In claim 1, the metal-organic structure is a semiconductor device having a heat insulating property. Claim 8 In claim 7, the metal-organic structure is a semiconductor device having a thermal conductivity of less than 0.1 W / mK. Claim 9 delete Claim 10 A semiconductor device according to claim 1, further comprising a lower contact structure disposed between the substrate and the element pattern structure and having the same cross-sectional area as the element pattern structure. Claim 11 In claim 10, the semiconductor device wherein the insulating layer is positioned to surround the side of the lower contact structure. Claim 12 In claim 1, the insulating layer is a semiconductor device including an air gap. Claim 13 A semiconductor device comprising: a substrate; a plurality of unit cells spaced apart from each other on the upper surface of the substrate, wherein each of the plurality of unit cells extends in a direction perpendicular to the surface of the substrate and includes a phase change layer; an insulating layer disposed on the sidewall surface of the device pattern structure and including a metal-organic structure; and an insulating layer disposed on the upper surface of the substrate and contacting the insulating layer in a lateral direction, wherein the insulating layer includes an insulating material different from the metal-organic structure. Claim 14 A semiconductor device according to claim 13, wherein the element pattern structure comprises a column structure, and the insulating layer is arranged to surround the outer surface of the column structure. Claim 15 In claim 13, the metal-organic structure is a semiconductor device having thermal insulating properties. Claim 16 In claim 13, the insulating layer is a semiconductor device including an air gap. Claim 17 A method for manufacturing a semiconductor device comprising: a step of preparing a substrate; a step of forming a stacked structure including a first electrode material layer, a phase change material layer, and a second electrode material layer sequentially disposed on the upper surface of the substrate; a step of selectively etching the stacked structure to form a device pattern structure having a first electrode layer, a phase change layer, and a second electrode layer on the upper surface of the substrate; a step of forming an insulating layer including a metal-organic structure on a sidewall surface of the device pattern structure on the upper surface of the substrate; and a step of forming an insulating layer disposed on the upper surface of the substrate and contacting the insulating layer in a lateral direction, wherein the insulating layer includes an insulating material different from the metal-organic structure. Claim 18 A method for manufacturing a semiconductor device according to claim 17, wherein the step of forming the insulating layer comprises forming the metal-organic structure by atomic layer deposition or chemical vapor deposition using a first precursor comprising a metal constituting a metal node and a second precursor comprising an organic ligand. Claim 19 A method for manufacturing a semiconductor device according to claim 17, wherein the step of forming the insulating layer comprises: synthesizing the metal-organic structure using a first precursor comprising a metal constituting a metal node and a second precursor comprising an organic ligand; and coating the synthesized metal-organic structure on the sidewall surface of the device pattern structure. Claim 20 A method for manufacturing a semiconductor device according to claim 17, further comprising: a step of forming a lower contact material layer between the substrate and the device pattern structure; and a step of forming a lower contact pattern layer on the substrate by patterning the lower contact material layer after optionally etching the device pattern structure. Claim 21 A method for manufacturing a semiconductor device according to claim 20, wherein the step of forming the insulating layer further comprises the step of forming the insulating layer on the substrate such that the insulating layer covers the side of the lower contact pattern layer. Claim 22 A method for manufacturing a semiconductor device according to claim 17, wherein the step of forming the stacked structure further comprises the step of forming a third electrode material layer and a selection element material layer between the substrate and the first electrode material layer, and the step of forming the element pattern structure further comprises the step of selectively etching the third electrode material layer and the selection element material layer to form the third electrode layer and the selection element layer. Claim 23 A method for manufacturing a semiconductor device according to claim 17, wherein the step of forming the stacked structure further comprises the step of sequentially forming a select element material layer and a third electrode material layer on the second electrode material layer, and the step of forming the element pattern structure further comprises the step of selectively etching the third electrode material layer and the select element material layer to form the third electrode layer and the select element layer. Claim 24 In claim 17, the metal-organic structure is a method for manufacturing a semiconductor device having a porous structure. Claim 25 In claim 17, the method of manufacturing a semiconductor device wherein the insulating layer comprises a void. Claim 26 A method for manufacturing a semiconductor device according to claim 17, further comprising the steps of: forming an upper contact material layer on the upper part of the element pattern structure; and patterning the upper contact material layer to form an upper contact pattern layer.

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