Three-dimensional semiconductor memory device and electronic system including the same

Abstract

The present invention discloses a three-dimensional semiconductor memory device comprising a substrate including a first region and a second region extending from the first region, interlayer insulating films and gate electrodes alternately and repeatedly stacked on the substrate, a stacked structure having a stepped structure on the second region, an insulating film covering the stepped structure of the stacked structure, first vertical channel structures penetrating the stacked structure on the first region and contacting the substrate, first contact plugs penetrating the insulating film and the stacked structure on the second region, and first insulating pads provided within the insulating film and surrounding the upper portion of each of the first contact plugs, wherein the first insulating pads overlap the first vertical channel structures in a horizontal direction, a method for manufacturing the same, and an electronic system including the same.

Description

Technology Field

[0001] The present invention relates to a three-dimensional semiconductor memory device and an electronic system including the same, and more specifically, to a non-volatile three-dimensional semiconductor memory device including a vertical channel structure, a method for manufacturing the same, and an electronic system including the same. Background Technology

[0003] In electronic systems requiring data storage, there is a demand for semiconductor devices capable of storing high-capacity data. To increase data storage capacity while meeting the superior performance and low cost demands of consumers, it is necessary to increase the integration density of semiconductor devices. In the case of two-dimensional or planar semiconductor devices, integration density is primarily determined by the area occupied by a unit memory cell, and thus is significantly influenced by the level of fine pattern formation technology. However, since ultra-expensive equipment is required for pattern miniaturization, the integration density of two-dimensional semiconductor devices remains limited despite increasing. Accordingly, three-dimensional semiconductor memory devices equipped with memory cells arranged in three dimensions are being proposed.

[0004] delete Prior art literature

[65535] KR Published Patent Application 10-2014-0122890 (Published on 2014-10-21) The problem to be solved

[0005] One technical problem of the present invention is to provide a three-dimensional semiconductor memory device with improved electrical characteristics and reliability, and a method for manufacturing the same.

[0006] One technical problem of the present invention is to provide an electronic system including the three-dimensional semiconductor memory device.

[0007] The problems that the present invention aims to solve are not limited to those mentioned above, and other unmentioned problems will be clearly understood by those skilled in the art from the description below. means of solving the problem

[0009] To solve the aforementioned technical problems, a three-dimensional semiconductor memory device according to an embodiment of the present invention comprises a substrate including a first region and a second region extending from the first region, interlayer insulating films and gate electrodes alternately and repeatedly stacked on the substrate, a stacked structure having a step structure on the second region, an insulating film covering the step structure of the stacked structure, first vertical channel structures penetrating the stacked structure on the first region and contacting the substrate, first contact plugs penetrating the insulating film and the stacked structure on the second region, and first insulating pads provided within the insulating film and surrounding the upper portion of each of the first contact plugs, wherein the first insulating pads may overlap the first vertical channel structures in a horizontal direction.

[0010] Additionally, a three-dimensional semiconductor memory device according to an embodiment of the present invention comprises: a first substrate including a first region, a second region extending from the first region, and a third region extending from the second region; a peripheral circuit structure including peripheral circuit transistors on the first substrate and a first insulating film covering the peripheral circuit transistors; a second substrate on the peripheral circuit structure; lower insulating patterns inside the second substrate; interlayer insulating films and gate electrodes alternately and repeatedly stacked on the second substrate and the lower insulating patterns; a stacked structure having a stepped structure on the second region; a second insulating film covering the stepped structure of the stacked structure; a third insulating film provided on the second insulating film and co-planar with the top surface of the stacked structure; vertical channel structures penetrating the stacked structure on the first region and contacting the second substrate; first contact plugs penetrating one of the second and third insulating films, the stacked structure, and the lower insulating patterns on the second region; and the second and third It may include insulating films, a second contact plug penetrating another of the lower insulating patterns, insulating pads provided within the third insulating film and surrounding the upper portions of each of the first and second contact plugs, bit lines provided on the third insulating film and electrically connected to each of the vertical channel structures, and conductive lines provided on the third insulating film and electrically connected to each of the first and second contact plugs.

[0011] Additionally, an electronic system according to an embodiment of the present invention comprises a three-dimensional semiconductor memory device and a controller electrically connected to the three-dimensional semiconductor memory device and configured to control the three-dimensional semiconductor memory device, wherein the three-dimensional semiconductor memory device comprises a substrate including a first region, a second region extending from the first region, and a third region extending from the second region, interlayer insulating films and gate electrodes alternately and repeatedly stacked on the substrate, a stacked structure having a step structure on the second region, an insulating film covering the step structure of the stacked structure, vertical channel structures penetrating the stacked structure on the first region and contacting the substrate, first contact plugs penetrating the insulating film and the stacked structure on the second region, a second contact plug penetrating the insulating film and the substrate on the third region, insulating pads provided within the insulating film and surrounding the upper portions of each of the first and second contact plugs, and an input / output pad connected to the second contact plug, and the controller [requires] the three-dimensional semiconductor through the input / output pad. It is electrically connected to a memory device, and the vertical height of each of the first and second contact plugs may be greater than the vertical height of each of the vertical channel structures. Effects of the invention

[0013] According to the three-dimensional semiconductor memory device of the present invention, by providing an insulating pad surrounding the upper part of a contact plug, the bowing phenomenon of the contact plug can be suppressed, the tilting of the side wall of the contact plug with respect to the vertical direction can be suppressed, and the variation in the width of the uppermost part of a plurality of contact plugs can be reduced.

[0014] Accordingly, the formation of a bridge between adjacent contact plugs can be prevented and / or minimized, and it can be easier to control the vertical height of each contact plug. As a result, the electrical characteristics and reliability of the three-dimensional semiconductor memory device according to the present invention can be improved. Brief explanation of the drawing

[0016] FIG. 1 is a schematic diagram illustrating an electronic system including a three-dimensional semiconductor memory device according to embodiments of the present invention. FIG. 2 is a schematic perspective view showing an electronic system including a three-dimensional semiconductor memory device according to embodiments of the present invention. FIGS. 3 and FIGS. 4 are cross-sectional views for illustrating a semiconductor package including a three-dimensional semiconductor memory device according to embodiments of the present invention, corresponding respectively to cross-sections cut along the line I-I' and II-II' of FIG. 2. FIG. 5a is a plan view illustrating a three-dimensional semiconductor memory device according to embodiments of the present invention. FIG. 5b is a cross-sectional view for illustrating a three-dimensional semiconductor memory device according to embodiments of the present invention, corresponding to the cross-section of FIG. 5a cut along the line I-I'. FIGS. 6a and FIGS. 6b are enlarged cross-sectional views for illustrating a part of a three-dimensional semiconductor memory device according to embodiments of the present invention, each corresponding to part A of FIG. 5b. FIG. 7 is an enlarged cross-sectional view for explaining a part of a three-dimensional semiconductor memory device according to embodiments of the present invention, corresponding to part B of FIG. 5b. FIGS. 8, FIGS. 9, and FIGS. 10 are cross-sectional views for explaining a method for manufacturing a three-dimensional semiconductor memory device according to embodiments of the present invention, each corresponding to a cross-section obtained by cutting FIG. 5a along the line I-I'. FIGS. 11 and FIGS. 12 are cross-sectional views illustrating a three-dimensional semiconductor memory device according to embodiments of the present invention. FIGS. 13a, FIGS. 13b, and FIGS. 13c are enlarged cross-sectional views for illustrating parts of a three-dimensional semiconductor memory device according to embodiments of the present invention, each corresponding to part C of FIG. 12. FIGS. 14 and 15 are cross-sectional views illustrating a method for manufacturing a three-dimensional semiconductor memory device according to embodiments of the present invention. FIG. 16 is a cross-sectional view illustrating a three-dimensional semiconductor memory device according to embodiments of the present invention. Specific details for implementing the invention

[0017] Hereinafter, a three-dimensional semiconductor memory device according to embodiments of the present invention, a method for manufacturing the same, and an electronic system including the same will be described in detail with reference to the drawings.

[0019] FIG. 1 is a schematic diagram illustrating an electronic system including a three-dimensional semiconductor memory device according to embodiments of the present invention.

[0020] Referring to FIG. 1, an electronic system (1000) according to embodiments of the present invention may include a three-dimensional semiconductor memory device (1100) and a controller (1200) electrically connected to the three-dimensional semiconductor memory device (1100). The electronic system (1000) may be a storage device or an electronic device including a storage device, comprising one or more three-dimensional semiconductor memory devices (1100). For example, the electronic system (1000) may be a solid state drive device (SSD), a Universal Serial Bus (USB), a computing system, a medical device, or a communication device, comprising one or more three-dimensional semiconductor memory devices (1100).

[0021] The three-dimensional semiconductor memory device (1100) may be a non-volatile memory device, for example, a three-dimensional NAND flash memory device as described below. The three-dimensional semiconductor memory device (1100) may include a first region (1100F) and a second region (1100S) on the first region (1100F). For example, the first region (1100F) may be placed next to the second region (1100S). The first region (1100F) may be a peripheral circuit region including a decoder circuit (1110), a page buffer (1120), and a logic circuit (1130). The second region (1100S) may be a memory cell region comprising a bit line (BL), a common source line (CSL), word lines (WL), first lines (LL1, LL2), second lines (UL1, UL2), and memory cell strings (CSTR) between the bit line (BL) and the common source line (CSL).

[0022] In the second region (1100S), each memory cell string (CSTR) may include first transistors (LT1, LT2) adjacent to a common source line (CSL), second transistors (UT1, UT2) adjacent to a bit line (BL), and a plurality of memory cell transistors (MCT) disposed between the first transistors (LT1, LT2) and the second transistors (UT1, UT2). The number of first transistors (LT1, LT2) and the number of second transistors (UT1, UT2) may vary depending on the embodiments.

[0023] For example, the first transistors (LT1, LT2) may include ground select transistors, and the second transistors (UT1, UT2) may include string select transistors. The first lines (LL1, LL2) may each be the gate electrodes of the first transistors (LT1, LT2). The word lines (WL) may be the gate electrodes of the memory cell transistors (MCT). The second lines (UL1, UL2) may each be the gate electrodes of the second transistors (UT1, UT2).

[0024] For example, the first transistors (LT1, LT2) may include a first erase control transistor (LT1) and a ground select transistor (LT2) connected in series. The second transistors (UT1, UT2) may include a string select transistor (UT1) and a second erase control transistor (UT2) connected in series. At least one of the first erase control transistor (LT1) and the second erase control transistor (UT2) may be used for an erase operation that deletes data stored in memory cell transistors (MCTs) using the Gate Induced Drain Leakage (GIDL) phenomenon.

[0025] The common source line (CSL), first lines (LL1, LL2), word lines (WL), and second lines (UL1, UL2) can be electrically connected to the decoder circuit (1110) through first connecting wires (1115) extending from the first area (1100F) to the second area (1100S). The bit line (BL) can be electrically connected to the page buffer (1120) through second connecting wires (1125) extending from the first area (1100F) to the second area (1100S).

[0026] In the first region (1100F), the decoder circuit (1110) and the page buffer (1120) can perform control operations on at least one selected memory cell transistor among a plurality of memory cell transistors (MCT). The decoder circuit (1110) and the page buffer (1120) can be controlled by the logic circuit (1130). The three-dimensional semiconductor memory device (1100) can communicate with the controller (1200) through an input / output pad (1101) that is electrically connected to the logic circuit (1130). The input / output pad (1101) can be electrically connected to the logic circuit (1130) through an input / output connection wire (1135) that extends from the first region (1100F) to the second region (1100S).

[0027] The controller (1200) may include a processor (1210), a NAND controller (1220), and a host interface (1230). For example, the electronic system (1000) may include a plurality of three-dimensional semiconductor memory devices (1100), and in this case, the controller (1200) may control the plurality of three-dimensional semiconductor memory devices (1100).

[0028] The processor (1210) can control the overall operation of the electronic system (1000), including the controller (1200). The processor (1210) can operate according to a predetermined firmware and can access the three-dimensional semiconductor memory device (1100) by controlling the NAND controller (1220). The NAND controller (1220) may include a NAND interface (1221) that handles communication with the three-dimensional semiconductor memory device (1100). Through the NAND interface (1221), control commands for controlling the three-dimensional semiconductor memory device (1100), data to be written to the memory cell transistors (MCTs) of the three-dimensional semiconductor memory device (1100), data to be read from the memory cell transistors (MCTs) of the three-dimensional semiconductor memory device (1100), etc., can be transmitted. The host interface (1230) can provide communication functions between the electronic system (1000) and an external host. When a control command is received from an external host through the host interface (1230), the processor (1210) can control the three-dimensional semiconductor memory device (1100) in response to the control command.

[0030] FIG. 2 is a schematic perspective view showing an electronic system including a three-dimensional semiconductor memory device according to embodiments of the present invention.

[0031] Referring to FIG. 2, an electronic system (2000) according to embodiments of the present invention may include a main board (2001), a controller (2002) mounted on the main board (2001), at least one semiconductor package (2003) and a DRAM (2004). The semiconductor package (2003) and the DRAM (2004) may be connected to the controller (2002) by wiring patterns (2005) provided on the main board (2001).

[0032] The main board (2001) may include a connector (2006) comprising a plurality of pins that are coupled to an external host. The number and arrangement of the plurality of pins in the connector (2006) may vary depending on the communication interface between the electronic system (2000) and the external host. For example, the electronic system (2000) may communicate with the external host according to any one of the interfaces such as USB (Universal Serial Bus), PCI-Express (Peripheral Component Interconnect Express), SATA (Serial Advanced Technology Attachment), and M-Phy for UFS (Universal Flash Storage). For example, the electronic system (2000) may operate by power supplied from the external host through the connector (2006). The electronic system (2000) may further include a Power Management Integrated Circuit (PMIC) that distributes power supplied from the external host to a controller (2002) and a semiconductor package (2003).

[0033] The controller (2002) can write data to the semiconductor package (2003) or read data from the semiconductor package (2003), and can improve the operating speed of the electronic system (2000).

[0034] The DRAM (2004) may be a buffer memory to mitigate the speed difference between the semiconductor package (2003), which is a data storage space, and an external host. The DRAM (2004) included in the electronic system (2000) may also function as a type of cache memory and may provide a space for temporarily storing data during control operations on the semiconductor package (2003). When the electronic system (2000) includes the DRAM (2004), the controller (2002) may further include a DRAM controller for controlling the DRAM (2004) in addition to the NAND controller for controlling the semiconductor package (2003).

[0035] A semiconductor package (2003) may include first and second semiconductor packages (2003a, 2003b) spaced apart from each other. The first and second semiconductor packages (2003a, 2003b) may each be a semiconductor package including a plurality of semiconductor chips (2200). Each of the first and second semiconductor packages (2003a, 2003b) may include a package substrate (2100), semiconductor chips (2200) on the package substrate (2100), adhesive layers (2300) disposed on the lower surface of each of the semiconductor chips (2200), a connection structure (2400) electrically connecting the semiconductor chips (2200) and the package substrate (2100), and a molding layer (2500) covering the semiconductor chips (2200) and the connection structure (2400) on the package substrate (2100).

[0036] The package substrate (2100) may be a printed circuit board including package upper pads (2130). Each semiconductor chip (2200) may include input / output pads (2210). Each of the input / output pads (2210) may correspond to the input / output pad (1101) of FIG. 1. Each of the semiconductor chips (2200) may include gate stacking structures (3210) and vertical channel structures (3220). Each of the semiconductor chips (2200) may include a three-dimensional semiconductor memory device as described below.

[0037] For example, the connection structure (2400) may be a bonding wire that electrically connects the input / output pads (2210) and the package upper pads (2130). In each of the first and second semiconductor packages (2003a, 2003b), the semiconductor chips (2200) may be electrically connected to each other by a bonding wire method and may be electrically connected to the package upper pads (2130) of the package substrate (2100). According to embodiments, in each of the first and second semiconductor packages (2003a, 2003b), the semiconductor chips (2200) may be electrically connected to each other by a through silicon via (TSV) instead of the bonding wire method connection structure (2400).

[0038] For example, the controller (2002) and the semiconductor chips (2200) may be included in a single package. For example, the controller (2002) and the semiconductor chips (2200) may be mounted on a separate interposer substrate different from the main substrate (2001), and the controller (2002) and the semiconductor chips (2200) may be connected to each other by wiring provided on the interposer substrate.

[0040] FIGS. 3 and FIGS. 4 are cross-sectional views for illustrating a semiconductor package including a three-dimensional semiconductor memory device according to embodiments of the present invention, corresponding respectively to cross-sections cut along the line I-I' and II-II' of FIG. 2.

[0041] Referring to FIGS. 3 and 4, a semiconductor package (2003) may include a package substrate (2100), a plurality of semiconductor chips (2200) on the package substrate (2100), and a molding layer (2500) covering the package substrate (2100) and the plurality of semiconductor chips (2200).

[0042] The package substrate (2100) may include a package substrate body portion (2120), package upper pads (2130) disposed on the upper surface of the package substrate body portion (2120), lower pads (2125) disposed on the lower surface of the package substrate body portion (2120) or exposed through the lower surface, and internal wiring (2135) that electrically connects the upper pads (2130) and the lower pads (2125) inside the package substrate body portion (2120). The upper pads (2130) may be electrically connected to connection structures (2400). The lower pads (2125) may be connected to wiring patterns (2005) of the main substrate (2010) of the electronic system (2000) illustrated in FIG. 2 through conductive connection portions (2800).

[0043] Each of the semiconductor chips (2200) may include a semiconductor substrate (3010) and a first structure (3100) and a second structure (3200) that are stacked sequentially on the semiconductor substrate (3010). The first structure (3100) may include a peripheral circuit region including peripheral wiring (3110). The second structure (3200) may include a common source line (3205), a gate stacking structure (3210) on the common source line (3205), vertical channel structures (3220) and separation structures (3230) penetrating the gate stacking structure (3210), bit lines (3240) electrically connected to the vertical channel structures (3220), gate connection wiring (3235) and conduction lines (3250) electrically connected to the word lines (WL in FIG. 1) of the gate stacking structure (3210). Each of the gate connection wires (3235) can be electrically connected to any one of the word lines (WL). At least one of the gate connection wires (3235) can be electrically connected to the common source line (3205).

[0044] Each of the semiconductor chips (2200) may include a through-wire (3245) that is electrically connected to the peripheral wiring (3110) of the first structure (3100) and extends into the second structure (3200). The through-wire (3245) may penetrate the gate stack structure (3210) and may be further disposed outside the gate stack structure (3210). Each of the semiconductor chips (2200) may further include an input / output connection wiring (3265) that is electrically connected to the peripheral wiring (3110) of the first structure (3100) and extends into the second structure (3200), and an input / output pad (2210) that is electrically connected to the input / output connection wiring (3265).

[0046] FIG. 5a is a plan view for illustrating a three-dimensional semiconductor memory device according to embodiments of the present invention. FIG. 5b is a cross-sectional view for illustrating a three-dimensional semiconductor memory device according to embodiments of the present invention, corresponding to the cross section of FIG. 5a cut along the line I-I'.

[0047] Referring to FIGS. 5a and 5b, a first substrate (10) may be provided, comprising a first region (R1), a second region (R2), and a third region (R3). The first substrate (10) may extend in a first direction (D1) toward the third region (R3) from the first region (R1) and in a second direction (D2) that intersects the first direction (D1). The upper surface of the first substrate (10) may be orthogonal to the third direction (D3) that intersects the first direction (D1) and the second direction (D2). For example, the first direction (D1), the second direction (D2), and the third direction (D3) may be directions that are orthogonal to each other.

[0048] A second region (R2) may extend from a first region (R1) in a first direction (D1). A third region (R3) may extend from a second region (R2) in a first direction (D1). The first region (R1) may be an area provided with vertical channel structures (3220), separation structures (3230), and bit lines (3240) electrically connected to the vertical channel structures (3220) as described with reference to FIGS. 3 and 4. The second region (R2) may be an area provided with a stepped structure of a stacked structure (ST). The third region (R3) may be an area provided with through-wires (3245) or input / output connection wires (3265) as described with reference to FIGS. 3 and 4.

[0049] The first substrate (10) may be, for example, a silicon substrate, a silicon-germanium substrate, a germanium substrate, or a monocrystalline epitaxial layer grown on a monocrystalline silicon substrate. A device isolation layer (11) may be provided within the first substrate (10). The device isolation layer (11) may define an active region of the first substrate (10). The device isolation layer (11) may include, for example, silicon oxide.

[0050] A peripheral circuit structure (PS) may be provided on a first substrate (10). The peripheral circuit structure (PS) may include peripheral circuit transistors (PTR) on the active region of the first substrate (10), peripheral circuit contact plugs (31), peripheral circuit wiring (33) electrically connected to the peripheral circuit transistors (PTR) through the peripheral circuit contact plugs (31), and a first insulating film (30) surrounding them. The peripheral circuit structure (PS) may correspond to the first region (1100F) of FIG. 1, and the peripheral circuit wiring (33) may correspond to the peripheral wiring (3110) of FIG. 3 and FIG. 4.

[0051] Peripheral circuit transistors (PTR), peripheral circuit contact plugs (31), and peripheral circuit wiring (33) can form a peripheral circuit. For example, peripheral circuit transistors (PTR) can form the decoder circuit (1110), page buffer (1120), and logic circuit (1130) of FIG. 1. More specifically, each peripheral circuit transistor (PTR) may include a peripheral gate insulating film (21), a peripheral gate electrode (23), a peripheral capping pattern (25), a peripheral gate spacer (27), and peripheral source / drain regions (29).

[0052] A peripheral gate insulating film (21) may be provided between the peripheral gate electrode (23) and the first substrate (10). A peripheral capping pattern (25) may be provided on the peripheral gate electrode (23). A peripheral gate spacer (27) may cover the sidewalls of the peripheral gate insulating film (21), the peripheral gate electrode (23), and the peripheral capping pattern (25). Peripheral source / drain regions (29) may be provided inside the first substrate (10) adjacent to both sides of the peripheral gate electrode (23).

[0053] Peripheral circuit wirings (33) can be electrically connected to peripheral circuit transistors (PTRs) through peripheral circuit contact plugs (31). Each peripheral circuit transistor (PTR) may be, for example, an NMOS transistor, a PMOS transistor, or a gate-all-around type transistor. For example, the peripheral circuit contact plugs (31) may increase in width as they move away from the first substrate (10). The peripheral circuit contact plugs (31) and peripheral circuit wirings (33) may include a conductive material such as metal.

[0054] A first insulating film (30) may be provided on the upper surface of a first substrate (10). The first insulating film (30) may cover peripheral circuit transistors (PTR), peripheral circuit contact plugs (31), and peripheral circuit wiring (33) on the first substrate (10). The first insulating film (30) may include a plurality of insulating films having a multilayer structure. For example, the first insulating film (30) may include silicon oxide, silicon nitride, and / or silicon oxynitride.

[0055] A cell array structure (CS) comprising a second substrate (100), a stacked structure (ST), first and second vertical channel structures (VS1, VS2), and first and second contact plugs (CP1, CP2) may be provided on a peripheral circuit structure (PS). Below, the structure of the cell array structure (CS) will be described in detail.

[0056] A second substrate (100) and lower insulating patterns (101) may be provided on the first insulating film (30). The second substrate (100) may extend in a first direction (D1) and a second direction (D2). The second substrate (100) may be a semiconductor substrate comprising a semiconductor material. The second substrate (100) may include, for example, at least one of silicon (Si), germanium (Ge), silicon germanium (SiGe), gallium arsenide (GaAs), indium gallium arsenide (InGaAs), aluminum gallium arsenide (AlGaAs), or a mixture thereof.

[0057] The lower insulating patterns (101) may define the locations where the first and second contact plugs (CP1, CP2), described later, are provided. The lower insulating patterns (101) may be provided between the first insulating film (30) and the source structure (SC) described later. Each of the lower insulating patterns (101) may be surrounded by the second substrate (100) in a planar view. The upper surface of each of the lower insulating patterns (101) may be substantially co-planar with the upper surface of the second substrate (100), and the lower surface of each of the lower insulating patterns (101) may be substantially co-planar with the lower surface of the second substrate (100) and the upper surface of the first insulating film (30). The lower insulating patterns (101) may include, for example, silicon oxide, silicon nitride and / or silicon oxynitride.

[0058] A stacked structure (ST) may be provided on the second substrate (100) and the lower insulating patterns (101). The stacked structure (ST) may extend in a first direction (D1) from a first region (R1) toward a second region (R2). The stacked structure (ST) may correspond to the stacked structures (3210) of FIGS. 3 and 4.

[0059] A plurality of stacked structures (ST) may be provided, and a plurality of stacked structures (ST) may be arranged along a second direction (D2). In a planar view, first separation structures (SS1) may be provided within first trenches (TR1) that traverse between a plurality of stacked structures (ST) in a first direction (D1). The first separation structures (SS1) may extend from a first region (R1) to a second region (R2). The first separation structures (SS1) may be provided on both side walls of any one of the plurality of stacked structures (ST). Stacked structures (ST) adjacent to each other in the second direction (D2) may be spaced apart in the second direction (D2) with one of the first separation structures (SS1) in between.

[0060] A second separation structure (SS2) may be provided within a second trench (TR2) extending in a first direction (D1) between the first separation structures (SS1). The second separation structure (SS2) may cross the top of the stacked structure (ST). The second separation structure (SS2) may be provided on the first region (R1). According to embodiments, a plurality of second separation structures (SS2) may be provided between the first separation structures (SS1). Additionally, according to embodiments, the second separation structure (SS2) may extend from the first region (R1) onto a portion of the second region (R2). The first and second separation structures (SS1, SS2) may comprise, for example, silicon oxide, silicon nitride, and / or silicon oxynitride.

[0061] In the following description, for the convenience of explanation, a single stacked structure (ST) and a single first separation structure (SS1) are described, but the following description can be applied substantially the same to other stacked structures (ST) and other first separation structures (SS1).

[0062] The stacked structure (ST) may include interlayer insulating films (ILD) stacked on the second substrate (100) and gate electrodes (EL) between the interlayer insulating films (ILD). The interlayer insulating films (ILD) and gate electrodes (EL) may be stacked alternately and repeatedly on the second substrate (100). The gate electrodes (EL) may correspond to the first lines (LL1, LL2), word lines (WL), and second lines (UL1, UL2) of FIG. 1.

[0063] The gate electrodes (EL) may have a length in the first direction (D1) that decreases as they move away from the second substrate (100) (i.e., toward the third direction (D3). In other words, the length of each gate electrode (EL) in the first direction (D1) may be greater than the length of the line located immediately above the line in the first direction (D1). The lowest gate electrode (EL) may have the longest length in the first direction (D1) among the gate electrodes (EL), and the highest gate electrode (EL) may have the shortest length in the first direction (D1) among the gate electrodes (EL).

[0064] The gate electrodes (EL) may have pad portions (ELp) on the second region (R2). The pad portions (ELp) of the gate electrodes (EL) may be positioned at different locations horizontally and vertically. The thickness of each pad portion (ELp) may be greater than the thickness of other parts of each gate electrode (EL). The upper surface of each pad portion (ELp) may be located at a higher level than the upper surface of other parts of each gate electrode (EL). Each pad portion (ELp) may cover at least a portion of the sidewall of the interlayer insulating film (ILD) above it.

[0065] The pad portions (ELp) can form a stepped structure along the first direction (D1). Due to the stepped structure, the thickness of the stacked structure (ST) can decrease as it moves away from the first vertical channel structures (VS1), and the sidewalls of the gate electrodes (EL) can be spaced apart at regular intervals along the first direction (D1) in a planar view.

[0066] The gate electrodes (EL) may include at least one selected from, for example, a doped semiconductor (e.g., doped silicon, etc.), a metal (e.g., tungsten, copper, aluminum, etc.), a conductive metal nitride (e.g., titanium nitride, tantalum nitride, etc.), or a transition metal (e.g., titanium, tantalum, etc.).

[0067] Interlayer insulating films (ILD) can be provided between gate electrodes (EL). Like the gate electrodes (EL), the length of the interlayer insulating films (ILD) in the first direction (D1) can decrease as it moves away from the second substrate (100).

[0068] For example, the thickness of each interlayer insulating film (ILD) may be smaller than the thickness of each gate electrode (EL). In this specification, thickness refers to the thickness in the third direction (D3). For example, the thickness of the bottommost of the interlayer insulating films (ILD) may be smaller than the thickness of each of the other interlayer insulating films (ILD). For example, the thickness of the topmost of the interlayer insulating films (ILD) may be larger than the thickness of each of the other interlayer insulating films (ILD). However, this is merely exemplary, and the thickness of the interlayer insulating films (ILD) may vary depending on the characteristics of the semiconductor device. The interlayer insulating films (ILD) may comprise, for example, silicon oxide, silicon nitride, and / or silicon oxynitride.

[0069] A source structure (SC) may be provided between the second substrate (100) and the stacked structure (ST). The second substrate (100) and the source structure (SC) may correspond to the common source line (CSL) of FIG. 1 and the common source line (3205) of FIG. 3 and FIG. 4.

[0070] The source structure (SC) may extend in a first direction (D1) and a second direction (D2) parallel to the gate electrodes (EL) of the stacked structure (ST). The source structure (SC) may extend from a first region (R1) to a second region (R2) and may not be provided in a third region (R3). The source structure (SC) may include a first source conduction pattern (SCP1) and a second source conduction pattern (SCP2) stacked in sequence. The second source conduction pattern (SCP2) may be provided between the first source conduction pattern (SCP1) and the lowest of the interlayer insulating films (ILD). The thickness of the first source conduction pattern (SCP1) may be greater than the thickness of the second source conduction pattern (SCP2). Each of the first and second source conduction patterns (SCP1, SCP2) may include an impurity-doped semiconductor material. For example, the impurity concentration of the first source conduction pattern (SCP1) may be greater than the impurity concentration of the second source conduction pattern (SCP2).

[0071] First vertical channel structures (VS1) may be provided to penetrate the stacked structure (ST) and the source structure (SC) on the first region (R1) and to contact the second substrate (100). Each of the first vertical channel structures (VS1) may penetrate at least a portion of the second substrate (100), and the lower surface of each of the first vertical channel structures (VS1) may be located at a lower level than the upper surface of the second substrate (100) and the lower surface of the source structure (SC). The first vertical channel structures (VS1) may be provided within vertical channel holes (CH) penetrating the stacked structure (ST) and the source structure (SC). Each of the first vertical channel structures (VS1) may have a width that increases toward the third direction (D3).

[0072] The first vertical channel structures (VS1) may be arranged in a zigzag shape along the first direction (D1) or the second direction (D2) in a planar view. The first vertical channel structures (VS1) may not be provided on the second region (R2). The first vertical channel structures (VS1) may be provided between the first separation structures (SS1). Some of the first vertical channel structures (VS1) may overlap with the second separation structure (SS2) in the third direction (D3), for example. The first vertical channel structures (VS1) may correspond to the vertical channel structures (3220) of FIGS. 2 through 4. The first vertical channel structures (VS1) may correspond to the channels of the first transistors (LT1, LT2), memory cell transistors (MCT), and second transistors (UT1, UT2) of FIG. 1.

[0073] Each of the first vertical channel structures (VS1) may include a data storage pattern (DSP) adjacent to the stacked structure (ST) (i.e., covering the inner wall of each of the vertical channel holes (CH)), a vertical semiconductor pattern (VSP) conformally covering the inner wall of the data storage pattern (DSP), a buried insulating pattern (VI) filling the internal space enclosed by the vertical semiconductor pattern (VSP), and a conductive pad (PAD) provided in the space enclosed by the buried insulating pattern (VI) and the data storage pattern (DSP). The upper surface of each of the first vertical channel structures (VS1) may be, for example, circular, elliptical, or bar-shaped.

[0074] A vertical semiconductor pattern (VSP) may be provided between a data storage pattern (DSP) and a buried insulation pattern (VI). The vertical semiconductor pattern (VSP) may have a pipe shape or a macaroni shape with a closed bottom. The vertical semiconductor pattern (VSP) may, for example, come into contact with a part of a source structure (SC). The vertical semiconductor pattern (VSP) may, for example, comprise polysilicon.

[0075] The data storage pattern (DSP) may have a pipe shape or a macaroni shape with an open bottom. The data storage pattern (DSP) may include a plurality of insulating films stacked in sequence. The buried insulating pattern (VI) may include, for example, silicon oxide. The conductive pad (PAD) may include, for example, an impurity-doped semiconductor material or a conductive material.

[0076] A plurality of second vertical channel structures (VS2) may be provided on the second region (R2) that penetrate the second and third insulating films (110, 120), the stacked structure (ST), and the source structure (SC) described later. More specifically, the second vertical channel structures (VS2) may penetrate the pad portions (ELp) of the gate electrodes (EL). The second vertical channel structures (VS2) may be provided around the first contact plugs (CP1) described later. The second vertical channel structures (VS2) may not be provided on the first region (R1). The second vertical channel structures (VS2) may be dummy channel structures that do not operate in the cell.

[0077] The second vertical channel structures (VS2) can be formed simultaneously with the first vertical channel structures (VS1). The second vertical channel structures (VS2) can have substantially the same structure as the first vertical channel structures (VS1).

[0078] On the second region (R2), a second insulating film (110) covering the stepped structure of the laminated structure (ST) may be provided. A third insulating film (120) may be provided on the second insulating film (110). The third insulating film (120) may have a substantially flat upper surface. The upper surface of the third insulating film (120) may be substantially co-planar with the uppermost surface of the laminated structure (ST) (i.e., the upper surface of the uppermost of the interlayer insulating films (ILD). The lower surface of the third insulating film (120) may be located at a higher level than the lower surface of the uppermost of the interlayer insulating films (ILD).

[0079] Each of the second and third insulating films (110, 120) may comprise, for example, silicon oxide, silicon nitride and / or silicon oxynitride. The third insulating film (120) may comprise, for example, silicon oxide doped with impurities.

[0080] On the second region (R2), first contact plugs (CP1) may be provided that penetrate one of the second and third insulating films (110, 120), the stacked structure (ST), the source structure (SC), and the lower insulating patterns (101). Each of the first contact plugs (CP1) may contact any one of the peripheral circuit wirings (33) of the peripheral circuit structure (PS) and may be electrically connected to at least one of the peripheral circuit transistors (PTR). Each of the first contact plugs (CP1) may be adjacent to the second vertical channel structures (VS2) but spaced apart from the second vertical channel structures (VS2). The height of each of the first contact plugs (CP1) in the third direction (D3) may be greater than the height of the stacked structure (ST) in the third direction (D3). The upper surface of each of the first contact plugs (CP1) may substantially co-plane with the upper surface of the third insulating film (120). The lower surface of each of the first contact plugs (CP1) may be located at a lower level than the lower surface of the second substrate (100) and the lower surfaces of the lower insulating patterns (101). The first contact plugs (CP1) may correspond to the gate connection wires (3235) of FIG. 4.

[0081] Each of the first contact plugs (CP1) can be electrically connected by contacting any one of the gate electrodes (EL) (i.e., the pad portions (ELp) of the gate electrodes (EL) exposed by the step structure). Each of the first contact plugs (CP1) can be horizontally spaced apart from each other by the gate electrodes (EL) and the source structure (SC) below the pad portions (ELp) and the isolation insulation patterns (IP) in between. In other words, each of the first contact plugs (CP1) can be electrically connected to any one of the gate electrodes (EL) and electrically isolated from other gate electrodes (EL).

[0082] On the third region (R3), a second contact plug (CP2) may be provided that penetrates one of the second and third insulating films (110, 120) and the lower insulating patterns (101). The second contact plug (CP2) may contact any one of the peripheral circuit wirings (33) of the peripheral circuit structure (PS) and may be electrically connected to at least one of the peripheral circuit transistors (PTR). The second contact plug (CP2) may be spaced apart in a first direction (D1) from the sidewall of the stacked structure (ST) (i.e., the sidewall of the lowest of the gate electrodes (EL)) and the sidewall of the source structure (SC). The height of the second contact plug (CP2) in the third direction (D3) may be substantially the same as the height of each of the first contact plugs (CP1) in the third direction (D3). The upper surface of the second contact plug (CP2) may substantially co-plane with the upper surface of the third insulating film (120). The lower surface of the second contact plug (CP2) may be located at a lower level than the lower surface of the second substrate (100) and the lower surfaces of the lower insulating patterns (101). The second contact plug (CP2) may correspond to the through wiring (3245) or input / output connection wiring (3265) of FIGS. 3 and 4. According to embodiments, the second contact plug (CP2) may be provided in plurality on the third region (R3).

[0083] Each of the first and second contact plugs (CP1, CP2) may have a width that increases toward the third direction (D3). The first and second contact plugs (CP1, CP2) may include a conductive material such as metal.

[0084] Insulating pads (NP) surrounding the upper portions of the second vertical channel structures (VS2) and the first and second contact plugs (CP1, CP2) respectively may be provided within the third insulating film (120). In this specification, the insulating pads (NP) surrounding the upper portions of the first contact plugs (CP1) may be referred to as the first insulating pads, the insulating pads (NP) surrounding the upper portions of the second vertical channel structures (VS2) may be referred to as the second insulating pads, and the insulating pad (NP) surrounding the upper portion of the second contact plug (CP2) may be referred to as the third insulating pad.

[0085] Each of the insulating pads (NP) may be surrounded by a third insulating film (120) in a planar view. The insulating pads (NP) may overlap horizontally with the laminated structure (ST) and the first vertical channel structures (VS1). The upper surfaces of the insulating pads (NP) may be located at the same level as the upper surfaces of the first and second vertical channel structures (VS1, VS2), the upper surfaces of the first and second contact plugs (CP1, CP2), and the uppermost surface of the laminated structure (ST) (i.e., the upper surface of the uppermost of the interlayer insulating films (ILD). The upper surfaces of the insulating pads (NP) may be substantially co-planar with the upper surface of the third insulating film (120). The lower surfaces of the insulating pads (NP) may be located at a higher level than the lower surface of the uppermost of the interlayer insulating films (ILD). The lower surfaces of the insulating pads (NP) may substantially co-plan with the lower surface of the third insulating film (120). The insulating pads (NP) may include an insulating material different from that of the second and third insulating films (110, 120). For example, the second and third insulating films (110, 120) may include silicon oxide, and the insulating pads (NP) may include silicon nitride.

[0086] A fourth insulating film (150) may be provided on the laminated structure (ST) and the third insulating film (120). The fourth insulating film (150) may include, for example, silicon oxide, silicon nitride and / or silicon oxynitride. The fourth insulating film (150) may include, for example, insulating pads (NP) and other insulating materials.

[0087] Bit line contact plugs (BP) penetrating the fourth insulating film (150) on the first region (R1) may be provided. Each bit line contact plug (BP) may be electrically connected to a conductive pad (PAD) of each of the first vertical channel structures (VS1). Each bit line contact plug (BP) may increase in width toward the third direction (D3). The bit line contact plugs (BP) may include a conductive material such as metal.

[0088] Bit lines (BL) electrically connected to bit line contact plugs (BP), first conductive lines (CL1) electrically connected to first contact plugs (CP1), and second conductive lines (CL2) electrically connected to second contact plugs (CP2) may be provided on the fourth insulating film (150). Each of the first vertical channel structures (VS1) may overlap with two bit lines (BL) in a third direction (D3) and may be electrically connected to one of them. The bit lines (BL), the first and second conductive lines (CL1, CL2) may include a conductive material such as metal. The bit lines (BL) may correspond to the bit line (BL) of FIG. 1 and the bit lines (3240) of FIG. 3 and FIG. 4, and the first and second conductive lines (CL1, CL2) may correspond to the conductive lines (3250) of FIG. 4. According to the embodiments, the second conductive line (CL2) can be electrically connected to the input / output pad (1101) of FIG. 1, and the input / output pads (2210) of FIG. 2 and FIG. 3.

[0089] Additional insulating film covering bit lines (BL), first and second conductive lines (CL1, CL2) on the fourth insulating film (150) and additional wiring inside the additional insulating film may be provided.

[0091] FIG. 6a is an enlarged cross-sectional view for explaining a part of a three-dimensional semiconductor memory device according to embodiments of the present invention, corresponding to part A of FIG. 5b.

[0092] Referring to FIG. 5b and FIG. 6a, a portion of one of the first contact plugs (CP1) and one of the insulating pads (NP) are shown. For convenience of explanation, a single first contact plug (CP1) is described below, but the following description may be applied substantially equally to other first contact plugs (CP1), second contact plugs (CP2), and second vertical channel structures (VS2). Additionally, a single insulating pad (NP) is described below, but the following description may be applied substantially equally to other insulating pads (NP).

[0093] The first contact plug (CP1) may include a first portion (CP11) and a second portion (CP12) on the first portion (CP11). The first portion (CP11) of the first contact plug (CP1) may be a portion surrounded by a second insulating film (110), and the second portion (CP12) of the first contact plug (CP1) may be a portion surrounded by a third insulating film (120) or an insulating pad (NP).

[0094] The sidewalls (CP11s) of the first part (CP11) may be covered with a second insulating film (110). The sidewalls (CP11s) of the first part (CP11) may have a convex curved profile (e.g., a bow profile). The first width (W1), defined as the width of the first part (CP11) in the horizontal direction (e.g., the first direction (D1)), may increase and then decrease as it goes toward the third direction (D3). In other words, the point where the first width (W1) is maximum may be located at a level lower than the bottom surface of the insulating pad (NP).

[0095] The sidewalls (CP12s) of the second part (CP12) may be covered with an insulating pad (NP). The sidewalls (CP12s) of the second part (CP12) may have a straight profile. The second width (W2), defined as the width of the second part (CP12) in the horizontal direction (e.g., the first direction (D1)), may be constant in the third direction (D3). The second width (W2) may be smaller than the maximum value of the first width (W1). The maximum value of the second width (W2) may be less than or equal to the top width of the first part (CP11).

[0096] According to the embodiments, the second width (W2) may decrease monotonically as it goes toward the third direction (D3). In this case, the uppermost width (Wt) of the second part (CP12) may be smaller than the average of the second width (W2).

[0097] According to other embodiments, the second width (W2) may increase monotonically as it moves toward the third direction (D3). In this case, the uppermost width (Wt) of the second part (CP12) may be greater than the average of the second width (W2). Even in this case, the uppermost width (Wt) of the second part (CP12) may be smaller than the maximum value of the first width (W1).

[0098] The ratio of the maximum value of the first width (W1) to the top width (Wt) of the second part (CP12) may be, for example, about 100% to about 110%. According to the embodiments, the ratio of the maximum value of the first width (W1) to the top width (Wt) of the second part (CP12) may be about 100% to about 105%. In this case, the top width (Wt) of the second part (CP12) may be, for example, about 90 nm to about 120 nm.

[0099] By providing an insulating pad (NP) surrounding the second part (CP12) of the first contact plug (CP1), the bowing phenomenon of the first contact plug (CP1) (i.e., the ratio of the maximum value of the first width (W1) to the top width (Wt) of the second part (CP12) becomes 100% or more) can be suppressed, the tilting of the side wall (CP12s) of the second part (CP12) of the first contact plug (CP1) with respect to the third direction (D3) can be suppressed, and the dispersion of the top width (Wt) in the plurality of first contact plugs (CP1) can be reduced. Accordingly, the formation of a bridge between adjacent first and second contact plugs (CP1, CP2) and second vertical channel structures (VS2) can be prevented and / or minimized, and it can be easier to control the height of each of the first and second contact plugs (CP1, CP2) and second vertical channel structures (VS2) in the third direction (D3). As a result, the electrical characteristics and reliability of the three-dimensional semiconductor memory device according to the present invention can be improved.

[0101] FIG. 6b is an enlarged cross-sectional view illustrating a part of a three-dimensional semiconductor memory device according to embodiments of the present invention, corresponding to part A of FIG. 5b. For convenience of explanation, the description of matters substantially identical to those described with reference to FIG. 5b and FIG. 6a is omitted below, and the differences are described in detail.

[0102] Referring to FIGS. 5b and FIGS. 6b, the sidewall of the first part (CP11) of the first contact plug (CP1) may include a first sidewall (CP11s1) and a second sidewall (CP11s2). The first sidewall (CP11s1) may be connected to the sidewall (CP12s) of the second part (CP12) without step (i.e., with a constant slope). The second sidewall (CP11s2) may extend below the first sidewall (CP11s1). The first sidewall (CP11s1), like the sidewall (CP12s) of the second part (CP12), may have a straight profile, and the second sidewall (CP11s2) may have a convex curved profile (e.g., a bow profile).

[0103] At the position corresponding to the first side wall (CP11s1), the first width (W1) of the first part (CP11) may be constant, and at the position corresponding to the second side wall (CP11s2), the first width (W1) of the first part (CP11) may increase and then decrease as it moves toward the third direction (D3).

[0105] FIG. 7 is an enlarged cross-sectional view for explaining a part of a three-dimensional semiconductor memory device according to embodiments of the present invention, corresponding to part B of FIG. 5b.

[0106] Referring to FIGS. 5b and FIG. 7, a portion of one of the first vertical channel structures (VS1) is shown, which includes a source structure (SC) comprising first and second source conduction patterns (SCP1, SCP2), a data storage pattern (DSP), a vertical semiconductor pattern (VSP), a buried insulation pattern (VI), and a lower data storage pattern (DSPr). For convenience of explanation, a single stacked structure (ST) and a single first vertical channel structure (VS1) are described below, but the following description may be applied substantially the same to other first vertical channel structures (VS1) that penetrate other stacked structures (ST).

[0107] The data storage pattern (DSP) may include a blocking insulating layer (BLK), a charge storage layer (CIL), and a tunneling insulating layer (TIL) stacked in sequence. The blocking insulating layer (BLK) may be adjacent to a stacked structure (ST) or a source structure (SC), and the tunneling insulating layer (TIL) may be adjacent to a vertical semiconductor pattern (VSP). The charge storage layer (CIL) may be interposed between the blocking insulating layer (BLK) and the tunneling insulating layer (TIL). The blocking insulating layer (BLK) may cover the inner wall of each of the vertical channel holes (CH).

[0108] The blocking insulating layer (BLK), the charge storage layer (CIL), and the tunneling insulating layer (TIL) may extend in a third direction (D3) between the stacked structure (ST) and the vertical semiconductor pattern (VSP). Due to the Fowler-Nordheim tunneling phenomenon induced by the voltage difference between the vertical semiconductor pattern (VSP) and the gate electrodes (EL), the data storage pattern (DSP) can store and / or change data. For example, the blocking insulating layer (BLK) and the tunneling insulating layer (TIL) may comprise silicon oxide, and the charge storage layer (CIL) may comprise silicon nitride or silicon oxynitride.

[0109] Among the source structures (SC), the first source conductive pattern (SCP1) can be in contact with the vertical semiconductor pattern (VSP), and the second source conductive pattern (SCP2) can be spaced apart from the vertical semiconductor pattern (VSP) with the data storage pattern (DSP) in between. The first source conductive pattern (SCP1) can be spaced apart from the buried insulating pattern (VI) with the vertical semiconductor pattern (VSP) in between.

[0110] More specifically, the first source conduction pattern (SCP1) may include protrusions (SCP1bt) located at a level higher than the lower surface (SCP2b) of the second source conduction pattern (SCP2) or at a level lower than the lower surface (SCP1b) of the first source conduction pattern (SCP1). However, the protrusions (SCP1bt) may be located at a level lower than the upper surface (SCP2a) of the second source conduction pattern (SCP2). In the protrusions (SCP1bt), for example, the surface in contact with the data storage pattern (DSP) or the lower data storage pattern (DSPr) may have a curved shape.

[0112] FIGS. 8, 9, and 10 are cross-sectional views illustrating a method for manufacturing a three-dimensional semiconductor memory device according to embodiments of the present invention, each corresponding to a cross-section obtained by cutting FIG. 5a along the line I-I'. Hereinafter, a method for manufacturing a three-dimensional semiconductor memory device according to embodiments of FIGS. 5a and 5b will be described in detail with reference to FIGS. 8, 9, and 10.

[0113] Referring to FIG. 8, a first substrate (10) comprising a first region (R1), a second region (R2), and a third region (R3) may be provided. A device isolation film (11) defining an active region may be formed within the first substrate (10). The device isolation film (11) may be formed by forming a trench on the first substrate (10) and filling the trench with silicon oxide.

[0114] Peripheral circuit transistors (PTRs) may be formed on the active region defined by the device isolation layer (11). Peripheral circuit contact plugs (31) and peripheral circuit wiring (33) connected to the peripheral source / drain regions (29) of the peripheral circuit transistors (PTRs) may be formed. A first insulating layer (30) covering the peripheral circuit transistors (PTRs), peripheral circuit contact plugs (31), and peripheral circuit wiring (33) may be formed.

[0115] A second substrate (100) and lower insulating patterns (101) may be formed on a first insulating film (30). Forming the second substrate (100) and lower insulating patterns (101) may include forming a semiconductor film on the first insulating film (30), patterning the semiconductor film until the upper surface of the first insulating film (30) is exposed, forming an insulating film on the first insulating film (30) and the semiconductor film, and flattening the insulating film until the upper surface of the semiconductor film is exposed. By the flattening process, the upper surfaces of the lower insulating patterns (101) and the upper surface of the second substrate (100) may substantially form a co-plane. In the following, substantially forming a co-plane means that a flattening process may be performed. The flattening process may be performed, for example, through a chemical mechanical polishing (CMP) process or an etch back process.

[0116] A lower sacrificial film (103) and a lower semiconductor film (105) may be formed sequentially on the second substrate (100) and the lower insulating patterns (101). The lower sacrificial film (103) may be formed of silicon nitride, for example. The lower sacrificial film (103) may be formed by stacking a plurality of insulating films sequentially, for another example. The lower semiconductor film (105) may be formed of the same material as the second substrate (100), for example.

[0117] A mold structure (MS) may be formed on a lower semiconductor film (105). Forming the mold structure (MS) may include alternately and repeatedly forming interlayer insulating films (ILD) and sacrificial films (SL) on the lower semiconductor film (105), forming a step structure on a second region (R2) by a trimming process, and increasing the thickness of each end of the sacrificial films (SL). The trimming process may include forming a mask pattern covering the upper surface of the uppermost of the interlayer insulating films (ILD), patterning some of the interlayer insulating films (ILD) and sacrificial films (SL) through the mask pattern, reducing the area of ​​the mask pattern, and patterning some of the interlayer insulating films (ILD) and sacrificial films (SL) through the mask pattern having the reduced area. Reducing the area of ​​the mask pattern and patterning may be repeated alternately. By the above trimming process, the mold structure (MS) can have a stepped structure on the second region (R2).

[0118] A second insulating film (110) covering the stepped structure of the mold structure (MS) on the second region (R2) and the second substrate (100) on the third region (R3) may be formed. A third insulating film (120) may be formed on the second insulating film (110). The third insulating film (120) may substantially co-plane with the uppermost surface of the mold structure (MS) (i.e., the upper surface of the uppermost of the interlayer insulating films (ILD)).

[0119] Referring to FIG. 9, a mask pattern (M) may be formed on a mold structure (MS) and a third insulating film (120). The mask pattern (M) may have a plurality of openings. At least some of the plurality of openings may overlap with the lower insulating patterns (101) in a third direction (D3). The third insulating film (120) exposed by the openings of the mask pattern (M) may be etched.

[0120] Referring to FIG. 10, an insulating pad film (NL) can be formed that covers the mold structure (MS) and the third insulating film (120) by filling the space etched by the third insulating film (120). The insulating pad film (NL) can be formed of an insulating material different from that of the second and third insulating films (110, 120). For example, the second and third insulating films (110, 120) can be formed of silicon oxide, and the insulating pad film (NL) can be formed of silicon nitride.

[0121] Referring again to FIG. 5a and FIG. 5b together with FIG. 10, insulating pads (NP) can be formed by a planarization process. The upper surfaces of the insulating pads (NP) can substantially co-plane with the upper surface of the third insulating film (120).

[0122] Vertical channel holes (CH) defining a space to be formed for first vertical channel structures (VS1) on the first region (R1) may be formed. Each of the vertical channel holes (CH) may penetrate the mold structure (MS), the lower semiconductor film (105), and the lower sacrificial film (103) to expose the second substrate (100).

[0123] First contact holes (CTH1) defining a space to be formed for first contact plugs (CP1) on the second region (R2) may be formed. Second contact holes (CTH2) defining a space to be formed for second contact plugs (CP2) on the third region (R3) may be formed. Each of the first contact holes (CTH1) may penetrate one of the insulating pads (NP), the second insulating film (110), the mold structure (MS), the lower semiconductor film (105), the lower sacrificial film (103), and one of the lower insulating patterns (101). The second contact hole (CTH2) may penetrate one of the insulating pads (NP), the second insulating film (110), and one of the lower insulating patterns (101). Each of the first and second contact holes (CTH1, CTH2) can further penetrate at least a portion of the first insulating film (30) and expose one of the peripheral circuit wirings (33) of the peripheral circuit structure (PS).

[0124] Vertical channel holes (CH) defining a space to be formed around the first contact holes (CTH1) on the second region (R2) can be formed. Each of the vertical channel holes (CH) on the second region (R2) can penetrate one of the insulating pads (NP), the second insulating film (110), the mold structure (MS), the lower semiconductor film (105), and the lower sacrificial film (103) to expose the second substrate (100).

[0125] First and second vertical channel structures (VS1, VS2) may be formed within the vertical channel holes (CH), and first and second contact plugs (CP1, CP2) may be formed within the first and second contact holes (CTH1, CTH2). Forming the first contact plugs (CP1) may include recessing the sacrificial membranes (SL) exposed by the first contact holes (CTH1), filling the space where the sacrificial membranes (SL) are recessed and the first contact holes (CTH1) with an insulating material, removing the insulating material from the first contact holes (CTH1), and filling the first contact holes (CTH1) with a conductive material. The insulating material remaining in the space where the sacrificial membranes (SL) are recessed may be referred to as isolated insulating patterns (IP). Each end of the sacrificial films (SL) may have a thicker thickness than other sacrificial films (SL) so that the degree of recessing may be less, and no separation insulation patterns (IP) may remain at each end of the sacrificial films (SL). During the process of recessing the sacrificial films (SL), the lower sacrificial film (103) and the lower semiconductor film (105) may also be recessed together, and the insulating material remaining in the space where the lower sacrificial film (103) and the lower semiconductor film (105) are recessed may also be referred to as a separation insulation pattern (IP).

[0126] First trenches (TR1) can be formed across the mold structure (MS) in a first direction (D1). The sacrificial membranes (SL) and the lower sacrificial membrane (103) exposed by the first trenches (TR1) can be optionally removed.

[0127] The selective removal of the sacrificial films (SL) and the lower sacrificial film (103) can be performed, for example, through a wet etching process using an etching solution. During the selective removal process of the sacrificial films (SL) and the lower sacrificial film (103), the interlayer insulating films (ILD) may not be removed.

[0128] By the above wet etching process, a first gap region defined as a space where the lower sacrificial film (103) is removed and a second gap region defined as a space where the sacrificial films (SL) are removed may be formed. By the first and second gap regions, a portion of the sidewalls of the first and second vertical channel structures (VS1, VS2) may be exposed. More specifically, by the first gap region, a portion of the sidewall of the vertical semiconductor pattern (VSP) of each of the first and second vertical channel structures (VS1, VS2) may be exposed.

[0129] A first source conduction pattern (SCP1) that fills the first gap region may be formed. The lower semiconductor film (105) on the first source conduction pattern (SCP1) may be referred to as a second source conduction pattern (SCP2). Consequently, a source structure (SC) including the first and second source conduction patterns (SCP1, SCP2) may be formed.

[0130] Gate electrodes (EL) that fill the second gap regions can be formed. Consequently, a stacked structure (ST) including gate electrodes (EL) and interlayer insulating films (ILD) between them can be formed. Subsequently, first separation structures (SS1) that fill the first trenches (TR1) can be formed.

[0131] On the first region (R1), bit line contact plugs (BP) can be formed that penetrate the fourth insulating film (150) and are connected to the conductive pads (PAD) of each of the first vertical channel structures (VS1). Bit lines (BL) that are electrically connected to the first vertical channel structures (VS1) through the bit line contact plugs (BP) can be formed on the fourth insulating film (150).

[0132] On the second region (R2), first and second conductive lines (CL1, CL2) may be formed on the fourth insulating film (150) through first and second contact plugs (CP1, CP2) connected to one of the gate electrodes (EL) and / or one of the peripheral circuit transistors (PTR).

[0134] FIG. 11 is a cross-sectional view illustrating a three-dimensional semiconductor memory device according to embodiments of the present invention. Hereinafter, for convenience of explanation, descriptions of matters substantially identical to those described with reference to FIG. 5a and 5b are omitted, and the differences are described in detail.

[0135] Referring to FIG. 11, the stacked structure (ST) may include alternately and repeatedly stacked interlayer insulating films (ILDa, ILDb) and gate electrodes (ELa, ELb). More specifically, the stacked structure (ST) may include a lower stacked structure (STa) on the second substrate (100) and an upper stacked structure (STb) on the lower stacked structure (STa). The lower stacked structure (STa) may include alternately and repeatedly stacked first interlayer insulating films (ILDa) and first gate electrodes (ELa), and the upper stacked structure (STb) may include alternately and repeatedly stacked second interlayer insulating films (ILDb) and second gate electrodes (ELb).

[0136] The first and second gate electrodes (ELa, ELb) may have a length in the first direction (D1) that decreases as they move away from the second substrate (100) (i.e., toward the third direction (D3). In other words, the length in the first direction (D1) of each of the first and second gate electrodes (ELa, ELb) may be greater than the length in the first direction (D1) of the electrode located immediately above the electrode. The first and second gate electrodes (ELa, ELb) may have pad portions (ELp) on the second region (R2). The pad portions (ELp) of the first and second gate electrodes (ELa, ELb) may be positioned at different locations horizontally and vertically. The pad portions (ELp) may form a stepped structure along the first direction (D1).

[0137] The lowest of the second interlayer insulating films (ILDb) may come into contact with the uppermost of the first interlayer insulating films (ILDa). For example, the thickness of the lowest of the first interlayer insulating films (ILDa) may be smaller than the thickness of each of the other interlayer insulating films (ILDa, ILDb). For example, the thickness of the uppermost of the first interlayer insulating films (ILDa) and the uppermost of the second interlayer insulating films (ILDb) may be larger than the thickness of each of the other interlayer insulating films (ILDa, ILDb). However, this is merely illustrative, and the thicknesses of the first and second interlayer insulating films (ILDa, ILDb) may vary depending on the characteristics of the semiconductor device.

[0138] On the second region (R2), a second insulating film (110) covering the stepped structure of the lower laminated structure (STa) may be provided. A third insulating film (120) may be provided on the second insulating film (110). The upper surface of the third insulating film (120) may substantially co-plane with the uppermost surface of the lower laminated structure (STa) (i.e., the upper surface of the uppermost of the first interlayer insulating films (ILDa). A fourth insulating film (150) may be provided on the upper laminated structure (STb). Between the third insulating film (120) and the fourth insulating film (150), a fifth insulating film (130) covering the stepped structure of the upper laminated structure (STb) and the third insulating film (120) may be provided. A sixth insulating film (140) may be provided on the fifth insulating film (130). The sixth insulating film (140) may be interposed between the fifth insulating film (130) and the fourth insulating film (150). The upper surface of the sixth insulating film (140) may substantially co-plane with the upper surface of the upper stacked structure (STb) (i.e., the upper surface of the uppermost of the second interlayer insulating films (ILDb)). Each of the second to sixth insulating films (110, 120, 130, 140, 150) may comprise, for example, silicon oxide, silicon nitride, and / or silicon oxynitride. The third insulating film (120) and the sixth insulating film (140) may comprise, for example, silicon oxide doped with impurities.

[0139] Each of the first and second vertical channel structures (VS1, VS2) may include a lower vertical channel structure (VSa) provided inside each of the lower vertical channel holes (CHa) penetrating the lower stacked structure (STa), and an upper vertical channel structure (VSb) provided inside each of the upper vertical channel holes (CHb) penetrating the upper stacked structure (STb). The lower vertical channel structure (VSa) may be connected to the upper vertical channel structure (VSb) in a third direction (D3).

[0140] Each of the upper and lower vertical channel structures (VSa, VSb) may have a width that increases toward, for example, the third direction (D3). The uppermost width of the lower vertical channel structure (VSa) may be, for example, greater than the lowermost width of the upper vertical channel structure (VSb). In other words, the side walls of each of the first and second vertical channel structures (VS1, VS2) may have a step at the boundary surface between the lower vertical channel structure (VSa) and the upper vertical channel structure (VSb). However, this is merely illustrative and the invention is not limited thereto, and the side walls of each of the first and second vertical channel structures (VS1, VS2) may have three or more steps at different levels, or may be flat without steps.

[0141] Each of the first and second contact plugs (CP1, CP2) may include a lower contact plug (CPa) penetrating the lower laminated structure (STa) or the second and third insulating films (110, 120) and an upper contact plug (CPb) penetrating the upper laminated structure (STb) or the fifth and sixth insulating films (130, 140). The lower contact plug (CPa) may be connected to the upper contact plug (CPb) in a third direction (D3).

[0142] Each of the upper and lower contact plugs (CPa, CPb) may have a width that increases toward, for example, the third direction (D3). The uppermost width of the lower contact plug (CPa) may be, for example, greater than the lowermost width of the upper contact plug (CPb). In other words, the side walls of each of the first and second contact plugs (CP1, CP2) may have a step at the interface between the lower contact plug (CPa) and the upper contact plug (CPb). However, this is merely illustrative and the invention is not limited thereto, and the side walls of each of the first and second contact plugs (CP1, CP2) may have three or more steps at different levels, or may be flat without a step.

[0143] Lower insulating pads (NPa) may be provided within the third insulating film (120) to surround the upper portion of the lower vertical channel structure (VSa) of each of the second vertical channel structures (VS2) and the upper portion of the lower contact plug (CPa) of each of the first and second contact plugs (CP1, CP2). Each of the lower insulating pads (NPa) may be surrounded by the third insulating film (120) in a planar view. Lower insulating pads (NPa) may not be provided on the upper portion of the lower vertical channel structure (VSa) and the upper portion of the lower contact plug (CPa) penetrating the uppermost portion of the first interlayer insulating films (ILDa).

[0144] Upper insulating pads (NPb) may be provided within the sixth insulating film (140) to surround the upper vertical channel structure (VSb) of each of the second vertical channel structures (VS2) and the upper contact plug (CPb) of each of the first and second contact plugs (CP1, CP2). Each of the upper insulating pads (NPb) may be surrounded by the sixth insulating film (140) in a planar view.

[0145] The lower insulating pads (NPa) and the upper insulating pads (NPb) may include insulating materials different from the second to sixth insulating films (110, 120, 130, 140, 150). For example, the second to sixth insulating films (110, 120, 130, 140, 150) may include silicon oxide, and the lower insulating pads (NPa) and the upper insulating pads (NPb) may include silicon nitride.

[0147] FIG. 12 is a cross-sectional view illustrating a three-dimensional semiconductor memory device according to embodiments of the present invention. FIG. 13a, FIG. 13b, and FIG. 13c are enlarged cross-sectional views illustrating parts of a three-dimensional semiconductor memory device according to embodiments of the present invention, each corresponding to part C of FIG. 12. Hereinafter, for convenience of explanation, descriptions of matters substantially identical to those described with reference to FIG. 5a, FIG. 5b, and FIG. 11 are omitted, and the differences are described in detail.

[0148] Referring to FIGS. 12 and 13a, the upper contact plug (CPb) of each of the first and second contact plugs (CP1, CP2) may include a lower portion (LCP) and an upper portion (UCP). The upper portion (UCP) may be provided on the lower portion (LCP). The width of the upper portion (UCP) in the horizontal direction (e.g., the first direction (D1)) may be greater than the width of the lower portion (LCP) in the horizontal direction (e.g., the first direction (D1)). The lowest width of the upper portion (UCP) may be greater than the highest width of the lower portion (LCP). At least a portion of the lower surface (UCPb) of the upper portion (UCP) may be in contact with the fifth insulating film (130) without contacting the lower portion (LCP). In other words, the upper contact plug (CPb) of each of the first and second contact plugs (CP1, CP2) may have a step at the interface between the lower part (LCP) and the upper part (UCP).

[0149] The lower surface (UCPb) of the upper portion (UCP) may be located at a lower level than, for example, the lower surface (140b) of the sixth insulating film (140). According to embodiments, the lower surface (UCPb) of the upper portion (UCP) may be substantially co-planar with or located at a higher level than the lower surface (140b) of the sixth insulating film (140). However, even then, the lower surface (UCPb) of the upper portion (UCP) may be located at a lower level than the lower surface (150b) of the fourth insulating film (150).

[0150] Referring to FIGS. 12 and 13b, an upper insulating pad (NPb) covering the sidewall of an upper portion (UCPb) may be provided between the lower surface (140b) of the sixth insulating film (140) and the lower surface (150b) of the fourth insulating film (150). In this case, the upper insulating pad (NPb) may be a portion that remains without being removed during the process of forming the upper portion (UCP) of the upper contact plug (CPb). The upper insulating pad (NPb) may be provided within the sixth insulating film (140).

[0151] Referring to FIG. 12 and FIG. 13c, the upper surface (UCPt) of the upper portion (UCP) of the upper contact plug (CPb) can be substantially co-plane with, for example, the lower surface (150b) of the fourth insulating film (150).

[0153] FIGS. 14 and 15 are cross-sectional views illustrating a method for manufacturing a three-dimensional semiconductor memory device according to embodiments of the present invention. Hereinafter, a method for manufacturing a three-dimensional semiconductor memory device according to embodiments of FIG. 12 will be described in detail with reference to FIGS. 14 and 15.

[0154] Referring to FIG. 14, a peripheral circuit structure (PS), a second substrate (100), lower insulating patterns (101), a lower mold structure (MSa), second and third insulating films (110, 120) covering them, and lower insulating pads (NPa) within the third insulating film (120) can be formed by a method substantially identical to that described with reference to FIG. 8 through 10.

[0155] Subsequently, lower vertical channel holes (CHa) penetrating the lower mold structure (MSa) and lower contact holes (CTHa) penetrating the lower mold structure (MSa) and / or the second and third insulating films (110, 120) may be formed. The lower vertical channel holes (CHa) and the lower contact holes (CTHa) may be filled, for example, with polysilicon.

[0156] Additionally, an upper mold structure (MSb), fifth and sixth insulating films (130, 140), and upper insulating pads (NPb) within the sixth insulating film (140) can be formed on a lower mold structure (MSa) and a third insulating film (120) by a method substantially identical to that described with reference to FIGS. 8 to 10.

[0157] Subsequently, upper vertical channel holes (CHb) penetrating the upper mold structure (MSb), and upper contact holes (CTHb) penetrating the upper mold structure (MSb) and / or the fifth and sixth insulating films (130, 140) may be formed. Each of the upper vertical channel holes (CHb) may be connected to each of the lower vertical channel holes (CHa) in a third direction (D3), and each of the upper contact holes (CTHb) may be connected to each of the lower contact holes (CTHa) in a third direction (D3). The upper vertical channel holes (CHb) and the upper contact holes (CTHb) may be filled, for example, with polysilicon. Consequently, sacrificial pillars (SP) filling the upper and lower vertical channel holes (CHa, CHb) and the upper and lower contact holes (CTHa, CTHb) may be formed.

[0158] Referring to FIG. 15, sacrificial pillars (SP) filling the upper and lower vertical channel holes (CHa, CHb) are removed, and first and second vertical channel structures (VS1, VS2) filling the space where the sacrificial pillars (SP) were removed can be formed.

[0159] A fourth insulating film (150) may be formed on the upper mold structure (MSb) and the sixth insulating film (140). A plurality of openings (OP) may be formed by patterning the fourth insulating film (150) and the sixth insulating film (140). At this time, a portion of the fifth insulating film (130) and a portion of each of the sacrificial pillars (SP) may be removed together.

[0160] A portion of each of the sacrificial pillars (SP) within the upper contact holes (CTHb) may be exposed by a plurality of openings (OP). In other words, the openings (OP) may be formed at locations corresponding to the upper contact holes (CTHb).

[0161] According to the embodiments, a plurality of openings (OP) may be formed by patterning the fourth insulating film (150) and the sixth insulating film (140) prior to forming the fourth insulating film (150). At this time, an upper contact plug (CPb) as described with reference to FIG. 13c may be formed as a result.

[0162] According to other embodiments, after forming the fourth insulating film (150), the sacrificial pillars (SP) filling the upper and lower vertical channel holes (CHa, CHb) and the upper and lower contact holes (CTHa, CTHb) may be removed at once.

[0163] Referring again to FIG. 12 in conjunction with FIG. 15, sacrificial pillars (SP) exposed by openings (OP) can be removed, and first and second contact plugs (CP1, CP2) that fill the space and openings (OP) where the sacrificial pillars (SP) have been removed can be formed. Subsequently, a stacked structure (ST) including upper and lower stacked structures (STa, STb) can be formed by replacing the first and second sacrificial films (SLa, SLb) with first and second gate electrodes (ELa, ELb). Consequently, a cell array structure (CS) of a three-dimensional semiconductor memory device according to FIG. 12 can be formed by substantially the same method as described with reference to FIG. 5a and FIG. 5b in conjunction with FIG. 10.

[0165] FIG. 16 is a cross-sectional view illustrating a three-dimensional semiconductor memory device according to embodiments of the present invention. For convenience of explanation, the description of matters substantially identical to those described with reference to FIG. 5a, 5b, FIG. 11, and FIG. 12 is omitted below, and the differences are described in detail.

[0166] Referring to FIG. 16, the laminated structure (ST) may include mold pillars (MP) that extend in a third direction (D3) on a second region (R2) and contact the lower surface of a third insulating film (120). The height of the mold pillars (MP) in the third direction (D3) may increase as they move away from the first region (R1). The second insulating film (110) may fill the space between the mold pillars (MP). The mold pillars (MP) may be spaced apart horizontally from each other with a portion of the second insulating film (110) in between.

[0167] Each of the gate electrodes (EL) of the stacked structure (ST) can form a stepped structure extending toward one another between the mold pillars (MP). More specifically, the pad portions (ELp) of the gate electrodes (EL) can be located at a lower level as they move further away from each of the mold pillars (MP). The pad portions (ELp) of the gate electrodes (EL) facing each other with a portion of the second insulating film (110) in between can be located at the same level.

[0168] Contact plugs may be provided that penetrate the pad portions (ELp) of the gate electrodes (EL), and insulating pads (NP) may be provided within the third insulating film (120) at a position corresponding to the contact plugs. According to embodiments, insulating pads (NP) may also be provided within the third insulating film (120) at a position corresponding to the mold pillars (MP).

[0170] Although embodiments of the present invention have been described above with reference to the attached drawings, those skilled in the art will understand that the present invention may be implemented in other specific forms without changing its technical concept or essential features. Therefore, the embodiments described above should be understood as illustrative in all respects and not restrictive.

Claims

Claim 1 A three-dimensional semiconductor memory device comprising: a substrate including a first region and a second region extending from the first region; a stacked structure having a stepped structure on the second region, comprising interlayer insulating films and gate electrodes alternately and repeatedly stacked on the substrate; an insulating film covering the stepped structure of the stacked structure; first vertical channel structures penetrating the stacked structure on the first region and contacting the substrate; first contact plugs penetrating the insulating film and the stacked structure on the second region; and first insulating pads provided within the insulating film and surrounding the upper portion of each of the first contact plugs, wherein the first insulating pads overlap the first vertical channel structures in a horizontal direction, and the level of the lower portions of the first insulating pads is higher than the level of the upper portion of the uppermost gate electrode among the gate electrodes. Claim 2 A three-dimensional semiconductor memory device according to claim 1, further comprising: second vertical channel structures penetrating the insulating film and the stacked structure on the second region and adjacent to each of the first contact plugs; and second insulating pads provided within the insulating film and surrounding the upper portion of each of the second vertical channel structures, wherein the second insulating pads overlap the first insulating pads in the horizontal direction. Claim 3 A three-dimensional semiconductor memory device according to claim 2, wherein the insulating film comprises silicon oxide, and each of the first and second insulating pads comprises silicon nitride. Claim 4 A three-dimensional semiconductor memory device according to claim 1, wherein each of the first contact plugs comprises a first portion surrounded by the insulating film and a second portion provided on the first portion and surrounded by each of the first insulating pads, wherein the sidewall of the first portion has a convex curved profile and the location where the first width, defined by the width in the horizontal direction of the first portion, is maximum is located at a lower level than the lower surfaces of the first insulating pads. Claim 5 In claim 4, the sidewall of the second part is a three-dimensional semiconductor memory device having a straight profile. Claim 6 A three-dimensional semiconductor memory device according to claim 4, wherein the ratio of the first width to the uppermost width of the second part is 100% to 110%. Claim 7 A three-dimensional semiconductor memory device according to claim 6, wherein the uppermost width of the second part is 90 nm to 120 nm. Claim 8 A three-dimensional semiconductor memory device according to claim 1, wherein the stacked structure comprises a lower stacked structure on the substrate and an upper stacked structure on the lower stacked structure, the insulating film comprises a lower insulating film covering the lower stacked structure and an upper insulating film covering the upper stacked structure, each of the first contact plugs comprises a lower contact plug penetrating the lower stacked structure and the lower insulating film, and an upper contact plug penetrating the upper stacked structure and the upper insulating film, and the first insulating pads comprise lower insulating pads provided within the lower insulating film and surrounding the upper portion of the lower contact plug, and upper insulating pads provided within the upper insulating film and surrounding the upper portion of the upper contact plug. Claim 9 A three-dimensional semiconductor memory device according to claim 8, wherein the upper contact plug comprises a lower part and an upper part, and the lowest width of the upper part is greater than the highest width of the lower part. Claim 10 In claim 1, the stacked structure comprises mold pillars extending vertically on the second region, forming a three-dimensional semiconductor memory device.

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