Transistor device

Abstract

In one embodiment, a transistor device is provided comprising: a semiconductor body having a substantially planar main surface; a source region extending to the main surface and having a first conductivity type; a body region extending to the main surface and having a second conductivity type—the body region forms an interface with the source region—a drain region extending to the main surface and having a first conductivity type; a drift region having a first conductivity type and extending between the body region and the drain region; and a gate electrode disposed transversely on the main surface between the source region and the drain region and electrically insulated from the semiconductor body by an insulating structure. The insulating structure comprises a gate dielectric disposed on the main surface and a shallow trench disposed within the drift region and filled with an electrical insulating material. The shallow trench has at least a partially wedge shape, and the electrical insulating material has an upper surface that is substantially planar and extends substantially parallel to the main surface of the semiconductor body.

Description

Background Technology

[0001] To date, transistors used in power electronics applications have generally been manufactured from silicon (Si) semiconductor materials. Common transistor devices for power applications include Si CoolMOS®, Si OptiMOS®, Si Power MOSFETs, and Si Insulated Gate Bipolar Transistors (IGBTs). Power devices capable of high-current switching and / or operation at higher voltages with low on-state resistance (RDSon) and high breakdown voltage are desirable.

[0002] Lateral field-effect transistors, such as LDMOS (Lateral Diffused Metal Oxide Semiconductor) transistors, can be fabricated using a dual diffusion process having drain, drift, and source regions extending to the main surface. Typically, a field plate is placed on a field oxide extending along the drift region adjacent to the main surface to lower RDSon for a given breakdown voltage. The field oxide can be formed using the LOCOS (Local Oxidation of Silicon) process. The breakdown voltage of a semiconductor device having such a field plate structure is influenced by dielectric properties and the vertical thickness of the field oxide. However, as the LOCOS field oxide becomes thicker, the on-state resistance Ron may increase.

[0003] U.S. Patent No. 8,686,505 discloses an integrated semiconductor device having a field-effect structure having an insulating structure within a trench such that a field-dielectric portion forms a drift region and a second horizontal interface and a third horizontal interface. Since the field-dielectric portion can be appropriately thickened for this field-effect structure, the breakdown voltage can be increased for the field-effect structure having the highest rated breaking capability without significantly reducing the on-resistance. Accordingly, an integrated semiconductor device having a structure with different rated breaking capabilities can be provided.

[0004] Accordingly, it is necessary to improve the electric field compensation structure in horizontal transistor devices.

[0005] In one embodiment, a transistor device is provided comprising a semiconductor body having a substantially planar main surface, a source region extending to the main surface and having a first conductivity type, a body region extending to the main surface and having a second conductivity type—the body region forms an interface with the source region—a drain region extending to the main surface and having a first conductivity type, a drift region having a first conductivity type and extending between the body region and the drain region, and a gate electrode. The gate electrode is disposed transversely on the main surface between the source region and the drain region and is electrically insulated from the semiconductor body by an insulating structure. The insulating structure comprises a gate dielectric disposed on the main surface and a shallow trench disposed within the drift region and filled with an electrical insulating material. The shallow trench has at least a partially wedge shape. The electrical insulating material has an upper surface that is substantially planar and extends substantially parallel to the main surface of the semiconductor body.

[0006] In some embodiments, the shallow trench has a base that extends into the semiconductor body at an angle α with respect to the main surface from the gate dielectric toward the drain region.

[0007] In some embodiments, the range of the inclination angle α is from 0.8° to 8.8°.

[0008] In some embodiments, the base extends into the semiconductor body at an angle α with respect to the main surface in the first portion and extends substantially parallel to the main surface in the second portion.

[0009] In some embodiments, the base of the shallow trench extends to a side wall that extends substantially perpendicularly to the main surface.

[0010] In some embodiments, the drain region contacts the insulating material within the shallow trench and forms the sidewall of the shallow trench.

[0011] In some embodiments, the transistor device further includes a doping layer having a first conductivity type formed in the semiconductor body. The doping layer forms the base of a shallow trench and is electrically coupled to the drain region.

[0012] In some embodiments, the transistor device further includes a field plate covering at least 50% of the length of a shallow trench on the main surface. The field plate may be integral with the gate electrode or may be separate from the gate electrode.

[0013] In some embodiments, the transistor device further includes a field plate extension comprising one or more portions disposed between the field plate and the drain region, spaced apart from the main surface by a distance greater than the distance between the field plate and the main surface.

[0014] In some embodiments, portions of the field plate extensions extend substantially parallel to the main surface and are electrically coupled to the field plate by conductive vias extending substantially perpendicularly to the main surface.

[0015] In some embodiments, the field plate extension comprises two or more parts forming staggered field plate extensions.

[0016] In some embodiments, one or more ends of the portion facing toward the drain area form an angle of inclination α' with respect to the main surface that is substantially the same as the angle of inclination α formed between the base of the shallow trench and the main surface.

[0017] In some embodiments, the transistor device further comprises a superjunction structure disposed in a drift region below a shallow trench. The superjunction structure comprises one or more first elongated doping regions of a first conductivity type and one or more second elongated doping regions of a second conductivity type, each of which has a length extending substantially parallel to the base of the shallow trench.

[0018] In some embodiments, the transistor device further comprises a first doped contact region having a first conductivity type and a second doped contact region having a second conductivity type. The first doped contact region is disposed on a first surface of the superjunction structure and is electrically coupled to the first doped region and drain region of the superjunction structure. The second doped contact region is disposed on a second surface of the superjunction structure, and the second surface faces the first surface. The second doped contact region is electrically coupled to a body contact portion on the main surface of the second doped region.

[0019] In some embodiments, the first doped contact area forms the base of a shallow trench.

[0020] In some embodiments, the first and second contact regions extend across the super-bonded structure.

[0021] In some embodiments, the second doped contact region is electrically coupled to a highly doped body contact that forms an interface with the source region by a doped region extending perpendicularly to the main surface.

[0022] In some embodiments, the shallow trench includes a first sidewall formed by a drain region, and the superjunction structure extends to the main surface located below the gate dielectric.

[0023] In some embodiments, the interface between the first elongated doping region and the second elongated doping region of the superjunction structure is positioned substantially perpendicular to the base of the shallow trench.

[0024] In one embodiment, a transistor device is provided comprising: a semiconductor body having a main surface; a source region extending to the main surface and having a first conductivity type; a body region extending to the main surface and having a second conductivity type—the body region forms an interface with the source region—a drain region extending to the main surface and having a first conductivity type; a drift region having a first conductivity type and extending between the body region and the drain region; and a gate electrode disposed transversely on the main surface between the source region and the drain region and electrically insulated from the semiconductor body by an insulating structure. The insulating structure comprises a gate dielectric disposed on the main surface and a shallow trench disposed within the drift region. The transistor device further comprises a superjunction structure disposed in the drift region. The superjunction structure comprises at least one first elongated doping region of the first conductivity type and at least one second elongated doping region of the second conductivity type, each of which has a length extending parallel to the main surface. A first doped contact region having a first conductivity type is disposed on a first surface of a superjunction structure, and the first doped contact region is electrically coupled to at least one first elongated doped region and a drain region of the superjunction structure. A second doped contact region having a second conductivity type is disposed on a second surface opposite to the first surface of the superjunction structure, and the second doped contact region is electrically coupled to at least one second elongated doped region of the superjunction structure and a body contact portion of the main surface.

[0025] In some embodiments, the first doped contact area forms the base of a shallow trench.

[0026] In some embodiments, the first and second contact regions extend across the entire super-joined structure.

[0027] In some embodiments, the second doped contact region is electrically coupled to a highly doped body contact that forms an interface with the source region by a doped region extending perpendicularly to the main surface.

[0028] In some embodiments, the shallow trench includes a first sidewall formed by a drain area.

[0029] In some embodiments, the superjunction structure extends to the main surface below the gate dielectric and forms a second sidewall opposite the first sidewall of the shallow trench.

[0030] In some embodiments, the first sidewall of the shallow trench extends substantially perpendicularly to the main surface.

[0031] In some embodiments, the super-bonded structure extends toward the main surface at an angle of inclination with respect to the main surface, and the angle of inclination is 45° to 89°.

[0032] In some embodiments, the interface between the first slender doping region and the second slender doping region of the superjunction structure is positioned substantially perpendicular to the main surface.

[0033] Those skilled in the art will be able to understand the additional features and benefits by reading the following detailed description and examining the attached drawings. Brief explanation of the drawing

[0034] Examples in the drawings are not necessarily scaled relative to one another. Similar reference numbers indicate corresponding similar parts. Features of the various illustrated embodiments may be combined unless they exclude one another. Embodiments are illustrated in the drawings and described in detail in the following description. FIG. 1 is a cross-sectional view of a transistor device according to one embodiment. FIG. 2 is a cross-sectional view of a transistor device according to one embodiment. FIG. 3 is a cross-sectional view of a transistor device according to one embodiment. FIG. 4 is a cross-sectional view of a transistor device according to one embodiment. FIG. 5a is a perspective view of a transistor device according to one embodiment. FIG. 5b is a cross-sectional view of the transistor device of FIG. 5a according to one embodiment. FIG. 6 is a cross-sectional view of a transistor device according to one embodiment. FIG. 7 is a cross-sectional view of a transistor device according to one embodiment. FIG. 8a is a perspective view of a transistor device according to one embodiment. FIG. 8b is a cross-sectional view of the transistor device of FIG. 8a according to one embodiment. Specific details for implementing the invention

[0035] In the following detailed description, reference is made to the accompanying drawings, which form part of this specification and illustrate specific embodiments that may be used to carry out the invention. In this regard, directional terms such as "upper," "lower," "forward," "rear," "leading," and "following" are used with reference to the directions of the drawings. Since the components of the embodiments may be located in a number of different directions, directional terms are used for illustrative purposes only and are not intended to be limiting in any way. It should be understood that other embodiments may be used and that structural or logical modifications may be made without departing from the scope of the invention. The following detailed description should not be taken in a limiting sense, and the scope of the invention is defined by the appended claims.

[0036] Many embodiments will be described below. In this case, identical structural features are identified by the same or similar reference symbols in the drawings. In the context of this description, "transverse" or "transverse direction" should be understood to mean a direction or range generally parallel to the transverse range of the semiconductor material or semiconductor carrier. Thus, the lateral direction generally extends parallel to these surfaces or sides. On the other hand, the term "vertical" or "vertical direction" is understood to mean a direction generally orthogonal to these surfaces or sides, that is, to the lateral direction. Thus, the vertical direction is the thickness direction of the semiconductor material or semiconductor carrier.

[0037] In this specification, when an element such as a layer, region, or substrate is described as being "on" or extending "up" another element, that element may be located directly above or extending directly above the other element, or intermediate elements may exist. On the other hand, when an element is described as being "on" or extending "up" another element, intermediate elements do not exist.

[0038] In this specification, when one element is referred to as being "connected" or "combined" to another element, it may be directly connected or combined to the other element, or an intermediate element may exist. On the other hand, when one element is referred to as being "directly connected" or "directly combined" to another element, no intermediate element exists.

[0039] As used herein, various device types and / or doped semiconductor regions may be identified as n-type or p-type, but this is merely for convenience of description and not intended to be limiting, and such identification may be replaced by the more general description of "first conductivity type" or "second opposite conductivity type," wherein the first type may be n-type or p-type and the second type may be p-type or n-type.

[0040] The diagram indicates relative doping concentrations by marking "-" or "+" next to the doping type "n" or "p". For example, "n-" means a doping concentration lower than that of the "n" doping region, and the "n+" doping region has a doping concentration higher than that of the "n" doping region. Doping regions with the same relative doping concentration do not necessarily have the same absolute doping concentration. For example, two different "n" doping regions may have the same or different absolute doping concentrations.

[0041] For horizontal Metal Oxide Semiconductor Field Effect Transistor (MOSFET) devices for voltages exceeding 20 V, a low on-state resistance (RDSON*A) for a given region is desirable. One challenge is to create a suitable structure that requires low processing effort but has improved electrical performance. According to the present disclosure, a compensation method, specifically field plate and / or superjunction compensation positioned close to the drift region, is applied to a horizontal transistor device to improve RDSON*A. In some embodiments, a tapered oxide structure or superjunction arrangement for field plate compensation is provided. In some embodiments, the horizontal transistor device includes a tapered field plate structure and a superjunction structure to improve RDSON*A.

[0042] In some embodiments, a tapered shallow trench isolation (STI) structure is provided to implement an improved oxide geometry for field plate compensation. This tapered shallow trench may optionally extend through an extension having a uniform depth for devices having a higher operating voltage. A stepped triangular plate array of at least two additional metal layers may also be provided on the extension.

[0043] In some embodiments, the superjunction structure is positioned below a tapered shallow STI. A continuous doping layer connected to the drain is positioned above the superjunction structure, and a continuous doping layer of the opposite doping type connected to the source is positioned below the superjunction structure. The doping layer above the superjunction structure includes charge carriers compensated by the field plate above the STI and the doping layer below the superjunction structure.

[0044] FIG. 1 is a cross-sectional view of a horizontal transistor device (10) according to one embodiment. The transistor device (10) includes a semiconductor body (11) having a planar main surface (12), a source region (13), a body region (14, 16), and a drain region (15). The source region (13) has a first conductivity type, and the body region (14, 16) has a second conductivity type opposite to the first conductivity type. The body region (14, 16) forms an interface with the source region (13). The drain region (15) has the first conductivity type. The source region (13), the body region (14), and the drain region (15) extend to the main surface (12) of the semiconductor body (11). The transistor device further includes a drift region (26) formed in the semiconductor body (11) having the first conductivity type, extending between the body region (16) and the drain region (15). The source region (13) and drain region (15) are more doped than the drift region (16).

[0045] In some embodiments, the first conductivity type is n-type and the second conductivity type is p-type. In other alternative embodiments, the first conductivity type is p-type and the second conductivity type is n-type. The semiconductor body (11) is formed of single crystal or epitaxial silicon.

[0046] The transistor device (10) further includes a gate electrode (17) disposed laterally on the main surface (12) between the source region (13) and the drain region (15). The gate electrode (17) is electrically insulated from the semiconductor surface (12) by an insulating structure (18). The insulating structure (18) includes a gate dielectric (19) disposed on the main surface (12) and a shallow trench (20) disposed over a drift region (26) and filled with an electrical insulating material (21). The shallow trench (20) has at least a partially wedge shape.

[0047] Due to the wedge shape of the shallow trench (20), the shallow trench (20) has a tapered shape and has a tip (27) that forms an acute angle (α), that is, an angle between 0.5° and 45° with the flat main surface (12).

[0048] The trench (21) has a base (22) extending into the semiconductor body (11) from the main surface (12) in the direction of the drain region (15) from the gate dielectric (19) at an angle of inclination α with respect to the planar main surface (12). Thus, the shallow trench (20) has a smaller depth on the gate side (28) than on the drain side (29). The electrical insulating material (21) filling the shallow trench (20) has an upper surface (31) extending in a plane substantially parallel to the plane of the planar main surface (12) of the semiconductor body (10) over the entire area of ​​the shallow trench (20). The angle of inclination α may be in the range of 0.8° to 8.8°, and in some embodiments may be in the range of 4.5° to 5°.

[0049] In some embodiments, as shown in FIG. 1, the base (22) of the shallow trench extends from the main surface (12) into the semiconductor body (11) at an angle of inclination (α) to a side wall (23) that extends substantially perpendicularly to the main surface (12), thereby forming a wedge shape for the shallow trench (20). The angle between the base (22) and the side wall is 90°-α°. The drain region (15) can form an interface with the electrical insulating material (12) and thus form the side wall (23) of the shallow trench (20). Due to the wedge shape of the shallow trench (20), the shallow trench (20) has a triangular cross-section.

[0050] The gate dielectric (19) is located between the gate electrode (17) and the main surface (12). In some embodiments, the drain-side edge (25) of the gate electrode (17) is in direct contact with an electrical insulating material (21) located within a shallow trench above the tip (27) of the trench (20). In these embodiments, the gate dielectric (19) is in contact with the side of the electrical insulating material (21).

[0051] In some embodiments, as illustrated in FIG. 1, the gate electrode (17) has a length such that at least 50% of its length lies over the shallow trench (20). An area of ​​insulating material (21) located adjacent to the drain region (15) is kept uncovered by the field plate (24). The portion of the gate electrode (17) located over the shallow trench (20) provides a field plate (24) that is integral with the gate electrode (17). The gate electrode (17) and the integral field plate portion (24) are substantially flat and extend substantially parallel to the main surface (12). Due to the angle of inclination α formed between the base (22) of the shallow trench (20) and the main surface (12) of the semiconductor body, an angle of inclination (α) is formed between the base (22) and the lower surface of the gate electrode (17) and the field plate (24). Due to this angle of inclination, the distance between the field plate (24) and the material of the semiconductor body (11) within the drift region (16) increases steadily from the source region (13) toward the drain region (15) as the depth of the wedge-shaped shallow trench (20) and the insulating material (21) within the trench (20) increases.

[0052] In some embodiments, the depth (d) of the shallow trench (20) located below the drain-side end (25) of the field plate (24) may be about 0.4 μm, and the length (l) of the base (22) from the main surface (12) to a point vertically below the drain-side end of the field plate may be about 5 μm. The angle of inclination α may be about 4.8°.

[0053] The transistor device (10) further comprises a first conductivity type doping layer (26) formed in the semiconductor body (11) and forming the base (22) of a shallow trench (20). The doping layer (26) is a drift region and has a doping type opposite to that of the body region (16). The doping layer (26) providing the drift region extends in the direction of the drain region (15) with an angle α from the main surface (12) to a position below the gate electrode (17). The doping layer (26) is electrically coupled to the drain region (15) and overlaps with the drain region (15). The gate-side end of the doping layer (26) forms part of the main surface (12) of the semiconductor body (11) and contacts the gate dielectric (19).

[0054] FIG. 2 is a cross-sectional view of a horizontal transistor device (30) according to a different embodiment having the insulating structure (18) shown in FIG. 1, but with the field plate (24) separated from the gate electrode (17). The gate electrode (17) extends from the source region (13) toward the drain region (15) and has a drain-side end (25) located over the tip (27) of the wedge-shaped shallow trench (20). The drain-side end (25) of the gate electrode (17) is in direct contact with the electrical insulating material (21) located within the shallow trench (20). The field plate (24) is spaced apart from the gate electrode (17) and is located between the drain-side end (25) of the gate electrode (17) and the drain region (15). The field plate (24) is substantially coplanar with the gate electrode (17) and is located directly over the electrical insulating material (21) located within the shallow trench (20), making direct contact with it. The gate electrode (17) and field plate (24) are planar.

[0055] The gap between the field plate (24) and the semiconductor material of the semiconductor body (11) and the doping layer (26) providing the drift region therewith increases from the gate end to the drain end of the field plate (24) due to the angle of inclination α formed between the base (22) of the shallow trench (20) and the flat upper surface (31) of the insulating material (21) which is substantially parallel to the main surface (12). Accordingly, the depth of the insulating material (21) located in the shallow trench (20) increases from the gate end to the drain end of the field plate (24) due to the angle of inclination α formed between the base (22) of the shallow trench (20) and the flat upper surface (31) of the insulating material (21).

[0056] In an embodiment where the field plate (24) is separated from the gate electrode (17), the separated field plate (24) may be connected to a source region or source potential, and the gate electrode may be connected or connected to an additional power source. An area of ​​insulating material located adjacent to the drain region (15) is kept uncovered by the field plate (24). The separated field plate (24) may cover 50% to less than 90% of the upper surface of the insulating material (21) within the shallow trench (20).

[0057] FIG. 3 is a cross-sectional view of a transverse transistor device (40) in which the shape of the shallow trench (20) differs from that of the transistor device (10, 30) shown in FIG. 1 and 2. Referring to FIG. 3, in some embodiments, the tapered wedge-shaped shallow trench (20) further includes an extension having substantially uniform depth. The base (22) of the trench (20) extends from the gate dielectric (19) toward the drain region (15) at an angle α with respect to the main surface (12) in the first portion (41), and has a triangular cross-section as in the embodiment shown in FIG. 1. The base (22) then extends to a second portion (42) substantially parallel to the main surface (12). While the first portion (41) has increasing depth in the direction from the gate (17) toward the drain region (15), the second portion (42) has substantially uniform depth.

[0058] The gate electrode (17) may have an integral field plate (24) as shown in FIG. 3, or the field plate (24) may be separated from the gate electrode (17). The field plate (24) has a length such that the drain-side end (20) is positioned over the wedge-shaped first portion (41) of the shallow trench (20) and the second portion (42) of the shallow trench (40) remains uncovered by the field plate (24). The transistor device (40) also includes a doping layer (26) forming a drift region that forms the base (22) of the shallow trench (22) in both the first portion and the second portion (41, 42). Thus, the doping layer (26) forming the drift region extends from the main surface at an angle α and then extends substantially parallel to the main surface to the drain region (15).

[0059] FIG. 4 is a cross-sectional view of a horizontal transistor device (50) according to one embodiment. The transistor device (50) comprises a first portion (41) having a base (22) that extends at an angle α with respect to a main surface (12) and a shallow trench (20) having the shape shown in FIG. 3. The first portion (41) extends to a second portion (42) having a substantially uniform depth from the first portion (41) to a drain region (15) in a plane substantially parallel to the plane of the main surface (12). The gate (17) has an integral field plate (24) and is positioned between the source region (13) and the drain region (15), and has a length such that the drain side end (25) of the field plate (24) is positioned over the first wedge-shaped portion (41) of the shallow trench (20).

[0060] In the embodiment illustrated in FIG. 4, the field plate (24) has an extension (51) disposed between the field plate (24) and the drain region (15). In the embodiment illustrated in FIG. 4, the field plate extension (51) includes two horizontal portions (52, 53) disposed so as to be further apart from the main surface (12) in the direction of the drain region (15). Together with the gate electrode (17) and the integrated field plate (24), the first portion (52) and the second portion (53) extend substantially parallel to the main surface (12).

[0061] The lower portion (52) of the field plate extension (51) overlaps vertically with the drain-side end (25) of the field plate (24) and is electrically connected to the lower field plate (24) by a first conductive via (54). The second portion (52) is positioned vertically above the drain-side end of the first portion (52) and overlaps with it, and is electrically connected to the first portion (52) by a second conductive via (55). The conductive vias (54, 55) extend substantially perpendicularly to the main surface (12). In the embodiment illustrated in FIG. 4, the field plate (24) may be considered to have staggered field plate extensions (51).

[0062] The drain-side ends (56, 57) of the two horizontal portions (52, 53) of the field plate extension (51) may form an angle of inclination (α') with the main surface (12). This angle of inclination (α') may be substantially the same as the angle (α) formed between the base (22) of the shallow trench (20) and the main surface (12). In this embodiment, an electric field reduction structure is provided below the main surface (12), inside the semiconductor body by the tapered shallow trench (20), and above the main surface (12) by the zigzag field plate structure (51). These two structures are arranged substantially symmetrically with respect to the main surface (12), and the distance between them increases from the gate dielectric (19) toward the drain region (15).

[0063] In another embodiment not illustrated, a field plate (24) separated from the gate electrode is provided as in the embodiment illustrated in FIG. 2. In this embodiment, the field plate (24) having an extension (51) may be electrically coupled to the source region (13) or a separate voltage supply or gate electrode.

[0064] FIG. 5a is a perspective view of a horizontal transistor device (60) according to one embodiment, and FIG. 5b is a cross-sectional view thereof. The transistor device (60) includes a semiconductor body (11) having a main surface (12), a source region (13) extending to the main surface and having a first conductivity type, and a body region (14, 16A, 16) extending to the main surface (12) and having a second conductivity type opposite to the first conductivity type. The body region (14, 16A, 16) forms an interface with the source region (13). The transistor device (60) further includes a drain region (15) having a first conductivity type and extending to the main surface (12) spaced apart from the source region (13). A transistor device (60) includes a drift region (64) having a first conductivity type and extending between a body region (16A) and a drain region (15), and a gate electrode (17) disposed laterally on a main surface (12) between a source region (13) and a drain region (15) to form a horizontal transistor device structure. The gate electrode (17) is electrically insulated from the semiconductor body (16A) by a gate insulation structure (18) comprising a gate dielectric (19) disposed on the main surface (12) and a shallow trench (20) disposed in the drift region (67).

[0065] In this embodiment, the shallow trench (20) has a substantially uniform depth along its length and has side walls (23, 23') that extend substantially perpendicularly to the main surface (12). The transistor device (60) includes a superjunction structure (61) as an electric field compensation structure. The superjunction structure (61) is positioned below a drift region (62) below the shallow trench (21) and extends to a drain region (15) that forms the side walls (23) of the shallow trench (20) below the entire area of ​​the shallow trench (21).

[0066] The superjunction structure (61) comprises at least one first elongated doping region (62) of the first conductivity type and at least one second elongated doping region (63) of the second conductivity type. The first and second elongated doping regions (62, 63) are arranged in a stack having a stacking direction (67) that extends substantially parallel to the main surface (12). Each of the first and second elongated doping regions (62, 63) has a length direction that extends from the source region (13) toward a drain region (15) that is substantially parallel to the main surface (12) and substantially perpendicular to the stacking direction (67). A PN junction (68) is formed between immediately adjacent first and second elongated doping regions (62, 63), which extends substantially perpendicular to the main surface (12), extends from the source region (13) toward the drain region (15), and has a length that is substantially parallel to the main surface (12). The first elongated doping region (62) forms the drift region (26) of the transistor device (60).

[0067] The transistor device (60) further comprises a first doped contact region (64) having a first conductivity type. The first doped contact region (64) is doped more than the first elongated doped region (62). The doping concentration of the first elongated doped region (62) may be equal to or less than the doping concentration of the contact region (64). The first doped contact region (64) is positioned on the first surface of the superjunction structure (61) and is electrically coupled to the first elongated doped region (62) and the drain region (15). The first doped contact region (64) forms part of the drift region (26) of the transistor device (60). The first doped contact region (64) may extend substantially parallel to the first main surface (12) and may be located directly above the first extended doped region (62) of the superjunction structure (61). The first doped contact area (64) may extend across the entire bottom area of ​​the trench (20) above the superjunction structure (61) and may come into contact with both the first and second doped areas (62, 63). The superjunction structure (61) is located below the base (22) of the shallow trench (20), and the first doped contact area (64) may form the base (22) of the shallow trench (20). The transistor device (60) further includes a second doped contact area (65) having a second conductivity type. The second doped contact area (65) is positioned on the second surface of the superjunction structure (61), and the second surface faces the first surface. The second doped contact area (65) is electrically coupled to a body contact portion (14) placed on the main surface (12) above the second elongated doped area (63) and the doped sinker area (66) of the super-bonded structure (61). The second doped contact area (65) may extend across the entire super-bonded structure (61) and contacts both the first and second elongated doped areas (62, 63).

[0068] As can be seen from the cross-sectional view of FIG. 5b, the second doped contact region (65) may extend within the semiconductor substrate (11) substantially parallel to the main surface (12) in a direction toward the body region (14). The second doped region (65) is electrically coupled from the main surface (12) to the body region (14) by, for example, a conductive via (66), such as a doped sinker structure.

[0069] The super-joint structure (61) generally comprises a plurality of first elongated doping regions (62) and second elongated doping regions (63) that are alternately arranged to form a plurality of PN junctions (68) each having a length substantially parallel to the main surface (12), and extends in the direction between the body region (16A) and the drain region (15). The pn junctions are arranged substantially perpendicular to the first main surface (12).

[0070] In some embodiments, the superjunction structure (61) extends to the main surface (12) to form the gate sidewall (23') of the shallow trench (20) located below the field plate (24). The opposite ends of the elongated doping regions (62, 63) extend to the drain region (15). The gate dielectric (19) may be located on the portion of the superjunction structure (61) forming the sidewall toward the gate electrode (17). The superjunction structure (61) may be considered to have an L-shape.

[0071] The first wall (23) of the shallow trench formed by the drain area (15) extends substantially perpendicularly to the main surface (12). The opposing side wall (23'), which may be formed by the first and second doping areas (62, 63) of the super-bonded structure (61), also extends substantially perpendicularly to the main surface or at an angle inclined to the main surface, so that the angle of inclination is between 45° and 89°.

[0072] In the cross-sectional view of FIG. 5b, a metal contact portion (69) for the source region (13) and body region (14), the gate electrode and field plate (24) and the drain region (15) is also shown.

[0073] In other embodiments not illustrated, a field plate (24) separated from the gate electrode is provided as described with reference to FIG. 2. In these embodiments, the field plate (24) may be electrically coupled to the source region (13) or a separate voltage supply or the gate electrode. In other embodiments not illustrated, the field plate (24) may have a field plate extension as described with reference to FIG. 4, thereby allowing the field plate (24) to be integrated with the gate electrode (17) or separated from the gate electrode.

[0074] FIG. 6 is a cross-sectional view of a horizontal transistor device (70) comprising a combination of a wedge-shaped shallow trench (20) with a triangular cross section and a superjunction structure (71) as a field compensation structure, as in the embodiment illustrated in FIG. 1 and 2. The superjunction structure (71) extends at an angle inclined with respect to the main surface (12), thereby the angle of inclination may be the same as the angle of inclination (α) of the base (22) of the shallow trench (20) so that the superjunction structure (71) extends substantially parallel to the base (22) of the shallow trench (20). The superjunction structure (71) extends into the semiconductor body (11) such that the depth from the surface (12) increases as it moves from the gate electrode (17) toward the drain region (15).

[0075] The super-junction structure (71) includes at least one first elongated doping region (72) of the first conductivity type and at least one second elongated doping region (73) of the second conductivity type. The first and second elongated doping regions (72, 73) are composed of a stack having a stacking direction (77) positioned at an angle of inclination α with respect to the main surface (12). A pn ​​junction (75) formed between the first and second elongated doping regions (72, 73) is also positioned at an angle of inclination α with respect to the main surface (12).

[0076] FIG. 6 also illustrates a doped contact region (26) that forms a drift region of the transistor device (70) and is electrically connected to the drain region (15). The doped contact region (26) forms the base of the shallow trench (20) and forms an interface with the first elongated doped region (72). The doped contact region (26) electrically couples the first elongated doped region (72) of the superjunction structure (71) to the drain region (15).

[0077] In other embodiments not illustrated, a field plate (24) separated from the gate electrode is provided as described with reference to FIG. 2. In these embodiments, the field plate (24) may be electrically coupled to the source region (13) or a separate voltage supply or the gate electrode. In other embodiments not illustrated, the field plate (24) may have a field plate extension as described with reference to FIG. 4, thereby allowing the field plate (24) to be integrated with the gate electrode (17) or separated from the gate electrode.

[0078] FIG. 7 is a cross-sectional view of a horizontal transistor device (80) comprising a wedge-shaped shallow trench (20) and a superjunction structure (71) extending at an angle α with respect to a main surface (12) similar to the transistor device (70) illustrated in FIG. 6. In this embodiment, the superjunction structure (71) comprises more than one PN junction and thus includes a plurality of first doped elongated regions (72) and second doped elongated regions (73) having opposite conductivity types and arranged alternately in the stacking direction (77). A stack of pn junctions (75) is formed, each having a length extending at an angle α with respect to the main surface (12) of the semiconductor body (11).

[0079] A first doping region (26) is also provided, which forms the base (22) of the drift region and shallow trench of the transistor device (80), extends over the entire area of ​​the superjunction structure (71), and forms an interface with the uppermost first doping region (72). The first doping region (72) extends to the drain region (15) and is electrically coupled to the drain region (15). Additionally, an electrical connection (78) for a second elongated doping region (73) of a second conductivity type, located either in front of or behind the plane of the drawing, is schematically illustrated in FIG. 7. There is an electrical connection of the drift layer (26) for all second elongated doping regions (73) on the source side, which can be arranged in three dimensions perpendicular to the cross-section, although not illustrated in FIG. 7.

[0080] In other embodiments not illustrated, a field plate (24) separated from the gate electrode is provided as described with reference to FIG. 2. In these embodiments, the field plate (24) may be electrically coupled to the source region (13) or a separate voltage supply or the gate electrode. In other embodiments not illustrated, the field plate (24) may have a field plate extension as described with reference to FIG. 4, thereby allowing the field plate (24) to be integrated with the gate electrode (17) or separated from the gate electrode.

[0081] FIG. 8a is a perspective view of a transistor device (90) comprising a shallow trench (20) having a tapered wedge shape with a triangular cross-section and a superjunction structure (61) having a shape similar to that shown in FIG. 5, and FIG. 8b is a cross-sectional view thereof. The inclined superjunction structure (61) has the shape shown in FIG. 5, having a stacking direction (67) in which a stack of first and second elongated doping regions (62, 63) extends parallel to the main surface (12). The superjunction structure (61) extends parallel to the base (22) of the wedge-shaped shallow trench (20) such that the lengths of the first and second elongated doping regions (62, 63) and the pn junction (65) extend at an angle of inclination α with respect to the main surface (12). The first elongated doping region (62) and the doped contact layer (64) provide a drift region (26) of the transistor device (90).

[0082] A first doped contact region (64) is provided between the base (22) of the shallow trench (20) and the upper surface of the superjunction structure (61). The first doped contact region (64) forms part of the drift region (26) of the transistor device and is electrically coupled to the drain region (15). A second doped contact region (65) is located on the opposite side of the superjunction structure (61) and extends further below the superjunction structure (61) and next to the body region (16A). The second doped contact region (65) has a low-resistance electrical connection to the body region (14) formed by a conductive via (66) that can be provided by a doped conductive via.

[0083] The interface between the first and second elongated doping regions (62, 63) and the pn junction extends substantially perpendicularly to the base (22) of the shallow trench (20). The superjunction structure (61) extends to the main surface (12) near the tip (27) of the shallow trench (20) located below the gate dielectric (19).

[0084] In other embodiments not illustrated, a field plate (24) separated from the gate electrode is provided as described with reference to FIG. 2. In these embodiments, the field plate (24) may be electrically coupled to the source region (13) or a separate voltage supply or the gate electrode. In other embodiments not illustrated, the field plate (24) may have a field plate extension as described with reference to FIG. 4, thereby allowing the field plate (24) to be integrated with the gate electrode (17) or separated from the gate electrode.

[0085] Spatial terms such as "below," "bottom," "lower," "above," and "upper" are used to facilitate the description of the location of one element relative to another. These terms are intended to include directions of the device other than those depicted in the drawings. Additionally, terms such as "first," "second," etc., are used to describe various elements, regions, sections, etc., and are not intended to be limiting. Similar terms indicate similar elements throughout the description.

[0086] As used herein, terms such as “having,” “comprising,” and “comprising” are open-ended terms that indicate the presence of a mentioned element or feature but do not exclude additional elements or features. Singular terms are intended to include the plural form unless the context clearly indicates otherwise. It should be understood that the features of the various embodiments described herein may be combined with one another unless specifically stated otherwise.

[0087] Although specific embodiments have been illustrated and described in this specification, those skilled in the art will understand that various other and / or equivalent implementations may substitute for the specific embodiments illustrated and described without departing from the scope of the invention. This application is intended to include any modification or variation of the specific embodiments discussed in this specification. Accordingly, the invention is intended to be limited only by the claims and their equivalents.

Claims

Claim 1 A transistor device comprises a semiconductor body having a substantially planar main surface, a source region extending to the main surface and having a first conductivity type, a body region extending to the main surface and having a second conductivity type—the body region forming an interface with the source region—a drain region extending to the main surface and having the first conductivity type, a drift region having the first conductivity type and extending between the body region and the drain region, and a gate electrode disposed transversely on the main surface between the source region and the drain region and electrically insulated from the semiconductor body by a gate insulating structure, wherein the gate insulating structure comprises a gate dielectric disposed on the main surface, and a shallow trench disposed within the drift region and filled with an electrical insulating material—the shallow trench having at least partially wedge-shaped, and the electrical insulating material having an upper surface that is substantially planar and extends substantially parallel to the main surface of the semiconductor body—the shallow trench extending into the semiconductor body at an angle of inclination α with respect to the main surface from the gate dielectric toward the drain region. A transistor device having a base, wherein the drain region forms an interface with the electrical insulating material within the shallow trench to form the sidewall of the shallow trench, the shallow trench has a triangular cross-section, the drift region is provided by a doping layer having the first conductivity type formed in the semiconductor body, and the doping layer forms the base of the shallow trench and is coupled to the drain region. Claim 2 delete Claim 3 A transistor device according to claim 1, wherein the range of the inclination angle α is 0.8° to 8.8°. Claim 4 A transistor device according to claim 1 or 3, wherein the base extends into the semiconductor body at an angle of inclination α with respect to the main surface in a first portion and extends substantially parallel to the main surface in a second portion. Claim 5 A transistor device according to claim 1, wherein the base of the shallow trench extends to a side wall that extends substantially perpendicularly to the main surface. Claim 6 In paragraph 5, the above drain region forms the sidewall, a transistor device. Claim 7 delete Claim 8 A transistor device according to claim 1, further comprising a field plate covering at least 50% of the length of the shallow trench on the main surface, wherein the field plate is integral with the gate electrode or separated from the gate electrode. Claim 9 A transistor device according to claim 8, further comprising a field plate extension portion disposed between the field plate and the drain region, the field plate being spaced apart from the main surface by a distance greater than the distance between the field plate and the main surface. Claim 10 A transistor device according to claim 9, wherein each of the one or more portions of the field plate extension has an end that forms an angle of inclination α' with respect to the main surface that is substantially the same as the angle of inclination α formed between the base of the shallow trench and the main surface facing the drain region. Claim 11 A transistor device according to claim 1, further comprising a superjunction structure disposed below the shallow trench, wherein the superjunction structure comprises one or more first elongated doping regions of the first conductivity type and one or more second elongated doping regions of the second conductivity type, and each of these first and second elongated doping regions has a length extending substantially parallel to the base of the shallow trench. Claim 12 A transistor device according to claim 11, further comprising: a first doped contact region having a first conductivity type disposed on a first surface of the superjunction structure—the first doped contact region being coupled to the first doped region and the drain region of the superjunction structure—and a second doped contact region having a second conductivity type disposed on a second surface opposite to the first surface of the superjunction structure—the second doped contact region being coupled to the second doped region and the body contact portion of the main surface. Claim 13 A transistor device according to claim 12, wherein the first doped contact region forms the base of the shallow trench. Claim 14 A transistor device according to claim 12 or 13, wherein the shallow trench comprises a first sidewall formed by the drain region, and the superjunction structure extends to the main surface below the gate dielectric. Claim 15 delete Claim 16 delete Claim 17 delete Claim 18 delete Claim 19 delete Claim 20 delete

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