Address fault detection in memory systems

Abstract

Various examples of memory systems including an address fault detection system are disclosed. The memory system includes an address fault detection system comprising a first memory array, a row decoder, and a second array, wherein the row decoder decodes row addresses into word lines, and each word line is coupled to a row of cells in the first array and a row of cells in the second array. The second array includes digital bits and / or analog values ​​used to identify address faults.

Description

Technology Field

[0001] Claim of priority

[0002] This application claims priority to U.S. Provisional Application No. 63 / 281,868 filed on November 22, 2021, under the title "Address Fault Detection in a Flash Memory System", and U.S. Patent Application No. 17 / 588,198 filed on January 28, 2022, under the title "Address Fault Detection in a Memory System".

[0003] Technology field

[0004] Various mechanisms for performing address fault detection in a memory system are disclosed. Background Technology

[0005] Non-volatile memory cells are well known in the art. A conventional non-volatile split-gate memory cell (10) comprising five terminals is illustrated in FIG. 1. The memory cell (10) comprises a semiconductor substrate (12) of a first conductive type, such as a P-type. The substrate (12) has a surface on which a first region (14) (also known as a source line, SL) of a second conductive type, such as an N-type, is formed. Additionally, a second region (16) (also known as a drain line) of an N-type is formed on the surface of the substrate (12). Between the first region (14) and the second region (16), there is a channel region (18). A bit line (BL) (20) is connected to the second region (16). A word line (WL) (22) is located over a first portion of the channel region (18) and is insulated from it. The word line (22) does not overlap with the second region (16) in any way. A floating gate (FG) (24) is located over another part of the channel region (18). The floating gate (24) is isolated from it and is adjacent to the word line (22). The floating gate (24) is also adjacent to the first region (14). The floating gate (24) may overlap with the first region (14) to provide coupling from the first region (14) into the floating gate (24). A coupling gate (CG) (also known as a control gate) (26) is located over the floating gate (24) and is isolated from it. An erase gate (EG) (28) is located over the first region (14), is adjacent to the floating gate (24) and the coupling gate (26), and is isolated from it. The upper corner of the floating gate (24) may be directed toward the inner corner of the T-shaped erase gate (28) to improve erasure efficiency. The erase gate (28) is also insulated from the first region (14).A memory cell (10) is described in more detail in U.S. Patent No. 7,868,375, the entire disclosure of which is incorporated herein by reference.

[0006] One exemplary operation for erasing and programming a non-volatile memory cell (10) of the prior art is as follows. The memory cell (10) is erased via a Fowler-Nordheim tunneling mechanism by applying a high voltage to the erase gate (28) while the other terminals are 0 volts. Electrons tunnel from the floating gate (24) into the erase gate (28), causing the floating gate (24) to become positively charged, which turns on the cell (10) under read conditions. The resulting cell erased state is known as the '1' state.

[0007] The memory cell (10) is programmed via a source-side thermionic programming mechanism by applying a high voltage on the coupling gate (26), a high voltage on the source line (14), an intermediate voltage on the erase gate (28), and a programming current on the bit line (20). Some of the electrons flowing across the gap between the word line (22) and the floating gate (24) acquire enough energy to be injected into the floating gate (24), causing the floating gate (24) to become negatively charged, which turns off the cell (10) from the read condition. The resulting cell programming state is known as the '0' state.

[0008] The memory cell (10) is read in the following current sensing mode: a bias voltage is applied to the bit line (20), a bias voltage is applied to the word line (22), a bias voltage is applied to the coupling gate (26), a bias or zero voltage is applied to the erase gate (28), and ground (e.g., zero voltage) is applied to the source line (14). In the erase state, there is cell current flowing from the bit line (20) to the source line (14), and in the programming state, there is insignificant or zero cell current flow from the bit line (20) to the source line (14). Alternatively, the memory cell (10) can be read in a reverse current sensing mode, where the bit line (20) is grounded and a bias voltage is applied to the source line (24). In this mode, the current is reversed in direction from the source line (14) to the bit line (20).

[0009] Alternatively, the memory cell (10) can be read in a voltage sensing mode as follows: a bias current (to ground) is applied to the bit line (20), a bias voltage is applied to the word line (22), a bias voltage is applied to the coupling gate (26), a bias voltage is applied to the erase gate (28), and a bias voltage is applied to the source line (14). In the erase state, there is a cell output voltage (significantly > 0 V) ​​on the bit line (20), and in the programming state, there is an output voltage that is insignificant or close to 0 on the bit line (20). Alternatively, the memory cell (10) can be read in a reverse voltage sensing mode, where the bit line (20) is biased at the bias voltage and a bias current (to ground) is applied to the source line (14). In this mode, the output voltage of the memory cell (10) is on the source line (14) rather than on the bit line (20).

[0010] In the prior art, various combinations of positive or zero voltages are applied to the word line (22), coupling gate (26), and floating gate (24) to perform read, programming, and erase operations.

[0011] In response to a read, erase, or program command, the logic circuit (270) (not shown) causes various voltages to be supplied to various parts of both the selected memory cell (10) and any unselected memory cells (10) in a timely manner with minimal disturbance.

[0012] For selected and unselected memory cells (10), the applied voltage and current are as follows. As used hereinafter, the following abbreviations are used: source line or first region (14) (SL), bit line (20) (BL), word line (22) (WL), and coupling gate (26) (CG).

[0013] [Table 1]

[0014]

[0015] For reference, in U.S. Patent No. 9,361,995, issued June 7, 2016, negative voltages could be applied to the word line (22) and / or coupling gate (26) during read, program, and / or erase operations. In this example, the voltage and current applied to the selected and unselected memory cells (10) are as follows.

[0016] [Table 2]

[0017]

[0018] In another example of the patent described above, negative voltages may be applied to the word line (22) when the memory cell (10) is not selected during read, erase, and program operations so that the following voltages are applied, and negative voltages may be applied to the coupling gate (26) during the erase operation:

[0019] [Table 3]

[0020]

[0021] The CGINH signal listed above is an inhibit signal applied to the coupling gate (26) of an unselected cell that shares the erase gate (28) with the selected cell.

[0022] FIG. 2 illustrates an example of a non-volatile split-gate memory cell (210) of another prior art. As with the memory cell (10), the memory cell (210) comprises a substrate (12), a first region (source line) (14), a second region (16), a channel region (18), a bit line (20), a word line (22), a floating gate (24), and an erase gate (28). Unlike the memory cell (10), the memory cell (210) does not include a coupling gate and comprises only four terminals—the bit line (20), the word line (22), the erase gate (28), and the source line (14). This significantly reduces the complexity of circuitry, such as the decoder circuitry required to operate an array of such memory cells.

[0023] The erase operation (erasing through an erase gate) and the read operation are similar to those in FIG. 1, except that there is no control gate bias. The programming operation is also performed without control gate bias, and therefore the program voltage on the source line is higher to compensate for the lack of control gate bias.

[0024] Table 4 shows typical voltage ranges that can be applied to the four terminals to perform read, erase, and program operations:

[0025] [Table 4]

[0026]

[0027] FIG. 3 illustrates an example of a non-volatile split-gate memory cell (310) of another prior art. As with the memory cell (10), the memory cell (310) includes a substrate (12), a first region (source line) (14), a second region (16), a channel region (18), a bit line (20), a floating gate (24), and an erase gate (28). Unlike the memory cell (10), the memory cell (310) does not include a coupling gate or an erase gate. Additionally, as illustrated, the word line (322) replaces the word line (22) and has a physical shape different from that of the word line (22).

[0028] One exemplary operation for erasing and programming a non-volatile memory cell (310) of the prior art is as follows. The cell (310) is erased via a Fowler-Nodheim tunneling mechanism by applying a high voltage on the word line (322) and 0 volts to the bit line and source line. Electrons tunnel from the floating gate (24) into the word line (322), causing the floating gate (24) to become positively charged, which turns on the cell (310) under read conditions. The resulting cell erased state is known as the '1' state. The cell (310) is programmed via a source-side thermionic programming mechanism by applying a high voltage on the source line (14), a small voltage on the word line (322), and a programming current on the bit line (320). Some of the electrons flowing across the gap between the word line (322) and the floating gate (24) acquire enough energy to be injected into the floating gate (24), causing the floating gate (24) to become negatively charged, which turns off the cell (310) from the read condition. The resulting cell programming state is known as the '0' state.

[0029] Exemplary voltages that can be used for read, program, erase, and standby operations in the memory cell (310) are shown in Table 5 below:

[0030] [Table 5]

[0031]

[0032] In addition, in the prior art, various techniques for performing address fault detection in memory systems are known. Address faults sometimes occur due to defects within materials or radiation, such as solar flares, which can cause a "1" bit to flip to a "0" bit within an address and vice versa. The result of an address fault is that while the decoder may receive the intended address for the operation, the occurrence of the fault causes the bits within the decoder to change, and the decoder may activate a word line corresponding to a different address, which will cause an incorrect row within the memory array to be accessed. Another possible result is that the fault causes the decoder to activate a word line corresponding to the intended address, and also a word line corresponding to a different address that is different from the intended address. If not detected or corrected, the address fault will cause an erroneous read or write / program operation.

[0033] FIG. 4 illustrates a prior art memory system (400). The prior art memory system (400) includes a row decoder (410) and an array (420). The row decoder (410) receives an address X, which is an address or part of an address corresponding to a selected row within the array (420). The row decoder (410) decodes the address X and selects a word line corresponding to the selected row. In this simplified example, four word lines are shown - WL0 (corresponding to address 0000), WL1 (corresponding to address 0001), WL2 (corresponding to address 0010), and WL3 (corresponding to address 0011). The selected word line will activate a row of memory cells within the array (420). Therefore, for example, when address 0010 is received, the row decoder (410) will activate WL2 (corresponding to address 0010).

[0034] FIG. 5 illustrates a memory system (400) of the prior art as in FIG. 4. However, in this situation, an address fault occurs. The row decoder (410) receives address 0010, but instead of activating WL2 (corresponding to address 0010), the row decoder (410) activates WL3 (corresponding to address 0011) instead due to a fault that occurred in the row decoder (410). If this fault is not detected or corrected, an error in the read or program operation occurs.

[0035] FIG. 6 illustrates a memory system (400) of the prior art as in FIG. 4 and FIG. 5. However, in this situation, an address fault of a different type than that in FIG. 4 occurs. The row decoder (410) receives address 0010, but instead of activating only WL2 (corresponding to address 0010), the row decoder (410) activates both WL2 and WL3 (corresponding to addresses 0010 and 0011, respectively) due to a fault that occurred in the row decoder (410). If this fault is not detected or corrected, an error in the read or program operation will occur.

[0036] FIG. 7 illustrates a memory system (700) of the prior art. The memory system (700) includes a row decoder (410) and an array (420), as in the memory systems of the preceding drawings. However, word lines, such as WL0, WL1, WL2, and WL3, are also coupled to a ROM (read-only memory) (710). The ROM (710) performs a verification function. Each word line is coupled to a row of cells within the ROM (710). When a specific word line is activated, the corresponding row of cells within the ROM (710) is activated. By design, each word line corresponds to a row within the ROM (710), and each row within the ROM (710) stores a different value in its cells. In this example, each row within the ROM (710) stores a value identical to the address corresponding to the word line connected to that row. Therefore, WL0 corresponds to address 0000, and the value stored in the row of the ROM (710) attached to WL0 is also 0000.

[0037] A memory system (700) is again illustrated in FIG. 8. A row decoder (410) receives address 0010, but due to a fault condition, word line WL3 (corresponding to address 0011) is selected instead of word line WL2 (corresponding to address 0010). This will cause an incorrect row of memory cells in the array (420) to be selected. Because word line WL3 is activated, the row in the ROM (710) corresponding to word line WL3 is also activated, and the ROM (710) outputs the value 0011 stored in that row. A comparator (450) compares the address received by the row decoder (410) (i.e., 0010) with the output of the ROM (710) (i.e., 0011) and determines that the values ​​do not match. Next, the comparator (450) may output a value (e.g., "0") which is understood to mean that no match was found, which will indicate that an address fault occurred.

[0038] Although a memory system (700) of the prior art can detect address faults in which an incorrect word line is activated, the memory system (700) of the prior art cannot detect faults in at least some situations where multiple rows are selected instead of just one row. The memory system (700) is again illustrated in FIG. 9. In this example, an address fault occurs in which the word line for the intended row (i.e., word line WL3 for address 0011) is activated and another word line (i.e., word line WL2 for address 0010) is activated. Both word lines WL2 and WL3 will be activated, and the contents for both rows in the ROM (710) will be output. Logically, the ROM (710) is designed so that when two rows are activated, the output becomes the "OR" of the two rows. Thus, the stored values ​​of 0010 and 0011 will cause the output to be 0011. The comparator (450) will compare the address (i.e., 0011) received by the row decoder (410) with the output of the ROM (i.e., 0011). In this case, no defect will be detected. Therefore, it can be understood that the memory system (700) is not always effective when identifying this type of address defect where two rows are selected instead of one row.

[0039] An improved address fault detection system is needed to identify three types of address faults in a memory system: a first situation where an incorrect word line is asserted, a second situation where a correct word line is asserted but a second line is also asserted with an error, and a third situation where no word line is asserted.

[0040] Various examples of memory systems including an address fault detection system are disclosed. The memory system includes an address fault detection system comprising a first memory array, a row decoder, and a second array, wherein the row decoder decodes row addresses into word lines, and each word line is coupled to a row of cells in the first array and a row of cells in the second array. The second array includes digital bits and / or analog values ​​used to identify address faults. Brief explanation of the drawing

[0041] FIG. 1 is a cross-sectional view of a conventional non-volatile memory cell to which the present invention can be applied. FIG. 2 is a cross-sectional view of a non-volatile memory cell of another prior art to which the present invention can be applied. FIG. 3 is a cross-sectional view of a non-volatile memory cell of another prior art to which the present invention can be applied. FIG. 4 illustrates a memory system of the prior art. FIG. 5 illustrates one type of address fault that can occur in the memory system of the prior art of FIG. 4. FIG. 6 illustrates another type of address fault that may occur in the memory system of the prior art of FIG. 4. FIG. 7 illustrates a conventional address fault detection system. FIG. 8 illustrates the prior art address fault detection system of FIG. 7 and one type of address fault. FIG. 9 illustrates the address fault detection system of the prior art of FIG. 7 and other types of address faults. FIG. 10 is a layout diagram of a die including non-volatile memory cells of the type illustrated in FIG. 1 to 3 and an improved address fault detection system. Figure 11 illustrates an example of an address fault detection system. FIG. 12 illustrates a conventional encoding scheme for verification data for addresses. FIG. 13a illustrates an example of an encoding scheme for acknowledgment data for addresses. Figure 13b illustrates another example of an encoding scheme for acknowledgment data for addresses. Figure 14 illustrates another example of an encoding scheme for acknowledgment data for addresses. Figure 15 illustrates another example of an address fault detection system. Figure 16 illustrates an example of an address fault detection circuit. FIGS. 17a and FIGS. 17b illustrate other examples of address fault detection systems. Figure 18 illustrates another example of an encoding scheme for acknowledgment data for addresses. Figure 19 illustrates another example of an address fault detection system. Figure 20 illustrates another example of an address fault detection system. Figure 21 illustrates another example of an address fault detection system. FIG. 22 illustrates another example of an address fault detection system. Figure 23 illustrates an encoding scheme for an address fault detection system. FIG. 24a illustrates an encoding scheme for an address fault detection system. FIG. 24b illustrates an encoding scheme for an address fault detection system. FIG. 25a illustrates an encoding scheme for an address fault detection system. FIG. 25b illustrates an encoding scheme for an address fault detection system. FIG. 26 illustrates an example of an address fault detection system. Figure 27 illustrates another example of an address fault detection system. Figure 28 illustrates another example of an address fault detection system. FIG. 29 illustrates another example of an address fault detection system. Figure 30 illustrates another example of an address fault detection system. Figure 31 illustrates another example of an address fault detection system. FIG. 32 illustrates an example of a detection circuit for use in examples of address fault detection systems. FIG. 33 illustrates an example of a comparator used in the sensing circuit of FIG. 32. FIG. 34 illustrates another example of a detection circuit for use in examples of address fault detection systems. FIG. 35 illustrates another example of a detection circuit for use in examples of address fault detection systems. FIG. 36 illustrates the layout of a flash memory cell for use in examples. FIG. 37 illustrates the layout of a flash memory cell configured as a ROM cell for use in examples. FIG. 38 illustrates examples of address fault detection systems and an example of a row decoder for use. FIG. 39 illustrates examples of address fault detection systems and one example of an erase gate decoder for use. FIG. 40 illustrates examples of address fault detection systems and one example of a source line decoder for use. FIG. 41 illustrates examples of address fault detection systems and one example of a control gate decoder for use. FIG. 42 illustrates examples of address fault detection systems and an example of a high-voltage level shifter for use. Specific details for implementing the invention

[0042] FIG. 10 illustrates an example of a memory system on a die. The die (1000) comprises: memory arrays (1001, 1002, 1003, and 1004) for storing data—each memory array optionally utilizing memory cells (10) as in FIG. 1, memory cells (210) as in FIG. 2, memory cells (310) as in FIG. 3, or other known types of memory cells—; row decoder circuits (1005, 1006, 1007, and 1008) used to access rows within the memory arrays (1001, 1002, 1003, and 1004), respectively, to be read or written; Column decoder circuits (1009, 1010, 1011, and 1012) used to access, respectively, columns within memory arrays (1001, 1002, 1003, and 1004) to be read or written; a sensing circuit (1013) used to read data from memory arrays (1001 and 1003), and a sensing circuit (1014) used to read data from memory arrays (1002 and 1004); analog circuits (1050); control logic circuits (1051) for providing various control functions, such as redundancy and built-in self-testing; high-voltage circuits (1052) used to provide positive and negative high-voltage supplies to the memory system; Charge pump circuits (1053) for providing increased voltages for erase and program operations for memory arrays (1001, 1002, 1003, and 1004); interface circuit (ITFC) (1054) for providing interface pins to connect to other macros on the chip; high-voltage decoder circuits (1018, 1019, 1020, and 1021) for use during read, erase, and program operations as needed.The die (1000) further includes address fault detection circuits (1022, 1023, 1024, and 1025) and array fault detection circuits (1026, 1027, 1028, and 1029) which are discussed in more detail below in relation to specific embodiments.

[0043] FIG. 11 illustrates an example of a memory system having improved address fault detection capabilities. The memory system (1100) includes a row decoder (1110), an array (1120), a high-voltage decoder (1140), a column decoder (1150), and a sensing amplifier (1160), each of which corresponds to components having similar descriptions in FIG. 10. The high-voltage decoder (1140) provides high voltages required for erase and program operations in the array (1120).

[0044] The memory system (1100) further includes an address fault detection system (1125) comprising an address fault detection array (1130), a detection amplifier (1170), and a comparator (1180). The address fault detection array (1130) includes a ROM array, a flash array, or another non-volatile memory array that stores an encoded value for each possible address that can be received by a row decoder (1110) and / or a column decoder (1150).

[0045] Various encoding schemes are considered for generating verification data for each possible address. An encoding scheme of the prior art is illustrated in FIG. 12. In this example, a 4-bit address is illustrated, which is an address that can be received by a row decoder (1110) and / or a column decoder (1150). For simplicity, the row portion of the address is assumed to be 4 bits in the range of 0000 to 1111. Each of these possible addresses is associated with a word line, which would be in the range of WL0 to WL15 (16 different row addresses and word lines). Each word line will activate a row in the address fault detection array (1130), and each row stores the same value as the row address associated with that word line. Thus, the address 0000 is associated with WL0, which consequently activates the row in the address fault detection array (1130) that stores the value 0000.

[0046] Referring again to FIG. 11, under the encoding scheme of FIG. 12, address X is received by a row decoder (1110), which will consequently activate a word line to access a row in the array (1120) and a row in the address fault detection array (1130). A detection amplifier (1170) will detect the value for each column in the address fault detection array (1130) where the word line was activated. The value in each column will be a logical “OR” of the value in that column for each activated row in the address fault detection array (1130), that is, if multiple rows have been activated, the value of the bit in that column of multiple activated rows will be 1 if any of the bits in that column of multiple activated rows is 1. The value from each column will be input to a comparator (1180), which will compare the received values ​​against address X (or, in this example, the row address portion of address X). As previously discussed, the output of the comparator (1180) will identify defects in situations where a faulty row is activated, because in such situations, the comparator will output a value indicating that the two input values ​​are different. However, as previously described in relation to FIG. 9, this scheme alone will not be effective in all situations involving defects where two rows were activated due to a defect.

[0047] An improved encoding scheme to increase power savings is illustrated in FIG. 13a. Those skilled in the art will understand that storing and detecting a "1" value in the address fault detection array (1130) consumes more energy than in the case of a "0" value. In this encoding scheme, an additional bit is stored, which is labeled as "PB" (polarity bit). When PB is "0", the encoded bits are a direct match to the associated address. When PB is "1", the encoded bits are an inverted version of the associated address. In this example, whenever more than half of the bits in the address are "1", a "1" value will be used for PB, and the bits will be inverted and stored. For example, for the address "1111", a value of "0000" is stored in the address fault detection array (1130), and "1" is stored in the PB bit for that value to indicate that each value is an inverted version of the corresponding address. Following this scheme, since fewer "1s" will be stored overall, the memory system will consume less energy than when using the scheme of the prior art of Fig. 12.

[0048] FIG. 13b illustrates a different encoding scheme. It is similar to the encoding scheme of FIG. 13a but includes an additional column for Multi-Row Detect (MRD) capable of detecting situations where multiple rows are incorrectly activated, which carries the risk of additional power consumption compared to the encoding scheme of FIG. 13a. The MRD column contains '1' for each row. A detailed description of Multi-Row Detect is included below.

[0049] Another improved encoding scheme is illustrated in FIG. 14. Here, each "0" in an address is encoded as "01" in the address fault detection array (1130), and each "1" in an address is encoded as "10" in the address fault detection array (1130). Thus, the address "0000" is encoded as "01010101", and the address "1111" is encoded as "10101010". Each bit Ax in an address is encoded as EAx and EBx. This means that the encoded values ​​in the address fault detection circuit (1130) will contain twice the number of bits of the corresponding address. Since any two addresses will always differ from each other by at least one bit, the sum of any two encoded values ​​corresponding to the two addresses will contain an "11" pattern in at least one bit pair (EAx and EBx). Therefore, detecting the "11" pattern in the detected values ​​of the address fault detection array (1130) indicates that two addresses are activated, which is a fault condition. This is a type of fault condition that the solution of the prior art of FIG. 12 cannot detect at least occasionally.

[0050] FIG. 15 illustrates an example of a memory system having an improved address fault detection system for implementing the encoding scheme of FIG. 14. The memory system (1500) includes the same components as the memory system (1100), except that the address fault detection system (1525) follows a different design from the address fault detection system (1125). Here, the address fault detection system (1525) includes an address fault detection array (1130) and an address fault detection circuit (1510). The address fault detection circuit (1510) receives outputs from each column within the address fault detection array (1130) where a word line was activated, wherein values ​​within any given column where a word line was activated are logically "OR"ed to generate an output for that column.

[0051] FIG. 16 further illustrates an example of an address fault detection circuit (1510). In response to the activation of a row containing bits EA[x] and EB[x] (where x is the number of address bits encoded in each row of the address fault detection circuit (1210)), each pair of bits EA[x] and EB[x] is input to the address fault detection circuit (1510). The address fault detection circuit (1510) includes a set of NAND gates (1601 and 1604), a NOR gate (1602), and an inverter (1603) configured as illustrated for each pair of bits EA[x] and EB[x].

[0052] The output A[x] of the address fault detection circuit (1510) for a pair of bits EA[x] and EB[x] will be "0" if the input is "01" or "10" (where the first bit is EA[x] and the second bit is EB[x]), and "1" otherwise. "1" indicates a fault condition (because the "11" or "00" pattern should not occur during normal operation based on the encoding scheme shown in FIG. 14 where EA[x] and EB[x] are always different bit values), that two rows are activated instead of one row—which is the only situation that will make EAx and EBx "11", that the received address has changed—which is the only situation that will make EAx and EBx "00", or that no row has been selected. Accordingly, the address fault detection system (1525) can detect fault situations where two rows are improperly activated or no row is selected.

[0053] FIG. 17a illustrates another example of a memory system having an improved address fault detection system. The memory system (1700) includes a row decoder (1110), an array (1120), and a column decoder (1150) as in the previously described examples. The memory system (1700) further includes an address fault detection system (1725) comprising an address fault detection array (1730), an address fault detection array (1731), and an address fault detection circuit (1710).

[0054] The column decoder (1150) is a set of multiplexers and may include layered multiplexers. Referring to FIG. 17b, a portion of an example of the column decoder (1150) is illustrated. Each column within the array (1120) is coupled to a bit line. Here, four bit lines are illustrated and labeled as BL0 through BL3. The first layer multiplexers select a pair of adjacent bit lines to be activated. A portion of two such first layer multiplexers is illustrated: T0 and T1. The second layer multiplexers select a bit line from a pair of adjacent bit lines. Here, each bit line has its own second layer multiplexer, which receives signals partially illustrated and labeled as V0 through V3. Thus, if BL0 is intended to be selected, T0 and V0 will be activated; if BL1 is intended to be selected, T0 and V1 will be activated; If BL2 is intended to be selected, T1 and V2 will be activated; if BL3 is intended to be selected, T1 and V3 will be activated.

[0055] Referring to both FIG. 17a and FIG. 17b, it can be understood that the column decoder (1150) is susceptible to faults as in the row decoder (1110). In this example, address X is input to the column decoder (1150). Here, address X includes a row address portion and a column address portion. The column portion of address X includes bits indicating which multiplexers should be activated (which will consequently assert the bit line). Each activation signal for the second layer multiplexers of the column decoder (1150) (V0, V1, V2, V3,…) is coupled to a row in the address fault detection array (1730), and each activation signal for the first layer multiplexers of the column decoder (1150) is coupled to a row in the address fault detection array (1731) (T0, T1,…). When a bit line is asserted, a row within the address fault detection array (1730) will be asserted, a row within the address fault detection array (1731) will be asserted, and a value will be output by each of the address fault detection array (1730) and the address fault detection array (1731). Such values ​​can be compared with a column portion of address X by the address fault detection circuit (1710). If the values ​​are different, a fault has occurred and an incorrect bit line has been asserted.

[0056] An exemplary encoding scheme for use in one example of FIG. 17a is illustrated in FIG. 18. Here, two layers of multiplexers are used. The first layer comprises multiplexers controlled by values ​​T[0] through T[3], which have column address bits AY[4] and AY[0]. The second layer comprises multiplexers controlled by values ​​V[0] through V[7], which have column address bits AY[2], AY[1], and AY[0]. It will be understood that additional layers are possible. The address fault detection arrays (1330 and 1331) have encoded values ​​for each multiplexer value, in particular, AYA[2], AYB[2], AYA[1], AYB[1], AYA[0], and AYB[0], and T[0]… for V[0]… T[3] includes AYA[4], AYB[4], AYA[3], and AYB[3]. As shown in FIG. 14, each "0" in the column component of the address is encoded as "01", and each "1" in the address is encoded as "10".

[0057] Referring again to FIG. 17a, the encoding scheme of FIG. 18 may be used. The address fault detection circuit (1710) follows the same design as the address fault detection circuit (1510) and will output "0" if a "11" or "00" pattern is detected in the bit pairs of encoded values ​​stored in the address fault detection array (1310) (because the "11" or "00" pattern should not occur during normal operation based on the encoding scheme shown in FIG. 18, where AYA[x] and AYB[x] are always different bit values). Thus, as a result of the operation of the address fault detection system (1725), the memory system (1700) can detect faults in the column components of the addresses.

[0058] FIGS. 19 and 20 illustrate variations of the examples already described. As can be seen, the functional blocks of the examples can be arranged in different configurations.

[0059] FIG. 19 illustrates a memory system (1900). The memory system (1900) is identical to the memory system (1100) of FIG. 11, except that a high-voltage decoder (1140) is coupled between an array (1120) and an address fault detection array (1130). Otherwise, the system operates as in FIG. 11.

[0060] FIG. 20 illustrates a memory system (2000). The memory system (2000) is identical to the memory system (1100) of FIG. 11, except that a row decoder (1110) is coupled between an array (1120) and an address fault detection array (1130). Otherwise, the system operates in the same way as in previous examples.

[0061] FIG. 21 illustrates a memory system (2100). Here, a row decoder (2103) operates with two arrays, namely array (2101) and array (2102). Array (2101) is coupled to a high-voltage decoder (2104), a column decoder (2106), and a sensing amplifier (2108). Array (2102) is coupled to a high-voltage decoder (2105), a column decoder (2107), and a sensing amplifier (2109). A single address fault detection system (2125) is used. The address fault detection system (2125) includes an address fault detection array (2110), a sensing amplifier (2111), and a comparator (2112). The address fault detection array (2110) is coupled to the sensing amplifier (2111) and the comparator (2112) and can operate as in the examples described above.

[0062] FIG. 22 illustrates an example of a memory system having an improved address fault detection system. The memory system (2200) includes a row decoder (2210), an array (2220), a high-voltage decoder (2240), a column decoder (2250), and a sensing amplifier (2260), each of which corresponds to components having similar descriptions in FIG. 10, FIG. 11, FIG. 15, FIG. 17a, FIG. 19, FIG. 20, and FIG. 21. The memory system (2200) further includes an address fault detection system (2225) comprising an address fault detection array (2230), an analog multi-state sensing amplifier (2270), and an analog comparator (2280). The address fault detection array (2230) includes a ROM array, a flash array, or another non-volatile memory array that stores an encoded value for each possible address that can be received by a row decoder (2210) and / or a column decoder (2250).

[0063] The memory system (2200) utilizes the encoding scheme illustrated in FIG. 23. The address fault detection array (2230) contains an encoded value for each possible address that is identical to the associated address. In this example, a 4-bit address [A3:A0] is illustrated, which is an address that can be received by the row decoder (2210) and / or the column decoder (2250). For simplicity, the row portion of the address is assumed to be 4 bits in the range of 0000 to 1111. Each of these possible addresses is associated with a word line, which would be in the range of WL0 to WL15 (16 different row addresses and word lines). Each word line will activate a row within the address fault detection array (2230), and each row within the address fault detection array (2230) stores a value identical to the row address associated with that word line. Therefore, address 0000 is associated with WL0, which will consequently activate the row storing the value 0000 in the address fault detection array (2230) at bit positions [EA3:EA0].

[0064] In FIG. 22, the multi-state sensing amplifier (2270) can detect analog levels within each column corresponding to 2-bit (or more) values; for example, it can detect 2-bit values ​​within the column instead of 1-bit values. The current generated in each column, representing the value for the column, is added for each activated row in the address fault detection array (1130), that is, if multiple rows have been activated, the values ​​of the bits within the multiple activated rows for that column are added together. The multi-state sensing amplifier (2270) optionally includes a multi-state digital sensing amplifier, a multi-state analog sensing amplifier, or both. In the example illustrated in FIG. 23, row 6 (ROM code pattern (0110)) and row 7 (code pattern 0111) are unintentionally short-circuited together, causing an error. The multi-state detection amplifier (2270) will display an output pattern as (0.2, 2, 1), which is essentially the value of row 6 added to the value of row 7. The fault address can be determined by subtracting the input address bits from the output pattern, where 0221 - 0110 = 0111.

[0065] FIGS. 24a, FIGS. 24b, FIGS. 25a, and FIGS. 25b illustrate additional encoding schemes that can be implemented in the address fault detection system (2225) of FIG. 22.

[0066] FIG. 24a illustrates an example for encoding a ROM pattern for 5-bit input addresses A [4:0]. In the table, empty cells should be understood to contain "0". The encoded word pattern is configured such that, as illustrated, the number of '1's in each codeword is less than half the number of bits in the encoded word. For example, in the words ER [0:9] encoded for all 32 rows, there are only 3 '1's in every word. As illustrated for the encoded word ER [0:9], the encoded pattern is configured such that there is only 1 '1' for the first 4 encoded bits ER [0:3], only 1 '1' for the next 4 encoded bits ER [4:7], and only 1 '1' for the last 2 encoded bits ER [8:9].

[0067] In another example illustrated in FIG. 24b, the encoded pattern is such that each word contains only one "1" within the first eight encoded bits ER [0:7] and only one "1" within the next four bits ER [8-11]. Empty cells in the table should be understood to contain "0". Therefore, each of the 32 rows contains exactly two "1s".

[0068] More generally, for words encoded as in FIG. 24a or FIG. 24b, for K-bit and / or L-bit groups among N-bit coded words, there is only one '1' in the K-bit group and / or L-bit group, and K>2 and / or L>2. For example, for 12-bit coded words (N=12), there are three groups of 4 bits (K=4), each of which contains only one '1'. In other examples, different combinations of K-bit and / or L-bit groups, such as 8-bit groups (K=8) together with 4-bit (L=4) groups, may be combined.

[0069] FIG. 25a illustrates an encoded scheme using digital ROM cells and analog (multi-state or multi-level) ROM cells (e.g., memory cells of FIG. 1, FIG. 2, or FIG. 3). In this example, the encoded word includes four digital bits ER [0-3] and four analog bits EAR [0:3] (meaning analog ROM cells that store multiple levels per cell, e.g., multi-state or multi-level cells), corresponding to four digital columns ER [0:3] and four analog columns ERA [0:3]. A multi-state detection amplifier (2270) is used in the analog columns to detect whether the cell current is 0.5X Ir or 1.0X Ir. The first four bits ER [0:3] follow the same pattern as in FIG. 24a. Cells that are empty in the table should be understood to contain "0". The first four encoded words have an EAR [0] equal to 0.5X Ir (ROM cell current), and the next four encoded words have an EAR [0] equal to 1.0X Ir (ROM cell current). This feature is used to distinguish the first four encoded words from the next four encoded words. The columns EAR [1], EAR [2], and EAR [3] perform the same function for subsequent groups of eight rows.

[0070] FIG. 25b illustrates an encoded scheme using only analog ROM cells. In this example, the encoded word contains six analog ROM cells. A multi-state sensing amplifier (2270) is used to read all columns.

[0071] FIG. 26 illustrates a memory system (2600). The memory system (2600) includes an array (1120), an address fault detection array (1130), and an analog comparator (2610). In this example, the address fault detection array (1130) includes a single row of non-volatile memory or ROM cells, each storing a value of "1". The outputs of each of the non-volatile memory or ROM cells are coupled in parallel to a single bit line. When a word line is asserted, the corresponding cell within that row will output "1", which generates a current Ir. A typical value for Ir is 20 μA. When more than one word line is asserted (which will occur when a fault causes both the intended word line and the unintended word line to be asserted), more than one cell within the address fault detection array (1130) will output "1", and the total output current is n * Ir, where n is the number of active word lines. The output is input to the analog comparator (2610). A reference current is also input to the analog comparator (2610). An exemplary reference current is 1.3 Ir. If the input from the address fault detection array (1130) exceeds 1.3 Ir, the output of the analog comparator (2610) will be "1," indicating that more than one word line is active, which indicates a fault condition. If the input from the address fault detection array (1130) is less than 1.3 Ir, the output will be "0," indicating that one or zero word lines are active, which indicates a non-fault condition. (It is possible for a zero word line situation to be faulty; this example will not detect that condition.) It can be understood that other multiples other than 1.3 may be selected.

[0072] In some examples where the address fault detection array (1130) includes flash memory cells, the “1” state in the cell is the erase state (having a cell current of Ir), and the “0” state in the cell is the programming state (having a cell current of approximately 0 μA). In other examples where the address fault detection array (1130) includes flash memory cells, the “1” state in the cell is the erase state, and the “0” state in the cell is a state where there is no bitline contact between the cell and the array column.

[0073] FIG. 27 illustrates a memory system (2700). The memory system (2700) is similar to the memory system (2600) of FIG. 26, except that it has two columns of cells within an address fault detection array (1130). The memory system (2700) includes an array (1120), an address fault detection array (1130), and analog comparators (2710 and 2720). In this example, the address fault detection array (1130) includes two columns of non-volatile memory or ROM cells, each storing a "1" value. The outputs of each of the non-volatile memory or ROM cells within each individual column are coupled in parallel to a single bit line. When a word line is asserted, each of the corresponding cells within that row will output a "1" corresponding to a current Ir. A typical value for Ir is 20 μA. When more than one word line is asserted (which is a type of fault condition), more than one pair of cells in the address fault detection array (1130) will output "1", where the total output current in each column is n * Ir, where n is the number of activated word lines. The output is input to analog comparators (2710 and 2720). Reference currents such as 0.5 Ir and 1.1 Ir are also input to analog comparators (2710 and 2720), respectively. When the input from the address fault detection array (1130) exceeds 1.1 Ir, the output of the comparator (2720) will be "1", which indicates that more than one word line is activated, which indicates a fault condition. If the input from the address fault detection array (1130) exceeds 0.5Ir but is less than 1.1Ir, the output of the comparator (2710) will be "1" and the output of the comparator (2720) will be "0", indicating that exactly one word line is active, which indicates a non-fault condition. If the input from the address fault detection array (1130) is 0.In the case of less than 5 Ir, the output of the comparator (2710) will be "0", which indicates that no word lines are active, which indicates a defective condition. It can be understood that multiples other than 1.1 may be selected to determine whether a specific number (e.g., 3) of word lines are defective.

[0074] FIG. 28 illustrates a memory system (2800). The memory system (2800) includes an array (1120), an address fault detection array (1130), and an analog comparator (2810). The memory system (2800) is identical to the memory system (2600) in FIG. 26, except that the address fault detection array (1130) is controlled by its own control gate signal (CGAFD), erase gate signal (EGAFD), and source line gate signal (SLGAFD). As in FIG. 26, the array (1120) and the address fault detection array (1130) share word lines. Thus, in this example, although the array (1120) and the address fault detection array (1130) share word lines, they use separate high-voltage control lines so that the address fault detection array (1130) can be erased or programmed independently from the array (1120).

[0075] FIG. 29 illustrates a memory system (2900). The memory system (2900) includes an array (1120) and an address fault detection array (1130). The address fault detection array (1130) includes one or more columns of non-volatile memory cells. Because the array (1120) and the address fault detection array (1130) share word lines and high-voltage control lines (control gate, erase gate, and source line gate signals), cells within a specific row of the address fault detection array (1130) will be erased when cells within that same row are erased in the array (1120). Accordingly, appropriate values ​​will need to be programmed into each erased row within the address fault detection array (1130) by a controller or other device following the erase operation. Specific columns within the address fault detection array (1130) include encoded acknowledgment bits for each possible address row portion and / or column using the encoding schemes of FIG. 12, FIG. 13a, FIG. 13b, FIG. 14, FIG. 18, FIG. 23, FIG. 24a, FIG. 24b, FIG. 25a, or FIG. 25b or other encoding schemes.

[0076] FIG. 30 illustrates a memory system (3000). The memory system (3000) includes an array (1120) and an address fault detection array (1130). The address fault detection array (1130) includes one or more columns of non-volatile memory cells. The memory system (3000) is identical to the memory system (2900) except that the memory system (3000) includes circuits (3010 and 3020) that pull down one or more bit lines to ground during operation. This is used, for example, to pull down a local source line to ground more strongly due to multiple cells and exists locally at the same time in the ROM (address fault detection array (1130)) pattern. It will be understood that the memory system (3000) may include one such circuit for each column within the address fault detection array (1130). Specific columns within the address fault detection array (1130) include encoded acknowledgment bits for each possible address row portion and / or column using the encoding schemes of FIG. 12, FIG. 13a, FIG. 13b, FIG. 14, FIG. 18, FIG. 23, FIG. 24a, FIG. 24b, FIG. 25a, or FIG. 25b or other encoding schemes.

[0077] FIG. 31 illustrates a memory system (3100). The memory system (3100) includes an array (1120), an address fault detection array (1130), and an analog comparator (3130). The address fault detection array (1130) includes one or more columns of non-volatile memory cells. The memory system (3100) is identical to the memory system (3000) except that the memory system (3100) includes a polarity column (3110) and a multi-row detection column (3120). The polarity column (3110) includes a single bit for each row to perform the function of the PB bit in FIG. 13a or FIG. 13b. The multi-row detection column (3120) includes a single cell for each row, and each single cell within the multi-row detection column (3120) stores "1". This column implements the function described above for FIG. 26. Other columns within the address fault detection array (1130) include encoded acknowledgment bits for each possible address row portion and / or column using the encoding schemes of FIG. 12, FIG. 13a, FIG. 13b, FIG. 14, FIG. 18, FIG. 23, FIG. 24a, FIG. 24b, FIG. 25a, or FIG. 25b or other encoding schemes.

[0078] In all examples described herein, when a defect occurs, the memory system may take appropriate steps. For example, the memory system may ignore the results of any read operation affected by the defect and repeat the read operation. The memory system may also repeat any write operation affected by the defect. In a situation where the array (1120) includes flash memory cells, the memory system may first erase the relevant part of the array before repeating the write (program) operation.

[0079] FIG. 32 illustrates an example of a sensing circuit. The sensing circuit (3200) includes bias transistors (3202 and 3204), current source (reference current) transistors (3201 and 3203), and an analog comparator (3205). The bias transistor (3202) is connected to a bit line (column) within an address fault detection array (1130). The bias transistor (3203) is connected to a dummy bit line, a balance capacitance, or a reference current generator.

[0080] Different configurations can be selected by selecting appropriate transistors for the current source transistors (3201 and 3203). In one configuration, the output of the comparator (3205) will indicate whether a word line is asserted. For example, the current source (reference current) transistor (3201) may be selected or set to generate a current equal to 0.5*IR, where IR is the current drawn by a single cell when a word line is asserted. In this configuration, an output of "0" from the comparator (3205) indicates that no word lines are asserted, and an output of "1" indicates that a word line is asserted.

[0081] In another configuration, the output of the comparator (3205) will indicate whether more than one word line is asserted. The current source transistors (3201 and 3203) are selected or set to generate a current equal to 1.1 * IR, where IR is the current drawn by a single cell when a word line is asserted. In this configuration, an output of "0" from the comparator (3205) indicates that one or fewer word lines are asserted, and indicates that more than one word line is asserted.

[0082] FIG. 33 illustrates additional details of the sensing circuit (3200). Bias switches (3301 and 3302) are also illustrated.

[0083] FIG. 34 illustrates another example of a sensing circuit. The sensing circuit (3400) includes bias transistors (3402 and 3404) and current mirror transistors (3401 and 3403). Transistors (3403 and 3404) constitute an output comparison stage (3410). The bias transistor (3402) is connected to a bit line (column) within the address fault detection array (1130). The bias transistor (3404) is connected to ground or another common potential. The mirror transistor (3403) mirrors the cell current (Ir) from the bit line within the address fault detection array (1130) through the mirror transistor (3401), which is to be compared with the reference current Iref from the bias transistor (3404). The bias transistor (3404) is modified to implement a different current comparison ratio (% * Ir) (e.g., a trimmable size). The output (Out) will indicate whether "1" is being output on the bit line from the address fault detection array (1130) or whether "0" is being output. Specifically, if the cell current Ir is greater than Iref (indicating a relatively high memory cell current indicating that "0" is stored in the cell), Out will be "1", and if the cell current Ir is less than Iref (indicating a relatively low memory cell current indicating that "1" is stored in the cell), Out will be "0". There may be multiple blocks of the output comparison stage (3410) to implement different current comparison ratios simultaneously with multiple outputs indicating different current detection ratios. Additionally, the transistor (3403) may be modified to implement different mirror ratios from the transistor (3401) to the transistor (3403) (e.g., a trimmable size).

[0084] FIG. 35 illustrates another example of a detection circuit. The detection circuit (3500) includes an inverter formed by bias transistors (3504 and 3502), control transistors (3501 and 3503), and transistors (3505 and 3506). The bias transistor (3504) is connected to a bit line (column) within the address fault detection array (1130). The bias transistor (3506) is connected to ground. The output at AFD_OUT will indicate whether "1" or "0" is being output from the address fault detection array (1130) on that bit line. The control transistor (3503) serves to cut off the current from the transistors (3502 and 3504) when detection is complete (the output of the inverter switches from "0" to "1," which means the gate of the transistor (3503) is off). The bias transistor (3502) is used to set a reference current to be compared with the cell current (Ir) coupled to the transistor (3504).

[0085] FIG. 36 illustrates a layout for a non-volatile memory cell (3600) that can be used in an address fault detection array (1130). The memory cell (3600) follows the architecture of the memory cell (10) in FIG. 1.

[0086] FIG. 37 illustrates a layout for a ROM cell (3700) that can be used in an address fault detection array (1130). The ROM memory cell (3700) follows the architecture of the memory cell (10) in FIG. 1, but is modified to operate as a ROM cell, and, for example, the CG and EG gates from the cell (3600) may be removed.

[0087] FIG. 38 illustrates a row decoder (3800) for eight word lines within a sector within a memory array (e.g., memory arrays (1001, 1002, 1003, and 1004)). The row decoder (3800) may be used for the row decoder (1110) in the aforementioned examples. The row decoder (3800) includes a NAND gate (3801) that receives pre-decoded address signals, denoted herein as lines XPA, XPB, XPC, and XPD, which selects a sector within the memory array. When XPA, XPB, XPC, and XPD are all "high," the output of the NAND gate (3801) will be "low," and this specific sector will be selected.

[0088] The row decoder (3800) further includes an inverter (3802), a decoder circuit (3810) for generating word line WL0, a decoder circuit (3820) for generating WL7, as well as additional decoder circuits (not shown) for generating word lines WL1, WL2, WL3, WL4, WL5, and WL6.

[0089] The decoder circuit (3810) includes PMOS transistors (3811, 3812, and 3814) and NMOS transistors (3813 and 3815) configured as illustrated. The decoder circuit (3810) receives the output of the NAND gate (3801), the output of the inverter (3802), and the pre-decoded address signal XPZB0 from the previous decoding level. When this specific sector is selected and XPZB0 is "low," WL0 will be asserted. When XPZB0 is "high," WL0 will not be asserted.

[0090] Similarly, the decoder circuit (3820) includes PMOS transistors (3821, 3822, and 3824) and NMOS transistors (3823 and 3825) configured as illustrated. The decoder circuit (3820) receives the output of the NAND gate (3801), the output of the inverter (3802), and the pre-decoded address signal XPZB7. When this specific sector is selected and XPZB7 is "low," WL7 will be asserted. When XPZB7 is "high," WL7 will not be asserted.

[0091] It should be understood that the decoder circuits (not shown) for WL1, WL2, and WL3, WL4, WL5, and WL6 will follow the same design as the decoder circuits (3810 and 3820), except that they will receive the inputs XPZB1, XPZB2, XPZB3, XPZB4, XPZB5, and XPZB6, respectively, instead of XPZB0 or ​​XPZB7.

[0092] In a situation where such a sector is selected and WL0 is asserted, the output of the NAND gate (3801) will be "low" and the output of the inverter will be "high". The PMOS transistor (3811) will be turned on, and the node between the PMOS transistor (3812) and the NMOS transistor (3813) will receive the value of XPZB0, which will be "low" when the word line WL0 is to be asserted. This will turn on the PMOS transistor (3814), which will pull WL0 "high" to ZVDD, which indicates the asserted state. In this case, XPZB7 is "high," indicating that WL7 should not be asserted, which will pull the node between the PMOS transistor (3822) and the NMOS transistor (3823) to the value of XPZB7 (which is "high"), which will turn on the NMOS transistor (3825) and make WL "low," which indicates an asserted state. In this way, one of the word lines WL0…WL7 can be selected when this sector is selected.

[0093] FIG. 39 illustrates an erase gate decoder (3900) as part of high voltage decoders (1018 to 1021). The erase gate decoder (3900) includes an NMOS transistor (3901) and PMOS transistors (3902 and 3903) configured as illustrated. The PMOS transistor (3903) is a current limiter having EGHV_BIAS as a current mirror bias level. When this erase gate signal (EG) is to be asserted, EN_HV_N will be set to low (e.g., 0 V or 1.2 V or 2.5 V), which will turn on the PMOS transistor (3902) and turn off the NMOS transistor (3901), which will cause the erase gate (EG) to be high (i.e., = VEGSUP, e.g., 11.5 V). When this erase gate signal (EG) should not be asserted, EN_HV_N will be set to high, which will turn off the PMOS transistor (3902) and turn on the NMOS transistor (3901), which will cause the erase gate (EG) to become low (i.e., = VEGSUP_LOW level, e.g., 0 V or 1.2 V or 2.5 V).

[0094] FIG. 40 illustrates a source line decoder (4000) as part of high-voltage decoders (1018 to 1021). The source line decoder (4000) includes NMOS transistors (4001, 4002, 4003, and 4004) configured as illustrated. The NMOS transistor (4001) pulls the source line (SL) low during a read operation in response to an active high SLRD_EN signal. The NMOS transistor (4002) pulls the source line (SL) low during a programming operation in response to an active high SLP_EN signal. The NMOS transistor (4003) performs a monitoring function through the output VSLMON, that is, it provides the voltage on the SL to be detected on the output VSLMON. The NMOS transistor (4004) provides a voltage to the source line (SL) in response to an active high EN_HV signal.

[0095] FIG. 41 illustrates a control gate decoder (4100) as part of high voltage decoders (1018 to 1021). The control gate decoder (4100) includes an NMOS transistor (4101) and a PMOS transistor (4102). The NMOS transistor (4101) will pull down the control gate signal (CG) in response to an active high signal EN_HV_N. The PMOS transistor (4102) will pull up the control gate signal (CG) in response to an active low signal EN_HV_N.

[0096] FIG. 42 illustrates a latch voltage shifter (4200) as part of high voltage decoders (1018 to 1021). The latch voltage shifter (4200), in the illustrated configuration, includes a low voltage latch inverter (4209), NMOS transistors (4203, 4204, 4207, and 4208), and PMOS transistors (4201, 4202, 4205, and 4206). The latch voltage shifter (4200) receives a signal EN_SEC as an input and outputs EN_HV and EN_HV_N having a voltage swing greater than the swing of EN_SEC.

Claims

Claim 1 A memory system comprising: a memory array including a first set of memory cells arranged in rows and columns; a row decoder for receiving a row address as input, wherein the row decoder is coupled to a plurality of word lines, each possible row address corresponds to a word line among the plurality of word lines, and each word line is coupled to a row of cells in the first set of memory cells; and an address fault detection array including a second set of memory cells arranged in rows and columns, wherein each of the plurality of word lines is coupled to a row of cells in the second set of memory cells having an N-bit encoded word, each possible row address corresponds to an N-bit encoded word, N is an integer, and each N-bit encoded word comprises one or more K-bit groups; A memory system comprising one or more of K-bit and L-bit groups, wherein each of the K-bit and L-bit groups comprises only one "1" bit, K and L are integers, K ≤ N, and L ≤ N, K > 2, L > 2, and the sum of the number of bits in one or more K-bit groups and one or more L-bit groups is N, and the same K-bit group and L-bit group are applied to each N-bit encoded word. Claim 2 delete Claim 3 delete Claim 4 A memory system according to claim 1, further comprising a comparator for identifying address defects based on the row address and the output of the address defect detection array. Claim 5 In paragraph 4, the memory system, wherein the comparator indicates a defect when no row is selected. Claim 6 In paragraph 4, the memory system, wherein the comparator indicates a defect when two or more rows of the memory array have been selected. Claim 7 In paragraph 4, the above comparator is a memory system including an analog comparator. Claim 8 A memory system according to claim 1, wherein each cell in the first set of memory cells is a split-gate flash memory cell. Claim 9 A memory system according to claim 1, wherein each cell in the second set of memory cells is a split-gate flash memory cell. Claim 10 A memory system according to claim 1, wherein each cell in the second set of memory cells is a read-only memory cell. Claim 11 A memory system according to claim 1, wherein each cell in the first set of memory cells is an analog memory cell. Claim 12 A memory system according to claim 1, further comprising a multi-state detection amplifier to detect the memory array. Claim 13 delete Claim 14 delete Claim 15 delete Claim 16 delete Claim 17 delete Claim 18 delete Claim 19 delete Claim 20 delete Claim 21 delete Claim 22 delete Claim 23 delete Claim 24 delete Claim 25 delete Claim 26 delete Claim 27 delete Claim 28 A memory system according to claim 1, wherein the memory cells in the second set of memory cells are multi-state memory cells. Claim 29 In paragraph 28, a memory system in which the memory cells in the first set of memory cells are analog memory cells. Claim 30 delete Claim 31 delete Claim 32 delete Claim 33 In paragraph 28, a memory system in which each first memory cell is a split-gate flash memory cell. Claim 34 In paragraph 28, a memory system in which each second memory cell is a split-gate flash memory cell. Claim 35 In paragraph 28, a memory system in which each second memory cell is a read-only memory cell. Claim 36 A memory system according to claim 28, further comprising a multi-state detection amplifier to detect the address fault detection array.

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