Signal Generator and memory device having the same

Abstract

The present invention includes a first amplifier that outputs an amplified voltage according to a reference voltage and a feedback voltage; a distribution circuit that distributes the amplified voltage to generate a distributed voltage and the feedback voltage; a signal generator comprising a buffer group that outputs a common sensing signal according to the amplified voltage and outputs a sensing signal according to the distributed voltage, and a memory device comprising the same.

Description

Technology Field

[0001] The present invention relates to a signal generator and a memory device including the same, and more specifically, to a signal generator that generates signals for controlling a page buffer of a memory device and a memory device including the same. Background Technology

[0003] The memory device may include a volatile memory device in which stored data is lost when the power supply is cut off, and a non-volatile memory device in which stored data is retained even when the power supply is cut off.

[0004] Volatile memory devices may include DRAM (dynamic random-access memory) and SRAM (static random-access memory). Non-volatile memory devices may include ROM (read-only memory), PROM (programmable read-only memory), EPROM (erasable PROM), EEPROM (electrically EPROM), flash memory devices, etc.

[0005] A memory device may include a memory cell array, peripheral circuits, and logic circuits.

[0006] A memory cell array includes multiple memory cells, and the multiple memory cells can store data.

[0007] Peripheral circuits can be configured to program data into a memory cell array, read programmed data, or erase programmed data.

[0008] A logic circuit can be configured to control peripheral circuits according to commands and addresses. The logic circuit may include software that executes an algorithm in response to a command, and hardware that outputs various signals according to the algorithm. The problem to be solved

[0010] An embodiment of the present invention provides a signal output circuit capable of generating signals for controlling peripheral circuits at an accurate time, and a method of operating the same. means of solving the problem

[0012] A signal output circuit according to an embodiment of the present invention includes: a first amplifier that outputs an amplified voltage according to a reference voltage and a feedback voltage; a distribution circuit that distributes the amplified voltage to generate a distributed voltage and the feedback voltage; and a buffer group that outputs a common sensing signal according to the amplified voltage and outputs a sensing signal according to the distributed voltage.

[0013] A memory device according to an embodiment of the present invention comprises: a memory block in which data is stored; page buffers connected to the memory block through bit lines; and a signal generation circuit that outputs page control signals for controlling the page buffers, wherein the signal generation circuit outputs a common sensing signal and a sensing signal included in the page control signals according to an amplification voltage and a distribution voltage generated through a feedback loop, and the page buffers precharge the bit lines or sense the voltage or current of the bit lines in response to the page control signals including the common sensing signal and the sensing signal. Effects of the invention

[0015] This technology can improve the reliability of a memory device including a signal output circuit by preventing a decrease in the reliability of a signal output circuit that generates signals controlling peripheral circuits. Brief explanation of the drawing

[0017] FIG. 1 is a drawing for explaining a memory device according to an embodiment of the present invention. Figure 2 is a diagram for specifically explaining a memory cell array. Figure 3 is a diagram illustrating the connection relationship between memory blocks and page buffer groups. Figure 4 is a circuit diagram illustrating the nth page buffer. Figure 5 is a diagram illustrating a signal output circuit. FIG. 6a is a circuit diagram for explaining a signal generation unit according to a first embodiment of the present invention. FIG. 6b is a circuit diagram for explaining a signal generation unit according to a second embodiment of the present invention. FIG. 6c is a circuit diagram for explaining a signal generation unit according to a third embodiment of the present invention. FIG. 6d is a circuit diagram for explaining a signal generation unit according to a fourth embodiment of the present invention. FIG. 7 is a drawing for explaining an embodiment of a memory system including a memory device according to an embodiment of the present invention. FIG. 8 is a drawing for explaining another embodiment of a memory system including a memory device according to an embodiment of the present invention. Specific details for implementing the invention

[0018] The advantages and features of the present invention and the methods for achieving them will be explained in detail through the embodiments described below in conjunction with the accompanying drawings. However, the present invention is not limited to the embodiments described herein and may be embodied in other forms. These embodiments are provided merely to explain in detail enough to enable those skilled in the art to easily implement the technical concept of the present invention.

[0019] Throughout the specification, when it is stated that a part is "connected" to another part, this includes not only cases where they are "directly connected," but also cases where they are "indirectly connected" with other elements interposed between them. Throughout the specification, when it is stated that a part "includes" a certain component, this means that, unless specifically stated otherwise, it does not exclude other components but may include additional components.

[0021] FIG. 1 is a drawing for explaining a memory device according to an embodiment of the present invention.

[0022] Referring to FIG. 1, a memory device (1100) may include a memory cell array (110) in which data is stored, peripheral circuits (120 to 160) that perform program, read, or erase operations, and a logic circuit (170) that controls the peripheral circuits (120 to 160).

[0023] The memory cell array (110) may include a plurality of memory blocks in which data is stored. Each of the memory blocks includes a plurality of memory cells, and the memory cells may be implemented in a two-dimensional structure arranged parallel to the substrate or a three-dimensional structure stacked perpendicular to the substrate.

[0024] Peripheral circuits (120 to 160) may include a voltage generator (120), a row decoder (130), a page buffer group (140), a column decoder (150), and an input / output circuit (160).

[0025] The voltage signal generation unit (120) can generate and output operating voltages (Vop) required for various operations in response to an operation signal (OPS). For example, the voltage signal generation unit (120) can generate and output a program voltage, a verification voltage, a read voltage, a pass voltage, and an erase voltage.

[0026] The row decoder (130) can select one memory block among the memory blocks included in the memory cell array (110) according to the row address (RADD) and transmit operating voltages (Vop) to the selected memory block.

[0027] A page buffer group (140) may be connected to a memory cell array (110) via bit lines. For example, the page buffer group (140) may include page buffers connected to each bit line. The page buffers may operate simultaneously in response to page buffer control signals (PBSIG) and may temporarily store data during a program or read operation. For example, the page buffers may precharge bit lines or sense the voltage or current of bit lines in response to page control signals (PBSIG). To this end, each page buffer may include multiple latches for temporarily storing data. The number of latches may vary depending on the programming method. For example, page buffers may be designed differently depending on the number of bits that can be stored in a single memory cell, and may be described differently depending on the number of verification voltages used during a verification operation. Additionally, verification voltages may be used to determine various threshold voltages of memory cells to be programmed with the same target voltage.

[0028] The column decoder (150) can transmit data (DATA) between the input / output circuit (160) and the page buffer group (140) according to the column address (CADD).

[0029] The input / output circuit (160) can be connected to the controller (1200) via input / output lines (IO). The input / output circuit (160) can input / output commands (CMD), addresses (ADD), and data (DATA) via input / output lines (IO). For example, the input / output circuit (160) can transmit the received commands (CMD) and addresses (ADD) via input / output lines (IO) to the logic circuit (170), and transmit the received data (DATA) via input / output lines (IO) to the column decoder (150). The input / output circuit (160) can output the data (DATA) received from the column decoder (150) to an external device via input / output lines (IO).

[0030] The logic circuit (170) can output operation signals (OPS), row address (RADD), page buffer control signals (PBSIG), and column address (CADD) in response to a command (CMD) and an address (ADD). For example, the logic circuit (170) may include software that executes an algorithm in response to a command (CMD), and hardware configured to output various signals according to the address (ADD) and the algorithm. For example, the logic circuit (170) may include a signal output circuit (180) configured to generate and output page buffer control signals (PBSIG).

[0032] Figure 2 is a diagram for specifically explaining a memory cell array.

[0033] Referring to FIG. 2, the memory cell array (110) may include first to i-th memory blocks (BLK1 to BLKi; i is a positive integer). Each of the first to i-th memory blocks (BLK1 to BLKi) includes a plurality of memory cells and may be configured identically to one another. The first to i-th memory blocks (BLK1 to BLKi) may be formed in a 2D or 3D structure. A 2D structure is a structure in which memory cells are arranged in a direction parallel to the substrate, and a 3D structure is a structure in which memory cells are stacked in a direction perpendicular to the substrate.

[0035] Figure 3 is a diagram illustrating the connection relationship between memory blocks and page buffer groups.

[0036] Referring to FIG. 3, the i-th memory block (BLKi) may include a plurality of strings (ST) connected between the first to n-th bit lines (BL1 to BLn; n is a positive integer) and the source line (SL). Each of the strings (ST) may include a source select transistor (SST), first to eighth memory cells (C1 to C8), and a drain select transistor (DST) connected in series between the source line (SL) and the first to n-th bit lines (BL1 to BLn). That is, one string (ST) may be connected between one bit line (e.g., BL1) and the source line (SL), and the string (ST) may include a source select transistor (SST), first to eighth memory cells (C1 to C8), and a drain select transistor (DST) connected in series with each other.

[0037] Since the i-th memory block (BLKi) illustrated in FIG. 3 is a diagram for explaining the configuration of memory blocks, the number of source select transistors (SST), first to eighth memory cells (C1~C8), and drain select transistors (DST) is not limited to the number illustrated in FIG. 3.

[0038] The gates of source select transistors (SST) connected to different strings (ST) are connected to the source select line (SSL), the gates of each of the first to eighth memory cells (C1 to C8) are connected to the first to eighth word lines (WL1 to WL8), and the gates of drain select transistors (DST) can be connected to the drain select line (DSL).

[0039] Memory cells connected to the same word line and contained in different strings (ST) can form a single physical page (PPG). Memory cells can be programmed or read in units of physical pages (PPG).

[0040] The first to nth bit lines (BL1~BLn) can each be connected to the first to nth page buffers (PB1~PBn) included in the page buffer group (140).

[0041] The first to nth page buffers (PB1 to PBn) can operate simultaneously in response to page buffer control signals (PBSIG). During program operation, the first to nth page buffers (PB1 to PBn) can precharge the first to nth bit lines (BL1 to BLn) or sense the voltage or current of the first to nth bit lines (BL1 to BLn) in response to the page buffer control signals (PBSIG). For example, the page buffer control signals (PBSIG) can be applied commonly to the first to nth page buffers (PB1 to PBn). Since the first to nth page buffers (PB1 to PBn) operate commonly in response to the page buffer control signals (PBSIG), the control of the page buffer control signals (PBSIG) can have a significant impact on the reliability of the memory device.

[0042] Since the first to nth page buffers (PB1~PBn) can be configured identically to each other, the nth page buffer (PBn) among them is described as an example as follows.

[0044] Figure 4 is a circuit diagram illustrating the nth page buffer.

[0045] Referring to FIG. 4, the n-th page buffer (PBn) may include a plurality of switches. FIG. 4 shows only a portion of the n-th page buffer (PBn) to aid in understanding the present embodiment.

[0046] The nth page buffer (PBn) may include first to ten switches (S1 to S10) and a latch (LAT). The nth page buffer (PBn) includes a plurality of latches (LAT), but for convenience of explanation, only one latch (LAT) is shown in FIG. 4.

[0047] The first switch (S1) may be implemented as an NMOS transistor that is turned on or turned off in response to a bitline select signal (BL_SEL). For example, when the first switch (S1) is turned on, the voltage of the first node (N1) may be transferred to the n-th bitline (BLn), or the voltage or current of the n-th bitline (BLn) may be transferred to the first node (N1). The second switch (S2) may be implemented as an NMOS transistor that connects or disconnects the first node (N1) and the ground terminal in response to a bitline discharge signal (BL_DIS). For example, when the second switch (S2) is turned on, the first node (N1) may be discharged.

[0048] The third switch (S3) can be implemented as an NMOS transistor that connects or disconnects the first node (N1) and the second node (N2) in response to a sensing signal (PBSENSE). Depending on the level of the sensing signal (PBSENSE), the amount of voltage or current transmitted between the n-th bit line (BLn) and the sensing node (SO) can be adjusted. The fourth switch (S4) can be implemented as an NMOS transistor that connects or disconnects the second node (N2) and the third node (N3) to each other in response to a common sensing signal (SA_CSOC). The turn-on level of the third and fourth switches (S3, S4) significantly affects the level of the sensed voltage or current when sensing the voltage or current of the n-th bit line (BLn). Additionally, the electrical characteristics of the third and fourth switches (S3, S4) may change depending on the temperature. Therefore, since the levels of the sensing signal (PBSENSE) and the common sensing signal (SA_CSOC) are important for sensing data in memory cells, adjustment is required to avoid these influences.

[0049] The fifth switch (S5) can be implemented as a PMOS transistor that supplies the power supply voltage (VCC) to the third node (N3) or blocks the supply of the power supply voltage (VCC) according to the data stored in the latch (LAT). The sixth switch (S6) can be implemented as a PMOS transistor that connects or disconnects the third node (N3) and the sensing node (SO) to each other in response to the sensing node precharge signal (SA_PRECH_N). The seventh switch (S7) can be implemented as an NMOS transistor that connects or disconnects the sensing node (SO) and the second node (N2) to each other in response to the sensing node sensing signal (SA_SENSE). The eighth and ninth switches (S8, S9) can discharge the second node (N2) according to the sensing node discharge signal (SA_DIS) and the data stored in the latch (KAT). The eighth switch (S8) can be connected between the second node (S2) and the ninth switch (S9), and the ninth switch (S9) can be connected between the eighth switch (S8) and the ground terminal. The eighth switch (S8) can be turned on or turned off in response to a sensing node discharge signal (SA_DIS), and the ninth switch (S9) can be turned on or turned off according to data stored in a latch (LAT). Thus, the second node (N2) can be discharged when both the eighth and ninth switches (S8, S9) are turned on. The tenth switch (S10) can be implemented as a PMOS transistor that supplies or cuts off the power supply voltage (VCC) to the sensing node (SO) in response to a precharge signal (PRECH_N).

[0050] In addition to the switches described above, the nth page buffer (PBn) may further include a plurality of latches and a plurality of switches for transferring data between the plurality of latches.

[0052] Figure 5 is a diagram illustrating a signal output circuit.

[0053] Referring to FIG. 5, the signal output circuit (180) can generate and output page buffer control signals (PBSIG) having various levels. The page buffer control signals (PBSIG) may include the signals described in FIG. 4 (BL_SEL, BL_DIF, …, PBSENSE, SA_CSOC). That is, page buffer control signals (PBSIG) that control the first to nth page buffers (PB1 to PBn in FIG. 3) can be generated and output by the signal output circuit (180).

[0054] In order to generate and output page buffer control signals (PBSIG) having various levels, the signal output circuit (180) may include a plurality of signal generating units (GN_1 to K; K is a positive integer). For example, the first signal generating unit (GN_1) may generate and output a bitline select signal (BL_SEL), the second signal generating unit (GN_2) may generate and output a bitline discharge signal (BL_DIS), and the Kth signal generating unit (GN_K; 190) may generate and output a sensing signal (PBSENSE) and a common sensing signal (SA_CSOC).

[0055] Since the levels of the sensing signal (PBSENSE) and the common sensing signal (SA_CSOC) are important during the sensing operation, in this embodiment, the K signal generating unit (GN_K; 190) that generates the sensing signal (PBSENSE) and the common sensing signal (SA_CSOC) will be described in detail.

[0057] FIG. 6a is a circuit diagram for explaining a signal generation unit according to a first embodiment of the present invention.

[0058] Referring to FIG. 6a, the K signal generation unit (190) may include a first amplifier (A1), a distribution circuit (DIV), and a first buffer group (APG1).

[0059] The first amplifier (A1) can operate by receiving the power supply voltage (VCC) and can output an amplified voltage (Vamp) according to the reference voltage (Vref) and the feedback voltage (Vfb). The reference voltage (Vref) can be applied to the input terminal (-) of the first amplifier (A1), and the feedback voltage (Vfb) can be applied to the input terminal (+) of the first amplifier (A1). The first amplifier (A1) can amplify the voltage difference between the reference voltage (Vref) and the feedback voltage (Vfb) and output an amplified voltage (Vamp) to the fourth node (N4). Here, the feedback voltage (Vfb) is the second divided voltage (Vdiv_2) output from the divided circuit (DIV).

[0060] The distribution circuit (DIV) may be connected between the fourth node (N4) and the ground terminal. The distribution circuit (DIV) may include a first variable resistor (R1), a voltage regulation circuit (VCT), and a second variable resistor (R2). The first variable resistor (R1) may be connected between the fourth node (N4) and the fifth node (N5), the voltage regulation circuit (VCT) may be connected between the fifth node (N5) and the sixth node (N6), and the second variable resistor (R2) may be connected between the sixth node (N6) and the ground terminal.

[0061] The resistance value of the first variable resistor (R1) can be varied in response to a first trim code (TC_1) consisting of multiple bits.

[0062] The voltage regulation circuit (VCT) may include a diode (D10) that allows current to flow from the fifth node (N5) to the sixth node (N6). In order to reduce the dispersion or deviation of the sensing signal (PBSENSE) applied to the gate of the third switch (S3 in FIG. 4) included in the page buffer (PBn in FIG. 4), the diode (D10) may be formed as a transistor identical to the third switch (S3 in FIG. 4). For example, the diode (D10) may be formed as a transistor having the same material, structure, and size as the third switch (S3) included in the page buffer (PBn in FIG. 4), and may be formed to have a threshold voltage identical to the threshold voltage of the third switch (S3).

[0063] The resistance value of the second variable resistor (R2) can be varied in response to a second trim code (TC_2) consisting of multiple bits. Since the second variable resistor (R2) is closer to the ground terminal than the first variable resistor (R1), the second trim code (TC_2) may consist of more bits than the first trim code (TC_1) in order to precisely adjust the first and second divided voltages (Vdiv_1, Vdiv_2). For example, if the first trim code (TC_1) consists of a 4-bit code, the second trim code (TC_2) may consist of a 6-bit code, which is larger than 4 bits. The number of bits in the first and second trim codes (TC_1, TC_2) is not limited thereto.

[0064] The sixth node (N6) is connected to the input terminal (+) of the first amplifier (A1). Accordingly, the second divided voltage (Vdiv_2) corresponding to the potential of the sixth node (N6) can be applied to the input terminal (+) of the first amplifier (A1) as a feedback voltage (Vfd).

[0065] Accordingly, a feedback loop (FBL) can be formed in which the amplified voltage (Vamp) output from the first amplifier (A1) is distributed by the first variable resistor (R1), the voltage control circuit (VCT), and the second variable resistor (R2), and the distributed voltage is applied again to the input terminal (+) of the first amplifier (A1).

[0066] The first buffer group (APG1) may include a second amplifier (A2) connected to the fourth node (N4) and a third amplifier (A3) connected to the fifth node (N5). The first to third amplifiers (A1 to A3) may all operate by receiving the same power supply voltage (VCC). The input terminal (+) of the second amplifier (A2) may be connected to the fourth node (N4), and the input terminal (-) may be connected to the output node of the second amplifier (A2). That is, the voltage output from the second amplifier (A2) may be applied to the page buffer as a common sensing signal (SA_CSOC) and may be applied again to the input terminal (-) of the second amplifier (A2). The input terminal (+) of the third amplifier (A3) may be connected to the fifth node (N5), and the input terminal (-) may be connected to the terminal of the third amplifier (A3). That is, the voltage output from the third amplifier (A3) can be applied to the page buffer as a sensing signal (PBSENSE) and can be applied again to the input terminal (-) of the third amplifier (A3).

[0067] Since the common sensing signal (SA_CSOC) can be varied according to the amplification voltage (Vamp) and the sensing signal (PBSENSE) can be varied according to the first distribution voltage (Vdiv_1), the levels of the common sensing signal (SA_CSOC) and the sensing signal (PBSENSE) can be varied according to the voltages generated in the feedback loop (FBL). That is, since the sensing signal (PBSENSE) is generated using the amplification voltage (Vamp), which is the voltage generating the common sensing signal (SA_CSOC), as a voltage source, the difference between the level of the sensing signal (PBSENSE) and the level of the common sensing signal (SA_CSOC) can be maintained constant.

[0069] FIG. 6b is a circuit diagram for explaining a signal generation unit according to a second embodiment of the present invention.

[0070] Referring to FIG. 6b, the signal generation unit (190) according to the second embodiment can be configured similarly to the first embodiment, so the description of the configuration that overlaps with the first embodiment is omitted. In the second embodiment, the voltage regulation circuit (VCT) may include a plurality of diodes (D10 to D1k; k is a positive integer). The plurality of diodes (D10 to D1k) may be connected in parallel between the fifth node (N5) and the sixth node (N6), and all may allow current to flow in the same direction. The transistors included in the plurality of diodes (D10 to D1k) may be formed as the same transistor as the third switch (S3 in FIG. 4) included in the page buffer (PBn in FIG. 4). For example, the transistors included in the plurality of diodes (D10 to D1k) can be formed as transistors having the same material, structure, and size as the third switch (S3) included in the page buffer (PBn in FIG. 4), and can be formed to have a threshold voltage equal to the threshold voltage of the third switch (S3).

[0071] The more diodes (D10~D1k) there are, the more stably the first division voltage (Vdiv_1) can be output, and as a result, the dispersion or deviation of the sensing signal (PBSENSE) applied to the third switch (S3) of the page buffer can be further reduced. That is, the more diodes (D10~D1k) there are, the more the sensing signal (PBSENSE) can maintain a constant level.

[0073] FIG. 6c is a circuit diagram for explaining a signal generation unit according to a third embodiment of the present invention.

[0074] Referring to FIG. 6c, the K signal generation unit (190) may include a first amplifier (A1), a distribution circuit (DIV), and a second buffer group (APG2).

[0075] The first amplifier (A1) can operate by receiving the power supply voltage (VCC) and can output an amplified voltage (Vamp) according to the reference voltage (Vref) and the feedback voltage (Vfb). The reference voltage (Vref) can be applied to the input terminal (-) of the first amplifier (A1), and the feedback voltage (Vfb) can be applied to the input terminal (+) of the first amplifier (A1). The first amplifier (A1) can amplify the voltage difference between the reference voltage (Vref) and the feedback voltage (Vfb) and output an amplified voltage (Vamp) to the fourth node (N4). Here, the feedback voltage (Vfb) is the second divided voltage (Vdiv_2) output from the divided circuit (DIV).

[0076] The distribution circuit (DIV) may be connected between the fourth node (N4) and the ground terminal. The distribution circuit (DIV) may include a first variable resistor (R1), a voltage regulation circuit (VCT), and a second variable resistor (R2). The first variable resistor (R1) may be connected between the fourth node (N4) and the fifth node (N5), the voltage regulation circuit (VCT) may be connected between the fifth node (N5) and the sixth node (N6), and the second variable resistor (R2) may be connected between the sixth node (N6) and the ground terminal.

[0077] The resistance value of the first variable resistor (R1) can be varied in response to a first trim code (TC_1) consisting of multiple bits.

[0078] The voltage regulation circuit (VCT) may include a diode (D10) that allows current to flow from the fifth node (N5) to the sixth node (N6). In order to reduce the dispersion or deviation of the sensing signal (PBSENSE) applied to the gate of the third switch (S3 in FIG. 4) included in the page buffer (PBn in FIG. 4), the diode (D10) may be formed as a transistor identical to the third switch (S3 in FIG. 4). For example, the diode (D10) may be formed as a transistor having the same material, structure, and size as the third switch (S3) included in the page buffer (PBn in FIG. 4), and may be formed to have a threshold voltage identical to the threshold voltage of the third switch (S3).

[0079] The resistance value of the second variable resistor (R2) can be varied in response to a second trim code (TC_2) consisting of multiple bits. Since the second variable resistor (R2) is closer to the ground terminal than the first variable resistor (R1), the second trim code (TC_2) may consist of more bits than the first trim code (TC_1) in order to precisely adjust the first and second divided voltages (Vdiv_1, Vdiv_2). For example, if the first trim code (TC_1) consists of a 4-bit code, the second trim code (TC_2) may consist of a 6-bit code, which is larger than 4 bits. The number of bits in the first and second trim codes (TC_1, TC_2) is not limited thereto.

[0080] The sixth node (N6) is connected to the input terminal (+) of the first amplifier (A1). Accordingly, the second divided voltage (Vdiv_2) corresponding to the potential of the sixth node (N6) can be applied to the input terminal (+) of the first amplifier (A1) as a feedback voltage (Vfd).

[0081] Accordingly, a feedback loop (FBL) can be formed in which the amplified voltage (Vamp) output from the first amplifier (A1) is distributed by the first variable resistor (R1), the voltage control circuit (VCT), and the second variable resistor (R2), and the distributed voltage is applied again to the input terminal (+) of the first amplifier (A1).

[0082] The second buffer group (APG2) may include a plurality of amplifiers (A21~A2k, A31~A3k) that generate a common sensing signal (SA_CSOC) and a sensing signal (PBSENSE) according to an amplification voltage (Vamp) and a first distribution voltage (Vdiv_1). The 21st to 2kth amplifiers (A21~A2k) may output a common sensing signal (SA_CSOC) according to the amplification voltage (Vamp), and the 31st to 3kth amplifiers (A31~A3k) may output a sensing signal (PBSENSE) according to the first distribution voltage (Vdiv_1). The first amplifier (A1), the 21st to 2kth amplifiers (A21~A2k), and the 31st to 3kth amplifiers (A31~A3k) may all operate by receiving the same power supply voltage (VCC).

[0083] The 21st to 2kth amplifiers (A21 to A2k) can be connected in series with each other between the fourth node (N4) and the last output node. The input terminal (+) of the 21st amplifier (A21) can be connected to the fourth node (N4), and the input terminal (-) can be connected to the output node of the 21st amplifier (A21). The output node of the 21st amplifier (A21) can be connected to the input terminal (+) of the next amplifier, the 22nd amplifier (A22). That is, the input terminal (+) of the 22nd amplifier (A22) can be connected to the output node of the previous amplifier, the 21st amplifier (A21), and the output node of the 22nd amplifier (A22) can be connected to the input terminal (-) of the 22nd amplifier (A22) and the input terminal (+) of the next amplifier. In this way, the 21st to 2kth amplifiers (A21 to A2k) can be connected in series with each other, and the signal output from the last connected 2kth amplifier (A2k) can be used as a common sensing signal (SA_CSOC).

[0084] The 31st to 3kth amplifiers (A31 to A3k) can be connected in series with each other between the 5th node (N5) and the last output node. The input terminal (+) of the 31st amplifier (A31) can be connected to the 5th node (N5), and the input terminal (-) can be connected to the output node of the 31st amplifier (A31). The output node of the 31st amplifier (A31) can be connected to the input terminal (+) of the next amplifier, the 32nd amplifier (A32). That is, the input terminal (+) of the 32nd amplifier (A32) can be connected to the output node of the previous amplifier, the 31st amplifier (A31), and the output node of the 32nd amplifier (A32) can be connected to the input terminal (-) of the 32nd amplifier (A32) and the input terminal (+) of the next amplifier. In this way, amplifiers 31 through 3k (A31 to A3k) can be connected in series with each other, and the signal output from the last connected amplifier (A3k) can be used as a sensing signal (PBSENSE).

[0085] Since the second buffer group (APG2) shown in FIG. 6c also uses the amplified voltage (Vamp) as a voltage source to simultaneously output the common sensing signal (SA_CSOC) and the sensing signal (PBSENSE), the level difference between the sensing signal (PBSENSE) and the common sensing signal (SA_CSOC) can be maintained constant in the K signal generation unit (190) shown in FIG. 6c.

[0087] FIG. 6d is a circuit diagram for explaining a signal generation unit according to a fourth embodiment of the present invention.

[0088] Referring to FIG. 6d, the signal generation unit (190) according to the fourth embodiment can be configured similarly to the third embodiment, so the description of the configuration that overlaps with the third embodiment is omitted. In the fourth embodiment, the voltage regulation circuit (VCT) may include a plurality of diodes (D10 to D1k; k is a positive integer). The plurality of diodes (D10 to D1k) may be connected in parallel between the fifth node (N5) and the sixth node (N6), and all may allow current to flow in the same direction. The transistors included in the plurality of diodes (D10 to D1k) may be formed as the same transistor as the third switch (S3 in FIG. 4) included in the page buffer (PBn in FIG. 4). For example, the transistors included in the plurality of diodes (D10 to D1k) can be formed as transistors having the same material, structure, and size as the third switch (S3) included in the page buffer (PBn in FIG. 4), and can be formed to have a threshold voltage equal to the threshold voltage of the third switch (S3).

[0089] The more diodes (D10~D1k) there are, the more stably the first division voltage (Vdiv_1) can be output, and as a result, the dispersion or deviation of the sensing signal (PBSENSE) applied to the third switch (S3) of the page buffer can be further reduced. That is, the more diodes (D10~D1k) there are, the more the sensing signal (PBSENSE) can maintain a constant level.

[0091] FIG. 7 is a drawing for explaining an embodiment of a memory system including a memory device according to an embodiment of the present invention.

[0092] Referring to FIG. 7, the memory system (1000) may include a memory device (1100) in which data is stored, and a controller (1200) that communicates between the memory device (1100) and a host (2000).

[0093] The memory system (1000) may include a plurality of memory devices (1100), and each of the memory devices (1100) may include the signal output circuit (180 in FIG. 1) and page buffer group (140 in FIG. 1) described above. The memory devices (1100) may be connected to a controller (1200) through at least one channel. For example, a plurality of memory devices (1100) may be connected to a single channel, and even when a plurality of channels are connected to the controller (1200), a plurality of memory devices (1100) may be connected to each channel.

[0094] The controller (1200) can communicate between the host (2000) and the memory device (1100). The controller (1200) can control the memory device (1100) according to a request from the host (2000), or perform background operations to improve the performance of the memory system (1000) even without a request from the host (2000). The host (2000) can generate requests for various operations and output the generated requests to the memory system (1000). For example, the requests may include a program request to control a program operation, a read request to control a read operation, an erase request to control an erase operation, and the like.

[0095] The host (2000) can communicate with the memory system (1000) through various interfaces such as PCIe (Peripheral Component Interconnect Express), ATA (Advanced Technology Attachment), SATA (Serial ATA), PATA (Parallel ATA), SAS (serial attached SCSI), NVMe (Non-Volatile Memory Express), USB (Universal Serial Bus), MMC (Multi-Media Card), ESDI (Enhanced Small Disk Interface), or IDE (Integrated Drive Electronics).

[0097] FIG. 8 is a drawing for explaining another embodiment of a memory system including a memory device according to an embodiment of the present invention.

[0098] Referring to FIG. 8, the memory system (70000) may be implemented as a memory card or a smart card. The memory system (70000) may include a memory device (1100), a controller (1200), and a card interface (7100).

[0099] The controller (1200) can control the exchange of data between the memory device (1100) and the card interface (7100). According to an embodiment, the card interface (7100) may be an SD (secure digital) card interface or an MMC (multi-media card) interface, but is not limited thereto.

[0100] Each of the memory devices (1100) may include the signal output circuit (180 in FIG. 1) and page buffer group (140 in FIG. 1) described above, and data stored in the memory device (1100) may be output through the card interface (7100) under the control of the controller (1200).

[0101] The card interface (7100) can interface for data exchange between the host (60000) and the controller (1200) according to the protocol of the host (60000). According to an embodiment, the card interface (7100) can support the Universal Serial Bus (USB) protocol and the Inter Chip (IC)-USB protocol. Here, the card interface (7100) may refer to hardware capable of supporting the protocol used by the host (60000), software installed on said hardware, or a signal transmission method.

[0102] When the memory system (70000) is connected to the host interface (6200) of a host (60000), such as a PC, tablet PC, digital camera, digital audio player, mobile phone, console video game hardware, or digital set-top box, the host interface (6200) can perform data communication with the memory device (1100) through the card interface (7100) and the controller (1200) under the control of the microprocessor (Microprocessor; μP; 6100). Explanation of the symbols

[0104] 1100: Memory device 110: Memory cell array 120: Voltage signal generator 130: Row decoder 140: Page buffer group 150: Column decoder 160: Input / Output Circuit 170: Logic Circuit 180: Signal output circuit 190: Kth signal generation unit VCT: Voltage regulator circuit D10~D1k: Diodes

Claims

Claim 1 A signal generator comprising: a first amplifier that outputs an amplified voltage according to a reference voltage and a feedback voltage; a distribution circuit that distributes the amplified voltage to generate a distributed voltage and the feedback voltage; and a buffer group that outputs a common sensing signal according to the amplified voltage and a sensing signal according to the distributed voltage, wherein the distribution circuit comprises a first variable resistor, a voltage regulating circuit, and a second variable resistor connected in series between the output node of the first amplifier and a ground terminal, wherein the distributed voltage is a voltage distributed between the first variable resistor and the voltage regulating circuit, and the feedback voltage is a voltage distributed between the voltage regulating circuit and the second variable resistor. Claim 2 A signal generator according to claim 1, wherein the reference voltage is applied to the input terminal (-) of the first amplifier and the feedback voltage is applied to the input terminal (+). Claim 3 delete Claim 4 delete Claim 5 A signal generator according to claim 1, wherein the resistance value of the first variable resistor is varied in response to a first trim code, and the resistance value of the second variable resistor is varied in response to a second trim code having more bits than the first trim code. Claim 6 In claim 1, the voltage regulation circuit is a signal generator composed of a diode or a plurality of diodes that causes current to flow from the first variable resistor toward the second variable resistor. Claim 7 In claim 6, the plurality of diodes are a signal generator connected in parallel between the first variable resistor and the second variable resistor. Claim 8 In claim 6, the diode or the plurality of diodes is a signal generator composed of a transistor or transistors having the same material, structure, and size as the switch that operates in response to the sensing signal among the plurality of switches included in the page buffers connected to the bit lines. Claim 9 In claim 1, the buffer group comprises a signal generator including a second amplifier that outputs the common sensing signal according to the amplification voltage; and a third amplifier that outputs the sensing signal according to the distribution voltage. Claim 10 In claim 9, the first to third amplifiers are signal generators that operate by receiving the same power supply voltage. Claim 11 A signal generator according to claim 9, wherein the amplification voltage is applied to the input terminal (+) of the second amplifier and the output node of the second amplifier is connected to the input terminal (-) of the second amplifier. Claim 12 In paragraph 11, the signal output through the output node of the second amplifier is the signal generator that is the common sensing signal. Claim 13 A signal generator according to claim 9, wherein the divided voltage is applied to the input terminal (+) of the third amplifier and the output node of the third amplifier is connected to the input terminal (-) of the third amplifier. Claim 14 In paragraph 13, the signal output through the output node of the third amplifier is the signal generator that is the sensing signal. Claim 15 In claim 1, the buffer group comprises a plurality of fourth amplifiers that output the common sensing signal according to the amplification voltage; and a plurality of fifth amplifiers that output the sensing signal according to the distribution voltage. Claim 16 In paragraph 15, the signal generator comprises a plurality of amplifiers connected in series between a node to which the amplification voltage is applied and an output node to which the common sensing signal is output. Claim 17 A signal generator according to claim 16, wherein the signal output from each of the output nodes of the fourth amplifiers is fed back to the input terminal (-) of each of the fourth amplifiers, and the signal output from each of the output nodes is applied to the input terminal (+) of the next amplifier. Claim 18 In paragraph 17, a signal generator to which the amplification voltage is applied to the input terminal (+) of the first amplifier among the four amplifiers. Claim 19 In claim 15, the signal generator comprises a plurality of amplifiers connected in series between a node to which the divided voltage is applied and an output node to which the sensing signal is output. Claim 20 A signal generator according to claim 19, wherein the signal output from each of the output nodes of the fifth amplifiers is fed back to the input terminal (-) of each of the fifth amplifiers, and the signal output from each of the output nodes is applied to the input terminal (+) of the next amplifier. Claim 21 In paragraph 20, a signal generator to which the divided voltage is applied to the input terminal (+) of the first amplifier among the five amplifiers. Claim 22 A memory device comprising: a memory block in which data is stored; page buffers connected to the memory block through bit lines; and a signal generation circuit for outputting page control signals for controlling the page buffers; wherein the signal generation circuit outputs a common sensing signal and a sensing signal included in the page control signal according to an amplification voltage and a distribution voltage generated through a feedback loop, and the page buffers precharge the bit lines or sense the voltage or current of the bit lines in response to the page control signals including the common sensing signal and the sensing signal, and the signal generation circuit comprises: a distribution circuit including at least one variable resistor and a voltage control circuit; a first amplifier that outputs the amplification voltage according to a reference voltage and a feedback voltage; and a buffer group that outputs the common sensing signal according to the amplification voltage and outputs the sensing signal according to the distribution voltage; wherein the distribution circuit comprises a distribution circuit that generates the distribution voltage and the feedback voltage by distributing the amplification voltage through the at least one variable resistor and the voltage control circuit. Claim 23 delete Claim 24 In claim 22, the above at least one variable resistor comprises a first variable resistor and a second variable resistor, and the first variable resistor, the voltage regulation circuit and the second variable resistor are connected in series with each other between the output node of the first amplifier and the ground terminal of the memory device. Claim 25 A memory device according to claim 24, wherein the divided voltage is a voltage divided between the first variable resistor and the voltage regulating circuit, and the feedback voltage is a voltage divided between the voltage regulating circuit and the second variable resistor. Claim 26 In claim 24, the voltage regulation circuit is a memory device composed of a diode or a plurality of diodes that allow current to flow from the first variable resistor in the direction of the second variable resistor. Claim 27 In claim 26, the memory device comprises the diode or the plurality of diodes having the same material, structure, and size as the switch that operates in response to the sensing signal among the plurality of switches included in the page buffers.

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