Three dimensional semiconductor memory device, electronic system including the same, and method of fabricating the same

Abstract

A three-dimensional semiconductor memory device, an electronic system including the same, and a method for manufacturing the same are provided. The device comprises: a stack structure including electrode layers and inter-electrode insulating films alternately stacked on a substrate; vertical semiconductor patterns adjacent to the substrate penetrating the stack structure; and a gate insulating film interposed between the vertical semiconductor patterns and the stack structure, wherein the gate insulating film comprises: a blocking insulating film adjacent to the stack structure; and charge storage patterns spaced apart from the stack structure with the blocking insulating film in between and arranged along the surface of the blocking insulating film, wherein the charge storage patterns have a wider width the closer they are to the blocking insulating film.

Description

Technology Field

[0001] The present invention relates to a semiconductor device, an electronic system including the same, and a method for manufacturing the same, and more specifically, to a three-dimensional semiconductor memory device with improved reliability and integration density, an electronic system including the same, and a method for manufacturing the same. Background Technology

[0002] In order to meet the superior performance and low price demands of consumers, it is required to increase the integration density of semiconductor devices. Since the integration density of semiconductor devices is a critical factor in determining product prices, particularly increased integration density is required. In the case of two-dimensional or planar semiconductor devices, the integration density is primarily determined by the area occupied by a unit memory cell, and thus is significantly influenced by the level of fine pattern formation technology. However, because ultra-expensive equipment is required for pattern miniaturization, the integration density of two-dimensional semiconductor devices is increasing but remains limited. Accordingly, three-dimensional semiconductor memory devices equipped with memory cells arranged in three dimensions are being proposed. Prior art literature

[65535] Published Patent Application No. 10-2010-0028824 (March 15, 2010) The problem to be solved

[0003] The problem that the present invention aims to solve is to provide a three-dimensional semiconductor memory device and electronic system with improved integration density and reliability.

[0004] The problem that the present invention aims to solve is to provide a method for manufacturing a three-dimensional semiconductor memory device with improved integration density and reliability.

[0005] The problems that the present invention aims to solve are not limited to those mentioned above, and other unmentioned problems will be clearly understood by those skilled in the art from the description below. means of solving the problem

[0006] A three-dimensional semiconductor memory device according to embodiments of the present invention for achieving the above objective comprises: a stack structure including electrode layers and inter-electrode insulating films alternately stacked on a substrate; vertical semiconductor patterns adjacent to the substrate penetrating the stack structure; and a gate insulating film interposed between the vertical semiconductor patterns and the stack structure, wherein the gate insulating film comprises: a blocking insulating film adjacent to the stack structure; and charge storage patterns spaced apart from the stack structure with the blocking insulating film in between and arranged along the surface of the blocking insulating film, wherein the charge storage patterns have a wider width the closer they are to the blocking insulating film.

[0007] A three-dimensional semiconductor memory device according to one aspect of the present invention comprises a peripheral circuit structure and a cell array structure disposed thereon, wherein the cell array structure comprises: a first substrate including a cell array region and a connection region disposed side by side in a first direction; a source structure on the first substrate; a stack structure including electrode layers and inter-electrode insulating films alternately stacked on the first substrate; a flat insulating film covering the end of the stack structure on the connection region; a plurality of vertical semiconductor patterns adjacent to the first substrate by penetrating the stack structure and the source structure in the cell array region; bitline pads disposed on each of the vertical patterns; and a gate insulating film interposed between the vertical semiconductor patterns and the stack structure, wherein the gate insulating film comprises: a blocking insulating film adjacent to the stack structure; and includes charge storage patterns spaced apart from the stack structure with the blocking insulating film in between and arranged along the surface of the blocking insulating film, wherein each of the vertical semiconductor patterns has silicon crystal grains, and the average size of the silicon crystal grains is larger than the average size of the charge storage patterns.

[0008] An electronic system according to the present invention for achieving the above other objectives comprises a peripheral circuit structure and a cell array structure disposed thereon, wherein the cell array structure comprises: a stack structure including electrode layers and inter-electrode insulating films alternately stacked on a substrate; vertical semiconductor patterns adjacent to the substrate through the stack structure; and a gate insulating film interposed between the vertical semiconductor patterns and the stack structure, wherein the gate insulating film comprises: a blocking insulating film adjacent to the stack structure; and charge storage patterns spaced apart from the stack structure with the blocking insulating film in between and arranged along the surface of the blocking insulating film, wherein the charge storage patterns have a wider width the closer they are to the blocking insulating film and include an input / output pad electrically connected to the peripheral circuit structure; and a controller electrically connected to the semiconductor device through the input / output pad and controlling the semiconductor device.

[0009] A method for manufacturing a three-dimensional semiconductor memory device according to the present invention for achieving the above additional objective comprises the steps of: alternately stacking sacrificial films and inter-electrode insulating films on a substrate; etching the inter-electrode insulating films and the sacrificial films to form vertical holes that expose the substrate; forming a blocking insulating film on the front surface of the substrate where the vertical holes are formed; forming an amorphous polysilicon film on the blocking insulating film; performing an annealing process to crystallize the amorphous polysilicon film to form a crystallized silicon film; etching the crystallized silicon film to form silicon crystal patterns; and forming a passivation film on the silicon crystal patterns. Effects of the invention

[0010] In a three-dimensional semiconductor memory device and an electronic system including the same according to embodiments of the present invention, charge storage patterns are spaced apart from each other. Lateral and vertical charge loss can be reduced compared to the case where charge storage patterns are connected. In addition, the charge storage patterns are formed to have a uniform size, thickness, and spacing, thereby ensuring uniform and constant reliability in data storage and erasure. Furthermore, the three-dimensional semiconductor memory device and an electronic system including the same according to embodiments of the present invention further include a capping film and / or passivation film covering the charge storage patterns to prevent defects such as dangling bonds that may be formed on the surface of the charge storage patterns, thereby reducing lateral and vertical charge loss. This improves the reliability of the three-dimensional semiconductor memory device.

[0011] A method for manufacturing a three-dimensional semiconductor memory device according to embodiments of the present invention can form charge storage patterns by forming an amorphous polysilicon film, crystallizing it through an annealing process, and then performing an etching process to etch the boundaries between silicon crystal grains. By doing so, charge storage patterns can be formed to have uniform size, thickness, and spacing. This allows for the manufacture of a three-dimensional semiconductor memory device with improved reliability. Brief explanation of the drawing

[0012] FIG. 1a is a schematic diagram showing an electronic system including a semiconductor device according to an exemplary embodiment of the present invention. FIG. 1b is a schematic perspective view of an electronic system including a semiconductor device according to an exemplary embodiment of the present invention. FIGS. 1c and FIGS. 1d are cross-sectional views schematically illustrating semiconductor packages according to exemplary embodiments of the present invention. FIG. 2 is a plan view of a three-dimensional semiconductor memory device according to embodiments of the present invention. FIG. 3 is a cross-sectional view of FIG. 2 taken along line A-A' according to embodiments of the present invention. FIG. 4 is a cross-sectional view of FIG. 2 taken along the line B-B' according to embodiments of the present invention. FIG. 5a is an enlarged view of the 'P1' portion of FIG. 4 according to embodiments of the present invention. FIGS. 5b to 5d are enlarged drawings of the 'P2' portion of FIG. 5a according to embodiments of the present invention. FIG. 6 is a partial perspective view of a three-dimensional semiconductor memory device according to embodiments of the present invention. FIG. 7a is an enlarged view of the 'P1' portion of FIG. 4 according to embodiments of the present invention. FIG. 7b is an enlarged view of the 'P2' portion of FIG. 7a according to embodiments of the present invention. FIG. 8 is an enlarged view of the 'P1' portion of FIG. 4 according to embodiments of the present invention. FIGS. 9a to 9e are cross-sectional views sequentially illustrating the process of manufacturing a three-dimensional semiconductor memory device having the cross-section of FIG. 4. FIG. 10 is a process flowchart showing the process of forming charge storage patterns according to embodiments of the present invention. FIGS. 11a to 11e are process cross-sectional views of the P1 portion of FIG. 9c, enlarged. FIG. 12 is a cross-sectional view of a semiconductor device according to an exemplary embodiment of the present invention. Specific details for implementing the invention

[0013] Hereinafter, in order to explain the present invention more specifically, embodiments according to the present invention will be described in more detail with reference to the accompanying drawings.

[0015] FIG. 1a is a schematic diagram showing an electronic system including a semiconductor device according to an exemplary embodiment of the present invention.

[0016] Referring to FIG. 1a, an electronic system (1000) according to an exemplary embodiment of the present invention may include a semiconductor device (1100) and a controller (1200) electrically connected to the semiconductor device (1100). The electronic system (1000) may be a storage device or an electronic device including a storage device, comprising one or more semiconductor devices (1100). For example, the electronic system (1000) may be a solid state drive device (SSD), a Universal Serial Bus (USB), a computing system, a medical device, or a communication device, comprising one or more semiconductor devices (1100).

[0017] The semiconductor device (1100) may be a non-volatile memory device, for example, a NAND flash memory device. The semiconductor device (1100) may include a first structure (1100F) and a second structure (1100S) on the first structure (1100F). In exemplary embodiments, the first structure (1100F) may be placed next to the second structure (1100S). The first structure (1100F) may be a peripheral circuit structure including a decoder circuit (1110), a page buffer circuit (1120), and a logic circuit (1130). The second structure (1100S) may be a memory cell structure comprising a bit line (BL), a common source line (CSL), word lines (WL), first and second gate upper lines (UL1, UL2), first and second gate lower lines (LL1, LL2), and memory cell strings (CSTR) between the bit line (BL) and the common source line (CSL).

[0018] In the second structure (1100S), each memory cell string (CSTR) may include lower transistors (LT1, LT2) adjacent to a common source line (CSL), upper transistors (UT1, UT2) adjacent to a bit line (BL), and a plurality of memory cell transistors (MCT) disposed between the lower transistors (LT1, LT2) and the upper transistors (UT1, UT2). The number of lower transistors (LT1, LT2) and the number of upper transistors (UT1, UT2) may vary depending on the embodiments.

[0019] In exemplary embodiments, the upper transistors (UT1, UT2) may include string select transistors, and the lower transistors (LT1, LT2) may include ground select transistors. The gate lower lines (LL1, LL2) may each be the gate electrodes of the lower transistors (LT1, LT2). The word lines (WL) may be the gate electrodes of the memory cell transistors (MCT), and the gate upper lines (UL1, UL2) may each be the gate electrodes of the upper transistors (UT1, UT2).

[0020] In exemplary embodiments, the lower transistors (LT1, LT2) may include a lower erase control transistor (LT1) and a ground select transistor (LT2) connected in series. The upper transistors (UT1, UT2) may include a string select transistor (UT1) and an upper erase control transistor (UT2) connected in series. At least one of the lower erase control transistor (LT1) and the upper erase control transistor (UT2) may be used for an erase operation to delete data stored in memory cell transistors (MCTs) using the Gate Induced Drain Leakage (GIDL) phenomenon.

[0021] The common source line (CSL), the first and second gate lower lines (LL1, LL2), the word lines (WL), and the first and second gate upper lines (UL1, UL2) can be electrically connected to the decoder circuit (1110) through first connecting wires (1115) extending from the first structure (1100F) to the second structure (1100S). The bit lines (BL) can be electrically connected to the page buffer circuit (1120) through second connecting wires (1125) extending from the first structure (1100F) to the second structure (1100S).

[0022] In the first structure (1100F), the decoder circuit (1110) and the page buffer circuit (1120) can perform control operations on at least one selected memory cell transistor among a plurality of memory cell transistors (MCTs). The decoder circuit (1110) and the page buffer circuit (1120) can be controlled by the logic circuit (1130). The semiconductor device (1100) can communicate with the controller (1200) through an input / output pad (1101) that is electrically connected to the logic circuit (1130). The input / output pad (1101) can be electrically connected to the logic circuit (1130) through an input / output connection wire (1135) that extends from the first structure (1100F) to the second structure (1100S).

[0023] The controller (1200) may include a processor (1211), a NAND controller (1220), and a host interface (1230). According to embodiments, the electronic system (1000) may include a plurality of semiconductor devices (1100), and in this case, the controller (1200) may control the plurality of semiconductor devices (1100).

[0024] The processor (1211) can control the operation of the entire electronic system (1000), including the controller (1200). The processor (1211) can operate according to a predetermined firmware and can access the semiconductor device (1100) by controlling the NAND controller (1220). The NAND controller (1220) may include a NAND interface (1221) that handles communication with the semiconductor device (1100). Through the NAND interface (1221), control commands for controlling the semiconductor device (1100), data to be written to the memory cell transistors (MCT) of the semiconductor device (1100), data to be read from the memory cell transistors (MCT) of the semiconductor device (1100), etc., may be transmitted. The host interface (1230) may provide communication functions between the electronic system (1000) and an external host. When a control command is received from an external host through the host interface (1230), the processor (1211) can control the semiconductor device (1100) in response to the control command.

[0025] FIG. 1b is a schematic perspective view of an electronic system including a semiconductor device according to an exemplary embodiment of the present invention.

[0026] Referring to FIG. 1b, an electronic system (2000) according to an exemplary embodiment of the present invention may include a main board (2001), a controller (2002) mounted on the main board (2001), one or more semiconductor packages (2003), and a DRAM (2004). The semiconductor package (2003) and the DRAM (2004) may be connected to the controller (2002) by wiring patterns (2005) formed on the main board (2001).

[0027] The main board (2001) may include a connector (2006) comprising a plurality of pins that are coupled to an external host. The number and arrangement of the plurality of pins in the connector (2006) may vary depending on the communication interface between the electronic system (2000) and the external host. In exemplary embodiments, the electronic system (2000) may communicate with the external host according to any one of interfaces such as USB (Universal Serial Bus), PCI-Express (Peripheral Component Interconnect Express), SATA (Serial Advanced Technology Attachment), and M-Phy for UFS (Universal Flash Storage). In exemplary embodiments, the electronic system (2000) may operate by power supplied from the external host through the connector (2006). The electronic system (2000) may further include a Power Management Integrated Circuit (PMIC) that distributes power supplied from the external host to a controller (2002) and a semiconductor package (2003).

[0028] The controller (2002) can write data to the semiconductor package (2003) or read data from the semiconductor package (2003), and can improve the operating speed of the electronic system (2000).

[0029] The DRAM (2004) may be a buffer memory to mitigate the speed difference between the semiconductor package (2003), which is a data storage space, and an external host. The DRAM (2004) included in the electronic system (2000) may also function as a type of cache memory and may provide a space for temporarily storing data during control operations on the semiconductor package (2003). When the electronic system (2000) includes the DRAM (2004), the controller (2002) may further include a DRAM controller for controlling the DRAM (2004) in addition to the NAND controller for controlling the semiconductor package (2003).

[0030] A semiconductor package (2003) may include first and second semiconductor packages (2003a, 2003b) spaced apart from each other. The first and second semiconductor packages (2003a, 2003b) may each be a semiconductor package including a plurality of semiconductor chips (2200). Each of the first and second semiconductor packages (2003a, 2003b) may include a package substrate (2100), semiconductor chips (2200) on the package substrate (2100), adhesive layers (2300) disposed on the lower surface of each of the semiconductor chips (2200), a connecting structure (2400) electrically connecting the semiconductor chips (2200) and the package substrate (2100), and a molding layer (2500) covering the semiconductor chips (2200) and the connecting structure (2400) on the package substrate (2100).

[0031] The package substrate (2100) may be a printed circuit board including package upper pads (2130). Each semiconductor chip (2200) may include an input / output pad (2210). The input / output pad (2210) may correspond to the input / output pad (1101) of FIG. 1A. Each of the semiconductor chips (2200) may include gate stacking structures (3210) and vertical structures (3220). Each of the semiconductor chips (2200) may include a semiconductor device according to embodiments of the present invention described below.

[0032] In exemplary embodiments, the connection structure (2400) may be a bonding wire that electrically connects the input / output pad (2210) and the package upper pads (2130). Accordingly, in each of the first and second semiconductor packages (2003a, 2003b), the semiconductor chips (2200) may be electrically connected to each other by a bonding wire method and may be electrically connected to the package upper pads (2130) of the package substrate (2100). According to embodiments, in each of the first and second semiconductor packages (2003a, 2003b), the semiconductor chips (2200) may be electrically connected to each other by a connection structure including a through silicon via (TSV) instead of the bonding wire method connection structure (2400).

[0033] In exemplary embodiments, the controller (2002) and the semiconductor chips (2200) may be included in a single package. In an exemplary embodiment, the controller (2002) and the semiconductor chips (2200) may be mounted on a separate interposer substrate different from the main substrate (2001), and the controller (2002) and the semiconductor chips (2200) may be connected to each other by wiring formed on the interposer substrate.

[0034] FIGS. 1C and 1D are schematic cross-sectional views of semiconductor packages according to exemplary embodiments of the present invention. FIGS. 1C and 1D each illustrate exemplary embodiments of the semiconductor package of FIG. 1B and conceptually show a region of the semiconductor package of FIG. 1B cut along the cutting line I-I'.

[0035] Referring to FIG. 1c, in a semiconductor package (2003), the package substrate (2100) may be a printed circuit board. The package substrate (2100) may include a package substrate body portion (2120), package upper pads (2130 in FIG. 1b) disposed on the upper surface of the package substrate body portion (2120), lower pads (2125) disposed on the lower surface of the package substrate body portion (2120) or exposed through the lower surface, and internal wiring (2135) electrically connecting the upper pads (2130) and the lower pads (2125) inside the package substrate body portion (2120). The upper pads (2130) may be electrically connected to connection structures (2400). The lower pads (2125) can be connected to the wiring patterns (2005) of the main board (2010) of the electronic system (2000) through conductive connections (2800) as in FIG. 1B.

[0036] Each of the semiconductor chips (2200) may include a semiconductor substrate (3010) and a first structure (3100) and a second structure (3200) that are sequentially stacked on the semiconductor substrate (3010). The first structure (3100) may include a peripheral circuit region including peripheral wiring (3110). The second structure (3200) may include a source structure (3205), a stacked structure (3210) on the source structure (3205), vertical structures (3220) penetrating the stacked structure (3210), bit lines (3240) electrically connected to the vertical structures (3220), and cell contact plugs (3235) electrically connected to the word lines (WL in FIG. 1) of the stacked structure (3210). Each of the first structure (3100) / second structure (3200) / semiconductor chips (2200) may further include separation structures described later.

[0037] Each of the semiconductor chips (2200) may include a through-wire (3245) that is electrically connected to the peripheral wiring (3110) of the first structure (3100) and extends into the second structure (3200). The through-wire (3245) may be positioned outside the stacked structure (3210) and may be further positioned to penetrate the stacked structure (3210). Each of the semiconductor chips (2200) may further include an input / output pad (2210 of FIG. 1b) that is electrically connected to the peripheral wiring (3110) of the first structure (3100).

[0038] Referring to FIG. 1d, in a semiconductor package (2003A), each of the semiconductor chips (2200a) may include a semiconductor substrate (4010), a first structure (4100) on the semiconductor substrate (4010), and a second structure (4200) bonded to the first structure (4100) by a wafer bonding method on the first structure (4100).

[0039] The first structure (4100) may include a peripheral circuit area comprising peripheral wiring (4110) and first junction structures (4150). The second structure (4200) may include a source structure (4205), a stacked structure (4210) between the source structure (4205) and the first structure (4100), vertical structures (4220) penetrating the stacked structure (4210), and second junction structures (4250) electrically connected to the word lines (WL in FIG. 1a) of the vertical structures (4220) and the stacked structure (4210), respectively. For example, the second bonding structures (4250) can be electrically connected to the vertical structures (4220) and the word lines (WL in FIG. 1) respectively through cell contact plugs (4235) that are electrically connected to the bit lines (4240) and the word lines (WL in FIG. 1) that are electrically connected to the vertical structures (4220). The first bonding structures (4150) of the first structure (4100) and the second bonding structures (4250) of the second structure (4200) can be bonded while in contact with each other. The bonded portions of the first bonding structures (4150) and the second bonding structures (4250) can be formed of, for example, copper (Cu).

[0040] Each of the first structure (4100) / second structure (4200) / semiconductor chips (2200a) may further include a source structure according to the embodiments described below. Each of the semiconductor chips (2200a) may further include an input / output pad (2210 of FIG. 1b) electrically connected to the peripheral wiring (4110) of the first structure (4100).

[0041] The semiconductor chips (2200) of FIG. 1c and the semiconductor chips (2200a) of FIG. 1d may be electrically connected to each other by connection structures (2400) in the form of bonding wires. However, in exemplary embodiments, semiconductor chips within a single semiconductor package, such as the semiconductor chips (2200) of FIG. 1c and the semiconductor chips (2200a) of FIG. 1d, may be electrically connected to each other by connection structures including through-vias (TSVs).

[0042] The first structure (3100) of FIG. 1c and the first structure (4100) of FIG. 1d may correspond to a peripheral circuit structure in the embodiments described below, and the second structure (3200) of FIG. 1c and the second structure (4200) of FIG. 1d may correspond to a cell array structure in the embodiments described below.

[0044] FIG. 2 is a plan view of a three-dimensional semiconductor memory device according to embodiments of the present invention. FIG. 3 is a cross-sectional view taken along line A-A' of FIG. 2 according to embodiments of the present invention. FIG. 4 is a cross-sectional view taken along line B-B' of FIG. 2 according to embodiments of the present invention. FIG. 5a is an enlarged view of the 'P1' portion of FIG. 4 according to embodiments of the present invention. FIG. 5b to 5d are enlarged views of the 'P2' portion of FIG. 5a according to embodiments of the present invention. FIG. 6 is a partial perspective view of a three-dimensional semiconductor memory device according to embodiments of the present invention.

[0045] Referring to FIGS. 2, 3, and 4, a cell array structure (CS) is placed on a peripheral circuit structure (PS). The cell array structure (CS) may include blocks (BLK) arranged side by side in a second direction (D2). Most of the blocks (BLK) may be memory blocks where data program / read / erase operations are performed. Alternatively, some of the blocks (BLK) may be dummy blocks where data program / read / erase operations are not performed. The blocks (BLK) may be separated by first isolation lines (SL1). FIG. 2 illustrates one of the blocks (BLK).

[0046] The first isolation insulation line (SL1) may extend along a first direction (D1) that intersects the second direction (D2). The first isolation insulation line (SL1) may be placed within a first groove (G1). The first isolation insulation line (SL1) may have a single or multiple film structure among at least one silicon oxide film, silicon nitride film, silicon oxynitride film, and porous insulating film. Each of the blocks (BLK) may include a cell array region (CAR) and a connection region (CNR) placed at both ends thereof.

[0047] Each block (BLK) can be divided into two sub-blocks (SBLK) by a second isolation line (SL2) that passes through its center and extends in a first direction (D1). The second isolation line (SL2) is not interrupted in the cell array area (CAR) and can extend to the connection area (CNR). The second isolation line (SL2) can be interrupted and divided into two at the connection area (CNR). The second isolation line (SL2) can be placed within the second groove (G2).

[0048] A peripheral circuit structure (PS) includes a first substrate (103). The first substrate (103) may be a silicon single-crystal substrate or a Silicon on Insulator (SOI) substrate. A device isolation film (105) may be disposed on the first substrate (103) to define active regions. Peripheral transistors (PTRs) may be disposed on the active regions. Each of the peripheral transistors (PTRs) may include a peripheral gate electrode, a peripheral gate insulating film, and peripheral source / drain regions disposed within the first substrate (103) adjacent to both sides thereof. The peripheral transistors (PTRs) may be covered by a peripheral interlayer insulating film (107). The peripheral interlayer insulating film (107) may have a single-film or multi-film structure among at least one silicon oxide film, silicon nitride film, silicon oxynitride film, and porous insulating film. Peripheral wiring (109) and peripheral contacts (33) may be disposed within the above peripheral interlayer insulating film (107). The peripheral wiring (109) and peripheral contacts (33) may include a conductive film.

[0049] Some of the peripheral wiring (109) and peripheral contacts (33) may be electrically connected to the peripheral transistors (PTR). The peripheral wiring (109) and the peripheral transistors (PTR) may form the page buffer circuit (1120) and decoder circuit (1110) of FIG. 1a. The peripheral circuit structure (PS) may include conductive pads (30b) positioned on top.

[0050] An etch stop layer (111) is disposed on the above peripheral circuit structure (PS). The etch stop layer (111) may include a material having etch selectivity with respect to the second substrate (201) and the peripheral interlayer insulating film (107). For example, the etch stop layer (111) may include silicon nitride or silicon oxide. The etch stop layer (111) may also be referred to as an 'adhesive film'.

[0051] Each block (BLK) belonging to the cell array structure (CS) may include a second substrate (201), a source structure (SCL), a first sub-stack structure (ST1), a second sub-stack structure (ST2), and first to third upper insulating films (205, 208, 209) stacked in sequence. The first sub-stack structure (ST1) may include first electrode layers (EL1) and first electrode interlayer insulating films (12) stacked alternately. The second sub-stack structure (ST2) may include second electrode layers (EL2) and second electrode interlayer insulating films (22) stacked alternately, and a top second electrode interlayer insulating film (24) located at the top layer. The second substrate (201) may be, for example, a silicon single crystal layer, a silicon epitaxial layer, or an SOI substrate. The second substrate (201) may be doped with, for example, an impurity of the first conductivity type. The impurity of the first conductivity type may be, for example, P-type boron. Or the impurity of the first conductivity type may be N-type arsenic or phosphorus.

[0052] The one located at the bottom and the one located above it among the first electrode layers (EL1) may correspond to the gate lower lines (LL1, LL2) of FIG. 1a, and may correspond to the gate electrodes of the lower transistors (LT1, LT2), namely the lower erase control transistor (LT1) and the ground select transistor (LT2).

[0053] At least two second electrode layers (EL2) located at the top of a sub-block (SBLK) may be separated into multiple lines by a source groove (CG) to form the gate upper lines (UL1, UL2). The uppermost and the lowermost of the second electrode layers (EL2) may correspond to the gate electrodes of the upper transistors (UT1, UT2), namely the upper erase control transistor (UT2) and the string select transistor (UT1), respectively. The other electrode layers (EL1, EL2) may correspond to the word lines (WL) of FIG. 1a. At least one of the other electrode layers (EL1, EL2) may be a dummy word line that does not actually operate.

[0054] The electrode layers (EL1, EL2) may include at least one selected from, for example, a doped semiconductor (e.g., doped silicon, etc.), a metal (e.g., tungsten, copper, aluminum, etc.), a conductive metal nitride (e.g., titanium nitride, tantalum nitride, etc.), or a transition metal (e.g., titanium, tantalum, etc.). The electrode interlayer insulating films (12, 22, 24) may include at least one single film or multiple film selected from a silicon oxide film, a silicon nitride film, a silicon oxynitride film, and a porous insulating film.

[0055] The source structure (SCL) may include a first source pattern (SC1) interposed between an electrode interlayer insulating film (12) located at the bottom layer and a second substrate (201), and a second source pattern (SC2) interposed between the first source pattern (SC1) and the second substrate (201). The first source pattern (SC1) may include an impurity-doped semiconductor pattern, for example, polysilicon doped with an impurity of a first conductivity type. The second source pattern (SC2) may include an impurity-doped semiconductor pattern, for example, polysilicon doped with an impurity. The second source pattern (SC2) may further include a semiconductor material different from the first source pattern (SC1). The conductivity type of the impurity doped in the second source pattern (SC2) may be the same as the conductivity type of the impurity doped in the first source pattern (SC1). The concentration of impurities doped in the second source pattern (SC2) may be equal to or different from the concentration of impurities doped in the first source pattern (SC1). The source structure (SCL) may correspond to the common source line (CSL) of FIG. 1a. Additionally, the second substrate (201) may also function as the common source line (CSL) of FIG. 1a.

[0056] Referring to FIGS. 2 and 4, in the cell array region (CAR) of each sub-block (SBLK), the electrode interlayer insulating films (12, 22, 24) and the electrode layers (EL1, EL2) can be penetrated by cell vertical patterns (VS) and center dummy vertical patterns (CDVS). The center dummy vertical patterns (CDVS) ​​can be arranged in a row along a first direction (D1). The center separation pattern (9) can be placed between the upper portions of the center dummy vertical patterns (CDVS). A gate insulating film (GO) can be interposed between the electrode layers (EL1, EL2) and the cell vertical patterns (VS), and between the electrode layers (EL1, EL2) and the center dummy vertical patterns (CDVS).

[0057] The cell vertical patterns (VS) and the center pile vertical patterns (CDVS) ​​may each have a hollow cup shape. The side walls of the cell vertical patterns (VS) and the center pile vertical patterns (CDVS) ​​may have an inflection point (IFP) adjacent to the first sub-stack structure (ST1) and the second sub-stack structure (ST2).

[0058] The interiors of the cell vertical patterns (VS) and the center pile vertical patterns (CDVS) ​​may be filled with a buried insulation pattern (29). The buried insulation pattern (29) may have a single or multilayer structure, for example, of silicon oxide, silicon nitride, or silicon oxynitride. A bitline pad (BPD) may be disposed on each of the cell vertical patterns (VS) and the center pile vertical patterns (CDVS). The bitline pad (BPD) may include impurity-doped polysilicon, or metals such as tungsten, aluminum, and copper.

[0059] Referring to FIGS. 5a through 6, the gate insulating film (GO) may include a tunnel insulating film (TL), a passivation film (PL), charge storage patterns (SN), and a blocking insulating film (BCL). The tunnel insulating film (TL) may be one of the materials having a band gap larger than that of the charge storage patterns (SN). For example, the tunnel insulating film (TL) may include silicon oxide. The blocking insulating film (BCL) may be silicon oxide, or a high dielectric film having a dielectric constant higher than that of silicon oxide. For example, the high dielectric film may include metal oxides such as aluminum oxide and hafnium oxide.

[0060] The charge storage patterns (SN) may each be silicon crystal patterns that are doped with or undoped with impurities. The silicon crystal patterns may also be referred to as 'nanocrystalline silicon (nanocrystalline Si)' or 'silicon nanocrystals'. The impurities may be phosphorus, arsenic, or boron. The charge storage patterns (SN) may be in contact with the blocking insulating film (BCL) and may be spaced apart from the cell vertical patterns (VS) and the center pile vertical patterns (CDVS). The charge storage patterns (SN) may be spaced apart from each other.

[0061] As shown in FIGS. 5a to 5d, the side (SN_W) of the charge storage patterns (SN) may be inclined with respect to the surface of the blocking insulating film (BCL). Each of the charge storage patterns (SN) may have a trapezoidal cross-section. Each of the charge storage patterns (SN) may have a first part (SN_P1) and a second part (SN_P2). In one charge storage pattern (SN), the first part (SN_P1) and the second part (SN_P2) are integrally formed with each other. The second part (SN_P2) may be in contact with the blocking insulating film, and the first part (SN_P1) may be spaced apart from the blocking insulating film. The width of the first part (SN_P1) may be different from the width of the second part (SN_P2). Preferably, the width of the first portions (SN_P1) may be narrower than the width of the second portions (SN_P2). The first width (WD1) of each of the charge storage patterns (SN) may increase as it approaches the blocking insulating film (BCL). The width (WD1_U) of the upper surface (SN_U) of each of the charge storage patterns (SN) may be narrower than the width (WD1_B) of the lower surface (SN_B) of each of the charge storage patterns (SN).

[0062] Or in another example, the width (WD1_U) of the upper surface (SN_U) of each of the charge storage patterns (SN) may be wider than the width (WD1_B) of the lower surface (SN_B) of each of the charge storage patterns (SN). The first width (WD1) of each of the charge storage patterns (SN) may become smaller as it approaches the blocking insulating film (BCL).

[0063] In one example, the charge storage patterns (SN) may have the same shape / size / thickness / spacing as each other. Or, the charge storage patterns (SN) may have similar / uniform shapes / sizes / thickness / spacing as each other.

[0064] The width (WD1_U) of the upper surface (SN_U) of each of the charge storage patterns (SN) may be 3 nm to 10 nm on average. In this specification, the term 'width' of any configuration may refer to the '(average) size' or '(average) diameter' of the configuration. The spacing (DS1) between the charge storage patterns (SN) may be 1 Å to 10 nm.

[0065] As shown in FIG. 6, the charge storage patterns (SN) can be arranged two-dimensionally along the surface of the blocking insulating film (BCL). When viewed in a direction perpendicular to the surface of the blocking insulating film (BCL), the charge storage patterns (SN) can each have a polygonal plane such as a square, trapezoid, pentagon, hexagon, heptagon, or octagon. In the three-dimensional semiconductor memory device, the dispersion / variation rate of the width (WD1_U) of the upper surface (SN_U) of the charge storage patterns (SN) can be 0.5 to 10% of the width (WD1_U). The dispersion / variation rate of the spacing (DS1) between the charge storage patterns (SN) can be 0.5 to 10% of the spacing (DS1).

[0066] The charge storage patterns (SN) according to the present example are spaced apart from each other. Compared to the case where the charge storage patterns (SN) are connected, lateral / vertical charge loss can be reduced. That is, by preventing charge spreading, the reliability of the three-dimensional semiconductor memory device can be improved.

[0067] In addition, the charge storage patterns (SN) have a uniform width (WD1_U) with a dispersion of less than 10% and a uniform spacing with a dispersion of less than 10%. This ensures uniform and constant reliability in data storage / erasing on the charge storage patterns (SN). As a result, Fowler-Nordheim Erase is possible, increasing Program / Erase speed and enabling Deep Erase. This can improve Erase saturation.

[0068] As shown in FIGS. 5a to 5d, the charge storage patterns (SN) are covered with a passivation film (PL). The passivation film (PL) may have a single film or multiple film structure among at least one of SiN, SiO, SiON, or metal oxide.

[0069] As shown in FIG. 5b, the passivation film (PL) can be in direct contact with the surface of the charge storage patterns (SN). In this case, the passivation film (PL) can reduce lateral / vertical charge loss by blocking defects, such as dangling bonds, that may form on the surface of the charge storage patterns (SN). The passivation film (PL) can be located between the charge storage patterns (SN) and can be in contact with a blocking insulating film (BCL).

[0070] Alternatively, as shown in FIG. 5c, the top surface (SN_U) and side surface (SN_W) of the charge storage patterns (SN) may be covered with a capping film (CPL). A passivation film (PL) may be located between the charge storage patterns (SN) and may be in contact with a blocking insulating film (BCL). Alternatively, as shown in FIG. 5d, the top surface (SN_U) and side surface (SN_W) of the charge storage patterns (SN) and the blocking insulating film (BCL) may be covered with a capping film (CPL). A passivation film (PL) may be located between the charge storage patterns (SN) and may be spaced apart from the blocking insulating film (BCL). The capping film (CPL) may comprise silicon oxide or silicon nitride. The capping film (CPL) can prevent defects such as dangling bonds that may form on the surface of charge storage patterns (SN), thereby reducing lateral / vertical charge loss.

[0071] The cell vertical patterns (VS) and the center pile vertical patterns (CDVS) ​​may comprise, for example, a silicon single crystal layer or polysilicon that is not doped with impurities. Alternatively, the cell vertical patterns (VS) and the center pile vertical patterns (CDVS) ​​may each have first silicon crystal grains (SG1). A first boundary (SG1_B) or first grain boundaries may exist between the first silicon crystal grains (SG1). The first silicon crystal grains (SG1) may each have a second width (WD2) (or a second average size) in a direction parallel to the surface of the blocking insulating film (BCL) (or a third direction (D3)). The second width (WD2) may differ from the first width (WD1) (or first average size) of each of the charge storage patterns (SN). Preferably, the second width (WD2) may be larger than the first width (WD1) (or first average size) of each of the charge storage patterns (SN). Or, in another example, the second width (WD2) may be smaller than the first width (WD1) (or first average size) of each of the charge storage patterns (SN).

[0072] Each charge storage pattern (SN) may have a first vertical thickness (VT1) in a direction perpendicular to the surface of the blocking insulating film (BCL) (or a second direction (D2)). Each cell vertical pattern (VS) and center pile vertical pattern (CDVS) ​​may have a second vertical thickness (VT2) in a direction perpendicular to the surface of the blocking insulating film (BCL) (or a second direction (D2)). The first vertical thickness (VT1) may be smaller than the second vertical thickness (VT2).

[0073] The electrode layers (EL1, EL2) may each have a third width (WD3) in a third direction (D3). The third width (WD3) of each of the electrode layers (EL1, EL2) may be smaller than the width (WD1_U) of the upper surface (SN_U) of the charge storage patterns (SN).

[0074] The gate insulating film (GO) may further include a high dielectric film (HL). The high dielectric film (HL) may be interposed between the blocking insulating film (BCL) and the electrode layers (EL1, EL2). The high dielectric film (HL) may be interposed between the electrode layers (EL1, EL2) and the electrode interlayer insulating films (12, 22, 24). The high dielectric film (HL) is a film having a higher dielectric constant than a silicon oxide film and may include, for example, a metal oxide film such as a hafnium oxide film or an aluminum oxide film.

[0075] The second source pattern (SC2) can penetrate the gate insulating film (GO) and come into contact with the cell vertical patterns (VS). The lower part of the gate insulating film (GO) can be separated from the upper part of the gate insulating film (GO) by the second source pattern (SC2). Thus, the lower part of the gate insulating film (GO) can be separated from the upper part of the gate insulating film (GO) by the second source pattern (SC2) and become the remaining gate insulating film (GOr).

[0076] The residual gate insulating layer (GOr) may include a residual tunnel insulating layer (TLr), a residual passivation layer (PLr), residual charge storage patterns (SNr), and a residual blocking insulating layer (BCLr). The residual tunnel insulating layer (TLr) may be part of the tunnel insulating layer (TL). The residual passivation layer (PLr) may be part of the passivation layer (PL). The shape, structure, and material of the residual charge storage patterns (SNr) may be identical to the charge storage pattern (SN). The residual charge storage patterns (SNr) may be dummy charge storage patterns that do not perform data storage functions. The residual blocking insulating layer (BCLr) may be part of the blocking insulating layer (BCL).

[0077] Referring again to FIG. 4, the first isolation insulation lines (SL1) and the second isolation insulation lines (SL2) can each penetrate the first upper interlayer insulating film (205) and the sub-stack structures (ST1, ST2). The first isolation insulation lines (SL1) and the second isolation insulation lines (SL2) can each preferably be formed of silicon oxide. In the present example, the first isolation insulation lines (SL1) and the second isolation insulation lines (SL2) can penetrate the source structure (SCL) and come into contact with the second substrate (201). Or in another example, the first isolation insulation lines (SL1) and the second isolation insulation lines (SL2) can penetrate the first source pattern (SC1) of the source structure (SCL) and come into contact with the second source pattern (SC2). The levels of the lower surfaces of the first separation insulation lines (SL1) and the second separation insulation lines (SL2) may be the same.

[0078] Although not shown, a source conductive plug or source conductive line is disposed in each of the first isolation insulation lines (SL1) and the second isolation insulation lines (SL2) to come into contact with the second substrate (201) or the source structure (SCL).

[0079] Referring to FIGS. 3 and 4, a second upper interlayer insulating film (208) may be disposed on a first upper interlayer insulating film (205). First conductive lines (BLL) that extend in a second direction (D2) and are parallel to each other may be disposed on the second upper interlayer insulating film (208). The first conductive lines (BLL) may correspond to the bit lines (BL) of FIG. 1a. On a cell array region (CAR), first contacts (CT1) may penetrate the first and second upper interlayer insulating films (205, 208) to connect one of the first conductive lines (BLL) with bit line pads (BPD) disposed on cell vertical patterns (VS).

[0080] Referring to FIGS. 2 and 3, the sub-stack structures (ST1, ST2) belonging to each of the blocks (BLK) may have a stepped shape in the connection area (CNR). That is, the electrode layers (EL1, EL2) and the electrode interlayer insulating films (12, 22, 24) may have a stepped shape in the connection area (CNR). The closer to the surrounding circuit structure (PS), the electrode layers (EL1, EL2) and the electrode interlayer insulating films (12, 22, 24) may be elongated and protrude in the first direction (D1). In the connection area (CNR), the end of the first sub-stack structure (ST1) may be covered with a first flat insulating film (210). In the connection area (CNR), the end of the second sub-stack structure (ST2) may be covered with a second flat insulating film (220). The first and second flat insulating films (210, 220) may include a silicon oxide film or a porous insulating film. First to third upper interlayer insulating films (205, 208, 209) may be sequentially laminated on the first and second flat insulating films (210, 220).

[0081] The ends of the electrode layers (EL1, EL2) can be connected to cell contact plugs (CC), respectively. The cell contact plugs (CC) can penetrate the first and second upper interlayer insulating films (205, 208) and the electrode interlayer insulating films (12, 22, 24) to come into contact with the electrode layers (EL1, EL2), respectively.

[0082] Referring to FIG. 2, the ends of the flat insulating films (210, 220), the stepped electrode layers (EL1, EL2), and the inter-electrode insulating films (12, 22, 24) can be penetrated by edge dummy vertical patterns (EDVS). The edge dummy vertical patterns (EDVS) may have an elliptical shape that is elongated in a certain direction in a planar manner. The cross-section of the edge dummy vertical patterns (EDVS) may be identical to / similar to the vertical semiconductor pattern (VS) of FIG. 4. The interior of the edge dummy vertical patterns (EDVS) may also be filled with a buried insulating pattern (29). A gate insulating film (GO) may be interposed between the edge dummy vertical patterns (EDVS) and the electrode layers (EL1, EL2). A bitline pad (BPD) may also be placed on the edge dummy vertical patterns (EDVS). However, the above edge dummy vertical patterns (EDVS) are not connected to the first conduction line (BLL).

[0083] Referring again to FIG. 3, an electrode connection wiring (CL) may be disposed on the second upper interlayer insulating film (208). In the connection region (CNR), an edge-penetrating via (ETHV) may penetrate the first upper interlayer insulating film (205), the flat insulating films (210, 220), the second substrate (201), and the etch stop film (111) to contact each surrounding conductive pad (30b). In this example, the edge-penetrating vias (ETHV) may be spaced apart from the sub-stack structures (ST1, ST2). The edge-penetrating vias (ETHV) may each be connected to the electrode connection wiring (CL) by third contacts (CT3) disposed within the second upper interlayer insulating film (208). Thus, the electrode layers (EL1, EL2) can be connected to the surrounding circuit structure (PS), for example, the decoder circuit (1110 in FIG. 1a). A via insulating pattern (SP2) may be interposed between the edge-through via (ETHV) and the flat insulating films (210, 220), and between the edge-through via (ETHV) and the etch stop film (111).

[0084] Each edge-through via (ETHV) may comprise at least one metal selected from tungsten, aluminum, copper, titanium, and tantalum. Each via insulating pattern (SP2) may comprise an insulating material such as silicon oxide, silicon nitride, and silicon oxynitride.

[0085] Referring to FIGS. 2 and 3, a substrate ground region (WR) may be disposed within the second substrate (201) at a location spaced apart from the edge penetration vias (ETHV). The substrate ground region (WR) may be doped with impurities of a first conductivity type doped within the second substrate (201), and may be doped at a higher concentration than the concentration of impurities doped in the second substrate (201). In the connection region (CNR), a substrate contact plug (WC) may penetrate the first upper interlayer insulating film (205) and the flat insulating films (210, 220) to come into contact with the substrate ground region (WR).

[0086] The electrode connection wires (CL) may be covered with a third upper interlayer insulating film (209). An external terminal (CP) may be disposed on the third upper interlayer insulating film (209). A fourth contact (CT4) may penetrate the third and second upper interlayer insulating films (209, 208) to connect the external terminal (CP) and the substrate contact plug (WC). The sidewall of the substrate contact plug (WC) may be covered with a contact insulating pattern (SP3).

[0088] FIG. 7a is an enlarged view of the 'P1' portion of FIG. 4 according to embodiments of the present invention. FIG. 7b is an enlarged view of the 'P2' portion of FIG. 7a according to embodiments of the present invention.

[0089] Referring to FIGS. 7a and 7b, charge storage patterns (SN) according to the present example can be connected to each other. Each of the charge storage patterns (SN) may have a first part (SN_P1) and a second part (SN_P2). In one charge storage pattern (SN), the first part (SN_P1) and the second part (SN_P2) are integrally formed with each other. The second parts (SN_P2) are in contact with the blocking insulating film. The second parts (SN_P2) can be connected to each other. Thus, the charge storage patterns (SN) can be connected to each other to form a charge storage film (SN).

[0090] A second silicon crystal boundary (SG2_B) may exist between the second portions (SN_P2). The first portions (SN_P1) may be spaced apart from the blocking insulating film. The first portions (SN_P1) may be spaced apart from each other. The width of the first portions (SN_P1) may be narrower than the width of the second portions (SN_P2). The side (SN_W) of the first portions (SN_P1) may be inclined with respect to the surface of the blocking insulating film (BCL). The width (WD1_U) of the upper surface (SN_U) of each of the charge storage patterns (SN) may have a size of 3 nm to 10 nm on average.

[0091] As shown in FIG. 6, the first portions (SN_P1) of the charge storage patterns (SN) can be arranged two-dimensionally along the surface of the blocking insulating film (BCL). When viewed in a direction perpendicular to the surface of the blocking insulating film (BCL), the first portions (SN_P1) of the charge storage patterns (SN) can each have a polygonal plane such as a triangle, square, trapezoid, pentagon, hexagon, heptagon, or octagon. The dispersion of the width (WD1_U) of the upper surface (SN_U) of the charge storage patterns (SN) can be 0.5 to 10%.

[0092] In the present example, the first portions (SN_P1) of the charge storage patterns (SN) are spaced apart from each other. This allows for a relative reduction in lateral / vertical charge loss compared to the case where the charge storage patterns (SN) are fully connected. Additionally, the first portions (SN_P1) of the charge storage patterns (SN) have a uniform width (WD1_U) of less than 10% of the dispersion. This ensures uniform and constant reliability in data storage in the charge storage patterns (SN).

[0093] The charge storage patterns (SN) are covered with a passivation film (PL). The passivation film (PL) may have a single or multiple film structure of at least one of SiN, SiO, SiON, or metal oxide. The passivation film (PL) can reduce lateral / vertical charge loss by blocking defects, such as dangling bonds, that may form on the surface of the charge storage patterns (SN). The passivation film (PL) may be spaced apart from a blocking insulating film (BCL). Other configurations may be the same or similar as described with reference to FIGS. 5a through 5d and FIG. 6.

[0095] FIG. 8 is an enlarged view of the 'P1' portion of FIG. 4 according to embodiments of the present invention.

[0096] Referring to FIG. 8, in the three-dimensional semiconductor memory device according to the present example, the gate insulating film (GO) may be excluded without including the tunnel insulating film (TL) of FIG. 5a and 5b. In this case, the passivation film (PL) may take the place of the function of the tunnel insulating film (TL). The passivation film (PL) may be in contact with the vertical semiconductor pattern (VS) and simultaneously in contact with the charge storage patterns (SN). Other configurations may be the same or similar as described with reference to FIG. 5a, 5b and FIG. 6.

[0098] FIGS. 9a to 9e are cross-sectional views sequentially illustrating the process of manufacturing a three-dimensional semiconductor memory device having the cross-section of FIG. 4. FIG. 10 is a process flowchart illustrating the process of forming charge storage patterns according to embodiments of the present invention. FIGS. 11a to 11e are process cross-sectional views of the P1 portion of FIG. 9c. FIG. 11e corresponds to a drawing of the 'P1' portion of FIG. 9c in enlargement.

[0099] Referring to FIG. 9a, a peripheral circuit structure (PS) is manufactured. To this end, an isolation layer (105) is formed on a first substrate (103) to define active regions. Transistors (PTRs) may be formed in the active regions. A multilayer peripheral interlayer insulating layer (107) covering the transistors (PTRs) and peripheral contacts (33) and peripheral wiring (109) are formed within the peripheral interlayer insulating layer (107). Peripheral conductive pads (30b) of FIG. 3 are formed on the top of the peripheral circuit structure (PS). An etch stop layer (111) is formed sequentially on the front surface of the peripheral circuit structure (PS).

[0100] Next, a second substrate (201) is formed on the etch stop layer (111). The second substrate (201) may be formed by forming a semiconductor epitaxial film or by attaching a semiconductor single-crystal substrate to the etch stop layer (111). The second substrate (201) may also be referred to as a semiconductor layer. The second substrate (201) may be doped with, for example, an impurity of the first conductivity type. A substrate ground region (WR) of FIG. 3 may be formed on the second substrate (201). The substrate ground region (WR) is formed by doping with the impurity of the first conductivity type, and may have a higher concentration than the concentration of the impurity doped in the second substrate (201). The second substrate (201) may include a cell array region (CAR) and a connection region (CNR) as shown in FIG. 2.

[0101] A first buffer layer (16), a first sacrificial film (17), a second buffer layer (18), and a first source pattern (SC1) are stacked sequentially on the second substrate (201). A first electrode interlayer insulating film (12) and a second sacrificial film (14) are alternately and repeatedly stacked on the first source pattern (SC1) to form a first pre-stack structure (PST1). The first source pattern (SC1) may be a polysilicon film doped with impurities. The first and second buffer layers (16, 18) and the electrode interlayer insulating film (12) may preferably include a silicon oxide film. The first sacrificial film (17) may include a material having an etching selectivity with the first and second buffer layers (16, 18), the first electrode interlayer insulating film (12), the first source pattern (SC1), and the second sacrificial film (14) simultaneously. For example, the second sacrificial films (14) may be formed of silicon nitride films. The first sacrificial film (17) may be a silicon germanium film or a silicon oxynitride film. Alternatively, the first sacrificial film (17) may be a polysilicon film doped with impurities at a concentration different from the concentration of impurities doped in the first source pattern (SC1).

[0102] Referring to FIG. 3, the ends of the first electrode interlayer insulating films (12) and the second sacrificial films (14) in the connection region (CNR) can be formed into a step shape by repeating the trimming process and the anisotropic etching process. At this time, the first buffer layer (16), the first sacrificial film (17), the second buffer layer (18), and the first source pattern (SC1) may also be partially etched so that the upper surface of the second substrate (201) is exposed. A first flat insulating film (210) is formed and a Chemical Mechanical Polishing (CMP) process is performed to cover the ends of the first pre-stack structure (PST1).

[0103] In the cell array region (CAR), a portion of the first pre-stack structure (PST1), the first source pattern (SC1), the second buffer layer (18), the first sacrificial layer (17), the first buffer layer (16), and the second substrate (201) is etched to form a plurality of lower holes (BH). Each of the lower holes (BH) is filled with lower sacrificial embedding patterns (BGP). The sacrificial embedding pattern (BGP) may be a material having etch selectivity simultaneously with the first electrode interlayer insulating films (12), the second sacrificial films (14), the first source pattern (SC1), the second buffer layer (18), the first sacrificial layer (17), the first buffer layer (16), and the second substrate (201). For example, the lower sacrificial embedding pattern (BGP) may include SOH (Spin on Hardmask), ACL (Amorphous Carbon Layer), or SiGe.

[0104] A second pre-stack structure (PST2) is formed by alternately and repeatedly stacking second electrode interlayer insulating films (22, 24) and third sacrificial films (26) on the first pre-stack structure (PST1) and the first flat insulating film (210). The second electrode interlayer insulating films (22, 24) may contain the same material as the first electrode interlayer insulating films (12). The third sacrificial films (26) may contain the same material as the second sacrificial films (14).

[0105] Referring to FIG. 3, the ends of the second electrode interlayer insulating films (22, 24) and the third sacrificial films (26) in the connection region (CNR) can be formed into a stepped shape by repeating the trimming process and the anisotropic etching process. A second flat insulating film (220) is formed and a Chemical Mechanical Polishing (CMP) process is performed to cover the ends of the second pre-stack structure (PST2). Then, the second pre-stack structure (PST2) can be etched in the cell array region (CAR) and the dummy region (DR) to form upper holes (UH) that expose sacrificial embedding patterns (BGP), respectively. Then, the upper holes (UH) are filled with an upper sacrificial embedding pattern (UGP). The upper sacrificial embedding pattern (UGP) may include SOH (Spin on Hardmask), ACL (Amorphous Carbon Layer), or SiGe.

[0106] The upper holes (UH) and the lower holes (BH) that overlap each other can form vertical holes (VH) and dummy vertical holes (DVH). The dummy vertical holes (DVH) are placed between the vertical holes (VH) and can be arranged along a first direction (D1).

[0107] Referring to Fig. 9b, the upper sacrificial burial pattern (UGP) and lower sacrificial burial pattern (BGP) inside the vertical holes (VH) and dummy vertical holes (DVH) are removed to expose the inner surface of the vertical holes (VH) and dummy vertical holes (DVH).

[0108] Referring to FIG. 9c, a gate insulating film (GO) is formed within the vertical holes (VH) and dummy vertical holes (DVH). To do this, a blocking insulating film (BCL) is first conformally formed on the first pre-stack structure (PST1) and the second pre-stack structure (PST2), in which the vertical holes (VH) and dummy vertical holes (DVH) are formed as in FIG. 11a. The blocking insulating film (BCL) can be formed, for example, by Atomic Layer Deposition (ALD) or Chemical Vapor Deposition (CVD).

[0109] Referring to FIGS. 10 and FIGS. 11a, an amorphous polysilicon film (APL) is formed on a blocking insulating film (BCL) (S10). The amorphous polysilicon film (APL) can be formed by depositing a silicon film using an Atomic Layer Deposition (ALD) or Chemical Vapor Deposition (CVD) method. The amorphous polysilicon film (APL) can be formed at a temperature of 300 to 800°C. When depositing the amorphous polysilicon film (APL), monosilane (SiH4), disilane (Si2H6), trisilane (Si3H8), or tetrasilane (Si4H4) can be used as the source gas. 10 ), neopentasilan (Si5H 12 At least one of diisopropylaminosilane (H3Si[N{(CH)(CH3)2}]), bisdiethylaminosilane (H2Si((N(C2H5)2)2), and tetrakisdimethylaminosilane (Si[N(CH3)2]4) can be supplied. Impurities may be doped in situ when depositing the amorphous polysilicon film (APL). The impurities may be phosphorus, arsenic, or boron.

[0110] Referring to FIG. 10 and FIG. 11b, an annealing process (ANG) is performed to crystallize the amorphous polysilicon film (APL) (S20) to form a crystallized silicon film (SNL). The annealing process (ANG) may be performed at a temperature of 500 to 1100°C. The crystallized silicon film (SNL) may be composed of a plurality of second silicon crystal grains (SG2). Second boundaries (SG2_B) or second grain boundaries may exist between the second silicon crystal grains (SG2). As the process time of the annealing process (ANG) increases and the temperature of the annealing process (ANG) increases, the size of the second silicon crystal grains (SG2) may increase. In the step (S10) of forming an amorphous polysilicon film (APL), the thicker the amorphous polysilicon film (APL), the larger the size of the second silicon crystal grains (SG2).

[0111] Referring to FIGS. 10, 11c, and 11d, a crystallized silicon film (SNL) is etched to form silicon crystal patterns (SN) (S30). At this time, an etchant (ETG) may be supplied through the vertical holes (VH) and dummy vertical holes (DVH). The etching process may be performed dry or wet and may be performed isotropically. The etchant may be, for example, at least one of Cl2 and HCl.

[0112] The above etching process may preferably be a Gas phase etch (GPE). In the above etching process, the etchants are more likely to penetrate toward the second boundaries (SG2_B) between the second silicon crystal grains (SG2) than toward the upper surfaces of the second silicon crystal grains (SG2). This may be because the second boundaries (SG2_B) between the second silicon crystal grains (SG2) are close to an amorphous silicon state, and thus the bonding force between silicon atoms at the second boundaries (SG2_B) between the second silicon crystal grains (SG2) is relatively weaker than inside the second silicon crystal grains (SG2). Thus, the second boundaries (SG2_B) between the second silicon crystal grains (SG2) are etched first, and grooves (SG2_H) can be formed at the second boundaries (SG2_B) between the second silicon crystal grains (SG2) as shown in FIG. 11c. By continuing the above etching process, silicon crystal patterns (SN) spaced apart from each other can be formed as shown in FIG. 11d. The silicon crystal patterns (SN) can be named charge storage patterns (SN). Gas phase etch (GPE) using the above etchant has an excellent etching selectivity for amorphous silicon relative to the blocking insulating film (BCL), so the second boundaries (SG2_B) between the second silicon crystal grains (SG2) can be effectively etched without damaging the blocking insulating film (BCL). As a result, the silicon crystal patterns (SN) can be formed effectively separated from each other.

[0113] In addition, silicon crystal patterns (SN) can be formed to have a uniform size, thickness, and spacing by adjusting etching conditions such as process temperature and pressure of the etching process. For example, as the process temperature and pressure of the etching process increase, the size of the silicon crystal patterns (SN) may become smaller and the spacing may become larger.

[0114] In the present invention, charge storage patterns can be formed by forming an amorphous polysilicon film, crystallizing it through an annealing process, and then etching the boundaries between silicon crystal grains through an etching process. As a result, charge storage patterns can be formed to have uniform size, thickness, and spacing. This prevents or minimizes data storage / erasure errors depending on location in a 3D semiconductor memory device and improves the reliability of the 3D semiconductor memory device.

[0115] Depending on the degree of etching in the above etching process, as described in FIGS. 7a and 7b, the second silicon crystal grains (SG2) may not be separated from each other, so that the second parts (SN_P2) of the charge storage patterns (SN) may be formed to be attached to each other.

[0116] Referring to FIGS. 10 and FIGS. 11d, a surface treatment of silicon crystal patterns (SN) is performed (S40). The surface treatment (S40) may be an oxidation process or a nitriding process using plasma (PLG) or a solution. The plasma (PLG) may be oxygen plasma or nitrogen plasma. The solution may be, for example, ozone water. By the surface treatment (S40), a capping film (CPL) may be formed on the surface of the silicon crystal patterns (SN) as in FIG. 5c or FIG. 5d. The surface treatment (S40) may be omitted.

[0117] Referring to FIGS. 10 and FIGS. 11e, a passivation film (PL) is formed (S50). The passivation film (PL) can be formed by ALD or CVD. The passivation film (PL) may have a single film or multiple film structure among at least one of SiN, SiO, SiON, or metal oxide.

[0118] Referring to FIG. 9c and FIG. 11e, a tunnel insulating film (TL) is formed on the passivation film (PL). The tunnel insulating film (TL) can be formed by an ALD or CVD process. This allows for the formation of a gate insulating film (GO). A vertical semiconductor pattern (VS) and a central dummy vertical semiconductor pattern (CDVS) ​​are formed on the gate insulating film (GO). Forming the vertical semiconductor pattern (VS) and the central dummy vertical semiconductor pattern (CDVS) ​​can be performed by an ALD or CVD process. The vertical semiconductor pattern (VS) and the central dummy vertical semiconductor pattern (CDVS) ​​can be formed from an amorphous polysilicon film that is doped with impurities or is not doped. An annealing process may be added to crystallize the amorphous polysilicon film of the vertical semiconductor pattern (VS) and the central dummy vertical semiconductor pattern (CDVS). Alternatively, even if an additional annealing process is not performed, the amorphous polysilicon film of the vertical semiconductor pattern (VS) and the central dummy vertical semiconductor pattern (CDVS) ​​can be crystallized by the heat applied by subsequent processes. Thus, as described in FIG. 5b, the vertical semiconductor pattern (VS) and the central dummy vertical semiconductor pattern (CDVS) ​​can have first silicon crystal grains (SG1). The amorphous polysilicon film for the vertical semiconductor pattern (VS) and the central dummy vertical semiconductor pattern (CDVS) ​​can be formed thicker than the amorphous polysilicon film (APL) for forming the charge storage pattern (SN) in FIG. 11a. Thus, the width (WD2) of the first silicon crystal grains (SG1) can be larger than the width (WD1) of the charge storage pattern (SN) as in FIG. 5b.

[0119] The interior of the vertical holes (VH) is filled with a buried insulating pattern (29). The upper part of the vertical semiconductor pattern (VS) can be partially removed and filled with an impurity-doped silicon film to form bitline pads (BPD).

[0120] Referring to FIGS. 9c and 9d, a first upper interlayer insulating film (205) is laminated on the second pre-stack structure (PST2). The first upper interlayer insulating film (205), the second pre-stack structure (PST2), the first pre-stack structure (PST1), the first source pattern (SC1), and the second buffer layer (18) are sequentially etched to form first and second grooves (G1, G2) that expose the first sacrificial film (17). Through the first and second grooves (G1, G2), the second buffer layer (18), the first sacrificial film (17), and the first buffer layer (16) can be removed to form a first empty space (ER1).

[0121] When forming the first empty space (ER1), a portion of the gate insulating film (GO) may be removed so that the sidewalls of the vertical semiconductor pattern (VS), the central dummy vertical semiconductor pattern (CDVS), and the edge dummy vertical pattern (EDVS) of FIG. 3 may be exposed. When forming the first empty space (ER1), the vertical semiconductor pattern (VS), the vertical conductive pattern (CSPG), and the edge dummy vertical pattern (EDVS) of FIG. 3 may serve to support the preliminary cell array structure (PCS) so that it does not collapse.

[0122] Referring to FIGS. 9d and 9e, a second source film can be conformally stacked to fill the first empty space (ER1) through the first and second grooves (G1, G2), and an anisotropic etching process can be performed to remove the second source film within the first and second grooves (G1, G2) and leave the second source film in the first empty space (ER1) to form a second source pattern (SC2). Thus, the first source pattern (SC1) and the second source pattern (SC2) can form a source structure (SCL).

[0123] Referring to FIG. 9e and FIG. 4, the second sacrificial films (14) and the third sacrificial films (26) can be removed through the first and second grooves (G1, G2) to form second empty spaces between the electrode interlayer insulating films (12, 22, 24). The second empty spaces are filled through the first and second grooves (G1, G2) by conformally stacking a conductive film. Then, an anisotropic etching process can be performed to remove the conductive film within the first and second grooves (G1, G2) to form electrode layers (EL1, EL2) within the second empty spaces. This allows for the formation of a first sub-stack structure (ST1) and a second sub-stack structure (ST2). Before stacking the conductive film for the electrode layers (EL1, EL2), the high dielectric film (HL) of FIG. 5a can be formed conformally. The insulating film is stacked conformally and anisotropically etched to form first and second isolated insulating lines (SL1, SL2) that fill the first and second grooves (G1, G2). Subsequently, a conventional process can be carried out to manufacture a three-dimensional semiconductor memory device as described with reference to FIGS. 2 to 4.

[0125] FIG. 12 is a cross-sectional view of a semiconductor device according to an exemplary embodiment of the present invention.

[0126] Referring to FIG. 12, the memory device (1400) may have a C2C (chip-to-chip) structure. A C2C structure may mean fabricating an upper chip containing a cell array structure (CELL) on a first wafer, fabricating a lower chip containing a peripheral circuit structure (PERI) on a second wafer different from the first wafer, and then connecting the upper chip and the lower chip to each other by a bonding method. For example, the bonding method may mean a method of electrically connecting a bonding metal formed on the uppermost metal layer of the upper chip and a bonding metal formed on the uppermost metal layer of the lower chip. For instance, if the bonding metal is formed of copper (Cu), the bonding method may be a Cu-to-Cu bonding method, and the bonding metal may also be formed of aluminum (Al) or tungsten (W).

[0127] Each of the peripheral circuit structure (PERI) and cell array structure (CELL) of the memory device (1400) may include an external pad bonding region (PA), a wordline bonding region (WLBA), and a bitline bonding region (BLBA).

[0128] The peripheral circuit structure (PERI) may include a first substrate (1210), an interlayer insulating layer (1215), a plurality of circuit elements (1220a, 1220b, 1220c) formed on the first substrate (1210), a first metal layer (1230a, 1230b, 1230c) connected to each of the plurality of circuit elements (1220a, 1220b, 1220c), and a second metal layer (1240a, 1240b, 1240c) formed on the first metal layer (1230a, 1230b, 1230c). In one embodiment, the first metal layer (1230a, 1230b, 1230c) may be formed of tungsten, which has relatively high electrical resistivity, and the second metal layer (1240a, 1240b, 1240c) may be formed of copper, which has relatively low electrical resistivity.

[0129] In this specification, only the first metal layer (1230a, 1230b, 1230c) and the second metal layer (1240a, 1240b, 1240c) are illustrated and described, but are not limited thereto, and at least one additional metal layer may be formed on the second metal layer (1240a, 1240b, 1240c). At least some of the one or more metal layers formed on the upper part of the second metal layer (1240a, 1240b, 1240c) may be formed of aluminum or the like, having an electrical resistivity lower than that of copper forming the second metal layer (1240a, 1240b, 1240c).

[0130] The interlayer insulating layer (1215) is disposed on a first substrate (1210) to cover a plurality of circuit elements (1220a, 1220b, 1220c), a first metal layer (1230a, 1230b, 1230c), and a second metal layer (1240a, 1240b, 1240c), and may include an insulating material such as silicon oxide, silicon nitride, etc.

[0131] A lower bonding metal (1271b, 1272b) may be formed on the second metal layer (1240b) of the wordline bonding region (WLBA). In the wordline bonding region (WLBA), the lower bonding metal (1271b, 1272b) of the peripheral circuit structure (PERI) may be electrically connected to the upper bonding metal (1371b, 1372b) of the cell array structure (CELL) by a bonding method, and the lower bonding metal (1271b, 1272b) and the upper bonding metal (1371b, 1372b) may be formed of aluminum, copper, or tungsten, etc.

[0132] The cell array structure (CELL) may correspond to the cell array structure (CS) described with reference to FIGS. 2 through 8. The cell array structure (CELL) may provide at least one memory block. The cell array structure (CELL) may include a second substrate (1310) and a common source line (1320). On the second substrate (1310), a plurality of word lines (1331-1338; 1330) may be stacked along a direction perpendicular to the upper surface of the second substrate (1310) (third direction (D3)). String selection lines and ground selection lines may be disposed on the upper and lower portions of the word lines (1330), respectively, and a plurality of word lines (1330) may be disposed between the string selection lines and the ground selection lines.

[0133] In the bitline bonding region (BLBA), the channel structure (1CH) may extend in a direction perpendicular to the upper surface of the second substrate (1310) (third direction (D3)) and penetrate word lines (1330), string select lines, and ground select lines. The channel structure (CH) may include a data storage layer, a channel layer, and a buried insulating layer, and the channel layer may be electrically connected to a first metal layer (1350c) and a second metal layer (1360c). For example, the first metal layer (1350c) may be a bitline contact, and the second metal layer (1360c) may be a bitline. In one embodiment, the bitline (1360c) may extend along a second direction (D2) parallel to the upper surface of the second substrate (1310).

[0134] In one embodiment illustrated in FIG. 12, the area where the channel structure (CH) and bit line (1360c) are placed may be defined as a bit line bonding area (BLBA). The bit line (1360c) may be electrically connected to circuit elements (1220c) that provide a page buffer (1393) in a peripheral circuit structure (PERI) in the bit line bonding area (BLBA). For example, the bit line (1360c) may be connected to an upper bonding metal (1371c, 1372c) in the peripheral circuit structure (PERI), and the upper bonding metal (1371c, 1372c) may be connected to a lower bonding metal (1271c, 1272c) that is connected to the circuit elements (1220c) of the page buffer (1393).

[0135] In the wordline bonding area (WLBA), the wordlines (1330) may extend along a first direction (D1) parallel to the upper surface of the second substrate (1310) while perpendicular to the second direction (D2), and may be connected to a plurality of cell contact plugs (1341-1347; 1340). The shape of the cell contact plugs (1341-1347; 1340) may be the same as the cell contact plug (CC) of FIG. 3.

[0136] Word lines (1330) and cell contact plugs (1340) may be connected to each other at pads provided by extending at least some of the word lines (1330) to different lengths along the first direction (D1). A first metal layer (1350b) and a second metal layer (1360b) may be connected in sequence to the upper portion of the cell contact plugs (1340) connected to the word lines (1330). The cell contact plugs (1340) may be connected to the peripheral circuit structure (PERI) through the upper bonding metal (1371b, 1372b) of the cell region (1CELL) and the lower bonding metal (1271b, 1272b) of the peripheral circuit structure (PERI) in the word line bonding region (WLBA).

[0137] Cell contact plugs (1340) may be electrically connected to circuit elements (1220b) forming a row decoder (1394) in a peripheral circuit structure (PERI). In one embodiment, the operating voltage of the circuit elements (1220b) forming the row decoder (1394) may be different from the operating voltage of the circuit elements (1220c) forming the page buffer (1393). For example, the operating voltage of the circuit elements (1220c) forming the page buffer (1393) may be greater than the operating voltage of the circuit elements (1220b) forming the row decoder (1394).

[0138] A common source line contact plug (1380) may be disposed in an external pad bonding area (PA). The common source line contact plug (1380) is formed of a conductive material such as a metal, a metal compound, or polysilicon and may be electrically connected to a common source line (1320). A first metal layer (1350a) and a second metal layer (1360a) may be sequentially laminated on top of the common source line contact plug (1380). For example, the area where the common source line contact plug (1380), the first metal layer (1350a), and the second metal layer (1360a) are disposed may be defined as an external pad bonding area (PA).

[0139] Meanwhile, input / output pads (1205, 1305) may be disposed in the external pad bonding area (1PA). Referring to FIG. 12, a lower insulating film (1201) covering the lower surface of the first substrate (1210) may be formed on the lower surface of the first substrate (1210), and a first input / output pad (1205) may be formed on the lower insulating film (1201). The first input / output pad (1205) is connected to at least one of a plurality of circuit elements (1220a, 1220b, 1220c) disposed in a peripheral circuit structure (PERI) through a first input / output contact plug (1203), and may be separated from the first substrate (1210) by the lower insulating film (1201). Additionally, a side insulating film is disposed between the first input / output contact plug (1203) and the first substrate (1210) to electrically separate the first input / output contact plug (1203) and the first substrate (1210).

[0140] Referring to FIG. 12, an upper insulating film (1301) covering the upper surface of the second substrate (1310) may be formed on the upper surface of the second substrate (1310), and a second input / output pad (1305) may be disposed on the upper insulating film (1301). The second input / output pad (1305) may be connected to at least one of a plurality of circuit elements (1220a, 1220b, 1220c) disposed in a peripheral circuit structure (PERI) through a second input / output contact plug (1303). In one embodiment, the second input / output pad (1305) may be electrically connected to a circuit element (1220a).

[0141] According to the embodiments, the second substrate (1310) and common source line (1320), etc., may not be placed in the area where the second input / output contact plug (1303) is placed. Additionally, the second input / output pad (1305) may not overlap with the word lines (1330) in the third direction (D3). Referring to FIG. 12, the second input / output contact plug (1303) is separated from the second substrate (1310) in a direction parallel to the upper surface of the second substrate (1310) and may be connected to the second input / output pad (1305) by penetrating the interlayer insulating layer (1315) of the cell array structure (CELL).

[0142] According to embodiments, the first input / output pad (1205) and the second input / output pad (1305) may be formed optionally. For example, the memory device (1400) may include only the first input / output pad (1205) disposed on the upper part of the first substrate (1210), or only the second input / output pad (1305) disposed on the upper part of the second substrate (1310). Alternatively, the memory device (1400) may include both the first input / output pad (1205) and the second input / output pad (1305).

[0143] In each of the external pad bonding region (PA) and bitline bonding region (BLBA) included in the cell array structure (CELL) and peripheral circuit region (1PERI), the metal pattern of the top metal layer may exist as a dummy pattern, or the top metal layer may be empty.

[0144] The memory device (1400) may form a lower metal pattern (1273a) of the same shape as the upper metal pattern (1372a) of the cell array structure (CELL) on the upper metal layer of the peripheral circuit structure (PERI) in the external pad bonding area (PA), corresponding to the upper metal pattern (1372a) formed on the upper metal layer of the cell array structure (CELL). The lower metal pattern (1273a) formed on the upper metal layer of the peripheral circuit structure (PERI) may not be connected to a separate contact in the peripheral circuit structure (PERI). Similarly, the memory device may form an upper metal pattern (1372a) of the same shape as the lower metal pattern (1273a) of the peripheral circuit structure (PERI) on the upper metal layer of the cell array structure (CELL) in the external pad bonding area (PA), corresponding to the lower metal pattern (1273a) formed on the upper metal layer of the peripheral circuit structure (PERI).

[0145] A lower bonding metal (1271b, 1272b) may be formed on the second metal layer (1240b) of the wordline bonding region (WLBA). In the wordline bonding region (WLBA), the lower bonding metal (1271b, 1272b) of the peripheral circuit structure (PERI) may be electrically connected to the upper bonding metal (1371b, 1372b) of the cell array structure (CELL) by a bonding method.

[0146] Additionally, in the bitline bonding area (BLBA), an upper metal pattern (1392) of the same shape as the lower metal pattern (1252) of the peripheral circuit structure (PERI) can be formed on the upper metal layer of the cell array structure (CELL) in correspondence with the lower metal pattern (1252) formed on the upper metal layer of the peripheral circuit structure (PERI). A contact may not be formed on the upper metal pattern (1392) formed on the upper metal layer of the cell array structure (CELL).

[0148] Although embodiments of the present invention have been described above with reference to the attached drawings, those skilled in the art will understand that the present invention may be implemented in other specific forms without changing its technical concept or essential features. Therefore, the embodiments described above should be understood as illustrative in all respects and not restrictive. The embodiments of FIGS. 1a through 12 may be combined with each other.

Claims

Claim 1 A three-dimensional semiconductor memory device comprising: a stack structure including electrode layers and inter-electrode insulating films alternately stacked on a substrate; vertical semiconductor patterns adjacent to the substrate penetrating the stack structure; and a gate insulating film interposed between the vertical semiconductor patterns and the stack structure, wherein the gate insulating film comprises: a blocking insulating film adjacent to the stack structure; and charge storage patterns spaced apart from the stack structure with the blocking insulating film in between and arranged along the surface of the blocking insulating film, wherein each of the charge storage patterns is a silicon crystal pattern that is doped with or undoped with impurities, and the charge storage patterns have a wider width the closer they are to the blocking insulating film. Claim 2 In claim 1, the charge storage patterns are a three-dimensional semiconductor memory device having a polygonal shape in a planar or cross-sectional manner. Claim 3 A three-dimensional semiconductor memory device according to claim 1, wherein the charge storage patterns each have a side angle inclined with respect to the surface of the blocking insulating film. Claim 4 A three-dimensional semiconductor memory device according to claim 1, wherein the charge storage patterns each have a first portion and a second portion, the second portions are in contact with the blocking insulating film, the second portions are connected to each other, and the first portions are spaced apart from each other and spaced apart from the blocking insulating film. Claim 5 A three-dimensional semiconductor memory device according to claim 1, wherein the electrode layers each have a first vertical length, the charge storage patterns each have a second vertical length, and the second vertical length is smaller than the first vertical length. Claim 6 delete Claim 7 A three-dimensional semiconductor memory device according to claim 1, wherein the vertical semiconductor patterns each have silicon crystal grains, and the average size of the silicon crystal grains is larger than the average size of the charge storage patterns. Claim 8 A three-dimensional semiconductor memory device according to claim 1, wherein the gate insulating film further comprises: a passivation film interposed between the charge storage patterns and the vertical semiconductor patterns, covering the charge storage patterns. Claim 9 In claim 8, the passivation film is a three-dimensional semiconductor memory device having a single film or multiple film structure of at least one of SiN, SiO, SiON, or metal oxide. Claim 10 In claim 8, the gate insulating film further comprises: a tunnel insulating film interposed between the passivation film and the vertical semiconductor patterns, in a three-dimensional semiconductor memory device. Claim 11 A three-dimensional semiconductor memory device according to claim 1, further comprising a source structure interposed between the substrate and the stack structure, wherein the vertical semiconductor patterns extend into the substrate by penetrating the source structure, the gate insulating film is interposed between the vertical semiconductor patterns and the substrate below the source structure, the source structure contacts the vertical semiconductor patterns by penetrating the gate insulating film, and the gate insulating film further comprises dummy charge storage patterns disposed below the source structure, wherein the dummy charge storage patterns have a wider width the closer they are to the blocking insulating film. Claim 12 A three-dimensional semiconductor memory device according to claim 1, wherein the gate insulating film further comprises: a capping film covering the charge storage patterns; a passivation film covering the capping film; and a tunnel insulating film covering the passivation film. Claim 13 The apparatus comprises a peripheral circuit structure and a cell array structure disposed thereon, wherein the cell array structure comprises: a first substrate including a cell array region and a connection region arranged side by side in a first direction; a source structure on the first substrate; a stack structure including electrode layers and inter-electrode insulating films alternately stacked on the first substrate; a flat insulating film covering the end of the stack structure on the connection region; a plurality of vertical semiconductor patterns adjacent to the first substrate by penetrating the stack structure and the source structure in the cell array region; bitline pads disposed on each of the vertical semiconductor patterns; and a gate insulating film interposed between the vertical semiconductor patterns and the stack structure, wherein the gate insulating film comprises: a blocking insulating film adjacent to the stack structure; A three-dimensional semiconductor memory device comprising charge storage patterns spaced apart from the stack structure with the blocking insulating film in between and arranged along the surface of the blocking insulating film, wherein each of the vertical semiconductor patterns has silicon crystal grains, and the average size of the silicon crystal grains is greater than the average size of the charge storage patterns. Claim 14 In claim 13, the charge storage patterns have a wider width the closer they are to the blocking insulating film in a three-dimensional semiconductor memory device. Claim 15 A three-dimensional semiconductor memory device according to claim 13, wherein the average size of the charge storage patterns is 3 nm to 10 nm. Claim 16 A three-dimensional semiconductor memory device according to claim 13, wherein the gate insulating film further comprises: a passivation film covering the charge storage patterns and interposed between the charge storage patterns and the vertical semiconductor patterns. Claim 17 In claim 16, the passivation film is a three-dimensional semiconductor memory device having a single film or multiple film structure of at least one of SiN, SiO, SiON, or metal oxide. Claim 18 In claim 16, the gate insulating film further comprises: a tunnel insulating film interposed between the passivation film and the vertical semiconductor patterns, in a three-dimensional semiconductor memory device. Claim 19 A three-dimensional semiconductor memory device according to claim 13, wherein the gate insulating film further comprises: a capping film covering the charge storage patterns; a passivation film covering the capping film; and a tunnel insulating film covering the passivation film. Claim 20 An electronic system comprising a peripheral circuit structure and a cell array structure disposed thereon, wherein the cell array structure comprises: a stack structure including electrode layers and inter-electrode insulating films alternately stacked on a substrate; vertical semiconductor patterns adjacent to the substrate through the stack structure; and a gate insulating film interposed between the vertical semiconductor patterns and the stack structure, wherein the gate insulating film comprises: a blocking insulating film adjacent to the stack structure; and charge storage patterns spaced apart from the stack structure with the blocking insulating film in between and arranged along the surface of the blocking insulating film, wherein the charge storage patterns have a wider width closer to the blocking insulating film and include an input / output pad electrically connected to the peripheral circuit structure; and a controller electrically connected to the semiconductor device through the input / output pad and controlling the semiconductor device.

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