Semiconductor devices

Abstract

A semiconductor device according to an embodiment of the present invention comprises a substrate including an active region extending in a first direction, a gate structure extending in a second direction intersecting the active region, a source / drain region disposed on the active region at least on one side of the gate structure, a contact plug disposed on the source / drain region at at least on one side of the gate structure, and a contact insulating layer on the sidewalls of the contact plug, wherein the bottom of the contact plug is located at a level lower than the bottom of the source / drain region.

Description

Technology Field

[0001] The present invention relates to a semiconductor device. Background Technology

[0003] As the demand for high performance, high speed, and / or multifunctionality of semiconductor devices increases, the integration density of semiconductor devices is increasing. In manufacturing semiconductor devices with fine patterns to meet the trend of high integration of semiconductor devices, it is required to implement patterns with fine widths or fine spacing. In addition, efforts are being made to develop semiconductor devices including FinFETs with three-dimensional channel structures to overcome the limitations of operating characteristics resulting from the size reduction of planar MOSFETs (metal oxide semiconductor FETs). The problem to be solved

[0005] One of the technical problems that the technical concept of the present invention aims to solve is to provide a semiconductor device with improved electrical characteristics. means of solving the problem

[0007] A semiconductor device according to exemplary embodiments comprises a substrate including an active region extending in a first direction, a gate structure extending in a second direction intersecting the active region, a source / drain region disposed on the active region at least on one side of the gate structure, a contact plug disposed on the source / drain region at at least on one side of the gate structure, and a contact insulating layer on the sidewalls of the contact plug, wherein the bottom of the contact plug may be located at a level lower than the bottom of the source / drain region.

[0008] A semiconductor device according to exemplary embodiments comprises: a substrate having first and second regions and active regions extending in a first direction; gate structures each disposed on the first and second regions and extending in a second direction intersecting the active regions; source / drain regions disposed on the active regions at at least one side of the gate structures and comprising a metal-semiconductor layer located at the top; contact plugs disposed such that the source / drain regions at at least one side of the gate structures are in contact with a portion of the outer surfaces and have a bottom located at a level lower than the bottom of the source / drain regions; and contact insulating layers on the sidewalls of the contact plugs, wherein each of the gate structures comprises a gate insulating layer and a gate electrode layer disposed sequentially on the substrate, and gate spacer layers disposed on the sidewalls of the gate electrode layer along the first direction, wherein in the first region, a first distance between the gate electrode layer and the adjacent contact plug is shorter than a second distance between the gate electrode layer and the adjacent contact plug in the second region. It is possible.

[0009] A semiconductor device according to exemplary embodiments may include a substrate having active regions extending in a first direction, gate structures extending in a second direction intersecting the active regions and including gate electrode layers, source / drain regions disposed on the active regions at least on one side of the gate structures, contact plugs disposed on the source / drain regions at at least on one side of the gate structures, contact insulating layers in contact with the gate structures and surrounding the entire sidewalls of the contact plugs, and a sidewall insulating layer positioned to be in contact with a portion of the outer surface of the source / drain regions and in contact with the contact plugs. Effects of the invention

[0011] After forming source / drain regions, a semiconductor device with improved electrical characteristics can be provided by sequentially forming a contact insulating layer and a contact plug on the source / drain regions.

[0012] The various and beneficial advantages and effects of the present invention are not limited to those described above and will be more easily understood in the process of explaining specific embodiments of the present invention. Brief explanation of the drawing

[0014] FIG. 1 is a plan view illustrating a semiconductor device according to exemplary embodiments. FIGS. 2a to 2c are cross-sectional views illustrating semiconductor devices according to exemplary embodiments. FIG. 3 is a plan view illustrating a semiconductor device according to exemplary embodiments. FIGS. 4a and FIGS. 4b are cross-sectional views illustrating a semiconductor device according to exemplary embodiments. FIG. 5 is a cross-sectional view illustrating a semiconductor device according to exemplary embodiments. FIGS. 6a and FIGS. 6b are cross-sectional views illustrating a semiconductor device according to exemplary embodiments. FIG. 7 is a plan view illustrating a semiconductor device according to exemplary embodiments. FIG. 8 is a cross-sectional view illustrating a semiconductor device according to exemplary embodiments. FIGS. 9a to 9c are cross-sectional views of a semiconductor device according to exemplary embodiments. FIGS. 10a to 10k are drawings illustrated in the order of process to explain a method for manufacturing a semiconductor device according to exemplary embodiments. Specific details for implementing the invention

[0015] Hereinafter, preferred embodiments of the present invention will be described as follows with reference to the attached drawings.

[0017] FIG. 1 is a plan view illustrating a semiconductor device according to exemplary embodiments.

[0018] FIGS. 2a through 2c are cross-sectional views illustrating semiconductor devices according to exemplary embodiments. FIGS. 2a through 2c illustrate cross-sections of the semiconductor device of FIG. 1 taken along cutting lines I-I', II-II', and III-III', respectively. For convenience of explanation, FIGS. 1 through 2c only show the main components of the semiconductor device.

[0019] Referring to FIGS. 1 to 2c, a semiconductor device (100) may include a substrate (101), active regions (105), a device isolation layer (110), source / drain regions (150), gate structures (160), contact insulating layers (170), contact plugs (180), and an interlayer insulating layer (190). The semiconductor device (100) may include FinFET devices in which the active regions (105) are transistors having a fin structure. The FinFET devices may include transistors arranged around the intersecting active regions (105) and gate structures (160).

[0021] The substrate (101) may have an upper surface extending in the x and y directions. The substrate (101) may include a semiconductor material, such as a group IV semiconductor, a group III-V compound semiconductor, or a group II-VI compound semiconductor. For example, the group IV semiconductor may include silicon, germanium, or silicon-germanium. The substrate (101) may be provided as a bulk wafer, an epitaxial layer, an epitaxial layer, a Silicon On Insulator (SOI) layer, or a Semiconductor On Insulator (SeOI) layer, etc.

[0023] The device isolation layer (110) can define an active region (105) on the substrate (101). The device isolation layer (110) can be formed, for example, by a shallow trench isolation (STI) process. According to embodiments, the device isolation layer (110) may include a region that extends deeper into the lower part of the substrate (101). The device isolation layer (110) may have a curved upper surface having a higher level as it is adjacent to the active regions (105), but the shape of the upper surface of the device isolation layer (110) is not limited thereto. The device isolation layer (110) may be made of an insulating material. The device isolation layer (110) may be, for example, an oxide, a nitride, or a combination thereof.

[0025] Active regions (105) are defined by the device isolation layer (110) within the substrate (101) and may be arranged to extend in a first direction, e.g., in the x-direction. The active regions (105) may have a structure protruding from the substrate (101). The top of the active regions (105) may be arranged to protrude to a predetermined height from the upper surface of the device isolation layer (110). The active regions (105) may be formed as part of the substrate (101) or may include an epitaxial layer grown from the substrate (101). Depending on the manner of description, the substrate (101) may be described as including the active regions (105) or as having the active regions (105) disposed on the substrate (101). However, on both sides of the gate structures (160), the active regions (105) on the substrate (101) may be partially recessed, and source / drain regions (150) may be disposed on the recessed active regions (105). According to embodiments, the active regions (105) may have doped regions containing impurities. For example, the active regions (105) may contain impurities diffused from the source / drain regions (150) in the region in contact with the source / drain regions (150). Also, in exemplary embodiments, the active regions (105) may have a form including first and second semiconductor layers alternately stacked in upper regions located parallel to the source / drain regions (150) along the x direction. Also, in exemplary embodiments, the active regions (105) may have a structure having a flat upper surface rather than a fin structure.

[0027] Source / drain regions (150) may be disposed on recessed regions where the active region (105) is recessed, on both sides of the gate structures (160). The recessed region may have a shape that extends along the x-direction between the gate structures (160). The source / drain regions (150) may be provided as source or drain regions of transistors. The source / drain regions (150) may include metal-semiconductor layers (155) located on top.

[0028] As illustrated in FIG. 2a, the upper surface of the source / drain regions (150) may be substantially flat in a cross-section along the x-direction and may be substantially co-plane with the upper surface of the substrate (101). Additionally, the upper surface of the source / drain regions (150) may be located at the same or similar height level as the lower surface of the gate structures (160) in a cross-section along the x-direction. However, the relative height between the source / drain regions (150) and the gate structures (160) may vary depending on the embodiments. For example, if the metal-semiconductor layers (155) of the source / drain regions (150) are formed to protrude onto the substrate (101), the source / drain regions (150) may have an elevated source / drain shape in which the upper surface is located higher than the lower surface of the gate structures (160). Additionally, source / drain regions (150) may be positioned below the outer surfaces of the gate spacer layers (164) so ​​as not to overlap with the gate structures (160) between adjacent gate structures (160), but are not limited thereto. For example, the source / drain regions (150) may have a shape that extends along the x direction to the bottom of the gate structures (160).

[0029] Additionally, the source / drain regions (150) may have a curved shape, such as a circular part, an elliptical part, or a similar shape, at the bottom of the flat upper surface. However, such a shape of the bottom may be varied in the embodiments depending on the distance between adjacent gate structures (160), the height of the active regions (105), etc. The upper surface of the source / drain regions (150) may be entirely covered with contact insulating layers (170) and contact plugs (180). Accordingly, at the upper surface of the source / drain regions (150), the width along the x-direction of one source / drain region (150) may be substantially equal to the sum of the width of the upper contact plug (180) and the widths of the two contact insulating layers (170) on both sides of the contact plug (180).

[0030] As illustrated in FIG. 2b, the source / drain regions (150) may have a cross-section along the y-direction that is pentagonal or similar in shape. However, in the embodiments, the source / drain regions (150) may have various shapes, for example, any one of polygonal, circular, elliptical, and rectangular shapes. As illustrated in FIG. 2b, the source / drain regions (150) may have inclined outer surfaces. Specifically, the outer surfaces of the source / drain regions (150) may have first surfaces that extend upward with an incline such that the width along the y-direction increases from the active regions (105), and second surfaces that extend upward with an incline such that the width along the y-direction decreases from the first surfaces and are connected to each other. The second surfaces may be referred to as upper surfaces. Among the first surfaces, the outer first surfaces may be in contact with sidewall insulating layers (170R), and the second surfaces may be in contact with contact plugs (180). Additionally, the sidewall insulating layers (170R) may not be disposed on the inner first surfaces located between the active regions (105) among the first surfaces.

[0031] As illustrated in FIG. 2b, the source / drain regions (150) may have a form in which they are connected to each other between adjacent active regions (105) along the y direction, but are not limited thereto. According to embodiments, the source / drain regions (150) may have a form in which they are connected to regions other than the metal-semiconductor layers (155) between adjacent active regions (105) along the y direction, rather than being connected by metal-semiconductor layers (155). Below the region in which the source / drain regions (150) are connected to each other between adjacent active regions (105), there may be an air-gap region (AG) between the device isolation layer (110), but is not limited thereto. For example, according to embodiments, some air-gap region (AG) may also exist below the first sides on the outer side where the sidewall insulating layers (170R) are disposed.

[0032] Metal-semiconductor layers (155) may be disposed on top of source / drain regions (150) to form the upper surface of the source / drain regions (150). Accordingly, the metal-semiconductor layers (155) may make direct contact with the contact plugs (180) through the upper surface. The metal-semiconductor layers (155) can reduce the contact resistance between the source / drain regions (150) and the contact plugs (180). In exemplary embodiments, the upper surface of the metal-semiconductor layers (155) may have a shape that partially protrudes over the substrate (101). In embodiments, the arrangement of the metal-semiconductor layers (155) within the source / drain regions (150) may be varied. In exemplary embodiments, the metal-semiconductor layers (155) may be disposed only on the upper side and not on the lower side including the first sides of the source / drain regions (150) in the cross-section of FIG. 2b.

[0033] Source / drain regions (150) may be formed of an epitaxial layer and may include, for example, silicon (Si), silicon germanium (SiGe), or silicon carbide (SiC). Additionally, source / drain regions (150) may further include impurities such as arsenic (As) and / or phosphorus (P). In exemplary embodiments, source / drain regions (150) may include multiple regions containing elements and / or doping elements of different concentrations. Metal-semiconductor layers (155) may include semiconductor elements and metal elements included in the lower regions of source / drain regions (150). The metal-semiconductor layers (155) may include, for example, titanium silicide (TiSi), nickel silicide (NiSi), cobalt silicide (CoSi), tungsten silicide (WSi), or other metal silicides, wherein germanium (Ge) or silicon germanium (SiGe) may be included instead of silicon (Si).

[0035] Gate structures (160) may be arranged to extend in one direction, e.g., in the y-direction, intersecting the active regions (105) above the active regions (105). Channel regions of transistors may be formed in the active regions (105) intersecting the gate structures (160). That is, a “channel region” may refer to a region adjacent to the gate structures (160) that intersects the gate structures (160) in the active regions (105), and includes a depletion region of the transistor. The gate structure (160) may include a gate insulating layer (162), a gate electrode layer (165), gate spacer layers (164), and a gate capping layer (166).

[0036] A gate insulating layer (162) may be disposed between the active region (105) and the gate electrode layer (165). In exemplary embodiments, the gate insulating layer (162) may be composed of a plurality of layers or disposed to extend laterally over the gate electrode layer (165). The gate insulating layer (162) may comprise an oxide, a nitride, or a high-k dielectric material. The high-k dielectric material may refer to a dielectric material having a dielectric constant higher than that of silicon oxide (SiO2). The high-k dielectric material is, for example, aluminum oxide (Al2O3), tantalum oxide (Ta2O3), titanium oxide (TiO2), yttrium oxide (Y2O3), zirconium oxide (ZrO2), zirconium silicon oxide (ZrSi2). x O y ), hafnium oxide (HfO2), hafnium silicon oxide (HfSi x O y ), lanthanum oxide (La2O3), lanthanum aluminum oxide (LaAl x O y ), lanthanum hafnium oxide (LaHf x O y ), hafnium aluminum oxide (HfAl x O y It can be any one of ), and praseodymium oxide (Pr2O3).

[0037] The gate electrode layer (165) may include a conductive material, for example, a metal nitride such as titanium nitride (TiN), tantalum nitride (TaN), or tungsten nitride (WN), and / or a metal material such as aluminum (Al), tungsten (W), or molybdenum (Mo), or a semiconductor material such as doped polysilicon. The gate electrode layer (165) may be composed of two or more multilayers. Depending on the configuration of the semiconductor device (100), the gate electrode layer (165) may be disposed separated between at least some adjacent transistors.

[0038] Gate spacer layers (164) may be disposed on both sides of the gate electrode layer (165). The gate spacer layers (164) may insulate the source / drain regions (150) from the gate electrode layer (165). The gate spacer layers (164) may be formed in a multilayer structure according to embodiments, and the slope of the outer surface may be varied. The gate spacer layers (164) may be made of oxides, nitrides, and oxynitrides, and in particular may be made of low dielectric constant films. The gate spacer layers (164) may include, for example, at least one of SiO, SiN, SiCN, SiOC, SiON, and SiOCN.

[0039] The gate capping layer (166) can be placed on top of the gate electrode layer (165), and the bottom and sides can be surrounded by the gate electrode layer (165) and the gate spacer layers (164), respectively.

[0041] Contact plugs (180) may extend from the top toward the substrate (101) and be connected to source / drain regions (150), and may apply an electrical signal to the source / drain regions (150). The contact plugs (180) may be positioned on the source / drain regions (150) so as to be in contact with the upper surface of the source / drain regions (150) without recessing the source / drain regions (150), as shown in FIGS. 2A and 2B. The lower surface of the contact plugs (180) may be located at substantially the same height as the lower surface of the gate structures (160) or at a higher level. The contact plugs (180) may be connected to a via or wiring line at the top, which is not shown.

[0042] The contact plugs (180) may have a width greater than 10 nm along the x direction, for example, a width in the range of 10 nm to 100 nm. If the width of the contact plugs (180) is smaller than the above range, the contact resistance may increase and the difficulty of the process may increase, and if it is larger than the above range, the size of the semiconductor device (100) may increase.

[0043] The contact plugs (180) may be positioned to have a length greater than the length of the source / drain regions (150) along the y-direction. For example, as shown in FIG. 2b, the contact plugs (180) may be positioned to completely cover the source / drain region (150) by being spaced outward from both ends of the source / drain region (150) in a cross-section along the y-direction. Accordingly, the contact plugs (180) may extend relatively deeply below the source / drain regions (150). For example, the bottom (180LE) or lowest side of the contact plugs (180) may be located at a lower level or height than the bottom (150LE) or lowest side of the source / drain regions (150). For example, the bottom (180LE) of the contact plugs (180) may be located below the first sides of the source / drain regions (150). The length along the y-direction of the contact plugs (180) can be determined by taking into account the parasitic capacitance between the contact plugs (180) and the gate electrode layers (165). The contact plugs (180) may have inclined sides in which the width of the lower portion becomes narrower than the width of the upper portion according to the aspect ratio, but are not limited thereto. The contact plugs (180) may include a conductive material, for example, a metallic material such as tungsten (W), aluminum (Al), copper (Cu), or a semiconductor material such as doped polysilicon.

[0044] As described above, the contact plugs (180) are positioned along the profile of the second sides of the source / drain regions (150) as shown in FIG. 2b, without substantially recessing the source / drain regions (150) so that the profile of the source / drain regions (150) is maintained, thereby maximizing the contact area and reducing the contact resistance. Additionally, even when the source / drain regions (150) are used to control the mobility of the charge in the channel region of the transistor, the source / drain regions (150) are not recessed, so the stress may not be released.

[0046] Contact insulating layers (170) may be disposed on both side walls of contact plugs (180) along the x-direction. Contact insulating layers (170) may be disposed to fill the space between the contact plugs (180) and the gate structures (160) and between the contact plugs (180) and the interlayer insulating layer (190). The contact insulating layers (170) may have a hollow shape that completely surrounds the entire side walls of each contact plug (180) in a plan view, as shown in FIG. 1. The contact insulating layers (170) may surround the contact plugs (180) with substantially uniform thickness. In particular, the contact insulating layer (170) may be disposed to fill the space between the contact plugs (180) and the adjacent gate structures (160) and to be in contact with the gate spacer layer (164) of each gate structure (160). The lower surfaces of the contact insulating layers (170) may be in contact with the upper surface of the metal-semiconductor layers (155). The contact insulating layers (170) may be spaced apart from both ends of the source / drain regions (150) in the y direction and positioned outside the source / drain regions (150).

[0047] The sidewalls of the contact insulating layers (170) may have a slope or curvature along the shape of the gate spacer layers (164). In the drawings, the side of the contact insulating layers (170) in contact with the contact plugs (180) is shown as being perpendicular to the upper surface of the substrate (101), but is not limited thereto and may have a shape corresponding to the other side facing it. The contact insulating layers (170) may comprise an insulating material, for example, silicon oxide, silicon oxynitride, or silicon nitride. According to embodiments, the contact insulating layers (170) may be made of an air gap.

[0049] Sidewall insulating layers (170R) may be disposed on first surfaces of the source / drain regions (150) that are located outward along the y-direction, as illustrated in FIG. 2b. Sidewall insulating layers (170R) may be folded and extended from the outward first surfaces onto the device isolation layer (110) adjacent to the source / drain regions (150). Sidewall insulating layers (170R) may be layers formed together with contact insulating layers (170) on the outer surfaces of the source / drain regions (150) and remaining without being removed. Thus, sidewall insulating layers (170R) may be made of the same material as the contact insulating layers (170) and may be positioned so that the entire surface overlaps the source / drain regions (150) in a plan view. The thickness, shape, and arrangement of the sidewall insulating layers (170R) in contact with the source / drain regions (150) and the device isolation layer (110) may vary depending on the embodiments.

[0051] The interlayer insulating layer (190) may be disposed on the substrate (101) and the device isolation layer (110) outside the contact insulating layers (170) and may extend over the gate structures (160) and contact plugs (180) not shown. The interlayer insulating layer (190) may include, for example, at least one of oxide, nitride, and oxynitride, and may include a low dielectric constant material. According to embodiments, the interlayer insulating layer (190) may be composed of a plurality of layers formed at different stages according to the manufacturing process.

[0053] FIG. 3 is a plan view illustrating a semiconductor device according to exemplary embodiments.

[0054] FIGS. 4a and 4b are cross-sectional views illustrating a semiconductor device according to exemplary embodiments. FIG. 4a illustrates cross-sections of the semiconductor device of FIG. 3 cut along the cutting lines IV-IV' and V-V', and FIG. 4b illustrates cross-sections of the semiconductor device of FIG. 3 cut along the cutting line VI-VI'. For convenience of explanation, FIGS. 3 to 4b only show the main components of the semiconductor device.

[0055] Referring to FIGS. 3 to 4b, a semiconductor device (100a) may include a substrate (101) having first and second regions (R1, R2), active regions (105), a device isolation layer (110), first and second source / drain regions (150A, 150B), gate structures (160), contact insulating layers (170), contact plugs (180), and an interlayer insulating layer (190). The semiconductor device (100a) may include transistors arranged around the intersecting active regions (105) and gate structures (160), for example, PMOS transistors may be arranged in the first region (R1) and NMOS transistors may be arranged in the second region (R2). Hereinafter, descriptions that overlap with the description above with reference to FIGS. 1 to 2c are omitted.

[0057] The substrate (101) and active regions (105) may contain impurities of different conductivity types in the first and second regions (R1, R2). The first and second source / drain regions (150A, 150B) may contain different materials. In particular, the first and second metal-semiconductor layers (155A, 155B) of the first and second source / drain regions (150A, 150B) may be made of different materials in the first and second regions (R1, R2). For example, the first metal-semiconductor layers (155A) of the first region (R1) may contain nickel silicide (NiSi), and the second metal-semiconductor layers (155B) of the second region (R2) may contain titanium silicide (TiSi). In exemplary embodiments, the gate electrode layers (165) may also include different metal materials in the first and second regions (R1, R2).

[0059] In the first region (R1), the first distance (D1) between the gate electrode layers (165) and the contact plugs (180) along the x direction may be shorter than the second distance (D2) between the gate electrode layers (165) and the contact plugs (180) along the x direction in the second region (R2). This may be intended to optimize the parasitic capacitance between the contact plugs (180) and the gate electrode layers (165) between transistors of different conductivity types.

[0060] In particular, in this embodiment, the thickness along the x-direction of the contact insulating layers (170) is constant in the first and second regions (R1, R2), and the thicknesses of the gate spacer layers (164) may differ from each other. Specifically, the gate spacer layers (164) may have a first thickness (T1) in the first region (R1) and a second thickness (T2) that is thicker than the first thickness (T1) in the second region (R2). Hereinafter, thickness or width, etc., may each refer to an average value or a value at the same height. According to the embodiments, the gate spacer layer (164) in the second region (R2) may further include a second layer formed on the first layer in addition to the first layer identical to that in the first region (R1). Additionally, the contact plugs (180) may have a first width (W1) along the x direction in a first region (R1) and a second width (W2) smaller than the first width (W1) in a second region (R2), but are not limited thereto.

[0062] FIG. 5 is a cross-sectional view illustrating a semiconductor device according to exemplary embodiments. FIG. 5 illustrates regions corresponding to FIG. 4a.

[0063] Referring to FIG. 5, in the semiconductor device (100b), the thickness of the gate spacer layers (164) along the x-direction is constant in the first and second regions (R1, R2), and the thickness of the contact insulating layers (170) may differ. Specifically, the contact insulating layers (170) may have a third thickness (T3) along the x-direction in the first region (R1) and a fourth thickness (T4) that is thicker than the third thickness (T3) in the second region (R2). Additionally, the contact plugs (180) may have a first width (W1) along the x-direction in the first region (R1) and a second width (W2) that is smaller than the first width (W1) in the second region (R2), but are not limited thereto and may have the same width.

[0064] Accordingly, in the semiconductor device (100b), the distance between the gate electrode layers (165) and the contact plugs (180) along the x direction in the first region (R1) may be shorter than the distance between the gate electrode layers (165) and the contact plugs (180) along the x direction in the second region (R2).

[0066] FIGS. 6A and 6B are cross-sectional views illustrating a semiconductor device according to exemplary embodiments. FIGS. 6A and 6B illustrate cross-sections along the y-direction at the boundary of the first and second regions (R1, R2).

[0067] Referring to FIG. 6a, in a semiconductor device (100c), parts of contact insulating layers (170) may come into contact with each other at the boundary of first and second regions (R1, R2). The contact insulating layer (170) at the end of the first region (R1) and the contact insulating layer (170) at the end of the second region (R2) may come into contact with each other. In this case, either the contact insulating layer (170) at the end of the first region (R1) and the contact insulating layer (170) at the end of the second region (R2) may have a relatively thinner thickness than the other.

[0069] Referring to FIG. 6b, in the semiconductor device (100d), the contact plugs (180) may have inclined sides that decrease in width as they face the substrate (101) from the top. Additionally, at the boundary between the first and second regions (R1, R2), the contact insulating layer (170) at the end of the first region (R1) may remain partially intact while in contact with the contact insulating layer (170) at the end of the second region (R2). This structure may be formed by partially removing the contact insulating layer (170) of the first region (R1) that was formed first when the contact insulating layer (170) of the second region (R2) is formed. However, the remaining height and shape of the contact insulating layer (170) of the first region (R1) that remains in the embodiments may be varied.

[0071] FIG. 7 is a plan view illustrating a semiconductor device according to exemplary embodiments.

[0072] FIG. 8 is a series of cross-sectional views illustrating a semiconductor device according to exemplary embodiments. FIG. 8 illustrates cross-sections of the semiconductor device of FIG. 7 cut along the cutting lines Ⅶ-Ⅶ' and Ⅷ-Ⅷ'.

[0073] Referring to FIGS. 7 and 8, the semiconductor device (100e) may include a substrate (101) having third and fourth regions (R3, R4), active regions (105), a device isolation layer (110), source / drain regions (150), first and second gate structures (160A, 160B), contact insulating layers (170), contact plugs (180), and an interlayer insulating layer (190). The semiconductor device (100e) may include transistors arranged around the intersecting active regions (105) and the first and second gate structures (160A, 160B), for example, the transistors in the third and fourth regions (R3, R4) may have different pitches and, accordingly, different channel region lengths. In this case, the transistors in the third and fourth regions (R3, R4) may be transistors driven under different threshold voltages.

[0074] The gate electrode layers (165) may have a third width (W3) along the x-direction in the third region (R3) and a fourth width (W4) greater than the third width (W3) along the x-direction in the fourth region (R4). Additionally, the thicknesses of the contact insulating layers (170) may differ in the third and fourth regions (R3, R4). Specifically, the contact insulating layers (170) may have a fifth thickness (T5) in the third region (R3) and a sixth thickness (T6) greater than the fifth thickness (T5) in the fourth region (R4). Additionally, the contact plugs (180) may have a fifth width (W5) along the x-direction in the third region (R3) and a sixth width (W6) greater than the fifth width (W5) in the fourth region (R4), but are not limited thereto. The thickness of the gate spacer layers (164) along the x-direction may be substantially the same in the third and fourth regions (R3, R4), but is not limited thereto. Accordingly, in the semiconductor device (100e), the first distance (D1) between the gate electrode layers (165) and the contact plugs (180) along the x-direction in the third region (R3) may be shorter than the third distance (D3) between the gate electrode layers (165) and the contact plugs (180) along the x-direction in the fourth region (R4).

[0076] FIGS. 9a through 9c are cross-sectional views of a semiconductor device according to exemplary embodiments. FIGS. 9a through 9c illustrate parts of regions corresponding to FIGS. 2a through 2c.

[0077] Referring to FIGS. 9a through 9c, a semiconductor device (100f) may include a substrate (101), active regions (105) on the substrate (101), a device isolation layer (110), channel structures (140) including a plurality of channel layers (141, 142, 143) spaced perpendicularly apart from each other on the active regions (105), source / drain regions (150) in contact with the plurality of channel layers (141, 142, 143), gate structures (160f) extending intersecting with the active regions (105), contact insulating layers (170), and contact plugs (180) connected to the source / drain regions (150). The semiconductor device (100f) may include transistors of a gate-all-around type structure in which gate structures (160f) are disposed between active regions (105) and channel structures (140) and between a plurality of nanosheet-shaped channel layers (141, 142, 143) of the channel structures (140). The semiconductor device (100f) is an MBCFET formed by channel structures (140), source / drain regions (150), and gate structures (160f). TM It may include transistors with a (Multi-Bridge Channel FET) structure.

[0079] The channel structure (140) may include first to third channel layers (141, 142, 143), which are two or more channel layers spaced apart from each other in a direction perpendicular to the upper surface of the active regions (105), for example, in the z direction, on the active regions (105). The first to third channel layers (141, 142, 143) may be spaced apart from the upper surfaces of the active regions (105) while being connected to the source / drain regions (150). The first to third channel layers (141, 142, 143) may have a width equal to or similar to that of the active regions (105) in the y direction and a width equal to or similar to that of the gate structures (160f) in the x direction. However, according to the embodiments, the first to third channel layers (141, 142, 143) may have a reduced width such that the sides are located below the gate structures (160f) in the x direction.

[0080] The first to third channel layers (141, 142, 143) may be made of a semiconductor material and may include, for example, at least one of silicon (Si), silicon germanium (SiGe), and germanium (Ge). The first to third channel layers (141, 142, 143) may be made of, for example, the same material as the substrate (101). The number and shape of the channel layers (141, 142, 143) forming a channel structure (140) may be varied in the embodiments. For example, according to the embodiments, additional channel layers may be located in the region where the active regions (105) contact the gate electrode layers (165).

[0082] Gate structures (160f) may be arranged to extend in one direction, e.g., in the y-direction, intersecting the active regions (105) and channel structures (140) on top of the active regions (105) and channel structures (140). Channel regions of transistors may be formed in the active regions (105) and channel structures (140) intersecting the gate structures (160f). Each gate structure (160f) may include a gate electrode layer (165), gate insulating layers (162) between the gate electrode layer (165) and a plurality of channel layers (141, 142, 143), gate spacer layers (164) on the sides of the gate electrode layer (165), and a gate capping layer (166) on the upper surface of the gate electrode layer (165).

[0083] The gate insulating layer (162) may be positioned between the active region (105) and the gate electrode layer (165) and between the channel structure (140) and the gate electrode layer (165), and may be positioned to cover at least some of the surfaces of the gate electrode layer (165). For example, the gate insulating layer (162) may be positioned to surround all surfaces of the gate electrode layer (165) except for the top surface.

[0084] The gate electrode layer (165) can be disposed extending above the channel structure (140) and filling the space between the plurality of channel layers (141, 142, 143) above the active regions (105). The gate electrode layer (165) can be spaced apart from the plurality of channel layers (141, 142, 143) by a gate insulating layer (162).

[0086] The internal spacer layers (130) may be arranged parallel to the gate electrode layer (165) between the channel structures (140). Below the third channel layer (143), the gate electrode layer (165) may be electrically separated from the source / drain regions (150) by the internal spacer layers (130). The internal spacer layers (130) may have a shape in which the side facing the gate electrode layer (165) is rounded inwardly convex toward the gate electrode layer (165), but is not limited thereto. The internal spacer layers (130) may be made of oxides, nitrides, and oxynitrides, and in particular may be made of low dielectric constant films.

[0088] In exemplary embodiments, the MBCFET TM A transistor of the structure may also be additionally disposed in one region of the semiconductor device described above with reference to FIGS. 1 to 8.

[0090] FIGS. 10a to 10k are drawings illustrated in the order of process to explain a method for manufacturing a semiconductor device according to exemplary embodiments. FIGS. 10a to 10k describe an example of a method for manufacturing a semiconductor device of FIGS. 3 to 4b, FIGS. 10a to 10e and FIGS. 10f to 10k illustrate cross-sections corresponding to FIG. 4a, and FIG. 10f illustrates a cross-section corresponding to FIG. 4b.

[0091] Referring to FIG. 10a, after forming active regions (105) by patterning a substrate (101) to form a device isolation layer (110), sacrificial gate structures (SG) and gate spacer layers (164) can be formed.

[0092] First, active regions (105) can be formed by forming trenches by anisotropically etching the substrate (101) using a mask layer. The substrate (101) may include first and second regions (R1, R2), and the active regions (105) may include impurities of different conductivity types in the first and second regions (R1, R2). Since the trench regions have a high aspect ratio, the width may become narrower towards the bottom, and accordingly, the active regions (105) may have a shape that narrows towards the top. The device isolation layer (110) can be formed by filling the trench regions with an insulating material and then flattening along the upper surface of the active regions (105).

[0093] Next, sacrificial gate structures (SG) can be formed on the active regions (105) to have a line shape extending in the y-direction intersecting the active regions (105). The sacrificial gate structures (SG) can be formed in the region where gate structures (160) are disposed as in FIG. 4a through a subsequent process. The sacrificial gate structures (SG) may include first to third sacrificial gate layers (SG1, SG2, SG3). The first and second sacrificial gate layers (SG1, SG2) may be an insulating layer and a conductive layer, respectively, but are not limited thereto, and the first and second sacrificial gate layers (SG1, SG2) may be formed as a single layer. For example, the first sacrificial gate layer (SG1) may include silicon oxide, and the second sacrificial gate layer (SG2) may include polysilicon. The third sacrificial gate layer (SG3) can be used to pattern the first and second sacrificial gate layers (SG1, SG2) and may include silicon oxide and / or silicon nitride. However, the structure of the sacrificial gate structure (SG) may be varied in the embodiments.

[0094] Gate spacer layers (164) may be formed on the sidewalls of the sacrificial gate structure (SG) and may remain partially on the active regions (105). An interlayer insulating layer (190) covering the sacrificial gate structure (SG) and the substrate (101) may be formed on the sacrificial gate structure (SG). The thickness of the interlayer insulating layer (190) may vary in the embodiments, and, for example, it may have a height equal to or similar to the top surface of the sacrificial gate structure (SG).

[0096] Referring to FIG. 10b, in the first region (R1), the interlayer insulating layer (190) can be removed from both sides of the sacrificial gate structures (SG) to form the first openings (OP1), and the active region (105) exposed between the sacrificial gate structures (SG) can be recessed to form the second openings (OP2).

[0097] First, by using separate mask layers, an area in the first region (R1) where the first source / drain regions (150A) of FIG. 4a, contact insulating layers (170), and contact plugs (180) are to be placed can be opened. The open area may be a rectangular area in which sacrificial gate structures (SG) are interposed.

[0098] The interlayer insulating layer (190) and the active region (105) can be sequentially removed between the sacrificial gate structures (SG) using different etchants. That is, in this embodiment, the region where the first source / drain regions (150A) are to be formed and the region where the contact plugs (180) are to be formed can be etched simultaneously or sequentially. The second openings (OP2) can be formed between the gate spacer layers (164) so ​​as to be connected from the outer surface of the gate spacer layers (164) as shown in FIG. 10b, or can be formed to have a shape extending to the bottom of the gate spacer layers (164) or the bottom of the sacrificial gate structures (SG). Optionally, after the formation of the second openings (OP2), a process of curing the surface of the recessed active region (105) may be performed through a separate process.

[0100] Referring to FIG. 10c, first source / drain regions (150A) can be formed in the second openings (OP2).

[0101] The first source / drain regions (150A) may be an epitaxial layer formed by growing from an active region (105) using, for example, a Selective Epitaxial Growth (SEG) process. According to embodiments, the first source / drain regions (150A) may contain impurities by in-situ doping.

[0103] Referring to FIG. 10d, a portion of the first source / drain regions (150A) can be metallized to form the first metal-semiconductor layers (155A) of the first source / drain regions (150A).

[0104] For example, if the first source / drain regions (150A) comprise silicon (Si), the first metal-semiconductor layers (155A) may be formed into metal silicide layers by a metallization process. For example, the first metal-semiconductor layers (155A) may comprise nickel silicide (NiSi).

[0105] The upper surfaces of the first metal-semiconductor layers (155A) may substantially co-plane with the upper surface of the active region (105) or be located higher than the upper surface of the active region (105), depending on the thickness of the first metal-semiconductor layers (155A). However, if the thickness of the first metal-semiconductor layers (155A) is excessively thick, parasitic capacitance may increase, and if the first metal-semiconductor layers (155A) are formed lower than the top of the second openings (OP2), stress in the first source / drain regions (150A) may decrease.

[0106] However, depending on the embodiments, the first metal-semiconductor layers (155A) may be formed after the formation of the contact insulating layers (170) described below with reference to FIG. 10e. In this case, since the sidewall insulating layers (170R) (see FIG. 10f) are formed first, the first metal-semiconductor layers (155A) may not be formed on at least the outer first faces of the first faces of the first source / drain regions (150A). Even when the first source / drain regions (150A) are formed to be connected on adjacent active regions (105), the first metal-semiconductor layers (155A) may not be formed on at least the inner first faces of the first faces of the first source / drain regions (150A).

[0108] Referring to FIG. 10e and FIG. 10f, contact insulating layers (170) can be formed on the sides of the interlayer insulating layer (190) and the gate spacer layers (164) within the first openings (OP1).

[0109] The contact insulating layers (170) may have the form of a liner. The contact insulating layers (170) may be formed by forming an insulating material in exposed areas with a uniform thickness and removing a portion from the z-direction so that the upper surfaces of the first source / drain areas (150A) are exposed. The contact insulating layers (170) may include silicon nitride or silicon oxide, and it may be advantageous in terms of parasitic capacitance to be made of a material with a relatively low dielectric constant. Although all sides of the contact insulating layers (170) are shown as vertical for convenience in the drawing, the contact insulating layers (170) may have a shape following the profile of the gate spacer layers (164).

[0110] As illustrated in FIG. 10f, in the region between the sacrificial gate structures (SG), a first opening (OP1) is formed so as to expose the source / drain regions (150A) and the device isolation layer (110), and contact insulating layers (170) may be formed on the sides of the interlayer insulating layers (190) spaced outward from each end of the first source / drain regions (150A). In particular, the contact insulating layers (170) may be formed to surround all the outer sides of the first source / drain regions (150A), as indicated by the dotted line, and then removed from the top by a predetermined thickness so that at least a portion remains only on the outer first sides at the bottom of the first source / drain regions (150A) to form the sidewall insulating layers (170R). Additionally, it may be formed on the upper surface of the device isolation layer (110) and then removed in an area that does not overlap with the first source / drain regions (150A). That is, by this process, the sidewall insulating layers (170R) may be disposed on the lower part of the first source / drain regions (150A) and on the upper surface of the device isolation layer (110) in an area that overlaps with the first source / drain regions (150A) in a plan view.

[0112] Referring to FIG. 10g, after forming contact plugs (180) on the first source / drain regions (150A) between the contact insulating layers (170), an upper interlayer insulating layer (195) can be formed, and first and second openings (OP1', OP2') can be formed in the second region (R2).

[0113] First, contact plugs (180) can be formed by depositing a conductive material between contact insulating layers (170) and performing a planarization process. In the planarization process, a third sacrificial gate layer (SG3) can be used as a stopper layer. Next, an upper interlayer insulating layer (195) can be formed on top.

[0114] In this way, the contact plugs (180) are formed not by etching a layer on the first source / drain regions (150A), but by filling an open region including a first opening (OP), so that the first source / drain regions (150A) can be formed without recessing. Accordingly, the contact area with the first source / drain regions (150A) can be secured, and the width at the bottom can also be secured, thereby preventing the stress of the first source / drain regions (150A) from being released or the contact resistance from increasing. In addition, the size of the contact plugs (180) can be controlled, thereby preventing the occurrence of defects in contact with the gate structures (160) formed subsequently.

[0115] The first and second openings (OP1', OP2') can be formed in the same manner as described above with reference to FIG. 10b. In the second region (R2), the first openings (OP1') can be formed by removing the interlayer insulating layer (190) from both sides of the sacrificial gate structures (SG), and the second openings (OP2') can be formed by recessing the active region (105) exposed between the sacrificial gate structures (SG).

[0117] Referring to FIG. 10h, second source / drain regions (150B) can be formed in the second openings (OP2), and a portion of the second source / drain regions (150B) can be metallized to form second metal-semiconductor layers (155B) of the second source / drain regions (150B).

[0118] The second source / drain regions (150B) and the second metal-semiconductor layers (155B) may be formed in the same manner as described above with reference to FIG. 10c and FIG. 10d. However, the second source / drain regions (150B) may include a material different from the first source / drain regions (150A), and the second metal-semiconductor layers (155B) may also include a material different from the first metal-semiconductor layers (155A). For example, the second metal-semiconductor layers (155B) may be formed to include titanium silicide (TiSi).

[0120] Referring to FIG. 10i, contact insulating layers (170) can be formed on the sides of the interlayer insulating layer (190) and the gate spacer layers (164) within the first openings (OP1').

[0121] The contact insulating layers (170) can be formed in the same manner as described above with reference to FIG. 10e and FIG. 10f. By doing so, sidewall insulating layers (170R) can also be formed on the outer surfaces of the lower part of the second source / drain regions (150B) and on the device isolation layer (110) in an unillustrated cross-section along the y direction.

[0123] Referring to FIG. 10j, after forming contact plugs (180) on the second source / drain regions (150B) between the contact insulating layers (170), a flattening process can be performed.

[0124] The contact plugs (180) can be formed in the manner described above with reference to FIG. 10g. Next, a flattening process can be performed on the first and second regions (R1, R2) to remove the upper interlayer insulating layer (195). According to embodiments, during the flattening process, the sacrificial gate structures (SG), contact insulating layers (170), contact plugs (180), and interlayer insulating layer (190) may also be partially removed from the upper portion.

[0125] In exemplary embodiments, if the contact insulating layers (170) are to be formed into an air gap, the contact insulating layer (170) material deposited in this step may be optionally removed.

[0127] Referring to FIG. 10k, in the first and second regions (R1, R2), the sacrificial gate structure (SG) can be removed to form the third openings (OP3).

[0128] The sacrificial gate structure (SG) can be selectively removed from the lower active regions (105) and the device isolation layer (110). The removal process of the sacrificial gate structure (SG) may utilize at least one of a dry etching process and a wet etching process.

[0130] Next, referring together with FIG. 4a, gate insulating layers (162), gate electrode layers (165), and gate capping layers (166) can be formed within the third openings (OP3) to finally form gate structures (160).

[0131] Gate insulating layers (162) may be formed along the bottom surface of the third openings (OP3) and may be formed to extend upward along the sides. After forming the gate insulating layers (162), gate electrode layers (165), and gate capping layers (166), the material remaining on the interlayer insulating layer (190) may be removed using a planarization process such as a Chemical Mechanical Polishing (CMP) process. In this step, the gate capping layers (166) and gate spacer layers (164) may also be partially removed from the top so that their height is finally reduced. However, depending on the embodiments, the process of forming the gate structures (160) may be performed before the formation of the first and second openings (OP1, OP2) described above with reference to FIG. 10b.

[0133] The present invention is not limited by the embodiments described above and the attached drawings, but is intended to be limited by the appended claims. Accordingly, various substitutions, modifications, and changes may be made by those skilled in the art within the scope of the technical concept of the present invention as described in the claims, and such are also to be considered to fall within the scope of the present invention. Explanation of the symbols

[0135] 101: Substrate 105: Active region 110: Device isolation layer 130: Internal spacer layer 140: Channel structure 141, 142, 143: Channel layer 150: Source / Drain Area 160: Gate Structure 162, 163: Gate insulation layer 164: Gate spacer layer 165: Gate electrode layer 166: Gate capping layer 170: Contact insulation layer 170R: Sidewall insulation layer 180: Contact plug 190: Interlayer insulation layer

Claims

Claim 1 A substrate having first and second regions and including active regions extending in a first direction; gate structures each disposed on the first and second regions and extending in a second direction intersecting the active regions; source / drain regions disposed on the active regions at at least one side of the gate structures and including metal-semiconductor layers located at the top; contact plugs disposed to contact a portion of the outer surfaces of the source / drain regions at at least one side of the gate structures and having a bottom positioned at a level lower than the bottom of the source / drain regions; contact insulating layers on the sidewalls of the contact plugs; A semiconductor device comprising an interlayer insulating layer on the substrate, wherein each of the gate structures comprises a gate insulating layer and a gate electrode layer sequentially disposed on the substrate, and gate spacer layers disposed on sidewalls along the first direction of the gate electrode layer, wherein in the first region, the first distance between the gate electrode layer and the adjacent contact plug is shorter than the second distance between the gate electrode layer and the adjacent contact plug in the second region, wherein the contact insulating layers surround the entire sidewalls of each of the contact plugs with a uniform thickness in a planar view, and further comprising a sidewall insulating layer comprising, in a cross-sectional view along the second direction, a first portion extending parallel to the upper surface of the substrate and a second portion extending parallel to the outer surface of the source / drain region while moving away from the upper surface of the substrate. Claim 2 A semiconductor device according to claim 1, wherein the contact insulating layers fill the space between the contact plugs and the gate structures and between the contact plugs and the interlayer insulating layer. Claim 3 A semiconductor device according to claim 1, wherein the lower surfaces of the contact insulating layers are in contact with the metal-semiconductor layers. Claim 4 A semiconductor device according to claim 1, wherein in the first region, the gate spacer layers have a first thickness along the first direction, and in the second region, the gate spacer layers have a second thickness along the first direction that is thicker than the first thickness. Claim 5 A semiconductor device according to claim 1, wherein in the first region, the contact insulating layers have a third thickness along the first direction, and in the second region, the contact insulating layers have a fourth thickness thicker than the third thickness along the first direction. Claim 6 A semiconductor device according to claim 1, wherein in the first region, the contact plugs have a first width along the first direction, and in the second region, the contact plugs have a second width along the first direction that is smaller than the first width. Claim 7 A semiconductor device according to claim 1, wherein at the boundary between the first region and the second region, the contact insulating layer on the first region is arranged to be in contact with the contact insulating layer on the second region. Claim 8 A semiconductor device according to claim 1, wherein in the first region, the gate electrode layer has a third width along the first direction, and in the second region, the gate electrode layer has a fourth width along the first direction that is greater than the third width. Claim 9 delete Claim 10 delete Claim 11 delete Claim 12 delete Claim 13 delete Claim 14 delete Claim 15 delete Claim 16 delete Claim 17 delete Claim 18 delete Claim 19 delete Claim 20 delete

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