Semiconductor memory device

Abstract

This invention provides a semiconductor memory device. The semiconductor memory device includes: a substrate, including at least one logic active region among a plurality of active regions in a memory cell region and a peripheral circuit region; word lines extending in a first horizontal direction and located on the plurality of active regions; a bit line structure extending in a second horizontal direction orthogonal to the first horizontal direction and located on the plurality of active regions, and including bit lines, a covering insulating structure on the side surface of the ends of the bit lines, and an insulating cover structure on the bit lines and the covering insulating structure; and a gate line located on at least one logic active region.

Description

Technical Field

[0001] [Cross-reference to related applications]

[0002] This application claims priority to Korean Patent Application No. 10-2022-0132714, filed on October 14, 2022, with the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety.

[0003] This disclosure relates to a semiconductor memory device, and more specifically, to a semiconductor memory device with electrical reliability. Prior Technology

[0004] Driven by the rapid development of the electronics industry and user demands, electronic devices are becoming increasingly smaller and lighter. Consequently, semiconductor memory devices used in electronic devices require high integration. In this regard, the design rules for semiconductor memory device components are shrinking. Summary of the Invention

[0005] This disclosure relates to a semiconductor memory device with electrical reliability.

[0006] According to one embodiment, a semiconductor memory device includes: a substrate including at least one logic active region among a plurality of active regions in a memory cell region and a peripheral circuit region; a word line extending in a first horizontal direction and located on the plurality of active regions; a bit line structure extending in a second horizontal direction orthogonal to the first horizontal direction and located on the plurality of active regions, and including the bit line, a covering insulating structure on the side surface of the bit line's end, and an insulating cover structure on the bit line and the covering insulating structure; and a gate line located on at least one logic active region.

[0007] According to another embodiment, a semiconductor memory device includes: a substrate including at least one logic active region among a plurality of active regions in a memory cell region and a peripheral circuit region; a word line extending in a first horizontal direction on the plurality of active regions; a bit line structure extending in a second horizontal direction orthogonal to the first horizontal direction on the plurality of active regions, and including a bit line having a stacked structure including a first metal conductive layer and a second metal conductive layer, a covering insulating structure on the side surface of the end of the bit line and spaced apart from the second metal conductive layer, and an insulating cover structure on the bit line and the covering insulating structure; and a gate line on at least one logic active region.

[0008] According to another embodiment, a semiconductor memory device includes: a substrate; a device isolation layer defining a plurality of active regions on a memory cell region of the substrate; a logic device isolation layer defining at least one logic active region on a peripheral circuit region of the substrate; a plurality of word lines in a plurality of word line trenches extending parallel to each other in a first horizontal direction across the plurality of active regions, each of the plurality of word lines having a stacked structure including a lower word line layer and an upper word line layer; a plurality of buried insulating layers in the plurality of word line trenches on the plurality of word lines; and a plurality of bit line structures on the plurality of active regions extending parallel to each other in a second horizontal direction orthogonal to the first horizontal direction, each of the plurality of bit line structures including: a bit line having a stacked structure including a first bit line conductive layer and a second bit line conductive layer; and a covering insulating structure on the side surface of the end of the bit line and adjacent to the second bit line conductive layer. The electrical layers are separated by a first bitline conductive layer; and an insulating cover structure is located on the bitline and covering the insulating structure and has a stacked structure including a first insulating cover layer, a second insulating cover layer and a third insulating cover layer; a gate line is located on at least one logic active region and has a stacked structure including a first gate line conductive layer and a second gate line conductive layer, the first gate line conductive layer and the first bitline conductive layer comprising a first identical material, and the second bitline conductive layer and the second gateline conductive layer comprising a second identical material; a plurality of embedded contacts are located in the space of the plurality of bitline structures and connected to the plurality of active regions; a plurality of landing pads are located in the space of the plurality of bitline structures and extend to the plurality of bitline structures; and a plurality of capacitor structures include a plurality of lower electrodes, an upper electrode and a capacitor dielectric layer between the plurality of lower electrodes and the upper electrode in contact with the plurality of landing pads. Simple Explanation of the Diagram

[0009] The above and other features will become more apparent from the following description of embodiments accompanied by the accompanying drawings: Figure 1 is a schematic planar layout for describing the main components of a semiconductor memory device according to an embodiment. Figures 2A, 2B, 2C, 2D, 2E, 3A, 3B, 3C, 3D, 3E, 4A, 4B, 4C, 4D, 4E, 5A, 5B, 5C, 5D, 5E, 6 to 16, 17A, 17B, 17C, 17D, 17E, 18A, 18B, 18C, 18D, 18E, 19A, 19B, 19C, 19D, and 19E are cross-sectional views illustrating a method of manufacturing a semiconductor memory device according to an embodiment, and Figures 20A, 20B, 20C, 20D, 20E, 21A, and 21B are cross-sectional views illustrating a semiconductor memory device according to an embodiment. Figures 22 and 23 are cross-sectional views illustrating a method of manufacturing a semiconductor memory device according to an embodiment, and Figures 24, 25A and 25B are cross-sectional views illustrating a semiconductor memory device according to an embodiment. Figures 26 to 30 are cross-sectional views illustrating a method of manufacturing a semiconductor memory device according to an embodiment, and Figures 31A, 31B, 31C, 31D, 31E, 32A, and 32B are cross-sectional views illustrating a semiconductor memory device according to an embodiment. Implementation

[0010] In the following description, embodiments will be described in detail with reference to the accompanying drawings. The embodiments described herein are illustrative examples, and therefore, this disclosure is not limited thereto and may be implemented in various other forms. The embodiments provided in the following description do not exclude the association with one or more features of another instance or another embodiment also provided herein or not provided herein but consistent with this disclosure. It should be understood that when an element or layer is referred to as being "on," "connected to," or "coupled to" another element or layer, the element or layer may be directly on, directly connected to, or coupled to the other element or layer, or there may be intervening elements or layers. Conversely, when an element is referred to as being "directly on," "directly connected to," or "directly coupled to" another element or layer, there are no intervening elements or layers. As used herein, the term "and / or" includes any one or more of the associated listed items and all combinations thereof. Expressions such as "at least one of" modify the entire list of elements when placed before the list of elements, and do not modify individual elements in the list. For example, the expression "at least one of a, b, and c" should be understood to include only a, only b, only c, both a and b, both a and c, both b and c, or all of a, b, and c. It should also be understood that even if one step or operation of manufacturing equipment or structure is described later than another step or operation, that step or operation may be performed later than the other step or operation unless the other step or operation is described as being performed after the first step or operation. The same reference numerals are used to indicate the same elements in the drawings, and their repeated descriptions are omitted. In the following embodiments and claims, it should be understood that although the terms first, second, etc., may be used herein to describe various elements, such elements should not be limited by these terms. These terms are used only to distinguish one element from another.

[0011] Figure 1 is a schematic planar layout for describing the main components of a semiconductor memory device 1 according to an embodiment.

[0012] Referring to Figure 1, the semiconductor memory device 1 includes a memory cell region CR and a peripheral circuit region PR. The semiconductor memory device 1 may include multiple active regions ACT formed in the memory cell region CR and multiple logic active regions ACTP formed in the peripheral circuit region PR.

[0013] In some embodiments, a plurality of active regions ACT may be configured in a memory cell region CR to have a long axis in an inclined direction relative to a first horizontal direction (X direction) and a second horizontal direction (Y direction).

[0014] Multiple word lines (WL) can extend parallel to each other in a first horizontal direction (X direction) across multiple active regions (ACT) within the memory cell region (CR). Multiple bit lines (BL) can extend parallel to each other in a second horizontal direction (Y direction) intersecting the first horizontal direction (X direction) along the multiple word lines (WL). The multiple bit lines (BL) can be connected to the multiple active regions (ACT) via direct contacts (DC).

[0015] In some embodiments, multiple embedded contacts BC may each be formed between two adjacent bit lines BL of multiple bit lines BL. In some embodiments, multiple embedded contacts BC may be arranged in rows in a first horizontal direction (X direction) and a second horizontal direction (Y direction).

[0016] Multiple landing pads LP may be formed on multiple embedded contacts BC. The multiple landing pads LP may be configured to at least partially and respectively overlap with the multiple embedded contacts BC. In some embodiments, each of the multiple landing pads LP may extend to the top of one of two adjacent bit lines BL.

[0017] Multiple storage nodes (SNs) can be formed on multiple landing pads (LPs). Multiple storage nodes (SNs) can be formed on multiple bit lines (BLs). Each of the multiple storage nodes (SNs) can be the lower electrode of each of multiple capacitors. Multiple storage nodes (SNs) can be connected to multiple active regions (ACTs) via multiple landing pads (LPs) and multiple embedded contacts (BCs).

[0018] Multiple gate line patterns (GLPs) can be configured on multiple logic active regions (ACTPs) within a peripheral circuit region (PR). In some embodiments, some of the gate line patterns (GLPs) may extend parallel to each other in a second horizontal direction (Y direction) on the multiple logic active regions (ACTPs). However, the embodiments are not limited thereto. For example, the multiple gate line patterns (GLPs) may have various widths, may extend parallel to each other in a first horizontal direction (X direction), may be curved, or may extend with different widths in each horizontal direction.

[0019] In Figure 1, for ease of illustration, components other than the multiple logic active regions (ACTPs) and multiple gate line patterns (GLPs) in the peripheral circuit region PR are omitted. Furthermore, Figure 1 shows that the multiple gate line patterns (GLPs) are only configured on the multiple logic active regions (ACTPs). However, the embodiment is not limited to this. For example, at least some of the gate line patterns (GLPs) may extend beyond the logic active region 117, for example, to the logic device isolation layer 115, as shown in Figure 20E.

[0020] Multiple gate line patterns (GLPs) may be at the same level as multiple bit lines (BLs). In some embodiments, the multiple gate line patterns (GLPs) and the multiple bit lines (BLs) may contain the same material, or at least partially contain the same material. For example, the process of forming all or some of the gate line patterns (GLPs) may be the same as the process of forming all or some of the bit lines (BLs).

[0021] Figures 2A to 2E, 3A to 3E, 4A to 4E, 5A to 5E, 6 to 16, 17A to 17E, 18A to 18E, and 19A to 19E are cross-sectional views illustrating a method of manufacturing a semiconductor memory device according to an embodiment, and Figures 20A to 20E, 21A, and 21B are cross-sectional views illustrating a semiconductor memory device according to an embodiment. Specifically, Figures 2A, 3A, 4A, 5A, 17A, 18A, 19A, and 20A are cross-sectional views taken along line A-A' of Figure 1; Figures 2B, 3B, 4B, 5B, 17B, 18B, 19B, and 20B are cross-sectional views taken along line B-B' of Figure 1; Figures 2C, 3C, 4C, 5C, 17C, 18C, 19C, and 20C are cross-sectional views taken along line C-C' of Figure 1; Figures 2D, 3A, 4A, 5A, 17A, 18A, 19A, and 20C are cross-sectional views taken along line C-C' of Figure 1; Figures 2D, 3A, 4A, 5A, 17A, 18A, 19A, and 20A are cross-sectional views taken along line A-A' of Figure 1; Figures 2B, 3B, 4B, 5B, 17B, 18B, 19B, and 20C are cross-sectional views taken along line C-C' of Figure 1; Figures 2D, 3A, 4A, 5A, 17A, 18A, 19A ...A are cross-sectional views taken along line A-A' of Figure 1. Figures 3D, 4D, 5D, 17D, 18D, 19D, and 20D are cross-sectional views taken along line D-D' in Figure 1; Figures 2E, 3E, 4E, 5E, 6 to 16, 17E, 18E, 19E, and 20E are cross-sectional views taken along line E-E' in Figure 1; Figure 21A is a cross-sectional view taken along line XXIa-XXIa' in Figure 20E; and Figure 21B is a cross-sectional view taken along line XXIb-XXIb' in Figure 20E.

[0022] Referring to Figures 2A to 2E, device isolation trench 116T and logic device isolation trench 115T can be formed in the substrate 110, and a device isolation layer 116 filling the device isolation trench 116T and a logic device isolation layer 115 filling the logic device isolation trench 115T can be formed.

[0023] The substrate 110 may comprise, for example, silicon (Si), such as crystalline Si, polycrystalline Si, or amorphous Si. Alternatively, the substrate 110 may comprise a semiconductor element such as germanium (Ge), or at least one compound semiconductor selected from the following: silicon germanium (SiGe), silicon carbide (SiC), gallium arsenide (GaAs), indium arsenide (InAs), and indium phosphide (InP). Alternatively, the substrate 110 may have a silicon-on-insulator (SOI) structure. For example, the substrate 110 may comprise a buried oxide (BOX) layer. The substrate 110 may comprise conductive regions, such as impurity-doped wells or impurity-doped structures.

[0024] Device isolation layer 116 and logic device isolation layer 115 may comprise at least one of, for example, silicon oxide, silicon nitride, and silicon oxynitride. Each of device isolation layer 116 and logic device isolation layer 115 may comprise: a single layer comprising one type of insulating layer; a double layer comprising two types of insulating layers; or a multilayer comprising a combination of at least three types of insulating layers. However, embodiments are not limited thereto. For example, logic device isolation layer 115 may comprise multiple layers consisting of a first device isolation layer 115A, a second device isolation layer 115B, and a third device isolation layer 115C respectively comprising oxide, nitride, and oxide, and device isolation layer 116 may comprise multiple layers consistent with or similar to logic device isolation layer 115. Multiple active regions 118 can be defined in the substrate 110 of the memory cell region CR (refer to FIG1) by means of device isolation layer 116, and multiple logic active regions 117 can be defined in the substrate 110 of the peripheral circuit region PR (refer to FIG1) by means of logic device isolation layer 115.

[0025] In the substrate 110, a portion of a plurality of active regions 118 and their adjacent portions are configured as memory cell regions CR, and a portion of a plurality of logic active regions 117 and their adjacent portions are configured as peripheral circuit regions PR. A plurality of bit lines BL can be configured in the memory cell regions CR, and a plurality of gate line patterns GLP can be configured in the peripheral circuit regions PR.

[0026] In some embodiments, device isolation layer 116 and logic device isolation layer 115 may be formed together and may be referred to as a device isolation structure. Device isolation layer 116 may define a plurality of active regions 118 in the device isolation structure, and logic device isolation layer 115 may define a plurality of logical active regions 117 in the device isolation structure. The device isolation structure at the boundary between memory cell region CR and peripheral circuit region PR may be device isolation layer 116 or logic device isolation layer 115, and device isolation layer 116 and logic device isolation layer 115 may not be clearly distinguished from each other at the boundary between memory cell region CR and peripheral circuit region PR.

[0027] Each of the plurality of active regions 118 may be presented in a planar view as an elongated island with a minor axis and a major axis, as shown in the plurality of active regions ACT in Figure 1. Each of the plurality of logical active regions 117 may be presented in a rectangular form in a planar view, as shown in the plurality of logical active regions ACTP in Figure 1. However, the embodiments are not limited to this, and each of the plurality of logical active regions 117 may be presented in the form of various planes.

[0028] In some embodiments, the uppermost end of the logic device isolation layer 115 may be at a higher level than the main surface or top surface of the substrate 110. The top surface of the first device isolation layer 115A of the logic device isolation layer 115 may be at the same level as the main surface or top surface of the substrate 110, the top surface of the third device isolation layer 115C may be at a higher level than the main surface or top surface of the substrate 110, and the top surface of the second device isolation layer 115B may be at a level between the top surface of the first device isolation layer 115A and the top surface of the third device isolation layer 115C. However, the embodiments are not limited thereto. For example, in the logic device isolation layer 115, a portion of the top surface adjacent to the substrate 110 may be substantially at the same level as the main surface or top surface of the substrate 110. A portion of the top surface of the logic device isolation layer 115 spaced apart from the substrate 110 may be at a higher level than the main surface or top surface of the substrate 110.

[0029] The level indicates the height in the vertical direction (Z direction) perpendicular to the main surface or top surface of the substrate 110. That is, the heights in the vertical direction (Z direction) perpendicular to the main surface or top surface of the substrate 110 are the same or constant for the same level or a certain level, and the heights in the higher / lower levels are higher / lower for the vertical direction (Z direction) perpendicular to the main surface or top surface of the substrate 110.

[0030] Multiple character line trenches 120T may be formed in the substrate 110. The multiple character line trenches 120T may extend parallel to each other in a first horizontal direction (X direction) and may be in the form of lines intersecting multiple active regions 118 and spaced apart from each other at substantially equal intervals in a second horizontal direction (Y direction). In some embodiments, steps may be formed on the bottom surface of the multiple character line trenches 120T. In some embodiments, the device isolation layer 116 and the substrate 110 may be etched using a single etching process with the multiple character line trenches 120T, such that the device isolation layer 116 and the substrate 110 are etched at different etching depths. In some embodiments, the device isolation layer 116 and the substrate 110 may be etched together with each other using the multiple character line trenches 120T, such that the device isolation layer 116 and the substrate 110 are etched at different etching depths due to differences in etching rates between the device isolation layer 116 and the substrate 110.

[0031] Multiple gate dielectric layers 122, multiple word lines 120, and multiple embedded insulating layers 124 may be sequentially formed in multiple word line trenches 120T. The multiple word lines 120 may respectively constitute multiple word lines WL as shown in FIG. 1. The multiple word lines 120 may extend parallel to each other in a first horizontal direction (X direction) and may be in the form of lines intersecting multiple active regions 118 and spaced apart from each other at substantially equal intervals in a second horizontal direction (Y direction). The top surface of each of the multiple word lines 120 may be at a lower level than the top surface of the substrate 110. The bottom surface of the multiple word lines 120 may be uneven, and saddle-shaped fin field-effect transistors (FETs) may be formed in the multiple active regions 118.

[0032] Each of the plurality of character lines 120 may have a stacked structure comprising a lower character line layer 120a and an upper character line layer 120b. For example, the lower character line layer 120a may comprise a metallic material, a conductive metal nitride, or a combination thereof. In some embodiments, the lower character line layer 120a may comprise titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), tungsten (W), tungsten nitride (WN), titanium silicon nitride (TiSiN), tungsten silicon nitride (WSiN), or a combination thereof. For example, the upper character line layer 120b may comprise doped polycrystalline silicon. In some embodiments, the lower character line layer 120a may comprise a core layer or a barrier layer disposed between the core layer and each of the plurality of gate dielectric layers 122. For example, the core layer may contain a metallic material or a conductive metal nitride, such as W, WN, TiSiN or WSiN, and the barrier layer may contain a metallic material or a conductive metal nitride, such as Ti, TiN, Ta or TaN.

[0033] In some embodiments, before or after the formation of the plurality of character lines 120, impurity ions may be implanted into the plurality of active regions 118 of the substrate 110 on both sides of the plurality of character lines 120 to form source regions and drain regions in the plurality of active regions 118.

[0034] The gate dielectric layer 122 may comprise at least one of the following: silicon oxide, silicon nitride, silicon oxynitride, oxide / nitride / oxide (ONO), and a high-k dielectric having a dielectric constant greater than that of silicon oxide. For example, each of the plurality of gate dielectric layers 122 may have a dielectric constant of about 10 to about 25. In some embodiments, the plurality of gate dielectric layers 122 may comprise at least one material selected from the following: hafnium oxide (HfO), hafnium silicate (HfSiO), hafnium oxynitride (HfON), hafnium silicon oxynitride (HfSiON), lanthanum oxide (LaO), aluminum lanthanum oxide (LaAlO), zirconium oxide (ZrO), zirconium silicate (ZrSiO), zirconium oxynitride (ZrON), zirconium silicon oxynitride (ZrSiON), tantalum oxide (TaO), titanium oxide (TiO), barium strontium titanium oxide (BaSrTiO), barium titanium oxide (BaTiO), strontium titanium oxide (SrTiO), yttrium oxide (YO), aluminum oxide (AlO), and lead scandium tantalum oxide (PbScTaO). For example, the plurality of gate dielectric layers 122 may comprise HfO 2, Al 2O 3, HfAlO 3, Ta 2O 3, or TiO 2.

[0035] The top surface of each of the plurality of embedded insulating layers 124 may be at substantially the same layer level as the top surface of the substrate 110. The plurality of embedded insulating layers 124 may comprise at least one material selected from the following: silicon oxide, silicon nitride, silicon oxynitride, and combinations thereof.

[0036] Referring to Figures 3A to 3E, a cover device isolation layer 116, a plurality of active regions 118, and a plurality of embedded insulating layers 124 are formed, including a first insulating layer pattern 112 and a second insulating layer pattern 114. The first insulating layer pattern 112 and the second insulating layer pattern 114 may further cover at least a portion of the logic device isolation layer 115 and at least a portion of the plurality of logic active regions 117. For example, the first insulating layer pattern 112 and the second insulating layer pattern 114 may cover a portion of the logic device isolation layer 115 and may not cover the remaining portion of the logic device isolation layer 115. In some embodiments, the first insulating layer pattern 112 and the second insulating layer pattern 114 may cover a portion of the logic device isolation layer 115 adjacent to the memory cell region CR and may not cover the remaining portion of the logic device isolation layer 115.

[0037] For example, the first insulating layer pattern 112 and the second insulating layer pattern 114 may comprise silicon oxide, silicon nitride, silicon oxynitride, a metallic dielectric, or a combination thereof. In some embodiments, the first insulating layer pattern 112 and the second insulating layer pattern 114 may be formed by stacking multiple insulating layers. In some embodiments, the first insulating layer pattern 112 may comprise silicon oxide, and the second insulating layer pattern 114 may comprise silicon oxynitride.

[0038] In some embodiments, the first insulating layer pattern 112 may include a non-metallic dielectric layer, and the second insulating layer pattern 114 may include a metallic dielectric layer. For example, the first insulating layer pattern 112 may include silicon oxide, silicon nitride, silicon oxynitride, or a combination thereof. For example, the second insulating layer pattern 114 may include at least one material selected from the following: hafnium oxide (HfO), hafnium silicate (HfSiO), hafnium oxynitride (HfON), hafnium silicate oxynitride (HfSiON), lanthanum oxide (LaO), aluminum lanthanum oxide (LaAlO), zirconium oxide (ZrO), zirconium silicate (ZrSiO), zirconium oxynitride (ZrON), zirconium silicate oxynitride (ZrSiON), tantalum oxide (TaO), titanium oxide (TiO), barium strontium titanium oxide (BaSrTiO), barium titanium oxide (BaTiO), strontium titanium oxide (SrTiO), yttrium oxide (YO), aluminum oxide (AlO), and lead scandium tantalum oxide (PbScTaO).

[0039] Next, a plurality of direct contact holes 134H are formed through the first insulating layer pattern 112 and the second insulating layer pattern 114 to expose the source regions in the plurality of active regions 118. In some embodiments, the plurality of direct contact holes 134H may extend into the plurality of active regions 118, i.e., into the source regions.

[0040] Referring to Figures 4A to 4E, a conductive semiconductor layer 132P is formed covering a substrate 110 on which a first insulating layer pattern 112 and a second insulating layer pattern 114 are formed, and a direct contact conductive layer 134P is filled with a plurality of direct contact holes 134H.

[0041] For example, the conductive semiconductor layer 132P may comprise doped polycrystalline silicon. For example, the direct contact conductive layer 134P may comprise Si, Ge, W, WN, cobalt (Co), nickel (Ni), Al, molybdenum (Mo), ruthenium (Ru), Ti, TiN, Ta, TaN, copper (Cu), or combinations thereof. In some embodiments, the direct contact conductive layer 134P may comprise an epitaxial silicon layer. In some embodiments, the direct contact conductive layer 134P may comprise doped polycrystalline silicon.

[0042] In some embodiments, the conductive semiconductor layer 132P and the direct contact conductive layer 134P may be formed together with each other. The conductive semiconductor layer 132P may cover the first insulating layer pattern 112 and the second insulating layer pattern 114, and the direct contact conductive layer 134P may be disposed in a plurality of direct contact holes 134H to fill the plurality of direct contact holes 134H.

[0043] In other embodiments, referring to Figures 3A to 4E, a conductive semiconductor layer 132P is first formed, which covers a substrate 110 on which a first insulating layer pattern 112 and a second insulating layer pattern 114 are formed. Then, a plurality of direct contact holes 134H are formed through the conductive semiconductor layer 132P and the first and second insulating layer patterns 112 and 114 to expose the source regions in a plurality of active regions 118. A direct contact conductive layer 134P filling the plurality of direct contact holes 134H can be formed. For example, the top surface of the conductive semiconductor layer 132P and the top surface of the direct contact conductive layer 134P may be at the same level.

[0044] Referring to Figures 5A to 5E, a protective mask layer 136 is formed that covers the conductive semiconductor layer 132P and directly contacts the conductive layer 134P. For example, the protective mask layer 136 may contain an oxide.

[0045] Referring to Figure 6, a first mask pattern MK1 having a first mask opening MKH1 is formed on a protective mask layer 136. For example, the first mask pattern MK1 may include a photoresist or a rigid mask layer.

[0046] The first masking opening MKH1 may be located above the logic device isolation layer 115 (i.e., along the vertical direction Z). For example, the first masking opening MKH1 may vertically overlap with portions of the first insulating layer pattern 112 and the second insulating layer pattern 114 located on the logic device isolation layer 115.

[0047] Referring to Figures 6 and 7, a first separation opening 130H is formed by removing portions of the protective mask layer 136, the conductive semiconductor layer 132P, and the first insulating layer pattern 112 and the second insulating layer pattern 114 using a first mask pattern MK1 as an etching mask. The logic device isolation layer 115 is exposed through the bottom surface of the first separation opening 130H. The first separation opening 130H may overlap with the logic device isolation layer 115.

[0048] In some embodiments, the first separation opening 130H may extend through the protective shielding layer 136, the conductive semiconductor layer 132P, and the first insulating layer pattern 112 and the second insulating layer pattern 114 into the upper portion of the logic device isolation layer 115, such that the bottom surface of the first separation opening 130H is at a lower level than the uppermost end of the logic device isolation layer 115.

[0049] After the first separation opening 130H is formed, the first mask pattern MK1 can be removed.

[0050] Referring to FIG8, a cover insulating layer 138 is formed covering the protective shield layer 136 and filling the first separation opening 130H. The portion of the cover insulating layer 138 filling the first separation opening 130H may be referred to as the cover insulating structure 138P. For example, the cover insulating layer 138 may contain a nitride. In some embodiments, the bottom surface of the cover insulating structure 138P may be at a lower level than the uppermost end of the logic device isolation layer 115. For example, the cover insulating structure 138P may extend through the protective shield layer 136, the conductive semiconductor layer 132P, and the first insulating layer pattern 112 and the second insulating layer pattern 114 into the upper portion of the logic device isolation layer 115.

[0051] Referring to Figures 8 and 9, a portion of the top surface of the protective cover layer 136 covering the insulating layer 138 is removed, leaving the insulating cover structure 138P filling the first separation opening 130H intact. In some embodiments, the portion of the top surface of the protective cover layer 136 covering the insulating layer 138 can be removed by performing a chemical mechanical polishing (CMP) process.

[0052] Referring to Figures 9 and 10, the protective mask layer 136 is removed. Because the protective mask layer 136 is removed, the covering insulating structure 138P protrudes above the top surface of the conductive semiconductor layer 132P.

[0053] Referring to FIG11, a first conductive metal layer 145 is formed on the conductive semiconductor layer 132P and the overlay insulating structure 138P. The first conductive metal layer 145 conformally covers the conductive semiconductor layer 132P and the overlay insulating structure 138P. For example, the first conductive metal layer 145 may comprise TiN or Ti-Si-N (TSN). In some embodiments, the first conductive metal layer 145 may act as a diffusion barrier.

[0054] Referring to Figure 12, a second conductive metal layer 146 is formed on the first conductive metal layer 145. The second conductive metal layer 146 may be thicker than the first conductive metal layer 145. For example, the second conductive metal layer 146 may contain W or tungsten silicon (WSi x).

[0055] Referring to Figures 12 and 13, a portion of the first conductive metal layer 145 and a portion of the second conductive metal layer 146 are removed, exposing the overlay insulating structure 138P. For example, a portion of the first conductive metal layer 145 and a portion of the second conductive metal layer 146 can be removed by performing a CMP process or an etch-back process.

[0056] The uppermost end of the covering insulating structure 138P, the uppermost end of the first metal conductive layer 145, and the uppermost end of the second metal conductive layer 146 may be on the same layer. The first metal conductive layer 145 may partially cover the side surface of the covering insulating structure 138P. The second metal conductive layer 146 may be spaced apart from the covering insulating structure 138P by the first metal conductive layer 145 therebetween. The first metal conductive layer 145 may cover the side surface of the second metal conductive layer 146 facing the side surface of the covering insulating structure 138P.

[0057] Referring to FIG. 14, a first insulating cover layer 148A is formed covering the insulating structure 138P, the first conductive metal layer 145, and the second conductive metal layer 146. In some embodiments, the first insulating cover layer 148A may contain the same material as the insulating structure 138P. For example, the first insulating cover layer 148A may contain a nitride.

[0058] Referring to Figure 15, a second mask pattern MK2 having a second mask opening MKH2 is formed on the first insulating cover layer 148A. For example, the second mask pattern MK2 may include a photoresist or a rigid mask layer.

[0059] The second masking opening MKH2 may be located above the logic device isolation layer 115 (i.e., along the vertical direction Z). For example, the second masking opening MKH2 may perpendicularly overlap with a portion of the overlay insulation structure 138P. The second masking opening MKH2 may be located further away from the plurality of active regions 118 than the overlay insulation structure 138P. For example, the second masking opening MKH2 may not perpendicularly overlap with a portion of the overlay insulation structure 138P that is close to the plurality of active regions 118, and may perpendicularly overlap with a portion of the overlay insulation structure 138P that is farther away from the plurality of active regions 118. The second masking opening MKH2 may perpendicularly overlap with a portion of the logic device isolation layer 115 adjacent to a side surface of the overlay insulation structure 138P relative to the plurality of active regions 118, but not perpendicularly overlap with the overlay insulation structure 138P.

[0060] Referring to Figures 15 and 16, a second separation opening 148H is formed by removing portions of the first insulating cover layer 148A, the second conductive metal layer 146, the first conductive metal layer 145, the covering insulating structure 138P, and the conductive semiconductor layer 132P using a second mask pattern MK2 as an etching mask. A portion of the logic device isolation layer 115 and a portion of the covering insulating structure 138P are exposed through the bottom surface of the second separation opening 148H. The bottom surface of the second separation opening 148H may be at a higher level than the bottom surface of the covering insulating structure 138P. The second separation opening 148H may be above a portion of the logic device isolation layer 115 and a portion of the covering insulating structure 138P (i.e., along the vertical direction Z). The bottom surface of the second separation opening 148H may be partially formed by the logic device isolation layer 115 and the covering insulating structure 138P.

[0061] After the second separation opening 148H is formed, the second mask pattern MK2 can be removed.

[0062] The first metal conductive layer 145 may cover the side surface of the second metal conductive layer 146 extending from the memory cell region CR (refer to FIG. 1) to the logic device isolation layer 115, and may not cover the side surface of the second metal conductive layer 146 extending from the peripheral circuit region PR (refer to FIG. 1) to the logic device isolation layer 115. The second metal conductive layer 146 extending from the memory cell region CR (refer to FIG. 1) to the logic device isolation layer 115 may be a part of each of a plurality of bit lines BL (refer to FIG. 1), and the second metal conductive layer 146 extending from the peripheral circuit region PR (refer to FIG. 1) to the logic device isolation layer 115 may be a part of each of a plurality of gate line patterns GLP (refer to FIG. 1).

[0063] Referring to Figures 17A to 17E, a first end spacer 172 and a second end spacer 174 are formed to sequentially cover the side surface of the second separation opening 148H, and a second insulating cover layer 148B is formed to cover the first insulating cover layer 148A and the second end spacer 174. For example, the first end spacer 172 may contain a nitride, and the second end spacer 174 may contain an oxide. For example, the second insulating cover layer 148B may contain a nitride. The second end spacer 174 may be thicker than the first end spacer 172. The second insulating cover layer 148B may be thinner than the second end spacer 174. In some embodiments, the second insulating cover layer 148B may conformally cover portions of the following: the top surface of the first insulating cover layer 148A, the surface of the second end spacer 174 opposite to the side surface of the second separation opening 148H, the surface of the covering insulating structure 138P exposed at the bottom surface of the second separation opening 148H, and the top surface of the logic device isolation layer 115 exposed at the bottom surface of the second separation opening 148H.

[0064] A logic fill layer 176 filling the second separation opening 148H is formed on the second insulating cover layer 148B. For example, the logic fill layer 176 may comprise an oxide. In some embodiments, the uppermost end of the second insulating cover layer 148B and the uppermost end of the logic fill layer 176 may be at the same level. For example, after forming a preliminary fill material layer that fills the second separation opening 148H and covers the second insulating cover layer 148B, the upper portion of the preliminary fill material layer is removed to expose the second insulating cover layer 148B, thereby forming the logic fill layer 176.

[0065] A third insulating cap layer 148C may be formed on the logic fill layer 176 and the second insulating cap layer 148B. For example, the third insulating cap layer 148C may contain a nitride. The stacked structure including the first insulating cap layer 148A, the second insulating cap layer 148B, and the third insulating cap layer 148C may be referred to as an insulating cap structure 148. The second insulating cap layer 148B may be thinner than each of the first insulating cap layer 148A and the third insulating cap layer 148C.

[0066] Referring to Figures 17A to 17E and 18A to 18E, a first conductive metal layer 145, a second conductive metal layer 146, and an insulating cap structure 148 are etched to form a plurality of bit lines 147 in the form of lines, each having a stacked structure comprising the first conductive metal layer 145, the second conductive metal layer 146, and the plurality of insulating cap structures 148 in the form of lines. For example, the first conductive metal layer 145, the second conductive metal layer 146, and the insulating cap structure 148 are etched using a mask pattern covering the insulating cap structure 148 as an etching mask. After the plurality of bit lines 147 are formed, the mask pattern can be removed. The plurality of bit lines 147 and the plurality of insulating cap structures 148 covering their respective bit lines 147 can each constitute a bit line structure 140. Multiple bit line structures 140, each including bit line 147 and insulating cover structure 148, can extend parallel to each other in a second horizontal direction (Y direction) parallel to the main surface of the substrate 110.

[0067] Multiple bit lines 147 can respectively constitute multiple bit lines BL shown in FIG1. ​​In some embodiments, during the formation of multiple bit line structures 140, conductive semiconductor layer 132P and multiple bit line structures 140 can be etched together to form multiple conductive semiconductor patterns 132 between the first insulating layer pattern 112 and the second insulating layer pattern 114 and the first metal conductive layer 145.

[0068] In the etching process used to form multiple bit line structures 140, the cover insulating structure 138P can also be etched and separated into multiple pieces. The multiple bit line structures 140 may include multiple cover insulating structures 138P. The cover insulating structure 138P may cover the side surface of the end of the bit line 147 and may form a line shape together with the bit line 147 and the insulating cover structure 148 as part of the bit line structure 140. For example, the bit line structure 140 may include a first insulating cover layer 148A in the form of a line, a portion of a second insulating cover layer 148B and a portion of a third insulating cover layer 148C on the first insulating cover layer 148A, the bit line 147 below the first insulating cover layer 148A, and the cover insulating structure 138P.

[0069] The bit line structure 140 may extend along a plurality of active regions 118 and a device isolation layer 116. In some embodiments, the bit line structure 140 may extend onto a logic device isolation layer 115. For example, the end of the bit line structure 140 may be located on the logic device isolation layer 115.

[0070] In the etching process used to form multiple bit line structures 140, a portion of the direct contact conductive layer 134P that does not perpendicularly overlap with the bit lines 147 can be removed by the etching process to form multiple direct contact conductive patterns 134. In this case, in the etching process forming multiple bit lines 147 and multiple direct contact conductive patterns 134, the first insulating layer pattern 112 and the second insulating layer pattern 114 can act as etching stop layers. The multiple direct contact conductive patterns 134 can respectively constitute multiple direct contacts DC as shown in FIG. 1. The multiple bit lines 147 can be electrically connected to multiple active regions 118 via the multiple direct contact conductive patterns 134.

[0071] Multiple insulating spacer structures 150 may cover the sidewalls of multiple bitline structures 140. Each of the multiple insulating spacer structures 150 may include a first insulating spacer 152, a second insulating spacer 154, and a third insulating spacer 156. The second insulating spacer 154 may contain a material having a lower dielectric constant than the first insulating spacer 152 and the third insulating spacer 156. In some embodiments, the first insulating spacer 152 and the third insulating spacer 156 may contain nitrides, and the second insulating spacer 154 may contain an oxide. In some embodiments, the first insulating spacer 152 and the third insulating spacer 156 may contain nitrides, and the second insulating spacer 154 may contain a material having etch selectivity relative to the first insulating spacer 152 and the third insulating spacer 156. For example, when the first insulating spacer 152 and the third insulating spacer 156 contain nitrides, the second insulating spacer 154 may contain an oxide and may be removed in a subsequent process to become an air spacer.

[0072] Multiple embedded contact holes 170H may be formed in multiple bit lines 147. The internal space of each of the multiple embedded contact holes 170H may be limited by an insulating spacer structure 150, which covers the sidewalls of two adjacent bit lines 147 between two adjacent bit lines 147 and the active region 118.

[0073] A plurality of buried contact holes 170H can be formed by using a plurality of insulating cover structures 148 and a plurality of insulating spacer structures 150 covering the sidewalls of a plurality of bit line structures 140 as an etching mask to remove portions of the first insulating layer pattern 112 and the second insulating layer pattern 114 and a plurality of active regions 118. In some embodiments, the plurality of buried contact holes 170H can be formed by performing an anisotropic etching process, which involves removing portions of the first insulating layer pattern 112 and the second insulating layer pattern 114 and a plurality of active regions 118 by using a plurality of insulating cover structures 148 and a plurality of insulating spacer structures 150 covering the sidewalls of a plurality of bit line structures 140 as an etching mask; and performing an isotropic etching process, which involves further removing other portions of the plurality of active regions 118 to expand the space restricted by the plurality of active regions 118.

[0074] Multiple gate line structures 140P may be formed on the logic active region 117. Each gate line structure 140P may include a gate line 147P and an insulating cover structure 148 covering the gate line 147P. The gate line structure 140P may include a first insulating cover layer 148A in the form of a line, a portion of a second insulating cover layer 148B and a portion of a third insulating cover layer 148C on the first insulating cover layer 148A, and a gate line 147P below the first insulating cover layer 148A.

[0075] Multiple gate lines 147P included in multiple gate line structures 140P can be formed together with multiple bit lines 147. That is, the gate line 147P can have a stacked structure including a first metal conductive layer 145 and a second metal conductive layer 146. The first metal conductive layer 145 and the second metal conductive layer 146 included in the bit line 147 can be referred to as the first bit line conductive layer and the second bit line conductive layer, and the first metal conductive layer 145 and the second metal conductive layer 146 included in the gate line 147P can be referred to as the first gate line conductive layer and the second gate line conductive layer. Therefore, the first bit line conductive layer and the first gate line conductive layer can be formed of the same material, and the second bit line conductive layer and the second gate line conductive layer can be formed of the same material.

[0076] In some embodiments, the gate line structure 140P may further include a conductive semiconductor pattern 132 disposed between the second insulating layer pattern 114 and the first metal conductive layer 145. A plurality of gate lines 147P may constitute a plurality of gate line patterns GLP as shown in FIG1.

[0077] The first end spacer 172 and the second end spacer 174 may sequentially cover the side surface of the end of the bit line structure 140 and the side surface of the end of the gate line structure 140P. The second insulating cover layer 148B may cover the first insulating cover layer 148A and the second end spacer 174.

[0078] Each of the plurality of bit line structures 140 extends along the active region 118 to the logic device isolation layer 115 and may have an end on the logic device isolation layer 115. Each of the plurality of gate line structures 140P extends along the logic active region 117 to the logic device isolation layer 115 and may have an end on the logic device isolation layer 115.

[0079] The ends of each of the plurality of bit lines 147 and the ends of each of the plurality of gate lines 147P may face the opposite side surface of the covering insulation structure 138P.

[0080] The end of bit line 147, the end of gate line structure 140P, the end of gate line 147P, the end of first metal conductive layer 145, and the end of second metal conductive layer 146 may face the covering insulating structure 138P.

[0081] The side surface of the end of the second metal conductive layer 146 contained in the bit line structure 140 or bit line 147 may be covered by the first metal conductive layer 145. The uppermost end of the first metal conductive layer 145 and the uppermost end of the second metal conductive layer 146 contained in the bit line structure 140 or bit line 147 may be at the same layer level. In the bit line structure 140 or bit line 147, the first metal conductive layer 145 may extend in the second horizontal direction (Y direction) to cover the bottom surface of the second metal conductive layer 146, and may extend in the vertical direction (Z direction) between the covering insulating structure 138P and the second metal conductive layer 146 to cover the side surface of the end of the second metal conductive layer 146.

[0082] The extension length of the first conductive metal layer 145 included in the bit line structure 140 or bit line 147 may be greater than the extension length of the second conductive metal layer 146. For example, the end side surface of the first conductive metal layer 145 included in the bit line structure 140 or bit line 147 may extend further toward the covering insulating structure 138P than the end side surface of the second conductive metal layer 146. That is, the end of the first conductive metal layer 145 included in the bit line structure 140 or bit line 147 may protrude from the end side surface of the second conductive metal layer 146 toward the covering insulating structure 138P. For example, the end side surface of the first conductive metal layer 145 included in the bit line structure 140 or bit line 147 may contact the side surface of the covering insulating structure 138P.

[0083] The overlay insulating structure 138P may be located between the bit line 147 and the first end spacer 172. The second metal conductive layer 146 contained in the bit line 147 may be spaced apart from the overlay insulating structure 138P by the first metal conductive layer 145 therebetween.

[0084] The end side surface of the second metal conductive layer 146 contained in the gate line structure 140P or gate line 147P may not be covered by the first metal conductive layer 145. The end side surface of the second metal conductive layer 146 contained in the gate line structure 140P or gate line 147P may be covered by the first end spacer 172. The uppermost end of the first metal conductive layer 145 contained in the gate line structure 140P or gate line 147P may be at a lower level than the uppermost end of the second metal conductive layer 146, and the uppermost end of the second metal conductive layer 146 may be at the same level as the uppermost end of the gate line 147P.

[0085] The extension length of the first metal conductive layer 145 included in the gate line structure 140P or the gate line 147P may be substantially the same as the extension length of the second metal conductive layer 146. For example, the side surface of the end of the first metal conductive layer 145 included in the gate line structure 140P or the gate line 147P may be aligned with the side surface of the end of the second metal conductive layer 146 in the vertical direction.

[0086] Referring to Figures 19A to 19E, a plurality of embedded contacts 170 and a plurality of insulating barriers 180 are formed in the space of a plurality of insulating spacer structures 150 covering the sidewalls of a plurality of bit line structures 140. Along a pair of insulating spacer structures 150 facing each other, i.e., in the second horizontal direction (Y direction), the plurality of embedded contacts 170 and the plurality of insulating barriers 180 may be alternately arranged. For example, the plurality of embedded contacts 170 may comprise polycrystalline silicon. For example, the plurality of insulating barriers 180 may comprise nitrides.

[0087] In some embodiments, a plurality of embedded contacts 170 may be arranged in a row in a first horizontal direction (X direction) and a second horizontal direction (Y direction). Each of the plurality of embedded contacts 170 may extend from each of the plurality of active regions 118 in a vertical direction (Z direction) perpendicular to the substrate 110. The plurality of embedded contacts 170 may constitute a plurality of embedded contacts BC shown in FIG. 1.

[0088] Multiple embedded contacts 170 can be configured in a space defined by multiple insulating fences 180 and multiple insulating spacer structures 150 covering the sidewalls of multiple bit line structures 140. The multiple embedded contacts 170 can fill the lower portion of the space in the multiple insulating spacer structures 150 covering the sidewalls of each of the multiple bit line structures 140.

[0089] The top surfaces of the multiple embedded contacts 170 may be at a lower level than the top surfaces of the multiple insulating cover structures 148. The top surfaces of the multiple insulating fences 180 and the top surfaces of the multiple insulating cover structures 148 may be at the same level in the vertical direction (Z direction).

[0090] Multiple landing pad holes 190H may be limited by multiple insulating spacer structures 150 and multiple insulating fences 180. Multiple embedded contacts 170 may be exposed via the bottom surface of the multiple landing pad holes 190H.

[0091] During the formation of multiple embedded contacts 170 and / or multiple insulating barriers 180, the upper portions of multiple insulating cover structures 148 and multiple insulating spacer structures 150 contained in multiple bit line structures 140 and multiple gate line structures 140P can be removed, thereby reducing the layer hierarchy of the top surfaces of the multiple bit line structures 140 and multiple gate line structures 140P.

[0092] Referring to Figures 20A to 21B, after forming a landing pad material layer covering multiple bit line structures 140, multiple gate line structures 140P, multiple embedded contacts 170, and multiple insulating fences 180, a portion of the landing pad material layer is removed to form multiple grooves 190R and multiple landing pads 190 separated by the multiple grooves 190R.

[0093] Multiple landing pads 190 are disposed on multiple embedded contacts 170 and extend to multiple bit line structures 140. In some embodiments, the multiple landing pads 190 may extend to multiple bit lines 147. The multiple landing pads 190 may be disposed on multiple embedded contacts 170 such that the multiple embedded contacts 170 can be electrically connected to the multiple landing pads 190 respectively. The multiple landing pads 190 may be connected to multiple active regions 118 via the multiple embedded contacts 170. The multiple landing pads 190 may constitute multiple landing pads LP as shown in FIG1.

[0094] Each of the plurality of embedded contacts 170 may be configured between two adjacent bit line structures 140, and each of the plurality of landing pads 190 may extend from between two adjacent bit line structures 140 to each of the plurality of bit line structures 140, and each of the plurality of embedded contacts 170 is located between two adjacent bit line structures 140 in the plurality of bit line structures 140.

[0095] In some embodiments, each of the plurality of landing pads 190 may include a conductive barrier layer and a conductive pad material layer on the conductive barrier layer. For example, the conductive barrier layer may include a metal, a conductive metal nitride, or a combination thereof. In some embodiments, the conductive barrier layer may have a Ti / TiN stacked structure. In some embodiments, the conductive pad material layer may include W.

[0096] In some embodiments, a metal silicate layer may be formed on a plurality of embedded contacts 170 prior to the formation of the landing pad material layer. The metal silicate layer may be disposed between the plurality of embedded contacts 170 and the plurality of landing pads 190. The metal silicate layer may comprise cobalt silicate (CoSi x), nickel silicate (NiSi x), or manganese silicate (MnSi x). However, the embodiments are not limited thereto.

[0097] A semiconductor memory device 1 comprising multiple capacitor structures 200 can be formed by sequentially forming multiple lower electrodes 210, capacitor dielectric layers 220, and upper electrodes 230 on multiple landing pads 190. The multiple lower electrodes 210 can be electrically connected to the multiple landing pads 190 respectively. The capacitor dielectric layer 220 can conformally cover the multiple lower electrodes 210. The upper electrodes 230 can cover the capacitor dielectric layer 220. The upper electrodes 230 can face the multiple lower electrodes 210, and the capacitor dielectric layer 220 is located between the upper electrodes 230 and the multiple lower electrodes 210. The capacitor dielectric layer 220 and the upper electrodes 230 can be integrally formed to cover the multiple lower electrodes 210 in a certain region (e.g., memory cell region CR). The multiple lower electrodes 210 can constitute multiple storage nodes SN as shown in FIG. 1.

[0098] Each of the plurality of lower electrodes 210 may be in the form of a column with a circular horizontal cross-section. However, the embodiments are not limited thereto. In some embodiments, each of the plurality of lower electrodes 210 may be in the form of a cylinder with a closed bottom. In some embodiments, the plurality of lower electrodes 210 may be in the form of a honeycomb arranged in a zigzag pattern in a first horizontal direction (X direction) or a second horizontal direction (Y direction). In other embodiments, the plurality of lower electrodes 210 may be in the form of a matrix arranged in rows in the first horizontal direction (X direction) and the second horizontal direction (Y direction). The plurality of lower electrodes 210 may comprise, for example, a metal doped with impurities such as Si, W, or Cu, or a conductive metal compound such as TiN. The semiconductor memory device 1 may further include at least one support pattern in contact with the sidewalls of the plurality of lower electrodes 210.

[0099] The capacitor dielectric layer 220 may contain, for example, TaO, TaAlO, TaON, AlO, AlSiO, HfO, HfSiO, ZrO, ZrSiO, TiO, TiAlO, BST ((Ba,Sr)TiO), STO (SrTiO), BTO (BaTiO), PZT (Pb(Zr,Ti)O), (Pb,La)(Zr,Ti)O, Ba(Zr,Ti)O, Sr(Zr,Ti)O, or combinations thereof.

[0100] The upper electrode 230 may contain, for example, doped silicon, Ru, RuO, Pt, PtO, Ir, IrO, SRO (SrRuO), BSRO ((Ba,Sr)RuO), CRO (CaRuO), BaRuO, La (Sr,Co)O, Ti, TiN, W, WN, Ta, TaN, TiAlN, TiSiN, TaAlN, TaSiN, or combinations thereof.

[0101] Before forming the plurality of capacitor structures 200, a plurality of insulating structures 195 filling the plurality of recesses 190R may be formed. In some embodiments, each of the plurality of insulating structures 195 may include an interlayer insulating layer and an etch stop layer. For example, the interlayer insulating layer may include an oxide, and the etch stop layer may include a nitride. Figures 20A and 20C show that the top surfaces of the plurality of insulating structures 195 and the bottom surfaces of the plurality of lower electrodes 210 are at the same level. However, the embodiments are not limited thereto. For example, the top surfaces of the plurality of insulating structures 195 may be at a higher level than the bottom surfaces of the plurality of lower electrodes 210, and the plurality of lower electrodes 210 may extend toward the substrate 110 into the plurality of insulating structures 195.

[0102] The semiconductor memory device 1 may further include a plurality of contact plugs GPGs. Each of the plurality of contact plugs GPGs may include a gate line contact plug GPG1 and a bit line contact plug GPG2. The gate line contact plug GPG1 may pass through the insulating cover structure 148 to connect to the gate line 147P, and the bit line contact plug GPG2 may pass through the insulating cover structure 148 to connect to the bit line 147P. In some embodiments, the gate line contact plug GPG1 and the bit line contact plug GPG2 may pass through the insulating cover structure 148 and the second metal conductive layer 146 to connect to the first metal conductive layer 145. In other embodiments, the gate line contact plug GPG1 and the bit line contact plug GPG2 may pass through the insulating cover structure 148 to connect to the second metal conductive layer 146. The gate line contact plug GPG1 may be adjacent to the end of the gate line structure 140P, and the bit line contact plug GPG2 may be adjacent to the end of the bit line structure 140P.

[0103] Multiple logic bit lines (BLPs) may be configured on the insulating cover structure 148. Each of the gate line contact plugs GPG1 and GPG2 may be connected to at least one of the multiple logic bit lines (BLPs). In some embodiments, the gate line contact plugs GPG1 and GPG2 comprise the same material as the multiple logic bit lines (BLPs) and may be integrally formed. In some embodiments, the gate line contact plugs GPG1 and GPG2 may comprise the same material as the multiple landing pads 190.

[0104] The top surfaces of bit lines 147 and gate lines 147P, that is, the top surface of the second metal conductive layer 146, may be located at the first vertical level LV1, and the top surface of the insulating cover structure 148, that is, the top surface of the third insulating cover layer 148C, may be located at a second vertical level LV2, which is higher than the first vertical level LV1. In some embodiments, the uppermost end of the first metal conductive layer 145 may be located at the first vertical level LV1.

[0105] The buried insulating layer 250 may fill multiple logic bit lines (BLPs) corresponding to the layers where the multiple capacitor structures 200 are located. The buried insulating layer 250 may comprise, for example, an oxide or an ultra-low K (ULK) material. The oxide may comprise one of the following: borophosphosilicate glass (BPSG), phosphosilicate glass (PSG), borosilicate glass (BSG), undoped silicon glass (USG), tetraethyl orthosilicate (TEOS), and high-density plasma (HDP). The ULK material may comprise, for example, a material selected from SiOC and SiCOH, and may have an ultra-low dielectric constant K of 2.2 to 2.4.

[0106] Semiconductor memory device 1 includes: a substrate 110 having a plurality of active regions 118 and a plurality of logic active regions 117; a plurality of gate dielectric layers 122 sequentially formed in a plurality of word line trenches 120T intersecting the plurality of active regions 118 in the substrate 110; a first insulating layer pattern 112 and a second insulating layer pattern 114 covering the plurality of word lines 120, a plurality of buried insulating layers 124, a device isolation layer 116, and the plurality of active regions 118; a plurality of bit line structures 140 on the first insulating layer pattern 112 and the second insulating layer pattern 114; a plurality of insulating spacer structures 150 covering the sidewalls of the plurality of bit line structures 140; and a plurality of... The logic active region 117 includes a plurality of gate line structures 140P; a plurality of end spacers (e.g., 172 and 174) covering the sidewalls of the plurality of gate line structures 140P; a plurality of embedded contacts 170 filling the lower portion of a space defined by a plurality of insulating fences 180 and a plurality of insulating spacer structures 150 and connecting to the plurality of active regions 118; a plurality of landing pads 190 filling the upper portion of the plurality of embedded contacts 170 and extending to the upper portion of the plurality of bit line structures 140; and a plurality of capacitor structures 200 including a plurality of lower electrodes 210, a capacitor dielectric layer 220 and an upper electrode 230 connected to the plurality of landing pads 190.

[0107] Referring to Figures 20B and 20C, a pair of insulating spacer structures 150 facing each other, along the sidewalls of a plurality of insulating spacer structures 150 covering each of the plurality of bit line structures 140, i.e., in the second horizontal direction (Y direction), can be spaced apart from each other. Each of the plurality of insulating spaces 180 can extend from between each pair of a plurality of embedded contacts 170 to between each pair of a plurality of landing pads 190.

[0108] Referring to Figures 20A, 20D, 21A, and 21B, beneath a plurality of first insulating cover layers 148A extending in the form of lines in the second horizontal direction (Y direction), a plurality of stacked structures, each including a conductive semiconductor pattern 132, a first metal conductive layer 145, and a second metal conductive layer 146, can be inserted into a plurality of active regions 118 and a device isolation layer 116, and can be located on the logic device isolation layer 115 spaced apart from the ends of the plurality of first insulating cover layers 148A, and a plurality of covering insulating structures 138P can be inserted into the logic device isolation layer 115 adjacent to the ends of the plurality of first insulating cover layers 148A.

[0109] If the bit line 147 is formed by etching using the insulating cover structure 148 as an etching mask, then when the bit line 147 is disposed at the end of the bit line structure 140, a portion of the bit line 147 disposed at the end of the bit line structure 140 may be thinned or penetrated.

[0110] The semiconductor memory device 1 according to an embodiment may include a cover insulating structure 138P, at the end of which a bit line structure 140 is disposed, such that the cover insulating structure 138P covers the side surface of the end of the bit line 147. Therefore, the cover insulating structure 138P may be disposed at the end of the linear bit line structure 140. The cover insulating structure 138P may contain the same material as a portion of the insulating cover structure 148 (e.g., the first insulating cover layer 148A). Therefore, in the etching process used to form the plurality of bit line structures 140, it is possible to prevent the ends of the plurality of bit lines 147 from being thinned or penetrated.

[0111] In the semiconductor memory device 1 according to the embodiment, since the ends of the plurality of bit lines 147 are not thinned, it is possible to prevent the electrical characteristics of the plurality of bit lines 147 from deteriorating, and since the ends of the plurality of bit lines 147 are not penetrated, it is possible to prevent adjacent bit lines 147 from connecting to each other. Therefore, the electrical reliability of the semiconductor memory device 1 can be ensured.

[0112] Figures 22 and 23 are cross-sectional views illustrating a method of manufacturing a semiconductor memory device according to an embodiment, and Figures 24, 25A, and 25B are cross-sectional views illustrating a semiconductor memory device according to an embodiment. Specifically, Figures 22, 23, and 24 are cross-sectional views taken along line E-E' of Figure 1, Figure 25A is a cross-sectional view taken along line XXVa-XXVa' of Figure 24, and Figure 25B is a cross-sectional view taken along line XXVb-XXVb' of Figure 24.

[0113] Referring to FIG22, in the results of FIG13, a portion of the first conductive metal layer 145 between the second conductive metal layer 146 and the covering insulating structure 138P is selectively removed to form a removal space 145G and a first separation opening 130H. In some embodiments, the conductive semiconductor layer 132P may be exposed via the bottom surface of the removal space 145G and the bottom surface of the first separation opening 130H.

[0114] Referring to Figure 23, a first insulating cover layer 148A is formed that covers the insulating structure 138P and the second metallic conductive layer 146 and fills the removal space 145G and the first separation opening 130H. A portion of the filling removal space 145G of the first insulating cover layer 148A may be referred to as the filling cover layer 148AP.

[0115] The filler cover layer 148AP can cover the side surface of the insulating structure 138P. The first conductive metal layer 145 and the second conductive metal layer 146 can be spaced apart from the insulating structure 138P by the filler cover layer 148AP therebetween. The filler cover layer 148AP can cover the side surfaces of the first conductive metal layer 145 and the second conductive metal layer 146 facing the side surface of the insulating structure 138P.

[0116] Referring to Figures 24, 25A and 25B, in the results of Figure 23, the semiconductor memory device 2 can be formed by performing subsequent processes as shown in Figures 14 to 21B.

[0117] In the semiconductor memory device 1 shown in Figures 20A to 21B, the second metal conductive layer 146 and the covering insulating structure 138P are spaced apart from each other by the first metal conductive layer 145 therebetween. Since the semiconductor memory device 2 is substantially the same as the first semiconductor memory device 1, except that the second metal conductive layer 146 and the covering insulating structure 138P are spaced apart from each other by the filling cover layer 148AP therebetween, which is part of the first insulating cover layer 148A, the description previously given with reference to Figures 20A to 21B will not be given.

[0118] The semiconductor memory device 2 may include a bit line structure 140, which includes a first insulating cap layer 148A in the form of a line, a portion of a second insulating cap layer 148B and a portion of a third insulating cap layer 148C on the first insulating cap layer 148A, a bit line 147 below the first insulating cap layer 148A, and a cover insulating structure 138P. The bit line 147 may have a stacked structure including a first metal conductive layer 145 and a second metal conductive layer 146. The bit line 147 may be spaced apart from the cover insulating structure 138P. A portion of the first insulating cap layer 148A (i.e., a fill cap layer 148AP) may be located between the bit line 147 and the cover insulating structure 138P. The first metal conductive layer 145 may be spaced apart from the cover insulating structure 138P by the fill cap layer 148AP therebetween, and the second metal conductive layer 146 may be spaced apart from the cover insulating structure 138P by the fill cap layer 148AP therebetween.

[0119] Figures 26 to 30 are cross-sectional views illustrating a method of manufacturing a semiconductor memory device according to an embodiment, and Figures 31A to 31E, 32A, and 32B are cross-sectional views illustrating a semiconductor memory device according to an embodiment. Specifically, Figure 31A is a cross-sectional view taken along line A-A' of Figure 1, Figure 31B is a cross-sectional view taken along line B-B' of Figure 1, Figure 31C is a cross-sectional view taken along line C-C' of Figure 1, Figure 31D is a cross-sectional view taken along line D-D' of Figure 1, Figures 26 to 30 and Figure 31E are cross-sectional views taken along line E-E' of Figure 1, Figure 32A is a cross-sectional view taken along line XXXIIa-XXXIIa' of Figure 31E, and Figure 32B is a cross-sectional view taken along line XXXIIb-XXXIIb' of Figure 31E.

[0120] Referring to FIG26, a base capping layer 149 is formed on the second metallic conductive layer 146 shown in FIG12. For example, the base capping layer 149 may contain a nitride.

[0121] Referring to Figures 26 and 27, a portion of the base capping layer 149 and a portion of the second conductive metal layer 146 are removed, exposing the first conductive metal layer 145. For example, a portion of the base capping layer 149 and a portion of the second conductive metal layer 146 can be removed by performing a CMP process or an etch-back process.

[0122] The uppermost end of the first metal conductive layer 145, the uppermost end of the second metal conductive layer 146, and the top surface of the base cover layer 149 can be at the same level.

[0123] Next, a first insulating cover layer 148A is formed covering the first metal conductive layer 145, the second metal conductive layer 146, and the base cover layer 149. In some embodiments, the first insulating cover layer 148A may contain the same material as the base cover layer 149. For example, the first insulating cover layer 148A may contain a nitride.

[0124] Referring to Figure 28, a second mask pattern MK2 with a second mask opening MKH2 is formed on the first insulating cover layer 148A.

[0125] Referring to Figures 28 and 29, by using the second mask pattern MK2 as an etching mask, portions of the first insulating cover layer 148A, the base cover layer 149, the second conductive metal layer 146, the first conductive metal layer 145, the covering insulating structure 138P, and the conductive semiconductor layer 132P are removed to form a second separation opening 148H. A portion of the logic device isolation layer 115 and a portion of the covering insulating structure 138P are exposed through the bottom surface of the second separation opening 148H. After forming the second separation opening 148H, the second mask pattern MK2 can be removed.

[0126] Referring to FIG. 30, after forming the first end spacer 172 and the second end spacer 174 to sequentially cover the side surface of the second separation opening 148H, a second insulating cover layer 148B is formed to cover the first insulating cover layer 148A and the second end spacer 174. Next, a logic fill layer 176 filling the second separation opening 148H is formed on the second insulating cover layer 148B. A third insulating cover layer 148C may be formed on the logic fill layer 176 and the second insulating cover layer 148B.

[0127] Referring to Figures 31A to 32B, in the results of Figure 30, a semiconductor memory device 3 can be formed by performing subsequent processes as shown in Figures 18A to 21B.

[0128] In the semiconductor memory device 1 shown in Figures 20A to 21B, the first metal conductive layer 145 covers only a portion of the side surface of the insulating structure 138P. Since the semiconductor memory device 3 is substantially the same as the first semiconductor memory device 1, except that the first metal conductive layer 145 covers a portion of the side surface of the insulating structure 138P and the top surface of the insulating structure 138P, the description previously given with reference to Figures 20A to 21B will not be provided.

[0129] The first conductive metal layer 145 may extend from between the covering insulating structure 138P and the second conductive metal layer 146 to between the first insulating cover layer 148A and the covering insulating structure 138P. In some embodiments, the first conductive metal layer 145 may cover the entire top surface of the covering insulating structure 138P. The base cover layer 149 may be located between the second conductive metal layer 146 and the first insulating cover layer 148A.

[0130] The uppermost end of the first metal conductive layer 145 and the uppermost end of the second metal conductive layer 146 may be at the same level. The uppermost end of the covering insulating structure 138P may be at a lower level than the uppermost ends of the first metal conductive layer 145 and the second metal conductive layer 146.

[0131] Since the first insulating cover layer 148A contains the same material as the base cover layer 149, the base cover layer 149 and the first insulating cover layer 148A included in the semiconductor memory device 3 shown in Figures 31A to 32B can perform substantially the same function as the first insulating cover layer 148A included in the semiconductor memory device 1 shown in Figures 20A to 21B. That is, the lower portion of the first insulating cover layer 148A included in the semiconductor memory device 1 shown in Figures 20A to 21B can correspond to the base cover layer 149 included in the semiconductor memory device 3 shown in Figures 31A to 32B, and the remaining upper portion of the first insulating cover layer 148A included in the semiconductor memory device 1 shown in Figures 20A to 21B can correspond to the first insulating cover layer 148A included in the semiconductor memory device 3 shown in Figures 31A to 32B.

[0132] Referring to Figures 31A, 31B, 32A, and 32B, beneath a plurality of first insulating cover layers 148A extending in the form of lines in the second horizontal direction (Y direction), a plurality of stacked structures, each comprising a conductive semiconductor pattern 132, a first conductive metal layer 145, a second conductive metal layer 146, and a base cover layer 149, can be inserted onto a plurality of active regions 118 and a device isolation layer 116, and can be located on a logic device isolation layer 115 spaced apart from the ends of the plurality of first insulating cover layers 148A. Furthermore, a plurality of covering insulating structures 138P and the first conductive metal layer 145 can be inserted into the logic device isolation layer 115 adjacent to the ends of the plurality of first insulating cover layers 148A.

[0133] Although various embodiments have been specifically illustrated and described, it should be understood that various changes in form and detail may be made therein without departing from the spirit and scope of the appended claims.

[0134] 1, 2, 3: Semiconductor memory devices 110: Base 112: Pattern of the first insulating layer 114: Pattern of the second insulating layer 115: Logic device isolation layer 115A: First device isolation layer 115B: Second device isolation layer 115C: Third device isolation layer 115T: Logic Device Isolation Trench 116: Device isolation layer 116T: Device isolation trench 117. ACTP: Logical Active Region 118. ACT: Active Zone 120, WL: Character Line 120a: Lower character line layer 120b: Upper character line layer 120T: Character line groove 122: Gate dielectric layer 124, 250: Embedded insulation layer 130H: First separation opening 132: Conductive semiconductor pattern 132P: Conductive semiconductor layer 134: Direct contact conductive pattern 134H: Direct contact hole 134P: Direct contact conductive layer 136: Protective masking layer 138: Covering insulation layer 138P: Covered insulation structure 140: Bitline Structure 140P: Gate-line structure 145: First metallic conductive layer 145G: Remove space 146: Second metallic conductive layer 147. BL: Bitline 147P: Gate wire 148: Insulating Cover Structure 148A: First insulating cover layer 148AP: Filler cap layer 148B: Second insulating cover layer 148C: Third insulating cover layer 148H: Second separation opening 149: Basic Cover Layer 150: Insulating spacer structure 152: First insulating spacer 154: Second insulating spacer 156: Third insulating spacer 170, BC: Embedded Contacts 170H: Embedded contact hole 172: First end spacer 174: Second end spacer 176: Logical Fill Layer 180: Insulating fence 190, LP: Landing mat 190H: Landing pad hole 190R: Groove 195: Insulation Structure 200: Capacitor Structure 210: Lower electrode 220: Capacitor dielectric layer 230: Upper electrode A-A', B-B', C-C', D-D', E-E', XXIa-XXIa', XXIb-XXIb', XXVa-XXVa', XXVb-XXVb', XXXIIa-XXXIIa', XXXIIb-XXXIIb': line BLP: Logic Bit Line CR: Memory Cell Region DC: Direct Contact GLP: Gate wire pattern GPG: Contact plug GPG1: Gate wire contact plug GPG2: Bitline Contact Plug LV1: First vertical level LV2: Second vertical level MK1: First Mask Pattern MK2: Second Mask Pattern MKH1: First mask opening MKH2: Second mask opening PR: Peripheral Circuit Area SN: Storage Node X: First horizontal direction Y: Second horizontal direction Z: Vertical direction

Claims

1. A semiconductor memory device, comprising: The substrate includes multiple active regions in the memory cell region and at least one logical active region in the peripheral circuit region; A character line extends in a first horizontal direction and is located on the plurality of active regions; a bit line structure extends in a second horizontal direction orthogonal to the first horizontal direction and is located on the plurality of active regions, and the bit line structure includes a bit line, a covering insulation structure on the side surface of the end of the bit line, and an insulating cover structure on the bit line and the covering insulation structure. And a gate line, located on the at least one logic active region, wherein the layer of the bottom surface of the covering insulation structure is lower than the layer of the bottom surface of the bit line.

2. The semiconductor memory device of claim 1, wherein the bit line has a stacked structure including a first metal conductive layer and a second metal conductive layer, and wherein the second metal conductive layer is spaced apart from the covering insulating structure.

3. The semiconductor memory device as claimed in claim 2, wherein the first metal conductive layer is disposed between the second metal conductive layer and the overlay insulating structure.

4. The semiconductor memory device as claimed in claim 3, wherein the first metal conductive layer covers the top surface of the overlay insulating structure.

5. The semiconductor memory device of claim 2, wherein the gate line has a stacked structure including a third metal conductive layer and a fourth metal conductive layer, and wherein the insulating cover structure extends between the fourth metal conductive layer and the covering insulating structure.

6. The semiconductor memory device as claimed in claim 2, further comprising: The device isolation layer defines the plurality of active regions; and a logic device isolation layer defining the at least one logic active region, wherein the bit line structure extends along the plurality of active regions and the device isolation layer to the logic device isolation layer.

7. The semiconductor memory device of claim 6, wherein the overlay insulating structure is located on the logic device isolation layer, and wherein the bottom surface of the overlay insulating structure is located between the bottom surface of the substrate and the uppermost end of the logic device isolation layer.

8. The semiconductor memory device as claimed in claim 6, wherein the uppermost end of the covering insulating structure is at the same level as the uppermost end of the second metal conductive layer.

9. The semiconductor memory device of claim 6, wherein the uppermost end of the first metal conductive layer and the uppermost end of the second metal conductive layer are at the same level.

10. The semiconductor memory device as claimed in claim 1, wherein the covering insulating structure and a portion of the insulating cover structure comprise the same material.

11. A semiconductor memory device, comprising: The substrate includes multiple active regions in the memory cell region and at least one logical active region in the peripheral circuit region; A character line extends in a first horizontal direction and is located on the plurality of active regions; a bit line structure extends in a second horizontal direction orthogonal to the first horizontal direction and is located on the plurality of active regions, and the bit line structure includes a bit line, a cover insulating structure, and an insulating cover structure, the bit line having a stacked structure including a first metal conductive layer and a second metal conductive layer, the cover insulating structure being located on the side surface of the end of the bit line and spaced apart from the second metal conductive layer, the insulating cover structure being located on the bit line and the cover insulating structure; and a gate line is located on the at least one logic active region, wherein the layer level of the bottom surface of the cover insulating structure is lower than the layer level of the bottom surface of the bit line.

12. The semiconductor memory device of claim 11, wherein the first metal conductive layer extends along the bottom surface of the second metal conductive layer and is located between the second metal conductive layer and the overlay insulating structure.

13. The semiconductor memory device of claim 11, wherein the first metal conductive layer extends from between the second metal conductive layer and the overlay insulating structure to the top surface of the overlay insulating structure.

14. The semiconductor memory device of claim 11, wherein the insulating cover structure extends between the second metal conductive layer and the covering insulating structure.

15. The semiconductor memory device of claim 11, wherein the end of the first metal conductive layer protrudes from the side surface of the end of the second metal conductive layer toward the covering insulating structure.

16. The semiconductor memory device of claim 11, wherein the first metal conductive layer is spaced apart from the covering insulating structure, and wherein the side surfaces of the end portions of the first metal conductive layer and the side surfaces of the end portions of the second metal conductive layer are aligned with each other in a vertical direction.

17. The semiconductor memory device of claim 11, further comprising an end spacer on a side surface of the end of the bit line structure, wherein the insulating cover structure has a stacked structure, the stacked structure of the insulating cover structure comprising a first insulating cover layer on the bit line, a second insulating cover layer on the first insulating cover layer and the end spacer, and a third insulating cover layer on the second insulating cover layer.

18. A semiconductor memory device, comprising: Base; The device isolation layer defines multiple active regions on the memory cell region of the substrate; A logic device isolation layer defines at least one logic active region on the peripheral circuit area of ​​the substrate; Multiple character lines in multiple character line trenches extend parallel to each other in a first horizontal direction across the multiple active regions, each of the multiple character lines having a stacked structure including a lower character line layer and an upper character line layer; multiple embedded insulating layers are located in the multiple character line trenches on the multiple character lines; multiple bit line structures are located on the multiple active regions and extend parallel to each other in a second horizontal direction orthogonal to the first horizontal direction, each of the multiple bit line structures including: a bit line having a stacked structure including a first bit line conductive layer and a second bit line conductive layer; A covering insulating structure is located on the side surface of the end of the bit line and spaced apart from the first bit line conductive layer therebetween; and an insulating cover structure is located on the bit line and the covering insulating structure and has a stacked structure including a first insulating cover layer, a second insulating cover layer and a third insulating cover layer; a gate line is located on the at least one logic active region and has a stacked structure including a first gate line conductive layer and a second gate line conductive layer, the first gate line conductive layer and the first bit line conductive layer comprising a first identical material, and the second bit line conductive layer and the second gate line conductive layer comprising a second identical material; a plurality of embedded contacts are located in the space of the plurality of bit line structures and connected to the plurality of active regions; a plurality of landing pads are located in the space of the plurality of bit line structures and extend to the plurality of bit line structures; and a plurality of capacitor structures include a plurality of lower electrodes, an upper electrode in contact with the plurality of landing pads and a capacitor dielectric layer located between the plurality of lower electrodes and the upper electrode. The layer level of the bottom surface of the covering insulation structure is lower than the layer level of the bottom surface of the bit line.

19. The semiconductor memory device of claim 18, wherein the uppermost end of the overlay insulating structure, the uppermost end of the first bit line conductive layer and the uppermost end of the second bit line conductive layer are at the same level, and wherein the bottom surface of the overlay insulating structure is at a lower level than the uppermost end of the logic device isolation layer.

20. The semiconductor memory device of claim 18, wherein each of the first insulating cover layer and the covering insulating structure comprises a nitride.

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