Vertical gate-all-around (GAA) memory cell, integrated chip, and method for forming the same

Abstract

The various embodiments disclosed herein relate to a vertical gate all-around (GAA) memory cell. An intermediate conductor overlays a lower conductor and its width decreases toward the lower conductor to reach a point spaced apart from the lower conductor. An insulator structure is located between the lower conductor and the intermediate conductor. A semiconductor channel overlays the intermediate conductor, and a gate electrode is laterally disposed around the semiconductor channel on a sidewall of the semiconductor channel. A gate dielectric layer separates the gate electrode from the semiconductor channel, and an upper conductor overlays the semiconductor channel. The lower conductor, the intermediate conductor, and the insulator structure correspond to a resistor; however, the intermediate conductor, the upper conductor, the gate electrode, the gate dielectric layer, and the semiconductor channel correspond to a transistor on top of the resistor.

Description

Technical Field

[0001] This disclosure relates to a vertical gate full-ring memory cell and a method for forming the same. Prior Technology

[0002] Increasingly, Internet of Things (IoT) devices are using Physically Uncopyable Function (PUF) devices to generate unique digital fingerprints. PUF devices generate unique values ​​based on the randomness of their electrical characteristics, which is essentially caused by manufacturing variations. Static Random Access Memory (SRAM) storage cells are commonly used in PUF devices. Summary of the Invention

[0003] This disclosure relates to a memory cell, comprising: a lower conductor; an intermediate conductor overlying the lower conductor and decreasing in width toward the lower conductor to a point spaced apart above the lower conductor; an insulator structure between the lower conductor and the intermediate conductor; a semiconductor channel overlying the intermediate conductor; a gate electrode laterally surrounding the semiconductor channel on a side wall of the semiconductor channel; a gate dielectric layer separating the gate electrode from the semiconductor channel; and an upper conductor on top of the semiconductor channel.

[0004] This disclosure also relates to an integrated chip, comprising: a first memory cell including a first resistor and a first transistor on top of the first resistor, wherein the first resistor includes a first conductor and shares a second conductor with the first transistor, wherein the second conductor covers the first conductor and has a first tip extending toward the first conductor; and a second memory cell including a second resistor and a second transistor on top of the second resistor, wherein the second resistor includes a third conductor and shares a fourth conductor with the second transistor, wherein the fourth conductor covers the third conductor and has a second tip extending toward the third conductor; wherein the first tip and the second tip have different heights.

[0005] This disclosure also relates to a method for forming a memory cell, comprising: patterning a first dielectric layer to form a trench exposing a lower conductor; depositing an insulating layer to fill the trench, wherein a seam is formed and sealed in the trench during the deposition of the insulating layer; etching back the insulating layer to remove the insulating layer from a top surface of the first dielectric layer and open the seam; after the etching back, forming an intermediate conductor to fill and follow an unfilled portion of the trench; forming a semiconductor channel on top of the intermediate conductor; forming a gate electrode around the semiconductor channel; and forming an upper conductor on top of the semiconductor channel. Simple Explanation of the Diagram

[0006] The best understanding of this disclosure is achieved by reading it in conjunction with the accompanying drawings and the following detailed description. It should be noted that, in accordance with industry standard practice, the various features are not drawn to scale. In fact, for clarity of explanation, the dimensions of the various features may be arbitrarily increased or decreased.

[0007] Figure 1 shows a cross-sectional view of a vertical gate full-loop (GAA) memory cell used in some embodiments of a device with physical non-replicable functionality (PUF).

[0008] Figures 2A and 2B show top layout diagrams of some embodiments of the vertical GAA memory cell of Figure 1.

[0009] Figure 3 shows a circuit diagram of some embodiments of the vertical GAA memory cell of Figure 1.

[0010] Figure 4 shows a cross-sectional view of some embodiments of an integrated chip, in which the vertical GAA memory cell of Figure 1 is on the front side of a logic device.

[0011] Figure 5 shows a circuit diagram of some embodiments of a memory array comprising a plurality of vertical GAA memory cells as shown in Figure 4.

[0012] Figures 6A to 6C show cross-sectional views of some alternative embodiments of the integrated chip of Figure 4, in which the vertical GAA memory cells and an interconnect structure are varied.

[0013] Figure 7 shows a circuit diagram of some embodiments of a memory array comprising a plurality of vertical GAA memory cells as shown in Figure 6C.

[0014] Figures 8A and 8B show cross-sectional views of some alternative embodiments of the integrated chip of Figure 6C, in which the vertical GAA memory cells and an interconnect structure are varied.

[0015] Figure 9 shows a cross-sectional view of some embodiments of an integrated chip, in which the vertical GAA memory cell of Figure 1 is on a rear side of a logic device.

[0016] Figures 10A to 10C show cross-sectional views of some alternative embodiments of the integrated wafer of Figure 9, in which the vertical GAA memory cells and an interconnect structure are varied.

[0017] Figures 11A and 11B show cross-sectional views of some alternative embodiments of the integrated wafer of Figure 10C, in which the vertical GAA memory cells and interconnect structures are varied.

[0018] Figures 12 to 37 show a series of cross-sectional views of some embodiments of a method for forming a pair of vertical GAA memory cells for use as a PUF device.

[0019] Figure 38 shows a block diagram of some embodiments of the methods of Figures 12 to 37.

[0020] Figures 39 to 42 show a series of cross-sectional views of some first alternative embodiments of the method of Figures 12 to 37.

[0021] Figures 43 to 48 show a series of cross-sectional views of some second alternative embodiments of the methods of Figures 12 to 37.

[0022] Figures 49 to 51 show a series of cross-sectional views of some embodiments of a method for forming an integrated wafer, in which a pair of vertical GAA memory cells are on a front side of a logic device.

[0023] Figures 52 to 64 show a series of cross-sectional views of some embodiments of a method for forming an integrated wafer, in which a pair of vertical GAA memory cells are on a rear side of a logic device. Implementation

[0024] This disclosure provides numerous different embodiments, or examples, for implementing various features of this disclosure. To simplify this disclosure, specific examples of components and configurations are described below. Of course, these components and configurations are merely examples and are not intended to be limiting. For instance, in the following description, the formation of a first feature on or over a second feature may include embodiments where the first and second features are formed in direct contact, and may also include embodiments where additional features are formed between the first and second features, such that the first and second features do not need to be in direct contact. Furthermore, this disclosure may repeat element symbols and / or symbols in various examples. Such repetition is for simplicity and clarity and does not in itself determine the relationship between the various embodiments and / or configurations discussed.

[0025] Furthermore, for ease of description, spatial relative terms such as "below," "under," "down," "above," "up," and similar terms may be used in this disclosure to describe the relationship between one element or feature and another element(s), as illustrated in the figures. Spatial relative terms are intended to cover different orientations of the apparatus in use or operation other than those depicted in the figures. The apparatus may be oriented in other ways (rotated 90 degrees or otherwise) and the spatial relative descriptions used in this disclosure shall be interpreted accordingly.

[0026] Static random access memory (SRAM) cells can have random differences in their electrical properties, which are inherently caused by manufacturing differences. These random differences can be used to generate the unique non-replicable function (PUF) values ​​(e.g., "0" or "1") of individual SRAM cells. For example, an SRAM cell may have a preferred state (e.g., logic "0" or logic "1") when powered on and before initialization. This preferred state can vary randomly from SRAM cell to SRAM cell due to inherent manufacturing differences and can therefore be used as the PUF value for the SRAM cell.

[0027] The challenge of using SRAM cells as PUF elements lies in the low stability of SRAM cells. The electrical properties that generate PUF values ​​can vary in response to environmental conditions, such as temperature or the like. For example, the preferred state of an SRAM cell can change in response to environmental conditions. Therefore, the unique digital fingerprint generated from the PUF value of an SRAM cell may vary with environmental conditions, which can cause problems because the unique digital fingerprint is expected to be constant regardless of environmental conditions.

[0028] The various embodiments disclosed herein pertain to vertical gate all-loop (GAA) memory cells used as PUF devices. Compared to SRAM cells, vertical GAA memory cells exhibit high stability in their electrical properties. For example, their electrical properties are less affected by environmental conditions, such as temperature or the like. Therefore, the PUF value generated by vertical GAA memory cells exhibits high stability compared to the PUF value generated by SRAM cells.

[0029] It is understood that the high stability is due to the low number of functional components in vertical GAA memory cells. For example, a vertical GAA memory cell may have only two functional components (e.g., a resistor and a transistor), while an SRAM cell may have six or more functional components (e.g., six transistors). The low number of functional components also results in a small size and therefore a high memory density.

[0030] In some embodiments, a vertical GAA memory cell includes a resistor and a GAA transistor overlaid and connected in series with the resistor. The resistor is formed by a pair of conductors that are vertically stacked and spaced apart from each other by an insulating structure. The pair of conductors includes a first conductor and a second conductor. The second conductor overlays the first conductor and its width decreases vertically toward the first conductor to reach a point spaced apart on the first conductor. The resistance of the resistor varies depending on this point and the spacing between the first conductors.

[0031] It is understood that the separation at this point and between the first conductor is random, essentially due to manufacturing variations. Therefore, the resistance of a resistor is random, essentially due to manufacturing variations. This randomness can be used to generate the PUF value and thus a unique digital fingerprint. Furthermore, because vertical GAA memory has high stability, the PUF value and unique digital fingerprint can remain constant regardless of environmental conditions, etc.

[0032] Referring to Figure 1, a cross-sectional view 100 is provided for use in some embodiments of a vertical GAA memory cell 102 as a PUF device. The vertical GAA memory cell 102 includes a resistor 104 and a GAA transistor 106. As will be shown thereafter, the vertical GAA memory cell 102 can be considered as a transistor-resistor (ITIR) memory cell, a resistive random access memory (RRAM) memory cell, or the like.

[0033] Resistor 104 is formed by a first conductor 108 and a second conductor 110, which are stacked vertically and spaced apart from each other by an insulator structure 112. The first conductor 108 pads the second conductor 110 and the insulator structure 112, and further has a flat or substantially flat surface facing the second conductor 110 and the insulator structure 112. The second conductor 110 extends into the insulator structure 112 toward the first conductor 108. Furthermore, the width Wsc of the second conductor 110 decreases vertically toward the first conductor 108 to reach a point spaced apart from the first conductor 108.

[0034] The resistance of resistor 104 varies depending on the spacing between that point and the first conductor 108. It is understood that the spacing between that point and the first conductor 108 is random, essentially due to manufacturing variations. Therefore, the resistance of resistor 104 is random, essentially due to manufacturing variations. This randomness can be used to generate the PUF value and thus a unique digital fingerprint. Furthermore, it is understood that the resistor has high stability. For example, the resistance is not affected or substantially affected by environmental conditions. Therefore, the PUF value and the unique digital fingerprint can have high stability.

[0035] The high stability of the PUF value and unique digital fingerprint can be attributed, for example, to the fact that the PUF value is generated from a low number of functional components. For instance, the PUF value can be generated from only two functional components: a resistor 104 and a GAA transistor 106. In contrast, SRAM cells that generate PUF values ​​from six or more transistors can produce PUF values ​​with low stability. The low number of functional components also allows for small size and therefore high memory density.

[0036] GAA transistor 106 is overlaid on resistor 104 and electrically coupled in series. Furthermore, GAA transistor 106 shares a second conductor 110 with resistor 104. However, the second conductor 110 serves as a top electrode for resistor 104 and as a lower source / drain electrode for GAA transistor 106. Source / drain may refer to either a source or a drain electrode, individually or collectively depending on the context.

[0037] A semiconductor channel 114 is overlaid on a second conductor 110, and a third conductor 116 is overlaid on the semiconductor channel 114. The semiconductor channel 114 has a columnar profile extending from the second conductor 110 to the third conductor 116. The third conductor 116 is on a top surface of the semiconductor channel 114 and also on the sidewalls of the semiconductor channel 114. In an alternative embodiment, the third conductor 116 is localized on the top surface of the semiconductor channel 114. Furthermore, the third conductor 116 serves as a higher source / drain for a GAA transistor 106. In some embodiments, the second conductor 110 serves as a drain for the GAA transistor 106, while the third conductor 116 serves as a source for the GAA transistor 106, or vice versa.

[0038] A gate electrode 118 is laterally positioned around the semiconductor channel 114 on the sidewall of the semiconductor channel 114, at least in the cross-sectional view 100, with a pair of segments therebetween in which the semiconductor channel 114 is laterally sandwiched. Furthermore, the gate electrode 118 is perpendicularly positioned between the second conductor 110 and the third conductor 116 and is laterally separated from the semiconductor channel 114 by a gate dielectric layer 120.

[0039] A dielectric structure surrounds the vertical GAA memory cell 102. Furthermore, the dielectric structure includes a plurality of interconnect dielectric layers 126, a first etch stop layer 128a, and a second etch stop layer 128b. The plurality of interconnect dielectric layers 126 are stacked alternately and perpendicularly with the first etch stop layer 128a and the second etch stop layer 128b. The first etch stop layer 128a pads the gate electrode 118 and the gate dielectric layer 120, while the second etch stop layer 128b covers the gate electrode 118 and the gate dielectric layer 120. Furthermore, the second etch stop layer 128b pads a third conductor 116 to separate the third conductor 116 from the gate electrode 118 and the gate dielectric layer 120.

[0040] During the use of the vertical GAA memory cell 102, the gate electrode 118 can be selectively biased to vary the conductivity of the semiconductor channel 114 and the electrical coupling between the second and third conductors 110, 116. For example, under a first bias condition, a gate-source voltage can be greater than a threshold. Thus, the semiconductor channel 114 can have high conductivity and can electrically couple the second and third conductors 110, 116 together. Under a second bias condition, the gate-source voltage can be less than the threshold. Thus, the semiconductor channel 114 can have low conductivity and can electrically isolate the second and third conductors 110, 116 from each other.

[0041] When semiconductor channel 114 is in the ON state (e.g., due to the first bias condition described above), the resistance of resistor 104 can be used to generate a PUF value. For example, a low voltage can be applied across resistor 104, from the first conductor 108 to the third conductor 116, and the resulting current can be compared with a reference current to determine a PUF value. A current less than the reference current results in a PUF value of "0", a current more than the reference current results in a PUF value of "1", and vice versa. The low voltage can be, for example, low enough not to cause dielectric breakdown of the insulator structure 112.

[0042] While the preceding discussion assumes that the vertical GAA memory cell 102 is used as a PUF device, the vertical GAA memory cell 102 is not limited to being used as a PUF device. In an alternative embodiment, the vertical GAA memory cell 102 can be used as a one-time programmable (OTP) memory cell, and the resistor 104 is an antifuse.

[0043] For example, when the vertical GAA memory cell 102 is initially formed, it can be in a high-resistance state (HRS). This HRS is subject to inherent randomness and can be used to generate the PUF value described above. Furthermore, the vertical GAA memory cell 102 can be irreversibly changed to a low-resistance state (LRS) by applying a high voltage across resistor 104. The high voltage can, for example, burn out a portion of the insulating structure 112 that separates the tip from the first conductor 108, thus resulting in low conductivity from the tip to the first conductor 108. HRS can, for example, represent logic "0", and LRS can, for example, represent logic "1", and vice versa.

[0044] When semiconductor channel 114 is in the ON state, the logic state can be determined, for example, from the resistance of the vertical GAA memory cell 102. For instance, a low voltage can be applied across resistor 104, from the first conductor 108 to the third conductor 116, and the resulting current can be compared with a reference current to determine the state of the vertical GAA memory cell 102. This low voltage can be, for example, low enough not to cause any dielectric breakdown in the insulating structure 112.

[0045] In some embodiments, the vertical GAA memory cell 102 is one of a plurality of memory cells in a plurality of columns and a plurality of bars. In some such embodiments, a first conductor 108 is electrically coupled to a bit line BL, a third conductor 116 is electrically coupled to a source line SL through a first via 124a, and a gate electrode 118 is electrically coupled to a word line WL through a second via 124b. The source line SL or the bit line BL may, for example, be grounded during use of the vertical GAA memory cell 102.

[0046] In some embodiments, the width Wsc of the second conductor 110 continuously decreases from a top surface of the second conductor 110 to that point on the second conductor 110. In some embodiments, a maximum width of the second conductor 110 is located on the top surface of the second conductor 110, and / or that point on the second conductor 110 is at a very low elevation of the second conductor 110. In some embodiments, the top surface of the second conductor 110 is flush with a top surface of the insulating structure 112. In some embodiments, a maximum width of the second conductor is substantially the same as a maximum width of the insulator structure 112. In some embodiments, the width Wsc of the second conductor 110 has a maximum width of about 130-150 nanometers or some other suitable value.

[0047] In some embodiments, the first conductor 108 is or comprises a conductive material selected from the group of electrode materials. In some embodiments, the second conductor 110 is or comprises a conductive material selected from the group of electrode materials. In some embodiments, the third conductor 116 is or comprises a conductive material selected from the group of electrode materials. In some embodiments, the gate electrode 118 is or comprises a conductive material selected from the group of electrode materials. The group of electrode materials may, for example, essentially consist of or comprise titanium nitride (e.g., TiN), tantalum nitride (e.g., TaN), molybdenum nitride (e.g., MoN), tungsten nitride (e.g., WN), aluminum, tungsten, copper, molybdenum, some other suitable metal or metal nitride, or any combination thereof. In some embodiments, but not in all embodiments, the first conductor 108, the second conductor 110, the third conductor 116, and the gate electrode 118 are made of the same material (e.g., titanium nitride or some other suitable material).

[0048] In some embodiments, the insulator structure 112 is or comprises hafnium oxide (e.g., HfO2), tantalum oxide (e.g., Ta2O5), titanium oxide (e.g., TiO2), zirconium oxide (e.g., ZrO2), aluminum oxide (e.g., Al2O3), or any combination thereof. Furthermore, in some embodiments, the insulator structure 112 is or comprises silicon oxide (e.g., SiO2), silicon nitride (e.g., SiN), silicon oxynitride (e.g., SiON), silicon carbonitride (e.g., SiCN), silicon carbonitride (e.g., SiCON), or any combination thereof.

[0049] In some embodiments, the semiconductor channel 114 is or comprises amorphous silicon, indium gallium zinc oxide (IGZO), copper oxide (e.g., Cu₂O), nickel oxide (e.g., NiO), tin oxide (e.g., SnO), some other suitable semiconductor material, or any combination thereof. Furthermore, in some embodiments, the semiconductor channel 114 is doped with n-type or p-type doping. For example, the semiconductor channel 114 may be or comprises n-type amorphous silicon, p-type amorphous silicon, n-type IGZO, p-type copper oxide, p-type nickel oxide, or p-type tin oxide.

[0050] In some embodiments, the first conductor 108, the second conductor 110, and the third conductor 116 may also be regarded as a first electrode, a second electrode, and a third electrode, respectively. Furthermore, in some embodiments, the first conductor 108, the second conductor 110, and the third conductor 116 may also be regarded as a lower conductor or electrode, an intermediate conductor or electrode, and an upper conductor or electrode, respectively.

[0051] Referring to Figures 2A and 2B, top layout diagrams 200A and 200B are provided for some embodiments of the vertical GAA memory cell 102 of Figure 1. Figure 2A shows a view along line A-A' in Figure 1, which is attached to resistor 104. Figure 2B shows a view along line B-B' in Figure 1, which is attached to GAA transistor 106. Additionally, a first conductor 108 is shown in the dashed box in both Figures 2A and 2B to provide a common reference point.

[0052] Focusing on Figure 2A, the first conductor 108, the second conductor 110, and the insulator structure 112 have a square top geometry. In an alternative embodiment, the first conductor 108, the second conductor 110, and the insulator structure 112 have a circular top geometry, a triangular top geometry, or some other suitable top geometry. The second conductor 110 is smaller than the insulator structure 112 (e.g., in length and width) and its length and width are smaller than the first conductor 108.

[0053] Focusing on Figure 2B, the gate electrode 118 and the gate dielectric layer 120 extend continuously in individual closed paths around the semiconductor channel 114, with the gate dielectric layer 120 separating the gate electrode 118 from the semiconductor channel 114. In other words, the gate electrode is "entirely" surrounding the semiconductor channel 114. In an alternative embodiment, the gate electrode 118 has one, two, or more interruptions around the semiconductor channel 114. Furthermore, the semiconductor channel 114 has a square top geometry. In an alternative embodiment, the semiconductor channel 114 has a circular top geometry, a triangular top geometry, or some other suitable top geometry.

[0054] Referring to FIG3, a circuit diagram 300 is provided for some embodiments of the vertical GAA memory cell 102 of FIG1. ​​A resistor 104 and a GAA transistor 106 are connected in series, such that a first (e.g., lower) source / drain of the GAA transistor 106 is electrically coupled to a first (e.g., upper) terminal of the resistor 104. In some embodiments, a second (e.g., lower) terminal of the resistor 104 is electrically coupled to a word line BL. Furthermore, in some embodiments, a second (e.g., upper) source / drain of the GAA transistor 106 is electrically coupled to a source line SL, and the gate electrode of the GAA transistor 106 is electrically coupled to a word line WL.

[0055] Referring to FIG4, a cross-sectional view 400 of some embodiments of an integrated chip is provided, in which a pair of vertical GAA memory cells 102 are on a front side FS of a first logic element 402a. Each of the vertical GAA memory cells 102 is as shown in FIG1. ​​Furthermore, each of the vertical GAA memory cells 102 may, by example, additionally or alternatively, be any of those in FIG2A, FIG2B, and FIG3 or any of those in the following figures.

[0056] A first logic element 402a is overlaid on the upper semiconductor substrate 404 and adjacent to a second logic element 402b. The front side FS of the first logic element 402a corresponds to a higher side of the first logic element 402a and faces an interconnect structure 406. The front side FS faces a rear side BS of the first logic element 402a. The rear side BS of the first logic element 402a corresponds to a bottom surface of the first logic element 402a. In some embodiments, the semiconductor substrate 404 is or comprises silicon, germanium, gallium, zinc, indium, oxygen, some other suitable material, or any combination thereof.

[0057] The first logic element 402a and the second logic element 402b are separated from each other by an isolation structure 408. The isolation structure 408 may, for example, be or include a shallow trench isolation (STI) structure, a deep trench isolation (DTI) structure, a silicon localized oxide (LOCOS) isolation structure, some other suitable isolation structure, or any combination thereof. Furthermore, the first logic element 402a and the second logic element 402b may, for example, be a planar field-effect transistor (planar FET), a fin field-effect transistor (fin field-effect transistor), a gate all-loop (GAA) field-effect transistor (GAAFET), some other suitable types of logic devices and / or transistors, or any combination thereof.

[0058] The first logic element 402a and the second logic element 402b each include a separate gate electrode 410, a separate gate dielectric layer 412, and separate pairs of source / drain regions 414. The pairs of source / drain regions 414 are inserted into a top portion of the semiconductor substrate 404. The gate electrodes 410 are respectively coated on the gate dielectric layer 412 and are respectively located between the pairs of source / drain regions 414. In some embodiments, the first logic element 402a and the second logic element 402b further include separate wells 416. The wells 416 correspond to doped regions of the semiconductor substrate 404 and respectively pad the pairs of source / drain regions 414 and the gate electrode 410.

[0059] In some embodiments, the gate electrode 410 is or comprises polycrystalline silicon, silicon, titanium, tantalum, aluminum tungsten, nitrogen, zinc, indium, gallium, germanium, carbon, some other suitable materials, or any combination thereof. In some embodiments, the gate dielectric layer 412 is or comprises silicon oxide (e.g., SiO2), hafnium oxide (e.g., HfO), lanthanum, silicon oxynitride (e.g., SiON), silicon carbon oxynitride (e.g., SiCON), zinc, zirconium, some other suitable materials, or any combination thereof. In some embodiments, the paired source / drain regions 414 are or comprise silicon, germanium, carbon, phosphorus, boron, some other suitable materials, or any combination thereof.

[0060] Interconnect structure 406 covers and is electrically coupled to a first logic element 402a and a second logic element 402b on the front side FS of a first logic element 402a. Interconnect structure 406 includes a plurality of lines 418 and a plurality of vias 124. The plurality of lines 418 form a plurality of line levels, and the plurality of vias 124 form a plurality of via levels, which are alternately stacked with the plurality of line levels. The line levels from a bottom to a top of interconnect structure 406 are labeled M1, M2, etc., up to M6. The via levels from the bottom to the top of interconnect structure 406 are labeled V0, V1, etc., up to V5.

[0061] A dielectric structure surrounds an interconnect structure 406 and includes a plurality of interconnect dielectric layers 126, a first etch stop layer 128a, and a second etch stop layer 128b. The plurality of interconnect dielectric layers 126 are stacked alternately and perpendicularly with the first etch stop layer 128a and the second etch stop layer 128b. In some embodiments, the first etch stop layer 128a and the second etch stop layer 128b are or comprise silicon nitride, silicon carbide, some other suitable dielectric, or any combination thereof. In some embodiments, the plurality of interconnect dielectric layers 126 are or comprise undoped silicate glass (USG), borosilicate glass (BSG), silicon oxide, some other suitable dielectric, or any combination thereof.

[0062] Pairs of vertical GAA memory cells 102 are vertically positioned between line levels M3 and M4 in interconnect structure 406. In an alternative embodiment, the pairs of vertical GAA memory cells 102 are positioned between different line levels. Furthermore, in an alternative embodiment, interconnect structure 406 contains more or fewer line levels and / or more or fewer via levels. Therefore, the pairs of vertical GAA memory cells 102 can be more generally described as being vertically positioned between line level Mx and line level Mx+1, where x is an integer representing a line level number, such as 3 or some other suitable number.

[0063] As described above, each of the vertical GAA memory cells 102 is as shown in FIG. 1, and may additionally or alternatively be any of FIG. 2A, FIG. 2B, and FIG. 3, or as shown in the following figures. Thus, the vertical GAA memory cell 102 includes, among other things, individual first conductors 108, individual second conductors 110, individual third conductors 116, individual semiconductor channels 114, individual gate electrodes 118, and individual gate dielectric layers 120.

[0064] The first conductor 108 is shared with the interconnect structure 406 and corresponds to the V-line horizontal M3. In some embodiments, the first conductor 108 is electrically coupled to or otherwise corresponds to a common bit line BL, which extends continuously between the vertical GAA memory cells 102 outside the cross-sectional view 400 of FIG4. In other embodiments, the first conductor 108 is electrically coupled to or corresponds to individual bit lines BL.

[0065] The second conductor 110 is respectively overlaid on the first conductor 108 and has individual tips extending toward the first conductor 108. Furthermore, due to the inherent randomness of manufacturing variations, the tips are separated from the first conductor 108 by different distances. Thus, the vertical GAA memory cell 102 has different resistances as described above. In some embodiments, the second conductor 110 has individual height and / or cross-sectional areas that differ due to the inherent randomness of manufacturing variations.

[0066] The third conductor 116 is respectively covered on the semiconductor channel 114, and the gate electrode 118 is respectively laterally surrounding the semiconductor channel 114. Furthermore, vias at via level V3 extend from the third conductor 116 and the gate electrode 118 respectively to a line at line level M4. In some embodiments, the line at line level M4 and electrically coupled to the gate electrode 118 corresponds to a character line WL. Furthermore, in some embodiments, the third conductor 116 is electrically coupled to a common line at line level M5, and this common line corresponds to a source line SL.

[0067] Referring to FIG. 5, a circuit diagram 500 is provided for some embodiments of a memory array comprising a plurality of vertical GAA memory cells 102 as shown in FIG. 4. In particular, the plurality of vertical GAA memory cells 102 are arranged in non-overlapping pairs along columns, each pair of vertical GAA memory cells as shown in FIG. 4. Furthermore, each of the plurality of vertical GAA memory cells 102 may additionally or alternatively be arranged as in any of FIG. 1, FIG. 2A, FIG. 2B, and FIG. 3, or as in any of the following figures.

[0068] The memory array has M columns and N columns, where M and N are integers. Furthermore, the memory array has M bit lines corresponding one-to-one to M columns, M source lines corresponding one-to-one to M columns, and N word lines corresponding one-to-one to N columns. However, other correspondences (e.g., one-to-two) are possible and are shown below in an alternative embodiment. Bit lines are labeled BL1, BL2, etc., to BLM, where the subscripts correspond to column numbers. Source lines are labeled SL1, SL2, etc., to SLM, where the subscripts correspond to column numbers. Word lines are labeled WL1, WL2, etc., to WLN, where the subscripts correspond to column numbers.

[0069] The source line of any given column is electrically coupled to a source / drain of each GAA transistor 106 in the given column; the bit line of any given column is electrically coupled to one end of each resistor 104 in the given column; and the word line of any given column is electrically coupled to the gate electrode of each GAA transistor 106 in the given column.

[0070] As described above, the selective conduction of a GAA transistor depends on how a corresponding gate electrode is biased. When a GAA transistor of a vertical GAA memory cell is in an on-state, the vertical GAA memory cell can be considered selected. When a GAA transistor of a vertical GAA memory cell is in a non-on-state, the vertical GAA memory cell can be considered unselected. Therefore, because the word line allows the bias state to be controlled by the gate electrode of the GAA transistor, a given column of word lines allows the vertical GAA memory cell to be selected for read and / or write operations. In this way, the GAA transistor 106 of the vertical GAA memory cell 102 can also be referred to as a select transistor, an access transistor, or the like.

[0071] The vertical GAA memory cell 102 can be used as a PUF device and / or an OTP memory cell. For example, the vertical GAA memory cell can be used as a PUF device in a first column of the memory array, while the vertical GAA memory cell can be used as an OTP memory cell in the remaining columns of the memory array. As another example, all of the vertical GAA memory cells 102 can be used as either a PUF device or an OTP memory cell. Because of the low number of functional components (e.g., resistors and transistors) per memory cell and because of the vertical stacking of these functional components, the memory density can be high.

[0072] Vertical GAA memory cells, used as PUF devices, can have individual PUF values, which are linked to generate a unique digital fingerprint. PUF devices are in HRS, which has inherent randomness. A PUF value for a PUF device can be determined by selecting a corresponding word line for the PUF device and then applying a low voltage across a resistor of the PUF device using the corresponding source and bit lines. The resulting current is then compared with a reference current to determine the PUF value. The low voltage can be, for example, low enough not to cause dielectric breakdown of the resistor.

[0073] Vertical GAA memory cells, used as OTP memory cells, can have individual logic values ​​for storing data. OTP memory cells are formed in HRS and can irreversibly change to LRS. By selecting an OTP memory cell using a corresponding word line, an OTP memory cell can irreversibly change to an LRS. A high voltage, then applied across a resistor using the corresponding bit line and source line, irreversibly breaks down the dielectric of the resistor. By selecting an OTP memory cell using a corresponding word line and then applying a low voltage across a resistor using the corresponding source line and bit line, the state of an OTP memory cell (e.g., LRS or HRS) can be determined. The resulting current is then compared to a reference current to determine whether the OTP memory cell is in HRS or LRS. Compared to a high voltage, a low voltage is low and will not cause dielectric breakdown of the resistor.

[0074] Referring to Figures 6A to 6C, cross-sectional views 600A to 600C are provided for some alternative embodiments of the integrated chip of Figure 4, in which the paired vertical GAA memory cells 102 and the interconnect structure 406 are varied.

[0075] In Figure 6A, the through holes at through-hole level V3 extend from the gate electrode 118 to the line at line level M4. Furthermore, the through holes at through-hole level V4 extend from the third conductor 116 to the line at line level M5. Therefore, the through holes at the gate electrode 118 and the through holes at the third conductor 116 are at different through-hole levels.

[0076] In Figure 6B, the second conductors 110 are integrated with semiconductor channels 114. In other words, each second conductor and its corresponding semiconductor channel are formed from a common semiconductor structure. In some embodiments, the second conductors 110 have p-type or n-type dopants with an increased doping concentration relative to the semiconductor channels 114.

[0077] In Figure 6C, the paired vertical GAA memory cells 102 share a common word line WL, a common gate electrode 118, and a common gate dielectric layer 120.

[0078] Referring to FIG7, a circuit diagram 700 is provided for some embodiments of a memory array comprising a plurality of vertical GAA memory cells 102 as shown in FIG6C. In particular, the plurality of vertical GAA memory cells 102 are arranged in non-overlapping pairs along columns, each pair of vertical GAA memory cells being as shown in FIG6C.

[0079] Referring to Figures 8A and 8B, cross-sectional views 800A and 800B are provided for some alternative embodiments of the integrated chip of Figure 6C, in which the paired vertical GAA memory cells 102 and the interconnect structure 406 are varied.

[0080] In Figure 8A, the through holes at through-hole level V3 extend from the gate electrode 118 to the line at line level M4. Furthermore, the through holes at through-hole level V4 extend from the third conductor 116 to the line at line level M5. Therefore, the through holes at the gate electrode 118 and the through holes at the third conductor 116 are at different through-hole levels.

[0081] In Figure 8B, the second conductors 110 are integrated with semiconductor channels 114. In other words, each second conductor and its corresponding semiconductor channel are formed from a common semiconductor structure. In some embodiments, the second conductors 110 have a p-type or n-type dopant with an increased doping concentration relative to the semiconductor channels 114.

[0082] Referring to FIG9, a cross-sectional view 900 of some embodiments of an integrated chip is provided, in which a pair of vertical GAA memory cells 102 are attached to a rear side BS of a first logic element 902a. Each of the vertical GAA memory cells 102 is as shown in FIG1. ​​Furthermore, each of the vertical GAA memory cells 102 may, by example, additionally or alternatively, be as shown in any of FIG2A, FIG2B, and FIG3, or as shown in the following figures.

[0083] A first logic element 902a is mounted on a carrier substrate 904 and adjacent to a second logic element 902b. A front side FS of the first logic element 902a corresponds to a lower side of the first logic element 902a and faces a first interconnect structure 906. Furthermore, the front side FS faces the rear side BS of the first logic element 902a. The rear side BS corresponds to a higher side of the first logic element 902a and faces a second interconnect structure 406. Furthermore, the rear side BS is surrounded by an isolation structure 907.

[0084] In some embodiments, the carrier substrate 904 is a semiconductor substrate and / or some other suitable type of carrier substrate. Furthermore, in some embodiments, the carrier substrate 904 is or comprises silicon, germanium, gallium, zinc, indium, oxygen, some other suitable materials, or any combination thereof. In some embodiments, the isolation structure 907 is or comprises an STI structure and / or some other suitable isolation structure.

[0085] The first logic element 902a and the second logic element 902b are GAAFETs. However, the first logic element 902a and the second logic element 902b may alternatively be, for example, planar FETs, fin field-effect transistors, some other suitable types of logic devices and / or transistors, or any combination thereof. The first logic element 902a and the second logic element 902b include individual plurality of semiconductor channels 908, individual protective layers 910, individual gate electrodes 912, individual gate dielectric layers 914, and corresponding source / drain regions 916.

[0086] The semiconductor channel 908 of one of the given first logic elements 902a and the second logic element 902b is vertically stacked and covered by a corresponding protective layer 910. Furthermore, the semiconductor channel 908 of one of the given first logic elements 902a and the second logic element 902b is laterally sandwiched between two source / drain regions 916 and vertically separated from each other by a corresponding gate electrode 912. As shown, the first logic element 902a and the second logic element 902b share one of the source / drain regions 916, but this may not be the case in alternative embodiments. The gate electrode 912 is separated from the semiconductor channel 908 by a gate dielectric layer 914.

[0087] In some embodiments, the first logic element 902a and the second logic element 902b further include corresponding individual first spacer structures 918, individual second spacer structures 920, and individual third spacer structures 922. The first spacer structures 918 separate corresponding semiconductor channels 908 from each other on the sidewalls of the gate electrode 912. The second spacer structures 920 and 922 are located below the semiconductor channels 908. Furthermore, the second spacer structure 920 is located on the sidewall of the gate electrode 912, and the third spacer structure 922 is located on the sidewall of the second spacer structure 920.

[0088] In some embodiments, the gate electrode 912 is or comprises polycrystalline silicon, silicon, titanium, tantalum, aluminum tungsten, nitrogen, zinc, indium, gallium, germanium, carbon, some other suitable materials, or any combination thereof. In some embodiments, the gate dielectric layer 914 is or comprises silicon oxide (e.g., SiO2), hafnium oxide (e.g., HfO), lanthanum, silicon oxynitride (e.g., SiON), silicon carbon oxynitride (e.g., SiCON), zinc, zirconium, some other suitable materials, or any combination thereof. In some embodiments, the paired source / drain regions 916 are or comprise silicon, germanium, carbon, phosphorus, boron, some other suitable materials, or any combination thereof.

[0089] A first interconnect structure 906 is raised and electrically coupled to a first logic element 902a and a second logic element 902b on the front side FS of the first logic element 902a. The first interconnect structure 906 includes a plurality of conductive features, including a plurality of first horizontal contacts 924, a plurality of second horizontal contacts 926, a line 928, and a via 930. The second horizontal contacts 926 are raised and spaced from a gate electrode 912, and the first horizontal contacts 924 extend from the second horizontal contacts 926 to the gate electrode 912. Lines 928 are spaced below the second horizontal contacts 926, and vias 930 extend from the lines 928 to each of the second horizontal contacts 926.

[0090] In some embodiments, line 928 can also be considered as a re-layer (RDL). While only one line and only one via are shown, more lines and / or more vias are feasible. Furthermore, while only one via level and only one line level are shown, more via levels and / or more line levels are feasible. In this embodiment, line and via levels are alternately stacked away from the second level contact 926.

[0091] A heat sink conductor 932 is overlaid on a carrier substrate 904 and bonded to a wire 928 at a bonding interface 934 to facilitate heat dissipation. In an alternative embodiment, the heat sink conductor 932 is omitted. The bonding interface 934 includes a conductor-to-conductor assembly (e.g., on the heat sink conductor 932) and a dielectric-to-dielectric assembly (e.g., on the dielectric layer, discussed later).

[0092] A dielectric structure surrounds the front sides of a first interconnect structure 906, a first logic element 902a, and a second logic element 902b, and a heat sink conductor 932. The dielectric structure includes an interlayer dielectric layer 936, a plurality of interconnect dielectric layers 938, a plurality of etch stop layers 940, and a bonding dielectric layer 942, which are vertically stacked on a carrier substrate 904. In some embodiments, the etch stop layer 940 is or comprises silicon nitride, silicon carbide, some other suitable dielectric, or any combination thereof. In some embodiments, the interlayer dielectric layer 936, the plurality of interconnect dielectric layers 938, and the bonding dielectric layer 942 are each or comprise a dielectric from a group of groups, which is essentially composed of or comprises USG, BSG, silicon oxide, some other suitable dielectric, or any combination thereof.

[0093] A second interconnect structure 406 covers and is electrically coupled to both the first logic element 902a and the second logic element 902b on the rear side BS of the first logic element 902a. In some embodiments, the second interconnect structure 406 is electrically coupled to both the first logic element 902a and the second logic element 902b via one of the source / drain regions 916, which are shared by both the first logic element 902a and the second logic element 902b. The second interconnect structure 406 is as its counterpart with respect to FIG4, unless described below.

[0094] The second interconnect structure 406 includes a plurality of lines 418 and a plurality of vias 124, respectively forming a plurality of line levels and a plurality of via levels. The line levels, from a bottom to a top of the second interconnect structure 406, are labeled M0, M1, etc., to M5. The via levels, from the bottom to the top of the second interconnect structure 406, are labeled V0, V1, etc., to V4. Furthermore, the second interconnect structure 406 includes a contact plug 944 extending from line level M0 to a first logic element 902a and a second logic element 902b. For example, the contact plug 944 may extend to one of the source / drain regions 916, which is shared by the first logic element 902a and the second logic element 902b. In some embodiments, the contact plug 944 may be considered a rear power rail or the like. In some embodiments, the contact plug 944 is or comprises tungsten, tungsten nitride, ruthenium, iridium, molybdenum, molybdenum nitride, copper, aluminum, silicon, or any combination thereof.

[0095] A dielectric structure surrounds the second interconnect structure 406 and includes a plurality of interconnect dielectric layers 126, a first etch stop layer 128a, and a second etch stop layer 128b. Furthermore, the plurality of interconnect dielectric layers 126 are stacked alternately and perpendicularly with the first etch stop layer 128a and the second etch stop layer 128b.

[0096] Pairs of vertical GAA memory cells 102 are positioned vertically between line levels M2 and M3 in the second interconnect structure 406. In alternative embodiments, the pairs of vertical GAA memory cells 102 are positioned between different line levels, and / or the second interconnect structure 406 includes more or fewer line levels and / or more or fewer via levels. As described above, each of the vertical GAA memory cells 102 is as shown in FIG. 1, and may additionally or alternatively be as shown in any of FIG. 2A, FIG. 2B, and FIG. 3, or as shown in any of the following figures. Thus, the vertical GAA memory cell 102 includes, among other things, an individual first conductor 108, an individual second conductor 110, an individual third conductor 116, an individual semiconductor channel 114, an individual gate electrode 118, and an individual gate dielectric layer 120.

[0097] Referring to Figures 10A to 10C, cross-sectional views 1000A to 1000C are provided for some alternative embodiments of the integrated chip of Figure 9, in which the paired vertical GAA memory cells 102 and the interconnect structure 406 are varied.

[0098] In Figure 10A, the through holes at through-hole level V2 extend from the gate electrode 118 to the line at line level M3. Furthermore, the through holes at through-hole level V3 extend from the third conductor 116 to the line at line level M4. Therefore, the through holes at the gate electrode 118 and the through holes at the third conductor 116 are at different through-hole levels.

[0099] In Figure 10B, the second conductors 110 are integrated with semiconductor channels 114. In other words, each second conductor and its corresponding semiconductor channel are formed from a common semiconductor structure. In some embodiments, the second conductors 110 have a p-type or n-type dopant with increased doping concentration relative to the semiconductor channels 114.

[0100] In Figure 10C, pairs of vertical GAA memory cells 102 share a common word line WL, a common gate electrode 118, and a common gate dielectric layer 120. The vertical GAA memory cell 102 may be, for example, part of a memory array as shown in Figure 7.

[0101] Referring to Figures 11A and 11B, cross-sectional views 1100A and 1100B are provided for some alternative embodiments of the integrated chip of Figure 10C, in which the paired vertical GAA memory cells 102 and the interconnect structure 406 are varied.

[0102] In Figure 11A, the through holes at through-hole level V2 extend from the gate electrode 118 to the line at line level M3. Furthermore, the through holes at through-hole level V3 extend from the third conductor 116 to the line at line level M4. Therefore, the through holes at the gate electrode 118 and the through holes at the third conductor 116 are at different through-hole levels.

[0103] In Figure 11B, the second conductors 110 are integrated with semiconductor channels 114. In other words, each second conductor and its corresponding semiconductor channel are formed from a common semiconductor structure. In some embodiments, the second conductor 110 has a p-type or n-type dopant with increased doping concentration relative to the semiconductor channel 114.

[0104] Referring to Figures 12 through 37, a series of cross-sectional views 1200 to 3700 are provided for some embodiments of a method for forming a pair of vertical GAA memory cells used as a PUF device. The pair of vertical GAA memory cells can be, for example, any of those shown in Figures 1, 4, and 9. Furthermore, the pair of vertical GAA memory cells can, for example, have a top-mounted layout as shown in Figures 2A and / or 2B.

[0105] As shown in the cross-sectional view 1200 of Figure 12, a pair of first conductors 108 are provided or otherwise formed to be covered by a first interconnect dielectric layer 126a. The pair of first conductors 108 correspond to lines 418 of an interconnect structure and are in a line level Mx, where x is an integer representing a line level.

[0106] As shown in the cross-sectional view 1300 of Figure 13, the first interconnect dielectric layer 126a is patterned to form a pair of trenches 1302 respectively overlaid on and exposing the first conductor 108. In some embodiments, the individual width Wtr of the trenches 1302 is approximately 130-150 nanometers or some other suitable value. Patterning can be performed, for example, by lithography / etching processes or some other suitable processes.

[0107] As shown in the cross-sectional view 1400 of Figure 14, an insulating layer 112l is deposited over the first interconnect dielectric layer 126a and scribes lines in the trench 1302. The deposition can be performed, for example, by physical vapor deposition (PVD), high-growth chemical vapor deposition (CVD), or some other suitable deposition process.

[0108] During the deposition of insulating layer 112l, the material of insulating layer 112l is deposited more rapidly at the top corner of the first interconnect dielectric layer 126a in trench 1302. As a result, trench 1302 is closed before it is fully formed and a pair of seams 1402 are formed in trench 1302 respectively. Due to the inherent randomness of the deposition of insulating layer 112l, seams 1402 can have different depths, profile areas, heights, etc., as shown later. This randomness allows for the generation of PUF values.

[0109] In some embodiments, the insulating layer 112l is a high-k dielectric material and / or comprises hafnium oxide, tantalum oxide, titanium oxide, zirconium oxide, aluminum oxide, or any combination thereof. In some embodiments, the insulating layer 112l is or comprises silicon oxide, silicon nitride, silicon oxynitride, silicon carbonitride, silicon carbonitride, or any combination thereof.

[0110] As shown in the cross-sectional view 1500 of Figure 15, the insulating layer 112l is etched back. This removes the insulating layer 112l from the top of the first interconnect dielectric layer 126a and forms a pair of insulating structures 112 respectively in the trench 1302. Because of the seam 1402, the insulating structures 112 only partially fill the trench 1302. Furthermore, the unfilled portions of the trench 1302 have individual profiles whose width decreases towards the first conductor 108 and reaches its apex at the point pointing towards the first conductor 108.

[0111] As shown in the cross-sectional view 1600 of Figure 16, a conductive layer 110l is deposited over the first interconnect dielectric layer 126a and fills a remaining portion of the trench 1302 on the insulator structure 112. The conductive layer 110l can be deposited, for example, by atomic layer deposition (ALD) or some other suitable deposition process. In some embodiments, the conductive layer 110l is or comprises titanium nitride, tantalum nitride, molybdenum nitride, tungsten nitride, aluminum, tungsten, copper, molybdenum, some other suitable metal or metal nitride, or any combination thereof.

[0112] As shown in the cross-sectional view 1700 of Figure 17, planarization is performed into the conductive layer 110l. Planarization can be performed, for example, by chemical mechanical polishing (CMP) or some other suitable planarization process.

[0113] Planarization removes the conductive layer 110l from the top of the first interconnect dielectric layer 126a and forms a pair of second conductors 110. The second conductors 110 are respectively overlaid on the first conductor 108 and separated from the first conductor 108 by the insulating structure 112. Furthermore, the width of the second conductors 110 decreases from one top of the first interconnect dielectric layer 126a toward the first conductor 108 to a certain point.

[0114] Collectively, the first conductor 108, the insulator structure 112, and the second conductor 110 form a pair of resistors 104. Because of the inherent randomness in the dimensions of the joint 1402 (see Figure 14), the second conductor 110 is inherently random in its height, cross-sectional area, separation from the first conductor 108, and so on. This inherent randomness results in inherent randomness in the resistance of the resistor 104, which can be used to generate a PUF value and thus a unique digital fingerprint.

[0115] As shown in the cross-sectional view 1800 of Figure 18, a first etch stop layer 128a is deposited on top of the first interconnect dielectric layer 126a and the resistor 104. The first etch stop layer 128a is a dielectric material different from that of the first interconnect dielectric layer 126a. In some embodiments, the first etch stop layer 128a is or comprises silicon nitride, silicon carbide, silicon oxynitride, some other suitable material, or any combination thereof.

[0116] As shown in the cross-sectional view 1900 of Figure 19, the first etch stop layer 128a is patterned to form a pair of openings 1902 overlying and exposing the second conductor 110 respectively. Patterning can be performed, for example, by lithography / etching processes or some other suitable patterning processes.

[0117] As shown in the cross-sectional view 2000 of Figure 20, a semiconductor layer 2002 is deposited on top of the first etch stop layer 128a and fills the opening 1902 on top of the resistor 104. In some embodiments, a top surface of the semiconductor layer 2002 is further planarized by planarization or the like. Planarization can be performed, for example, by CMP and / or some other suitable planarization process.

[0118] In some embodiments, the semiconductor layer 2002 is or comprises amorphous silicon, indium gallium zinc oxide, copper oxide, nickel oxide, tin oxide, some other suitable semiconductor material, or any combination thereof. Furthermore, in some embodiments, the semiconductor layer 2002 is doped with an n-type dopant or a p-type dopant. For example, the semiconductor layer 2002 may be or comprises n-type amorphous silicon, p-type amorphous silicon, n-type indium gallium zinc oxide, p-type copper oxide, p-type nickel oxide, or p-type tin oxide. However, other suitable materials are feasible.

[0119] As shown in the cross-sectional view 2100 of FIG21, the semiconductor layer 2002 is patterned to form a pair of semiconductor channels 114 on the resistor 104. In some embodiments, the patterning is such that the semiconductor channels 114 have individual widths that are the same as or similar to the individual widths of the opening 1902 (see FIG19). The patterning can be performed, for example, by a lithography / etching process or some other suitable patterning process. To some extent, the patterning is performed by a lithography / etching process, and the first etch stop layer 128a can, for example, serve as an etch stop during the etching of the semiconductor layer 2002.

[0120] As shown in the cross-sectional view 2200 of Figure 22, a dielectric layer 120l and a conductive layer 118l are deposited over the first etch stop layer 128a and the semiconductor channel 114, and further scribe lines are drawn on the sidewalls of the semiconductor channel 114. The dielectric layer 120l can be deposited, for example, by ALD and / or some other suitable deposition process. The conductive layer 118l is deposited on the dielectric layer 120l and can be deposited, for example, by ALD and / or some other suitable deposition process.

[0121] In some embodiments, the conductive layer 118l is or comprises titanium nitride, tantalum nitride, molybdenum nitride, tungsten nitride, aluminum, tungsten, copper, molybdenum, some other suitable metal or metal nitride, or any combination thereof. In some embodiments, the dielectric layer 120l is or comprises silicon oxide, silicon nitride, silicon oxynitride, silicon carbonitride, silicon carbonitride, or any combination thereof.

[0122] As shown in the cross-sectional view 2300 of Figure 23, the conductive layer 118l and the dielectric layer 120l are patterned to form a pair of gate stacks individually connected to the semiconductor channel 114. Alternatively, a single, continuous gate stack is patterned to communicate with the semiconductor channel 114, as exemplarily in Figures 6C, 8A, 8B, 10C, 11A, or 11B. Each gate stack includes a gate electrode 118 formed from the conductive layer 118l, and each gate stack further includes a gate dielectric layer 120 formed from the dielectric layer 120l. The gate stacks are located on the sidewalls of the semiconductor channel 114 and, in some embodiments, completely surround the corresponding semiconductor channel when viewed from top to bottom. See Figure 2B for example. Patterning can be performed, for example, by lithography / etching processes or some other suitable patterning processes.

[0123] As shown in the cross-sectional view 2400 of Figure 24, a second interconnect dielectric layer 126b is deposited to cover the gate electrode 118 and the first etch stop layer 128a, and further along the sidewall of the gate electrode 118.

[0124] As shown in the cross-sectional view 2500 of Figure 25, planarization is performed into the second interconnect dielectric layer 126b. Planarization flattens a top surface of the second interconnect dielectric layer 126b and recesses the top surface until it is flush with a top surface of the gate electrode 118. Planarization can be performed, for example, by CMP and / or some other suitable planarization process.

[0125] As shown in the cross-sectional view 2600 of Figure 26, an etch-back process is performed to recess a top surface of the second interconnect dielectric layer 126b relative to the individual top surface of the gate electrode 118. The etch-back exposes the upper sidewall portion of the gate electrode 118, leaving the lower sidewall portion covered by the second interconnect dielectric layer 126b. The etch-back can be performed, for example, using an etchant with a high etch rate on the second interconnect dielectric layer 126b relative to the gate electrode 118, such that the gate electrode 118 is etched with minimal etching.

[0126] As shown in the cross-sectional view 2700 of FIG27, another etchback is performed to recess the individual top surfaces of the gate electrode 118 and the gate dielectric layer 120 relative to the individual top surface of the semiconductor channel 114. In some embodiments, the individual top surfaces of the gate electrode 118 and the gate dielectric layer 120 are etched back until they are flush with or substantially flush with a top surface of the second interconnect dielectric layer 126b. The etchback can be performed, for example, using an etchant that has a high etch rate on the gate electrode 118 and the gate dielectric layer 120 relative to the semiconductor channel 114 and the second interconnect dielectric layer 126b, such that the semiconductor channel 114 and the second interconnect dielectric layer 126b are etched with minimal etch.

[0127] As shown in the cross-sectional view 2800 of Figure 28, a second etch stop layer 128b is deposited over the second interconnect dielectric layer 126b and the semiconductor channel 114, with further scribe lines on the sidewalls of the semiconductor channel 114. The second etch stop layer 128b is a dielectric material and is a different type of dielectric material from the second interconnect dielectric layer 126b. In some embodiments, the second interconnect dielectric layer 126b is or comprises silicon nitride, silicon carbide, silicon oxynitride, some other suitable material, or any combination thereof.

[0128] As shown in the cross-sectional view 2900 of Figure 29, the second etch stop layer 128b is patterned to remove the second etch stop layer 128b from the top of the semiconductor channel 114. Furthermore, patterning partially removes the second etch stop layer 128b from the sidewalls of the semiconductor channel 114. In some embodiments, after patterning, the second etch stop layer 128b has a substantially uniform height throughout. Patterning can be performed, for example, by lithography / etching processes or some other suitable patterning process.

[0129] As shown in the cross-sectional view 3000 of Figure 30, a conductive layer 116l is deposited over the second etch stop layer 128b and the semiconductor channel 114, and further scribes lines on the sidewalls of the semiconductor channel 114. The conductive layer 116l can be deposited, for example, by ALD and / or some other suitable deposition process. In some embodiments, the conductive layer 116l is or comprises titanium nitride, tantalum nitride, molybdenum nitride, tungsten nitride, aluminum, tungsten, copper, molybdenum, some other suitable metal or metal nitride, or any combination thereof.

[0130] As shown in the cross-sectional view 3100 of Figure 31, the conductive layer 116l is patterned to form a pair of third conductors 116 on the semiconductor channel 114. Patterning can be performed, for example, by a lithography / etching process or some other suitable patterning process. In some cases, the patterning is performed by a lithography / etching process, and the second etch stop layer 128b can, for example, act as an etch stop during the etching of the conductive layer 116l.

[0131] Collectively, the second conductor 110, semiconductor channel 114, third conductor 116, gate electrode 118, and gate dielectric layer 120 form a pair of GAA transistors 106 on the resistor 104. Furthermore, the resistor 104 and the GAA transistors 106 form a pair of vertical GAA memory cells 102. The vertical GAA memory cells 102 can, for example, be PUF devices and / or OTP memory cells.

[0132] The resistance of a vertical GAA memory cell 102 can be inherently random due to manufacturing variations. This is reflected in the different distances from a point on the second conductor 110 to the lower layer of the first conductor 108. A larger distance results in more dielectric material separating the first and second conductors, and therefore a larger resistance. A smaller distance results in less dielectric material separating the first and second conductors, and therefore a smaller resistance. Therefore, when a vertical GAA memory cell is used as a PUF device, the resistance can be used to generate a PUF value.

[0133] In some embodiments, a PUF value for a vertical GAA memory cell is generated by applying a low voltage across a resistor of the vertical GAA memory cell and comparing the resulting current with a reference current. A PUF value of "0" is generated if the resulting current is less than the reference current, and a PUF value of "1" is generated if the resulting current is more than the reference current, and vice versa. The low voltage can be, for example, low enough not to cause dielectric breakdown of the insulating structure.

[0134] It is understood that the resistance of the vertical GAA memory cell 102 has high stability. For example, the resistance is unaffected or substantially unaffected by environmental conditions. Therefore, the PUF value can have high stability. This high stability of the PUF value can be attributed, for example, to the fact that the PUF value is generated from a low number of functional components. For example, the PUF value can be generated from only two functional components: a resistor and a GAA transistor. In contrast, an SRAM cell that generates its PUF value from six or more transistors may produce a PUF value with low stability.

[0135] When the vertical GAA memory cell 102 is formed as described above, the vertical GAA memory cell 102 is in HRS. However, a vertical GAA memory cell may irreversibly change to LRS by applying a high voltage across the resistor of the vertical GAA memory cell. The high voltage burns a portion of the insulating structure separating the tip of the second conductor from the first conductor, thus resulting in low conductivity from the tip to the first conductor. When a vertical GAA memory cell is used as an OTP memory cell, HRS and LRS can be used to represent data. HRS can, for example, represent logic "0", and LRS can, for example, represent logic "1", or vice versa.

[0136] As shown in the cross-sectional view 3200 of Figure 32, a third interconnect dielectric layer 126c is deposited covering the third conductor 116 and the second etch stop layer 128b.

[0137] As shown in the cross-sectional view 3300 of Figure 33, planarization is performed into the third interconnect dielectric layer 126c to planarize a top surface of the third interconnect dielectric layer 126c. Planarization can be performed, for example, by CMP and / or some other suitable planarization process.

[0138] As shown in the cross-sectional view 3400 of Figure 34, a via 124 of an interconnect structure and additional lines 418 of the interconnect structure are formed in a second interconnect dielectric layer 126b, a third interconnect dielectric layer 126c, and a second etch stop layer 128b. The additional lines 418 form a horizontal line Mx+1 at the top of the third interconnect dielectric layer 126c. The via 124 forms a via level Vy between the horizontal line Mx and the horizontal line Mx+1 and extends from the additional lines 418 to the gate electrode 118 and the third conductor 116, respectively. X is an integer representing the horizontal line level, and y is an integer representing the horizontal via level.

[0139] The process for forming the via level Vy and line level Mx+1 can, for example, involve patterning a second interconnect dielectric layer 126b and a third interconnect dielectric layer 126c, as well as a second etch stop layer 128b, to form an opening having a profile matching the via level Vy and line level Mx+1. Subsequently, a conductive layer can be deposited to fill the opening, and planarization can be performed to flush a top surface of the conductive layer with a top surface of the third interconnect dielectric layer 126c. However, other suitable processes are feasible.

[0140] As shown in the cross-sectional view 3500 of Figure 35, additional dielectric material is deposited to extend the third interconnect dielectric layer 126c above the horizontal line Mx+1. Furthermore, in some embodiments, planarization is performed to planarize a top surface of the third interconnect dielectric layer 126c. Planarization can be performed, for example, by CMP and / or some other suitable planarization process.

[0141] As shown in the cross-sectional view 3600 of Figure 36, an additional via 124 and an additional line 418 of an interconnect structure are formed in the third interconnect dielectric layer 126c. The additional line 418 forms a line level Mx+2 at the top of the third interconnect dielectric layer 126c. The additional via 124 forms a via level Vy+1 between the line level Mx+1 and the line level Mx+2 to interconnect these line levels. x is an integer representing the line level, and y is an integer representing the via level. The process used to form the via level Vy+1 and the line level Mx+2 can, for example, be the same as the process used to form the via level Vy and the line level Mx+1. However, other suitable processes are feasible.

[0142] As shown in the cross-sectional view 3700 of Figure 37, the operations described with respect to Figures 35 and 36 are repeated. These operations are repeated to further extend the third interconnect dielectric layer 126c, and additional vias 124 and additional lines 418 are formed, respectively, forming via level Vy+2 and line level Mx+3. In particular, the via at via level Vy+2 is outside the cross-sectional view 3700 of Figure 37. In an alternative embodiment, the operations described with respect to Figures 35 and 36 are not repeated, or are repeated two or more times.

[0143] While Figures 12 through 37 are described with reference to the method, it is understood that the structures shown in these figures are not limited to this method but may be independent of it. Although Figures 12 through 37 depict a series of operations, it is understood that the order of operations may be changed in other embodiments. While Figures 12 through 37 show and describe a specific set of operations, some operations shown and / or described may be omitted in other embodiments. Furthermore, operations not shown and / or described may be included in other embodiments.

[0144] Referring to FIG38, a block diagram 3800 is provided for some embodiments of the methods of FIG12 to FIG37.

[0145] At 3802, a first interconnect dielectric layer is patterned to form a trench exposing a first conductor, wherein the first conductor corresponds to a line of a partially formed interconnect structure. See Figures 12 and 13 for examples.

[0146] At 3804, an insulating layer is deposited over the first interconnect dielectric layer and trenches are etched, wherein a seam is formed in the trenches during deposition. See Figure 14 for an example.

[0147] At 3806, the insulating layer is etched back to remove the insulating layer from the top of the first interconnect dielectric layer and open the seam. See Figure 15 for an example.

[0148] At 3808, a second conductor is formed to fill an unfilled portion of the trench above the insulating layer, wherein the width of the second conductor decreases toward the first conductor to form a tip. See Figures 16 and 17 for examples.

[0149] At 3810, a first stop layer is formed on top of the second conductor and the first interconnect dielectric layer. See Figure 18 for an example.

[0150] At 3812, a semiconductor channel is formed extending through the first etch stop layer to the second conductor. See Figures 19 to 21 for examples.

[0151] At 3814, a gate stack is formed on top of the semiconductor channel and on the sidewall of the semiconductor channel. See Figures 22 and 23 for examples.

[0152] At 3816, a second interconnect dielectric layer is formed to cover the lower sidewall portion of the gate stack, leaving the upper sidewall portion of the gate stack exposed. See Figures 24 to 26 for examples.

[0153] At 3818, a portion of the gate stack, including the uppermost sidewall portion, is removed. See Figure 27 for an example.

[0154] At 3820, a second etch stop layer is formed over the gate stack and the second interconnect dielectric layer, and has a top surface recessed relative to a top surface of the semiconductor channel. See Figures 28 and 29 for examples.

[0155] At 3822, a third conductor is formed on top of the semiconductor channel. See Figures 30 and 31 for examples.

[0156] At 3824, the interconnect structure is completed on top of the third conductor. See Figures 32 to 37 for examples.

[0157] Although block diagram 3800 of Figure 38 is illustrated and described herein as a series of operations or events, it is understood that the order of such operations or events illustrated should not be construed as limiting. For example, some operations may occur in a different order and / or simultaneously with other operations or events, rather than those illustrated and / or described herein. Furthermore, not all operations shown in the diagrams may require the implementation of one or more aspects or embodiments described herein; one or more operations described herein may be performed in one or more separate operations and / or stages.

[0158] Referring to Figures 39 to 42, a series of cross-sectional views 3900 to 4200 are provided for some first alternative embodiments of the methods of Figures 12 to 37. Such embodiments may be employed, for example, to form interconnect structures such as those in Figures 6A, 8A, 10A, or 11A, or some other suitable interconnect structures.

[0159] As shown in the cross-sectional view 3900 of Figure 39, the operation described with respect to Figures 12 to 34 is performed. The operation is performed as described with respect to Figures 12 to 34, except that the via horizontal Vy does not extend to the third conductor 116 and the line horizontal Mx+1 is not electrically coupled to the third conductor 116 through the via.

[0160] As shown in the cross-sectional view 4000 of Figure 40, the operation described in Figure 35 is performed to extend the third interconnect dielectric layer 126c above the via level Vy and the line level Mx+1.

[0161] As shown in the cross-sectional view 4100 of Figure 41, the operations described with respect to Figure 36 are performed to form a via level Vy+1 and a line level Mx+2. The operations are performed as described with respect to Figure 36, except that forming the via level Vy+1 includes a via extending from the line level Mx+2 to the third conductor 116.

[0162] As shown in the cross-sectional view 4200 of Figure 42, the operations described in Figure 37 are performed to form the through-hole horizontal Vy+2 and the line horizontal Mx+3.

[0163] While Figures 39 to 42 are described with reference to the method, it is understood that the structures shown in these figures are not limited to this method but may be independent of it. Although Figures 39 to 42 depict a series of operations, it is understood that the order of operations may be changed in other embodiments. While Figures 39 to 42 show and describe a specific set of operations, some operations shown and / or described may be omitted in other embodiments. Furthermore, operations not shown and / or described may be included in other embodiments.

[0164] Referring to Figures 43 to 48, a series of cross-sectional views 4300 to 4800 are provided for some second alternative embodiments of the methods of Figures 12 to 37. Such embodiments may be employed, for example, to form a vertical GAA memory cell as shown in Figure 8B or Figure 10B.

[0165] As shown in the cross-sectional view 4300 of Figure 43, the operation described with respect to Figures 12 to 16 is performed. The operation is performed as described with respect to Figures 12 to 16, except that a sacrificial layer 4302l is used instead of the conductive layer 110l. The sacrificial layer 4302l can be, for example, polycrystalline silicon and / or some other suitable sacrificial material.

[0166] As shown in the cross-sectional view 4400 of Figure 44, planarization is performed into the sacrificial layer 4302l. Planarization can be performed, for example, by CMP or some other suitable planarization process. Planarization removes the sacrificial layer 4302l from the top of the first interconnect dielectric layer 126a and forms a pair of sacrificial structures 4302. The sacrificial structures 4302 are respectively overlaid on the first conductor 108 and separated from the first conductor 108 by the insulating structure 112. Furthermore, the width of the sacrificial structure 4302 decreases from one top of the first interconnect dielectric layer 126a toward the first conductor 108 to reach a certain point.

[0167] As shown in the cross-sectional view 4500 of Figure 45, the operations described with respect to Figures 18 and 19 are performed to form a first etch stop layer 128a with an opening 1902. Subsequently, the sacrificial structure 4302 is removed to partially clear the trench 1302 at the opening 1902. Removal can be performed, for example, by an etching process and / or by some other suitable removal process.

[0168] As shown in the cross-sectional view 4600 of Figure 46, a semiconductor layer 2002 is deposited on top of the first etch stop layer 128a, and further fills the remaining portion of the opening 1902 and trench 1302 on top of the insulator structure 112. In some embodiments, a top surface of the semiconductor layer 2002 is further planarized by planarization. Planarization may be performed, for example, by CMP and / or some other suitable planarization process.

[0169] As shown in the cross-sectional view 4700 of Figure 47, the semiconductor layer 2002 is patterned to form a pair of semiconductor channels 114 and a pair of second conductors 110. Patterning can be performed, for example, by a lithography / etching process or some other suitable patterning process. In some cases, the patterning is performed by a lithography / etching process, and the first etch stop layer 128a can, for example, serve as an etch stop during the etching of the semiconductor layer 2002.

[0170] The paired second conductors 110 correspond to portions of the semiconductor layer 2002 in FIG. 44 that partially fill the trench 1302 and form a pair of resistors 104 with an insulating structure 112 and a first conductor 108. Semiconductor channels 114 are respectively overlaid on the second conductors 110 and correspond to portions of the semiconductor layer 2002 outside the trench 1302 in FIG. 44. In some embodiments, the patterning is such that the semiconductor channels 114 have individual widths that are the same as or similar to the individual widths of the openings 1902 (see FIG. 43).

[0171] As shown in the cross-sectional view 4800 of Figure 48, the operations described with respect to Figures 22 to 37 are performed to complete the vertical GAA memory cell 102 and further complete the interconnect structure (e.g., formed from line 418 and via 124).

[0172] While Figures 43 to 48 are described with reference to the method, it is understood that the structures shown in these figures are not limited to this method but may be independent of it. Although Figures 43 to 48 depict a series of operations, it is understood that the order of operations may be changed in other embodiments. While Figures 43 to 48 show and describe a specific set of operations, some operations shown and / or described may be omitted in other embodiments. Furthermore, operations not shown and / or described may be included in other embodiments.

[0173] Referring to Figures 49 to 51, a series of cross-sectional views 4900 to 5100 are provided for some embodiments of a method for forming an integrated wafer, in which a pair of vertical GAA memory cells are on a front side of a logic device. The integrated wafer corresponds to Figure 4, but may alternatively correspond to any of, for example, Figures 6A to 6C, Figure 8A, and Figure 8B.

[0174] As shown in the cross-sectional view 4900 of Figure 49, a first logic element 402a and a second logic element 402b are formed on a semiconductor substrate 404. The first logic element 402a and the second logic element 402b are separated from each other by an isolation structure 408. The first logic element 402a and the second logic element 402b can be, for example, a planar FET, a fin field-effect transistor, a GAAFET, some other suitable type of logic device and / or transistor, or any combination thereof.

[0175] In some embodiments, the first logic element 402a and the second logic element 402b include individual gate electrodes 410, individual gate dielectric layers 412, and individual pairs of source / drain regions 414. The pairs of source / drain regions 414 are inserted into a top of the semiconductor substrate 404. The gate electrodes 410 are respectively coated on the gate dielectric layers 412 and are respectively located between the pairs of source / drain regions 414. In some embodiments, the first logic element 402a and the second logic element 402b further include individual wells 416 respectively covered under the gate electrodes 410 in the semiconductor substrate 404.

[0176] As shown in the cross-sectional view 5000 of Figure 50, an interconnection structure 406 is partially formed on the first logic element 402a and the second logic element 402b, on a front side FS of the first logic element 402a, facing a rear side BS of the first logic element 402a.

[0177] Interconnect structure 406 includes a plurality of lines 418 and a plurality of vias 124 in a first interconnect dielectric layer 126a. The plurality of lines 418 are divided into a plurality of line levels, and the plurality of vias 124 are divided into a plurality of via levels, which are alternately stacked with the plurality of line levels. The line levels from a bottom to a top of interconnect structure 406 are labeled M1, M2, and M3. Furthermore, two lines in line level M3 correspond to a pair of first conductors 108 subsequently formed for a vertical GAA memory cell. The via levels from the bottom to the top of interconnect structure 406 are labeled V0, V1, and V2.

[0178] As shown in the cross-sectional view 5100 of Figure 51, the operations described with respect to Figures 12 through 37 are performed. This forms a pair of vertical GAA memory cells 102 and completes the interconnect structure 406. The interconnect structure 406, as completed, further includes additional via levels V3, V4, V5 and additional line levels M4, M5, M6. In an alternative embodiment, the operations described with respect to Figures 39 through 42 are performed in reverse, or the operations described with respect to Figures 43 through 48 are performed in reverse.

[0179] While Figures 49 to 51 are described with reference to the method, it is understood that the structures shown in these figures are not limited to this method but may be independent of it. Although Figures 49 to 51 depict a series of operations, it is understood that the order of operations may be changed in other embodiments. While Figures 49 to 51 show and describe a specific set of operations, some operations shown and / or described may be omitted in other embodiments. Furthermore, operations not shown and / or described may be included in other embodiments.

[0180] Referring to Figures 52 to 64, a series of cross-sectional views 5200 to 6400 are provided for some embodiments of a method for forming an integrated wafer, in which pairs of vertical GAA memory cells are on a rear side of a logic device. The integrated wafer corresponds to Figure 9, but may alternatively correspond to any of, for example, Figures 10A to 10C, Figure 11A, and Figure 11B.

[0181] As shown in the cross-sectional view 5200 of Figure 52, a first logic element 902a and a second logic element 902b are formed adjacent to a semiconductor substrate 5202. The semiconductor substrate 5202 may, for example, be or contain silicon and / or some other suitable semiconductor material. The first logic element 902a and the second logic element 902b are GAAFETs, but may alternatively be, for example, planar FETs, fin field-effect transistors, some other suitable types of logic devices and / or transistors, or any combination thereof.

[0182] The first logic element 902a and the second logic element 902b each include a plurality of semiconductor channels 908, a separate guard layer 910, a separate gate electrode 912, a separate gate dielectric layer 914, and corresponding source / drain regions 916. The semiconductor channel 908 of one of the first logic elements 902a and the second logic element 902b is vertically stacked on its counterpart in the guard layer 910. Furthermore, the semiconductor channel 908 of one of the first logic elements 902a and the second logic element 902b is laterally sandwiched between two source / drain regions 916 and vertically separated from each other by their counterparts in the gate electrode 912. The gate electrode 912 is separated from the semiconductor channel 908 by the gate dielectric layer 914.

[0183] The first logic element 902a and the second logic element 902b further include corresponding individual first spacer structures 918, individual second spacer structures 920, and individual third spacer structures 922. The first spacer structures 918 separate corresponding semiconductor channels 908 on the sidewalls of the gate electrode 912. The second spacer structures 920 cover the semiconductor channels 908 on the sidewalls of the gate electrode 912, and the third spacer structures 922 cover the semiconductor channels 908 on the sidewalls of the second spacer structures 920.

[0184] An isolation structure 907 surrounds the bottom of the first logic element 902a and the second logic element 902b, below the source / drain region 916. Furthermore, an inter-dielectric layer 936 surrounds the top of the first logic element 902a and the second logic element 902b, above the source / drain region 916.

[0185] As shown in the cross-sectional view 5300 of Figure 53, a first interconnect structure 906 is formed on top of a first logic element 902a and a second logic element 902b, on a front side FS of the first logic element 902a, facing a rear side BS of the first logic element 902a. Furthermore, the first interconnect structure 906 is formed in a dielectric structure. The dielectric structure includes a plurality of interconnect dielectric layers 938 and a plurality of etch stop layers 940, which may alternatively be stacked vertically.

[0186] The first interconnect structure 906 includes a plurality of conductive features, including a plurality of first horizontal contacts 924, a plurality of second horizontal contacts 926, a wire 928, and a via 930. The second horizontal contacts 926 overlay and space from the gate electrode 912, and the first horizontal contacts 924 extend from the second horizontal contacts 926 to the gate electrode 912. The wire 928 is spaced over the second horizontal contacts 926, and the via 930 extends from the wire 928 to each of the second horizontal contacts 926. In some embodiments, the wire 928 may also be considered as an RDL. Furthermore, while only one via level and only one wire level are shown, more via levels and / or more wire levels are feasible.

[0187] As shown in the cross-sectional view 5400 of Figure 54, a heat sink conductor 932 and a bonding dielectric layer 942 are formed on a carrier substrate 904. The heat sink conductor 932 is inserted into the bonding dielectric layer 942 such that a top surface of the heat sink conductor 932 is flush with a top surface of the bonding dielectric layer 942.

[0188] As shown in the cross-sectional view 5500 of Figure 55, the structure of Figure 53 is vertically flipped and bonded to the structure of Figure 54 through a bonding interface 934. The bonding interface 934 includes a dielectric-to-dielectric interface between one of the bonding dielectric layer 942 and the interconnect dielectric layer 938. The bonding interface 934 further includes a conductor-to-conductor interface between the heat sink conductor 932 and the wire 928.

[0189] As shown in the cross-sectional view 5600 of Figure 56, the semiconductor substrate 5202 is thinned from the rear side BS of the first logic element 902a. Thinning can be performed, for example, by CMP and / or some other suitable planarization.

[0190] As shown in the cross-sectional view 5700 of Figure 57, the semiconductor substrate 5202 is removed, thereby exposing the isolation structure 907 and the protective layer 910. Removal can be performed, for example, by etching V and / or some other suitable removal process.

[0191] As shown in the cross-sectional view 5800 of Figure 58, a first interconnect dielectric layer 126a is deposited on top of the isolation structure 907 and the protective layer 910.

[0192] As shown in the cross-sectional view 5900 of Figure 59, a contact plug 944 is formed and inserted into the first interconnect dielectric layer 126a. The process for forming the contact plug 944 may, for example, include patterning the first interconnect dielectric layer 126a to form an opening exposing a source / drain region common to the first logic element 902a and the second logic element 902b. A conductive layer may be deposited to fill the opening and cover the first interconnect dielectric layer 126a, after which planarization may be performed into the conductive layer to remove the conductive layer from the top of the first interconnect dielectric layer. However, other suitable processes are feasible.

[0193] As shown in the cross-sectional view 6000 of Figure 60, additional dielectric material is deposited on top of the contact plug 944 to extend the first interconnect dielectric layer 126a over the contact plug 944. Furthermore, a line 418 is formed and inserted into the first interconnect dielectric layer 126a, covering and extending from the contact plug 944. The contact plug 944 and the line 418 partially form a second interconnect structure 406, with the line 418 corresponding to a line level M0 of the second interconnect structure 406. The line 418 can be, for example, formed by patterning the first interconnect dielectric layer 126a to form an opening covering the contact plug and subsequently filling the opening with a conductive material.

[0194] As shown in the cross-sectional view 6100 of Figure 61, additional dielectric material is deposited on top of line level M0. Furthermore, additional lines 418 and a via 124 are formed and inserted into the first interconnect dielectric layer 126a, covering the line level M0 to extend the second interconnect structure 406. The additional lines 418 form a line level M1 above the line level M0, and the via 124 forms a via level V0 extending between the line level M0 and the line level M1. The additional lines 418 and via 124 can, for example, be formed by patterning the first interconnect dielectric layer 126a to form openings covering the line level M0 and subsequently filling the openings with a conductive material.

[0195] As shown in the cross-sectional view 6200 of Figure 62, the operation described with respect to Figure 61 is repeated to extend the second interconnect structure 406 with an additional line 418 and an additional via 124. The additional line 418 forms a line horizontal M2, and the additional via 124 forms a via horizontal V1 between the line horizontal M1 and the line horizontal M2.

[0196] As shown in the cross-sectional view 6300 of Figure 63, additional dielectric material is deposited on top of the horizontal line M2 to extend the first interconnect dielectric layer 126a.

[0197] As shown in the cross-sectional view 6400 of Figure 64, the operations described with respect to Figures 12 through 37 are performed. This forms a pair of vertical GAA memory cells 102 and completes the second interconnect structure 406. The second interconnect structure 406, as completed, further includes additional via levels V2, V3, V4 and additional line levels M3, M4, M5. In an alternative embodiment, the operations described with respect to Figures 39 through 42 are performed in reverse, or the operations described with respect to Figures 43 through 48 are performed in reverse.

[0198] While Figures 52 to 64 are described with reference to the method, it is understood that the structures shown in these figures are not limited to this method but may be independent of it. Although Figures 52 to 64 depict a series of operations, it is understood that the order of operations may be changed in other embodiments. While Figures 52 to 64 show and describe a specific set of operations, some operations shown and / or described may be omitted in other embodiments. Furthermore, operations not shown and / or described may be included in other embodiments.

[0199] In some embodiments, this disclosure relates to a memory cell comprising: a lower conductor; an intermediate conductor overlying the lower conductor and decreasing in width toward the lower conductor to a point spaced apart above the lower conductor; an insulating structure between the lower conductor and the intermediate conductor; a semiconductor channel overlying the intermediate conductor; a gate electrode laterally surrounding the semiconductor channel on a sidewall of the semiconductor channel; a gate dielectric layer separating the gate electrode from the semiconductor channel; and a higher conductor on top of the semiconductor channel. In some embodiments, the intermediate conductor and the semiconductor channel correspond to different regions of a common semiconductor layer. In some embodiments, the intermediate conductor has a different material composition than the semiconductor channel. In some embodiments, the intermediate conductor has the same material type as the gate electrode and / or the upper conductor. In some embodiments, the insulating structure extends along the sidewall of the intermediate conductor and directly contacts the lower conductor and the intermediate conductor. In some embodiments, the upper conductor wraps around a top of the semiconductor channel from the sidewall to a top surface of the semiconductor channel. In some embodiments, the memory cell further includes an etch stop layer on the sidewall of the semiconductor channel, wherein the etch stop layer separates the uppermost conductor from the gate dielectric layer and further separates the uppermost conductor from the gate electrode.

[0200] In some embodiments, this disclosure pertains to an integrated chip, comprising: a first memory cell including a first resistor and a first transistor atop the first resistor, wherein the first resistor includes a first conductor and shares a second conductor with the first transistor, wherein the second conductor overlays the first conductor and has a first tip extending toward the first conductor; and a second memory cell including a second resistor and a second transistor atop the second resistor, wherein the second resistor includes a third conductor and shares a fourth conductor with the second transistor, wherein the fourth conductor overlays the third conductor and has a second tip extending toward the third conductor; wherein the first tip and the second tip have different heights. In some embodiments, the first transistor and the second transistor include individual, continuously connected gate electrodes. In some embodiments, the integrated wafer further includes: a first conductive line and a second conductive line flush with each other and superimposed on the first transistor; and a first via and a second via extending from the first conductive line and the second conductive line to a gate electrode and a source / drain electrode of the first transistor, respectively. In some embodiments, the integrated wafer further includes: a first conductive line and a second conductive line superimposed on the first transistor, wherein a top surface of the first conductive line is recessed relative to a bottom surface of the second conductive line; and a first conductive hole and a second conductive hole extending from the first conductive line and the second conductive line to a gate electrode and a source / drain electrode of the first transistor, respectively. In some embodiments, the integrated wafer further includes: a gate all-ring (GAA) transistor having a front side and a rear side opposite to the front side; a first interconnect structure on the front side of the GAA transistor, wherein the first interconnect structure includes a conductive feature extending to a gate electrode of the GAA transistor; and a second interconnect structure on the rear side of the GAA transistor, wherein the second interconnect structure surrounds and is electrically coupled to the first memory cell and the second memory cell. In some embodiments, the integrated wafer further includes: an interconnect structure overlaid on a semiconductor substrate and including a plurality of conductive lines and a plurality of conductive vias alternately stacked, wherein the first conductor and the third conductor correspond to two of the plurality of conductive lines.

[0201] In some embodiments, this disclosure provides a method for forming a memory cell, comprising: patterning a first dielectric layer to form a trench exposing a lower conductor; depositing an insulating layer to fill the trench, wherein a seam is formed and sealed in the trench during the deposition of the insulating layer; etching back the insulating layer to remove the insulating layer from a top surface of the first dielectric layer and open the seam; after the etching back, forming an intermediate conductor to fill and follow an unfilled portion of the trench; forming a semiconductor channel on top of the intermediate conductor; forming a gate electrode around the semiconductor channel; and forming an upper conductor on top of the semiconductor channel. In some embodiments, the width of the unfilled portion of the trench decreases toward the lower conductor to reach a point spaced apart above the lower conductor. In some embodiments, forming the intermediate conductor comprises: depositing a conductive layer to fill the unfilled portion of the trench; and performing a planarization into the conductive layer to remove the conductive layer from the top of the first dielectric layer, wherein a portion of the conductive layer in the trench corresponds to the intermediate conductor. In some embodiments, forming the semiconductor channel includes: depositing a semiconductor layer over the intermediate conductor; and patterning the semiconductor layer into a columnar structure on top of the intermediate conductor, wherein the columnar structure corresponds to the semiconductor channel. In some embodiments, forming the intermediate conductor includes: depositing a sacrificial layer to fill the unfilled portion of the trench; performing planarization into the sacrificial layer to remove the sacrificial layer from top of the first dielectric layer; depositing an etch stop layer over the first dielectric layer and the sacrificial layer; patterning the etch stop layer to form an opening exposing the sacrificial layer; and replacing the sacrificial layer with a semiconductor material corresponding to the intermediate conductor. In some embodiments, forming the gate electrode includes: depositing a conductive layer over the semiconductor channel and scribing it onto the sidewalls of the semiconductor channel; and etching back the conductive layer to recess a top surface of the conductive layer relative to a top surface of the semiconductor channel, wherein a portion of the conductive layer remaining on the sidewalls of the semiconductor channel corresponds to the gate electrode. In some embodiments, the method further includes depositing an etch stop layer over a top surface of the gate electrode, wherein forming the uppermost conductor includes: depositing a conductive layer over the semiconductor channel and the etch stop layer, and further over the sidewalls of the semiconductor channel; and patterning the conductive layer into the uppermost conductor.

[0202] The foregoing outlines the features of several embodiments to enable those skilled in the art to better understand various aspects of this disclosure. Those skilled in the art will recognize that this disclosure can readily serve as the basis for designing or modifying other processes and structures to achieve the same objectives and / or realize the same advantages of the embodiments described in this disclosure. Those skilled in the art should also recognize that such equivalent structures do not depart from the spirit and scope of this disclosure, and various changes, substitutions, and modifications can be made to this disclosure without departing from its spirit and scope.

[0203] 100: Sectional View 102: Vertical GAA memory unit 104: Resistor 106:GAA transistor 108: First Conductor 110: Second conductor 112: Insulator Structure 114: Semiconductor Channel 116: Third conductor 118: Gate electrode 120: Gate dielectric layer 124: Through hole 124a: First through hole 124b: Second through hole 126: Interconnect dielectric layer 126a: First interconnect dielectric layer 126b: Second interconnect dielectric layer 126c: Third interconnect dielectric layer 128a: First etch stop layer 128b: Second etch stop layer 200A, 200B: Top Layout Diagram 300: Circuit Diagram 400: Sectional View 402a: First Logic Element 402b: Second Logic Element 404: Semiconductor substrate 406: Interconnection Structure 408: Isolation Structure 410: Gate electrode 412: Gate dielectric layer 414: Source / Drain Region 416: Well 418: Line 500: Circuit Diagram 600A-600C, 800A, 800B, 900: Sectional View 700: Circuit Diagram 902: Conductor for heat sink 902a: First Logic Element 902b: Second Logic Element 904: Carrier substrate 906: First interconnect structure 907: Isolation Structure 908: Semiconductor Channel 910: Protective layer 912: Gate electrode 914: Gate Dielectric Layer 916: Source / Drain Region 918: First spacer structure 920: Second spacer structure 922: Third spacer structure 924: First level contact 926: Second level contact 928: Line 930: Through hole 932: Heat sink conductor 934: Bonding Interface 936: Interlayer dielectric layer 938: Interconnect dielectric layer 940: Etching Stop Layer 942: Bonding Dielectric Layer 944: Contact embolism 1000A-1000C, 1100A, 1100B, 1200-3700, 3900-6400: Sectional View 110l: Conductive layer 112l: Insulating layer 116l: Conductive layer 120l: Dielectric layer 1302: Trench 1402: Seam 118l: Conductive layer 1902: Opening 2002: Semiconductor Layer 3800: Block Map 4302l: Sacrifice Layer 4302: Sacrifice Structure 5202: Semiconductor substrate M0-M5, Mx, Mx+1, Mx+2: Line horizontal V0-V4, Vy, Vy+1: Through-hole horizontal FS: Front BS: rear side BL: Bitline SL: Source Line WL: Character Line Wsc: width Wtr: width

Claims

1. A memory cell comprising: a lower conductor; an intermediate conductor overlying the lower conductor and having a width decreasing toward the lower conductor to a point spaced apart above the lower conductor; an insulator structure between the lower conductor and the intermediate conductor; a semiconductor channel overlying the intermediate conductor; a gate electrode laterally surrounding the semiconductor channel on a sidewall of the semiconductor channel; a gate dielectric layer separating the gate electrode from the semiconductor channel; and an upper conductor on top of the semiconductor channel.

2. The memory cell of claim 1, wherein the intermediate conductor and the semiconductor channel correspond to different regions of a common semiconductor layer.

3. The memory cell of claim 1, wherein the intermediate conductor has a different material composition than the semiconductor channel.

4. The memory cell of claim 1, wherein the intermediate conductor has the same material type as the gate electrode and / or the uppermost conductor.

5. The memory cell of claim 1, wherein the insulating structure extends along the sidewall of the intermediate conductor and directly contacts the lower conductor and the intermediate conductor.

6. The memory cell of claim 1, wherein the uppermost conductor is wound around a top of the semiconductor channel from the sidewall of the semiconductor channel to a top surface of the semiconductor channel.

7. The memory cell of claim 1 further comprises: an etch stop layer on the sidewall of the semiconductor channel, wherein the etch stop layer separates the uppermost conductor from the gate dielectric layer, and further separates the uppermost conductor from the gate electrode.

8. An integrated chip, comprising: a first memory cell including a first resistor and a first transistor on top of the first resistor, wherein the first resistor includes a first conductor and shares a second conductor with the first transistor, wherein the second conductor overlays the first conductor and has a first tip extending toward the first conductor, and the first conductor and the second conductor are spaced apart by an insulator structure; and a second memory cell including a second resistor and a second transistor on top of the second resistor, wherein the second resistor includes a third conductor and shares a fourth conductor with the second transistor, wherein the fourth conductor overlays the third conductor and has a second tip extending toward the third conductor, and the third conductor and the fourth conductor are spaced apart by another insulator structure; wherein the first tip and the second tip have different heights.

9. The integrated wafer of claim 8, wherein the first transistor and the second transistor share a common gate electrode.

10. A method for forming a memory cell, comprising: patterning a first dielectric layer to form a trench exposing a lower conductor; depositing an insulating layer to fill the trench, wherein a seam is formed and sealed in the trench during the deposition of the insulating layer; etching back the insulating layer to remove the insulating layer from a top surface of the first dielectric layer and open the seam; forming an intermediate conductor after the etching back to fill and follow an unfilled portion of the trench; forming a semiconductor channel on top of the intermediate conductor; forming a gate electrode around the semiconductor channel; and forming an upper conductor on top of the semiconductor channel.

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