Semiconductor devices and methods of formation

Abstract

A trench capacitor structure is formed in a semiconductor device, having a deep trench structure including multiple interconnect trench segments in a top view of the trench capacitor structure. The interconnect trench segments provide a larger surface area along the sidewalls for the electrode layers and insulating layers of the trench capacitor structure, thereby increasing the capacitance of the trench capacitor structure. The interconnect trench segments may be contained within the perimeter of the trench capacitor structure to achieve a compact lateral footprint. Furthermore and / or alternatively, the vertical dimension of the trench capacitor structure (and therefore the capacitance of the trench capacitor structure) may be increased by extending the deep trench structure of the trench capacitor structure entirely between the bonding structure of the semiconductor device and the underlying device layer of the semiconductor device.

Description

Technical Field

[0001] The embodiments of the present invention relate to a semiconductor device and a method for forming the same. Prior Technology

[0002] Semiconductor devices may include one or more capacitor structures in an interconnect layer (e.g., back-end layer or back-end region) above the device layer. These capacitor structures may perform and / or support one or more functions within the semiconductor device, such as memory (e.g., dynamic random access memory, DRAM), charge decoupling, analog-to-digital (A / D) conversion, and / or other functions. In some cases, capacitor structures may be included in the pixel sensor circuitry of an image sensor device to provide overflow photocurrent storage, thereby enabling increased full-well capacity of the pixel sensor circuitry. Summary of the Invention

[0003] Some embodiments described herein provide a semiconductor device. The semiconductor device includes a semiconductor layer. The semiconductor device includes one or more integrated circuit devices, at least located in or on the semiconductor layer. The semiconductor device includes an interconnect layer above the semiconductor layer. The semiconductor device includes a capacitor structure extending vertically through the interconnect layer. The capacitor structure includes a top electrode layer and an insulating layer located between a bottom electrode layer and the top electrode layer. The bottom electrode layer, the top electrode layer, and the insulating layer extend and conform to the cross-sectional profile of a deep trench. In a top view of the deep trench structure, the deep trench includes trench segments of multiple interconnects.

[0004] Some embodiments described herein provide a semiconductor device. The semiconductor device includes a semiconductor layer. The semiconductor device includes one or more integrated circuit devices, at least located in or on the semiconductor layer. The semiconductor device includes an interconnect layer above the semiconductor layer. The semiconductor device includes one or more conductive structures in the interconnect layer. The semiconductor device includes one or more bonding structures above the interconnect layer. The semiconductor device includes a trench capacitor structure extending vertically through the interconnect layer, wherein the top of the trench capacitor structure is coupled to one of the one or more bonding structures, and the bottom of the trench capacitor structure is coupled to a gate structure of one or more integrated circuit devices.

[0005] Some embodiments described herein provide a method. The method includes forming one or more integrated circuit devices in a semiconductor layer of a semiconductor device. The method includes forming an interconnect layer of the semiconductor device above the semiconductor layer. The method includes forming a trench through a plurality of dielectric layers of the interconnect layer to a gate structure of one of the one or more integrated circuit devices. The method includes forming a trench capacitor structure of the semiconductor device in the trench, such that the trench capacitor structure lands on the gate structure. The method includes forming a bonding structure of the semiconductor device on the trench capacitor structure. Simple Explanation of the Diagram

[0006] The best understanding of all aspects of this disclosure can be obtained from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that, according to industry standard practice, the various feature elements are not drawn to scale. In fact, for clarity, the dimensions of the various feature elements may be arbitrarily increased or decreased. Figure 1 is a schematic diagram of an embodiment of the semiconductor device described herein. Figures 2A and 2B are schematic diagrams of embodiments of the capacitor structure described herein. Figures 3A to 3E are schematic diagrams of top-view layout embodiments of the capacitor structure described in this article. Figures 4A to 4J are schematic diagrams of embodiments of the semiconductor device described herein. Figure 5 is a schematic diagram of an embodiment of another semiconductor device described herein. Figure 6 is a schematic diagram of an embodiment of another semiconductor device described herein. Figures 7A to 7E are schematic diagrams of embodiments of the semiconductor device described herein. Figures 8A and 8B are schematic diagrams of embodiments of the semiconductor device described herein. Figures 9A and 9B are schematic diagrams of embodiments of the semiconductor package described herein. Figures 10A and 10B are schematic diagrams of embodiments of the semiconductor package described herein. Figure 11 is an example process flow diagram related to the formation of a semiconductor device as described in this article. Implementation

[0007] The following disclosure provides numerous different embodiments or instances for implementing various features of the provided subject matter. Specific examples of elements and configurations are described below to simplify this disclosure. These are, of course, merely examples and are not intended to be limiting. For example, in the following description, the formation of a first feature above or on a second feature may include embodiments where the first and second features are in direct contact, and may also include embodiments where an additional feature may be formed between the first and second features such that the first and second features are not in direct contact. Furthermore, reference numerals and / or letters may be repeated throughout this disclosure. This repetition is for simplicity and clarity and does not in itself indicate a relationship between the various embodiments and / or configurations discussed.

[0008] Furthermore, spatially relative terms such as "below," "below," "lower," "above," and "upper" may be used herein to facilitate the description of the relationship between one element or feature shown in the figures and another (other) element or feature. These spatially relative terms are intended to also encompass different orientations of the device in use or operation, in addition to those shown in the figures. The device may have other orientations (rotated 90 degrees or in other orientations), and the spatially relative descriptive terms used herein shall be interpreted accordingly.

[0009] Capacitor structures may include metal-insulator-metal (MIM) structures, where an insulating layer is sandwiched between two conductive electrode layers. The capacitance of a capacitor structure (e.g., the amount of charge it can store) depends directly on the geometry of the conductive electrode layers. The larger the surface area of ​​the conductive electrode layers, the greater the capacitance. Therefore, increasing the size of the metal electrode layers can increase the capacitance of the capacitor structure.

[0010] However, increasing the lateral dimensions of the capacitor structure directly contradicts semiconductor design principles in the semiconductor industry, which aim to reduce the size of semiconductor devices to achieve lower power consumption, higher operating performance and efficiency, and / or enable semiconductor devices to be used in increasingly smaller form factor applications. Therefore, in some cases, the size of the capacitor structure can be increased vertically within the semiconductor device, allowing the capacitor structure to extend through multiple layers within the device. A deep trench capacitor (DTC) is a type of capacitor structure formed in a deep trench within a semiconductor device, with its electrode and insulating layers extending along and conforming to the contour of the trench. This allows for an increase in the area of ​​the conductive electrode layers (thus increasing capacitance) while minimizing the increase in the lateral dimensions of the capacitor structure.

[0011] In some embodiments described herein, a trench capacitor structure (e.g., a deep trench capacitor structure) is formed in a semiconductor device having a deep trench structure that includes multiple trench segments of interconnects in a top view of the trench capacitor structure. The trench segments of the interconnects provide a larger surface area along the sidewalls for the electrode layers and insulating layers of the trench capacitor structure, thereby increasing the capacitance of the trench capacitor structure. The trench segments of the interconnects may be contained within the perimeter of the trench capacitor structure to achieve a compact lateral footprint. Furthermore and / or alternatively, the vertical dimension of the trench capacitor structure (and thus the capacitance) may be increased by extending the deep trench structure of the trench capacitor structure entirely between the bonding structure of the semiconductor device and the underlying device layer of the semiconductor device. The bottom of the trench capacitor structure may be electrically connected to the gate structure of an integrated circuit device in the device layer.

[0012] Figure 1 is a schematic diagram of an exemplary embodiment 100 of the semiconductor device 102 described herein. The semiconductor device 102 may include system-on-chip (SoC) dies, such as logic dies, central processing unit (CPU) dies, graphics processing unit (GPU) dies, digital signal processing (DSP) dies, application-specific integrated circuit (ASIC) dies, and / or other types of SoC dies. Furthermore and / or alternatively, the semiconductor device 102 may include memory dies, input / output (I / O) dies, pixel sensor dies, and / or other types of semiconductor dies. Memory dies may include static random access memory (SRAM) dies, DRAM dies, NAND dies, high bandwidth memory (HBM) dies, and / or other types of memory dies. Generally, the semiconductor device 102 is a semiconductor device whose interconnect layer includes one or more capacitor structures.

[0013] As shown in FIG1, the semiconductor device 102 includes a device layer 104, an interconnect layer 106 and a bonding layer 108. The interconnect layer 106 is arranged perpendicularly to the device layer 104 in the semiconductor device 102 (e.g., in the z direction), and the bonding layer 108 is arranged perpendicularly to the interconnect layer 106 in the semiconductor device 102 (e.g., in the z direction).

[0014] Device layer 104 may also be referred to as the front end of line (FEOL) process of semiconductor device 102. Device layer 104 includes substrate layer 110. Substrate layer 110 may correspond to a portion of the semiconductor wafer forming semiconductor device 102. Substrate layer 110 may include silicon (Si) substrate, substrate formed of silicon-containing material, III-V compound semiconductor material substrate such as gallium arsenide (GaAs), silicon on insulator (SOI) substrate, or other types of semiconductor substrate. Substrate layer 110 may extend in semiconductor device 102 along the x-direction and / or y-direction.

[0015] Integrated circuit device 112 may be contained within and / or on substrate layer 110 in device layer 104 of semiconductor device 102. Integrated circuit device 112 may include front-end transistor structures (e.g., front-end planar transistor structures, front-end fin field-effect transistor (FinFET) structures, front-end gate all-around (GAA) transistor structures), pixel sensors, front-end capacitors, front-end resistors, front-end inductors, photodetectors, transceivers, transmitters, receivers, optical circuitry, and / or other types of front-end semiconductor devices. "Front-end semiconductor device" refers to a semiconductor device formed in device layer 104 of semiconductor device 102 (e.g., within and / or on substrate layer 110), and not a semiconductor device formed in interconnect layer 106 of semiconductor device 102.

[0016] A dielectric layer 114 is contained above a substrate layer 110. The dielectric layer 114 includes an interlayer dielectric (ILD) layer, an etch stop layer (ESL), and / or other types of dielectric layers. The dielectric layer 114 includes a dielectric material that allows for selective etching or etch-free treatment of portions of the substrate layer 110 and / or the integrated circuit device 112, and / or electrically isolates the integrated circuit device 112 within the device layer 104. The dielectric layer 114 includes silicon nitride (SixNy), oxides (e.g., silicon oxide (SiOx) and / or other oxide materials), and / or other types of dielectric materials. The dielectric layer 114 may extend in the semiconductor device 102 along the x-direction and / or the y-direction.

[0017] An interconnect layer 106 of semiconductor device 102 is located above substrate layer 110 and integrated circuit device 112 in the z-direction of semiconductor device 102. Integrated circuit device 112 is electrically coupled to interconnect layer 106. Interconnect layer 106 includes a plurality of dielectric layers (e.g., back-end dielectric layers) arranged in one direction (e.g., the z-direction) approximately perpendicular to substrate layer 110. The dielectric layers may include interlayer dielectric layers 116 and etch stop layers 118, which are alternately arranged in the z-direction. Interlayer dielectric layers 116 and etch stop layers 118 may extend in the x-direction and / or y-direction of semiconductor device 102.

[0018] Interlayer dielectric layers 116 may each comprise oxides (e.g., silicon oxide (SiO₂x) and / or other oxide materials), undoped silicate glass (USG), borosilicate glass (BSG), fluorosilicone glass (FSG), tetraethyl orthosilicate (TEOS), hydrosilsesquioxane (HSQ), and / or other suitable dielectric materials. In some embodiments, interlayer dielectric layers 116 comprise extremely low dielectric constant (ELK) dielectric materials with a dielectric constant less than about 2.5. Examples of extremely low dielectric materials include carbon-doped silicon oxide (C-SiO x), amorphous fluorinated carbon (aC xF y), poly(p-xylene), bisbenzocyclobutene (BCB), polytetrafluoroethylene (PTFE), silicon oxycarbon (SiOC) polymers, porous hydrosilsesquioxane (HSQ), porous methylsilsesquioxane (MSQ), porous polyaryl ether (PAE), and / or porous silicon oxide (SiO x), among others.

[0019] The etch stop layer 118 may each comprise silicon nitride (SixNy), silicon carbide (SiC), silicon oxynitride (SiON), and / or other suitable dielectric materials. In some embodiments, the interlayer dielectric layer 116 and the etch stop layer 118 comprise different dielectric materials to provide etch selectivity, enabling various structures to be formed in the interconnect layer 106.

[0020] Interconnect layer 106 includes multiple conductive structures. One or more conductive structures 120 are electrically coupled and / or physically coupled to one or more integrated circuit devices 112 in device layer 104. Conductive structures 120 provide electrical wiring to enable signals and / or power to be provided to and / or received from integrated circuit devices 112. Conductive structures 120 may include a combination of metallization structures and interconnect structures. Metallization structures may include trenches, metallization layers, conductive traces, and / or other types of metallization structures. Interconnect structures may include vias, plugs, interconnects, and / or other types of interconnect structures. Conductive structures 120 may include one or more conductive materials, such as tungsten (W), cobalt (Co), ruthenium (Ru), titanium (Ti), aluminum (Al), copper (Cu), gold (Au), and / or combinations thereof, and other examples of conductive materials. In some embodiments, conductive structures 120 include one or more substrates. One or more substrates may include barrier substrates, adhesive substrates, and / or other types of substrates. Examples of materials for one or more liner layers include tantalum nitride (TaN) and / or titanium nitride (TiN), among others.

[0021] In some embodiments, the conductive structures 120 may be arranged in multiple layers arranged vertically (e.g., in the z-direction) within the interconnect layer 106. In other words, the multiple conductive structure layers 120 may extend within the interconnect layer 106 over the device layer 104 to facilitate the routing of electrical signals and / or power between the device layer 104 and the interconnect layer 106. Metallization structures may be arranged in a metallization layer referred to as the M layer. For example, a metal-O (MO) layer containing multiple conductive structures 120 (e.g., metallization structures) may be located at the bottom of the interconnect layer 106 and may be directly coupled to the device layer 104 (e.g., to the integrated circuit device 112 in the device layer 104). A via-I (V1) layer containing multiple conductive structures (e.g., interconnect structures) may be included above the MO layer. A metal-1 layer (M1) containing multiple conductive structures 120 (e.g., metallized structures) may be located above the V1 layer in the interconnect layer 106; a via-2 layer (V2) containing multiple conductive structures (e.g., interconnect structures) may be contained above the M1 layer; a metal-2 layer (M2) containing multiple conductive structures 120 (e.g., metallized structures) may be located above the V2 layer, and so on.

[0022] One or more top metal layers may be included above the conductive structures 120 (e.g., M and V layers) in the interconnect layer 106. For example, the interconnect layer 106 may include an etch stop layer 122, an interlayer dielectric layer 124, an etch stop layer 126, an interlayer dielectric layer 128, an etch stop layer 130, an interlayer dielectric layer 132, an etch stop layer 134, and an interlayer dielectric layer 136, and may include a top via 138 (e.g., extending through the etch stop layer 122 and the interlayer dielectric layer 124), a top metal layer 140 (e.g., extending through the etch stop layer 126 and the interlayer dielectric layer 128), a top via 142 (e.g., extending through the etch stop layer 130 and the interlayer dielectric layer 132), and / or a top metal layer 144 (e.g., extending through the etch stop layer 134 and / or the interlayer dielectric layer 136), and other examples.

[0023] Top vias 138 and 142 may be physically larger (e.g., higher in the z-direction) than the interconnect structure of conductive structure 120. Similarly, top metal layers 140 and 144 may be physically larger (e.g., higher in the z-direction) than the metallization structure of conductive structure 120. For example, the metallization structure of conductive structure 120 may have a sub-micrometer z-direction height, while top metal layers 140 and 144 may have a z-direction height of about 1 micrometer or greater. However, other z-direction heights of the metallization structure of conductive structure 120 and top metal layers 140 and 144 are within the scope of this disclosure.

[0024] The physically larger size of the top vias 138 and 142, as well as the top metal layers 140 and 144, provides lower chip resistance and enables the processing of higher current signals on top of the interconnect layer 106. The physically smaller size of the conductive structure 120 allows for a higher density of conductive structures 120 near the integrated circuit devices 112 in the device layer 104, enabling the integrated circuit devices 112 to be placed closer together to achieve a higher density of integrated circuit devices in the device layer 104.

[0025] In some embodiments, etch stop layers 122, 126, 130, and 134 may include alternative arrangements of materials. For example, etch stop layers 122 and 130 may include silicon carbide (SiC), and etch stop layers 126 and 134 may include silicon nitride (SixNY, such as Si3NY7). However, other combinations of materials for etch stop layers 122, 126, 130, and 134 are within the scope of this disclosure.

[0026] In some embodiments, etch stop layer 122 may have a z-direction thickness ranging from about 300 angstroms to about 800 angstroms. However, other values ​​in this range are within the scope of this disclosure. In some embodiments, interlayer dielectric layer 124 may have a z-direction thickness ranging from about 4000 angstroms to about 8000 angstroms. However, other values ​​in this range are within the scope of this disclosure. In some embodiments, etch stop layer 126 may have a z-direction thickness ranging from about 300 angstroms to about 700 angstroms. However, other values ​​in this range are within the scope of this disclosure. In some embodiments, interlayer dielectric layer 128 may have a z-direction thickness ranging from about 6000 angstroms to about 12000 angstroms. However, other values ​​in this range are within the scope of this disclosure. In some embodiments, etch stop layer 130 may have a z-direction thickness ranging from about 300 angstroms to about 800 angstroms. However, other values ​​in this range are within the scope of this disclosure. In some embodiments, interlayer dielectric layer 132 may have a z-direction thickness ranging from about 4000 angstroms to about 8000 angstroms. However, other values ​​within this range are within the scope of this disclosure. In some embodiments, the etch stop layer 134 may have a z-direction thickness ranging from about 300 angstroms to about 700 angstroms. However, other values ​​within this range are within the scope of this disclosure. In some embodiments, the interlayer dielectric layer 136 may have a z-direction thickness ranging from about 7000 angstroms to about 10000 angstroms. However, other values ​​within this range are within the scope of this disclosure.

[0027] Bonding layer 108 may be connected to the top metal layer 144 of interconnect layer 106. Bonding layer 108 may include additional etch stop layers and dielectric layers, such as etch stop layer 146, dielectric layer 148, etch stop layer 150, and / or dielectric layer 152. Furthermore, bonding layer 108 may include bonding vias 154 (e.g., extending through etch stop layer 146 and / or dielectric layer 148) and bonding pads 156 (e.g., extending through etch stop layer 150 and / or dielectric layer 152). Bonding via 154 may be electrically connected and / or physically connected to the top metal layer 144, and bonding pads 156 may be electrically connected and / or physically connected to the bonding via 154.

[0028] Etch stop layers 146 and 150 may each comprise silicon nitride (SixNy), silicon carbide (SiC), silicon oxynitride (SiON), and / or other suitable dielectric materials. Dielectric layers 148 and 152 may each comprise oxides (e.g., silicon oxide (SiOx) and / or other oxide materials), undoped silicate glass (USG), borosilicate glass (BSG), fluorinated silicate glass (FSG), tetraethoxysilane (TEOS), hydrosilsesquioxane (HSQ), and / or other suitable dielectric materials.

[0029] In some embodiments, the thickness of the etch stop layer 146 in the Z direction may range from about 500 angstroms to about 1000 angstroms. However, other ranges are also within the scope of this disclosure. In some embodiments, the thickness of the dielectric layer 148 in the Z direction may range from about 4000 angstroms to about 9000 angstroms. However, other ranges are also within the scope of this disclosure. In some embodiments, the thickness of the etch stop layer 150 in the Z direction may range from about 800 angstroms to about 1600 angstroms. However, other ranges are also within the scope of this disclosure. In some embodiments, the thickness of the dielectric layer 152 in the Z direction may range from about 6000 angstroms to about 12000 angstroms. However, other ranges are also within the scope of this disclosure.

[0030] The bonding via 154 includes a conductive structure extending primarily in the Z direction. The bonding via 154 electrically couples the top metal layer 144 to the bonding pad 156. The bonding pad 156 includes a conductive pad for bonding the semiconductor device 102 to another semiconductor device to form a vertically stacked semiconductor package. The bonding via 154 and the bonding pad 156 include one or more conductive materials, such as tungsten (W), cobalt (Co), ruthenium (Ru), titanium (Ti), aluminum (Al), copper (Cu), gold (Au), and / or combinations thereof, as well as other conductive materials.

[0031] The bonding layer 108 also includes a bonding dielectric layer 158 surrounding the bonding pad 156. The bonding dielectric layer 158 can also be used to bond the semiconductor device 102 to another semiconductor device to form a vertically stacked semiconductor package. Therefore, the combination of the bonding pad 156 and the bonding dielectric layer 158 enables the semiconductor device 102 to be bonded to another semiconductor device via metal-to-metal bonding and dielectric-to-dielectric bonding. The bonding dielectric layer 158 may include one or more dielectric materials, such as silicon nitride (SixNy), silicon carbide (SiC), silicon oxynitride (SiON), and / or other suitable dielectric materials. In some embodiments, the thickness of the bonding dielectric layer 158 in the Z direction may be in the range of about 500 angstroms to about 1000 angstroms. However, other range values ​​are also within the scope of this disclosure.

[0032] As further shown in FIG1, the semiconductor device 102 may include one or more capacitor structures 160. The capacitor structure 160 may include a trench capacitor structure extending through a portion of the bonding layer 108 and through a portion of the interconnect layer 106. The capacitor structure 160 may include a deep trench capacitor structure because the capacitor structure 160 has a high aspect ratio between its vertical (Z-direction) height and its lateral (X-direction) width. For example, the aspect ratio of the capacitor structure 160 may be greater than about 10:1, and in some embodiments is included in the range of about 18:1 to about 55:1. However, other values ​​and ranges of aspect ratios for the capacitor structure 160 are also within the scope of this disclosure.

[0033] As shown in Figure 1, the capacitor structure 160 includes multiple conformal layers (metal-insulator-metal, MIM), including a bottom electrode layer 162, an insulating layer 164 on the bottom electrode layer 162, and a top electrode layer 166 on the insulating layer 164. Therefore, the insulating layer 164 is located between the bottom electrode layer 162 and the top electrode layer 166, enabling the capacitor structure 160 to store charge based on the capacitance between the bottom electrode layer 162 and the top electrode layer 166. Dielectric filler 168 may be included between segments of the top electrode layer 166 to electrically isolate the segments of the top electrode layer 166. However, in other embodiments, the dielectric filler 168 may be omitted.

[0034] Bottom electrode layer 162, insulating layer 164, and top electrode layer 166 correspond to the metal-insulator-metal (MIM) stack of capacitor structure 160. Therefore, capacitor structure 160 can also be referred to as MIM capacitor structure. Bottom electrode layer 162 (also called capacitor bottom metal (CBM)) and top electrode layer 166 (also called capacitor top metal (CTM)) may each include one or more conductive metals, one or more conductive metallic materials, one or more conductive ceramic materials, and / or other types of conductive materials. For example, these include tungsten (W), cobalt (Co), ruthenium (Ru), titanium (Ti), tantalum (Ta), aluminum (Al), copper (Cu), gold (Au), titanium nitride (TiN), and / or tantalum nitride (TaN). In some embodiments, bottom electrode layer 162 and top electrode layer 166 include the same material or the same material composition. In some embodiments, bottom electrode layer 162 and top electrode layer 166 include different materials or different material compositions.

[0035] The insulating layer 164 may include one or more electrically insulating materials. In some embodiments, the insulating layer 164 includes one or more low-dielectric materials, such as silicon oxide (SiOx, e.g., SiO 2). Additionally and / or alternatively, the insulating layer 164 may include one or more high-dielectric materials, such as zirconium oxide (ZrO x, e.g., ZrO 2), aluminum oxide (Al xO y, e.g., Al 2O 3), silicon nitride (Si xN y, e.g., Si 3N 4), yttrium oxide (Y xO y, e.g., Y 2O 3), lanthanum oxide (La xO y, e.g., La 2O 3), and / or hafnium oxide (HfO x, e.g., HfO 2). In some embodiments, the insulating layer 164 is a multilayer stack comprising multiple dielectric layers. For example, the insulating layer 164 may include a ZrO 2 / Al 2O 3 / ZrO 2 (ZAZ) layer stack.

[0036] As further shown in FIG1, the capacitor structure 160 may include one or more capping layers above the top electrode layer 166. The one or more capping layers may include capping layer 170, capping layer 172, and / or other capping layers. The capping layers may provide electrical isolation for the MIM stack of the capacitor structure 160, and / or may also serve as a hard mask layer stack for etching the bottom electrode layer 162, insulating layer 164, and / or top electrode layer 166. Capping layers 170 and 172 may include oxide-containing dielectric materials such as silicon oxide (SiOx, e.g., SiO2), nitride-containing dielectric materials such as silicon oxynitride (SiON), nitride-containing dielectric materials such as silicon nitride (SixNy, e.g., Si3N4), and / or other suitable dielectric materials. In some embodiments, capping layers 170 and 172 comprise the same material and / or the same material composition. In some embodiments, capping layers 170 and 172 comprise different materials and / or different material compositions.

[0037] As further shown in Figure 1, the capacitor structure 160 may include one or more sidewall spacers 174 and / or 176 on the sidewalls of the capping layers 170 and / or 172, and / or on the sidewalls of the top electrode layer 166 on top of the capacitor structure 160. The combination of the capping layers 170, 172 and the sidewall spacers 174, 176 can serve as a self-aligned mask when etching layers to define the bottom electrode layer 162. The sidewall spacer 174 may include an oxide-containing dielectric material, such as silicon oxide (SiOx, e.g., SiO2). The sidewall spacer 176 may include a nitride-containing dielectric material, such as silicon nitride (SixNy, e.g., Si3N4).

[0038] As further shown in FIG1, the capacitor structure 160 may include a deep trench structure 178 extending vertically (e.g., in the z-direction) through multiple dielectric layers in the interconnect layer 106. For example, the deep trench structure 178 may extend through one or more interlayer dielectric layers 116, one or more etch stop layers 118, etch stop layer 122, interlayer dielectric layer 124, etch stop layer 126, interlayer dielectric layer 128, etch stop layer 130, and / or interlayer dielectric layer 132, etc. In the example shown in FIG1, the top of the capacitor structure 160 (e.g., top electrode layer 166) is physically coupled and / or electrically coupled to a top via 142 in the interconnect layer 106. In other examples, as shown in FIG5, FIG6, FIG9A, FIG9B, FIG10A, and FIG10B, the top of the capacitor structure 160 (e.g., top electrode layer 166) may be physically coupled and / or electrically coupled to a bonding via 154 or a bonding pad 156. In these examples, the deep trench structure 178 of the capacitor structure 160 may also extend into and / or through the etch stop layer 134, the interlayer dielectric layer 136, the etch stop layer 146, the dielectric layer 148, the etch stop layer 150, and / or the dielectric layer 152, etc. In some embodiments, the depth (or height) of the deep trench structure 178 in the z-direction may include a range from approximately 0.25 micrometers to approximately 6 micrometers. However, other values ​​and ranges are also within the scope of this disclosure.

[0039] Figures 2A and 3A through 3E illustrate various top view layout examples of the trench segments of the deep trench structure 178. As shown in Figures 2A and 3A through 3E, the trench segments of the deep trench structure 178 can be interconnected and can provide increased surface area for the bottom electrode layer 162, the insulating layer 164, and the top electrode layer 166 (e.g., relative to an arrangement with only non-connected trenches in the top view of the capacitor structure 160), which allows the capacitor structure to achieve increased capacitance.

[0040] As further shown in Figure 1, the bottom electrode layer 162, insulating layer 164, and / or top electrode layer 166 may be conformal layers extending into the deep trench structure 178. Specifically, the bottom electrode layer 162, insulating layer 164, and / or top electrode layer 166 may extend along the sidewalls and bottom surface of the deep trench structure 178. A portion of the bottom electrode layer 162 at the bottom of the capacitor structure 160 may be located on and in physical contact with the underlying conductive structure 120 at the bottom of the capacitor structure 160. Therefore, the bottom electrode layer 162 may be electrically connected to the conductive structure 120 in the interconnect layer 106.

[0041] As indicated above, Figure 1 is provided as an example. Other examples may differ from those illustrated with respect to Figure 1.

[0042] Figures 2A and 2B are diagrams of an embodiment 200 of the capacitor structure 160 described herein. The capacitor structure 160 may be contained in the interconnect layer 106 of the semiconductor device 102, and / or may be contained in the interconnect layer 106 of another semiconductor device described herein, such as semiconductor device 102a shown in Figures 9A and / or 10A, semiconductor device 102b shown in Figures 9A and / or 10A, and / or another semiconductor device.

[0043] Figure 2A illustrates the top view layout of capacitor structure 160 in the xy plane. As shown in the top view layout of capacitor structure 160 in Figure 2A, the deep trench structure 178 of capacitor structure 160 includes multiple interconnected trench segments 202a-202f. Trench segments 202a, 202b, 202c, and 202d can be connected in a closed-loop arrangement and can define the perimeter of deep trench structure 178. Trench segments 202e and 202f can extend within the perimeter of deep trench structure 178 and can be connected to one or more trench segments 202a, 202b, 202c, and / or 202d. Bottom electrode layer 162, insulating layer 164, and top electrode layer 166 can extend into trench segments 202a-202f (e.g., along the sidewalls and bottom surface).

[0044] Two or more trench segments 202a-202f may be connected in various connection regions of the deep trench structure 178. A "connection region" refers to the area in the deep trench structure 178 where two or more trench segments are connected. The connection region may be located at the ends of the two or more trench segments, at the center or midpoint of the first trench segment and at the ends of the second trench segment, at the center or midpoint of the two or more trench segments, and / or at other locations on the two or more trench segments.

[0045] As shown in the example top view layout in Figure 2A, the first ends of trench segment 202a and trench segment 202c can be connected in connection region 204a of deep trench structure 178. The first ends of trench segment 202b and the second ends of trench segment 202c (e.g., opposite to the first end of trench segment 202c) can be connected in connection region 204b of deep trench structure 178. The second ends of trench segment 202b (e.g., opposite to the first end of trench segment 202b) and the second ends of trench segment 202d (e.g., opposite to the first end of trench segment 202d) can be connected in connection region 204c of deep trench structure 178. The second ends of trench segment 202a (e.g., opposite to the first end of trench segment 202a) and the first ends of trench segment 202d can be connected in connection region 204d of deep trench structure 178.

[0046] As further shown in the example top view layout in Figure 2A, the first end of trench segment 202e can be connected to the first ends of trench segment 202a and trench segment 202c in connection region 204a. The second end of trench segment 202e (e.g., opposite to the first end of trench segment 202e) can be connected to the second ends of trench segment 202b and trench segment 202d in connection region 204c. The first end of trench segment 202f can be connected to the first ends of trench segment 202b and trench segment 202c in connection region 204b. The second end of trench segment 202f (e.g., opposite to the first end of trench segment 202f) can be connected to the second ends of trench segment 202a and trench segment 202d in connection region 204d. Trench segments 202e and 202f can be connected in connection region 204e (e.g., at approximately the midpoint of trench segments 202e and 202f). Connection regions 204a-204d may be located at the corners of the perimeter of the deep trench structure 178, while connection region 204e may be located approximately at the center of the deep trench structure 178.

[0047] In some embodiments, trench segments 202a, 202b, 202c, and 202d may be arranged in an approximately hollow square layout in a top view of capacitor structure 160, or in an approximately hollow rectangular layout in a view of capacitor structure 160. In the example top view layout of FIG. 2A, trench segments 202e and 202f may extend diagonally through the perimeter of deep trench structure 178. In these embodiments, the angles between trench segments 202a and 202c, between trench segments 202b and 202c, between trench segments 202b and 202d, and between trench segments 202a and 202d may each be contained within a range of approximately 85 degrees to approximately 95 degrees. However, other values ​​and ranges are also within the scope of this disclosure. In some embodiments, trench segments 202a, 202b, 202c, and 202d may be arranged in another hollow top view layout.

[0048] The perimeter of the deep trench structure 178 may have an x-direction width (dimension D2) and a y-direction width (dimension D3). In some embodiments, the x-direction width and y-direction width may each be within the range of approximately 0.5 micrometers to approximately 10 micrometers. If the x-direction width and / or y-direction width is less than approximately 0.5 micrometers, insufficient spacing may be provided between trench segments 202a-202f, resulting in a reduction in the surface area of ​​the bottom electrode layer 162, insulating layer 164, and top electrode layer 166 (and therefore, a reduction in the capacitance of the capacitor structure 160). If the x-direction width and / or y-direction width is greater than approximately 10 micrometers, the lateral footprint of the deep trench structure 178 may be excessive, resulting in a reduction in the structure and / or device density in the interconnect layer 106 of the semiconductor device 102. However, other values ​​and ranges, other than approximately 0.5 micrometers to approximately 10 micrometers, are also within the scope of this disclosure.

[0049] In some embodiments, the lateral width (dimension D4) of each trench segment 202a-202f may be contained in the range of approximately 0.1 micrometers to approximately 1 micrometer. If the lateral width of the trench segments 202a-202f is less than approximately 0.1 micrometers, insufficient gap-filling performance may result in the formation of the deep trench structure 178, which may lead to voids and other discontinuities in the bottom electrode layer 162, the insulating layer 164, and / or the top electrode layer 166. If the lateral width of the trench segments 202a-202f is greater than approximately 1 micrometer, insufficient spacing may be provided between the trench segments 202a-202f, resulting in a reduction in the surface area of ​​the bottom electrode layer 162, the insulating layer 164, and the top electrode layer 166 (and therefore, a reduction in the capacitance of the capacitor structure 160). However, other values ​​and ranges, other than approximately 0.1 micrometers to approximately 1 micrometer, are also within the scope of this disclosure.

[0050] Figure 2B illustrates a cross-sectional view of capacitor structure 160 along line AA in Figure 2A. Therefore, the cross-sectional view of capacitor structure 160 in Figure 2B includes a portion of trench segment 202a (e.g., in a non-connection region), a portion of trench segment 202b (e.g., in a non-connection region), and portions of trench segments 202e and 202f (e.g., in connection region 204e).

[0051] In deep trench structure 178, the trench segment portion in the connecting region may have a greater depth or z-direction height than the trench segment portion not located in the connecting region. For example, as shown in FIG2B, a portion of trench segment 202a in the non-connecting region may have a z-direction depth (e.g., between the top and bottom of trench segment 202a), labeled as dimension D5 in FIG2B, and portions of trench segments 202e and 202f (e.g., in connecting region 204e) may have a z-direction depth (e.g., between the top and bottom of trench segments 202e and 202f), labeled as dimension D6 in FIG2B, and dimension D6 may be greater than dimension D5, the difference being labeled as dimension D7 in FIG2B. As another example, as shown in Figure 2B, a portion of the trench segment 202b in the non-connected region may have a depth in the z-direction (e.g., between the top and bottom of the trench segment 202b), denoted as dimension D8 in Figure 2B, and dimension D6 may be greater than dimension D8, the difference of which is denoted as dimension D9 in Figure 2B.

[0052] The difference in z-direction depth or height between the non-connected regions and the connected regions 204a-204e may be due to the depth loading effect that occurs in the connected regions 204a-204e when forming the deep trench structure 178. For example, the dielectric layer forming the deep trench structure 178 may be etched using an etchant, and due to the larger open volume in the connected regions 204a-204e, the etchant may remove the dielectric layer material in the connected regions 204a-204e faster than in the non-connected regions of the deep trench structure 178. The larger open volume (meaning the larger open area of ​​the groove formed for the deep trench structure 178 in the connected regions 204a-204e) results in more etchant contacting the dielectric layer for a longer time, thus leading to a greater degree of etching. As described above, Figures 2A and 2B are provided only as examples. Other examples may differ from those described with respect to Figures 2A and 2B.

[0053] Figures 3A to 3E are schematic top views of embodiments of the capacitor structure 160 described herein. The top views shown in Figures 3A to 3E are non-limiting examples, and other top views of the capacitor structure 160 described herein are also within the scope of this disclosure.

[0054] Figure 3A illustrates an embodiment 300 of the top view layout of the capacitor structure 160. As shown in Figure 3A, the top view layout of embodiment 300 is similar to the top view layout of embodiment 200 in Figure 2A. For example, in the top view layout of embodiment 300, the deep trench structure 178 of the capacitor structure 160 includes trench segments 202a-202f and connection regions 204a-204e, similar to the top view layout of embodiment 200 in Figure 2A.

[0055] However, in the top-view layout of embodiment 300, trench segments 202e and 202f extend approximately vertically (e.g., relative to the diagonal) and connect to trench segments 202a-202d in connection regions 204f-204i that are not located at the ends of trench segments 202a-202d. For example, a first end of trench segment 202e may connect to approximately the midpoint along trench segment 202a in connection region 204f, and a second end of trench segment 202e may connect to approximately the midpoint along trench segment 202b in connection region 204g. As another example, a first end of trench segment 202f may connect to approximately the midpoint along trench segment 202c in connection region 204h, and a second end of trench segment 202f may connect to approximately the midpoint along trench segment 202d in connection region 204i.

[0056] Therefore, trench segments 202e and 202f form a cross shape or (plus sign (+) shape) in the top view of the deep trench structure 178 of capacitor structure 160, rather than an X shape. Trench segment 202e extends approximately parallel to trench segments 202c and 202d in the x-direction, while trench segment 202f extends approximately parallel to trench segments 202a and 202b in the y-direction.

[0057] As further shown in Figure 2B, dimension D10 may correspond to the distance or spacing between trench segments, for example, between trench segments 202a and 202f. In some embodiments, the minimum spacing between trench segments may include a range of about 0.10 micrometers to about 0.2 micrometers. However, other values ​​and ranges are also within the scope of this disclosure. In some embodiments, the number of trench segments may include a range of 2 to 20. In some embodiments, the number of trench segments may be greater than 20. Furthermore, other numbers of trench segments are also within the scope of this disclosure.

[0058] Figure 3B illustrates an embodiment 302 of the top view layout of the capacitor structure 160. As shown in Figure 3B, the top view layout of embodiment 302 is similar to the top view layout of embodiment 200 in Figure 2A. For example, in embodiment 302 of the top view layout, the deep trench structure 178 of the capacitor structure 160 includes trench segments 202a-202f and connecting regions 204a-204e, similar to the top view layout of embodiment 200 in Figure 2A. Furthermore, trench segments 202e and 202f extend diagonally within the perimeter of the deep trench structure 178 and are connected to trench segments 202a-202d in connecting regions 204a-204d at the corners of the deep trench structure 178.

[0059] However, in embodiment 302 with a top-view layout, the deep trench structure 178 of the capacitor structure 160 includes an additional trench segment 202g that extends approximately parallel to trench segments 202a and 202b. Trench segment 202g passes approximately through the center of the deep trench structure 178 (e.g., in the y-direction as shown in FIG. 3B, or in the x-direction) and intersects with trench segments 202e and 202f in the connection region 204e. One end of trench segment 202g may be connected in the connection region 204f to trench segment 202c along its approximately midpoint, while the other end of trench segment 202g (e.g., opposite to the first end of trench segment 202g) may be connected in the connection region 204g to trench segment 202d along its approximately midpoint.

[0060] The additional trench segment 202g can provide additional surface area for the bottom electrode layer 162, the insulating layer 164 and / or the top electrode layer 166, thereby further increasing the capacitance of the capacitor structure 160.

[0061] Figure 3C illustrates an embodiment 304 of the top view layout of the capacitor structure 160. As shown in Figure 3C, the top view layout of embodiment 304 is similar to the top view layout of embodiment 302 in Figure 3B. For example, in embodiment 304 of the top view layout, the deep trench structure 178 of the capacitor structure 160 includes trench segments 202a-202g and connection regions 204a-204g, similar to the top view layout of embodiment 302 in Figure 3B.

[0062] However, in embodiment 304 with a top-view layout, the deep trench structure 178 of capacitor structure 160 includes an additional trench segment 202h that extends approximately parallel to trench segments 202c and 202d. Trench segment 202h passes approximately through the center of deep trench structure 178 (e.g., in the x-direction as shown in FIG. 3B, or in the x-direction) and intersects with trench segments 202e, 202f, and 202g in connection region 204e. One end of trench segment 202h may be connected in connection region 204h to trench segment 202a along its approximately midpoint, while the other end of trench segment 202h (e.g., opposite to the first end of trench segment 202h) may be connected in connection region 204i to trench segment 202b along its approximately midpoint.

[0063] The additional trench section 202h can provide additional surface area for the bottom electrode layer 162, the insulating layer 164 and / or the top electrode layer 166, thereby further increasing the capacitance of the capacitor structure 160.

[0064] Figure 3D illustrates an embodiment 306 of the top view layout of the capacitor structure 160. As shown in Figure 3D, the top view layout of embodiment 306 is similar to the top view layout of embodiment 200 in Figure 2A. For example, in embodiment 306 of the top view layout, the deep trench structure 178 of the capacitor structure 160 includes trench segments 202a-202f and connection regions 204a-204d, similar to the top view layout of embodiment 200 in Figure 2A.

[0065] However, in the top-view layout of embodiment 306, trench segments 202e and 202f extend approximately parallel (e.g., rather than diagonally). Therefore, trench segments 202e and 202f do not intersect, but are spaced apart from each other. Trench segments 202e and 202f extend approximately parallel to trench segments 202c and 202d (and to each other) in the x-direction.

[0066] Trench segments 202e and 202f are connected to trench segments 202a-202d at connection regions 204e-204h that are not located at the ends of trench segments 202a-202d. For example, one end of trench segment 202e may be connected to trench segment 202a in connection region 204e located between the ends of trench segment 202a, while the other end of trench segment 202e may be connected to trench segment 202b in connection region 204f located between the ends of trench segment 202b. Another example is that one end of trench segment 202f may be connected to trench segment 202a in connection region 204g located between the ends of trench segment 202a, while the other end of trench segment 202f may be connected to trench segment 202b in connection region 204h located between the ends of trench segment 202b. The connecting regions 204e and 204g may not overlap, so that the trench segments 202e and 202f do not contact each other, and the connecting regions 204f and 204h may not overlap, so that the trench segments 202e and 202f do not contact each other.

[0067] Figure 3E illustrates an embodiment 308 of the top view layout of the capacitor structure 160. As shown in Figure 3E, in the top view layout embodiment 308, the capacitor structure 160 includes a plurality of discontinuous deep trench structures 178. Although the example in Figure 3E illustrates two deep trench structures 178 (e.g., deep trench structure 178a and deep trench structure 178b), the scope of this disclosure includes other numbers of deep trench structures of the capacitor structure 160 described herein.

[0068] As further shown in Figure 3E, each of the deep trench structures 178a and 178b includes multiple trench segments. For example, deep trench structure 178a includes trench segments 202a-202c, while deep trench structure 178b includes trench segments 202d and 202e. These arrangements are examples, and the scope of this disclosure includes examples of other arrangements and numbers of trench segments.

[0069] In the deep trench structure 178a, one end of trench segment 202a and one end of trench segment 202c can be connected in connecting region 204a. The other end of trench segment 202a can face the deep trench structure 178b. One end of trench segment 202b and the other end of trench segment 202c can be connected in connecting region 204b. The other end of trench segment 202b can face the deep trench structure 178b. Trench segments 202a-202c and connecting regions 204a and 204b can be arranged to give the deep trench structure 178a an approximately U-shaped top view layout. However, the scope of this disclosure includes other top view layouts of the deep trench structure 178a.

[0070] In the deep trench structure 178b, one end of the trench segment 202e can be connected to approximately the midpoint of the trench segment 202d in the connecting region 204c. The other end of the trench segment 202e can face the deep trench structure 178a. The trench segments 202d and 202e, and the connecting region 204c, can be arranged in a top view configuration that gives the deep trench structure 178b an approximately T-shaped configuration. However, the scope of this disclosure includes other top view configurations of the deep trench structure 178b.

[0071] As described above, Figures 3A to 3E are provided as examples. Other examples may differ from those depicted in Figures 3A-3E.

[0072] Figures 4A to 4J are illustrations of an embodiment 400 of forming the semiconductor device 102 described herein. Specifically, embodiment 400 includes an example of embodiment 100 forming the semiconductor device 102 shown in Figure 1. However, one or more semiconductor process operations associated with Figures 4A to 4J may be performed to form the semiconductor device 102 of another embodiment described herein. In some embodiments, one or more semiconductor process tools associated with Figures 4A-4J may be used to perform one or more semiconductor process operations, such as deposition tools, exposure tools, development tools, etching tools, planarization tools, ion implantation tools, wafer / die transport tools, and / or other types of semiconductor process tools.

[0073] Turning to Figure 4A, a substrate layer 110 may be provided. The substrate layer 110 may be provided in the form of a semiconductor wafer, such as a silicon (Si) wafer, a silicon-on-insulator (SiI) wafer, and / or other types of semiconductor devices. The semiconductor device 102 may be formed on the semiconductor wafer together with other semiconductor devices.

[0074] As shown in Figure 4B, the integrated circuit device 112 may be formed within and / or on the substrate layer 110 of the device layer 104 of the semiconductor device 102. One or more portions of the integrated circuit device 112 may be formed using one or more semiconductor process tools. For example, an ion implantation tool may be used to dope one or more regions of the substrate layer 110 with one or more types of dopant to form well regions, implantation regions, and / or other types of doped regions of the integrated circuit device 112 in the substrate layer 110. Alternatively, a deposition tool may be used to perform various deposition operations to deposit layers and / or structures of the integrated circuit device 112, and / or to deposit a photoresist layer to etch portions of the substrate layer 110 and / or the deposited layer. Alternatively, an exposure tool may be used to expose the photoresist layer to form a pattern in the photoresist layer. Alternatively, a development tool may be used to develop the pattern in the photoresist layer. Alternatively, an etching tool may be used to etch portions of the substrate layer 110 and / or the deposited layer to form the integrated circuit device 112. Alternatively, a planarization tool may be used to planarize portions of the integrated circuit device 112. For example, electroplating tools can be used to deposit the metal structure and / or layers of the integrated circuit device 112.

[0075] As further shown in FIG4B, a dielectric layer 114 is deposited on and / or above the substrate layer 110 and on and / or above the integrated circuit device 112 using a deposition tool. The dielectric layer 114 can be deposited using physical vapor deposition (PVD), atomic layer deposition (ALD), chemical vapor deposition (CVD), oxidation, and / or other suitable deposition techniques. In some embodiments, a planarization operation, such as chemical mechanical planarization (CMP), can be performed using a planarization tool to planarize the dielectric layer 114 after deposition.

[0076] As shown in FIG4C, a first portion of the interconnect layer 106 of the semiconductor device 102 is formed on the dielectric layer 114. Alternating interlayer dielectric layers 116 and etch stop layers 118 are deposited in the first portion of the interconnect layer 106 of the semiconductor device 102 using one or more deposition tools. In this manner, the interlayer dielectric layers 116 and etch stop layers 118 can be aligned along the z-direction in the semiconductor device 102. Each interlayer dielectric layer 116 and each etch stop layer 118 can be deposited using one or more deposition tools through physical vapor deposition, atomic layer deposition, chemical vapor deposition, oxidation, and / or other suitable deposition techniques. In some embodiments, a planarization tool can be used to planarize the interlayer dielectric layers 116 and / or etch stop layers 118 after deposition.

[0077] Before forming the interconnect layer 106, contact windows of the integrated circuit device 112 may be formed through the dielectric layer 114. Contact windows may be formed in recesses in the dielectric layer 114. In some embodiments, the dielectric layer 114 is etched to form recesses using a pattern in a photoresist layer. In these embodiments, a photoresist layer may be formed on the dielectric layer 114 using a deposition tool. The photoresist layer may be patterned by exposing it to a radiation source using an exposure tool. A portion of the photoresist layer may be developed and removed using a development tool to expose the pattern. The dielectric layer may be etched based on the pattern using an etching tool to form recesses. In some embodiments, the etching operation includes dry etching operations (e.g., plasma-based etching operations, gas-based etching operations), wet chemical etching operations, and / or other types of etching operations. In some embodiments, remaining portions of the photoresist layer may be removed using a photoresist removal tool (e.g., using chemical strippers, plasma ashing, and / or other techniques). In some embodiments, a hard mask layer is used as an alternative technique to etch the dielectric layer 114 based on the pattern to form recesses.

[0078] Contacts may be formed in the grooves. In some embodiments, contact windows (e.g., gate contact windows) are formed on the gate structure of the integrated circuit device 112. In some embodiments, contact windows (e.g., source / drain contact windows) are formed on the source / drain regions of the integrated circuit device 112. Material for the contacts may be deposited in the grooves using deposition tools through chemical vapor deposition, physical vapor deposition, atomic layer deposition, electroplating, and / or other suitable deposition techniques. The material for the contacts may be deposited in one or more deposition operations. In some embodiments, a seed layer is first deposited, and then the material for the contacts is deposited on the seed layer. In some embodiments, a planarization operation (e.g., chemical mechanical planarization) is performed using a planarization tool to planarize the contacts after deposition, such that the top of the contacts is substantially coplanar with the top of the dielectric layer 114.

[0079] As further shown in FIG4C, various operations can be performed using deposition tools, exposure tools, developing tools, etching tools, planarization tools, electroplating tools, and / or other semiconductor process tools to form a conductive structure 120 in a first portion of the interconnect layer 106 of the semiconductor device 102. In some embodiments, the first portion of the interconnect layer 106 may be formed in multiple layers. For example, an interlayer dielectric layer 116 and an etch stop layer 118 may be formed (e.g., using one or more deposition tools and / or one or more planarization tools), grooves may be formed in and / or through the interlayer dielectric layer 116 and the etch stop layer 118 (e.g., using exposure tools, developing tools, and / or etching tools), and a first layer (e.g., MO layer) of the conductive structure 120 (e.g., a metallized structure) may be formed in the interlayer dielectric layer 116 and the etch stop layer 118 (e.g., using one or more deposition tools and / or one or more planarization tools). Another interlayer dielectric layer 116 and another etch stop layer 118 may be formed, and a second layer (e.g., VO layer) of conductive structure 120 (e.g., interconnect structure) may be formed in the interlayer dielectric layer 116 and the etch stop layer 118. An additional layer of conductive structure 120 may be formed in the interconnect layer 106 in a similar manner.

[0080] The conductive structure 120 can be deposited using one or more deposition tools through physical vapor deposition, atomic layer deposition, chemical vapor deposition, electroplating (e.g., electrochemical plating), and / or other suitable deposition techniques. In some embodiments, the conductive structure 120 can be planarized using a planarization tool after deposition.

[0081] As further shown in Figure 4C, etch stop layers 122, 126, and 130 may be formed in interconnect layer 106, and interlayer dielectric layers 124, 128, and 132 may be formed in interconnect layer 106. Etch stop layers 122, 126, and 130, and interlayer dielectric layers 124, 128, and 132 are deposited using one or more deposition tools via physical vapor deposition, atomic layer deposition, chemical vapor deposition, oxidation, and / or other suitable deposition techniques. In some embodiments, planarization tools may be used to planarize etch stop layers 122, 126, and 130 and interlayer dielectric layers 124, 128, and 132.

[0082] As further shown in FIG4C, various operations can be performed using deposition tools, exposure tools, developing tools, etching tools, planarization tools, electroplating tools, and / or other semiconductor process tools to form a top via 138 and a top metal layer 140 in a first portion of the interconnect layer 106 of the semiconductor device 102. In some embodiments, an etch stop layer 122 and an interlayer dielectric layer 124 may be formed, and grooves may be formed in and / or through the etch stop layer 122 and the interlayer dielectric layer 124 (e.g., using exposure tools, developing tools, and / or etching tools), and a top via 138 may be formed in the grooves (e.g., using one or more deposition tools and / or one or more planarization tools). In some embodiments, an etch stop layer 126 and an interlayer dielectric layer 128 may be formed, and grooves may be formed in and / or through the etch stop layer 126 and the interlayer dielectric layer 128 (e.g., using an exposure tool, a development tool, and / or an etching tool), and a top metal layer 140 may be formed in the grooves (e.g., using one or more deposition tools and / or one or more planarization tools). In some embodiments, an etch stop layer 130 and an interlayer dielectric layer 132 may be formed, and grooves may be formed in and / or through the etch stop layer 130 and the interlayer dielectric layer 132 (e.g., using an exposure tool, a development tool, and / or an etching tool), and a top via 142 may be formed in the grooves (e.g., using one or more deposition tools and / or one or more planarization tools). In some embodiments, an etch stop layer 134 and an interlayer dielectric layer 136 may be formed, and grooves may be formed in and / or through the etch stop layer 134 and the interlayer dielectric layer 136 (e.g., using an exposure tool, a development tool, and / or an etching tool), and a top metal layer 144 may be formed in the grooves (e.g., using one or more deposition tools and / or one or more planarization tools).

[0083] The top vias 138, 142 and the top metal layers 140, 144 can be deposited using one or more deposition tools via physical vapor deposition, atomic layer deposition, chemical vapor deposition, electroplating (e.g., electrochemical plating), and / or other suitable deposition techniques. In some embodiments, the top vias 138, 142 and the top metal layers 140, 144 can be planarized using a planarization tool after deposition.

[0084] As shown in Figure 4D, a patterned stack 402 may be formed over a portion of the interlayer dielectric layer 132. The patterned stack 402 may include multiple masking layers for forming recesses in which a capacitor structure 160 may be formed in the semiconductor device 102. The masking layers may include an advanced patterning film (APF) layer 404, an anti-reflective coating (BARC) 406 on the APF layer 404, and / or a photoresist layer 408 on the anti-reflective coating 406, and other examples. The masking layers of the patterned stack 402 may be selected to form the recesses of the capacitor structure 160 in a highly controlled manner to achieve substantially vertical sidewalls of the capacitor structure 160 (thus achieving a high aspect ratio). The advanced patterning film layer 404 may comprise an amorphous carbon material and / or other suitable materials. The anti-reflective coating 406 may comprise silicon oxynitride (SiON), a polymer, and / or other suitable materials. Advanced exposure pattern thin film layer 404, anti-reflective coating 406, and / or photoresist layer 408 can be deposited using deposition tools through physical vapor deposition, chemical vapor deposition, atomic layer deposition, spin coating, and / or other suitable deposition techniques.

[0085] As shown in Figure 4E, an etching tool can be used to etch portions through interlayer dielectric layer 132, through etch stop layer 130, through interlayer dielectric layer 128, through etch stop layer 126, through interlayer dielectric layer 124, through etch stop layer 122, through one or more etch stop layers 118, and / or through one or more interlayer dielectric layers 116 to form one or more recesses 410 to the underlying conductive structure 120 in interconnect layer 106. Recesses 410 may contain trenches for multiple interconnects, arranged in a top view layout as shown in Figures 2A and / or one or more of Figures 3A to 3E, and other example top view layouts.

[0086] In some embodiments, a pattern is formed in the photoresist layer 408, and the pattern is used to form the groove 410. The photoresist layer 408 can be patterned by exposing it to a radiation source using an exposure tool. A portion of the photoresist layer 408 can be developed and removed using a development tool to expose the pattern. An etching tool can be used to etch the antireflective coating 406 and / or the advanced exposure pattern film layer 404 based on the pattern to transfer the pattern to the antireflective coating 406 and / or the advanced exposure pattern film layer 404. An etching tool can be used to etch portions through the interlayer dielectric layer 132, through the etch stop layer 130, through the interlayer dielectric layer 128, through the etch stop layer 126, through the interlayer dielectric layer 124, through the etch stop layer 122, through one or more etch stop layers 118, and / or through one or more interlayer dielectric layers 116 based on the pattern in the photoresist layer 408, the antireflective coating 406, and / or the advanced exposure pattern film layer 404 to form the groove 410. In some embodiments, the etching operation that forms the groove 410 includes dry etching operations (e.g., plasma-based etching operations, gas-based etching operations), wet chemical etching operations, and / or other types of etching operations.

[0087] In some embodiments, deep reactive ion etching (sometimes referred to as "BOSCH" etching) can be used to achieve a high aspect ratio for the recess 410. Deep reactive ion etching is a cyclic etching technique in which multiple deposition and etching cycles are performed, using a protective liner to minimize lateral etching. For example, a deep reactive ion etching cycle may include etching the recess 410 to a first depth, forming a protective liner on the sidewalls and bottom surface of the recess 410, etching the protective liner to remove the protective liner from the bottom surface of the recess 410, and etching the bottom of the recess 410 to increase the depth of the recess 410 to a second depth, while the protective liner protects the sidewalls of the recess 410 from lateral etching. Additional cycles may be performed to achieve a specific depth for the recess 410.

[0088] In some embodiments, the remaining portion of the photoresist layer 408 may be removed using a photoresist removal tool (e.g., using a chemical stripper, plasma ashing, and / or other techniques). Additionally, the remaining portion of the antireflective coating 406 and / or the remaining portion of the advanced exposure pattern thin film layer 404 may be removed using an etching tool and / or a planarization tool.

[0089] As shown in Figure 4F, a bottom electrode layer 162, an insulating layer 164, a top electrode layer 166, and a dielectric filler 168 may be formed in the groove 410. The bottom electrode layer 162 may be conformally deposited on the sidewalls and bottom surface of the groove 410 (corresponding to the top surface of the conductive structure 120 exposed through the groove 410). The bottom electrode layer 162 may also be deposited on the top surface of a portion of the dielectric layer 148. In some embodiments, the bottom electrode layer 162 is deposited using conformal chemical vapor deposition and / or atomic layer deposition techniques.

[0090] An insulating layer 164 may be deposited on the bottom electrode layer 162. Therefore, the insulating layer 164 is deposited on the sidewalls and bottom surface of the recess 410 (corresponding to the top surface of the conductive structure 120 exposed through the recess 410). The insulating layer 164 may also be deposited on the top surface of a portion of the dielectric layer 148. In some embodiments, the insulating layer 164 is conformally deposited using a deposition tool via conformal chemical vapor deposition and / or atomic layer deposition techniques.

[0091] A top electrode layer 166 may be deposited on the insulating layer 164. Therefore, the top electrode layer 166 is deposited on the sidewalls and bottom surface of the recess 410 (corresponding to the top surface of the conductive structure 120 exposed through the recess 410). The top electrode layer 166 may also be deposited on the top surface of a portion of the dielectric layer 148. In some embodiments, the top electrode layer 166 is conformally deposited using a deposition tool via conformal chemical vapor deposition and / or atomic layer deposition techniques.

[0092] Dielectric filler 168 may be deposited on top electrode layer 166 to fill the remaining area of ​​groove 410. In some embodiments, dielectric filler 168 is deposited using deposition tools via physical vapor deposition, chemical vapor deposition, atomic layer deposition, and / or other suitable deposition techniques.

[0093] As further shown in Figure 4F, cap layers 170 and 172 may be formed above the recess 410. For example, cap layers 170 and 172 may be formed on the top surface of the interlayer dielectric layer 132. Cap layers 170 and 172 may be deposited using deposition tools via physical vapor deposition, atomic layer deposition, chemical vapor deposition, oxidation techniques, and / or other suitable deposition techniques. In some embodiments, a planarization operation (e.g., chemical mechanical planarization) may be performed using planarization tools to planarize cap layers 170 and / or 172 after deposition.

[0094] As shown in Figure 4G, etching operations can be performed to define the cap layers 170 and 172, the top electrode layer 166, and / or the insulating layer 164 of the capacitor structure 160. Etching tools can be used to etch the cap layers 170 and 172, the top electrode layer 166, and / or the insulating layer 164. In some embodiments, the etching operations include dry etching operations (e.g., plasma-based etching operations, gas-based etching operations), wet chemical etching operations, and / or other types of etching operations. In some embodiments, photoresist removal tools can be used to remove the remaining portions of the patterned mask layer (e.g., using chemical strippers, plasma ashing, and / or other techniques).

[0095] As further shown in Figure 4G, sidewall spacers 174 and 176 are formed on the ends of the insulating layer 164, the top electrode layer 166, the capping layer 170, and / or the capping layer 172. The sidewall spacers 174 and 176 can be deposited using deposition tools through physical vapor deposition, atomic layer deposition, chemical vapor deposition, oxidation techniques, and / or other suitable deposition techniques. The sidewall spacers 174 and 176 can be deposited in one or more deposition operations.

[0096] As further shown in Figure 4G, another etching operation can be performed to trim the bottom electrode layer 162 portion above the top surface of the dielectric layer 148 portion to define the bottom electrode layer 162 of the capacitor structure. The capping layer 172 and sidewall spacers 174 and 176 can be used as self-aligned masks to etch the bottom electrode layer 162. In some embodiments, the etching operation includes dry etching operations (e.g., plasma-based etching operations, gas-based etching operations), wet chemical etching operations, and / or other types of etching operations.

[0097] As shown in Figure 4H, additional material can be formed to cover the top of the capacitor structure 160 within the interlayer dielectric layer 132. The additional material of the interlayer dielectric layer 132 can be deposited using deposition tools via physical vapor deposition, atomic layer deposition, chemical vapor deposition, oxidation techniques, and / or other suitable deposition techniques. In some embodiments, the interlayer dielectric layer 132 can be planarized using a planarization tool after the additional material of the interlayer dielectric layer 132 has been deposited.

[0098] As shown in Figure 4I, an etch stop layer 134 and an interlayer dielectric layer 136 can be formed. Grooves can be formed in and / or through the etch stop layer 134 and the interlayer dielectric layer 136 (e.g., using an exposure tool, a development tool, and / or an etching tool). A top metal layer 144 can be formed in the grooves (e.g., using one or more deposition tools and / or one or more planarization tools).

[0099] The top via 142 and the top metal layer 144 can be deposited using one or more deposition tools through physical vapor deposition, atomic layer deposition, chemical vapor deposition, electroplating (e.g., electrochemical plating), and / or other suitable deposition techniques. In some embodiments, the top via 142 and the top metal layer 144 can be planarized using a planarization tool after deposition.

[0100] As further shown in Figure 4I, a top via 142 may be formed so that the top via 142 lands on the top electrode layer 166 of the capacitor structure 160. The top via 142 electrically connects the capacitor structure 160 to the top metal layer 144 and other structures in the semiconductor device 102.

[0101] As shown in Figure 4J, etch stop layers 146 and 150, dielectric layers 148 and 152, and a bonding dielectric layer 158 of the bonding layer 108 can be formed above the interconnect layer 106. A bonding via 154 can be formed in and / or through the etch stop layers 146 and 148, and can be formed on the top metal layer 144. A bonding pad 156 can be formed in and / or through the etch stop layers 150, 152, and / or the bonding dielectric layer 158, and can be formed on the bonding via 154.

[0102] The etch stop layer 146, dielectric layer 148, etch stop layer 150, dielectric layer 152, and / or bonding dielectric layer 158 can be deposited using one or more deposition tools through physical vapor deposition, atomic layer deposition, chemical vapor deposition, oxidation, and / or other suitable deposition techniques. In some embodiments, a planarization operation (e.g., chemical mechanical planarization) can be performed using a planarization tool to planarize the etch stop layer 146, dielectric layer 148, etch stop layer 150, dielectric layer 152, and / or bonding dielectric layer 158.

[0103] In some embodiments, the engagement via 154 and the engagement pad 156 may be formed in a dual damascene groove. For example, a first etching operation may be performed to form a trench portion of the dual damascene groove, and a second etching operation may be performed to form a via portion of the dual damascene groove. As another example, a first etching operation may be performed to form a via portion of the dual damascene groove, and a second etching operation may be performed to form a trench portion of the dual damascene groove. The engagement via 154 may be formed in the via portion of the dual damascene groove, while the engagement pad 156 may be formed in the trench portion of the dual damascene groove.

[0104] The bonding vias 154 and bonding pads 156 can be deposited using deposition tools via chemical vapor deposition, physical vapor deposition, atomic layer deposition, electroplating, and / or other suitable deposition techniques. The bonding vias 154 and bonding pads 156 can be deposited in one or more deposition operations. In some embodiments, a seed layer is first deposited in a dual damascene groove, and then the bonding vias 154 and bonding pads 156 are deposited on the seed layer. In some embodiments, a padding layer (e.g., an adhesive pad, a barrier pad) is first deposited in a dual damascene groove, and then the bonding vias 154 and bonding pads 156 are deposited on the padding layer. The padding layer may include a suitable padding material, such as tantalum nitride (TaN) and / or titanium nitride (TiN). In some embodiments, after depositing the bonding vias 154 and bonding pads 156, a planarization operation (e.g., chemical mechanical planarization) is performed using a planarization tool to planarize the bonding pads 156.

[0105] As described above, Figures 4A to 4J provide examples. Other examples may differ from those shown in Figures 4A to 4J.

[0106] Figure 5 is a schematic diagram of another embodiment 500 of the semiconductor device 102 described herein. As shown in Figure 5, embodiment 500 of the semiconductor device 102 may include combinations and arrangements of layers and / or structures similar to embodiment 100 of the semiconductor device 102 shown in Figure 1.

[0107] However, in Embodiment 500 of FIG5, a high aspect ratio of the capacitor structure 160 is achieved by directly connecting the top of the capacitor structure 160 to a bonding via 154 in the bonding layer 108 of the semiconductor device 102 (e.g., opposite to a top via 142 that connects the top of the capacitor structure 160 to the top of the interconnect layer 106), and by directly connecting the bottom of the capacitor structure 160 to the gate structure 502 (e.g., a polysilicon gate structure, a metal gate structure) of the integrated circuit device 112 in and / or on the substrate layer 110 of the semiconductor device 102. The direct connection of the top of the capacitor structure 160 to the bonding via 154 and the direct connection of the bottom of the capacitor structure 160 to the gate structure 502 of the integrated circuit device 112 allows the capacitor structure 160 to be contained within and extend through a portion of the bonding layer 108, and within and through the interconnect layer 106 to the device layer 104. This can increase the capacitance of capacitor structure 160 (e.g., up to 12 times or more, compared to the case where capacitor structure 160 only extends through interconnect layer 106).

[0108] As shown in Figure 5, a portion of the top electrode layer 166 at the top of the capacitor structure 160 can make physical contact (e.g., direct physical contact) with the bonding via 154 at the top of the capacitor structure 160. Therefore, the top electrode layer 166 can be directly electrically connected to the bonding via 154 in the bonding layer 108.

[0109] A bonding via 154 connected to the top electrode layer 166 of the capacitor structure 160 may extend through the cap layers 170 and 172. In some embodiments, the bonding via 154 connected to the top electrode layer 166 of the capacitor structure 160 may extend into the top electrode layer 166 such that the bottom surface of the bonding via 154 is recessed into the top electrode layer 166.

[0110] As further shown in FIG5, the bottom of capacitor structure 160 (e.g., the bottom electrode layer 162 portion of the bottom of capacitor structure 160) may be located on and / or in contact with the gate structure 502 (e.g., polysilicon gate structure, metal gate structure) of integrated circuit device 112 in and / or on the substrate layer 110 of semiconductor device 102. The gate structure 502 connected to capacitor structure 160 may be a gate structure of transistor structure and / or other types of integrated circuit structure. In some embodiments, the gate structure 502 connected to capacitor structure 160 may also be connected to one or more conductive structures 120 in interconnect layer 106 of semiconductor device 102. In some embodiments, the gate structure 502 connected to capacitor structure 160 may have a z-direction thickness (dimension D10) ranging from about 500 angstroms to about 1500 angstroms. However, other values ​​and ranges are also within the scope of this disclosure.

[0111] As further shown in Figure 5, the gate structure 502 can be extended into the shallow trench isolation (STI) region 504 of the substrate layer 110 for electrical isolation. The shallow trench isolation region 504 may contain one or more dielectric materials, such as silicon oxide (SiO x, e.g., SiO 2), silicon nitride (Si xN y), and / or other suitable dielectric materials.

[0112] One or more integrated circuit devices 112 in device layer 104 of semiconductor device 102 may include doped regions 506 under the gate structure 502 of semiconductor device 102. In some embodiments, doped regions 506 may include p-type doped regions (e.g., a region of substrate layer 110 is doped with one or more p-type dopants, such as boron (B) or gallium (Ga)). In some embodiments, doped regions 506 may include n-type doped regions (e.g., a region of substrate layer 110 is doped with one or more n-type dopants, such as arsenic (As) or phosphorus (P)). In some embodiments, the doped regions 506 may be omitted from integrated circuit device 112, and the substrate layer 110 region under the gate structure 502 of integrated circuit device 112 may be an undoped semiconductor material (e.g., undoped silicon (Si)).

[0113] The deep trench structure 178 of capacitor structure 160 may extend into and / or through interlayer dielectric layer 116, etch stop layer 118, etch stop layer 122, interlayer dielectric layer 124, etch stop layer 126, interlayer dielectric layer 128, etch stop layer 130 and / or interlayer dielectric layer 132, etch stop layer 134, interlayer dielectric layer 136, etch stop layer 146 and / or dielectric layer 148. The deep trench structure 178 of capacitor structure 160 may have one or more top view layouts according to the exemplary embodiments shown in FIG2A and / or FIG3A to FIG3E. In some embodiments, the deep trench structure 178 of capacitor structure 160 has a z-direction depth or height (dimension D11) ranging from about 4 micrometers to about 6 micrometers. However, other values ​​and ranges are also within the scope of this disclosure. In some embodiments, capacitor structure 160 may include more than one deep trench structure 178. For example, capacitor structure 160 may include two deep trench structures 178, three deep trench structures 178 and / or other numbers of deep trench structures 178.

[0114] As described above, Figure 5 is provided as an example. Other examples may differ from those described according to Figure 5.

[0115] Figure 6 is a diagram of another embodiment 600 of the semiconductor device 102 described herein. As shown in Figure 6, embodiment 600 of the semiconductor device 102 may include a combination and arrangement of layers and / or structures similar to embodiment 500 of the semiconductor device 102 shown in Figure 5. However, in embodiment 600 of Figure 6, the semiconductor device 102 omits the etch stop layer 146, the dielectric layer 148, and the bonding via 154. Instead, the bonding pad 156 is directly connected (e.g., physically and / or electrically) to the top metal layer 144 and directly connected (e.g., physically and / or electrically) to the top electrode layer 166 of the capacitor structure 160.

[0116] As shown in Figure 6, an etch stop layer 150 may be included on an interlayer dielectric layer 136, a dielectric layer 152 may be included on an etch stop layer 150, and a bonding dielectric layer 158 may be included on a dielectric layer 152. The top of the capacitor structure 160 may be included in the dielectric layer 152. In some embodiments, the vertical (z-direction) thickness of the dielectric layer 152 in embodiment 200 of the semiconductor device 102 may be in the range of about 6800 angstroms to about 16600 angstroms. However, other values ​​and ranges are also within the scope of this disclosure.

[0117] A bonding pad 156 connected to the top electrode layer 166 of the capacitor structure 160 may pass through the cap layers 170 and 172. In some embodiments, the bonding pad 156 connected to the top electrode layer 166 of the capacitor structure 160 may extend into the top electrode layer 166 such that the bottom surface of the bonding pad 156 is recessed into the top electrode layer 166.

[0118] As further shown in FIG6, the bottom of the capacitor structure 160 (e.g., a portion of the bottom electrode layer 162 located at the bottom of the capacitor structure 160) may be located in and / or in contact with the gate structure 502 (e.g., polysilicon gate structure, metal gate structure) of the integrated circuit device 112 included in the substrate layer 110 of the semiconductor device 102.

[0119] The deep trench structure 178 of capacitor structure 160 may extend into and / or through interlayer dielectric layer 116, etch stop layer 118, etch stop layer 122, interlayer dielectric layer 124, etch stop layer 126, interlayer dielectric layer 128, etch stop layer 130, and / or interlayer dielectric layer 132, etch stop layer 134, interlayer dielectric layer 136, etch stop layer 150, and / or dielectric layer 152. The deep trench structure 178 of capacitor structure 160 may have a top view layout according to one or more embodiments shown in FIG. 2A and / or FIG. 3A to 3E, as well as other examples. In some embodiments, capacitor structure 160 may include more than one deep trench structure 178. For example, capacitor structure 160 may include two deep trench structures 178, three deep trench structures 178, and / or other numbers of deep trench structures 178.

[0120] As shown above, Figure 6 is provided as an example. Other examples may differ from those illustrated in Figure 6.

[0121] Figures 7A to 7E are schematic diagrams of an embodiment 700 of forming the semiconductor device 102 described herein. Specifically, embodiment 700 includes an example of embodiment 500 forming the semiconductor device 102 shown in Figure 5. However, one or more semiconductor process operations described in relation to Figures 7A to 7E can be used to form the semiconductor device 102 of another embodiment described herein. In some embodiments, one or more semiconductor process operations described in relation to Figures 7A to 7E can be performed using one or more semiconductor process tools, such as deposition tools, exposure tools, development tools, etching tools, planarization tools, ion implantation tools, wafer / die transport tools, and / or other types of semiconductor process tools.

[0122] Referring to Figure 7A, a substrate layer 110 may be provided. The substrate layer 110 may be provided in the form of a semiconductor wafer, such as a silicon (Si) wafer, a silicon-on-insulator (SiO2) wafer, and / or other types of semiconductor devices. The semiconductor device 102 may be formed on the semiconductor wafer together with other semiconductor devices.

[0123] As shown in FIG7B, shallow trench isolation region 504 and integrated circuit device 112 may be formed in device layer 104 and / or substrate layer 110 of semiconductor device 102. To form shallow trench isolation region 504, a groove may be formed in substrate layer 110, and shallow trench isolation region 504 may be formed in the groove. In some embodiments, a pattern in a photoresist layer is used to etch substrate layer 110 to form the groove. In these embodiments, a photoresist layer may be formed on substrate layer 110 using deposition tools (e.g., using spin coating and / or other suitable deposition techniques). An exposure tool may be used to expose the photoresist layer to a radiation source to pattern the photoresist layer. A development tool may be used to develop and remove portions of the photoresist layer to expose the pattern. An etching tool may be used to etch substrate layer 110 based on the pattern to form the groove. A deposition tool may be used to deposit shallow trench isolation region 504 in the groove using physical vapor deposition, atomic layer deposition, chemical vapor deposition, oxidation techniques, and / or other suitable deposition techniques. In some embodiments, a planarization tool may be used to perform a planarization operation (e.g., a chemical mechanical planarization operation) on the shallow trench isolation region 504 after deposition to planarize the shallow trench isolation region 504.

[0124] One or more semiconductor fabrication tools can be used to form one or more portions of the integrated circuit device 112. For example, an ion implantation tool can be used to dope one or more regions in the substrate layer 110 with one or more types of dopants to form a doped region 506 of the integrated circuit device 112 in the substrate layer 110. As another example, deposition tools can be used to perform various deposition operations to deposit the gate structure 502 of the integrated circuit device 112. Yet another example is the use of exposure tools and etching tools to pattern and etch the gate structure 502.

[0125] As further shown in FIG7B, a dielectric layer 114 is deposited on and / or above the substrate layer 110 and on and / or above the integrated circuit device 112 using a deposition tool. The dielectric layer 114 can be deposited using physical vapor deposition, atomic layer deposition, chemical vapor deposition, oxidation techniques, and / or other suitable deposition techniques. In some embodiments, a planarization operation, such as a chemical mechanical planarization operation, can be performed on the dielectric layer 114 after deposition using a planarization tool to planarize the dielectric layer 114.

[0126] As shown in FIG7C, the interconnect layer 106 may be formed on the device layer 104 of the semiconductor device 102. The interlayer dielectric layers 116, 124, 128, 132, 136; etch stop layers 118, 122, 126, 130, 134; conductive structure 120; top vias 138, 142; and / or top metal layers 140, 144 of the interconnect layer 106 may be formed in a manner similar to that described in FIG4A to FIG4J. As further shown in FIG7C, a portion of the etch stop layer 146 and dielectric layer 148 of the bonding layer 108 may be formed on the interconnect layer 106.

[0127] As shown in Figure 7D, the capacitor structure 160 may be formed in and / or through the bonding layer 108, and in and / or through the interconnect layer 106. For example, a groove may be formed in the interlayer dielectric layers 116, 124, 128, 132, 136; the etch stop layers 118, 122, 126, 130, 134, 146; and the dielectric layer 148. A bottom electrode layer 162, an insulating layer 164, a top electrode layer 166, and a dielectric filler 168 may be formed in the groove. The groove may be formed downward to the gate structure 502 of the integrated circuit device 112 in the device layer 104. The bottom electrode layer 162 of the capacitor structure 160 may be formed in the groove such that a portion of the bottom electrode layer 162 lands on the exposed gate structure 502 in the groove.

[0128] As shown in Figure 7E, an additional portion of dielectric layer 148 may be formed over the top of capacitor structure 160 and over the first portion of dielectric layer 148. The top of capacitor structure 160 may be encapsulated within dielectric layer 148. An etch stop layer 150 of bonding layer 108 may be formed on dielectric layer 148, a dielectric layer 152 of bonding layer 108 may be formed on etch stop layer 150, and a bonding dielectric layer 158 of bonding layer 108 may be formed on dielectric layer 152. The additional portion of dielectric layer 148, etch stop layer 150, dielectric layer 152, and / or bonding dielectric layer 158 may be deposited using physical vapor deposition, atomic layer deposition, chemical vapor deposition, oxidation techniques, and / or other suitable deposition techniques. The additional portion of dielectric layer 148, etch stop layer 150, dielectric layer 152, and / or bonding dielectric layer 158 may be deposited in one or more deposition operations. In some embodiments, a planarization operation (e.g., a chemical mechanical planarization operation) may be performed using a planarization tool to planarize dielectric layer 148, etch stop layer 150, dielectric layer 152 and / or bonding dielectric layer 158.

[0129] As further shown in FIG7E, a bonding via 154 is formed in and / or through the dielectric layer 148 and the etch stop layer 146, and a bonding pad 156 is formed on the bonding via 154, such that the bonding pad 156 passes through the etch stop layer 150, the dielectric layer 152, and / or the bonding dielectric layer 158. The bonding via 154 may be formed in the via portion of a recess, such that the bonding via 154 lands on the top electrode layer 166 of the capacitor structure 160. In some embodiments, the bonding via 154 is formed such that the bonding via 154 is recessed into a portion of the top electrode layer 166. In other words, the bottom surface of the bonding via 154 may be located below the top surface of the top electrode layer 166.

[0130] The bonding vias 154 and bonding pads 156 can be deposited using chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), electroplating, and / or other suitable deposition techniques. The bonding vias 154 and bonding pads 156 can be deposited in one or more deposition operations. In some embodiments, a seed layer is first deposited, and then the bonding vias 154 and bonding pads 156 are deposited on the seed layer. In some embodiments, a padding layer (e.g., an adhesive pad, a barrier pad) is first deposited, and then the bonding vias 154 and bonding pads 156 are deposited on the padding layer. The padding layer may include a suitable padding material, such as tantalum nitride (TaN) and / or titanium nitride (TiN). In some embodiments, after depositing the bonding vias 154 and bonding pads 156, a planarization operation (e.g., CVD) is performed using a planarization tool to planarize the bonding pads 156.

[0131] As described above, Figures 7A to 7E are provided as an example. Other examples may differ from those described with respect to Figures 7A to 7E.

[0132] Figures 8A and 8B are diagrams of an exemplary embodiment 800 of forming the semiconductor device 102 described herein. Specifically, exemplary embodiment 800 includes exemplary embodiment 600 of forming the semiconductor device 102 shown in Figure 6. However, one or more semiconductor process operations described in relation to Figures 8A and 8B may be performed to form the semiconductor device 102 of another exemplary embodiment described herein. In some embodiments, one or more semiconductor process tools may be used to perform one or more semiconductor process operations described in relation to Figures 8A and 8B, such as deposition tools, exposure tools, development tools, etching tools, planarization tools, ion implantation tools, wafer / die transport tools, and / or other types of semiconductor process tools.

[0133] As shown in FIG8A, one or more semiconductor process operations described in relation to FIG7A to 7D can be performed to form device layer 104, interconnect layer 106, and capacitor structure 160. However, in example embodiment 800, the formation of etch stop layer 146 and dielectric layer 148 is omitted. Instead, etch stop layer 150 is formed on interlayer dielectric layer 136, dielectric layer 152 is formed on etch stop layer 150, and bonding dielectric layer 158 is formed on dielectric layer 152. The recess of capacitor structure 160 may be formed through a portion of dielectric layer 152 and through etch stop layer 150, rather than through a portion of dielectric layer 148 and through etch stop layer 146.

[0134] As shown in FIG8B, a bonding pad 156 is formed on the top electrode layer 166 of the capacitor structure 160. The bonding pad 156 may be formed in a recessed portion of the top electrode layer 166. In other words, the bottom surface of the bonding pad 156 may be located below the top surface of the top electrode layer 166. The bonding pad 156 may also be formed in a groove 504, allowing the bonding pad 156 to land on the top metal layer 144. In some embodiments, the bonding pad 156 may be planarized after being formed in the groove using a planarization tool.

[0135] As described above, Figures 8A and 8B are provided as examples. Other examples may differ from those described with respect to Figures 8A and 8B.

[0136] Figures 9A and 9B are diagrams of an example embodiment 900 of the semiconductor package 902 described herein. As shown in the cross-sectional view of the semiconductor package 902 in Figure 9A, the semiconductor package 902 is a three-dimensional (3D) structure comprising semiconductor devices 102a (e.g., a first semiconductor die) and 102b (e.g., a second semiconductor die) directly bonded together at a bonding interface 904, such that semiconductor devices 102a and 102b are stacked and vertically arranged within the semiconductor package 902. Semiconductor devices 102a and 102b may each include combinations and arrangements of layers and / or structures similar to those in the example embodiment 500 of the semiconductor device 102 shown in Figure 5, and may be formed through similar semiconductor process operations and / or techniques described in relation to Figures 7A to 7E.

[0137] At the bonding interface 904, semiconductor devices 102a and 102b can be bonded together via a combination of metal-to-metal bonding and dielectric-to-dielectric bonding. For example, the bonding pad 156 of semiconductor device 102a can be bonded to the bonding pad 156 of semiconductor device 102b at the bonding interface 904 via metal-to-metal bonding. Another example is that the bonding dielectric layer 158 of semiconductor device 102a can be bonded to the bonding dielectric layer 158 of semiconductor device 102b at the bonding interface 904 via dielectric-to-dielectric bonding.

[0138] In some embodiments, misalignment may occur between the bonding pad 156 of semiconductor device 102a and the bonding pad 156 of semiconductor device 102b at the bonding interface 904. Therefore, a misalignment region 906 may appear on one or more sides of the bonding pads 156 of semiconductor devices 102a and 102b. The misalignment region 906 may include the portion where the bonding surface of the bonding pad 156 of semiconductor device 102a contacts the bonding dielectric layer 158 of semiconductor device 102b. Another misalignment region 906 may include the portion where the bonding surface of the bonding pad 156 of semiconductor device 102b contacts the bonding dielectric layer 158 of semiconductor device 102a. In other words, the bonding pads 156 are laterally offset, such that the edges of the bonding pads 156 of the bonded semiconductor devices 102a and 102b may be misaligned.

[0139] In some embodiments, semiconductor package 902 is an image sensor device (e.g., a three-dimensional complementary metal-oxide-semiconductor (CMOS) image sensor (CIS) device). Therefore, semiconductor device 102a may include an application-specific integrated circuit (ASIC) die for the image sensor device, while semiconductor device 102b may include an image sensor die for the image sensor device. Thus, semiconductor device 102b may include a plurality of pixel sensors 908 in its substrate layer 110. Pixel sensors 908 may be configured to absorb photons of incident light and convert them into photocurrent to generate images and / or video. Semiconductor device 102a and / or semiconductor device 102b may include one or more capacitor structures 160 configured to store charge in the pixel sensors 908 to increase full-well conversion (FWC) of the pixel sensors 908 and / or enable semiconductor device 102b to implement a global shutter function.

[0140] For example, semiconductor device 102a may include a capacitor structure 160 directly connected to a bonding via 154 in bonding layer 108 of semiconductor device 102a. The capacitor structure 160 is electrically connected to bonding pad 156 of semiconductor device 102b through the bonding via 154 and the bonding pad 156 of semiconductor device 102a, which is physically connected to the bonding via 154 and the bonding pad 156 of semiconductor device 102b. This allows the capacitor structure 160 included in semiconductor device 102a to be electrically connected to a pixel sensor 908 included in semiconductor device 102b. Furthermore, the bottom of the capacitor structure 160 may be directly connected to a gate structure 502 in substrate layer 110 of semiconductor device 102a.

[0141] Additionally and / or alternatively, semiconductor device 102b may include a capacitor structure 160 directly connected to a bonding via 154 in bonding layer 108 of semiconductor device 102b. The capacitor structure 160 may be electrically connected to bonding pad 156 of semiconductor device 102a through bonding via 154 and bonding pad 156 of semiconductor device 102b, which is physically connected to bonding via 154 and bonding pad 156 of semiconductor device 102a. Furthermore, the bottom of capacitor structure 160 may be directly connected to a gate structure 502 in substrate layer 110 of semiconductor device 102b.

[0142] Figure 9B illustrates a top view of semiconductor package 902 and shows an example of a pixel sensor array 910 including multiple pixel sensors 908. As shown in Figure 9B, the pixel sensors 908 may be arranged in a grid pattern in the pixel sensor array 910. As further shown in Figure 9B, a peripheral region 912 may laterally surround the pixel sensor array 910. The peripheral region 912 may include other functional structures of semiconductor package 902, such as black level correction (BLC) structures and / or other pixel circuit elements (e.g., source-follower transistors, row-select transistors).

[0143] As further shown in FIG9B, a capacitor structure 160 included in semiconductor devices 102a and / or 102b may be located below the pixel sensor 908 of the pixel sensor array 910. A portion of the cross-section shown in FIG9A is indicated by line BB in FIG9B. Bonding pads 156 and bonding vias 154 of semiconductor devices 102a and 102b provide "in-pixel" connections between the pixel sensors 908 of the pixel sensor array 910 because the capacitor structure 160 on semiconductor device 102a may be located below the pixel sensor 908 and electrically connected to the pixel sensor 908 via the bonding vias 154 and bonding pads 156 below the pixel sensor 908 in semiconductor devices 102a and 102b.

[0144] As indicated above, Figures 9A and 9B are provided as examples. Other examples may differ from those described with respect to Figures 9A and 9B.

[0145] Figures 10A and 10B are diagrams of an exemplary embodiment 1000 of the semiconductor package 1002 described herein. As shown in the cross-sectional view of the semiconductor package 1002 in Figure 10A, the semiconductor package 1002 is a 3D structure including semiconductor devices 102a (e.g., a first semiconductor die) and semiconductor devices 102b (e.g., a second semiconductor die) directly bonded together at a bonding interface 1004, such that semiconductor devices 102a and 102b are stacked and vertically arranged within the semiconductor package 1002. Semiconductor devices 102a and 102b may each include combinations and arrangements of layers and / or structures similar to those in the exemplary embodiment 600 of the semiconductor device 102 shown in Figure 6, and may be formed through similar semiconductor process operations and / or techniques described in relation to Figures 7A-7E and / or 8A and 8B.

[0146] At the bonding interface 1004, semiconductor devices 102a and 102b can be bonded together via a combination of metal-to-metal bonding and dielectric-to-dielectric bonding. For example, the bonding pad 156 of semiconductor device 102a can be bonded to the bonding pad 156 of semiconductor device 102b at the bonding interface 1004 via metal-to-metal bonding. Another example is that the bonding dielectric layer 158 of semiconductor device 102a can be bonded to the bonding dielectric layer 158 of semiconductor device 102b at the bonding interface 1004 via dielectric-to-dielectric bonding.

[0147] In some embodiments, misalignment may occur between the bonding pad 156 of semiconductor device 102a and the bonding pad 156 of semiconductor device 102b at the bonding interface 1004. Therefore, a misalignment region 1006 may appear on one or more sides of the bonding pads 156 of semiconductor devices 102a and 102b. The misalignment region 1006 may include a portion of the bonding surface of the bonding pad 156 of semiconductor device 102a that contacts the bonding dielectric layer 158 of semiconductor device 102b. Another misalignment region 1006 may include a portion of the bonding surface of the bonding pad 156 of semiconductor device 102b that contacts the bonding dielectric layer 158 of semiconductor device 102a. In other words, the bonding pads 156 are laterally offset, such that the edges of the bonding pads 156 of the bonded semiconductor devices 102a and 102b may be misaligned.

[0148] In some embodiments, semiconductor package 1002 is an image sensor device (e.g., a 3D CIS device). Therefore, semiconductor device 102a may include an application-specific integrated circuit die for the image sensor device, while semiconductor device 102b may include an image sensor die for the image sensor device. Thus, semiconductor device 102b may include a plurality of pixel sensors (not shown) in its substrate layer 110. The pixel sensors may be configured to absorb photons of incident light and convert them into photocurrent to generate images and / or video. Semiconductor device 102a and / or semiconductor device 102b may include one or more capacitor structures 160 configured to store charge in the pixel sensor 1008 to increase the full-well capacity (FWC) of the pixel sensor and / or enable global shutter functionality in semiconductor device 102b.

[0149] For example, semiconductor device 102a may include a capacitor structure 160 directly connected to bonding pads 156 in bonding layer 108 of semiconductor device 102a. The capacitor structure 160 may be electrically connected to bonding pads 156 of semiconductor device 102b via bonding pads 156 of semiconductor device 102a (which are bonded to bonding pads 156 on semiconductor device 102b). This allows the capacitor structure 160 included in semiconductor device 102a to be electrically connected to a pixel sensor 1008 included in semiconductor device 102b. Furthermore, the bottom of the capacitor structure 160 may be directly connected to a gate structure 502 in substrate layer 110 of semiconductor device 102a.

[0150] Additionally and / or alternatively, semiconductor device 102b may include a capacitor structure 160 directly connected to bonding pads 156 in bonding layer 108 of semiconductor device 102b. The capacitor structure 160 may be electrically connected to bonding pads 156 of semiconductor device 102a via bonding pads 156 of semiconductor device 102b (which are bonded to bonding pads 156 on semiconductor device 102a). Furthermore, the bottom of capacitor structure 160 may be directly connected to a gate structure 502 in substrate layer 110 of semiconductor device 102b.

[0151] Figure 10B illustrates a top view of semiconductor package 1002 and shows an example of pixel sensor 1008 in pixel sensor array 1010. As shown in Figure 10B, pixel sensors 1008 may be arranged in a grid in pixel sensor array 1010. As further shown in Figure 10B, a peripheral region 1012 may laterally surround pixel sensor array 1010. Peripheral region 1012 may include other functional structures of semiconductor package 1002, such as BLC structures and / or other pixel circuit elements (e.g., source follower transistors, row select transistors).

[0152] As further shown in FIG10B, the capacitor structure 160 contained in semiconductor devices 102a and / or 102b may be located around the pixel sensor array 1010. For example, the capacitor structure 160 may be located in a peripheral region 1012, which may correspond to the die edge or die periphery of semiconductor devices 102a and / or 102b. A portion of the location of the cross-section shown in FIG10A is indicated by the CC line in FIG10B. Bonding pads 156 around semiconductor devices 102a and 102b provide connections between the pixel sensors 1008 of the pixel sensor array 1010 and the capacitor structure 160 on semiconductor device 102a.

[0153] As described above, Figures 10A and 10B are provided as examples. Other examples may differ from those illustrated with respect to Figures 10A and 10B.

[0154] Figure 11 is a flowchart of an exemplary process 1100 associated with the formation of the semiconductor device described herein. In some embodiments, one or more process blocks of Figure 11 are performed using one or more semiconductor process tools, such as deposition tools, exposure tools, development tools, etching tools, planarization tools, ion implantation tools, annealing tools, wafer / die transport tools, bonding tools, and / or other types of semiconductor process tools.

[0155] As shown in Figure 11, process 1100 may include forming one or more integrated circuit devices (block 1110) in a semiconductor layer of a semiconductor device. For example, one or more integrated circuit devices (e.g., one or more integrated circuit devices 112) may be formed in a semiconductor layer (e.g., substrate layer 110) of a semiconductor device (e.g., semiconductor device 102) using one or more semiconductor process tools, as described herein.

[0156] As further shown in Figure 11, process 1100 may include forming an interconnect layer (block 1120) of a semiconductor device on the semiconductor layer. For example, one or more semiconductor process tools may be used to form an interconnect layer (e.g., interconnect layer 106) of a semiconductor device on the semiconductor layer, as described herein.

[0157] As further shown in Figure 11, process 1100 may include forming a recess into the gate structure (502) of an integrated circuit device in one or more integrated circuit devices through multiple dielectric layers of the interconnect layer (block 1130). For example, one or more semiconductor process tools may be used to form a recess into the gate structure (e.g., gate structure 502) of an integrated circuit device in one or more integrated circuit devices through multiple dielectric layers of the interconnect layer (e.g., one or more interlayer dielectric layers 116, one or more etch stop layers 118, etch stop layer 122, interlayer dielectric layer 124, etch stop layer 126, interlayer dielectric layer 128, etch stop layer 130, interlayer dielectric layer 132, etch stop layer 134, interlayer dielectric layer 136), as described herein.

[0158] As further shown in Figure 11, process 1100 may include forming a trench capacitor structure of a semiconductor device in a recess, such that the trench capacitor structure lands on a gate structure (block 1140). For example, one or more semiconductor process tools may be used to form a trench capacitor structure (e.g., capacitor structure 160) of a semiconductor device in a recess, such that the trench capacitor structure lands on a gate structure, as described herein.

[0159] As further shown in Figure 11, process 1100 may include forming a bonding structure (block 1150) of a semiconductor device on the trench capacitor structure. For example, one or more semiconductor process tools may be used to form the bonding structure of the semiconductor device (e.g., bonding via 154, bonding pad 156) on the trench capacitor structure, as described herein.

[0160] Process 1100 may include additional embodiments, such as any single embodiment or any combination of embodiments of one or more other processes set forth below and / or set forth elsewhere herein.

[0161] In a first embodiment, forming a trench capacitor structure includes forming a plurality of interconnecting trench segments (e.g., trench segments 202a-202h) that are interconnected in a top view of the trench capacitor structure.

[0162] In the second embodiment, alone or in combination with the first embodiment, process 1100 includes bonding a semiconductor device to another semiconductor device (e.g., bonding semiconductor devices 102a and 102b), and bonding a bonding structure directly to another bonding structure of another semiconductor device (e.g., another bonding via 154, another bonding pad 156).

[0163] In the third embodiment, the joining structure and another joining structure are misaligned, either alone or in combination with one or more of the first and second embodiments.

[0164] In the fourth embodiment, forming a bonding structure, either alone or in combination with one or more of the first to third embodiments, includes forming a bonding via (e.g., bonding via 154) on the top electrode layer (e.g., top electrode layer 166) of the trench capacitor structure, wherein process 1100 further includes forming a bonding pad (e.g., bonding pad 156) on the bonding via.

[0165] Although Figure 11 shows an example block of process 1100, in some embodiments, process 1100 includes additional blocks, fewer blocks, different blocks, or blocks with a different configuration than those depicted in Figure 11. Alternatively, two or more blocks of process 1100 may be executed in parallel.

[0166] Thus, a trench capacitor structure (e.g., a deep trench capacitor structure) is formed in the semiconductor device, giving it a deep trench structure that includes multiple interconnect trench segments in a top view of the trench capacitor structure. The interconnect trench segments provide a larger sidewall surface area for the electrode and insulating layers of the trench capacitor structure, thereby increasing the capacitance of the trench capacitor structure. The interconnect trench segments may be contained within the perimeter of the trench capacitor structure to achieve a compact lateral footprint. Furthermore and / or otherwise, by extending the deep trench structure of the trench capacitor structure fully between the bonding structure of the semiconductor device and the underlying device layer of the semiconductor device, the vertical dimension of the trench capacitor structure can be increased (thereby increasing the capacitance of the trench capacitor structure). The bottom of the trench capacitor structure can be electrically connected to the gate structure of an integrated circuit device in the device layer.

[0167] As detailed above, some embodiments described herein provide a semiconductor device. The semiconductor device includes a semiconductor layer. The semiconductor device includes one or more integrated circuit devices, at least located in or on the semiconductor layer. The semiconductor device includes an interconnect layer above the semiconductor layer. The semiconductor device includes a capacitor structure extending vertically through the interconnect layer. The capacitor structure includes a top electrode layer and an insulating layer located between a bottom electrode layer and the top electrode layer. The bottom electrode layer, the top electrode layer, and the insulating layer extend and conform to the cross-sectional profile of a deep trench. In a top view of the deep trench structure, the deep trench includes trench segments of multiple interconnects.

[0168] As detailed above, some embodiments described herein provide a semiconductor device. The semiconductor device includes a semiconductor layer. The semiconductor device includes one or more integrated circuit devices, at least located in or on the semiconductor layer. The semiconductor device includes an interconnect layer above the semiconductor layer. The semiconductor device includes one or more conductive structures in the interconnect layer. The semiconductor device includes one or more bonding structures above the interconnect layer. The semiconductor device includes a trench capacitor structure extending vertically through the interconnect layer, wherein the top of the trench capacitor structure is coupled to one of the bonding structures, and the bottom of the trench capacitor structure is coupled to a gate structure of one or more integrated circuit devices.

[0169] As detailed above, some embodiments described herein provide a method. The method includes forming one or more integrated circuit devices in a semiconductor layer of a semiconductor device. The method includes forming an interconnect layer of the semiconductor device over the semiconductor layer. The method includes forming a trench through a plurality of dielectric layers of the interconnect layer to a gate structure of one of the one or more integrated circuit devices. The method includes forming a trench capacitor structure of the semiconductor device in the trench, such that the trench capacitor structure lands on the gate structure. The method includes forming a bonding structure of the semiconductor device on the trench capacitor structure.

[0170] The terms "approximately" and "substantially" can indicate that the value of a given quantity varies within a range of 5% of the value (e.g., ±1%, ±2%, ±3%, ±4%, ±5%). These values ​​are merely illustrative and not limiting. It should be understood that the terms "approximately" and "substantially" can refer to a percentage of the value of a given quantity as described in this disclosure.

[0171] The features of the above embodiments are designed to facilitate understanding of this disclosure by those skilled in the art. Those skilled in the art should understand that this disclosure can be used as a basis to design and modify other processes and structures to achieve the same purpose and / or the same advantages as the above embodiments. Those skilled in the art should also understand that these equivalent substitutions do not depart from the spirit and scope of this disclosure, and changes, substitutions, or modifications can be made without departing from the spirit and scope of this disclosure.

[0172] 100, 200, 300, 302, 304, 306, 308, 400, 500, 600, 700, 800, 900, 1000: Example Implementations 102, 102a, 102b: Semiconductor devices 104: Device Layer 106: Interconnect layer 108: Bonding layer 110: Substrate layer 112: Integrated circuit device 114, 148, 152: Dielectric layer 116, 124, 128, 132, 136: Interlayer dielectric layers 118, 122, 126, 130, 134, 146, 150: Etching stop layer 120: Conductive structure 138, 142: Top through holes 140, 144: Top metal layer 154: Connecting through hole 156: Joining Pad 158: Bonding Dielectric Layer 160: Capacitor Structure 162: Bottom Electrode Layer 164: Insulation layer 166: Top electrode layer 168: Dielectric filler 170, 172: Cap layer 174, 176: Sidewall gap wall 178, 178a, 178b: Deep trench structure 202a, 202b, 202c, 202d, 202e, 202f, 202g, 202h: Trench sections 204a, 204b, 204c, 204d, 204e, 204f, 204g, 204h, 204i: Connecting regions 402: Patterned Stacking 404: Advanced Exposure Pattern Thin Film Layer 406: Anti-reflective coating 408: Photoresist layer 410: Groove 502: Gate structure 504: Shallow trench isolation area 506: Doped region 902, 1002: Semiconductor packaging 904, 1004: Bonding Interface 906, 1006: Misalignment areas 908, 1008: Pixel sensor 910, 1010: Pixel sensor array 912, 1012: Surrounding areas 1100: Process 1110, 1120, 1130, 1140, 1150: Squares D1, D2, D3, D4, D5, D6, D7, D8, D9, D10, D11: Dimensions AA, BB, CC: lines

Claims

1. A semiconductor device, comprising: Semiconductor layer; One or more integrated circuit devices are located at least in or on the semiconductor layer; An interconnect layer is located above the semiconductor layer; The trench capacitor structure extends vertically through the interconnect layer and includes: a bottom electrode layer; a top electrode layer; and an insulating layer located between the bottom electrode layer and the top electrode layer, wherein the bottom electrode layer, the top electrode layer, and the insulating layer are conformal to the cross-sectional profile of the deep trench, and wherein, in a top view of the trench capacitor structure, the trench capacitor structure includes trench segments of a plurality of interconnects.

2. The semiconductor device of claim 1, wherein the trench segments of the plurality of interconnects include: First trench section; Second trench section; Third trench section; And a fourth trench segment, wherein the first end of the first trench segment and the first end of the third trench segment are connected in a first connection region, wherein the second end of the first trench segment and the first end of the fourth trench segment are connected in a second connection region, wherein the first end of the second trench segment and the second end of the third trench segment are connected in a third connection region, and wherein the second end of the second trench segment and the second end of the fourth trench segment are connected in a fourth connection region.

3. The semiconductor device of claim 2, wherein the trench segments of the plurality of interconnects include: Fifth trench section; And a sixth trench segment, wherein the first end of the fifth trench segment is connected in the first connection region to the first end of the first trench segment and the first end of the third trench segment, wherein the second end of the fifth trench segment is connected in the fourth connection region to the second end of the second trench segment and the second end of the fourth trench segment, wherein the first end of the sixth trench segment is connected in the third connection region to the first end of the second trench segment and the second end of the third trench segment, and wherein the second end of the sixth trench segment is connected in the second connection region to the second end of the first trench segment and the first end of the fourth trench segment.

4. The semiconductor device of claim 3, wherein the first trench, the second trench, the third trench, and the fourth trench are arranged in an approximately hollow rectangular layout in the top view of the trench capacitor structure; wherein the fifth trench segment extends diagonally between two corners of the approximately hollow rectangular layout; and wherein the sixth trench segment extends diagonally between the other two corners of the approximately hollow rectangular layout.

5. The semiconductor device of claim 2, wherein the trench segments of the plurality of interconnects include: Fifth trench section; And a sixth trench segment, wherein the first end of the fifth trench segment is connected to the first trench segment in a fifth connecting region, the fifth connecting region being located between the first end of the first trench segment and the second end of the first trench segment; wherein the second end of the fifth trench segment is connected to the second trench segment in a sixth connecting region, the sixth connecting region being located between the first end of the second trench segment and the second end of the second trench segment; wherein the first end of the sixth trench segment is connected to the third trench segment in a seventh connecting region, the seventh connecting region being located between the first end of the third trench segment and the second end of the third trench segment; and wherein the second end of the sixth trench segment is connected to the fourth trench segment in an eighth connecting region, the eighth connecting region being located between the first end of the fourth trench segment and the second end of the fourth trench segment.

6. The semiconductor device of claim 5, wherein the fifth trench segment and the sixth trench segment intersect in the ninth connection region.

7. The semiconductor device of claim 2, wherein the trench segments of the plurality of interconnects include: Fifth trench section; And a sixth trench segment, wherein the first end of the fifth trench segment is connected to the first trench segment in a fifth connecting region, the fifth connecting region being located between the first end of the first trench segment and the second end of the first trench segment; wherein the second end of the fifth trench segment is connected to the second trench segment in a sixth connecting region, the sixth connecting region being located between the first end of the second trench segment and the second end of the second trench segment; wherein the first end of the sixth trench segment is connected to the third trench segment in a seventh connecting region, the seventh connecting region being located between the first end of the third trench segment and the second end of the third trench segment; wherein the second end of the sixth trench segment is connected to the fourth trench segment in an eighth connecting region, the eighth connecting region being located between the first end of the fourth trench segment and the second end of the fourth trench segment.

8. A semiconductor device, comprising: Semiconductor layer; One or more integrated circuit devices are located in and on the semiconductor layer; An interconnect layer, located above the semiconductor layer and including one or more conductive structures electrically coupled to the one or more integrated circuit devices; one or more bonding structures, located above the interconnect layer; and a trench capacitor structure extending vertically through the interconnect layer, wherein the top of the trench capacitor structure is coupled to a bonding structure in the one or more bonding structures, and wherein the bottom of the trench capacitor structure is coupled to a gate structure in the one or more integrated circuit devices.

9. A method of forming a semiconductor device, comprising: One or more integrated circuit devices are formed in the semiconductor layer of a semiconductor device; An interconnect layer of the semiconductor device is formed above the semiconductor layer, wherein the interconnect layer includes a plurality of dielectric layers and one or more conductive structures formed in the plurality of dielectric layers and electrically coupled to the one or more integrated circuit devices; a groove is formed through the plurality of dielectric layers of the interconnect layer to reach the gate structure of one of the one or more integrated circuit devices; a trench capacitor structure of the semiconductor device is formed in the groove such that the trench capacitor structure lands on the gate structure; and a bonding structure of the semiconductor device is formed on the trench capacitor structure.

10. The method of claim 9, wherein forming the trench capacitor structure comprises: Groove segments forming multiple interconnected internal lines in a top view of the trench capacitor structure.

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