Method for manufacturing semiconductor structure

Abstract

A method for manufacturing a semiconductor structure includes the following steps: Receiving a substrate, wherein the substrate has a functional region and a virtual region surrounding the functional region; Forming a functional pattern on the functional region and a virtual pattern on the virtual region in the same process step, wherein the closest distance between the functional pattern and the virtual pattern is 15 nanometers to 50 nanometers; Removing the virtual pattern.

Description

Technical Field

[0001] This disclosure relates to a method for manufacturing a semiconductor structure. Prior Technology

[0002] Lithography is a process that uses photoresist as a photomask to create patterned structures. Therefore, the robustness of the photoresist is crucial for pattern definition. As technological advancements drive continuous miniaturization, various technical challenges arise. For example, some semiconductor structures cannot be successfully formed due to miniaturization.

[0003] Therefore, it is necessary to improve semiconductor manufacturing processes, especially lithography. Summary of the Invention

[0004] This disclosure provides a method for manufacturing a semiconductor structure. The method includes the following steps: receiving a substrate having a functional region and a virtual region surrounding the functional region; forming a functional pattern on the functional region and a virtual pattern on the virtual region in the same process step, wherein the closest distance between the functional pattern and the virtual pattern is 15 nanometers to 50 nanometers; and removing the virtual pattern.

[0005] According to one or more embodiments of this disclosure, the density of the functional pattern is substantially equal to the density of the virtual pattern.

[0006] According to one or more embodiments of this disclosure, the material of the functional pattern is the same as the material of the virtual pattern.

[0007] According to one or more embodiments of this disclosure, the pattern of the functional pattern is different from the pattern of the virtual pattern.

[0008] According to one or more embodiments of this disclosure, the pattern of the functional pattern is the same as the pattern of the virtual pattern.

[0009] According to one or more embodiments of this disclosure, the linewidth of the functional pattern is less than 20 nanometers.

[0010] Another aspect of this disclosure is to provide a method for manufacturing a semiconductor structure. This method includes the following steps: receiving a substrate, wherein the substrate has functional regions and virtual regions surrounding the functional regions; forming a stacked layer on the substrate; patterning the stacked layer to form bit line structures on the functional regions and simultaneously forming virtual patterns on the virtual regions, wherein the closest distance between the bit line structures and the virtual patterns is 15 nanometers to 50 nanometers; patterning the bit line structures to form a plurality of bit lines on the functional regions and a plurality of trenches surrounding these bit lines; and removing the virtual patterns.

[0011] According to one or more embodiments of this disclosure, the density of the bitline structure is substantially equal to the density of the virtual pattern.

[0012] According to one or more embodiments of this disclosure, the pattern of the bitline structure differs from the pattern of the virtual pattern.

[0013] According to one or more embodiments of this disclosure, the pattern of the bitline structure is the same as the pattern of the virtual pattern.

[0014] According to one or more embodiments of this disclosure, the linewidth of each line is less than 20 nanometers.

[0015] According to one or more embodiments of this disclosure, the stacked layer includes an oxide layer, a polycrystalline silicon layer, a first nitride layer, a metal layer, and a second nitride layer stacked sequentially on a substrate from bottom to top.

[0016] According to one or more embodiments of this disclosure, each bit line includes an oxide layer, a polycrystalline silicon layer, a first nitride layer, a metal layer, and a second nitride layer stacked sequentially on a substrate from bottom to top.

[0017] According to one or more embodiments of this disclosure, a method of manufacturing a semiconductor structure further includes forming a filling material in the trench to surround the bit line.

[0018] According to one or more embodiments of this disclosure, the top surface of the filler material is flush with the top surface of the bit line.

[0019] According to one or more embodiments of this disclosure, patterning the bitline structure and removing the virtual pattern are performed in the same process step.

[0020] It should be understood that the foregoing general description and the following detailed description are exemplary and explanatory only, and are intended to provide further explanation of the claimed content of this disclosure. Simple Explanation of the Diagram

[0021] This disclosure can be more fully understood by reading the following detailed description of the embodiments and referring to the accompanying drawings. Figure 1 is a top view schematic diagram of a substrate according to some embodiments of the present disclosure. Figure 2 is a top view of the pattern in region R of Figure 1, enlarged according to some embodiments of the present disclosure. Figure 3 is a top view showing an enlarged view of the pattern in region R of Figure 1, according to some other embodiments of the present disclosure. Figure 4 is an enlarged top view of the pattern in region R' of the comparative example. Figures 5 and 6 are schematic cross-sectional views of semiconductor structures at various manufacturing stages according to some embodiments of the present disclosure. Figure 7 is a top view schematic diagram of a cutout masking layer according to some embodiments of the present disclosure. Figures 8 through 11 are schematic cross-sectional views of semiconductor structures at various manufacturing stages according to some embodiments of the present disclosure. Implementation

[0022] Embodiments of the present disclosure will now be described in detail, examples of which are illustrated in the accompanying drawings. Where possible, the same reference numerals are used in the drawings and description to refer to the same or similar parts.

[0023] The following are specific embodiments of the present disclosure, described in detail with reference to the accompanying drawings. The elements and designs in the following embodiments are for simplification of the disclosed invention and are not intended to limit the scope of the disclosure. The description mentions that a first structural feature is located on top of a second structural feature, which includes embodiments where the first and second structural features are in direct contact, and also includes embodiments where there are other structural features between the first and second structural features, i.e., the first and second structural features are not in direct contact. Furthermore, the present disclosure may use repeated reference numerals and / or words in various embodiments. These repeated numerals or words are for simplification and clarity purposes and are not intended to limit the various embodiments and / or the relationship between the structures described.

[0024] Furthermore, for ease of description, spatial relative terms such as "below," "under," "lower," "above," "above," "upper," and the like are used herein to describe the relationship of an element or feature to one or more other elements or features illustrated in the figures. In addition to the orientations depicted in the figures, spatial relative terms are also intended to cover different orientations of the device in use or operation. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatial relative descriptors used herein can be interpreted accordingly.

[0025] Unless otherwise defined, all terms used herein (including technical and scientific terms) shall have the same meaning as commonly understood by one of ordinary skill in the art to which the embodiments of this disclosure pertain. It should be understood that terms defined, for example, in common dictionaries, shall be interpreted as having the same meaning as they have in the relevant field and in the context of this disclosure, and shall not be construed as, or as having, an overly formal meaning unless expressly defined herein.

[0026] Figure 1 is a top view schematic diagram of a substrate according to some embodiments of the present disclosure. One aspect of the present disclosure is to provide a method for manufacturing a semiconductor structure. This method includes the following steps.

[0027] Although the methods described herein are illustrated using a series of operations or steps, the order in which these operations or steps are shown should not be construed as a limitation of this disclosure. For example, some operations or steps may be performed in a different order and / or simultaneously with other steps. Furthermore, it is not necessary to perform all illustrated operations, steps, and / or features to achieve the implementation of this disclosure. Additionally, each operation or step described herein may comprise several sub-steps or actions.

[0028] In this disclosure, "patterning" and "patterned" describe the operation of forming a predetermined pattern on a surface. This patterning operation includes various steps and procedures, which vary depending on the embodiment. In some embodiments, the patterning process is used to pattern an existing film or layer. The patterning process includes forming a mask on the existing film or layer and removing the unmasked film or layer by etching or other removal processes. The mask may be a photoresist or a hard mask. In some embodiments, the patterning process is used to directly form a patterned layer on a surface. The patterning process includes forming a photosensitive film on the surface, performing a photolithography process, and performing a development process. The remaining photosensitive film is retained and integrated into a semiconductor device.

[0029] A receiving substrate 100 is provided, wherein the substrate 100 has a functional region FA and a virtual region DA surrounding the functional region FA, as shown in Figure 1.

[0030] Figure 2 is a magnified top view of the pattern in region R of Figure 1, according to some embodiments of the present disclosure. Figure 3 is a magnified top view of the pattern in region R of Figure 1, according to other embodiments of the present disclosure. Next, in the same process step, a functional pattern FP is formed on the functional region FA and a virtual pattern DP is formed on the virtual region DA. Notably, the closest distance CD between the virtual pattern DP and the functional pattern FP is from 15 nanometers (nm) to approximately 50 nm. For example, the closest distance CD between the virtual pattern DP and the functional pattern FP can be 20 nm, 25 nm, 30 nm, 35 nm, 40 nm, or 45 nm. Then, the virtual pattern DP is removed.

[0031] Understandably, by designing a virtual pattern DP in a virtual region DA adjacent to the functional region FA, the etching load between the functional region FA and the virtual region DA can be balanced to prevent excessive differences in etching load between the two regions, which could lead to defects in the functional pattern FP at the edge of the functional region FA, as shown in Figures 2 and 3. Therefore, the closest distance CD between the virtual pattern DP and the functional pattern FP is approximately 15nm to 50nm. When the closest distance CD between the virtual pattern DP and the functional pattern FP is greater than a certain value, such as 50nm, the difference in etching load between the functional region FA and the virtual region DA still cannot be reduced. Conversely, when the closest distance CD between the virtual pattern DP and the functional pattern FP is less than a certain value, such as 15nm, incomplete etching of the functional pattern may occur.

[0032] According to one or more embodiments of this disclosure, the density of the functional pattern FP is substantially equal to the density of the virtual pattern DP. According to one or more embodiments of this disclosure, the pattern of the functional pattern FP differs from the pattern of the virtual pattern DP, as shown in Figure 2. For example, the virtual pattern DP may include straight lines, horizontal lines, diagonals, geometric patterns, irregular patterns, or any suitable pattern, but is not limited thereto. According to one or more embodiments of this disclosure, the pattern of the functional pattern FP is the same as the pattern of the virtual pattern DP, as shown in Figure 3. According to one or more embodiments of this disclosure, the linewidth LW of the functional pattern FP is less than 20 nm. According to one or more embodiments of this disclosure, the material of the virtual pattern DP is the same as the material of the functional pattern FP.

[0033] Figure 4 is a magnified top view of the pattern in region R' of the comparative example. In this comparative example, no virtual pattern was designed within the virtual region DA'. However, the etching process in the comparative example may not run successfully, especially as the technology node continues to shrink. As the linewidth LW' narrows, the photoresist line becomes more fragile. Specifically, after the etching process, the functional pattern FP' at the edge of the functional region FA' collapses. Since there is no virtual pattern within the virtual region DA', the etching load within the functional region FA' is much greater than that within the virtual region DA', resulting in uneven etching. As the aspect ratio of the pattern increases, the effect of the undercut also increases, making pattern collapse more likely.

[0034] Another aspect of this disclosure is a method for manufacturing a semiconductor structure (e.g., a memory structure). In advanced technologies, process windows require greater attention. The array region and peripheral region within a dynamic random-access memory (DRAM) cell have different pattern densities and different functions after the DRAM cell's manufacturing process is complete. Therefore, the process windows between the array region and the peripheral region differ significantly. Typically, their respective circuit patterns may not be formed simultaneously.

[0035] In semiconductor multi-patterning processes, such as self-aligned double patterning (SADP) or self-aligned quadruple patterning (SAQP), a chop mask layer is required to transfer critical patterns onto the wafer. For example, the metal zero (MO) layer is a critical layer because it connects to multiple subsequent interconnect structures. In some embodiments, the fabrication of the MO layer involves two separate processes: a peripheral region process and an array region process. The peripheral region process is used to form patterns in the peripheral region of the DRAM cell. The array region process is used to form patterns in the array region of the DRAM cell.

[0036] Figures 5 to 6 and 8 to 11 are schematic cross-sectional views of a semiconductor structure shown along line X'-X within region R in Figure 1 at various manufacturing stages, according to some embodiments of this disclosure. This method includes the following steps. Referring to Figure 1, a receiving substrate 100 is provided, wherein the substrate 100 has a functional region FA and a virtual region DA surrounding the functional region FA.

[0037] Please refer to Figure 5. According to one or more embodiments of this disclosure, substrate 100 may include at least one transistor 102 in functional region FA. According to one or more embodiments of this disclosure, substrate 100 may also include at least one landing pad (not shown) disposed on transistor 102 in functional region FA. In some embodiments, the landing pad is gate-coupled to transistor 102.

[0038] According to one or more embodiments of this disclosure, substrate 100 may include a plurality of isolation regions (not shown) and a plurality of active regions (not shown). The active regions are separated by the isolation regions. The isolation regions may be formed using a shallow trench isolation (STI) process. The isolation regions may include, for example, a material comprising at least one of silicon oxide, silicon nitride, and silicon oxynitride. The isolation regions may be a single layer comprising one insulator, a double layer comprising two insulators, or a multilayer comprising a combination of at least three insulators. For example, the isolation regions may include silicon nitride and silicon oxide. For example, the isolation regions may include a triple layer of silicon oxide, silicon nitride, and silicon oxynitride.

[0039] According to one or more embodiments of this disclosure, substrate 100 may include, for example, silicon (e.g., crystalline silicon, polycrystalline silicon, or amorphous silicon). In some embodiments, substrate 100 may include other elemental semiconductors, such as germanium. In some embodiments, substrate 100 may include alloy semiconductors such as silicon germanium, gallium indium phosphide, and silicon germanium carbide. In some embodiments, substrate 100 may include compound semiconductors such as silicon carbide, gallium arsenide, indium phosphide, and indium arsenide. Furthermore, substrate 100 may optionally include a semiconductor-on-insulator (SOI) structure.

[0040] Referring to Figure 5, a stacked layer is formed on substrate 100. According to some embodiments, this stacked layer includes at least an oxide layer 112, a polycrystalline silicon layer 114, a first nitride layer 116, a metal layer 118, and a second nitride layer 120, stacked sequentially from bottom to top on substrate 100. According to one or more embodiments of this disclosure, the oxide layer 112, polycrystalline silicon layer 114, first nitride layer 116, metal layer 118, and second nitride layer 120 have a flat top surface and a flat bottom surface, as shown in Figure 5. In some embodiments, the metal layer 118 may include tungsten (W), aluminum (Al), cobalt (Co), copper (Cu), or other suitable metals or metal alloys. In some embodiments, the first nitride layer 116 (also referred to as a barrier layer) may be omitted. That is, the metal layer 118 may be in direct contact with the polycrystalline silicon layer 114. In some embodiments, the layers in the stack may be formed using methods such as chemical vapor deposition, physical vapor deposition, or sputtering. In some embodiments, each layer in the stack has a substantially flat surface.

[0041] Referring to Figure 6, the stacked layers are patterned to form a bit line structure (BLS) on the functional region FA and a virtual pattern (DP) on the virtual region DA. Specifically, the stacked layers are double-patterned in the direction perpendicular to the substrate 100. Double patterning may include, but is not limited to, litho-etch-litho-etch (LELE) spacing or self-aligned double patterning (SADP). Here, the bit line structure (BLS) is a continuous basic structure. In some embodiments, the material of the virtual pattern (DP) is the same as that of the bit line structure (BLS). More specifically, the virtual pattern (DP) includes an oxide layer 112, a polycrystalline silicon layer 114, a first nitride layer 116, a metal layer 118, and a second nitride layer 120, stacked sequentially from bottom to top on the substrate 100. Similarly, the bit line structure (BLS) also includes an oxide layer 112, a polycrystalline silicon layer 114, a first nitride layer 116, a metal layer 118, and a second nitride layer 120, which are stacked sequentially from bottom to top on the substrate 100.

[0042] It is worth noting that the nearest distance CD between the virtual pattern DP and the bit line structure BLS is approximately 15 nm to 50 nm. For example, the nearest distance CD between the virtual pattern DP and the bit line structure BLS can be 20 nm, 25 nm, 30 nm, 35 nm, 40 nm, or 45 nm. When the nearest distance CD between the virtual pattern DP and the functional pattern FP is greater than a certain value, such as 50 nm, it is still impossible to reduce the difference in etch load between the functional region FA and the virtual region DA. Conversely, when the nearest distance CD between the virtual pattern DP and the functional pattern FP is less than a certain value, such as 15 nm, it may cause incomplete etching of the functional pattern.

[0043] It is worth noting that the bit line structure (BLS) and the virtual pattern (DP) are formed simultaneously. In other words, the bit line structure (BLS) and the virtual pattern (DP) are formed using the same mask.

[0044] According to one or more embodiments of this disclosure, the density of the bit line structure (BLS) is substantially equal to the density of the virtual pattern (DP). According to one or more embodiments of this disclosure, the pattern of the bit line structure (BLS) differs from the pattern of the virtual pattern (DP), as shown in Figure 2. For example, the virtual pattern (DP) may include straight lines, horizontal lines, diagonals, geometric patterns, irregular patterns, or any suitable pattern, but is not limited thereto. According to one or more embodiments of this disclosure, the pattern of the bit line structure (BLS) is the same as the pattern of the virtual pattern (DP) shown in Figure 3. According to one or more embodiments of this disclosure, the linewidth (LW) of the bit line structure (BLS) is less than 20 nm.

[0045] Next, the bit line structure BLS is patterned to form multiple bit lines BL and multiple trenches 160 around these bit lines BL on the functional region FA. As described in more detail below, the virtual pattern DP on the virtual region DA is removed. According to one or more embodiments of this disclosure, the patterning of the bit line structure BLS and the removal of the virtual pattern DP are performed in the same process step.

[0046] Figure 7 is a top view schematic diagram of a cutout masking layer according to some embodiments of the present disclosure. The cutout masking layer CM shown in Figure 7 is used to define a virtual region DA and a functional region FA. The virtual region DA surrounds the functional region FA. As shown in Figure 7, the cutout masking layer CM includes at least one rectangular pattern, i.e., the rectangular pattern has a rectangular outline to define the functional region FA. This rectangular pattern corresponds to the functional region FA of the substrate 100 shown in Figure 1.

[0047] Referring to Figure 8, a notch mask layer CM is formed above the substrate 100. Furthermore, a virtual pattern DP is exposed from the notch mask layer CM. More specifically, multiple portions of the bit line structure BLS are exposed from the notch mask layer CM (not shown).

[0048] Please refer to Figure 9. Remove the exposed portions of the virtual pattern DP and bit line structure BLS. Therefore, the virtual pattern DP does not exist on the virtual region DA of the substrate 100, while the bit line BL is formed on the functional region FA of the substrate 100, where the bit line BL is still covered by the cutout masking layer CM.

[0049] Referring to Figure 10, the notch masking layer CM is removed, and the trench 160 is located between adjacent bit lines BL. According to one or more embodiments of this disclosure, each bit line BL includes an oxide layer 112, a polycrystalline silicon layer 114, a first nitride layer 116, a metal layer 118, and a second nitride layer 120 stacked sequentially from bottom to top on a substrate. According to one or more embodiments of this disclosure, the bit line BL is electrically connected to a transistor 102.

[0050] Referring to Figure 11, a filler material 170 is formed in trench 160. Specifically, the filler material 170 surrounds the bit line BL. In some embodiments, after the filler material 170 is filled in trench 160, a planarization process (e.g., chemical mechanical planarization) is performed. According to one or more embodiments of this disclosure, the top surface of the filler material 170 is flush with the top surface of the bit line BL. In some embodiments, the filler material 170 (e.g., CVD oxide, TEOS oxide, or other dielectric) is deposited into trench 160.

[0051] In some embodiments, at least one capacitor (not shown) is formed over the substrate 100. The capacitor includes a bottom electrode, a dielectric layer, and a top electrode. The dielectric layer comprises a high-k dielectric material. This capacitor is electrically connected to the gate of the transistor 102.

[0052] The above embodiments offer several advantages. Embodiments of this disclosure disclose a self-aligned double patterning (SADP) technique for defining functional patterns in functional regions of a substrate within a semiconductor structure. Due to linewidth considerations (less than 20 nanometers), functional patterns (e.g., bit lines) require two lithography processes and two etching processes. Adding virtual patterns to the virtual regions where bit lines are fabricated on the substrate at the MO layer can increase the stability and integrity of the peripheral bit line patterns. Therefore, by designing virtual patterns in virtual regions adjacent to functional regions, the etching load between functional regions and virtual regions can be balanced to avoid excessive differences in etching load between the two regions, which could cause functional pattern defects at the edges of the functional regions.

[0053] Although this disclosure has been described in considerable detail with reference to certain embodiments, other embodiments may also be possible. Therefore, the spirit and scope of the appended claims should not be limited to the description of the embodiments included herein.

[0054] It will be apparent to those skilled in the art that various modifications and variations can be made to the structure of this disclosure without departing from its scope or spirit. In view of the foregoing, this disclosure is intended to cover modifications and variations of this disclosure that fall within the scope of the appended patent applications.

[0055] 100:Substrate 102: Transistor 112: Oxide layer 114: Polycrystalline silicon layer 116: First nitride layer 118: Metal layer 120: Second nitride layer 160: Trench 170: Filling material BL: Bitline BLS: Bitline Structure CD: Closest Distance CM: Cutout Masking Layer DA: Virtual Region DA': Virtual Region DP: Virtual Pattern FA: Functional Area FA': Functional Area FP: Functional pattern FP': Functional pattern LW: Line width LW': Line width R: Region R': Region X'-X: Line

[0056] Domestic storage information (please note in order of storage institution, date, and number) none Overseas storage information (please note in the order of storage country, institution, date, and number) none

Claims

1. A method for manufacturing a semiconductor structure, comprising: Receive a substrate having a functional region and a virtual region surrounding the functional region; In the same process step, a functional pattern is formed on the functional area and a virtual pattern is formed on the virtual area, wherein the closest distance between the functional pattern and the virtual pattern is 15 nanometers to 50 nanometers; and the virtual pattern is removed.

2. A method for manufacturing a semiconductor structure as described in claim 1, wherein a density of the functional pattern is substantially equal to a density of the virtual pattern.

3. A method for manufacturing a semiconductor structure as described in claim 1, wherein a material of the functional pattern is the same as a material of the virtual pattern.

4. A method for manufacturing a semiconductor structure as described in claim 1, wherein a pattern of the functional pattern is different from a pattern of the virtual pattern.

5. A method for manufacturing a semiconductor structure as described in claim 1, wherein a pattern of the functional pattern is identical to a pattern of the virtual pattern.

6. A method for manufacturing a semiconductor structure as described in claim 1, wherein the line width of the functional pattern is less than 20 nanometers.

7. A method for manufacturing a semiconductor structure, comprising: Receive a substrate having a functional region and a virtual region surrounding the functional region; A stacked layer is formed on the substrate; The stacked layer is patterned to form a bitline structure on the functional region and simultaneously form a virtual pattern on the virtual region, wherein the closest distance between the bitline structure and the virtual pattern is 15 nanometers to 50 nanometers; the bitline structure is patterned to form a plurality of bitlines and a plurality of trenches surrounding the bitlines on the functional region; and the virtual pattern is removed.

8. A method for manufacturing a semiconductor structure as described in claim 7, wherein a density of the bit line structure is substantially equal to a density of the virtual pattern.

9. A method for manufacturing a semiconductor structure as described in claim 7, wherein a pattern of the bit line structure is different from a pattern of the virtual pattern.

10. A method for manufacturing a semiconductor structure as described in claim 7, wherein a pattern of the bit line structure is identical to a pattern of the virtual pattern.

11. A method for manufacturing a semiconductor structure as described in claim 7, wherein the line width of each bit line is less than 20 nanometers.

12. A method of manufacturing a semiconductor structure as claimed in claim 7, wherein the stacked layer comprises an oxide layer, a polycrystalline silicon layer, a first nitride layer, a metal layer and a second nitride layer stacked sequentially from bottom to top on the substrate.

13. A method of manufacturing a semiconductor structure as claimed in claim 7, wherein each bit line comprises an oxide layer, a polysilicon layer, a first nitride layer, a metal layer and a second nitride layer stacked sequentially from bottom to top on the substrate.

14. The method for manufacturing the semiconductor structure as described in claim 11 further includes: A filling material is formed in these trenches to surround these bit lines.

15. A method of manufacturing a semiconductor structure as claimed in claim 14, wherein a top surface of the filling material is flush with a plurality of top surfaces of the bit lines.

16. A method for manufacturing a semiconductor structure as described in claim 11, wherein patterning the bitline structure and removing the dummy pattern are performed in the same process step.

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