Monolithic device structure and manufacturing method thereof

Abstract

A single-chip device structure includes a silicon substrate with an active region, a semiconductor element, an oxide semiconductor field-effect transistor (OSFET), and a connection structure for electrically connecting the semiconductor element to the OSFET. The semiconductor element is disposed on the silicon substrate within the active region, wherein the drain of the semiconductor element is electrically connected to a read word line, and the source of the semiconductor element is electrically connected to a read bit line. The OSFET is disposed above the semiconductor element. The OSFET includes at least an oxide semiconductor layer, a top gate, a bottom gate, first and second gate insulating layers, a source electrode, and a drain electrode. The top gate is electrically connected to a write word line. The source electrode is electrically connected to the gate of the semiconductor element via a storage node of the connection structure, and the drain electrode is electrically connected to the write bit line.

Claims

1. A single-chip device structure, comprising: Silicon substrate; A component isolation structure is disposed in the silicon substrate to define the active region; A semiconductor element is disposed on the silicon substrate within the active region, wherein the drain of the semiconductor element is electrically connected to the read word line, and the source of the semiconductor element is electrically connected to the read bit line; an oxide semiconductor field-effect transistor (OSFET) is disposed above the semiconductor element; The OSFET includes: an oxide semiconductor layer disposed above the semiconductor element; a top gate disposed above the oxide semiconductor layer, wherein the top gate is electrically connected to a write word line; a bottom gate disposed below the oxide semiconductor layer, wherein the bottom gate is electrically connected to the top gate; a first gate insulating layer disposed between the oxide semiconductor layer and the top gate; a second gate insulating layer disposed between the oxide semiconductor layer and the bottom gate; a source electrode disposed on the oxide semiconductor layer on a first side of the top gate, wherein the source electrode is electrically connected to the gate of the semiconductor element via a storage node of the connection structure; and a drain electrode disposed on the oxide semiconductor layer on a second side of the top gate, wherein the drain electrode is electrically connected to a write bit line. The connection structure includes: Multiple contacts are disposed above the semiconductor element for electrically connecting the source, drain and gate of the semiconductor element, respectively; and a metal layer is disposed above the multiple contacts, wherein the metal layer includes the storage node, a first portion and a second portion, and the storage node, the first portion and the second portion are electrically isolated.

2. The single-chip device structure as claimed in claim 1, wherein, in a top view, the bottom gate and the top gate have the same direction of extension.

3. The single-chip device structure as claimed in claim 1, wherein the source of the semiconductor element is electrically connected to the read bit line via the first portion, and the drain of the semiconductor element is electrically connected to the read word line via the second portion.

4. The single-chip device structure as described in claim 1, further comprising: Metal wiring is installed above the top gate; And multiple through-holes electrically connect the metal wiring to the storage node.

5. The single-chip device structure as claimed in claim 4, wherein the source electrode is electrically connected to the gate of the semiconductor element via the storage node, the contact, the via, and the metal wiring.

6. The single-chip device structure as claimed in claim 1, wherein the first gate insulating layer is further disposed between the top gate and the source electrode and between the top gate and the drain electrode.

7. A method for manufacturing a single-chip device structure, comprising: Silicon substrates are provided; A device isolation structure is formed in the silicon substrate to define the active region; A semiconductor device is formed, wherein the semiconductor device includes a gate on the silicon substrate and a source and a drain in the active region on both sides of the gate; a back-end processing (BEOL) structure is formed on the semiconductor device, wherein the BEOL structure includes a storage node; an oxide semiconductor field-effect transistor (OSFET) is formed on the BEOL structure, wherein the OSFET includes an oxide semiconductor layer, a top gate disposed on the oxide semiconductor layer, a bottom gate disposed below the oxide semiconductor layer, a first gate insulating layer disposed between the oxide semiconductor layer and the top gate, a second gate insulating layer disposed between the oxide semiconductor layer and the bottom gate, and a source electrode and a drain electrode disposed on the oxide semiconductor on both sides of the top gate; and an interconnection structure is formed to electrically connect the source electrode to the gate of the semiconductor device via the storage node.

8. The manufacturing method as described in claim 7, further comprising, prior to forming the BEOL structure: Multiple contacts are formed above the semiconductor element, which are used to electrically connect the source, the gate, and the gate of the semiconductor element, respectively.

9. The manufacturing method as described in claim 8, wherein the step of forming the BEOL structure includes: A metal layer is formed over the plurality of contacts, wherein the metal layer includes the storage node, a first portion and a second portion, wherein the storage node, the first portion and the second portion are electrically isolated.

10. The manufacturing method of claim 9, wherein the source of the semiconductor element is electrically connected to a read bit line via the first portion, and the drain of the semiconductor element is electrically connected to a read word line via the second portion.

11. The manufacturing method as described in claim 7, wherein the step of forming the BEOL structure includes: Forming a dielectric layer; Multiple vias are formed through the dielectric layer; A metal layer is formed on the dielectric layer and electrically connected to the plurality of vias.

12. The manufacturing method as claimed in claim 11, wherein the bottom gate and the metal layer formed on the dielectric layer are the same layer.

13. The manufacturing method as described in claim 7, wherein the step of forming the connection structure includes: Multiple vias are formed above the OSFET for electrically connecting the source electrode, drain electrode, bottom gate, and top gate of the OSFET; and metal wiring is formed on the multiple vias.

14. The manufacturing method as claimed in claim 13, wherein the drain electrode is electrically connected to the write bit line via one of the plurality of vias.

15. The manufacturing method as claimed in claim 13, wherein the top gate is electrically connected to the write character line via one of the plurality of vias.

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