Data processing method and data processing apparatus

Abstract

Disclosed in the embodiments of the present application are a data processing method and a data processing apparatus. The method specifically comprises: separately carrying out internal code encoding on n first data streams, so as to obtain n second data streams, the n second data streams comprising n internal code codewords which are respectively from the n second data streams, the n internal code codewords comprising n / m codeword sets, each codeword set comprising m internal code codewords, and each internal code codeword comprising N bits; separately carrying out bit interleaving on the n / m codeword sets, so as to obtain n / m target bit sets; and separately carrying out mapping on m×N bits in each target bit set to obtain m×N / L modulation symbols, so as to obtain n×N / L modulation symbols in total, every L bits being mapped into a modulation symbol, the L bits of each modulation symbol being respectively from L internal code codewords, and if the L bits of each modulation symbol are all from information bits of the internal code codewords, any two bits in the modulation symbol being from two different positions of two different internal code codewords.

Description

Data processing method and data processing device

[0001] This application claims priority to the Chinese patent application filed with the China Patent Office on June 24, 2022, with application number 202210727137.1 and invention name “A data processing method and data processing device”, and the Chinese patent application filed with the China Patent Office on July 22, 2022, with application number 202210867882.6 and invention name “A data processing method and data processing device”, and the Chinese patent application filed with the China Patent Office on April 4, 2023, with application number 202310382561.1 and invention name “A data processing method and data processing device”, all of which are incorporated into this application by application. Technical Field

[0002] The present application relates to the field of communications, and in particular to a data processing method and a data processing device. Background Art

[0003] Driven by 5G, cloud computing, big data, and artificial intelligence, high-speed optical transmission networks are developing towards large capacity, packetization, and intelligence. Forward error correction (FEC) coding is used to correct errors in transmitted data, resolving transmission errors and recovering the original data from the received data.

[0004] A cascaded FEC transmission scheme is currently being proposed. The transmitting device and the transmitting processing module are connected via an attachment unit interface (AUI). The transmitting device performs a first FEC encoding on the data to be transmitted and sends the data after the first FEC encoding to the transmitting processing module. The transmitting processing module then performs a second FEC encoding on the data after the first FEC encoding, modulates and maps the bit sequence after the second FEC encoding to generate a corresponding modulation symbol sequence, and finally transmits the generated symbol sequence to the receiving end via the optical transmission network. The receiving end demodulates and decodes the received modulation symbol sequence to obtain the information sent by the transmitting end.

[0005] Typically, concatenated code interleaving is added before the second FEC code to shuffle the data after the first FEC code to enhance the error correction performance of the overall FEC scheme. Furthermore, during actual transmission of the modulation symbol sequence, bursts can affect the transmission link, causing errors in several consecutive symbols within the modulation symbol sequence. The receiver then receives a burst-affected modulation symbol sequence. Due to the high number of consecutive errors, accurate error correction using FEC codes is difficult, resulting in a high bit error rate (BER) in the transmitted information.

[0006] Summary of the Invention

[0007] The embodiments of the present application provide a data processing method and a data processing device, which enable the cascaded FEC transmission scheme to have a strong burst resistance capability and be applicable to a wide range of transmission scenarios, especially to actual coherent transmission scenarios where the channel has colored noise.

[0008] In a first aspect, the present application provides a data processing method. The method comprises the following steps. First, inner code encoding is performed on each of n first data streams to obtain n second data streams. Each of the n first data streams is outer code encoded, and both the inner code encoding and the outer code encoding are FEC encoding. The n second data streams include at least n inner codewords, each of which comes from the n second data streams. The n inner codewords include n / m codeword sets, each of which includes m inner codewords. Each inner codeword includes N bits, and the N bits include K information bits and P check bits, where n is an integer greater than 1 and is divisible by m. Next, bit interleaving is performed on each of the n / m codeword sets to obtain n / m target bit sets. Each target bit set includes m×N bits. Furthermore, the m×N bits in each target bit set are mapped to obtain m×N / L modulation symbols, resulting in a total of n×N / L modulation symbols. Each L bit is mapped to a modulation symbol, m is divisible by L, and the L bits mapped to a modulation symbol come from L inner codewords. If the L bits mapped to a modulation symbol all come from information bits of an inner codeword, then any two bits among the L bits mapped to a modulation symbol come from two different positions of two different inner codewords.

[0009] In this implementation, a cascaded FEC transmission scheme is adopted, whereby the data stream undergoes outer code encoding and inner code encoding in sequence. Based on this, the present application designs a bit interleaving and mapping method that allows both the bits in the outer codeword and the bits in the inner codeword to be discretely and evenly mapped to the modulation symbols. This makes the cascaded FEC transmission scheme highly robust against burst errors, particularly short burst errors that can be directly corrected by inner code decoding. This makes it applicable to a wide range of transmission scenarios, particularly in practical coherent transmission scenarios where the channel contains colored noise.

[0010] In some possible implementations, N is divisible by L, the N bits of each inner codeword are respectively mapped to N modulation symbols, the N bits of the inner codeword include L first bit subsets, bits in the same first bit subset are respectively mapped to the same bit positions of different modulation symbols, and bits in different first bit subsets are respectively mapped to different bit positions of different modulation symbols. For example, a modulation symbol includes bit position b0, bit position b1, ..., bit position b L-1, the N bits of the inner code word are mapped to bit b0, bit b1, ..., bit b L-1 The number of bits is N / L. It should be understood that the probability of errors occurring in the above L bits during transmission is not necessarily equal. Mapping the bits of an inner codeword more evenly to modulation symbols can improve the burst resistance of the cascaded FEC scheme in actual transmission.

[0011] In some possible implementations, bit interleaving a codeword set to obtain a target bit set includes: performing a first position transformation on the K information bits of each inner codeword in the codeword set to obtain a first bit set. Performing a second position transformation on the bits located at the same position in the first bit set to obtain the target bit set. Taking the codeword set as a bit matrix as an example, the first position transformation can be understood as performing a position transformation on the bits located in each row, and the second position transformation can be understood as performing a position transformation on the bits located in each column. This implementation provides a specific implementation method for bit interleaving, which makes the present solution have strong anti-burst capabilities.

[0012] In some possible implementations, performing a first position transformation on the K information bits of each inner codeword in the codeword set includes performing a left cyclic shift or a right cyclic shift on the K information bits of each inner codeword in the codeword set. This implementation provides a specific implementation of the first position transformation, which has good practical effects.

[0013] In some possible implementations, the codeword set and the first bit set are both represented as bit matrices, and the target bit set is represented as a bit matrix or a one-dimensional array. The bit matrix includes m rows and N columns of bits, and the one-dimensional array includes m×N bits. The bits at the same position in the first bit set are a column of m bits in the bit matrix corresponding to the first bit set.

[0014] In some possible implementations, the first position change satisfies a first condition, where the first condition includes:

[0015] H1[i][j] represents the bit in the i-th row and j-th column of the bit matrix before the first position transformation, H2[i][j] represents the bit in the i-th row and j-th column of the bit matrix after the first position transformation, Y%Z represents the remainder after the integer Y is divided by the integer Z, Δ is a non-zero integer greater than -K and less than K, 0≤i <m。

[0016] In some possible implementations, each identical position in the first bit set includes m / L second bit subsets, each second bit subset including L bits. Performing a second position transformation on the bits at the identical position in the first bit set includes performing an upward cyclic shift or a downward cyclic shift on each identical position of the m / L second bit subsets in the first bit set. This implementation provides a specific implementation method for the second position transformation, which has good practical effects.

[0017] In some possible implementations, the second position change satisfies a second condition, which includes:

[0018] H2[i][j] represents the bit in the i-th row and j-th column of the bit matrix before the second position transformation, and H3[i][j] represents the bit in the i-th row and j-th column of the bit matrix after the second position transformation. Indicates rounding down, Y%Z indicates the remainder after dividing integer Y by integer Z, θ is a non-zero integer greater than -L and less than L, 0≤i <m,0≤j<N。

[0019] In some possible implementations, the second position change satisfies a third condition, which includes:

[0020] H2[i][j] represents the bit in the i-th row and j-th column of the bit matrix before the second position transformation, and H3[i][j] represents the bit in the i-th row and j-th column of the bit matrix after the second position transformation. Indicates rounding down, Y%Z indicates the remainder after dividing integer Y by integer Z, Y^Z indicates the integer corresponding to the bit sequence obtained by performing an XOR operation on the bit sequence corresponding to integer Y and the bit sequence corresponding to integer Z, 0≤i <m,0≤j<N。

[0021] In some possible implementations, the second position transformation satisfies a fourth condition, which includes: H3[i][j]=H2[i^(j%L)][j]

[0022] H2[i][j] represents the bit in the i-th row and j-th column of the bit matrix before the second position transformation, H3[i][j] represents the bit in the i-th row and j-th column of the bit matrix after the second position transformation, Y%Z represents the remainder after the integer Y is divided by the integer Z, Y^Z represents the integer corresponding to the bit sequence obtained by performing an XOR operation on the bit sequence corresponding to the integer Y and the bit sequence corresponding to the integer Z, 0≤i <m,0≤j<N。

[0023] In some possible embodiments, the codeword set is represented as a bit matrix, and the target bit set is represented as a bit matrix or a one-dimensional array. The bit matrix includes m rows and N columns of bits, and the one-dimensional array includes m×N bits.

[0024] In some possible embodiments, the target bit set is a bit matrix, and the bit interleaving satisfies the fifth condition, which includes:

[0025] H1[i][j] represents the bit in the i-th row and j-th column of the bit matrix before bit interleaving, H3[i][j] represents the bit in the i-th row and j-th column of the bit matrix after bit interleaving, Y%Z represents the remainder of integer Y divided by integer Z, Δ is a non-zero integer greater than -K and less than K, represents rounding down, θ is a non-zero integer greater than -L and less than L, 0≤i<m.

[0026] In some possible embodiments, the target bit set is a one-dimensional array, and the bit interleaving satisfies the sixth condition, which includes:

[0027] H1[i][j] represents the bit in the i-th row and j-th column of the bit matrix before bit interleaving, A[t] represents the t-th bit in the one-dimensional array after bit interleaving, 0≤t<m×N, Y%Z represents the remainder of integer Y divided by integer Z, Δ is a non-zero integer greater than -K and less than K, represents rounding down, θ is a non-zero integer greater than -L and less than L, 0≤i<m.

[0028] In some possible embodiments, the target bit set is a bit matrix, and the bit interleaving satisfies the seventh condition, which includes:

[0029] H1[i][j] represents the bit in the i-th row and j-th column of the bit matrix before bit interleaving, H3[i][j] represents the bit in the i-th row and j-th column of the bit matrix after bit interleaving, Y%Z represents the remainder of integer Y divided by integer Z, Δ is a non-zero integer greater than -K and less than K, Y^Z represents the integer corresponding to the bit sequence obtained by performing an exclusive OR operation on the bit sequence corresponding to integer Y and the bit sequence corresponding to integer Z, 0≤i<m.

[0030] In some possible embodiments, the target bit set is a one-dimensional array, and the bit interleaving satisfies the eighth condition, which includes:

[0031] H1[i][j] represents the bit at the i-th row and j-th column in the bit matrix before bit interleaving. A[t] represents the t-th bit in the one-dimensional array after bit interleaving, where 0 ≤ t < m × N. Y % Z represents the remainder of integer Y divided by integer Z. Δ is a non-zero integer greater than -K and less than K. Y ^ Z represents the integer corresponding to the bit sequence obtained by performing an exclusive OR operation on the bit sequence corresponding to integer Y and the bit sequence corresponding to integer Z, where 0 ≤ i < m.

[0032] In some possible implementation manners, mapping the m × N bits in each target bit set to obtain m × N / L modulation symbols includes: mapping every consecutive L bits at the same position in each target bit set to one modulation symbol, so as to obtain m × N / L modulation symbols.

[0033] In some possible implementation manners, the modulation symbol stream includes the m × N / L modulation symbols obtained by mapping. The m / L modulation symbols obtained by mapping the m bits at the same position in each target bit set are consecutive in the modulation symbol stream. When the target bit set is represented as a bit matrix, the m bits at the same position in the target bit set are m bits in one column of the bit matrix; when the target bit set is represented as a one-dimensional array, the m bits at the same position in the target bit set are consecutive m bits in the one-dimensional array.

[0034] In some possible implementation manners, the modulation symbol stream includes the m × N / L modulation symbols obtained by mapping. Each target bit set is represented as a bit matrix including m rows and N columns of bits. The m bits in one column of each target bit set are mapped to obtain m / L first modulation symbols, and every consecutive T first modulation symbols among the m / L first modulation symbols are consecutive in the modulation symbol stream. The m bits in another column of each target bit set are mapped to obtain m / L second modulation symbols, and every consecutive T second modulation symbols among the m / L second modulation symbols are consecutive in the modulation symbol stream. One column is adjacent to the other column. The consecutive T first modulation symbols among the m / L first modulation symbols and the consecutive T second modulation symbols among the m / L second modulation symbols are consecutive in the modulation symbol stream, and m / L is divisible by T.

[0035] In some possible implementation manners, all n first data streams undergo identification locking and channel deviation correction processing. When the W × L bits in consecutive W modulation symbols are all information bits of an inner code codeword, the W × L bits come from more than 2 outer code codewords that have undergone outer code encoding, where W ≥

[0036] In some possible implementations, each modulation symbol is a dual-polarization quadrature amplitude modulation (DP-16QAM) modulation symbol, each modulation symbol includes 8 bits. Alternatively, each modulation symbol is a pulse amplitude modulation (PAM4) modulation symbol, each modulation symbol includes 2 bits.

[0037] In a second aspect, the present application provides a data processing method. The method includes the following steps. First, inner code encoding is performed on n first data streams to obtain n second data streams. The n first data streams are all outer code encoded, and both the inner code encoding and the outer code encoding are FEC encoding. The n second data streams include at least n inner code codewords, and the n inner code codewords come from the n second data streams respectively. The n inner code codewords include n / m codeword sets, and each codeword set includes m inner codewords. Each inner code codeword includes N bits, and the N bits include K information bits and P check bits, where n is an integer greater than 1 and n is divisible by m. Thereafter, bit interleaving is performed on the n / m codeword sets to obtain n / m target bit sets. Each target bit set includes m×N bits, and bit interleaving includes position shifting of the K information bits of each inner codeword in the codeword set. Then, the m×N bits in each target bit set are mapped to obtain m×N / L modulation symbols, so as to obtain a total of n×N / L modulation symbols. Among them, each L bit is mapped to a modulation symbol, and m is divisible by L. The L bits mapped to a modulation symbol come from L r Inner code words, L r Each inner code word has L c bits are mapped to modulation symbols. The 2L bits mapped to 2 consecutive modulation symbols come from 2L r inner code words, L = L r ×L c ,L c >1.

[0038] In some possible implementations, performing position transformation on the K information bits of each inner codeword in the codeword set includes performing a left cyclic shift or a right cyclic shift on the K information bits of each inner codeword in the codeword set.

[0039] In some possible implementations, the codeword set is represented as a bit matrix, and the target bit set is represented as a bit matrix or a one-dimensional array. The bit matrix includes m rows and N columns of bits, and the one-dimensional array includes m×N bits.

[0040] In some possible implementations, the position change satisfies a target condition, which includes:

[0041] H1[i][j] represents the bit in the i-th row and j-th column of the bit matrix before the position transformation, H2[i][j] represents the bit in the i-th row and j-th column of the bit matrix after the position transformation, Y%Z represents the remainder after the integer Y is divided by the integer Z, Δ is a non-zero integer greater than -K and less than K, 0≤i <m。

[0042] In some possible implementations, each target bit set includes m rows and N columns of bits, and each L in the target bit set r Line L c A total of L bits in a column are mapped to one modulation symbol.

[0043] In some possible implementations, the modulation symbol stream includes m×N / L modulation symbols obtained by mapping, and each L in the target bit set c m / L obtained by column bit mapping r The modulation symbols are continuous in the modulation symbol stream, and the m×N / L modulation symbols obtained by mapping every N columns of bits in the target bit set are continuous in the modulation symbol stream.

[0044] In some possible implementations, the modulation symbol stream includes m×N / L modulation symbols obtained by mapping. c The bit mapping of the column gets m / L r The first modulation symbol, m / L r Each of the T consecutive first modulation symbols in the first modulation symbols is continuous in the modulation symbol stream. c The bit mapping of the column gets m / L r The second modulation symbol, m / L r Every consecutive T second modulation symbols in the modulation symbol stream are consecutive. c Column and other L c Adjacent rows, m / L r The T consecutive first modulation symbols in the first modulation symbols are equal to m / L r T second modulation symbols are continuous in the modulation symbol stream, m / L r Divisible by T.

[0045] In some possible implementations, each modulation symbol is a dual-polarization quadrature amplitude modulation (DP-16QAM) modulation symbol, each modulation symbol includes 8 bits. Alternatively, each modulation symbol is a pulse amplitude modulation (PAM4) modulation symbol, each modulation symbol includes 2 bits.

[0046] In a third aspect, the present application provides a data processing device. The data processing device includes: an encoding module, a bit interleaving module, and a bit mapping module. The encoding module is used to: perform inner code encoding on n first data streams respectively to obtain n second data streams. Among them, the n first data streams are all outer code encoded, and both the inner code encoding and the outer code encoding are forward error correction FEC encoding. The n second data streams include at least n inner code codewords, and the n inner code codewords come from the n second data streams respectively. The n inner code codewords include n / m codeword sets, and each codeword set includes m inner codewords. Each inner code codeword includes N bits, and the N bits include K information bits and P check bits, where n is an integer greater than 1 and n is divisible by m. The bit interleaving module is used to interleave n / m codeword sets to obtain n / m target bit sets, each target bit set including m×N bits. The bit mapping module is used to map the m×N bits in each target bit set to obtain m×N / L modulation symbols, thereby obtaining a total of n×N / L modulation symbols. Each L bit is mapped to a modulation symbol, m is divisible by L, and the L bits mapped to a modulation symbol come from L inner codewords. If the L bits mapped to a modulation symbol all come from information bits of an inner codeword, then any two bits of the L bits mapped to a modulation symbol come from two different positions of two different inner codewords.

[0047] In some possible implementations, N is divisible by L, the N bits of each inner code word are respectively mapped to N modulation symbols, the N bits of the inner code word include L first bit subsets, the bits in the same first bit subset are respectively mapped to the same bit positions of different modulation symbols, and the bits in different first bit subsets are respectively mapped to different bit positions of different modulation symbols.

[0048] In some possible implementations, the bit mapping module is specifically configured to: perform a first position transformation on K information bits of each inner codeword in the codeword set to obtain a first bit set, and perform a second position transformation on bits at the same position in the first bit set to obtain a target bit set.

[0049] In some possible implementations, the bit mapping module is specifically configured to perform a left cyclic shift or a right cyclic shift on the K information bits of each inner codeword in the codeword set.

[0050] In some possible implementations, the codeword set and the first bit set are both represented as bit matrices, and the target bit set is represented as a bit matrix or a one-dimensional array. The bit matrix includes m rows and N columns of bits, and the one-dimensional array includes m×N bits. The bits at the same position in the first bit set are a column of m bits in the bit matrix corresponding to the first bit set.

[0051] In some possible implementations, the first position change satisfies a first condition, where the first condition includes:

[0052] H1[i][j] represents the bit in the i-th row and j-th column of the bit matrix before the first position transformation, H2[i][j] represents the bit in the i-th row and j-th column of the bit matrix after the first position transformation, Y%Z represents the remainder after the integer Y is divided by the integer Z, Δ is a non-zero integer greater than -K and less than K, 0≤i <m。

[0053] In some possible implementations, each identical position in the first bit set includes m / L second bit subsets, and each second bit subset includes L bits. The bit mapping module is specifically configured to perform an upward cyclic shift or a downward cyclic shift on each identical position of the m / L second bit subsets in the first bit set.

[0054] In some possible implementations, the second position change satisfies a second condition, which includes:

[0055] H2[i][j] represents the bit in the i-th row and j-th column of the bit matrix before the second position transformation, and H3[i][j] represents the bit in the i-th row and j-th column of the bit matrix after the second position transformation. Indicates rounding down, Y%Z indicates the remainder after dividing integer Y by integer Z, θ is a non-zero integer greater than -L and less than L, 0≤i <m,0≤j<N。

[0056] In some possible implementations, the second position change satisfies a third condition, which includes:

[0057] H2[i][j] represents the bit in the i-th row and j-th column of the bit matrix before the second position transformation, and H3[i][j] represents the bit in the i-th row and j-th column of the bit matrix after the second position transformation. Indicates rounding down, Y%Z indicates the remainder after dividing integer Y by integer Z, Y^Z indicates the integer corresponding to the bit sequence obtained by performing an XOR operation on the bit sequence corresponding to integer Y and the bit sequence corresponding to integer Z, 0≤i <m,0≤j<N。

[0058] In some possible implementations, the second position transformation satisfies a fourth condition, which includes: H3[i][j]=H2[i^(j%L)][j]

[0059] H2[i][j] represents the bit at the i-th row and j-th column in the bit matrix before the second position transformation, H3[i][j] represents the bit at the i-th row and j-th column in the bit matrix after the second position transformation, Y % Z represents the remainder of integer Y divided by integer Z, Y^Z represents the integer corresponding to the bit sequence obtained by performing an exclusive OR operation on the bit sequences corresponding to integer Y and integer Z, 0 ≤ i < m, 0 ≤ j < N.

[0060] In some possible implementation manners, the codeword set is represented as a bit matrix, the target bit set is represented as a bit matrix or a one-dimensional array, the bit matrix includes m rows and N columns of bits, and the one-dimensional array includes m×N bits.

[0061] In some possible implementation manners, the target bit set is a bit matrix, and the bit interleaving satisfies the fifth condition, and the fifth condition includes:

[0062] H1[i][j] represents the bit at the i-th row and j-th column in the bit matrix before the bit interleaving, H3[i][j] represents the bit at the i-th row and j-th column in the bit matrix after the bit interleaving, Y % Z represents the remainder of integer Y divided by integer Z, Δ is a non-zero integer greater than -K and less than K, represents rounding down, θ is a non-zero integer greater than -L and less than L, 0 ≤ i < m.

[0063] In some possible implementation manners, the target bit set is a one-dimensional array, and the bit interleaving satisfies the sixth condition, and the sixth condition includes:

[0064] H1[i][j] represents the bit at the i-th row and j-th column in the bit matrix before the bit interleaving, A[t] represents the t-th bit in the one-dimensional array after the bit interleaving, 0 ≤ t < m×N, Y % Z represents the remainder of integer Y divided by integer Z, Δ is a non-zero integer greater than -K and less than K, represents rounding down, θ is a non-zero integer greater than -L and less than L, 0 ≤ i < m.

[0065] In some possible implementation manners, the target bit set is a bit matrix, and the bit interleaving satisfies the seventh condition, and the seventh condition includes:

[0066] H1[i][j] represents the bit at the i-th row and j-th column in the bit matrix before bit interleaving, H3[i][j] represents the bit at the i-th row and j-th column in the bit matrix after bit interleaving, Y % Z represents the remainder of integer Y divided by integer Z, Δ is a non-zero integer greater than -K and less than K, Y^Z represents the integer corresponding to the bit sequence obtained by performing an exclusive OR operation on the bit sequence corresponding to integer Y and the bit sequence corresponding to integer Z, and 0 ≤ i < m.

[0067] In some possible implementation manners, the target bit set is a one-dimensional array, and the bit interleaving satisfies the eighth condition, where the eighth condition includes:

[0068] H1[i][j] represents the bit at the i-th row and j-th column in the bit matrix before bit interleaving, A[t] represents the t-th bit in the one-dimensional array after bit interleaving, 0 ≤ t < m × N, Y % Z represents the remainder of integer Y divided by integer Z, Δ is a non-zero integer greater than -K and less than K, Y^Z represents the integer corresponding to the bit sequence obtained by performing an exclusive OR operation on the bit sequence corresponding to integer Y and the bit sequence corresponding to integer Z, and 0 ≤ i < m.

[0069] In some possible implementation manners, the bit mapping module is specifically configured to: map every consecutive L bits at the same position in each target bit set into a modulation symbol, so as to obtain m × N / L modulation symbols.

[0070] In some possible implementation manners, the modulation symbol stream includes the m × N / L modulation symbols obtained by mapping. The m / L modulation symbols obtained by mapping the m bits at the same position in each target bit set are consecutive in the modulation symbol stream. When the target bit set is represented as a bit matrix, the m bits at the same position in the target bit set are m bits in a column of the bit matrix. When the target bit set is represented as a one-dimensional array, the m bits at the same position in the target bit set are m consecutive bits in the one-dimensional array.

[0071] In some possible implementations, the modulation symbol stream includes m×N / L modulation symbols obtained by mapping, and each target bit set is represented as a bit matrix including m rows and N columns of bits. The m bits located in one column of each target bit set are mapped to obtain m / L first modulation symbols, and each consecutive T first modulation symbols among the m / L first modulation symbols are continuous in the modulation symbol stream. The m bits located in another column of each target bit set are mapped to obtain m / L second modulation symbols, and each consecutive T second modulation symbols among the m / L second modulation symbols are continuous in the modulation symbol stream. One column is adjacent to another column, and T consecutive first modulation symbols among the m / L first modulation symbols and T consecutive second modulation symbols among the m / L second modulation symbols are continuous in the modulation symbol stream, and m / L is divisible by T.

[0072] In some possible implementations, the n first data streams are all processed by identification locking and channel deskew. When W×L bits in W consecutive modulation symbols are all information bits of an inner code word, the W×L bits come from more than two outer code code words encoded by an outer code, where W≥2.

[0073] In some possible implementations, each modulation symbol is a DP-16QAM modulation symbol, each modulation symbol includes 8 bits, or each modulation symbol is a PAM4 modulation symbol, each modulation symbol includes 2 bits.

[0074] In a fourth aspect, the present application provides a data processing device. The data processing device includes: an encoding module, a bit interleaving module, and a bit mapping module. The encoding module is configured to perform inner code encoding on each of n first data streams to obtain n second data streams. Each of the n first data streams is outer code encoded, and both the inner and outer code encodings are forward error correction (FEC) encodings. The n second data streams include at least n inner codewords, each of which is derived from the n second data streams. The n inner codewords include n / m codeword sets, each of which includes m inner codewords. Each inner codeword includes N bits, each of which includes K information bits and P check bits, where n is an integer greater than 1 and is divisible by m. The bit interleaving module is configured to perform bit interleaving on each of the n / m codeword sets to obtain n / m target bit sets. Each target bit set includes m×N bits, and bit interleaving includes permuting the positions of the K information bits of each inner codeword in the codeword set. The bit mapping module is used to map the m×N bits in each target bit set to obtain m×N / L modulation symbols, so as to obtain a total of n×N / L modulation symbols. Among them, each L bit is mapped to a modulation symbol, m is divisible by L, and the L bits mapped to a modulation symbol come from L r Inner code words, L r Each inner code word has Lc bits are mapped to modulation symbols, and the 2L bits mapped to 2 consecutive modulation symbols come from 2L r inner code words, L = L r ×L c ,L c >1.

[0075] In some possible implementations, the bit interleaving module is specifically configured to perform a left cyclic shift or a right cyclic shift on the K information bits of each inner codeword in the codeword set.

[0076] In some possible implementations, the codeword set is represented as a bit matrix, and the target bit set is represented as a bit matrix or a one-dimensional array. The bit matrix includes m rows and N columns of bits, and the one-dimensional array includes m×N bits.

[0077] In some possible implementations, the position change satisfies a target condition, which includes:

[0078] H1[i][j] represents the bit in the i-th row and j-th column of the bit matrix before the position transformation, H2[i][j] represents the bit in the i-th row and j-th column of the bit matrix after the position transformation, Y%Z represents the remainder after the integer Y is divided by the integer Z, Δ is a non-zero integer greater than -K and less than K, 0≤i <m。

[0079] In some possible implementations, each target bit set includes m rows and N columns of bits, and each L in the target bit set r Line L c A total of L bits in a column are mapped to one modulation symbol.

[0080] In some possible implementations, the modulation symbol stream includes m×N / L modulation symbols obtained by mapping, and each L in the target bit set c m / L obtained by column bit mapping r The modulation symbols are continuous in the modulation symbol stream, and the m×N / L modulation symbols obtained by mapping every N columns of bits in the target bit set are continuous in the modulation symbol stream.

[0081] In some possible implementations, the modulation symbol stream includes m×N / L modulation symbols obtained by mapping. c The bit mapping of the column gets m / L r The first modulation symbol, m / L r Each of the T consecutive first modulation symbols in the first modulation symbols is continuous in the modulation symbol stream. c The bit mapping of the column gets m / L r The second modulation symbol, m / Lr Every consecutive T second modulation symbols in the modulation symbol stream are consecutive. c Column and other L c Adjacent rows, m / L r The T consecutive first modulation symbols in the first modulation symbols are equal to m / L r T second modulation symbols are continuous in the modulation symbol stream, m / L r Divisible by T.

[0082] In some possible implementations, each modulation symbol is a DP-16QAM modulation symbol, each modulation symbol includes 8 bits, or each modulation symbol is a PAM4 modulation symbol, each modulation symbol includes 2 bits.

[0083] In a fifth aspect, the present application provides a data processing method. The method comprises the following steps. First, interleaving and encoding each n1 first data streams in the n0 first data streams is performed to obtain a second data stream, so as to obtain a total of n2 second data streams. n2 = n0 / n1, n0 is an integer greater than 1, and n1 is an integer greater than 0. Afterwards, each 2 bits in the n2 second data streams are mapped to a PAM4 symbol to obtain a total of n2 PAM4 symbol data streams. Specifically, the interleaving and encoding process comprises the following steps: obtaining a0 first bit sets from each first data stream of the n1 first data streams to obtain a total of m = n1 × a0 first bit sets, wherein the n1 first data streams are all outer code encoded, each first bit set includes K bits, and n1, a0, and K are all integers greater than 1. Inner coding is performed on each of the m first bit sets to obtain m inner codewords. Both the inner coding and outer coding are forward error correction (FEC) codes. Each inner codeword includes one first bit set involved in the inner coding and one parity bit set, totaling N bits, where N = K + P. Each parity bit set includes P bits, where P is an integer greater than or equal to 1. Cyclic shift is performed on each of the m inner codewords to obtain m third bit sets. Each third bit set includes one second bit set obtained by cyclic shifting the first bit set and one parity bit set. Two bits are obtained from each third bit set by polling to obtain a fourth bit set. The fourth bit set includes m × N bits. In the fourth bit set, a total of m × K bits from the m second bit sets are continuous, and a total of m × P bits from the m parity bit sets are continuous. It should be understood that each second data stream includes multiple fourth bit sets, and each fourth bit set is mapped to obtain a total of m×N / 2 PAM4 symbols, wherein the m×2 bits mapped to m consecutive PAM4 symbols in the m×N / 2 PAM4 symbols come from m inner code words.

[0084] In some possible implementations, each first data stream is outer code encoded, and 20 consecutive bits in the first data stream are interleaved and mapped to obtain at least 10 PAM4 symbols, the consecutive 20 bits come from two outer code symbols of an outer code codeword, and any two PAM4 symbols among the at least 10 PAM4 symbols are separated by at least 2 PAM4 symbols in the PAM4 symbol data stream.

[0085] In some possible implementations, the number of bits cyclically shifted in any two of the m first bit sets is different.

[0086] In some possible implementations, the m inner codewords and the m third bit sets are both represented as a bit matrix, and the bit matrix includes m rows and N columns of bits.

[0087] In some possible implementations, the second bit set is cyclically shifted leftward from the first bit set. bits are obtained, and the left cyclic shift satisfies the first condition, which includes:

[0088] Among them, M c [i][j] represents the bit in the i-th row and j-th column of the bit matrix corresponding to the m inner codewords before cyclic shift to the left, M3[i][j] represents the bit in the i-th row and j-th column of the bit matrix corresponding to the m third bit sets after cyclic shift to the left, Y%Z represents the remainder after the integer Y is divided by the integer Z, 0≤i <m,

[0089] In some possible implementations, the second bit set is cyclically shifted right by δ from the first bit set. i bits are obtained, and the right cyclic shift satisfies the second condition, which includes:

[0090] Among them, M c [i][j] represents the bit in the i-th row and j-th column of the bit matrix corresponding to the m inner codewords before the right cyclic shift, M3[i][j] represents the bit in the i-th row and j-th column of the bit matrix corresponding to the m third bit sets after the right cyclic shift, Y%Z represents the remainder after the integer Y is divided by the integer Z, 0≤i <m,0≤δ i <K。

[0091] In some possible implementations, the m third bit sets and the fourth bit set satisfy a third condition, where the third condition includes:

[0092] Wherein, M3[i][j] represents the bit in the i-th row and j-th column of the bit matrix corresponding to the m third bit sets, Indicates the fourth bit set bits, 0≤i <m,0≤j<N, Indicates a floor operation.

[0093] In some possible implementations, K=120, m=8, and the i-th second bit set is cyclically shifted leftward from the i-th first bit set. bits are obtained, 0≤i<8, The value of satisfies the first value item Any item in the first value item include:

[0094] {0,30,60,90,110,20,50,80};

[0095] {0,30,90,60,110,20,80,50};

[0096] {0,60,30,90,110,50,20,80};

[0097] {0,60,90,30,110,50,80,20};

[0098] {0,90,30,60,110,80,20,50};

[0099] {0,90,60,30,110,80,50,20}.

[0100] In some possible implementations, K=120, m=8, and the i-th second bit set is cyclically shifted right by δ from the i-th first bit set. i bits are obtained, 0≤i<8, δ i The value of satisfies any one of the second value items {δ0,δ1,δ2,δ3,δ4,δ5,δ6,δ7}, and the second value items {δ0,δ1,δ2,δ3,δ4,δ5,δ6,δ7} include:

[0101] {0,30,60,90,10,40,70,100};

[0102] {0,30,90,60,10,40,100,70};

[0103] {0,60,30,90,10,40,40,100};

[0104] {0,60,90,30,10,70,100,40};

[0105] {0,90,30,60,10,100,40,70};

[0106] {0,90,60,30,10,100,70,40}.

[0107] In a sixth aspect, the present application provides a data processing method. The method comprises the following steps. First, interleaving and encoding each n1 first data streams in the n0 first data streams is performed to obtain a second data stream, so as to obtain a total of n2 second data streams. n2 = n0 / n1, n0 is an integer greater than 1, and n1 is an integer greater than 0. Afterwards, each 2 bits in the n2 second data streams are mapped to a PAM4 symbol to obtain a total of n2 PAM4 symbol data streams. Specifically, the interleaving and encoding process comprises the following steps: obtaining a0 first bit sets from each first data stream of the n1 first data streams to obtain a total of m = n1 × a0 first bit sets, wherein the n1 first data streams are all outer code encoded, each first bit set includes K bits, and n1, a0, and K are all integers greater than 1. Cyclic shift is performed on each of the m first bit sets to obtain m second bit sets, and inner coding is performed on each of the m first bit sets to obtain m parity bit sets, where both the inner coding and the outer coding are forward error correction (FEC) coding. Each second bit set includes K bits, and each parity bit set includes P bits, where P is an integer greater than or equal to 1. Two bits are obtained from each second bit set by polling to obtain a total of m×K consecutive bits, and two bits are obtained from each parity bit set by polling to obtain a total of m×P consecutive bits, to obtain a third bit set including m×N bits, where N=K+P. It should be understood that each second data stream includes multiple third bit sets, each third bit set contains m×K bits of the second bit set and m×P bits of the check bit set, the m×K bits from the second bit set in each third bit set are mapped to obtain a total of m×K / 2 PAM4 symbols, the m×P bits from the check bit set in each third bit set are mapped to obtain a total of m×P / 2 PAM4 symbols, and the m×2 bits mapped to m consecutive PAM4 symbols in the total m×N / 2 PAM4 symbols come from m second bit sets and / or m check bit sets.

[0108] In some possible implementations, each first data stream is outer code encoded, and 20 consecutive bits in the first data stream are interleaved and mapped to obtain at least 10 PAM4 symbols, the consecutive 20 bits come from two outer code symbols of an outer code codeword, and any two PAM4 symbols among the at least 10 PAM4 symbols are separated by at least 2 PAM4 symbols in the PAM4 symbol data stream.

[0109] In some possible implementations, the number of bits cyclically shifted in any two of the m first bit sets is different.

[0110] In some possible implementations, the m first bit sets and the m second bit sets are both represented as a bit matrix, and the bit matrix includes m rows and K columns of bits.

[0111] In some possible implementations, the second bit set is cyclically shifted leftward from the first bit set. bits are obtained, and the left cyclic shift satisfies the first condition, which includes:

[0112] Where M1[i][j] represents the bit in the i-th row and j-th column of the bit matrix corresponding to the m first bit sets before cyclic shift to the left, M2[i][j] represents the bit in the i-th row and j-th column of the bit matrix corresponding to the m second bit sets after cyclic shift to the left, Y%Z represents the remainder after the integer Y is divided by the integer Z, and 0≤j <K,0≤i<m,

[0113] In some possible implementations, the second bit set is cyclically shifted right by δ from the first bit set. i bits are obtained, and the right cyclic shift satisfies the second condition, which includes: M2[i][j]=M1[i][(j-δ i )%K]

[0114] Wherein, M1[i][j] represents the bit in the i-th row and j-th column of the bit matrix corresponding to the m first bit sets before cyclic shift to the right, M2[i][j] represents the bit in the i-th row and j-th column of the bit matrix corresponding to the m second bit sets after cyclic shift to the right, Y%Z represents the remainder after the integer Y is divided by the integer Z, 0≤j <K,0≤i<m,0≤δ i <K。

[0115] In some possible implementations, K=120, m=8, and the i-th second bit set is cyclically shifted leftward from the i-th first bit set. bits are obtained, 0≤i<8, The value of satisfies the first value item Any item in the first value item include:

[0116] {0,30,60,90,110,20,50,80};

[0117] {0,30,90,60,110,20,80,50};

[0118] {0,60,30,90,110,50,20,80};

[0119] {0,60,90,30,110,50,80,20};

[0120] {0,90,30,60,110,80,20,50};

[0121] {0,90,60,30,110,80,50,20}.

[0122] In some possible implementations, K=120, m=8, and the i-th second bit set is cyclically shifted right by δ from the i-th first bit set. i bits are obtained, 0≤i<8, δ i The value of satisfies any one of the second value items {δ0,δ1,δ2,δ3,δ4,δ5,δ6,δ7}, and the second value items {δ0,δ1,δ2,δ3,δ4,δ5,δ6,δ7} include:

[0123] {0,30,60,90,10,40,70,100};

[0124] {0,30,90,60,10,40,100,70};

[0125] {0,60,30,90,10,40,40,100};

[0126] {0,60,90,30,10,70,100,40};

[0127] {0,90,30,60,10,100,40,70};

[0128] {0,90,60,30,10,100,70,40}.

[0129] In a seventh aspect, the present application provides a data processing method. The method includes the following steps. First, interleaving and encoding each of the n1 first data streams in the n0 first data streams is performed to obtain a second data stream, resulting in a total of n2 second data streams. n2 = n0 / n1, where n0 is an integer greater than 1 and n1 is an integer greater than 0. Then, mapping each of the two bits in the n2 second data streams into a PAM4 symbol to obtain a total of n2 PAM4 symbol data streams. Specifically, the interleaving and encoding process includes the following steps: obtaining a0 first bit sets from each of the n1 first data streams to obtain a total of m = n1 × a0 first bit sets, wherein the n1 first data streams are all outer-coded, each first bit set includes K bits, and n1, a0, and K are all integers greater than 1. Cyclic shifting is performed on each of the m first bit sets to obtain m second bit sets, each second bit set includes K bits. Inner coding is performed on each of the m second bit sets to obtain m inner codewords. Both the inner coding and outer coding are forward error correction (FEC) codes. Each inner codeword includes one second bit set involved in the inner coding and one parity bit set, totaling N bits, where N = K + P. Each parity bit set includes P bits, where P is an integer greater than or equal to 1. Two bits are obtained from each inner codeword by polling to obtain a third bit set. The third bit set includes m × N bits. In the third bit set, a total of m × K bits from the m second bit sets are continuous, and a total of m × P bits from the m parity bit sets are continuous. It should be understood that each second data stream includes multiple third bit sets. Each third bit set is mapped to obtain a total of m × N / 2 PAM4 symbols. The m × 2 bits mapped to m consecutive PAM4 symbols in the m × N / 2 PAM4 symbols come from m inner codewords.

[0130] In some possible implementations, each first data stream is outer code encoded, and 20 consecutive bits in the first data stream are interleaved and mapped to obtain at least 10 PAM4 symbols, the consecutive 20 bits come from two outer code symbols of an outer code codeword, and any two PAM4 symbols among the at least 10 PAM4 symbols are separated by at least 2 PAM4 symbols in the PAM4 symbol data stream.

[0131] In some possible implementations, the number of bits cyclically shifted in any two of the m first bit sets is different.

[0132] In some possible implementations, the m first bit sets and the m second bit sets are both represented as a bit matrix, and the bit matrix includes m rows and K columns of bits.

[0133] In some possible implementations, the second bit set is cyclically shifted leftward from the first bit set. bits are obtained, and the left cyclic shift satisfies the first condition, which includes:

[0134] Wherein, M1[i][j] represents the bit in the i-th row and j-th column of the bit matrix corresponding to the m first bit sets before cyclic shift to the left, M2[i][j] represents the bit in the i-th row and j-th column of the bit matrix corresponding to the m second bit sets after cyclic shift to the left, Y%Z represents the remainder after the integer Y is divided by the integer Z, 0≤i <m,0≤j<K,

[0135] In some possible implementations, the second bit set is cyclically shifted right by δ from the first bit set. i bits are obtained, and the right cyclic shift satisfies the second condition, which includes:

[0136] M2[i][j]=M1[i][(j-δ i )%K]

[0137] Wherein, M1[i][j] represents the bit in the i-th row and j-th column of the bit matrix corresponding to the m first bit sets before cyclic shift to the right, M2[i][j] represents the bit in the i-th row and j-th column of the bit matrix corresponding to the m second bit sets after cyclic shift to the right, Y%Z represents the remainder after the integer Y is divided by the integer Z, 0≤i <m,0≤j<K,0≤δ i <K。

[0138] In some possible implementations, the m inner codewords are represented as a bit matrix including m rows and N columns, and the m inner codewords and the third bit set satisfy a third condition, where the third condition includes:

[0139] Among them, M c [i][j] represents the bit in row i and column j of the bit matrix corresponding to the m inner code words. Indicates the third bit set bits, 0≤i <m,0≤j<N, Indicates a floor operation.

[0140] In some possible implementations, K=120, m=8, and the i-th second bit set is cyclically shifted leftward from the i-th first bit set. bits are obtained, 0≤i<8, The value of satisfies the first value item Any item in the first value item include:

[0141] {0,30,60,90,110,20,50,80};

[0142] {0,30,90,60,110,20,80,50};

[0143] {0,60,30,90,110,50,20,80};

[0144] {0,60,90,30,110,50,80,20};

[0145] {0,90,30,60,110,80,20,50};

[0146] {0,90,60,30,110,80,50,20}.

[0147] In some possible implementations, K=120, m=8, and the i-th second bit set is cyclically shifted right by δ from the i-th first bit set. i bits are obtained, 0≤i<8, δ i The value of satisfies any one of the second value items {δ0,δ1,δ2,δ3,δ4,δ5,δ6,δ7}, and the second value items {δ0,δ1,δ2,δ3,δ4,δ5,δ6,δ7} include:

[0148] {0,30,60,90,10,40,70,100};

[0149] {0,30,90,60,10,40,100,70};

[0150] {0,60,30,90,10,40,40,100};

[0151] {0,60,90,30,10,70,100,40};

[0152] {0,90,30,60,10,100,40,70};

[0153] {0,90,60,30,10,100,70,40}.

[0154] In an eighth aspect, the present application provides a data processing method. The method comprises the following steps. First, interleaving and encoding each n1 first data streams in the n0 first data streams is performed to obtain a second data stream, so as to obtain a total of n2 second data streams. n2 = n0 / n1, n0 is an integer greater than 1, and n1 is an integer greater than 0. Afterwards, each 2 bits in the n2 second data streams are mapped to a PAM4 symbol to obtain a total of n2 PAM4 symbol data streams. Specifically, the interleaving and encoding process comprises the following steps: obtaining a0 first bit sets from each first data stream of the n1 first data streams to obtain a total of m = n1 × a0 first bit sets, wherein the n1 first data streams are all outer code encoded, each first bit set includes K bits, and n1, a0, and K are all integers greater than 1. Perform inner code encoding on the m first bit sets to obtain m inner code codewords. Both the inner code encoding and the outer code encoding are forward error correction FEC encoding. Each inner code codeword includes a first bit set and a check bit set participating in the inner code encoding, totaling N bits, where N=K+P. Each check bit set includes P bits, where P is an integer greater than or equal to 1. Perform interleaving on the m inner code codewords to obtain a second bit set. The second bit set includes m×N bits. bits satisfy the first or second condition, 0≤i <m,0≤j<N。

[0155] The first condition includes:

[0156] in, Indicates the first bit in the second bit set bits, represents the first inner code word bits, C i [j] represents the jth bit in the i-th inner code word.

[0157] The second condition includes:

[0158] in, Indicates the first bit in the second bit set bits, C i [(j-δ i )%K] represents the (j-δ i )% K bits, C i [j] represents the jth bit in the i-th inner code word.

[0159] It should be understood that each second data stream includes multiple second bit sets, and each second bit set is mapped to obtain a total of m×N / 2 PAM4 symbols, wherein the m×2 bits mapped to m consecutive PAM4 symbols in the m×N / 2 PAM4 symbols come from m inner code words.

[0160] In some possible implementations, K=120, m=8, The value of satisfies the first value item Any item in the first value item include:

[0161] {0,30,60,90,110,20,50,80};

[0162] {0,30,90,60,110,20,80,50};

[0163] {0,60,30,90,110,50,20,80};

[0164] {0,60,90,30,110,50,80,20};

[0165] {0,90,30,60,110,80,20,50};

[0166] {0,90,60,30,110,80,50,20};

[0167] δ i The value of satisfies any one of the second value items {δ0,δ1,δ2,δ3,δ4,δ5,δ6,δ7}, and the second value items {δ0,δ1,δ2,δ3,δ4,δ5,δ6,δ7} include:

[0168] {0,30,60,90,10,40,70,100};

[0169] {0,30,90,60,10,40,100,70};

[0170] {0,60,30,90,10,40,40,100};

[0171] {0,60,90,30,10,70,100,40};

[0172] {0,90,30,60,10,100,40,70};

[0173] {0,90,60,30,10,100,70,40}.

[0174] In a ninth aspect, the present application provides a data processing device, comprising: an interleaving coding module and a bit mapping module. The interleaving coding module is configured to perform interleaving coding on each of n1 first data streams in n0 first data streams to obtain a second data stream, thereby obtaining a total of n2 second data streams, where n2 = n0 / n1, n0 is an integer greater than 1, and n1 is an integer greater than 0. The bit mapping module is configured to map each of the two bits in the n2 second data streams into a PAM4 symbol, thereby obtaining a total of n2 PAM4 symbol data streams. The interleaving coding module is specifically configured to obtain a0 first bit sets from each of the n1 first data streams to obtain a total of m = n1 × a0 first bit sets, wherein the n1 first data streams are all outer-code encoded, each first bit set includes K bits, and n1, a0, and K are all integers greater than 1. Inner coding is performed on each of the m first bit sets to obtain m inner codewords. Both the inner coding and outer coding are forward error correction (FEC) codes. Each inner codeword includes one first bit set involved in the inner coding and one parity bit set, totaling N bits, where N = K + P. Each parity bit set includes P bits, where P is an integer greater than or equal to 1. Cyclic shift is performed on each of the m inner codewords to obtain m third bit sets. Each third bit set includes one second bit set obtained by cyclic shifting the first bit set and one parity bit set. Two bits are obtained from each third bit set by polling to obtain a fourth bit set. The fourth bit set includes m × N bits. In the fourth bit set, a total of m × K bits from the m second bit sets are continuous, and a total of m × P bits from the m parity bit sets are continuous. It should be understood that each second data stream includes multiple fourth bit sets, and each fourth bit set is mapped to obtain a total of m×N / 2 PAM4 symbols, wherein the m×2 bits mapped to m consecutive PAM4 symbols in the m×N / 2 PAM4 symbols come from m inner code words.

[0175] In some possible implementations, each first data stream is outer code encoded, and 20 consecutive bits in the first data stream are interleaved and mapped to obtain at least 10 PAM4 symbols, the consecutive 20 bits come from two outer code symbols of an outer code codeword, and any two PAM4 symbols among the at least 10 PAM4 symbols are separated by at least 2 PAM4 symbols in the PAM4 symbol data stream.

[0176] In some possible implementations, the number of bits cyclically shifted in any two of the m first bit sets is different.

[0177] In some possible implementations, the m inner codewords and the m third bit sets are both represented as a bit matrix, and the bit matrix includes m rows and N columns of bits.

[0178] In some possible implementations, the second bit set is cyclically shifted leftward from the first bit set. bits are obtained, and the left cyclic shift satisfies the first condition, which includes:

[0179] Among them, M c [i][j] represents the bit in the i-th row and j-th column of the bit matrix corresponding to the m inner codewords before cyclic shift to the left, M3[i][j] represents the bit in the i-th row and j-th column of the bit matrix corresponding to the m third bit sets after cyclic shift to the left, Y%Z represents the remainder after the integer Y is divided by the integer Z, 0≤i <m,

[0180] In some possible implementations, the second bit set is cyclically shifted right by δ from the first bit set. i bits are obtained, and the right cyclic shift satisfies the second condition, which includes:

[0181] Among them, M c [i][j] represents the bit in the i-th row and j-th column of the bit matrix corresponding to the m inner codewords before the right cyclic shift, M3[i][j] represents the bit in the i-th row and j-th column of the bit matrix corresponding to the m third bit sets after the right cyclic shift, Y%Z represents the remainder after the integer Y is divided by the integer Z, 0≤i <m,0≤δ i <K。

[0182] In some possible implementations, the m third bit sets and the fourth bit set satisfy a third condition, where the third condition includes:

[0183] Wherein, M3[i][j] represents the bit in the i-th row and j-th column of the bit matrix corresponding to the m third bit sets, Indicates the fourth bit set bits, 0≤i <m,0≤j<N, Indicates a floor operation.

[0184] In some possible implementations, K=120, m=8, and the i-th second bit set is cyclically shifted leftward from the i-th first bit set. bits are obtained, 0≤i<8, The value of satisfies the first value item Any item in the first value item include:

[0185] {0,30,60,90,110,20,50,80};

[0186] {0,30,90,60,110,20,80,50};

[0187] {0,60,30,90,110,50,20,80};

[0188] {0,60,90,30,110,50,80,20};

[0189] {0,90,30,60,110,80,20,50};

[0190] {0,90,60,30,110,80,50,20}.

[0191] In some possible implementations, K=120, m=8, and the i-th second bit set is cyclically shifted right by δ from the i-th first bit set. i bits are obtained, 0≤i<8, δ i The value of satisfies any one of the second value items {δ0,δ1,δ2,δ3,δ4,δ5,δ6,δ7}, and the second value items {δ0,δ1,δ2,δ3,δ4,δ5,δ6,δ7} include:

[0192] {0,30,60,90,10,40,70,100};

[0193] {0,30,90,60,10,40,100,70};

[0194] {0,60,30,90,10,40,40,100};

[0195] {0,60,90,30,10,70,100,40};

[0196] {0,90,30,60,10,100,40,70};

[0197] {0,90,60,30,10,100,70,40}.

[0198] In a tenth aspect, the present application provides a data processing device, comprising: an interleaving coding module and a bit mapping module. The interleaving coding module is configured to interleave and code each n1 first data streams in n0 first data streams to obtain a second data stream, thereby obtaining a total of n2 second data streams, where n2 = n0 / n1, n0 is an integer greater than 1, and n1 is an integer greater than 0. The bit mapping module is configured to map each two bits in the n2 second data streams into a PAM4 symbol, thereby obtaining a total of n2 PAM4 symbol data streams. The interleaving coding module is specifically configured to obtain a0 first bit sets from each first data stream of the n1 first data streams, thereby obtaining a total of m = n1 × a0 first bit sets, wherein the n1 first data streams are all outer-code encoded, each first bit set includes K bits, and n1, a0, and K are all integers greater than 1. Cyclic shift is performed on each of the m first bit sets to obtain m second bit sets, and inner coding is performed on each of the m first bit sets to obtain m parity bit sets, where both the inner coding and the outer coding are forward error correction (FEC) coding. Each second bit set includes K bits, and each parity bit set includes P bits, where P is an integer greater than or equal to 1. Two bits are obtained from each second bit set by polling to obtain a total of m×K consecutive bits, and two bits are obtained from each parity bit set by polling to obtain a total of m×P consecutive bits, to obtain a third bit set including m×N bits, where N=K+P. It should be understood that each second data stream includes multiple third bit sets, each third bit set contains m×K bits of the second bit set and m×P bits of the check bit set, the m×K bits from the second bit set in each third bit set are mapped to obtain a total of m×K / 2 PAM4 symbols, the m×P bits from the check bit set in each third bit set are mapped to obtain a total of m×P / 2 PAM4 symbols, and the m×2 bits mapped to m consecutive PAM4 symbols in the total m×N / 2 PAM4 symbols come from m second bit sets and / or m check bit sets.

[0199] In some possible implementations, each first data stream is outer code encoded, and 20 consecutive bits in the first data stream are interleaved and mapped to obtain at least 10 PAM4 symbols, the consecutive 20 bits come from two outer code symbols of an outer code codeword, and any two PAM4 symbols among the at least 10 PAM4 symbols are separated by at least 2 PAM4 symbols in the PAM4 symbol data stream.

[0200] In some possible implementations, the number of bits cyclically shifted in any two of the m first bit sets is different.

[0201] In some possible implementations, the m first bit sets and the m second bit sets are both represented as a bit matrix, and the bit matrix includes m rows and K columns of bits.

[0202] In some possible implementations, the second bit set is cyclically shifted leftward from the first bit set. bits are obtained, and the left cyclic shift satisfies the first condition, which includes:

[0203] Where M1[i][j] represents the bit in the i-th row and j-th column of the bit matrix corresponding to the m first bit sets before cyclic shift to the left, M2[i][j] represents the bit in the i-th row and j-th column of the bit matrix corresponding to the m second bit sets after cyclic shift to the left, Y%Z represents the remainder after the integer Y is divided by the integer Z, and 0≤j <K,0≤i<m,

[0204] In some possible implementations, the second bit set is cyclically shifted right by δ from the first bit set. i bits are obtained, and the right cyclic shift satisfies the second condition, which includes: M2[i][j]=M1[i][(j-δ i )%K]

[0205] Wherein, M1[i][j] represents the bit in the i-th row and j-th column of the bit matrix corresponding to the m first bit sets before cyclic shift to the right, M2[i][j] represents the bit in the i-th row and j-th column of the bit matrix corresponding to the m second bit sets after cyclic shift to the right, Y%Z represents the remainder after the integer Y is divided by the integer Z, 0≤j <K,0≤i<m,0≤δ i <K。

[0206] In some possible implementations, K=120, m=8, and the i-th second bit set is cyclically shifted leftward from the i-th first bit set. bits are obtained, 0≤i<8, The value of satisfies the first value item Any item in the first value item include:

[0207] {0,30,60,90,110,20,50,80};

[0208] {0,30,90,60,110,20,80,50};

[0209] {0,60,30,90,110,50,20,80};

[0210] {0,60,90,30,110,50,80,20};

[0211] {0,90,30,60,110,80,20,50};

[0212] {0,90,60,30,110,80,50,20}.

[0213] In some possible implementations, K=120, m=8, and the i-th second bit set is cyclically shifted right by δ from the i-th first bit set. i bits are obtained, 0≤i<8, δ i The value of satisfies any one of the second value items {δ0,δ1,δ2,δ3,δ4,δ5,δ6,δ7}, and the second value items {δ0,δ1,δ2,δ3,δ4,δ5,δ6,δ7} include:

[0214] {0,30,60,90,10,40,70,100};

[0215] {0,30,90,60,10,40,100,70};

[0216] {0,60,30,90,10,40,40,100};

[0217] {0,60,90,30,10,70,100,40};

[0218] {0,90,30,60,10,100,40,70};

[0219] {0,90,60,30,10,100,70,40}.

[0220] In an eleventh aspect, the present application provides a data processing device comprising an interleaving coding module and a bit mapping module. The interleaving coding module is configured to interleave and code each of n1 first data streams in n0 first data streams to obtain a second data stream, thereby obtaining a total of n2 second data streams, where n2 = n0 / n1, n0 is an integer greater than 1, and n1 is an integer greater than 0. The bit mapping module is configured to map each of the two bits in the n2 second data streams into a PAM4 symbol, thereby obtaining a total of n2 PAM4 symbol data streams. The interleaving coding module is specifically configured to obtain a0 first bit sets from each of the n1 first data streams to obtain a total of m = n1 × a0 first bit sets, wherein the n1 first data streams are all outer-coded, each first bit set comprises K bits, and n1, a0, and K are all integers greater than 1. The m first bit sets are each cyclically shifted to obtain m second bit sets, each comprising K bits. Inner coding is performed on each of the m second bit sets to obtain m inner codewords. Both the inner coding and outer coding are forward error correction (FEC) codes. Each inner codeword includes one second bit set involved in the inner coding and one parity bit set, totaling N bits, where N = K + P. Each parity bit set includes P bits, where P is an integer greater than or equal to 1. Two bits are obtained from each inner codeword by polling to obtain a third bit set. The third bit set includes m × N bits. In the third bit set, a total of m × K bits from the m second bit sets are continuous, and a total of m × P bits from the m parity bit sets are continuous. It should be understood that each second data stream includes multiple third bit sets. Each third bit set is mapped to obtain a total of m × N / 2 PAM4 symbols. The m × 2 bits mapped to m consecutive PAM4 symbols in the m × N / 2 PAM4 symbols come from m inner codewords.

[0221] In some possible implementations, each first data stream is outer code encoded, and 20 consecutive bits in the first data stream are interleaved and mapped to obtain at least 10 PAM4 symbols, the consecutive 20 bits come from two outer code symbols of an outer code codeword, and any two PAM4 symbols among the at least 10 PAM4 symbols are separated by at least 2 PAM4 symbols in the PAM4 symbol data stream.

[0222] In some possible implementations, the number of bits cyclically shifted in any two of the m first bit sets is different.

[0223] In some possible implementations, the m first bit sets and the m second bit sets are both represented as a bit matrix, and the bit matrix includes m rows and K columns of bits.

[0224] In some possible implementations, the second bit set is cyclically shifted leftward from the first bit set. bits are obtained, and the left cyclic shift satisfies the first condition, which includes:

[0225] Wherein, M1[i][j] represents the bit in the i-th row and j-th column of the bit matrix corresponding to the m first bit sets before cyclic shift to the left, M2[i][j] represents the bit in the i-th row and j-th column of the bit matrix corresponding to the m second bit sets after cyclic shift to the left, Y%Z represents the remainder after the integer Y is divided by the integer Z, 0≤i <m,0≤j<K,

[0226] In some possible implementations, the second bit set is cyclically shifted right by δ from the first bit set. i bits are obtained, and the right cyclic shift satisfies the second condition, which includes: M2[i][j]=M1[i][(j-δ i )%K]

[0227] Wherein, M1[i][j] represents the bit in the i-th row and j-th column of the bit matrix corresponding to the m first bit sets before cyclic shift to the right, M2[i][j] represents the bit in the i-th row and j-th column of the bit matrix corresponding to the m second bit sets after cyclic shift to the right, Y%Z represents the remainder after the integer Y is divided by the integer Z, 0≤i <m,0≤j<K,0≤δ i <K。

[0228] In some possible implementations, the m inner codewords are represented as a bit matrix including m rows and N columns, and the m inner codewords and the third bit set satisfy a third condition, where the third condition includes:

[0229] Among them, M c [i][j] represents the bit in row i and column j of the bit matrix corresponding to the m inner code words. Indicates the third bit set bits, 0≤i <m,0≤j<N, Indicates a floor operation.

[0230] In some possible implementations, K=120, m=8, and the i-th second bit set is cyclically shifted leftward from the i-th first bit set. bits are obtained, 0≤i<8, The value of satisfies the first value item Any item in the first value item include:

[0231] {0,30,60,90,110,20,50,80};

[0232] {0,30,90,60,110,20,80,50};

[0233] {0,60,30,90,110,50,20,80};

[0234] {0,60,90,30,110,50,80,20};

[0235] {0,90,30,60,110,80,20,50};

[0236] {0,90,60,30,110,80,50,20}.

[0237] In some possible implementations, K=120, m=8, and the i-th second bit set is cyclically shifted right by δ from the i-th first bit set. i bits are obtained, 0≤i<8, δ i The value of satisfies any one of the second value items {δ0,δ1,δ2,δ3,δ4,δ5,δ6,δ7}, and the second value items {δ0,δ1,δ2,δ3,δ4,δ5,δ6,δ7} include:

[0238] {0,30,60,90,10,40,70,100};

[0239] {0,30,90,60,10,40,100,70};

[0240] {0,60,30,90,10,40,40,100};

[0241] {0,60,90,30,10,70,100,40};

[0242] {0,90,30,60,10,100,40,70};

[0243] {0,90,60,30,10,100,70,40}.

[0244] In a twelfth aspect, the present application provides a data processing device, comprising: an interleaving coding module and a bit mapping module. The interleaving coding module is configured to perform interleaving coding on each of n1 first data streams in n0 first data streams to obtain a second data stream, thereby obtaining a total of n2 second data streams, where n2 = n0 / n1, n0 is an integer greater than 1, and n1 is an integer greater than 0. The bit mapping module is configured to map each of the two bits in the n2 second data streams into a PAM4 symbol, thereby obtaining a total of n2 PAM4 symbol data streams. The interleaving coding module is specifically configured to obtain a0 first bit sets from each of the n1 first data streams to obtain a total of m = n1 × a0 first bit sets, wherein the n1 first data streams are all outer-code encoded, each first bit set includes K bits, and n1, a0, and K are all integers greater than 1. Perform inner code encoding on the m first bit sets to obtain m inner code codewords. Both the inner code encoding and the outer code encoding are forward error correction FEC encoding. Each inner code codeword includes a first bit set and a check bit set participating in the inner code encoding, totaling N bits, where N=K+P. Each check bit set includes P bits, where P is an integer greater than or equal to 1. Perform interleaving on the m inner code codewords to obtain a second bit set. The second bit set includes m×N bits. bits satisfy the first or second condition, 0≤i <m,0≤j<N。

[0245] The first condition includes:

[0246] in, Indicates the first bit in the second bit set bits, represents the first inner code word bits, C i [j] represents the jth bit in the i-th inner code word.

[0247] The second condition includes:

[0248] in, Indicates the first bit in the second bit set bits, C i [(j-δ i )%K] represents the (j-δ i )% K bits, C i [j] represents the jth bit in the i-th inner code word.

[0249] It should be understood that each second data stream includes multiple second bit sets, and each second bit set is mapped to obtain a total of m×N / 2 PAM4 symbols, wherein the m×2 bits mapped to m consecutive PAM4 symbols in the m×N / 2 PAM4 symbols come from m inner code words.

[0250] In some possible implementations, K=120, m=8, The value of satisfies the first value item Any item in the first value item include:

[0251] {0,30,60,90,110,20,50,80};

[0252] {0,30,90,60,110,20,80,50};

[0253] {0,60,30,90,110,50,20,80};

[0254] {0,60,90,30,110,50,80,20};

[0255] {0,90,30,60,110,80,20,50};

[0256] {0,90,60,30,110,80,50,20};

[0257] δ i The value of satisfies any one of the second value items {δ0,δ1,δ2,δ3,δ4,δ5,δ6,δ7}, and the second value items {δ0,δ1,δ2,δ3,δ4,δ5,δ6,δ7} include:

[0258] {0,30,60,90,10,40,70,100};

[0259] {0,30,90,60,10,40,100,70};

[0260] {0,60,30,90,10,40,40,100};

[0261] {0,60,90,30,10,70,100,40};

[0262] {0,90,30,60,10,100,40,70};

[0263] {0,90,60,30,10,100,70,40}.

[0264] In the embodiments of this application, a cascaded FEC transmission scheme is adopted, whereby the data stream is sequentially encoded using both outer and inner codes. Based on this, this application designs a bit interleaving and mapping method, which allows both the bits in the outer and inner codewords to be discretely and evenly mapped onto modulation symbols. This makes the cascaded FEC transmission scheme highly robust against burst errors, particularly short burst errors, which can be directly corrected by inner code decoding. This scheme is applicable to a wide range of transmission scenarios, particularly practical coherent transmission scenarios where channels contain colored noise. BRIEF DESCRIPTION OF THE DRAWINGS

[0265] FIG1 is a schematic diagram of a communication system used in an embodiment of the present application;

[0266] FIG2 is a schematic diagram of a data transmission process in the communication system shown in FIG1 ;

[0267] FIG3 is a flow chart of a data processing method provided in an embodiment of the present application;

[0268] FIG4 is a schematic diagram of performing a left cyclic shift on the bits of each row in an embodiment of the present application;

[0269] FIG5 is a schematic diagram of performing an upward cyclic shift on the bits of each column in an embodiment of the present application;

[0270] FIG6 is a schematic diagram of position transformation of bits in each column in an embodiment of the present application;

[0271] FIG7 is a first schematic diagram of bit mapping in an embodiment of the present application;

[0272] FIG8 is a second schematic diagram of bit mapping according to an embodiment of the present application;

[0273] FIG9 is a third schematic diagram of bit mapping according to an embodiment of the present application;

[0274] FIG10 is a fourth schematic diagram of bit mapping according to an embodiment of the present application;

[0275] FIG11 is a schematic diagram of performing inner code encoding and interleaved modulation mapping on a data stream in an embodiment of the present application;

[0276] FIG12( a ) is a schematic diagram of a first operation flow of a transmitting end processing module in an embodiment of the present application;

[0277] FIG12( b ) is a schematic diagram of a second operation flow of the transmitting end processing module in an embodiment of the present application;

[0278] FIG12( c ) is a schematic diagram of a third operation flow of the transmitting end processing module in an embodiment of the present application;

[0279] FIG12( d ) is a schematic diagram of a fourth operation flow of the transmitting end processing module in an embodiment of the present application;

[0280] FIG13 is a schematic diagram of a 1×800G interface scenario in an embodiment of the present application;

[0281] FIG14 is a schematic diagram of a 2×400G interface scenario in an embodiment of the present application;

[0282] FIG15 is another schematic diagram of a 1×800G interface scenario in an embodiment of the present application;

[0283] FIG16 is a schematic diagram of a first type of cascade interleaving according to an embodiment of the present application;

[0284] FIG17 is a schematic diagram of a first structure of a convolutional interleaver according to an embodiment of the present application;

[0285] FIG18 is a second schematic diagram of cascade interleaving according to an embodiment of the present application;

[0286] FIG19 is a schematic diagram of a second structure of a convolutional interleaver according to an embodiment of the present application;

[0287] FIG20 is a third schematic diagram of cascade interleaving according to an embodiment of the present application;

[0288] FIG21 is a schematic diagram of a third structure of a convolutional interleaver according to an embodiment of the present application;

[0289] FIG22 is a schematic diagram of a fourth structure of a convolutional interleaver according to an embodiment of the present application;

[0290] FIG23 is a schematic diagram of a fifth structure of a convolutional interleaver according to an embodiment of the present application;

[0291] FIG24 is a schematic diagram of a data processing flow in an embodiment of the present application;

[0292] FIG25 is a schematic structural diagram of a data processing device according to an embodiment of the present application;

[0293] FIG26 is another flowchart of a data processing method provided in an embodiment of the present application;

[0294] FIG27 is a schematic diagram of a first embodiment of interleaving coding processing;

[0295] FIG28 is a schematic diagram of a second embodiment of interleaving coding processing;

[0296] FIG29 is a schematic diagram of a third embodiment of interleaving coding processing;

[0297] FIG30 is a schematic diagram of a fourth embodiment of interleaving coding processing;

[0298] FIG31 is a schematic diagram of a fifth embodiment of interleaving coding processing;

[0299] FIG32 is a schematic diagram of a sixth embodiment of interleaving coding processing;

[0300] FIG33 is a schematic diagram of a seventh embodiment of interleaving coding processing;

[0301] FIG34 is a schematic diagram of an eighth embodiment of interleaving coding processing;

[0302] FIG35 is a schematic diagram of a ninth embodiment of interleaving coding processing;

[0303] FIG36 is a schematic diagram of a tenth embodiment of interleaving coding processing;

[0304] FIG37 is a schematic diagram of an eleventh embodiment of interleaving coding processing;

[0305] FIG38 is a schematic diagram of a twelfth embodiment of interleaving coding processing;

[0306] FIG39 is another schematic diagram of the structure of a data processing device according to an embodiment of the present application;

[0307] Figure 40 is another structural schematic diagram of the data processing device in an embodiment of the present application. DETAILED DESCRIPTION

[0308] The embodiments of the present application provide a data processing method and apparatus. This enables the cascaded FEC transmission scheme to have strong burst resistance and be applicable to a wide range of transmission scenarios, particularly in practical coherent transmission scenarios where channels contain colored noise. It should be noted that the terms "first," "second," and so on, in the specification and claims of this application, and in the accompanying drawings, are used to distinguish similar objects, rather than to define a specific order or precedence. It should be understood that the above terms are interchangeable where appropriate, so that the embodiments described in this application can be implemented in an order other than that described in this application. Furthermore, the terms "including," "having," and any variations thereof, are intended to cover non-exclusive inclusions. For example, a process, method, system, product, or device comprising a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units that are not explicitly listed or that are inherent to such process, method, product, or device.

[0309] FIG1 is a schematic diagram of a communication system used in an embodiment of the present application. As shown in FIG1 , the communication system includes a transmitting device 01, a transmitting processing module 02, a channel transmission medium 03, a receiving processing module 04, and a receiving device 05. Taking the communication system as a data center network as an example, the transmitting device 01 and the receiving device 05 can be devices such as switches or routers, and the transmitting device 01 is also called a client-side chip (host chip) located at the transmitting end, and the receiving device 05 is also called a client-side chip located at the receiving end. The channel transmission medium 03 can be an optical fiber. The client-side chip is sometimes also called a client-side device (host device). The transmitting device 01 and the transmitting processing module 02 can be connected via an attachment unit interface (AUI), and the receiving device 05 and the receiving processing module 04 can be connected via an AUI. The transmitting processing module 02 and the receiving processing module 04 can be optical modules, electrical modules, connectors, or other modules that process data during data transmission. For example, the processing module may be an 800LR module (a coherent optical module). Furthermore, the transmitting device 01, transmitting processing module 02, channel transmission medium 03, receiving processing module 04, and receiving device 05 in the communication system may support bidirectional transmission or unidirectional transmission, without limitation herein.

[0310] Figure 2 is a schematic diagram of a data transmission process within the communication system shown in Figure 1. As shown in Figure 2, during data transmission from transmitting device 01 to receiving device 05, transmitting device 01 performs outer code encoding on the data and then transmits the outer-coded data to transmitting processing module 02. Transmitting processing module 02 performs inner code encoding on the outer-coded data to obtain outer-coded and inner-coded data, and then transmits the outer-coded and inner-coded data to channel transmission medium 03. Channel transmission medium 03 transmits the outer-coded and inner-coded data to receiving processing module 04. Receiving processing module 04 performs inner code decoding on the outer-coded and inner-coded data and transmits the inner-coded data to receiving device 05. Receiving device 05 performs outer code decoding on the inner-coded data.

[0311] It should be understood that the distinction between "inner" in inner code and "outer" in outer code is based solely on the distance between the entity performing the data operation and the channel transmission medium 03. The entity performing the inner code operation is closer to the channel transmission medium, while the entity performing the outer code operation is farther away. In the embodiment of the present application, after data is transmitted from transmitting device 01, it passes through transmitting processing module 02 to channel transmission medium 03, and then from channel transmission medium 03 to receiving device 05 via receiving processing module 04. The data encoded by transmitting device 01 is farther from channel transmission medium 03 than the data encoded by transmitting processing module 02, and the data decoded by receiving device 05 is farther from channel transmission medium 03 than the data decoded by receiving processing module 04. Therefore, data encoded by transmitting device 01 is referred to as data encoded with an outer code, data encoded by transmitting processing module 02 is referred to as data encoded with an inner code, data decoded by receiving device 05 is referred to as data decoded with an outer code, and data decoded by receiving processing module 04 is referred to as data decoded with an inner code. In one possible implementation, both the inner and outer codes described above employ FEC encoding, thereby forming a cascaded FEC transmission scheme. For example, the transmitting device 01 may employ Reed-Solomon (RS) code for outer code encoding, and the transmitting processing module 02 may employ Hamming code for inner code encoding. For another example, the transmitting device 01 may employ RS code for outer code encoding, and the transmitting processing module 02 may employ Bose–Chaudhuri–Hocquenghem (BCH) code for inner code encoding.

[0312] It should be noted that the above content is an illustrative description of the application scenarios of the data processing method provided in the embodiments of the present application, and does not constitute a limitation on the application scenarios of the data processing method. A person skilled in the art will know that as business needs change, its application scenarios can be adjusted according to application needs, and the embodiments of the present application do not list them one by one.

[0313] Figure 3 is a flow chart of a data processing method provided in an embodiment of the present application. It should be understood that this method processes data streams encoded with an outer code, and can be implemented specifically by the transmitting end processing module 02 described above.

[0314] 301. Perform inner code encoding on n first data streams respectively to obtain n second data streams.

[0315] In this embodiment, the Physical Medium Attachment (PMA) sublayer of the transmitting processing module performs first data processing on data from multiple multiple multiple module performs first data processing on data from multiple synchronized client lanes, and obtains n first data streams, where n is an integer greater than 1. The above first data processing may include alignment lock, lane de-skew, lane reorder processing, or concatenated interleaving processing, etc. The above n first data streams are all data streams encoded by an outer code. For example, the outer code encoding may use RS code, and the n data streams after outer code encoding may include multiple RS codewords. In practical applications, other coding methods may also be used for outer code encoding. For the convenience of description, the following uniformly uses RS codewords to represent the codewords generated after outer code encoding. It should be noted that in this application, the value of the outer code length is counted in units of outer code symbols, where a symbol may include one or more bits. For example, the outer code is the KP4RS(544,514) code used, with a code length of 544 symbols, and one outer code symbol contains 10 bits.

[0316] The inner code encoder performs inner code encoding on every K bits in each first data stream, and then adds P check bits to obtain an inner codeword with a total of N bits. Here, the K bits can be referred to as the inner code information sequence, and K + P = N. Usually, K is a multiple of 10, and these K bits correspond to K / 10 outer code symbols. In some scenarios, the K / 10 outer code symbols corresponding to the K information bits come from K / 10 different outer codewords.

[0317] It should be understood that each second data stream after inner code encoding contains at least one inner codeword. One inner codeword is obtained from each second data stream respectively, resulting in a total of n inner codewords. These n inner codewords include n / m codeword sets, namely codeword set 0, codeword set 1,..., codeword set n / m - 1. Each codeword set includes m inner codewords. Codeword set h (0 ≤ h < n / m) contains codewords m×h, codeword m×h + 1,..., codeword m×h + m - 1. Among them, n is divisible by m.

[0318] It should be noted that the above codeword sets are only concepts introduced for the convenience of description. In practical applications, the second data stream is a whole and there is no such division. Each codeword set can be regarded as multiple bits in the second data stream.

[0319] 302. Perform bit interleaving on the n / m codeword sets respectively to obtain n / m target bit sets.

[0320] It should be understood that the number of bits in both the codeword set and the target bit set is m×N bits. This step is to perform a position transformation on the bits in the codeword set to obtain the target bit set. As an example, the target bit set can be represented as a bit matrix with m rows and N columns. As another example, the target bit set can also be represented as a one-dimensional array including m×N bits. It should be noted that taking the codeword set as a bit matrix as an example, the bit interleaving provided in this application includes, but is not limited to, performing a position transformation on the bits in each row of the codeword set (referred to as row transformation), performing a position transformation on the bits in each column of the codeword set (referred to as column transformation), and performing a position exchange on the bits in each row and each column of the codeword set (referred to as row-column transformation). Among them, the row-column transformation includes performing row transformation first and then column transformation, performing column transformation first and then row transformation, and performing row and column transformation simultaneously. Below, several specific implementation manners will be used to introduce the bit interleaving in detail.

[0321] For simplicity of description, the m×N codeword bits in the codeword set h (0≤h<n / m) are represented by a first matrix H1 with m rows and N columns, where each row of the first matrix H1 includes N bits of an inner codeword. The bit at the i-th (0≤i<m) row and j-th (0≤j<N) column in the first matrix H1 is denoted as H1[i][j]. More specifically, H1[i][j] represents the j-th bit of the i-th inner codeword in the codeword set h, and also represents the j-th bit in the codeword m×h+i from the second data stream m×h+i. It should be noted that the n / m codeword sets correspond to n / m first matrices H1, that is, the codeword set h (0≤h<n / m) corresponds to the h-th first matrix H1. For simplicity of description below, the h-th first matrix H1 is simply described as the first matrix H1.

[0322] A total of K bits from the 0-th column to the K-1 column in each row of the first matrix H1 correspond to the K-length information bits of an inner codeword; a total of m×K bits from the 0-th column to the K-1 column in the first matrix H1 correspond to the m×K information bits of m inner codewords. Similarly, a total of P bits from the K-th column to the N-1 column in each row of the first matrix H1 correspond to the P-length parity bits of an inner codeword; a total of m×P bits from the K-th column to the N-1 column in the first matrix H1 correspond to the m×P parity bits of m inner codewords.

[0323] Below, the specific manners of independently implementing row transformation and column transformation will be introduced first.

[0324] Implementation manner 1 of bit interleaving: Row transformation (which can also be called the first position transformation).

[0325] Specifically, perform a first position exchange on the K information bits of each inner codeword in the codeword set. Alternatively, it can also be described as "performing a first position transformation on the K information bits of each row in the first matrix H1". In one possible implementation manner, this first position transformation is specifically to perform a left circular shift or a right circular shift on the K information bits of each row in the first matrix H1. Taking the left circular shift as an example, perform a left circular shift of i×Δ bits on the K information bits in the i-th (0≤i<m) row of the first matrix H1, where the non-zero integer Δ is the row offset constraint factor. It should be noted that for the K information bits (u0, u1, u2, u3, …, u K-2 , u K-1 ), perform a left circular shift of i×Δ bits to obtain the shifted K bits (u (i×Δ)％K , u (1+i×Δ)％K , u (2+i×Δ)％K , …, u(K-2+i×Δ)%K, u(K-1+i×Δ)%K).

[0326] [[ID=·13]]FIG. 4 is a schematic diagram of performing a left circular shift on the information bits of each row in an embodiment of the present application. As shown in the example of (a) in FIG. 4, taking K = 8 and a left circular shift of 2 bits as an example, the 8 information bits (u i,0 , u i,1 , u i,2 , u i,3 , u i,4 , u i,5 , u i,6 , u i,7 ) in the i-th row are left circularly shifted by 2 bits to be (u i,2 , u i,3 , u i,4 , u i,5 , u i,6 , u i,7 , u i,0 , u i,1 ). As shown in the example of (b) in FIG. 4, taking Δ = 2 as an example, the 8 information bits in the i-th row are left circularly shifted by i×2 bits, for example, the 8 information bits in the 0-th row are left circularly shifted by 0 bits, the 8 information bits in the 1-st row are left circularly shifted by 2 bits, and the 8 information bits in the 2-nd row are left circularly shifted by 4 bits. Perform circular shifting in this way to implement the first position transformation on the K information bits of each row in the first matrix H1.

[0327] [[ID=4·8]]More specifically, the first position transformation is introduced by means of circular shifting through the following formulas.

[0328] As an example, the first position transformation using a left circular shift satisfies formula (1.1):

[0329] H1[i][j] represents the bit at the j-th column of the i-th row in the bit matrix before the first position transformation, H2[i][j] represents the bit at the j-th column of the i-th row in the bit matrix after the first position transformation, Y % Z represents the remainder of the integer Y divided by the integer Z, and 0 ≤ i < m. Generally, the row offset constraint factor Δ is a multiple of 10 and 0 < Δ < K.

[0330] It should be noted that circularly shifting the K information bits to the left by i × Δ bits is equivalent to circularly shifting the K information bits to the left by (i × Δ) % K bits. That is, the above formula (1.1) can be written as the following formula (1.2):

[0331] For the K information bits in the i-th row of the first matrix H1, circularly shifting them to the left by i × Δ bits gives the K bits from the 0-th column to the (K - 1)-th column in the i-th row of the second matrix H2. Equivalently, for the K information bits from the 0-th column to the (K - 1)-th column in the i-th row of the first matrix H1, circularly shifting them to the right by i × (K - Δ) bits gives the K bits from the 0-th column to the (K - 1)-th column in the i-th row of the second matrix H2. As shown in the example of (a) in Figure 4, when K = 8, circularly shifting the information bits to the left by 2 bits is equivalent to circularly shifting them to the right by 6 bits.

[0332] As another example, the first position transformation uses a right circular shift to satisfy formula (1.3):

[0333] where the integer α is a multiple of K, and when 0 ≤ i < m and 0 ≤ j < K is a non-negative integer, the integer Generally, the row offset constraint factor is a multiple of 10 and Other parameters the same as the above formula (1.1) are not elaborated here one by one.

[0334] In some specific formula expressions, for simplicity of description, formula (1.3) is abbreviated as formula (1.4):

[0335] It should also be noted that the above circular shift of the K information bits from the 0-th column to the (K - 1)-th column in each row of the first matrix H1 only operates on the information bits in the first matrix H1. Therefore, it can also be described as: circularly shifting the K information bits from the 0-th column to the (K - 1)-th column in each row of the first matrix H1 to obtain the fourth matrix H4 with m rows and K columns. Specifically, for the first position transformation using a left circular shift to satisfy formula (3.1): H4 = H1[i][(j + i × Δ) % K]

[0336] Among them, the meanings of the parameters in formula (3.1) are similar to those in formula (1.1), and will not be elaborated here.

[0337] Implementation method 2 of bit interleaving: column transformation (which can also be called the second position transformation).

[0338] It should be noted that the column transformation introduced in this implementation method is described based on the fact that the first matrix H1 is transformed into the second matrix H2 through row transformation above. In some possible scenarios, this implementation method can also be used to perform column transformation on the first matrix H1 first, which will not be elaborated here.

[0339] Specifically, the bits at the same position in the second matrix H2 are subjected to the second position transformation to obtain the third matrix H3. It should be understood that the bits at the same position in the second matrix H2 can be understood as the m bits in the same column of the second matrix H2, that is, the position transformation of the m bits in the same column is performed. Alternatively, the bits at the same position in the second matrix H2 can also be understood as the G×m bits in the same G columns of the second matrix H2, where G is an integer greater than 1, that is, the up and down position transformation is performed with G bits in the same G columns of each row as a unit. For the sake of convenience of description, the same column at the same position will be used as an example for introduction below.

[0340] In a possible implementation manner, the second matrix H2 is divided into m / L first sub-matrices, and each first sub-matrix contains L rows and N columns. In each first sub-matrix, the L bits in each column are cycled upward or downward to implement the position transformation of the bits in each first sub-matrix. Taking the upward cyclic shift as an example, the L bits in the jth (0≤j<N) column in each first sub-matrix are cycled upward by θ×(j%L) bits, where the non-zero integer θ is the column offset constraint factor. Here, cycling the L bits in the jth (0≤j<N) column in each first sub-matrix upward by θ×(j%L) bits is also equivalent to cycling upward by θ×j bits, which is known to those of ordinary skill in the art and will not be elaborated here. For the L bits are cycled upward by θ×(j%L) to obtain the shifted L bits

[0341] FIG. 5 is a schematic diagram of cyclically shifting the L bits in each column of each first sub-matrix upward in an embodiment of the present application. As shown in the example of (a) in FIG. 5, taking L = 8 and cyclically shifting upward by 2 bits as an example, the 8 bits in the jth column are cycled upward by 2 bits to obtain the shifted 8 bits As shown in the example of (b) in Figure 5, taking θ = 2 as an example, the 8 bits in the j-th column are circularly shifted upward by 2×(j%8) bits. For example, the 8 bits in the 0-th column are circularly shifted upward by 0 bits, the 8 bits in the 1st column are circularly shifted upward by 2 bits, and the 8 information bits in the 2nd column are circularly shifted upward by 4 bits. Circular shifting is performed in this way to implement the second position transformation on the bits at the same position in the second matrix H2.

[0342] More specifically, the second position transformation is introduced in a circular shifting manner through the following formulas.

[0343] As an example, the second position transformation uses upward circular shifting to satisfy formula (2.1):

[0344] H2[i][j] represents the bit in the i-th row and j-th column of the bit matrix before the second position transformation, and H3[i][j] represents the bit in the i-th row and j-th column of the bit matrix after the second position transformation. represents taking the floor, Y%Z represents the remainder after integer Y is divided by integer Z, 0 ≤ i < m, 0 ≤ j < N. The non-zero integer θ is the column offset constraint factor. Usually, the column offset constraint factor 0 < θ < L.

[0345] It should be understood that the above formula (2.1) can also be written as:

[0346] For the L bits in the j-th column of the first sub-matrix in the second matrix H2, circularly shifting upward by θ×(j%L) bits is equivalent to circularly shifting downward by (L - θ)×(j%L) bits. As shown in the example of (a) in Figure 5, L = 8, and circularly shifting upward by 2 bits is equivalent to circularly shifting downward by 6 bits.

[0347] As another example, the second position transformation uses downward circular shifting to satisfy formula (2.2):

[0348] Where the integer β is a multiple of L, when all 0 ≤ i < m and 0 ≤ j < N is a non-negative integer, the integer Usually, the column offset constraint factor Other parameters the same as the above formula (2.1) are not elaborated here one by one.

[0349] In some specific formula expressions, for simplicity of description, formula (2.2) is abbreviated as formula (2.3):

[0350] In another possible implementation, different from the above-mentioned upward cyclic shift or downward cyclic shift, the second position transformation satisfies formula (2.4):

[0351] H2[i][j] represents the bit in the i-th row and j-th column of the bit matrix before the second position transformation, and H3[i][j] represents the bit in the i-th row and j-th column of the bit matrix after the second position transformation. Indicates rounding down, Y%Z indicates the remainder after dividing integer Y by integer Z, Y^Z indicates the integer corresponding to the bit sequence obtained by performing an XOR operation on the bit sequence corresponding to integer Y and the bit sequence corresponding to integer Z, 0≤i <m,0≤j<N。

[0352] FIG6 is a schematic diagram of a position transformation of bits in each column in an embodiment of the present application. As shown in FIG6 , when m=8, L=8, a second position transformation method satisfying the above formula (2.4) is shown. i,j Represented as the bits in the i-th row and j-th column of the second symbol matrix H2. Every consecutive 8 columns of the second matrix H2, i.e., columns 8*k to 8*k+7, are interleaved and mapped to the consecutive 8 columns of the third symbol matrix, i.e., columns 8*k to 8*k+7, in the manner shown in the figure.

[0353] It should be noted that when the integer L is a power of 2, the second position transformation can also satisfy the formula (2.5): H3[i][j]=H2[i^(j%L)][j]

[0354] H2[i][j] represents the bit in the i-th row and j-th column of the bit matrix before the second position transformation, H3[i][j] represents the bit in the i-th row and j-th column of the bit matrix after the second position transformation, Y%Z represents the remainder after the integer Y is divided by the integer Z, Y^Z represents the integer corresponding to the bit sequence obtained by performing an XOR operation on the bit sequence corresponding to the integer Y and the bit sequence corresponding to the integer Z, 0≤i <m,0≤j<N。

[0355] It should also be noted that the first position transformation mentioned above only transforms the information bits, while the second position transformation transforms both the information bits and the check bits. For the fourth matrix H4 described above, which only transforms the information bits with m rows and K columns, the second position transformation can be expressed as follows:

[0356] Specifically, the fourth matrix H4 with m rows and K columns and the first matrix H1 with columns K to N-1, a total of m rows and N columns, are divided into multiple second sub-matrices, each of which contains L rows and N columns. The L bits in each column of each second sub-matrix are permuted to obtain a third matrix H3 with m rows and N columns.

[0357] One specific implementation is to cyclically shift the L bits in the j-th (0 ≤ j < N) column of each second sub-matrix upward by θ×(j % L) bits. More specifically, for 0 ≤ i < m, the second position transformation can also satisfy formula (4.1):

[0358] where the integer θ is the column offset constraint factor. Formula (4.1) can also be abbreviated as:

[0359] Another specific implementation is that, for 0 ≤ i < m, the second position transformation can also satisfy formula (4.2):

[0360] When L is a power of 2, for 0 ≤ i < m, the second position transformation can also satisfy formula (4.3):

[0361] It should be understood that the above specific ways of independently implementing the row transformation and the column transformation have been introduced, that is, bit interleaving includes 2 steps of operations. In some possible scenarios, the above row transformation and column transformation can also be implemented through 1 step of operation. The following details this implementation method.

[0362] Implementation method 3 of bit interleaving: The row transformation and the column transformation are implemented through 1 step of operation.

[0363] In one specific implementation, for 0 ≤ i < m, bit interleaving satisfies formula (5):

[0364] H1[i][j] represents the bit in the i-th row and j-th column of the bit matrix before bit interleaving, H3[i][j] represents the bit in the i-th row and j-th column of the bit matrix after bit interleaving, Y % Z represents the remainder of the integer Y divided by the integer Z, Δ is a non-zero integer greater than -K and less than K, represents rounding down, and θ is a non-zero integer greater than -L and less than L.

[0365] Formula (5) can also be abbreviated as:

[0366] In another specific implementation, for 0 ≤ i < m, bit interleaving satisfies formula (6):

[0367] H1[i][j] represents the bit in the i-th row and j-th column of the bit matrix before bit interleaving, H3[i][j] represents the bit in the i-th row and j-th column of the bit matrix after bit interleaving, Y % Z represents the remainder of the integer Y divided by the integer Z, Δ is a non-zero integer greater than -K and less than K, represents rounding down, θ is a non-zero integer greater than -L and less than L, and Y^Z represents the integer corresponding to the bit sequence obtained by performing an exclusive OR operation on the bit sequence corresponding to integer Y and the bit sequence corresponding to integer Z.

[0368] When L is a power of 2, for 0 ≤ i < m, the bit interleaving satisfies formula (7):

[0369] It should be noted that when the integer Δ is a multiple of 10 and 1 outer code symbol in the outer codeword contains 10 bits, K information bits can be considered as K / 10 symbols, where each symbol corresponds to 10 information bits. Cyclically shifting the K information bits in the i-th (0 ≤ i < m) row of the first matrix H1 by i×Δ bits can be considered as cyclically shifting the K / 10 symbols in the i-th (0 ≤ i < m) row of the first matrix H1. symbols. The specific implementation method is known to those of ordinary skill in the art and will not be elaborated here.

[0370] When specific values of parameters such as Δ, θ, m, and L are given, the interleaving correspondence relationship for obtaining the third matrix H3 by bit interleaving the first matrix H1 can be described using a table. The specific implementation method is known to those of ordinary skill in the art and will not be elaborated here.

[0371] When specific values of parameters such as Δ, θ, m, and L are given, the above formula (5) or (6) can be simply transformed into other formulas. For example, when m = L, formula (5) can be simplified as follows:

[0372] Formula (6) can be transformed as follows:

[0373] Or

[0374] It should be understood that the specific implementation methods of other simple transformations are known to those of ordinary skill in the art and will not be elaborated here.

[0375] It should be noted that the above codeword sets, bit matrices, and sub-matrices are concepts introduced for the convenience of description. In actual applications, the data stream is a whole and there is no division. Each codeword set, bit matrix, and sub-matrix can be regarded as one or more bits in the data stream. In addition, in actual applications, the above first matrix, second matrix, third matrix, fourth matrix, etc. may not be presented in matrix form. For example, the first matrix H1 is presented as a first bit set, and the first bit set includes m first bit subsets, and each first bit subset contains N column bit elements corresponding to a row in the first matrix H1.

[0376] It should be noted that in the above implementation, the target bit set after bit-interleaving of m codewords is represented by the third matrix H3 with m rows and N columns. In addition, the target bit set can also be represented by a one-dimensional array (array), denoted as array A, which contains m×N bits. The t-th (0≤t<m×N) bit in array A is denoted as A[t]. Obtaining the array A containing m×N bit elements by bit-interleaving the first matrix H1 can also be represented in the following manner.

[0377] As an example, for 0≤i<m, the bit-interleaving satisfies formula (8):

[0378] H1[i][j] represents the bit in the i-th row and j-th column of the bit matrix before the said bit-interleaving, A[t] represents the t-th bit in the one-dimensional array after the said bit-interleaving, 0≤t<m×N, Y%Z represents the remainder after integer Y is divided by integer Z, Δ is a non-zero integer greater than -K and less than K, represents rounding down, and θ is a non-zero integer greater than -L and less than L.

[0379] As another example, for 0≤i<m, the bit-interleaving satisfies formula (9):

[0380] H1[i][j] represents the bit in the i-th row and j-th column of the bit matrix before bit-interleaving, A[t] represents the t-th bit in the one-dimensional array after the said bit-interleaving, Y%Z represents the remainder after integer Y is divided by integer Z, Δ is a non-zero integer greater than -K and less than K, represents rounding down, θ is a non-zero integer greater than -L and less than L, and Y^Z represents the integer corresponding to the bit sequence obtained by performing an exclusive OR operation on the bit sequences corresponding to integer Y and integer Z.

[0381] When L is a power of 2, for 0≤i<m, the bit-interleaving satisfies formula (10):

[0382] 303. Map the m×N bits in each target bit set respectively to obtain m×N / L modulation symbols, so as to obtain a total of n×N / L modulation symbols.

[0383] In this embodiment, m is divisible by L. Every L bits in the target bit set are mapped to one modulation symbol, that is, one modulation symbol includes L bits. The L bits in each modulation symbol come from L inner codewords respectively. And if the L bits mapped to the modulation symbol all come from the information bits of the inner codewords, then any two of the L bits mapped to the modulation symbol come from two different positions of two different inner codewords.

[0384] It should be understood that the n×N / L modulation symbols obtained by mapping all target bit sets can be represented as a modulation symbol stream. Alternatively, the m×N / L modulation symbols obtained by mapping each target bit set can be represented as a modulation symbol stream, resulting in a total of n / m modulation symbol streams. The modulation symbol stream can then undergo additional data processing before being sent to the channel transmission medium for transmission. Additional data processing may include polarization distribution or DSP framing.

[0385] In a possible implementation, when N is divisible by L, the N bits of each inner codeword are respectively mapped to N modulation symbols, and the N bits of the inner codeword include L first bit subsets, bits in the same first bit subset are respectively mapped to the same bit positions of different modulation symbols, and bits in different first bit subsets are respectively mapped to different bit positions of different modulation symbols. For example, a modulation symbol includes bit position b0, bit position b1, ..., bit position b L-1 , the N bits of the inner code word are mapped to bit b0, bit b1, ..., bit b L-1 The number of bits is N / L. It should be understood that the probability of errors occurring in the above L bits during transmission is not necessarily equal. Mapping the bits of an inner codeword more evenly to modulation symbols can improve the burst resistance of the cascaded FEC scheme in actual transmission.

[0386] It should be noted that in some possible scenarios, the n first data streams are all processed by identification locking and channel correction. When the W×L bits in W consecutive modulation symbols are all information bits of the inner code word, the W×L bits come from more than 2 outer code code words encoded by the outer code, where W≥2.

[0387] In some implementations used in coherent optical communications, the modulation scheme is dual-polarization quadrature amplitude modulation (DP-QAM), such as DP-QPSK or DP-16QAM. For DP-QPSK modulation, one DP-QPSK modulation symbol corresponds to L = 4 bits; for DP-16QAM modulation, one DP-16QAM modulation symbol corresponds to L = 8 bits.

[0388] In some implementations applied to direct-detection optical communications, the modulation scheme is pulse-amplitude modulation (PAM), such as PAM4. Under PAM4 modulation, one PAM4 modulation symbol corresponds to L=2 bits.

[0389] The following describes a specific implementation of the mapping by taking the target bit set represented by the third matrix H3 as an example.

[0390] Mapping implementation method 1:

[0391] Each L consecutive bits of the m bits in each column of the third matrix H3 are mapped to a modulation symbol. Each third matrix H3 is mapped to m×N / L modulation symbols.

[0392] In one possible implementation, the m / L modulation symbols obtained by mapping the m bits in each column of the third matrix H3 are continuous in the modulation symbol stream. That is, the m / L modulation symbols obtained by mapping each column in the third matrix H3 serve as the continuous m / L modulation symbols in the modulation symbol stream, and the m×N / L modulation symbols obtained by mapping N columns in the third matrix H3 serve as the continuous m×N / L modulation symbols in the modulation symbol stream.

[0393] Figure 7 is a first schematic diagram of bit mapping in an embodiment of the present application. As shown in Figure 7, when m / L=2, the third matrix H3 maps two modulation symbols per column, and these two modulation symbols are represented by S(0,j) and S(1,j), where 0≤j <N。

[0394] In another possible implementation, the m bits in column B of the third matrix H3 are mapped to obtain m / L first modulation symbols, and each consecutive T first modulation symbols among the m / L first modulation symbols are continuous in the modulation symbol stream. The m bits in column C of the third matrix H3 are mapped to obtain m / L second modulation symbols, and each consecutive T second modulation symbols among the m / L second modulation symbols are continuous in the modulation symbol stream. Column B is adjacent to column C, and T consecutive first modulation symbols among the m / L first modulation symbols are continuous with T consecutive second modulation symbols among the m / L second modulation symbols in the modulation symbol stream, and m / L is divisible by T.

[0395] FIG. 8 is a second schematic diagram of mapping bits in an embodiment of the present application. As shown in FIG. 8, when m / L = 4 and T = 2, each column of the third matrix H3 is mapped to 4 modulation symbols, denoted as S(0,j), S(1,j), S(2,j), S(3,j), where 0 ≤ j < N. It can be seen that among the m / L modulation symbols obtained by mapping each column of the third matrix H3, the first T modulation symbols are used as T consecutive modulation symbols in the modulation symbol stream. Correspondingly, a total of T×N modulation symbols in N columns are used as T×N consecutive modulation symbols in the modulation symbol stream. Among the m / L modulation symbols obtained by mapping each column of the third matrix H3, the next T modulation symbols are used as T consecutive modulation symbols in the modulation symbol stream. Correspondingly, a total of T×N modulation symbols in N columns are used as the next consecutive T×N modulation symbols in the modulation symbol stream. By analogy, m×N / L consecutive modulation symbols in the modulation symbol stream can be obtained.

[0396] Implementation method 2 of mapping:

[0397] The L bits in each modulation symbol come from L r inner code codewords. Each of the L r inner code codewords has L c bits, and a total of L r ×L c bits are mapped to one modulation symbol. The 2L bits in two consecutive modulation symbols come from 2L r inner code codewords. Each of the 2L r inner code codewords has L c bits and are mapped to two consecutive modulation symbols. L = L r ×L c [[ID=二十六]],L c > 1. That is to say, a total of L r columns in L c rows of the third matrix H3 are mapped to one modulation symbol, where L r ×L c = L bits, and L c > 1. For example, the L inner code bits corresponding to the bit b0, bit b1,..., bit b L-1 of a modulation symbol come from L r different inner code codewords, and each inner code codeword provides L c bits. For the above-mentioned third matrix H3, a total of m×L c bits in every L c columns are mapped to m / L r modulation symbols. Each third matrix H3 is mapped to m×N / L modulation symbols, obtaining m×N / L consecutive modulation symbols in the modulation symbol data stream.

[0398] In one possible implementation, the third matrix H3 is c m / L obtained by column mapping r modulation symbols as the continuous m / L in the modulation symbol stream r modulation symbols, and the m×N / L modulation symbols obtained by N column mapping are used as continuous m×N / L modulation symbols in the modulation symbol stream.

[0399] FIG9 is a third schematic diagram of mapping bits in an embodiment of the present application. As shown in FIG9, when When each L in the third matrix H3 c The columns map a total of m×L c The bitmap is modulation symbols, represented by S(0,j) and S(1,j), where 0≤j <N / L c .

[0400] In another possible implementation, the bit mapping in column B of the third matrix H3 is m / L r The first modulation symbol, m / L r Each consecutive T first modulation symbols in the first modulation symbols are continuous in the modulation symbol stream. The bit mapping in the C column of each target bit set is obtained by m / L r The second modulation symbol, m / L r Each consecutive T second modulation symbols in the modulation symbol stream is continuous. c Column C also includes L c Column, Column B is adjacent to Column C, m / L r The T consecutive first modulation symbols in the first modulation symbols are equal to m / L r T second modulation symbols are continuous in the modulation symbol stream, m / L r Divisible by T.

[0401] FIG10 is a fourth schematic diagram of mapping bits in an embodiment of the present application. As shown in FIG10 , when When T=2, each L in the third matrix H3 c The columns map a total of m×L c The bitmap is modulation symbols, represented by S(0,j), S(1,j), S(2,j), S(3,j), where 0≤j <N / L c It can be seen that each L c m / L obtained by column mapping r The first T modulation symbols in the modulation symbols are used as the consecutive T modulation symbols in the first modulation symbol stream. Accordingly, the total number of N columns is T×N / L. cmodulation symbols as consecutive T×N / L in the modulation symbol stream c modulation symbols. c m / L obtained by column mapping r The next T modulation symbols in the modulation symbols are used as the consecutive T modulation symbols in the first modulation symbol stream. Accordingly, the total number of N columns is T×N / L. c modulation symbols as the next consecutive T×N / L in the modulation symbol stream c Modulation symbols. And so on, a continuous m×N / L modulation symbols in the modulation symbol stream can be obtained.

[0402] In the embodiments of this application, a cascaded FEC transmission scheme is adopted, whereby the data stream is sequentially encoded using both outer and inner codes. Based on this, this application designs a bit interleaving and mapping method, which allows both the bits in the outer and inner codewords to be discretely and evenly mapped onto modulation symbols. This makes the cascaded FEC transmission scheme highly robust against burst errors, particularly short burst errors, which can be directly corrected by inner code decoding. This scheme is applicable to a wide range of transmission scenarios, particularly practical coherent transmission scenarios where channels contain colored noise.

[0403] The following further introduces the process of the data processing method described in FIG. 3 in conjunction with some specific embodiments.

[0404] Embodiment 1: The target bit set is represented by a bit matrix, n=32, m=16, K=160, L=8.

[0405] The Physical Medium Attachment (PMA) sublayer of the transmitting end processing module processes data from multiple synchronous client lanes to produce n = 32 first data streams. These 32 first data streams are then fed into an inner code encoder for inner code encoding to produce 32 second data streams. The inner code uses the BCH (176, 160) scheme, meaning the codeword length is N = 176, the information bit length is K = 160, and the parity bit length is P = 16. The 160 information bits in each inner codeword come from 16 symbols of 16 different outer code Reed-Solomon (RS) codewords.

[0406] The 32 codewords after the inner code encoding are divided into h = 2 codeword sets, each containing m = 16 BCH (176, 160) codewords. Considering DP-16QAM modulation, every L = 8 bits are mapped to a DP-16QAM symbol. After bit interleaving and mapping, the 16 BCH (176, 160) codewords in each codeword set yield 352 DP-16QAM symbols.

[0407] The above 16 BCH (176, 160) codewords, totaling 2816 bits, are represented by a first matrix H1 with 16 rows and 176 columns, where each row of the first matrix H1 contains 176 bits of an inner code BCH (176, 160) codeword. The first matrix H1 is bit-interleaved to obtain a third matrix H3 with 16 rows and 176 columns, and its interleaving correspondence is: for 0≤i<16,

[0408] in, represents a floor operation, a non-zero integer Δ is a row offset constraint factor, Δ is a multiple of 10 and -160 < Δ < 160, and a non-zero integer θ is a column offset constraint factor, and the non-zero integer θ satisfies -8 < θ < 8. In this embodiment, typical values ​​of the integer Δ are 10, 20, 30, 50, 60, 70, 90, 100, 110, 130, 140, and 150. A typical value of the integer θ is θ = 7, and another typical value is θ = 1.

[0409] The third matrix H3 with 16 rows and 176 columns mentioned above contains 16 bits in each column. Every 8 bits of the 16 bits are mapped to a DP-16QAM symbol. Each column is mapped to 2 modulation symbols respectively. A specific implementation method is to map rows 0-7 in each column to a DP-16QAM symbol, and rows 8-15 to another DP-16QAM symbol. Each third matrix H3 is mapped to 352 DP-16QAM symbols. The 2 DP-16QAM symbols mapped in each column serve as 2 consecutive DP-16QAM symbols in the first modulation symbol stream, and the 352 DP-16QAM symbols mapped in 176 columns serve as 352 consecutive DP-16QAM symbols in the first modulation symbol stream.

[0410] Every 16 codewords in the 32 codewords are mapped to 352 DP-16QAM symbols after bit interleaving. The 32 codewords are mapped to a total of 704 DP-16QAM symbols after bit interleaving, which are used as 704 consecutive DP-16QAM symbols in the first modulation symbol stream.

[0411] In this embodiment, when colored noise is present in actual transmission and the width is four DP-16QAM symbols, 32 error bits can be dispersed across multiple inner codes BCH (176, 160), and the number of error bits corresponding to each inner code is no more than two. Considering that the inner code BCH (176, 160) can correct two bits, the colored noise of 2-3 DP-16QAM symbol widths can be effectively corrected by the inner code. In addition, by using the designed bit interleaving and mapping method, the cascaded FEC scheme as a whole can resist burst errors greater than 1500 bits in length. That is, by using the designed bit interleaving and mapping method, the cascaded FEC scheme as a whole can effectively resist colored noise of up to four DP-16QAM symbol widths and can resist burst errors greater than 1500 bits in length. By using the designed bit interleaving and mapping method, the cascaded FEC scheme as a whole can effectively resist colored noise of up to four DP-16QAM symbol widths and can resist burst errors greater than 1500 bits in length.

[0412] Embodiment 2: The target bit set is represented as an array, n=32, m=16, K=160, L=8.

[0413] Based on the solution of Example 1, the 16 BCH (176, 160) codewords with a total of 2816 bits are represented by a first matrix H1 with 16 rows and 176 columns. The data obtained by bit interleaving is not represented by the third matrix H3 with 16 rows and 176 columns as shown in Example 1, but by an array A with a length of 2816 bits. The first matrix H1 is bit interleaved to obtain an array A with a length of 2816 bits. The interleaving correspondence is: for 0≤i<16,

[0414] in, represents a floor operation, a non-zero integer Δ is a row offset constraint factor, Δ is a multiple of 10 and -160 < Δ < 160, and a non-zero integer θ is a column offset constraint factor, θ satisfies -8 < θ < 8. In this embodiment, typical values ​​of the integer Δ are 10, 20, 30, 50, 60, 70, 90, 100, 110, 130, 140, and 150. A typical value of the integer θ is θ = 7, and another typical value is θ = 1.

[0415] By mapping every 8 consecutive bits in the first array A containing 2816 bits to a DP-16QAM symbol, 352 DP-16QAM symbols can be obtained as 352 consecutive DP-16QAM symbols in the first modulation symbol stream.

[0416] Every 16 codewords in the 32 codewords are mapped to 352 DP-16QAM symbols after bit interleaving. The 32 codewords are mapped to a total of 704 DP-16QAM symbols after bit interleaving, which are used as 704 consecutive DP-16QAM symbols in the first modulation symbol stream.

[0417] It should be noted that when the row offset constraint factor Δ and the column offset constraint factor θ in Example 1 are equal to the values ​​of Δ and θ in Example 2, respectively, the 32 codewords in Example 2 are bit interleaved and mapped to obtain the same 704 DP-16QAM symbols as in Example 2.

[0418] In this embodiment, the designed bit interleaving and mapping method is adopted, and the cascade FEC scheme as a whole can effectively resist colored noise with a width of up to 4 DP-16QAM symbols, and can resist burst errors with a length greater than 1500 bits.

[0419] Embodiment 3: The target bit set is represented by a bit matrix, n=32, m=8, K=160, L=8.

[0420] Based on the solution in Example 1, the 32 codewords after inner code encoding are not divided into two codeword sets as shown in Example 1, but are divided into four codeword sets, each of which contains m = 8 BCH (176, 160) codewords. Considering DP-16QAM modulation, every L = 8 bits is mapped to a DP-16QAM symbol. After bit interleaving and mapping, the eight BCH (176, 160) codewords in each codeword set can obtain 176 DP-16QAM symbols.

[0421] The above 8 BCH (176, 160) codewords with a total of 1408 bits are represented by the first matrix H1 with 8 rows and 176 columns, where each row of the first matrix H1 contains 176 bits of an inner code BCH (176, 160) codeword. The first matrix H1 is bit-interleaved to obtain the third matrix H3 with 8 rows and 176 columns. The interleaving correspondence is: for 0≤i<8,

[0422] It can be simplified to

[0423] in, represents a floor operation, a non-zero integer Δ is a row offset constraint factor, Δ is a multiple of 10 and -160 < Δ < 160, and a non-zero integer θ is a column offset constraint factor, θ satisfies -8 < θ < 8. In this embodiment, typical values ​​of the integer Δ are 10, 20, 30, 40, 50, 60, 70, 90, 100, 110, 120, 130, 140, and 150. A typical value of the integer θ is θ = 7, and another typical value is θ = 1.

[0424] The third matrix H3, with 8 rows and 176 columns, contains 8 bits per column. Each 8-bit column is mapped to a DP-16QAM symbol. Each third matrix H3 is mapped to 176 DP-16QAM symbols. The 176 DP-16QAM symbols obtained by mapping the 176 columns serve as 176 consecutive DP-16QAM symbols in the first modulation symbol stream.

[0425] Every 8 codewords in the above 32 codewords are mapped to 176 DP-16QAM symbols after bit interleaving. The 32 codewords are mapped to a total of 704 DP-16QAM symbols after bit interleaving, which are used as 704 consecutive DP-16QAM symbols in the first modulation symbol stream.

[0426] In this embodiment, the designed bit interleaving and mapping method is adopted, and the cascade FEC scheme as a whole can effectively resist colored noise with a width of up to 2 DP-16QAM symbols, and can resist burst errors with a length greater than 2000 bits.

[0427] Embodiment 4: The target bit set is represented as an array, n=32, m=8, K=160, L=8.

[0428] Based on the solution of Example 3, 8 BCH (176, 160) codewords with a total of 1408 bits are represented by a first matrix H1 with 8 rows and 176 columns. The data obtained after bit interleaving is not represented by the third matrix H3 with 8 rows and 176 columns as shown in Example 1, but by an array A with a length of 1408 bits. The first matrix H1 is bit interleaved to obtain an array A with a length of 1408 bits. The interleaving correspondence is: for 0≤i<8,

[0429] in, represents a floor operation, a non-zero integer Δ is a row offset constraint factor, Δ is a multiple of 10 and -160 < Δ < 160, and a non-zero integer θ is a column offset constraint factor, θ satisfies -8 < θ < 8. In this embodiment, typical values ​​of the integer Δ are 10, 20, 30, 40, 50, 60, 70, 90, 100, 110, 120, 130, 140, and 150. A typical value of the integer θ is θ = 7, and another typical value is θ = 1.

[0430] By mapping every 8 consecutive bits in the first array A containing 1408 bits to a DP-16QAM symbol, 176 DP-16QAM symbols can be obtained as 176 consecutive DP-16QAM symbols in the first modulation symbol stream.

[0431] Every 8 codewords in the above 32 codewords are mapped to 176 DP-16QAM symbols after bit interleaving. The 32 codewords are mapped to a total of 704 DP-16QAM symbols after bit interleaving.

[0432] It should be noted that when the row offset constraint factor Δ and the column offset constraint factor θ in Example 4 are equal to the values ​​of Δ and θ in Example 3, respectively, the 32 codewords in Example 4 are bit interleaved and mapped to obtain the same 704 DP-16QAM symbols as those in Example 3.

[0433] In this embodiment, the designed bit interleaving and mapping method is adopted, and the cascade FEC scheme as a whole can effectively resist colored noise with a width of up to 2 DP-16QAM symbols, and can resist burst errors with a length greater than 2000 bits.

[0434] Embodiment 5: The target bit set is represented by a bit matrix, n=32, m=32, K=160, L=8.

[0435] Based on the solution in Example 1, the 32 codewords after inner code encoding are not divided into two codeword sets as shown in Example 1. Instead, the 32 codewords are grouped as one codeword set, containing m = 32 BCH (176, 160) codewords. Considering DP-16QAM modulation, every L = 8 bits is mapped to a DP-16QAM symbol. After bit interleaving and mapping, the 32 BCH (176, 160) codewords can be converted into 704 DP-16QAM symbols.

[0436] The above 32 BCH (176, 160) codewords, totaling 5632 bits, are represented by a first matrix H1 with 32 rows and 176 columns, where each row of the first matrix H1 contains 176 bits of an inner code BCH (176, 160) codeword. The first matrix H1 is bit-interleaved to obtain a third matrix H3 with 32 rows and 176 columns. The interleaving correspondence is: for 0≤i<32,

[0437] in, represents a floor operation, a non-zero integer Δ is a row offset constraint factor, Δ is a multiple of 10 and -160 < Δ < 160, and a non-zero integer θ is a column offset constraint factor, θ satisfies -8 < θ < 8. In this embodiment, typical values ​​of the integer Δ are 20, 30, 50, 60, 70, 90, 100, 110, 130, and 140. A typical value of the integer θ is θ = 7, and another typical value is θ = 1.

[0438] The third matrix H3, with 32 rows and 176 columns, contains 32 bits per column. Each 32-bit column is mapped to four DP-16QAM symbols. After bit interleaving, the 32 codewords are mapped to a total of 704 DP-16QAM symbols, constituting 704 consecutive DP-16QAM symbols in the first modulation symbol stream.

[0439] A specific implementation method is that the first T = 1 DP-16QAM symbol of the 4 DP-16QAM symbols mapped in each column (that is, the 0th DP-16QAM symbol mapped in each column), and a total of 176 DP-16QAM symbols in 176 columns are used as the next 176 consecutive DP-16QAM symbols in the first modulation symbol stream; the next T = 1 DP-16QAM symbol of the 4 DP-16QAM symbols mapped in each column (that is, the 1st DP-16QAM symbol mapped in each column), and a total of 176 DP-16QAM symbols in 176 columns are used as the next 176 consecutive DP-16QAM symbols in the first modulation symbol stream; and so on, a total of 704 consecutive DP-16QAM symbols in the first modulation symbol stream can be obtained.

[0440] In this embodiment, the designed bit interleaving and mapping method is adopted, and the cascade FEC scheme as a whole can effectively resist colored noise with a width of up to 2 DP-16QAM symbols, and can resist burst errors with a length greater than 2000 bits.

[0441] Embodiment 6: The target bit set is represented by a bit matrix, 2 symbols are output continuously in each column, n=32, m=32, K=160, L=8.

[0442] Based on the scheme of Example 5, the 32 codewords are mapped into a total of 704 DP-16QAM symbols after bit interleaving, constituting 704 consecutive DP-16QAM symbols in the first modulation symbol stream. This embodiment provides another specific implementation method: the first two DP-16QAM symbols of the four DP-16QAM symbols mapped in each column (i.e., the 0th and 1st DP-16QAM symbols mapped in each column), and a total of 352 DP-16QAM symbols in 176 columns are used as the 352 consecutive DP-16QAM symbols in the first modulation symbol stream; the last two DP-16QAM symbols of the four DP-16QAM symbols mapped in each column (i.e., the 2nd and 3rd DP-16QAM symbols mapped in each column), and a total of 352 DP-16QAM symbols in 176 columns are used as the next 352 consecutive DP-16QAM symbols in the first modulation symbol stream; and finally, 704 consecutive DP-16QAM symbols in the first modulation symbol stream are obtained.

[0443] In this embodiment, the designed bit interleaving and mapping method is adopted, and the cascade FEC scheme as a whole can effectively resist colored noise with a width of up to 4 DP-16QAM symbols, and can resist burst errors with a length greater than 1500 bits.

[0444] Embodiment 7: The target bit set is represented by a bit matrix, 2 symbols are output continuously in each column, n=16, m=16, K=160, L=8.

[0445] The Physical Medium Attachment (PMA) sublayer of the transmitting end processing module processes data from multiple synchronous client lanes to generate n = 16 first data streams. These 16 first data streams are then fed into an inner code encoder for inner code encoding to generate 16 second data streams. The inner code uses the BCH (176, 160) scheme, meaning the codeword length is N = 176, the information bit length is K = 160, and the parity bit length is P = 16. The 160 information bits in each inner codeword come from 16 symbols of 16 different outer code Reed-Solomon (RS) codewords.

[0446] The 16 inner codewords described above are considered a codeword set, comprising m = 16 BCH (176, 160) codewords. Considering DP-16QAM modulation, every L = 8 bits are mapped to a DP-16QAM symbol. After bit interleaving and mapping, the 16 BCH (176, 160) codewords yield 352 DP-16QAM symbols.

[0447] The above 16 BCH (176, 160) codewords, totaling 2816 bits, are represented by a first matrix H1 with 16 rows and 176 columns, where each row of the first matrix H1 contains 176 bits of an inner code BCH (176, 160) codeword. The first matrix H1 is bit-interleaved to obtain a third matrix H3 with 16 rows and 176 columns, and its interleaving correspondence is: for 0≤i<16,

[0448] in, represents a floor operation, a non-zero integer Δ is a row offset constraint factor, Δ is a multiple of 10 and -160 < Δ < 160, and an integer θ is a column offset constraint factor, and the non-zero integer θ satisfies -8 < θ < 8. In this embodiment, typical values ​​of the integer Δ are 20, 30, 50, 60, 70, 90, 100, 110, 130, and 140. A typical value of the integer θ is θ = 7, and another typical value is θ = 1.

[0449] The third matrix H3 with 16 rows and 176 columns mentioned above contains 16 bits in each column. The 16 bits in each column are mapped to 2 DP-16QAM symbols. A specific implementation method is to map rows 0-7 in each column to one DP-16QAM symbol, and rows 8-15 to another DP-16QAM symbol. The 16 codewords are mapped to a total of 352 DP-16QAM symbols after bit interleaving, constituting 352 consecutive DP-16QAM symbols in the first modulation symbol stream. A specific implementation method is to use the 2 DP-16QAM symbols mapped in each column as 2 consecutive DP-16QAM symbols in the first modulation symbol stream, and the 352 DP-16QAM symbols mapped in 176 columns as 352 consecutive DP-16QAM symbols in the first modulation symbol stream.

[0450] It should be noted that the 2816-bit interleaved data obtained by bit interleaving of the above-mentioned first matrix H1 is represented by a third matrix H3 with 16 rows and 176 columns, and can also be represented by an array of length 2816 bits, as shown in Example 2 and Example 4. The specific implementation method is known to ordinary technicians in this field and will not be repeated here.

[0451] In this embodiment, the designed bit interleaving and mapping method is adopted, and the cascade FEC scheme as a whole can effectively resist colored noise with a width of up to 4 DP-16QAM symbols, and can resist burst errors with a length greater than 1500 bits.

[0452] It should be noted that the transmitting end processing module's operational flow can also be as shown in Figure 12(b), where the channel data streams, after being identified and locked, are directly sent to channel reordering without undergoing channel deskew. When the client-side interface is a dual-lane 400G interface, the RS symbols in any of channel data streams 0-15 and any of channel data streams 16-31 that are sent to the convolutional interleaving come from two different RS outer codewords. In this 2×400G interface scenario, the transmitting end processing module uses the operational flow shown in Figure 12(c) or Figure 12(d) without performing channel reordering. This still ensures that the 160 information bits in the inner codeword correspond to 16 RS symbols, originating from 16 different outer code RS codewords. This reduces the latency of the overall cascaded FEC scheme, but its ability to combat burst errors is somewhat weakened. Whether to perform channel deskew and channel reordering in the transmitting end processing module can be determined based on the actual transmission scenario.

[0453] Embodiment 8: The target bit set is represented by a bit matrix, 4 symbols in each column are output continuously, n=8, m=8, K=120, L=2.

[0454] The Physical Medium Attachment (PMA) sublayer of the transmitting end processing module processes data from multiple synchronous client lanes to produce n = 8 first data streams. These eight first data streams are then fed into an inner code encoder for inner code encoding to produce eight second data streams. The inner code uses the Hamming (128, 120) code, meaning the codeword length is N = 128, the information bit length is K = 120, and the parity bit length is P = 8. The 120 information bits in each inner codeword come from 12 symbols of 12 different outer code Reed-Solomon (RS) codewords.

[0455] The eight inner codewords described above are considered a codeword set, consisting of m = 8 Hamming (128, 120) codewords. Considering PAM4 modulation, every L = 2 bits are mapped to a PAM4 symbol. After bit interleaving and mapping, the eight Hamming (128, 120) codewords yield 512 PAM4 symbols.

[0456] The above 8 Hamming (128, 120) codewords with a total of 1024 bits are represented by the first matrix H1 with 8 rows and 128 columns, where each row of the first matrix H1 contains 128 bits of an inner code Hamming (128, 120) codeword. The first matrix H1 is bit-interleaved to obtain the third matrix H3 with 8 rows and 128 columns. The interleaving correspondence is: for 0≤i<8,

[0457] in, represents a floor operation, a non-zero integer Δ is a row offset constraint factor, Δ is a multiple of 10 and 0 < Δ < 120, and a non-zero integer θ is a column offset constraint factor, θ = 1. In this embodiment, typical values ​​of the integer Δ are 20, 30, 50, 60, 70, 90, and 100.

[0458] The third matrix H3 with 8 rows and 176 columns mentioned above contains 8 bits in each column. The 8 bits in each column are mapped to 4 PAM4 symbols. One specific implementation method is to map the 2 bits in rows 0-1 in each column to one PAM4 symbol, the 2 bits in rows 2-3 to another PAM4 symbol, the 2 bits in rows 4-5 to another PAM4 symbol, and the 2 bits in rows 6-7 to another PAM4 symbol. After bit interleaving, the 8 codewords are mapped to a total of 512 PAM4 symbols, constituting 512 consecutive PAM4 symbols in the first modulation symbol stream. One specific implementation method is to use the 4 PAM4 symbols mapped in each column as the 4 consecutive PAM4 symbols in the first modulation symbol stream, and the 512 PAM4 symbols mapped in 128 columns as the 512 consecutive PAM4 symbols in the first modulation symbol stream.

[0459] In this embodiment, the designed bit interleaving and mapping method is adopted, and the cascaded FEC scheme as a whole can effectively resist colored noise of up to 4 PAM4 symbol widths and can resist burst errors of length greater than 1200 bits.

[0460] Embodiment 9: The target bit set is represented by a bit matrix, 4 symbols in each column are output continuously, n=32, m=8, K=120, L=2.

[0461] The Physical Medium Attachment (PMA) sublayer of the transmitting end processing module processes the data from multiple synchronous client lanes to obtain n=32 first data streams. Figure 11 is a schematic diagram of the inner code encoding and interleaved modulation mapping of the data stream in an embodiment of the present application. As shown in Figure 11, the 32 first data streams are respectively sent to the inner code encoder for inner code encoding to obtain 32 second data streams. The inner code encoding adopts Hamming code Hamming (128, 120), that is, the code word bit length N=128, the information bit length K=120, and the check bit length P=8. The 120 information bits of each inner code codeword come from 12 symbols of 12 different outer code RS codewords. The 32 second data streams are divided into 4 second data stream groups, each group contains 8 second data streams, and each second data stream group obtains a modulation symbol stream after interleaving modulation, resulting in a total of 4 modulation mapping streams. The 4 modulation mapping data streams will be transmitted through 4 different channels. The 4 different channels shown can be 4 different wavelengths, or 4 different optical fibers, etc.

[0462] A Hamming (128, 120) codeword is obtained from each of the above second data streams. A total of 8 Hamming (128, 120) codewords with a total of 1024 bits are represented by a first matrix H1 with 8 rows and 128 columns, where each row of the first matrix H1 includes 128 bits of an inner code Hamming (128, 120) codeword. The first matrix H1 is bit-interleaved to obtain a third matrix H3 with 8 rows and 128 columns. The interleaving correspondence is: for 0≤i<8,

[0463] in, represents a floor operation, a non-zero integer Δ is a row offset constraint factor, Δ is a multiple of 10 and 0 < Δ < 120, and a non-zero integer θ is a column offset constraint factor, θ = 1. In this embodiment, typical values ​​of the integer Δ are 10, 20, 30, 40, 50, 60, 70, 80, 90, 100, and 110.

[0464] Another interleaving mapping relationship is:

[0465] The third matrix H3, with 8 rows and 176 columns, contains 8 bits per column. Each 8-bit column is mapped to 4 PAM4 symbols. In one specific implementation, the 2 bits in rows 0-1 of each column are mapped to one PAM4 symbol, the 2 bits in rows 2-3 are mapped to another PAM4 symbol, the 2 bits in rows 4-5 are mapped to another PAM4 symbol, and the 2 bits in rows 6-7 are mapped to yet another PAM4 symbol. After bit interleaving, the 8 codewords are mapped to a total of 512 PAM4 symbols, constituting 512 consecutive PAM4 symbols in the first modulation symbol stream.

[0466] In this embodiment, the designed bit interleaving and mapping method is adopted, and the cascaded FEC scheme as a whole can effectively resist colored noise of up to 8 PAM4 symbol widths on each channel, and can resist burst errors with a length greater than 1100 bits.

[0467] It should be noted that the transmitting end processing module can also operate as shown in Figure 12(b). After the channel data stream has been identified and locked, it can be directly sent to the channel reordering process without undergoing channel deskew. This reduces the latency of the overall cascaded FEC solution, but its ability to combat burst errors is somewhat weakened. Whether to perform channel deskew and channel reordering in the transmitting end processing module can be determined based on the actual transmission scenario.

[0468] Example 10: The target bit set is represented by a bit matrix, n=32, m=8, K=160, L=8, L r =4,L c =2.

[0469] The Physical Medium Attachment (PMA) sublayer of the transmitting end processing module processes data from multiple synchronous client lanes to produce n = 32 first data streams. These 32 first data streams are then fed into an inner code encoder for inner code encoding to produce 32 second data streams. The inner code uses the BCH (176, 160) scheme, meaning the codeword length is N = 176, the information bit length is K = 160, and the parity bit length is P = 16. The 160 information bits in each inner codeword come from 16 symbols of 16 different outer code Reed-Solomon (RS) codewords.

[0470] The 32 codewords after inner code encoding are divided into four codeword sets, each containing m = 8 BCH (176, 160) codewords. Considering DP-16QAM modulation, every L = 8 bits are mapped to a DP-16QAM symbol. After bit interleaving and mapping, the eight BCH (176, 160) codewords in each codeword set yield 176 DP-16QAM symbols.

[0471] The above 8 BCH (176, 160) codewords with a total of 1408 bits are represented by the first matrix H1 with 8 rows and 176 columns, where each row of the first matrix H1 contains 176 bits of an inner code BCH (176, 160) codeword. The first matrix H1 is bit-interleaved to obtain the third matrix H3 with 8 rows and 176 columns. The interleaving correspondence is: for 0≤i<8,

[0472] in, The non-zero integer Δ represents a row offset constraint factor, where Δ is a multiple of 10 and 0 < Δ < 160. The integer represents a column offset constraint factor. In this embodiment, typical values ​​of the integer Δ are 10, 20, 30, 40, 50, 60, 70, 90, 100, 110, 120, 130, 140, and 150.

[0473] The third matrix H3 with 8 rows and 176 columns has 8 bits per column. r =4,L c = 2. The two columns in every four rows, totaling 8 bits, are mapped to one DP-16QAM symbol. The two modulation symbols obtained by mapping every two columns in the third matrix H3 serve as two consecutive modulation symbols in the first modulation symbol stream. The 176 modulation symbols obtained by mapping the 176 columns serve as 176 consecutive modulation symbols in the first modulation symbol stream, serving as 176 consecutive DP-16QAM symbols in the first modulation symbol stream.

[0474] Every 8 codewords in the above 32 codewords are mapped to 176 DP-16QAM symbols after bit interleaving. The 32 codewords are mapped to a total of 704 DP-16QAM symbols after bit interleaving, which are used as 704 consecutive DP-16QAM symbols in the first modulation symbol stream.

[0475] Example 11: The target bit set is represented by a bit matrix, n=32, m=16, K=160, L=8, L r =4,L c =2.

[0476] The Physical Medium Attachment (PMA) sublayer of the transmitting end processing module processes data from multiple synchronous client lanes to produce n = 32 first data streams. These 32 first data streams are then fed into an inner code encoder for inner code encoding to produce 32 second data streams. The inner code uses the BCH (176, 160) scheme, meaning the codeword length is N = 176, the information bit length is K = 160, and the parity bit length is P = 16. The 160 information bits in each inner codeword come from 16 symbols of 16 different outer code Reed-Solomon (RS) codewords.

[0477] The 32 codewords after inner code encoding are divided into two codeword sets, each containing m = 16 BCH (176, 160) codewords. Considering DP-16QAM modulation, every L = 8 bits is mapped to a DP-16QAM symbol. After bit interleaving and mapping, the 16 BCH (176, 160) codewords in each codeword set can obtain 352 DP-16QAM symbols.

[0478] The above 16 BCH (176, 160) codewords, totaling 1408 bits, are represented by a first matrix H1 with 16 rows and 176 columns, where each row of the first matrix H1 contains 176 bits of an inner code BCH (176, 160) codeword. The first matrix H1 is bit-interleaved to obtain a third matrix H3 with 16 rows and 176 columns. The interleaving correspondence is: for 0≤i<16,

[0479] in, The non-zero integer Δ represents a row offset constraint factor, where Δ is a multiple of 10 and 0 < Δ < 160. The integer represents a column offset constraint factor. In this embodiment, typical values ​​of the integer Δ are 10, 20, 30, 40, 50, 60, 70, 90, 100, 110, 120, 130, 140, and 150.

[0480] The third matrix H3 with 16 rows and 176 columns has 16 bits per column. r =4,L c = 2. 8 bits in 2 columns in every 4 rows are mapped to one DP-16QAM symbol. 4 DP-16QAM symbols are obtained by mapping every 2 columns in the third matrix H3.

[0481] The first two DP-16QAM symbols of the four DP-16QAM symbols mapped from every two columns in the third matrix H3 (i.e., the 0th and 1st DP-16QAM symbols mapped from each column), and a total of 176 DP-16QAM symbols in 176 columns are used as the 176 consecutive DP-16QAM symbols in the first modulation symbol stream; the last two DP-16QAM symbols of the four DP-16QAM symbols mapped from every two columns (i.e., the 2nd and 3rd DP-16QAM symbols mapped from every two columns), and a total of 176 DP-16QAM symbols in 176 columns are used as the next 176 consecutive DP-16QAM symbols in the first modulation symbol stream; finally, 352 consecutive DP-16QAM symbols in the first modulation symbol stream are obtained.

[0482] Every 16 codewords in the 32 codewords are mapped to 352 DP-16QAM symbols after bit interleaving. The 32 codewords are mapped to a total of 704 DP-16QAM symbols after bit interleaving, which are used as 704 consecutive DP-16QAM symbols in the first modulation symbol stream.

[0483] Embodiment 12: The target bit set is represented by a bit matrix, n=32, m=16, K=110, L=8.

[0484] The Physical Medium Attachment (PMA) sublayer of the transmitting end processing module processes data from multiple synchronous client lanes to produce n = 32 first data streams. These 32 first data streams are then fed into an inner code encoder for inner code encoding to produce 32 second data streams. The inner code uses the BCH (126, 110) scheme, meaning the codeword length is N = 126, the information bit length is K = 110, and the parity bit length is P = 16. The 110 information bits in each inner codeword come from 11 symbols of 11 different outer code Reed-Solomon (RS) codewords.

[0485] The 32 codewords after the inner code encoding are divided into h = 2 codeword sets, each containing m = 16 BCH (126, 110) codewords. Considering DP-16QAM modulation, every L = 8 bits are mapped to a DP-16QAM symbol. After bit interleaving and mapping, the 16 BCH (126, 110) codewords in each codeword set yield 252 DP-16QAM symbols.

[0486] The above 16 BCH (126, 110) codewords, totaling 2016 bits, are represented by a first matrix H1 with 16 rows and 126 columns, where each row of the first matrix H1 contains 126 bits of an inner code BCH (126, 110) codeword. The first matrix H1 is bit-interleaved to obtain a third matrix H3 with 16 rows and 126 columns, and its interleaving correspondence is: for 0≤i<16,

[0487] in, represents a floor operation, a non-zero integer Δ is a row offset constraint factor, Δ is a multiple of 10 and -110 < Δ < 110, and a non-zero integer θ is a column offset constraint factor, and the non-zero integer θ satisfies -8 < θ < 8. In this embodiment, typical values ​​of the integer Δ are 10, 20, 30, 50, 60, 70, 90, and 100. A typical value of the integer θ is θ = 7, and another typical value is θ = 1.

[0488] The third matrix H3 with 16 rows and 126 columns mentioned above contains 16 bits in each column. Every 8 bits of the 16 bits are mapped to a DP-16QAM symbol. Each column is mapped to 2 modulation symbols. A specific implementation method is to map rows 0-7 in each column to a DP-16QAM symbol, and rows 8-15 to another DP-16QAM symbol. Each third matrix H3 is mapped to 252 DP-16QAM symbols. The 2 DP-16QAM symbols mapped in each column serve as 2 consecutive DP-16QAM symbols in the first modulation symbol stream, and the 252 DP-16QAM symbols mapped in 176 columns serve as 252 consecutive DP-16QAM symbols in the first modulation symbol stream.

[0489] Every 16 of the 32 codewords are mapped to 252 DP-16QAM symbols after bit interleaving. The 32 codewords are mapped to a total of 504 DP-16QAM symbols after bit interleaving, which are used as 504 consecutive DP-16QAM symbols in the first modulation symbol stream.

[0490] In this embodiment, when colored noise is present during actual transmission and the width is four DP-16QAM symbols, 32 error bits can be dispersed across multiple inner codes BCH (126, 110), and the number of error bits corresponding to each inner code is no more than two. Considering that the inner code BCH (126, 110) can correct two bits, the colored noise of 2-3 DP-16QAM symbol widths can be effectively corrected by the inner code. In addition, by using the designed bit interleaving and mapping method, the cascaded FEC scheme as a whole can resist burst errors greater than 1200 bits in length. In other words, by using the designed bit interleaving and mapping method, the cascaded FEC scheme as a whole can effectively resist colored noise of up to four DP-16QAM symbol widths and can resist burst errors greater than 1200 bits in length. By using the designed bit interleaving and mapping method, the cascaded FEC scheme as a whole can effectively resist colored noise of up to four DP-16QAM symbol widths and can resist burst errors greater than 1200 bits in length.

[0491] Example 13: The target bit set is represented as an array, n=32, m=16, K=110, L=8.

[0492] Based on the solution of Example 12, the 16 BCH (126, 110) codewords with a total of 2016 bits are represented by a first matrix H1 with 16 rows and 126 columns. The data obtained after bit interleaving is not represented by the third matrix H3 with 16 rows and 126 columns as shown in Example 1, but by an array A with a length of 2016 bits. The first matrix H1 is bit interleaved to obtain an array A with a length of 2016 bits. The interleaving correspondence is: for 0≤i<16,

[0493] in, represents a floor operation, a non-zero integer Δ is a row offset constraint factor, Δ is a multiple of 10 and -110<Δ<110, a non-zero integer θ is a column offset constraint factor, and the integer θ satisfies -8<θ<8. In this embodiment, typical values ​​of the integer Δ are 10, 20, 30, 50, 60, 70, 90, and 100. A typical value of the integer θ is θ=7, and another typical value is θ=1. In particular, for 0≤i<16, we have

[0494] By mapping every 8 consecutive bits in the first array A containing 2016 bits to a DP-16QAM symbol, 252 DP-16QAM symbols can be obtained as 252 consecutive DP-16QAM symbols in the first modulation symbol stream.

[0495] Every 16 of the 32 codewords are mapped to 252 DP-16QAM symbols after bit interleaving. The 32 codewords are mapped to a total of 504 DP-16QAM symbols after bit interleaving, which are used as 504 consecutive DP-16QAM symbols in the first modulation symbol stream.

[0496] It should be noted that when the row offset constraint factor Δ and the column offset constraint factor θ in Example 11 are equal to the values ​​of Δ and θ in Example 12, respectively, the 32 codewords in Example 11 are bit interleaved and mapped to obtain the same 504 DP-16QAM symbols as those in Example 12.

[0497] In this embodiment, the designed bit interleaving and mapping method is adopted, and the cascade FEC scheme as a whole can effectively resist colored noise with a width of up to 4 DP-16QAM symbols, and can resist burst errors with a length greater than 1200 bits.

[0498] Example 14: The target bit set is represented by a bit matrix, n=32, m=8, K=110, L=8, L r =4,L c =2.

[0499] The Physical Medium Attachment (PMA) sublayer of the transmitting end processing module processes data from multiple synchronous client lanes to produce n = 32 first data streams. These 32 first data streams are then fed into an inner code encoder for inner code encoding to produce 32 second data streams. The inner code uses the BCH (126, 110) scheme, meaning the codeword length is N = 126, the information bit length is K = 110, and the parity bit length is P = 16. The 110 information bits in each inner codeword come from 11 symbols of 11 different outer code Reed-Solomon (RS) codewords.

[0500] The 32 codewords after inner code encoding are divided into four codeword sets, each containing m = 8 BCH (126, 110) codewords. Considering DP-16QAM modulation, every L = 8 bits are mapped to a DP-16QAM symbol. After bit interleaving and mapping, the eight BCH (126, 110) codewords in each codeword set yield 126 DP-16QAM symbols.

[0501] The above 8 BCH (126, 110) codewords with a total of 1008 bits are represented by the first matrix H1 with 8 rows and 126 columns, where each row of the first matrix H1 contains 126 bits of an inner code BCH (126, 110) codeword. The first matrix H1 is bit-interleaved to obtain the third matrix H3 with 8 rows and 126 columns. The interleaving correspondence is: for 0≤i<8,

[0502] in, The non-zero integer Δ represents a round-down operation. The non-zero integer Δ represents a row offset constraint factor, where Δ is a multiple of 10 and -100 < Δ < 100. The non-zero integer Δ represents a column offset constraint factor. In this embodiment, typical values ​​of the integer Δ are 10, 20, 30, 40, 50, 60, 70, 90, and 100.

[0503] The third matrix H3 with 8 rows and 126 columns has 8 bits per column. r =4,L c = 2. The two columns in every four rows, totaling 8 bits, are mapped to one DP-16QAM symbol. The two modulation symbols obtained by mapping every two columns in the third matrix H3 serve as two consecutive modulation symbols in the first modulation symbol stream. The 126 modulation symbols obtained by mapping the 126 columns serve as 126 consecutive modulation symbols in the first modulation symbol stream, serving as 126 consecutive DP-16QAM symbols in the first modulation symbol stream.

[0504] Every 8 codewords in the above 32 codewords are mapped to 126 DP-16QAM symbols after bit interleaving. The 32 codewords are mapped to a total of 504 DP-16QAM symbols after bit interleaving, which are used as 504 consecutive DP-16QAM symbols in the first modulation symbol stream.

[0505] Embodiment 15: The target bit set is represented by a bit matrix, n=16, m=16, K=120, L=8.

[0506] The Physical Medium Attachment (PMA) sublayer of the transmitting end processing module processes data from multiple synchronous client lanes to generate n = 16 first data streams. These 16 first data streams are then fed into an inner code encoder for inner code encoding to generate 16 second data streams. The inner code uses the BCH (136, 120) scheme, meaning the codeword length is N = 136, the information bit length is K = 120, and the parity bit length is P = 16. The 120 information bits in each inner codeword come from 12 symbols of 12 different outer code Reed-Solomon (RS) codewords.

[0507] The 16 codewords after the inner code encoding described above are considered as h = 1 codeword sets, which contain m = 16 BCH (136, 120) codewords. Considering DP-16QAM modulation, every L = 8 bits are mapped to a DP-16QAM symbol. After bit interleaving and mapping, the 16 BCH (136, 120) codewords in each codeword set can obtain 272 DP-16QAM symbols.

[0508] The above 16 BCH (136, 120) codewords, totaling 2176 bits, are represented by a first matrix H1 with 16 rows and 136 columns, where each row of the first matrix H1 contains 136 bits of an inner code BCH (136, 120) codeword. The first matrix H1 is bit-interleaved to obtain a third matrix H3 with 16 rows and 136 columns. The interleaving correspondence is: for 0≤i<16,

[0509] in, represents a floor operation, a non-zero integer Δ is a row offset constraint factor, Δ is a multiple of 10 and -120 < Δ < 120, and a non-zero integer θ is a column offset constraint factor, and the non-zero integer θ satisfies -8 < θ < 8. In this embodiment, typical values ​​of the integer Δ are 10, 20, 30, 50, 60, 70, 90, 100, and 110. A typical value of the integer θ is θ = 7, and another typical value is θ = 1.

[0510] The third matrix H3 with 16 rows and 136 columns mentioned above contains 16 bits in each column. Every 8 bits of the 16 bits are mapped to a DP-16QAM symbol. Each column is mapped to 2 modulation symbols. A specific implementation method is to map rows 0-7 in each column to a DP-16QAM symbol, and rows 8-15 to another DP-16QAM symbol. Each third matrix H3 is mapped to 272 DP-16QAM symbols. The 2 DP-16QAM symbols mapped to each column serve as 2 consecutive DP-16QAM symbols in the first modulation symbol stream, and the 272 DP-16QAM symbols mapped to the 136 columns serve as 272 consecutive DP-16QAM symbols in the first modulation symbol stream.

[0511] In this embodiment, when colored noise is present during actual transmission and the width is four DP-16QAM symbols, 32 error bits can be dispersed across multiple inner codes BCH (136, 120), and the number of error bits corresponding to each inner code is no more than two. Considering that the inner code BCH (136, 120) can correct two bits, the colored noise of 2-3 DP-16QAM symbol widths can be effectively corrected by the inner code. In addition, by using the designed bit interleaving and mapping method, the cascaded FEC scheme as a whole can resist burst errors greater than 1200 bits in length. In other words, by using the designed bit interleaving and mapping method, the cascaded FEC scheme as a whole can effectively resist colored noise of up to four DP-16QAM symbol widths and can resist burst errors greater than 1200 bits in length. By using the designed bit interleaving and mapping method, the cascaded FEC scheme as a whole can effectively resist colored noise of up to four DP-16QAM symbol widths and can resist burst errors greater than 1200 bits in length.

[0512] Example 16: The target bit set is represented as an array, n=16, m=16, K=120, L=8.

[0513] Based on the scheme of Example 15, the 16 BCH (136, 120) codewords with a total of 2176 bits are represented by a first matrix H1 with 16 rows and 136 columns. The data obtained after bit interleaving is not represented by the third matrix H3 with 16 rows and 136 columns as shown in Example 1, but by an array A with a length of 2176 bits. The first matrix H1 is bit interleaved to obtain an array A with a length of 2176 bits. The interleaving correspondence is: for 0≤i<16,

[0514] in, represents a floor operation, a non-zero integer Δ is a row offset constraint factor, Δ is a multiple of 10 and -120<Δ<120, a non-zero integer θ is a column offset constraint factor, and the integer θ satisfies -8<θ<8. In this embodiment, typical values ​​of the integer Δ are 10, 20, 30, 50, 60, 70, 90, 100, and 110. A typical value of the integer θ is θ=7, and another typical value is θ=1. In particular, for 0≤i<16, we have

[0515] By mapping every 8 consecutive bits in the first array A containing 2176 bits to a DP-16QAM symbol, 272 DP-16QAM symbols can be obtained as 272 consecutive DP-16QAM symbols in the first modulation symbol stream.

[0516] In this embodiment, the designed bit interleaving and mapping method is adopted, and the cascade FEC scheme as a whole can effectively resist colored noise with a width of up to 4 DP-16QAM symbols, and can resist burst errors with a length greater than 1200 bits.

[0517] Example 17: The target bit set is represented by a bit matrix, n=16, m=8, K=120, L=8, L r =4,L c =2.

[0518] The Physical Medium Attachment (PMA) sublayer of the transmitting end processing module processes data from multiple synchronous client lanes to generate n = 16 first data streams. These 16 first data streams are then fed into an inner code encoder for inner code encoding to generate 16 second data streams. The inner code uses the BCH (136, 120) scheme, meaning the codeword length is N = 136, the information bit length is K = 120, and the parity bit length is P = 16. The 120 information bits in each inner codeword come from 12 symbols of 12 different outer code Reed-Solomon (RS) codewords.

[0519] The 16 codewords after inner code encoding are divided into two codeword sets, each containing m = 8 BCH (126, 110) codewords. Considering DP-16QAM modulation, every L = 8 bits are mapped to a DP-16QAM symbol. After bit interleaving and mapping, the eight BCH (136, 120) codewords in each codeword set yield 136 DP-16QAM symbols.

[0520] The above 8 BCH (136, 120) codewords with a total of 1088 bits are represented by the first matrix H1 with 8 rows and 136 columns, where each row of the first matrix H1 contains 136 bits of an inner code BCH (136, 120) codeword. The first matrix H1 is bit-interleaved to obtain the third matrix H3 with 8 rows and 136 columns. The interleaving correspondence is: for 0≤i<8,

[0521] in, The non-zero integer Δ represents a row offset constraint factor, Δ is a multiple of 10 and 0 < Δ < 120, and the integer represents a column offset constraint factor. In this embodiment, typical values ​​of the integer Δ are 10, 20, 30, 40, 50, 60, 70, 90, 100, and 110.

[0522] The third matrix H3 with 8 rows and 136 columns has 8 bits per column. r =4,L c = 2. The two columns in every four rows, totaling 8 bits, are mapped to one DP-16QAM symbol. The two modulation symbols obtained by mapping every two columns in the third matrix H3 serve as two consecutive modulation symbols in the first modulation symbol stream. The 136 modulation symbols obtained by mapping the 136 columns serve as 136 consecutive modulation symbols in the first modulation symbol stream, serving as 136 consecutive DP-16QAM symbols in the first modulation symbol stream.

[0523] Every 8 codewords in the above 16 codewords are mapped to 136 DP-16QAM symbols after bit interleaving. After bit interleaving, the 16 codewords are mapped to a total of 272 DP-16QAM symbols, which are used as 272 consecutive DP-16QAM symbols in the first modulation symbol stream.

[0524] Example 18: The target bit set is represented by a bit matrix, n=12, m=12, K=160, L=8, L r =4,L c =2.

[0525] The Physical Medium Attachment (PMA) sublayer of the transmitting end processing module processes data from multiple synchronous client lanes to produce n = 12 first data streams. These 12 first data streams are then fed into an inner code encoder for inner code encoding to produce 12 second data streams. The inner code uses the BCH (176, 160) scheme, meaning the codeword length is N = 176, the information bit length is K = 160, and the parity bit length is P = 16. The 160 information bits in each inner codeword come from 16 symbols of 16 different outer code Reed-Solomon (RS) codewords.

[0526] The 12 codewords after inner code encoding are considered a codeword set, which contains m = 12 BCH (176, 160) codewords. Considering DP-16QAM modulation, every L = 8 bits are mapped to a DP-16QAM symbol. After bit interleaving and mapping, the 12 BCH (176, 160) codewords in each codeword set can obtain 264 DP-16QAM symbols.

[0527] The above 12 BCH (176, 160) codewords, totaling 2112 bits, are represented by a first matrix H1 with 12 rows and 176 columns, where each row of the first matrix H1 contains 176 bits of an inner code BCH (176, 160) codeword. The first matrix H1 is bit-interleaved to obtain a third matrix H3 with 12 rows and 176 columns, and its interleaving correspondence is: for 0≤i<12,

[0528] in, The non-zero integer Δ represents a row offset constraint factor, where Δ is a multiple of 10 and 0 < Δ < 160. The integer Δ represents a column offset constraint factor. In this embodiment, typical values ​​of the integer Δ are 10, 20, 30, 40, 50, 60, 70, 90, 100, 110, 120, 130, 140, and 150.

[0529] The third matrix H3 with 12 rows and 176 columns has 8 bits per column. r=4,L c = 2. The two columns in every four rows, totaling 8 bits, are mapped to one DP-16QAM symbol. The three modulation symbols obtained by mapping every two columns in the third matrix H3 serve as three consecutive modulation symbols in the first modulation symbol stream, and the 264 modulation symbols obtained by mapping the 176 columns serve as 264 consecutive DP-16QAM modulation symbols in the first modulation symbol stream.

[0530] It should be noted that the above embodiments are all about introducing the operation steps in the data processing method shown in Figure 3. In actual applications, the operations performed by the transmitting end processing module 02 shown in Figure 2 include but are not limited to the data processing method shown in Figure 3. The following describes other operations performed by the transmitting end processing module 02 in conjunction with some specific implementation methods.

[0531] Implementation 1: Operational process of applying the transmitting end processing module to the 1×800G interface scenario.

[0532] The Physical Medium Attachment (PMA) sublayer of the transmitting end processing module performs first data processing on data from multiple synchronous client lanes to obtain n first data streams, where n is an integer greater than 1. This first data processing may include alignment lock, lane de-skew, lane reordering, or concatenated interleaving. This embodiment provides specific details of the first data processing.

[0533] Figure 12(a) is a schematic diagram of the first operational flow of the transmitting end processing module in an embodiment of the present application. As shown in Figure 12(a), the Physical Medium Attachment (PMA) sublayer of the transmitting end processing module processes data from multiple synchronized client lanes to obtain multiple channel data streams encoded with an outer code. Alignment markers are then used to perform alignment lock and lane de-skew to obtain aligned multiple channel data streams. Lane reordering is then performed on the multiple channel data according to the alignment markers, so that the multiple channel data can be arranged in a specified order. The reordered channel data streams are then sent to a cascaded interleaver to scramble the data order, resulting in n first data streams, which are then sent to an inner code encoder for inner code encoding. The inner code encoded data streams are subjected to the designed bit interleaving and mapping to obtain modulation symbols, which are then processed and sent to the channel transmission medium for transmission. The data processing may include polarization distribution or DSP framing, etc. Here, n is a positive integer greater than 1.

[0534] It should be noted that the lane de-skew processing and lane reordering in Figure 12(a) are both optional. Figure 12(b) is a schematic diagram of the second operation flow of the transmitting end processing module in the embodiment of the present application. As shown in Figure 12(b), the channel data stream after the identification lock (alignment lock) does not undergo channel de-skew processing and is directly sent to the channel reordering. Figure 12(c) is a schematic diagram of the third operation flow of the transmitting end processing module in the embodiment of the present application. As shown in Figure 12(c), the channel data stream after the identification lock undergoes channel de-skew processing and is directly sent to the cascade interleaving without undergoing channel reordering. Figure 12(d) is a schematic diagram of the fourth operation flow of the transmitting end processing module in the embodiment of the present application. As shown in Figure 12(d), the channel data stream after the identification lock does not undergo channel de-skew processing or channel reordering and is directly sent to the cascade interleaving. It should be noted that, as shown in the transmitting end processing module flow chart in Figures 12(b) and 12(d), the channel data streams after alignment lock do not undergo channel deskew processing. In this case, the data in each channel data stream is required to be aligned based on the outer code. More specifically, taking KP4 as an example, the offset between any two channel data streams is a multiple of 10, which means that the data in the channel data streams is aligned based on the KP4RS symbol.

[0535] Figure 13 is a schematic diagram of a 1×800G interface scenario in an embodiment of the present application. As shown in Figure 13, the transmitting device uses a schematic diagram of 32 physical coding sublayer (PCS) channel data streams of the 1×800G interface. The transmitting device performs KP4RS (544, 514) code encoding on the 1-way 800GbE service data stream to be transmitted to obtain 32 PCS lane data streams. In PCS lane data streams 0-15, each data stream is spaced 68 symbols apart, for a total of 1088 symbols, which includes 2 RS code words. The two adjacent symbols in each PCS lane data stream come from different RS code words, and the two symbols at the same position of two adjacent PCS lane data streams come from different RS code words. Similarly, in PCS lane data streams 16-31, each data stream is spaced 68 symbols apart, for a total of 1088 symbols, which includes 2 RS code words. The two adjacent symbols in each PCS channel data stream come from different RS codewords, and the two symbols at the same position in two adjacent PCS channel data streams come from different RS codewords. After being processed by the PMA, the 32 PCS channel data streams are sent to the transmitting end processing module through the connection unit interface 800GAUI-8.

[0536] Based on the data processing diagram of the transmitting end processing module shown in Figure 12(a), the transmitting end processing module uses the known alignment markers of the PCS lanes to perform alignment lock on the channel data streams. The known alignment markers for each of the 32 lanes are different (see the Ethernet Technology Consortium 800G Specification). The transmitting end processing module then performs lane de-skew processing on the 32 channel data streams to obtain 32 aligned channel data streams. Lane reordering is then performed on the 32 channel data streams based on the alignment markers, so that the 32 channel data are arranged in a specified order. One order is to sort the channel data streams from top to bottom, from 0 to 31, as shown in Figure 13. The 32 reordered PCS channel data streams are then sent to a cascaded interleaver to shuffle the data order, resulting in n first data streams. These are then sent to the inner code encoder for inner code encoding. After the n second data streams are encoded by the inner code and subjected to the designed bit interleaving and mapping, they are processed and sent to the channel transmission medium for transmission. It should be noted that the value of n here can be equal to 32 or 16.

[0537] It should be noted that the transmitting processing module can also operate as shown in Figure 12(b). After the channel data stream has been identified and locked, it can be directly sent to the channel reordering process without undergoing channel deskew. This reduces the latency of the overall cascaded FEC solution, but its ability to combat burst errors is somewhat weakened. Whether to perform channel deskew in the transmitting processing module can be determined based on the actual transmission scenario.

[0538] Implementation 2: Operational flow of the transmitting end processing module applied to a 2×400G interface scenario.

[0539] Figure 14 is a schematic diagram of a 2×400G interface scenario in an embodiment of the present application. As shown in Figure 14, the transmitting device is a schematic diagram of 32 PCS channel data streams using a 2×400G interface. The transmitting device performs KP4RS (544, 514) outer code encoding on the two 400GbE service data streams to be transmitted to obtain two channels of 32 PCS channel data streams in total, each of which includes 16 PCS channel data streams. Each data stream in PCS channel data streams 0-15 or PCS channel data streams 16-31 is separated by 68 symbols, for a total of 1088 symbols, which includes 2 RS code words. The two adjacent symbols in each PCS channel data stream come from different RS code words, and the two symbols at the same position of the two adjacent PCS channel data streams come from different RS code words. After being processed by the PMA, the 32 PCS channel data streams are sent to the transmitting processing module through the connection unit interface 2×400GAUI-4.

[0540] Based on the data processing diagram of the transmitting end processing module shown in Figure 12(a), the transmitting end processing module uses the known alignment markers of PCS lanes 0-15 or PCS lanes 16-31 to perform alignment lock on the 16-lane data streams. Here, PCS lanes 0-15 can be considered to be PCS lanes 0-15 in 400G lane 0, and PCS lanes 16-31 can be considered to be PCS lanes 0-15 in 400G lane 1. The known alignment markers of the 16 lanes in 400G lane 0 are the same as the known alignment markers of the 16 lanes in 400G lane 1. The transmitting end processing module then performs lane de-skew processing on the 32-lane data streams to obtain aligned 32-lane data streams. Lane reordering is then performed on the 16 lanes of data based on the alignment markers of PCS lanes 0-15 or PCS lanes 16-31, ensuring that the 16 lanes of data are arranged in the specified order. Finally, the 32 lanes of data are arranged in the specified order. One order is to sort the channel data streams from top to bottom, from 0 to 31, as in Figure 14. The 32 reordered PCS channel data streams are then sent to a cascaded interleaver for data decompression, resulting in n first data streams. These are then sent to an inner code encoder for inner code encoding. The n second data streams undergoing inner code encoding undergo the designed bit interleaving and mapping, data processing, and transmission onto the channel transmission medium. It should be noted that n can be either 32 or 16.

[0541] It should be noted that the operating flow of the transmitting processing module can also be as shown in Figure 12(b), where the channel data stream after identification lock is sent directly to the channel reordering without channel de-skew processing. Furthermore, considering that the client-side interface is a dual-channel 400G, the RS symbols in any of the channel data streams 0-15 and the RS symbols in any of the channel data streams 16-31 sent to the convolutional interleaving come from two different RS outer codewords. In this 2×400G interface scenario, the transmitting processing module can also adopt the operating flow shown in Figure 12(c) or Figure 12(d) without performing the channel reordering operation. In this case, the latency of the overall cascaded FEC solution can be reduced, but its ability to resist burst errors will be weakened. Whether to perform channel de-skew processing and channel reordering in the transmitting processing module can be determined based on the actual transmission scenario.

[0542] Implementation 3: Operational process of applying the transmitting end processing module to another 1×800G interface scenario.

[0543] Figure 15 is another schematic diagram of a 1×800G interface scenario in an embodiment of the present application. As shown in Figure 15, the transmitting device is a schematic diagram of eight channel data streams using a 1×800G interface. The transmitting device performs KP4RS (544, 514) outer code encoding on one 800GbE service data stream to be transmitted to obtain eight channel data streams. Each data stream in channel data streams 0-8 is separated by 136 symbols, totaling 1088 symbols, which contains two RS codewords. The two adjacent symbols in each channel data stream come from different RS codewords, and the two symbols at the same position in two adjacent channel data streams come from different RS codewords. After PMA processing, the eight channel data streams are sent to the transmitting processing module via the connection unit interface 800GAUI-8. It should be noted that in some specific implementations, the above eight channel data streams are referred to as eight PCS channel data streams; in other specific implementations, the above eight channel data streams are referred to as eight FEC channel data streams. This is not specifically limited here.

[0544] Based on the data processing diagram of the transmitting end processing module shown in Figure 12(a), the transmitting end processing module uses the known alignment markers of the channels to perform alignment lock on the channel data streams. The known alignment markers for each of the eight channels are different. The transmitting end processing module then performs lane de-skew processing on the eight channel data streams to obtain eight aligned channel data streams. The eight channel data are then reordered based on the alignment markers, so that the eight channel data are arranged in a specified order. One order is to sort the channel data streams from top to bottom, from 0 to 7, as shown in Figure 15. The eight reordered channel data streams are then sent to a cascaded interleaver for data de-ordering to obtain n first data streams, which are then sent to an inner code encoder for inner code encoding. The n second data streams, which have undergone inner code encoding, undergo the designed bit interleaving and mapping, data processing, and transmission onto the channel transmission medium. Typically, n is 8.

[0545] It should be noted that the transmitting processing module's operation flow can also be as shown in Figure 12(b), where the identified and locked channel data streams are sent directly to channel reordering without undergoing channel deskew. The transmitting processing module can also adopt the operation flow shown in Figure 12(c) or Figure 12(d) without performing channel reordering. This reduces the latency of the overall cascaded FEC solution, but its ability to combat burst errors is somewhat weakened. Whether to perform channel deskew and channel reordering in the transmitting processing module can be determined based on the actual transmission scenario.

[0546] Implementation method 4: An operation process of applying the transmitting end processing module to cascade interleaving in a 1×800G or 2×400G interface scenario.

[0547] Based on the above-mentioned Embodiment 1 or Embodiment 2, this embodiment provides a specific implementation of a cascade interleaver, which shuffles the data order of the 32 PCS channel data streams after channel reordering to obtain n=32 first data streams. The specific structure of the cascade interleaver is described below.

[0548] Figure 16 is a first schematic diagram of cascade interleaving in an embodiment of the present application. As shown in Figure 16, 4 outer code RS symbols are obtained from each of the 32 PCS channel data streams, for a total of 128 symbols, each of which contains 10 bits. The 128 RS symbols before channel permutation can be represented by a matrix of 32 rows and 4 columns, and the 4 symbols in the rth row come from the PCS channel data stream r. The 128 RS symbols after permutation can also be represented by a matrix of 32 rows and 4 columns. Among the 32 rows and 4 columns of symbols after channel permutation, the symbol in the rth row of the 0th column (0≤r<32) comes from the symbol in the rth row of the 0th column before channel permutation, the symbol in the rth row of the 1st column comes from the symbol in the rth row of the 1st column before channel permutation; the symbol in the rth row of the 2nd column comes from the symbol in the rth row of the 1st column before channel permutation; The sign of the row comes from the 2nd column before channel permutation The symbol of the row, column 2 The sign of the row comes from the 2nd column before channel permutation The symbol of the row; the 3rd column The sign of the row comes from the 3rd column before channel permutation. The symbol of the row, column 3 The sign of the row comes from the 3rd column before channel permutation. Line symbol.

[0549] As shown in Figure 16, a total of 128 RS symbols in 32 rows and 4 columns are subjected to channel permutation to obtain 128 RS symbols after 32 rows and 4 columns permutation. The channel permutation relationship can be expressed by the formula. The symbol of the 128 RS symbols in the 32 rows and 4 columns after permutation, the symbol of the r0th row and c0th column comes from the symbol of the 128 RS symbols in the 32 rows and 4 columns before permutation. The 32 data streams after channel permutation are sent to the convolution interleaver to interleave and disrupt the data order.

[0550] FIG17 is a schematic diagram of the first structure of the convolution interleaver in an embodiment of the present application. As shown in FIG17 , the convolution interleaver used in this embodiment includes four delay lines. These four delay lines include 3Q storage units, 2Q storage units, Q storage units, and 0 storage units, respectively. Each storage unit is used to store 4 RS symbols, where each symbol is 10 bits. In other words, the delay value of delay line 0 is 12Q symbols, the delay value of delay line 1 is 8Q symbols, the delay value of delay line 2 is 4Q symbols, and the delay value of delay line 3 is 0 symbols, i.e., no delay. As shown in FIG17 , C r () represents an RS symbol in the data stream r (0≤r<32) after channel permutation. For example, C r (16t), C r (16t+1), C r (16t+2), C r (16t+3) represents the 4 RS symbols currently input to delay line 0 in channel data stream r and C r (16t-48Q), C r (16t-48Q+1), C r (16t-48Q+2), C r (16t-48Q+3) are the 4 RS symbols output by delay line 0; C r (16t+4), C r (16t+5), C r (16t+6), C r (16t+7) represents the next 4 RS symbols input to delay line 1 in the channel data stream and C r (16t-32Q+4), C r (16t-32Q+5), C r (16t-32Q+6), C r (16t-32Q+7) are the 4 RS symbols output by delay line 1; C r (16t+8), C r (16t+9), C r (16t+10), C r (16t+11) represents the next 4 RS symbols input to delay line 2 in the channel data stream and C r (16t-16Q+8), C r (16t-16Q+9), C r (16t-16Q+10), C r (16t-16Q+11) are the 4 RS symbols output by delay line 2; C r (16t+12), C r(16t+13), C r (16t+14), C r (16t+15) represents the 4 RS symbols subsequently input to delay line 3 in the channel data stream and C r (16t+12), C r (16t+13), C r (16t+14), C r (16t+15) is the 4 RS symbols output by delay line 3. When 16Q+4≥68, that is, Q≥4, the C output of the convolution interleaving is r (16t-48Q), C r (16t-48Q+1), C r (16t-48Q+2), C r (16t-48Q+3), C r (16t-32Q+4),

[0551] C r (16t-32Q+5), C r (16t-32Q+6), C r (16t-32Q+7), C r (16t-16Q+8), C r (16t-16Q+9),

[0552] C r (16t-16Q+10), C r (16t-16Q+11), C r (16t+12), C r (16t+13), C r (16t+14), C r A total of 16 RS symbols (16t+15) come from 16 different RS codewords. In this embodiment, Q=4 is used. The delay value of delay line 0 is 48 RS symbols (i.e., 480-bit delay), the delay value of delay line 1 is 32 RS symbols (i.e., 320-bit delay), the delay value of delay line 2 is 16 RS symbols (i.e., 160-bit delay), and the delay value of delay line 3 is 0, i.e., no delay.

[0553] Implementation 5: Another operation flow of cascading interleaving in which the transmitting end processing module is applied to a 1×800G or 2×400G interface scenario.

[0554] Based on the above-described embodiment 1 or embodiment 2, this embodiment provides another specific implementation of a cascaded interleaver, which shuffles the data order of the 32 PCS channel data streams after channel reordering to obtain n=16 first data streams. The specific structure of the cascaded interleaver is described below.

[0555] Figure 18 is a schematic diagram of the second cascade interleaving method in an embodiment of the present application. As shown in Figure 18, 32 PCS channel data streams are convolutionally interleaved to obtain 32 third data streams, and then 32 third data streams are multiplexed in pairs to obtain one first data stream, resulting in a total of 16 first data streams.

[0556] FIG19 is a schematic diagram of the second structure of the convolution interleaver in the embodiment of the present application. As shown in FIG19 , the convolution interleaver used in this embodiment includes 4 delay lines. These 4 delay lines include 3Q storage units, 2Q storage units, Q storage units, and 0 storage units, respectively. Each storage unit is used to store 2 RS symbols, where each symbol is 10 bits. In other words, the delay value of delay line 0 is 6Q symbols, the delay value of delay line 1 is 4Q symbols, the delay value of delay line 2 is 2Q symbols, and the delay value of delay line 3 is 0 symbols, i.e., no delay. As shown in FIG19 , C r () represents an RS symbol in the channel data stream r (0≤r<32). For example, C r (8t), C r (8t+1) represents the two RS symbols currently input to delay line 0 in channel data stream r and C r (8t-24Q), C r (8t-24Q+1) are the two RS symbols output by delay line 0; C r (8t+2), C r (8t+3) represents the next two RS symbols input to delay line 1 in the channel data stream and C r (8t-16Q+2), C r (8t-16Q+3) are the two RS symbols output by delay line 1; C r (8t+4), C r (8t+5) represents the next two RS symbols input to delay line 2 in the channel data stream and C r (8t-8Q+4), C r (8t-8Q+5) are the two RS symbols output by delay line 2; C r (8t+6), C r (8t+7) represents the two RS symbols subsequently input to delay line 3 in the channel data stream and C r (8t+6), C r (8t+7) are the two RS symbols output by delay line 3. When 8Q+2≥68, i.e., Q≥9, the convolution interleaving output C r (8t-24Q), C r (8t-24Q+1), C r(8t-16Q+2), C r (8t-16Q+3), C r (8t-8Q+4), C r (8t-8Q+5), C r (8t+6), C r A total of 8 RS symbols (8t+7) come from 8 different RS codewords. In this embodiment, Q=9 is used. The delay value of delay line 0 is 54 RS symbols (i.e., 540-bit delay), the delay value of delay line 1 is 36 RS symbols (i.e., 360-bit delay), the delay value of delay line 2 is 18 RS symbols (i.e., 180-bit delay), and the delay value of delay line 3 is 0, i.e., no delay.

[0557] The 32 third data streams obtained by the above convolution interleaving process are multiplexed every 2 to obtain 1 first data stream, and a total of 16 first data streams are obtained. As shown in Figure 18, multiplexing p (0≤p<16) multiplexes 8 consecutive RS symbols in the third data stream p and 8 consecutive RS symbols in the third data stream p+15 into 16 consecutive symbols in the first data stream p. The above 16 consecutive symbols come from 16 RS symbols in 16 different outer code RS code words. A specific implementation method is that the 8 consecutive RS symbols C in the third data stream p p (0), C p (1) C p (2) C p (3) C p (4) C p (5) C p (6) C p (7) and the 8 consecutive RS symbols C in the third data stream p+16 p+16 (0), C p+16 (1) C p+16 (2) C p+16 (3) C p+16 (4) C p+16 (5) C p+16 (6) C p+16 (7) Multiplex into 16 consecutive symbols C in the first data stream p p (0), C p (1) C p (2) C p (3) C p (4) C p (5) C p (6) C p (7) C p+16 (0), C p+16 (1) C p+16 (2) C p+16(3) C p+16 (4) C p+16 (5) C p+16 (6) C p+16 (7) Another specific implementation is that the eight consecutive RS symbols C in the third data stream p p (0), C p (1) C p (2) C p (3) C p (4) C p (5) C p (6) C p (7) and the 8 consecutive RS symbols C in the third data stream p+16 p+16 (0), C p+16 (1) C p+16 (2) C p+16 (3) C p+16 (4) C p+16 (5) C p+16 (6) C p+16 (7) Multiplex into 16 consecutive symbols C in the first data stream p p (0), C p+16 (0), C p (1) C p+16 (1) C p (2) C p+16 (2) C p (3) C p+16 (3) C p (4) C p+16 (4) C p (5) C p+16 (5) C p (6) C p+16 (6) C p (7) C p+16 (7). Here, for the 16 symbols C p (0), C p (1) C p (2) C p (3) C p (4) C p (5) C p (6) C p (7) and C p+16 (0), C p+16 (1) C p+16 (2) C p+16 (3) C p+16 (4) C p+16 (5) C p+16 (6) Cp+16 The specific order of arrangement of (7) is not limited.

[0558] Implementation method 6: Another operation flow of cascade interleaving in which the transmitting end processing module is applied to a 1×800G interface scenario.

[0559] Based on the above embodiment 3, this embodiment provides another specific implementation of the cascade interleaver, which shuffles the order of the 8 channel data streams after channel reordering to obtain n=8 first data streams. The specific structure of the cascade interleaver is introduced below.

[0560] Figure 20 is a third schematic diagram of cascade interleaving in an embodiment of the present application. As shown in Figure 20, 8 channel data streams are respectively subjected to convolution interleaving processing to obtain 8 first data streams.

[0561] FIG21 is a schematic diagram of the third structure of the convolution interleaver in the embodiment of the present application. As shown in FIG21 , the convolution interleaver used in this embodiment includes 6 delay lines. These 6 delay lines include 5Q storage units, 4Q storage units, 3Q storage units, 2Q storage units, Q storage units, and 0 storage units, respectively. Each storage unit is used to store 2 RS symbols, where each symbol is 10 bits. In other words, the delay value of delay line 0 is 10Q symbols, the delay value of delay line 1 is 8Q symbols, the delay value of delay line 2 is 6Q symbols, the delay value of delay line 3 is 4Q symbols, the delay value of delay line 4 is 2Q symbols, and the delay value of delay line 5 is 0 symbols, i.e., no delay. As shown in FIG21 , C r () represents an RS symbol in the data stream r (0≤r<8) after channel permutation. For example, C r (12t), C r (12t+1) represents the two RS symbols currently input to delay line 0 in channel data stream r and C r (12t-60Q), C r (12t-60Q+1) are the two RS symbols output by delay line 0; C r (12t+2), C r (12t+3) represents the next two RS symbols input to delay line 1 in the channel data stream and C r (12t-48Q+2), C r (12t-48Q+3) are the two RS symbols output by delay line 1; and so on, C r (12t+10), C r (12t+11) represents the next two RS symbols input to delay line 2 in the channel data stream and C r (12t+10), Cr (12t+11) are the two RS symbols output by delay line 2. When 12Q+2≥68, that is, Q≥6, the output C r (12t-60Q), C r (12t-60Q+1), C r (12t-48Q+2),

[0562] C r (12t-48Q+3), C r (12t-36Q+4), C r (12t-36Q+5), C r (12t-24Q+6), C r (12t-24Q+7),

[0563] C r (12t-12Q+8), C r (12t-12Q+9), C r (12t+10), C r A total of 12 RS symbols (12t+11) come from 12 different RS codewords. In this embodiment, Q=6, with delay line 0 having a delay value of 60 RS symbols (i.e., a 600-bit delay), delay line 1 having a delay value of 48 RS symbols (i.e., a 480-bit delay), delay line 2 having a delay value of 36 RS symbols (i.e., a 360-bit delay), delay line 3 having a delay value of 24 RS symbols (i.e., a 240-bit delay), delay line 4 having a delay value of 12 RS symbols (i.e., a 120-bit delay), and delay line 5 having a delay value of 0, i.e., no delay.

[0564] Implementation method 7: Another operation flow of cascading interleaving in which the transmitting end processing module is applied to a 1×800G or 2×400G interface scenario.

[0565] On the basis of the above-mentioned embodiment 4, this embodiment provides another structural diagram of the convolution interleaver. Figure 22 is a fourth structural diagram of the convolution interleaver in the embodiment of the present application. As shown in Figure 22, the convolution interleaver used in this embodiment includes 3 delay lines. These 3 delay lines include 2Q storage units, Q storage units, and 0 storage units, respectively. Each storage unit is used to store 4 RS symbols, where each symbol is 10 bits. In other words, the delay value of delay line 0 is 8Q symbols, the delay value of delay line 1 is 4Q symbols, and the delay value of delay line 2 is 0 symbols, that is, no delay. As shown in Figure 22, the delay line 0 has a delay value of 8Q symbols, the delay value of delay line 1 has a delay value of 4Q symbols, and the delay value of delay line 2 has a delay value of 0 symbols, that is, no delay. r () represents an RS symbol in the data stream r (0≤r<32) after channel permutation. For example, C r (16t), C r(16t+1), C r (16t+2), C r (16t+3) represents the 4 RS symbols currently input to delay line 0 in channel data stream r and C r (16t-24Q), C r (16t-24Q+1), C r (16t-24Q+2), C r (16t-24Q+3) are the 4 RS symbols output by delay line 0; C r (16t+4), C r (16t+5), C r (16t+6), C r (16t+7) represents the next 4 RS symbols input to delay line 1 in the channel data stream and C r (16t-12Q+4), C r (16t-12Q+5), C r (16t-12Q+6), C r (16t-12Q+7) are the 4 RS symbols output by delay line 1; C r (16t+8), C r (16t+9), C r (16t+10), C r (16t+11) represents the next 4 RS symbols input to delay line 2 in the channel data stream and C r (16t+8), C r (16t+9), C r (16t+10), C r (16t+11) is the 4 RS symbols output by delay line 2. When 12Q+4≥68, that is, Q≥6, the convolution interleaving output C r (16t-24Q), C r (16t-24Q+1), C r (16t-24Q+2), C r (16t-24Q+3), C r (16t-12Q+4),

[0566] C r (16t-12Q+5), C r (16t-12Q+6), C r (16t-12Q+7), C r (16t+8), C r (16t+9), C r (16t+10),

[0567] Cr A total of 12 RS symbols (16t+11) come from 12 different RS codewords. In this embodiment, Q=6, and the delay value of delay line 0 is 48 RS symbols (i.e., 480-bit delay), the delay value of delay line 1 is 24 RS symbols (i.e., 240-bit delay), and the delay value of delay line 2 is 0, i.e., no delay.

[0568] Implementation 8: Another operation flow of applying the transmitting end processing module to cascade interleaving in a 1×800G or 2×400G interface scenario.

[0569] On the basis of the above-mentioned embodiment 5, this embodiment provides another structural diagram of the convolution interleaver. Figure 23 is a fifth structural diagram of the convolution interleaver in the embodiment of the present application. As shown in Figure 23, the convolution interleaver used in this embodiment includes 3 delay lines. These 3 delay lines include 2Q storage units, Q storage units, and 0 storage units, respectively. Each storage unit is used to store 2 RS symbols, where each symbol is 10 bits. In other words, the delay value of delay line 0 is 4Q symbols, the delay value of delay line 1 is 2Q symbols, and the delay value of delay line 2 is 0 symbols, that is, there is no delay. As shown in Figure 23, the delay line 0 has a delay value of 4Q symbols, the delay value of delay line 1 has a delay value of 2Q symbols, and the delay value of delay line 2 has a delay value of 0 symbols, that is, no delay. r () represents an RS symbol in the channel data stream r (0≤r<32). For example, C r (6t), C r (6t+1) represents the two RS symbols currently input to delay line 0 in channel data stream r and C r (6t-12Q), C r (6t-12Q+1) are the two RS symbols output by delay line 0; C r (6t+2), C r (6t+3) represents the next two RS symbols input to delay line 1 in the channel data stream and C r (6t-6Q+2), C r (6t-6Q+3) are the two RS symbols output by delay line 1; C r (6t+4), C r (6t+5) represents the next two RS symbols input to delay line 2 in the channel data stream and C r (6t+4), C r (6t+5) are the two RS symbols output by delay line 2; when 6Q+2≥68, i.e., Q≥11, the convolution interleaving output C r (6t-12Q), C r (6t-12Q+1), C r (6t-6Q+2), C r (6t-6Q+3), C r(6t+4), C r A total of 6 RS symbols (6t+5) come from 6 different RS codewords. In this embodiment, Q=11, the delay value of delay line 0 is 44 RS symbols (i.e., 440-bit delay), the delay value of delay line 1 is 22 RS symbols (i.e., 220-bit delay), and the delay value of delay line 2 is 0, i.e., no delay.

[0570] The 32 third data streams obtained through the convolutional interleaving described above are multiplexed into one first data stream for every two of them, resulting in a total of 16 first data streams. As shown in Figure 18, multiplexing p (0≤p<16) multiplexes 6 consecutive RS symbols in the third data stream p and 6 consecutive RS symbols in the third data stream p+15 into 12 consecutive symbols in the first data stream p. These 12 consecutive symbols come from 12 RS symbols in 12 different outer code RS codewords.

[0571] It should be noted that, in some practical applications, different bit interleaving and mapping methods can be selected according to different transmission scenarios. Figure 24 is a flow chart of a data processing in an embodiment of the present application. As shown in Figure 24, V types of bit interleaving and mapping processing modules are provided, and V is an integer greater than 1. Among them, the V types of bit interleaving and mapping processing modules shown have different anti-burst capabilities. In a specific application, n first data streams are encoded by inner code to obtain n second data streams, and one of the bit interleaving and mapping processing modules is selected according to the actual transmission scenario to bit interleave and map the data in the second data stream to obtain multiple modulation symbols. It should be understood that the inner code encoding module in Figure 24 is used to execute step 301 in the embodiment shown in Figure 3, and each bit interleaving and mapping processing module in Figure 24 is used to execute steps 302 and 303 in the embodiment shown in Figure 3. The specific implementation method will not be repeated here. As an example, the above-mentioned embodiments 1-11 provide a total of 11 different bit interleaving and mapping methods. Then, 11 bit interleaving and mapping processing modules can be provided accordingly in Figure 24 to select the required bit interleaving and mapping processing modules according to the actual transmission scenario to implement the bit interleaving and mapping methods in the corresponding embodiments.

[0572] The above describes the data processing method provided in the embodiment of the present application. The following describes the data processing device provided in the embodiment of the present application.

[0573] FIG25 is a schematic diagram of the structure of a data processing device in an embodiment of the present application. As shown in FIG25 , the data processing device includes an encoding module 101, a bit interleaving module 102, and a bit mapping module 103. The encoding module 101 is used to perform the operation of step 301 in the data processing method shown in FIG3 . The bit interleaving module 102 is used to perform the operation of step 302 in the data processing method shown in FIG3 . The bit mapping module 103 is used to perform the operation of step 303 in the data processing method shown in FIG3 . For details, please refer to the relevant introduction of the above-mentioned data processing method, which will not be repeated here.

[0574] It should be understood that the device provided in this application can also be implemented in other ways. For example, the unit division in the above-mentioned device is only a logical functional division. There may be other division methods in actual implementation. For example, multiple units or components can be combined or integrated into another system. In addition, the functional units in the various embodiments of this application can be integrated into one processing unit, or they can be independent physical units, or two or more functional units can be integrated into one processing unit. The above-mentioned integrated units can be implemented in the form of hardware or in the form of software functional units.

[0575] It should be noted that in the data processing method described in FIG3 , the n inner codewords are derived from n second data streams, wherein an inner codeword is obtained from each second data stream, and then the n inner codewords are bit-interleaved. In some specific applications, multiple inner codewords can also be obtained from each data stream and bit-interleaved. FIG26 is another flow diagram of the data processing method provided in an embodiment of the present application. It should be understood that this method is data processing performed on a data stream after outer code encoding, and can be specifically implemented by the above-mentioned transmitting end processing module 02.

[0576] 401. Perform interleaving coding on each n1 first data streams in the n0 first data streams to obtain a second data stream, so as to obtain a total of n2 second data streams, where n2 = n0 / n1, and n1 is an integer greater than 0.

[0577] In this embodiment, the Physical Medium Attachment (PMA) sublayer of the transmitting end processing module performs a first data processing on data from multiple synchronous client lanes to obtain n0 first data streams, where n0 is an integer greater than 1. The first data processing may include alignment lock, lane de-skew or lane alignment, lane reordering, or symbol multiplexing. The n0 first data streams are all data streams encoded with an outer code. For example, the outer code may use an RS code, and the n data streams after outer code encoding may include multiple RS code words. For example, the outer code may use a KP4RS (544, 514) code with a code length of 544 symbols, and each outer code symbol contains 10 bits.

[0578] The following describes the specific operations of interleaving and coding the n1 first data streams to obtain a second data stream. The interleaving and coding process includes operations such as inner code coding, cyclic shifting, and polling reading.

[0579] Figure 27 is a schematic diagram of a first embodiment of interleaved coding. As shown in Figure 27 (a), the interleaved coding process first performs inner code encoding, then performs cyclic shifting, and then performs round-robin reading. It should be understood that each first data stream contains at least a0 first bit sets, each first bit set containing K bits, where the integer a0 > 1. For the n1 first data streams, a0 first bit sets are obtained from each first data stream, resulting in a total of m = n1 × a0 first bit sets, totaling n1 × a0 × K bits.

[0580] As shown in (b) of Figure 27, the inner code encoding performs inner code encoding on each of the m first bit sets containing K bits, adds P check bits, and obtains an inner code codeword containing N bits, resulting in a total of m inner code codewords. Here, the first bit set containing K bits can be called an inner code information sequence, and K+P=N. The P check bits are also called a check bit set. One inner code codeword contains one first bit set and one check bit set. That is to say, the m inner code codewords contain m first bit sets and m check bit sets. Usually, K is an integer multiple of 10. It should be noted that in the present application materials, the inner code codeword is also referred to as a codeword.

[0581] It should be noted that convolutional interleaving is typically performed before inner code encoding to ensure that the K information bits correspond to a larger number of KP4 outer code symbols, such as K / 10 outer code symbols, and that the corresponding outer code symbols come from a larger number of outer codewords, thereby achieving better overall cascaded FEC performance. For example, if K = 120, the 120 information bits correspond to 12 KP4 outer code symbols, which come from 12 outer codewords.

[0582] It should be noted that in some scenarios requiring low latency, convolutional interleaving is typically not performed before inner code encoding. The K information bits correspond to K / 10 outer code symbols, and the number of outer code words from which these outer code symbols originate is less than K / 10. For example, if K = 120, the 120 information bits correspond to 12 KP4 outer code symbols, and the 12 KP4 symbols come from 4 outer code words.

[0583] As shown in FIG27( b ), for the information bit sequences of m inner codewords, i.e., m first bit sets, the cyclic shift cyclically shifts each first bit set to the left. bits or cyclically shifted δ bits to the right to obtain a second bit set containing K bits. Each second bit set is combined with the P-length check bits in its corresponding inner code word to obtain a third bit set containing N bits. It should be noted that the third bit set containing N bits is obtained by cyclically shifting the information bit sequence (first bit set) containing K bits in the inner code word and combining it with the check bits containing P bits in the inner code word. For the sake of simplicity of description, this application material simply describes the third bit set containing N bits as being obtained by cyclically shifting the inner code code word containing N bits.

[0584] Taking the left cyclic shift as an example, for the first bit set (u0,u1,u2,u3,…,u K-2 ,u K-1 ), circular shift to the left bits, and obtain the second bit set containing K bits after shifting Where Y%Z represents the remainder after dividing the integer Y by the integer Z. Usually, the offset constraint factor for the left circular shift is is an integer multiple of 10, and

[0585] Taking the right cyclic shift as an example, for the first bit set (u0,u1,u2,u3,…,u K-2 ,u K-1 ), cyclically shift δ bits to the right to obtain the second bit set (u (-δ)％K ,u (1-δ)％K,u (2-δ)％K ,…,u (K-2-δ)％K ,u (K-1-δ)％K ), where Y%Z represents the remainder after the integer Y is divided by the integer Z. Usually, the offset constraint factor δ of the right cyclic shift is an integer multiple of 10, and 0≤δ <K。

[0586] It should be noted that the first bit set is cyclically shifted to the left bits to obtain the second bit set, which is equivalent to the first bit set being cyclically shifted to the right. bits to obtain the second bit set.

[0587] It should be noted that the offset constraint factor of the left cyclic shift is The offset constraint factor δ of the rightward cyclic shift is not fixed and can be time-varying. Usually, the period of the cyclic shift is p c , the cyclic shift is performed to the left for the first bit set of the i-th group containing K bits bits, or perform a right cyclic shift δ i bits, where m is an integer p c Integer multiples of , 0≤i <p c Usually m=p c Typically, there are m offset constraint factors (Right now Any two of The values ​​of m offset constraint factors δ are not equal to each other; i (i.e. δ0,δ1,…,δ m-1 ) in which the values ​​of any two δ are not equal.

[0588] As shown in (b) of Figure 27, for the m third-bit sets output by the cyclic shift, the polling read polling obtains 2 bits from each of the third-bit sets, and continuously performs m×N / 2 operations to obtain all the bits in the m third-bit sets, and obtains a fourth-bit set containing m×N bits.

[0589] The said second data stream contains multiple 4th bit sets, the said 1 4th bit set containing m×N bits is obtained by polling and reading out 2 bits of m 3rd bit sets, the said m 3rd bit sets containing N bits are obtained by cyclic shifting of m inner code codewords, the said m inner code codewords are obtained by inner code encoding of m 1st bit sets, and the said m 1st bit sets are obtained by obtaining a0 1st bit sets from each 1st data stream in n1 1st data streams, where m=n1×a0.

[0590] It should be noted that the "polling readout" polls and obtains 2 bits from each of the above-mentioned 3-bit sets, obtaining a 4-bit set containing m×N bits, which is equivalent to the following operation: First, for m 2-bit sets, polling and obtaining 2 bits from each of the 2-bit sets to obtain a total of m×K bits, and then for the parity bit sets in m inner code codewords, polling and obtaining 2 bits from each of the parity bit sets to obtain a total of m×P bits. Combining the m×K bits obtained from the m 2-bit sets and the m×P bits obtained from the m parity bit sets, a 4-bit set containing m×N bits is obtained.

[0591] It should be noted that in some specific applications, the cyclic shift and the polling readout operation can be combined and implemented in one step to perform bit interleaving on the m inner code codewords containing m×N bits to obtain 1 such 4-bit set.

[0592] FIG. 28 is a schematic diagram of a second implementation manner of interleaving encoding processing. As shown in FIG. 28, the m 1-bit sets can be represented by a 1-bit matrix M1 with m rows and K columns, where each row in the 1-bit matrix M1 includes K bits of a 1-bit set. The bit at the i-th (0≤i<m) row and the e-th (0≤e<K) column in the 1-bit matrix M1 is denoted as M1[i][e]. The m inner code codewords can be represented by an inner codeword matrix M with m rows and N columns c denoted as, where each row in the inner codeword matrix M c includes N bits of an inner codeword. The bit at the i-th (0≤i<m) row and the j-th (0≤j<N) column in the inner codeword matrix M c is denoted as M c [i][j]. The m 2-bit sets can be represented by a 2-bit matrix M2 with m rows and K columns, where each row in the 2-bit matrix M2 includes K bits of a 2-bit set. The bit at the i-th (0≤i<m) row and the e-th (0≤e<K) column in the 2-bit matrix M2 is denoted as M2[i][e]. The m parity bit sets can be represented by a parity bit matrix M p denoted as, where each row in the parity bit matrix M p includes P parity bits of an inner codeword. The bit at the i-th (0≤i<m) row and the f-th (0≤f<P) column in the parity bit matrix M p is denoted as M p[i][f]. The m third-bit sets can be represented by a third-bit matrix M3 of m rows and N columns, where each row in the third-bit matrix M3 includes N bits of a third-bit set. The bit at the i-th (0 ≤ i < m) row and j-th (0 ≤ j < N) column in the third-bit matrix M3 is denoted as M3[i][j]. The fourth-bit set containing m×N bits is represented by an array A. The k-th (0 ≤ k < m×N) bit in the array A is denoted as A[k].

[0593] As shown in FIG. 28, the first-bit matrix M1 is encoded by inner code to obtain an inner-code codeword matrix M c .

[0594] For the cyclic shift operation, taking the left cyclic shift as an example, for the inner-code codeword matrix M c the K information bits in the i-th (0 ≤ i < m) row (i.e., the K bits in the i-th row of the first-bit matrix M1) are cyclically shifted to the left bits to obtain the K bits in the i-th (0 ≤ i < m) row of the third-bit matrix M3, where the non-zero integer is the offset constraint factor for the cyclic shift of the i-th row. At this time, the third-bit matrix M3 and the inner-code codeword matrix M c satisfy formula (X-1):

[0595] where, Y%Z represents the remainder after the integer Y is divided by the integer Z, 0 ≤ i < m. Generally, the offset constraint factor for the left cyclic shift is an integer multiple of 10, and

[0596] It should be noted that for the K information bits in the i-th row of the first matrix H1, performing a left cyclic shift of bits results in the K bits in the 0th column to the (K-1)th column in the i-th row of the second matrix H2. This is equivalent to performing a right cyclic shift of bits on the K information bits in the 0th column to the (K-1)th column in the i-th row of the first matrix H1, resulting in the K bits in the 0th column to the (K-1)th column in the i-th row of the second matrix H2.

[0597] As another example, using the right cyclic shift, the third-bit matrix M3 and the inner-code codeword matrix M c satisfy formula (X-2):

[0598] where, Y%Z represents the remainder after the integer Y is divided by the integer Z, 0 ≤ i < m. Generally, the offset constraint factor δ i for the right cyclic shift is an integer multiple of 10, and 0 ≤ δ i <K.

[0599] It should be noted that for the inner code codeword matrix M c The K information bits in the i-th row are cyclically shifted to the right by δ i bits to obtain the K bits from the 0th column to the (K - 1)th column in the i-th row of the third-bit matrix M3. This is equivalent to cyclically shifting the K information bits from the 0th column to the (K - 1)th column in the i-th row of the third-bit matrix M3 to the left by δ i bits to obtain the K bits from the 0th column to the (K - 1)th column in the i-th row of the inner code codeword matrix M c That is to say, formula (X - 2) can also be written as formula (X - 3):

[0600] The inner code codeword matrix M c Performs cyclic shift of information bits in each row to obtain the third-bit matrix M3.

[0601] As shown in Figure 28, the "polling read" polls 2 bits from each row of the third-bit matrix M3, continuously m times to obtain 2 columns in the third-bit matrix M3, and a total of m×N / 2 operations are used to read all m×N bits, obtaining the array A containing m×N interleaved bits. The bit in the i-th row and j-th column of the third-bit matrix M3 is output to the -th bit in the array A, which satisfies formula (X - 4):

[0602] where 0 ≤ i < m, 0 ≤ j < N, represents the floor operation.

[0603] It should be noted that the operation of polling 2 bits from each row of the third-bit matrix M3 is called m-way codeword interleaving.

[0604] The above-mentioned operation of cyclically shifting the information bits in each row of the inner code codeword matrix M c to obtain the third-bit matrix M3 and then polling 2 bits from each row is implemented by two-step operations, and it can also be implemented by one-step operation. The direct corresponding relationship between M c and A is directly given below.

[0605] If a left cyclic shift is used, combining formula (X - 1) and formula (X - 4), there is the following formula (X - 5):

[0606] where 0 ≤ i < m. Usually, the cyclic shift offset constraint factor is an integer multiple of 10 and Typically, m offset constraint factors (i.e., ) any two The numerical values are not equal to each other.

[0607] If right circular shift is adopted and combined with formula (X - 2) and formula (X - 4), there is the following formula (X - 6):

[0608] where 0 ≤ i < m. Usually, the circular shift offset constraint factor δ i is an integer multiple of 10 and Typically, m offset constraint factors δ i (i.e., δ0, δ1, …, δ m-1 ) The numerical values of any two δ are not equal to each other.

[0609] It should be noted that the circular shift and polling readout adopt one-step operation, which has the advantages of simple implementation and low complexity.

[0610] It should be noted that the interleaved coding process performs circular shift and inner code coding in parallel, and then performs polling readout. The following introduces this implementation manner.

[0611] FIG. 29 is a schematic diagram of the third implementation manner of the interleaved coding process. As shown in FIG. 29, for the n1 first data streams, a0 first bit sets are respectively obtained from each first data stream, and a total of m = n1 × a0 first bit sets are obtained, which altogether contain n1 × a0 × K bits.

[0612] As shown in (b) of FIG. 29, the circular shift circularly shifts the i-th first bit set in the m first bit sets <00...​​​​​​​​​​​​​​​​​​​​​​​The inner code encoding respectively performs inner code encoding on each of the m first-bit sets containing K bits to obtain a check-bit set containing P bits, and a total of m check-bit sets are obtained. The "polling readout" first targets the m second-bit sets, polls and obtains 2 bits from each of the second-bit sets for a total of m×K bits, and then targets the m check-bit sets, polls and obtains 2 bits from each of the check-bit sets for a total of m×P bits. The m×K bits obtained from the m second-bit sets and the m×P bits obtained from the m check-bit sets result in a fourth-bit set containing m×N bits.

[0614] Figure 30 is a schematic diagram of the fourth implementation manner of the interleaving encoding process. As shown in Figure 30, the m first-bit sets can be represented by a first-bit matrix M1 with m rows and k columns, and the m second-bit sets can be represented by a second-bit matrix M2 with m rows and k columns. Specifically, the first-bit matrix M1 is cyclically shifted to obtain the second-bit matrix M2.

[0615] Taking left cyclic shift as an example, the first-bit matrix M1 and the second-bit matrix M2 satisfy formula (X-7):

[0616] where, Y%Z represents the remainder after integer Y is divided by integer Z, 0≤i<m, 0≤j<K. Usually, the offset constraint factor of the left cyclic shift is an integer multiple of 10, and

[0617] It should be noted that for the K bits in the i-th row of the first-bit matrix M1, perform a left cyclic shift bits to obtain the K bits in the i-th row of the second-bit matrix M2. This is equivalent to performing a right cyclic shift bits on the K bits in the i-th row of the first-bit matrix M1 to obtain the K bits in the i-th row of the second-bit matrix M2.

[0618] As another example, for position transformation, a right cyclic shift is adopted. Perform a right cyclic shift of δ i bits on the i-th first-bit set among the m first-bit sets, where the non-zero integer δ i is the cyclic shift offset constraint factor corresponding to the i-th bit set. The right cyclic shift satisfies formula (X-8): M2[i][j] = M1[i][(j - δ i )%K]

[0619] where, Y%Z represents the remainder after integer Y is divided by integer Z, 0≤i<m, 0≤j<K. Usually, the offset constraint factor δ of the right cyclic shift iis an integer multiple of 10, and 0 ≤ δ i <K.

[0620] It should be noted that for the K bits in the i-th row of the first bit matrix M1, a cyclic right shift of δ i bits is performed to obtain the K bits in the i-th row of the second bit matrix M2. This is equivalent to performing a cyclic left shift of δ i bits on the K bits in the i-th row of the second bit matrix M2 to obtain the K bits in the i-th row of the first bit matrix M1. That is to say, formula (X - 8) can also be written as formula (X - 9): M1[i][j] = M2[i][(j + δ i ) % K]

[0621] where 0 ≤ i < m and 0 ≤ j < K.

[0622] As shown in Figure 30, the first bit matrix M1 is encoded by inner code to obtain a parity check bit matrix M p . Two bits are polled and read from each row of the second bit matrix M2, and a total of m × K / 2 operations are performed to read all m × K bits of the second bit matrix M2, obtaining the 0th to the (m × K - 1)th bits in the array A containing m × N interleaved bits. Two bits are polled and read from each row of the parity check bit matrix M p , and a total of m × P / 2 operations are performed to read all m × P bits of the parity check bit matrix M p , obtaining the (m × K)th to the (m × N - 1)th bits in the array A.

[0623] It should be noted that the cyclic shift and the inner code encoding are performed in parallel, which has the advantage of low latency.

[0624] It should be noted that the interleaving encoding process first performs a cyclic shift, then performs an inner code encoding, and then performs a polling read. The following introduces this implementation manner.

[0625] Figure 31 is a schematic diagram of the fifth implementation manner of the interleaving encoding process. As shown in Figure 31, for the n1 first data streams, a0 first bit sets are respectively obtained from each first data stream, obtaining a total of m = n1 × a0 first bit sets, which altogether contain n1 × a0 × K bits.

[0626] As shown in (b) of Figure 31, the cyclic shift performs a cyclic left shift of the i-th first bit set among the m first bit sets or a cyclic right shift of δ i bits to obtain the i-th second bit set containing K bits, obtaining a total of m second bit sets, 0 ≤ i < m. Usually, the offset constraint factor for the cyclic left shift is an integer multiple of 10, and the offset constraint factor δ for right circular shift i is an integer multiple of 10, and 0 ≤ δ i <K. Typically, m offset constraint factors (i.e., ) any two of have unequal values; any two of the m offset constraint factors δ i (i.e., δ0, δ1, …, δ m-1 ) have unequal values.

[0627] As shown in (b) of FIG. 31, the inner code encoding respectively performs inner code encoding on each of the m second-bit sets containing K bits, adds P parity bit positions, and obtains an inner code codeword containing N bits, resulting in a total of m inner code codewords.

[0628] As shown in (b) of FIG. 31, for the m inner code codewords, the polling readout polls 2 bits from each of the inner code codewords, and after m×N / 2 consecutive operations, all the bits in the m inner code codewords are obtained, resulting in a fourth-bit set containing m×N bits.

[0629] FIG. 32 is a schematic diagram of the sixth implementation manner of the interleaving encoding process. As shown in FIG. 32, the m first-bit sets can be represented by a bit matrix M1 with m rows and K columns, the m second-bit sets can be represented by a bit matrix M2 with m rows and K columns, and the m inner code codewords can be represented by a bit matrix M c representation. The first-bit matrix M1 undergoes a circular shift to obtain the second-bit matrix M2.

[0630] Taking the left circular shift as an example, the first-bit matrix M1 and the second-bit matrix M2 satisfy formula (X - 10):

[0631] where Y % Z represents the remainder after integer Y is divided by integer Z, 0 ≤ i < m, 0 ≤ j < K. Usually, the offset constraint factor for the left circular shift is an integer multiple of 10, and

[0632] It should be noted that for the K bits in the i-th row of the first-bit matrix M1, performing a left circular shift bits results in the K bits in the i-th row of the second-bit matrix M2. This is equivalent to performing a right circular shift bits on the K bits in the i-th row of the first-bit matrix M1 to obtain the K bits in the i-th row of the second-bit matrix M2.

[0633] As another example, the position transformation uses a right circular shift, and the $i$-th first-bit set in the $m$ first-bit sets is circularly shifted to the right by $\delta$ i bits, where the non-zero integer $\delta$ i is the offset constraint factor for the circular shift corresponding to the $i$-th bit set. The right circular shift satisfies formula (X - 11): $M2[i][j]=M1[i][(j - \delta$ i ) \% K]$

[0634] where, $Y\%Z$ represents the remainder after the integer $Y$ is divided by the integer $Z$, $0\leq i\lt m$, $0\leq j\lt K$. Usually, the offset constraint factor $\delta$ i for the right circular shift is an integer multiple of 10, and $0\leq \delta$ i $\lt K$.

[0635] It should be noted that for the $K$ bits in the $i$-th row of the first-bit matrix $M1$, a right circular shift of $\delta$ i bits is performed to obtain the $K$ bits in the $i$-th row of the second-bit matrix $M2$. This is equivalent to performing a left circular shift of $\delta$ i bits on the $K$ bits in the $i$-th row of the second-bit matrix $M2$ to obtain the $K$ bits in the $i$-th row of the first-bit matrix $M1$. That is, formula (X - 11) can also be written as formula (X - 12): $M1[i][j]=M2[i][(j + \delta$ i ) \% K]$

[0636] where, $0\leq i\lt m$, $0\leq j\lt K$.

[0637] As shown in Figure 32, the second-bit matrix $M2$ is encoded with an inner code to obtain an inner-code word matrix $M$ c . The "polling readout" polls and reads out 2 bits from each row of the inner-code word matrix $M$ c , and a total of $m\times N / 2$ operations are performed to read all $m\times N$ bits, obtaining the array $A$ containing $m\times N$ interleaved bits. The bit in the $i$-th row and $j$-th column of the inner-code word matrix $M$ c is output to the $ $-th bit in the array $A$, which satisfies formula (X - 13):

[0638] where, $0\leq i\lt m$, $0\leq j\lt N$, represents the floor operation.

[0639] 402. Map every 2 bits in each of the $n2$ second data streams to a PAM4 symbol respectively to obtain $n2$ PAM4 symbol data streams.

[0640] For PAM4 modulation, where every two bits are mapped to a PAM4 modulation symbol, the fourth bit set or array A, consisting of m×N bits, is mapped to m×N / 2 PAM4 modulation symbols. The mapping is such that the two bits of a PAM4 modulation symbol come from one inner codeword, and the mapping is such that the m×2 bits of m consecutive PAM4 modulation symbols come from m inner codewords.

[0641] Furthermore, for two outer code symbols from the same RS outer code word in a first data stream, after the above data processing, they are mapped into multiple PAM4 symbols in the same PAM4 symbol data stream, and the offset constraint factor of the left cyclic shift is selected appropriately. Or the offset constraint factor δ of the right cyclic shift i , so that any two PAM4 symbols among the multiple PAM4 symbols are separated by at least two PAM4 symbols in the PAM4 symbol data stream. It should be noted that two adjacent PAM4 symbols in a PAM4 symbol data stream are considered to be separated by one PAM4 symbol.

[0642] In some specific applications, before bit mapping is performed on the n2 second data streams, padding bits are periodically inserted into the n2 second data streams, where the padding bits include an alignment flag for alignment and synchronization of a receiving end.

[0643] In the embodiments of this application, a cascaded FEC transmission scheme is adopted, whereby the data stream is sequentially encoded using both outer and inner codes. Based on this, this application designs an interleaved coding method that allows both the bits in the outer and inner codewords to be discretely and evenly mapped onto modulation symbols. This gives the cascaded FEC transmission scheme strong burst resistance, particularly for shorter burst errors, which can be directly corrected by inner code decoding. This makes it applicable to a wide range of transmission scenarios, particularly in practical coherent transmission scenarios where the channel contains colored noise.

[0644] It should be noted that the polling readout in the present application material obtains 2 bits from each of the third bit sets to obtain a fourth bit set containing m×N bits. That is, 2 bits are obtained from the 0th third bit set, 2 bits are obtained from the 1st third bit set, ..., 2 bits are obtained from the m-1th third bit set, and then 2 bits are obtained from the 0th third bit set, until all m×N bits are obtained. In some specific implementations, the order of polling readout may be changed, and the offset constraint factor of the left loop in the cyclic shift operation may be changed accordingly. Or the right-loop offset constraint factors δ0,δ1,…,δ m-1 Just change the order accordingly.

[0645] The following further describes the data processing method described in Figure 26 with reference to some specific examples. The following Examples X-1 to X-6 describe the data processing process described in Figures 27 and 28.

[0646] Example X-1: n0=4, n1=1, a0=8, the data processing flow includes convolution interleaving, taking the bit set representation as an example, using left cyclic shift.

[0647] The Physical Medium Attachment (PMA) sublayer of the transmitting end processing module performs first data processing on data from multiple synchronous client lanes to obtain n0=4 first data streams. These n0=4 first data streams are all outer-coded data streams. The interleaving encoding process is then performed on each n1=1 of the n0=4 first data streams to obtain a second data stream, resulting in a total of n2=4 second data streams.

[0648] Referring to Figure 27 , the interleaved encoding process first performs inner code encoding, then cyclic shifting, and then polling readout. For the n1 = 1 first data stream, m = n1 × a0 = 8 first bit sets containing K = 120 bits are obtained, totaling m × K = 960 bits. Before inner code encoding, the first data stream also undergoes convolutional interleaving, resulting in the K = 120 bits coming from 12 KP4 symbols of 12 different outer code KP4RS codewords.

[0649] The inner code encoding performs inner code encoding on every K=120 bits and adds P=8 check bits to obtain an inner code word containing N=128 bits, and a total of m=8 inner code words are obtained. The K=120 bits are also called information bit sequence.

[0650] In the present application, the cyclic shift operation performs a cyclic shift to the left on the K=120 information bits in the i-th (0≤i<8) inner codeword, i.e., the i-th first bit set. bits to get the ith bit set, where the 8 left cyclic shift offset constraint factors are The specific value of is one of the following value items 1:

[0651] {0,30,60,90,110,20,50,80},

[0652] {0,30,90,60,110,20,80,50},

[0653] {0,60,30,90,110,50,20,80},

[0654] {0,60,90,30,110,50,80,20},

[0655] {0,90,30,60,110,80,20,50},

[0656] {0,90,60,30,110,80,50,20}

[0657] It should be understood that for any term, the offset constraint factor of 8 left cyclic shifts Add a fixed offset to each factor value in is still considered a legal parameter term, where Δ is an integer.

[0658] The i-th second bit set is combined with P=8 check bits in the i-th inner codeword to obtain the i-th third bit set containing N=128 bits.

[0659] Referring to Figure 27, for the m=8 third bit sets output by the cyclic shift, the polling read polling obtains 2 bits from each of the third bit sets, and performs 512 consecutive operations to obtain all bits in the m=8 third bit sets, and obtains a fourth bit set containing m×N=1024 bits.

[0660] Every two bits in the fourth bit set of 1024 bits are mapped to a PAM4 modulation symbol, resulting in a total of 512 PAM4 symbols. The two bits mapped to one PAM4 modulation symbol come from one inner codeword, and the 16 bits mapped to eight consecutive PAM4 modulation symbols come from eight inner codewords.

[0661] For the two KP4 outer code symbols of the same RS outer code word in the n1=1 first data stream, a total of 20 bits, which are processed by the above interleaving coding and mapped to 10 PAM4 symbols in one PAM4 symbol data stream, the offset constraint factor of the left cyclic shift described in the value item 1 is used. Any two of the 10 PAM4 symbols may be spaced apart by at least two PAM4 symbols in the PAM4 symbol data stream. More specifically, when the two of the 10 PAM4 symbols come from different KP4 outer codewords, they are spaced apart by at least 12 PAM4 symbols in the PAM4 symbol data stream.

[0662] The interleaving coding processing method designed in this embodiment enables the bits in the outer codeword and the bits in the inner codeword to be discretely and evenly mapped to the modulation symbols, so that the cascaded FEC transmission scheme has a strong burst resistance capability.

[0663] It should be noted that in this embodiment, n0=4, n1=1, a0=8, and n2=n0 / n1=4 can be applied to 800GE scenarios, where n2=4 second data streams have a rate of approximately 200G and are carried and transmitted on four optical signals. The interleaving coding process used in this embodiment can be applied to 1.6TE scenarios, where n0=8, n1=1, a0=8, and n2=n0 / n1=8. In this case, the Physical Medium Attachment (PMA) sublayer of the transmitting end processing module performs first data processing on data from multiple synchronous client lanes to obtain n0=8 first data streams. The above n0=8 first data streams are all data streams encoded with outer codes. The interleaving coding process is performed on each n1=1 first data stream in the n0=8 first data streams to obtain a second data stream, resulting in a total of n2=8 second data streams. The n2=8 second data streams (each approximately 200G) are carried and sent out on 8 optical signals.

[0664] Example X-2: n0=4, n1=1, a0=8, the data processing flow includes convolution interleaving, and taking matrix representation as an example, a left cyclic shift is adopted.

[0665] Based on the scheme of embodiment X-1, the m=8 first bit sets can be represented by a first bit matrix M1 with 8 rows and 120 columns. The K=120 bits in each row of the first bit matrix M1 are respectively encoded by inner code to obtain an inner code with N=128 bits. The 8 inner code codewords can be represented by an inner code codeword matrix M with 8 rows and 128 columns. c Represents, where the inner codeword matrix M c Each row in M ​​contains N=128 bits of an inner code word. c The total m×K=960 bits from column 0 to column K-1=119 correspond to m×K=960 information bits of m=8 inner code words; the inner code word matrix M c A total of m×P=64 bits from the K=120th column to the N-1=127th column correspond to m×P=64 check bits of m=8 inner code words.

[0666] Inner code word matrix M c The 120 information bits in the i-th (0≤i<8) row (i.e., the 120 bits in the i-th row of the first bit matrix M1) are cyclically shifted to the left bits, and the 120 bits in the i-th row of the third bit matrix M3 are obtained, satisfying the following formula:

[0667] Where Y%Z represents the remainder after dividing integer Y by integer Z, 0≤i<8. The offset constraint factor of 8 left cyclic shifts The specific value of is one of the value items 1.

[0668] FIG33 is a schematic diagram of the seventh embodiment of interleaving coding processing. As shown in FIG33, considering The letters a, b, c, d, f, g, h, k, p, q, r, and s each represent a KP4 symbol, each containing 10 bits. The KP4 symbols for the same letter in Figure 33 come from the same KP4 outer code, while the KP4 symbols for different letters come from different KP4 outer codes. For example, the eight KP4 symbols for the same letter a in Figure 33 all come from the same KP4 outer code.

[0669] 2 bits are read from each row of the third bit matrix M3 in a round-robin manner, and all 1024 bits are read in 512 operations in total, thereby obtaining the array A containing m×N=1024 interleaved bits. The bit of the i-th row and j-th column in the third bit matrix M3 is output to the j-th column in the array A. bits, satisfying the following formula:

[0670] Among them, 0≤i<8, 0≤j<128, Indicates a floor operation.

[0671] It should be noted that the above inner codeword matrix M c The 1024-bit array A is obtained by performing circular shift and polling reading in two operations. It can also be performed in one step. The following directly gives M c The direct correspondence with A:

[0672] Among them, 0≤i<8.

[0673] Every two bits in the 1024-bit array A are mapped to a PAM4 modulation symbol, resulting in a total of 512 PAM4 symbols. The two bits mapped to one PAM4 modulation symbol come from one inner codeword, and the 16 bits mapped to eight consecutive PAM4 modulation symbols come from eight inner codewords.

[0674] For the two KP4 outer code symbols of the same RS outer code word in the n1=1 first data stream, a total of 20 bits, which are processed by the above interleaving coding and mapped to 10 PAM4 symbols in one PAM4 symbol data stream, the offset constraint factor of the left cyclic shift described in the value item 1 is used. Any two of the 10 PAM4 symbols can be separated by at least 2 PAM4 symbols in the PAM4 symbol data stream. More specifically, when the two PAM4 symbols among the 10 PAM4 symbols come from different KP4 outer code codewords, their separation in the PAM4 symbol data stream is at least 12 PAM4 symbols.

[0675] The interleaved coding processing method designed in this embodiment makes the bits in the outer code codeword and the bits in the inner code codeword be discretely and uniformly mapped to the modulation symbols, so that the cascaded FEC transmission scheme has strong burst resistance.

[0676] It should be noted that in this embodiment, n0 = 4, n1 = 1, a0 = 8, n2 = n0 / n1 = 4, which can be applied to the 800GE scenario, where n2 = 4, the second data stream rate is about 200G and is correspondingly carried on 4 optical signals and sent out. The interleaved coding processing adopted in this embodiment can be applied to the 1.6TE scenario, where n0 = 8, n1 = 1, a0 = 8, n2 = n0 / n1 = 8. At this time, the Physical Medium Attachment (PMA) sublayer of the transmitting end processing module performs the first data processing on the data from multiple synchronized client lanes to obtain n0 = 8 first data streams. The above n0 = 8 first data streams are all data streams encoded by the outer code. The interleaved coding processing is respectively performed on every n1 = 1 of the n0 = 8 first data streams to obtain one second data stream, so as to obtain a total of n2 = 8 second data streams. The n2 = 8 second data streams (each about 200G) and are correspondingly carried on 并对应承载在8路光信号上发出。

[0677] Embodiment X-3: n0 = 4, n1 = 1, a0 = 8, the data processing flow includes convolutional interleaving. Taking the matrix representation as an example, right circular shift is adopted.

[0678] On the basis of the Embodiment X-2 scheme, right circular shift is adopted. For the inner codeword matrix M c The 120 information bits in the i-th (0 ≤ i < 8) row (that is, the 1st bit matrix M1, the 120 bits in the i-th row) are circularly shifted to the right by δ i bits to obtain the 120 bits in the i-th row of the 3rd bit matrix M3, satisfying the following formula:

[0679] where, Y%Z represents the remainder after integer Y is divided by integer Z, 0 ≤ i < m. The specific values of the 8 right circular shift offset constraint factors {δ0, δ1, δ2, δ3, δ4, δ5, δ6, δ7} are one of the following value items 2:

[0680] {0,30,60,90,10,40,70,100},

[0681] {0,30,90,60,10,40,100,70},

[0682] {0,60,30,90,10,40,40,100},

[0683] {0,60,90,30,10,70,100,40},

[0684] {0,90,30,60,10,100,40,70},

[0685] {0,90,60,30,10,100,70,40}

[0686] It should be noted that the corresponding relationship between M3 and M2 can also be written as the following formula:

[0687] Among them, 0≤i<8.

[0688] It should be noted that for any item in the value item 2, a fixed offset is added to each factor value in the 8 right cyclic shift offset constraint factors {δ0, δ1, δ2, δ3, δ4, δ5, δ6, δ7}, that is, {(δ0+Δ)%K, (δ1+Δ)%K, (δ2+Δ)%K, (δ3+Δ)%K, (δ4+Δ)%K, (δ5+Δ)%K, (δ6+Δ)%K, (δ7+Δ)%K} is still considered to be a legal parameter item, where Δ is an integer.

[0689] Figure 34 is a schematic diagram of the eighth embodiment of interleaved coding. As shown in Figure 34, consider {δ0 = 0, δ1 = 90, δ2 = 60, δ3 = 30, δ4 = 10, δ5 = 100, δ6 = 70, δ7 = 40}, where the letters a, b, c, d, f, g, h, k, p, q, r, and s each represent a KP4 symbol containing 10 bits. KP4 symbols with the same letter in Figure 34 come from the same KP4 outer code, while KP4 symbols with different letters come from different KP4 outer codes. For example, the eight KP4 symbols with the same letter a in Figure 34 come from the same KP4 outer code.

[0690] 2 bits are read from each row of the third bit matrix M3 in a round-robin manner, and all 1024 bits are read in 512 operations in total, thereby obtaining the array A containing m×N=1024 interleaved bits. The bit of the i-th row and j-th column in the third bit matrix M3 is output to the j-th column in the array A. bits, satisfying the following formula:

[0691] Among them, 0≤i<8, 0≤j<128, Indicates a floor operation.

[0692] It should be noted that the above inner codeword matrix M c The 1024-bit array A is obtained by performing circular shift and polling reading in two operations. It can also be performed in one step. The following directly gives M c The direct correspondence with A:

[0693] Among them, 0≤i<8.

[0694] Every two bits in the 1024-bit array A are mapped to a PAM4 modulation symbol, resulting in a total of 512 PAM4 symbols. The two bits mapped to one PAM4 modulation symbol come from one inner codeword, and the 16 bits mapped to eight consecutive PAM4 modulation symbols come from eight inner codewords.

[0695] For the two KP4 outer code symbols of the same RS outer code word in the n1=1 first data stream, a total of 20 bits are processed by the above interleaving coding and mapped to 10 PAM4 symbols in the PAM4 symbol data stream, the offset constraint factor δ of the right cyclic shift described in the value item 2 is adopted. i , any two of the 10 PAM4 symbols may be separated by at least two PAM4 symbols in the PAM4 symbol data stream. More specifically, when the two of the 10 PAM4 symbols come from different KP4 outer codewords, they may be separated by at least 12 PAM4 symbols in the PAM4 symbol data stream.

[0696] The interleaved coding processing method designed in this embodiment enables the bits in the outer codeword and the bits in the inner codeword to be discretely and evenly mapped to the modulation symbols, making the cascaded FEC transmission scheme have a strong burst resistance capability.

[0697] It should be noted that in this embodiment, n0=4, n1=1, a0=8, and n2=n0 / n1=4 can be applied to 800GE scenarios, where n2=4 second data streams have a rate of approximately 200G and are carried and transmitted on four optical signals. The interleaving coding process used in this embodiment can be applied to 1.6TE scenarios, where n0=8, n1=1, a0=8, and n2=n0 / n1=8. In this case, the Physical Medium Attachment (PMA) sublayer of the transmitting end processing module performs first data processing on data from multiple synchronous client lanes to obtain n0=8 first data streams. The above n0=8 first data streams are all data streams encoded with outer codes. The interleaving coding process is performed on each n1=1 first data stream in the n0=8 first data streams to obtain a second data stream, resulting in a total of n2=8 second data streams. The n2=8 second data streams (each approximately 200G) are carried and sent out on 8 optical signals.

[0698] Example X-4: n0=4, n1=1, a0=8, the data processing flow does not include convolution interleaving, and taking the bit set representation as an example, a left cyclic shift is adopted.

[0699] Based on Example X-1, the convolution interleaving operation is not performed (bypassed), which has the advantage of low latency and meets application scenarios with high latency requirements. The Physical Medium Attachment (PMA) sublayer of the transmitting end processing module performs first data processing on data from multiple synchronous client lanes to obtain n0=4 first data streams. The above n0=4 first data streams are all data streams that have been encoded with outer codes. The interleaving encoding process is performed on each n1=1 first data stream in the n0=4 first data streams to obtain a second data stream, so as to obtain a total of n2=4 second data streams.

[0700] Referring to Figure 27 , the interleaved encoding process first performs inner code encoding, then cyclic shifting, and finally polling readout. For the n1 = 1 first data stream, m = n1 × a0 = 8 first bit sets containing K = 120 bits are obtained, for a total of m × K = 960 bits. The 120 information bits of each inner codeword come from 12 KP4 symbols of four different outer code KP4RS codewords.

[0701] The inner code encoding performs inner code encoding on every K=120 bits and adds P=8 check bits to obtain an inner code word containing N=128 bits, and a total of m=8 inner code words are obtained. The K=120 bits are also called information bit sequence.

[0702] In the present application, the cyclic shift operation performs a cyclic shift to the left on the K=120 information bits in the i-th (0≤i<8) inner codeword, i.e., the i-th first bit set. bits to get the ith bit set, where the 8 left cyclic shift offset constraint factors are The specific value of is one of the following 3 value items:

[0703] {0,30,60,90,110,20,50,80},

[0704] {0,60,30,90,110,50,20,80}

[0705] It should be understood that for any term, the offset constraint factor of 8 left cyclic shifts A fixed offset is added to each factor value in is still considered a legal parameter term, where Δ is an integer.

[0706] The i-th second bit set is combined with P=8 check bits in the i-th inner codeword to obtain the i-th third bit set containing N=128 bits.

[0707] Referring to Figure 27, for the m=8 third bit sets output by the cyclic shift, the polling read polling obtains 2 bits from each of the third bit sets, and performs 512 consecutive operations to obtain all bits in the m=8 third bit sets, and obtains a fourth bit set containing m×N=1024 bits.

[0708] Every two bits in the fourth bit set of 1024 bits are mapped to a PAM4 modulation symbol, resulting in a total of 512 PAM4 symbols. The two bits mapped to one PAM4 modulation symbol come from one inner codeword, and the 16 bits mapped to eight consecutive PAM4 modulation symbols come from eight inner codewords.

[0709] For the two KP4 outer code symbols of the same RS outer code word in the n1=1 first data stream, a total of 20 bits, which are processed by the above interleaving coding and mapped to 10 PAM4 symbols in one PAM4 symbol data stream, the offset constraint factor of the left cyclic shift described in value item 3 is used. Any two PAM4 symbols among the 10 PAM4 symbols may be spaced apart by at least two PAM4 symbols in the PAM4 symbol data stream.

[0710] The bit interleaving and mapping method designed in this embodiment enables the bits in the outer codeword and the bits in the inner codeword to be mapped to the modulation symbols more discretely and more evenly while ensuring low latency, so that the cascaded FEC transmission scheme has better anti-burst capability.

[0711] It should be noted that in this embodiment, n0=4, n1=1, a0=8, and n2=n0 / n1=4 can be applied to 800GE scenarios, where n2=4 second data streams have a rate of approximately 200G and are carried and transmitted on four optical signals. The interleaving coding process used in this embodiment can be applied to 1.6TE scenarios, where n0=8, n1=1, a0=8, and n2=n0 / n1=8. In this case, the Physical Medium Attachment (PMA) sublayer of the transmitting end processing module performs first data processing on data from multiple synchronous client lanes to obtain n0=8 first data streams. The above n0=8 first data streams are all data streams encoded with outer codes. The interleaving coding process is performed on each n1=1 first data stream in the n0=8 first data streams to obtain a second data stream, resulting in a total of n2=8 second data streams. The n2=8 second data streams (each approximately 200G) are carried and sent out on 8 optical signals.

[0712] Example X-5: n0=4, n1=1, a0=8, the data processing flow does not perform convolution interleaving, and using matrix representation as an example, a left cyclic shift is used.

[0713] Based on Example X-4, the m=8 bit set can be represented by a matrix. The K=120 bits in each row of the first bit matrix M1 are respectively encoded by inner code to obtain the inner code codeword matrix M c . For the inner code word matrix M c The 120 information bits in the i-th (0≤i<8) row (i.e., the 120 bits in the i-th row of the first bit matrix M1) are cyclically shifted to the left bits, and the 120 bits in the i-th row of the third bit matrix M3 are obtained, satisfying the following formula:

[0714] Where Y%Z represents the remainder after dividing integer Y by integer Z, 0≤i<8. The offset constraint factor of 8 left cyclic shifts The specific value of is one of the value items 3.

[0715] FIG35 is a schematic diagram of a ninth embodiment of interleaving coding processing. As shown in FIG35 , considering The letters a, b, c, and d each represent a KP4 symbol, each containing 10 bits. The KP4 symbols for the same letter in Figure 35 come from the same KP4 outer code, while the KP4 symbols for different letters come from different KP4 outer codes. For example, the 24 KP4 symbols for the same letter a in Figure 35 come from the same KP4 outer code.

[0716] Two bits are read out from each row of the third bit matrix M3 in a round-robin manner, and all 1024 bits are read through 512 operations in total, thereby obtaining the array A containing m×N=1024 interleaved bits.

[0717] Every two bits in the 1024-bit array A are mapped to a PAM4 modulation symbol, resulting in a total of 512 PAM4 symbols. The two bits mapped to one PAM4 modulation symbol come from one inner codeword, and the 16 bits mapped to eight consecutive PAM4 modulation symbols come from eight inner codewords.

[0718] For the two KP4 outer code symbols of the same RS outer code word in the n1=1 first data stream, a total of 20 bits, which are processed by the above interleaving coding and mapped to 10 PAM4 symbols in one PAM4 symbol data stream, the offset constraint factor of the left cyclic shift described in value item 3 is used. Any two PAM4 symbols among the 10 PAM4 symbols may be spaced apart by at least two PAM4 symbols in the PAM4 symbol data stream.

[0719] The bit interleaving and mapping method designed in this embodiment enables the bits in the outer codeword and the bits in the inner codeword to be mapped to the modulation symbols more discretely and more evenly while ensuring low latency, so that the cascaded FEC transmission scheme has better anti-burst capability.

[0720] It should be noted that in this embodiment, n0 = 4, n1 = 1, a0 = 8, n2 = n0 / n1 = 4, which can be applied to the 800GE scenario. Among them, n2 = 4 second data streams have a rate of approximately 200G and are respectively carried on 4 optical signals and sent out. The interleaving coding process adopted in this embodiment can be applied to the 1.6TE scenario, where n0 = 8, n1 = 1, a0 = 8, n2 = n0 / n1 = 8. At this time, the Physical Medium Attachment (PMA) sublayer of the transmitting end processing module performs the first data processing on the data from multiple synchronized client lanes, and then obtains n0 = 8 first data streams. The above n0 = 8 first data streams are all data streams encoded by the outer code. The interleaving coding process is respectively performed on every n1 = 1 first data stream among the n0 = 8 first data streams to obtain one second data stream, so as to obtain a total of n2 = 8 second data streams. The n2 = 8 second data streams have a rate (about 200G per stream) and are respectively carried on 8 optical signals and sent out.

[0721] Embodiment X-6: n0 = 4, n1 = 1, a0 = 8, the data processing process does not perform convolutional interleaving. Taking matrix representation as an example, right circular shift is adopted.

[0722] Based on Embodiment X-5, the circular shift adopts right circular shift. For the inner code codeword matrix M c The 120 information bits in the i-th (0 ≤ i < 8) row in it (that is, the 120 bits in the i-th row of the first bit matrix M1) are circularly shifted to the right by δ i bits to obtain the 120 bits in the i-th row of the third bit matrix M3, which satisfy the following formula:

[0723] Where, Y%Z represents the remainder after integer Y is divided by integer Z, and 0 ≤ i < m. The specific values of the 8 right circular shift offset constraint factors {δ0, δ1, δ2, δ3, δ4, δ5, δ6, δ7} are one of the following value items 4:

[0724] {0, 60, 90, 30, 10, 70, 100, 40},

[0725] {0, 90, 60, 30, 10, 100, 70, 40}

[0726] It should be understood that for any item, a fixed offset is added to each factor value in the 8 right cyclic shift offset constraint factors {δ0, δ1, δ2, δ3, δ4, δ5, δ6, δ7}, that is, {(δ0+Δ)%K, (δ1+Δ)%K, (δ2+Δ)%K, (δ3+Δ)%K, (δ4+Δ)%K, (δ5+Δ)%K, (δ6+Δ)%K, (δ7+Δ)%K} is still considered a legal parameter item, where Δ is an integer.

[0727] It should be noted that M3 and M c The corresponding relationship can also be written as follows:

[0728] Among them, 0≤i<8.

[0729] Figure 36 is a schematic diagram of the tenth embodiment of interleaved coding. As shown in Figure 36, consider {δ0 = 0, δ1 = 60, δ2 = 90, δ3 = 30, δ4 = 10, δ5 = 70, δ6 = 100, δ7 = 40}, where the letters a, b, c, and d each represent a KP4 symbol containing 10 bits. KP4 symbols with the same letter in Figure 36 come from the same KP4 outer code, while KP4 symbols with different letters come from different KP4 outer codes. For example, the 24 KP4 symbols with the same letter a in Figure 36 come from the same KP4 outer code.

[0730] Two bits are read out from each row of the third bit matrix M3 in a round-robin manner, and all 1024 bits are read through 512 operations in total, thereby obtaining the array A containing m×N=1024 interleaved bits.

[0731] Every two bits in the 1024-bit array A are mapped to a PAM4 modulation symbol, resulting in a total of 512 PAM4 symbols. The two bits mapped to one PAM4 modulation symbol come from one inner codeword, and the 16 bits mapped to eight consecutive PAM4 modulation symbols come from eight inner codewords.

[0732] For the two KP4 outer code symbols of the same RS outer code word in the n1=1 first data stream, a total of 20 bits, which are processed by the above interleaving coding and mapped to 10 PAM4 symbols in the PAM4 symbol data stream, the offset constraint factor δ of the right cyclic shift described in the value item 4 is adopted. i , so that any two PAM4 symbols among the 10 PAM4 symbols are spaced apart by at least two PAM4 symbols in the PAM4 symbol data stream.

[0733] The bit interleaving and mapping method designed in this embodiment enables the bits in the outer codeword and the bits in the inner codeword to be mapped to the modulation symbols more discretely and more evenly while ensuring low latency, so that the cascaded FEC transmission scheme has better anti-burst capability.

[0734] It should be noted that in this embodiment, n0=4, n1=1, a0=8, and n2=n0 / n1=4 can be applied to 800GE scenarios, where n2=4 second data streams have a rate of approximately 200G and are carried and transmitted on four optical signals. The interleaving coding process used in this embodiment can be applied to 1.6TE scenarios, where n0=8, n1=1, a0=8, and n2=n0 / n1=8. In this case, the Physical Medium Attachment (PMA) sublayer of the transmitting end processing module performs first data processing on data from multiple synchronous client lanes to obtain n0=8 first data streams. The above n0=8 first data streams are all data streams encoded with outer codes. The interleaving coding process is performed on each n1=1 first data stream in the n0=8 first data streams to obtain a second data stream, resulting in a total of n2=8 second data streams. The n2=8 second data streams (each approximately 200G) are carried and sent out on 8 optical signals.

[0735] It should be noted that in Examples X-1 to X-6, inner code encoding is performed first, followed by cyclic shifting. The inner code encoding and cyclic shifting can also be performed in parallel, as shown in Figures 29 and 30. The following describes an equivalent implementation of Example X-3, taking Example X-7 as an example.

[0736] Example X-7: n0=4, n1=1, a0=8, the data processing flow includes convolution interleaving, taking matrix representation as an example, using left cyclic shift, inner code encoding and cyclic shift in parallel.

[0737] Based on the solution of embodiment X-3, in this embodiment, inner code encoding and cyclic shift are performed in parallel.

[0738] FIG37 is a schematic diagram of the eleventh embodiment of the interleaving coding process. As shown in FIG37, the 120 information bits in the i-th (0≤i<8) row of the first bit matrix M1 (i.e., the 120 bits in the i-th row of the first bit matrix M1) are cyclically shifted to the left. bits, and the 120 bits in the i-th row of the second bit matrix M2 are obtained, satisfying the following formula:

[0739] Where Y%Z represents the remainder after dividing integer Y by integer Z, 0≤i<8, 0≤j<120. The offset constraint factor of 8 left cyclic shifts The specific value of is one of the value items 1. As shown in Figure 37, consider

[0740] The K=120 bits in each row of the first bit matrix M1 are encoded with an inner code to obtain a P=8 check bit, and the check bit matrix M is obtained. p .

[0741] 2 bits are read from each row of the third bit matrix M3 in a round-robin manner, and all 1024 bits are read in 512 operations in total, thereby obtaining the array A containing m×N=1024 interleaved bits. The bit of the i-th row and j-th column in the third bit matrix M3 is output to the j-th column in the array A. bits, satisfying the following formula:

[0742] Among them, 0≤i<8, 0≤j<128, Indicates a floor operation.

[0743] It should be noted that the above inner codeword matrix M c The 1024-bit array A is obtained by performing circular shift and polling reading in two operations. It can also be performed in one step. The following directly gives M c The direct correspondence with A:

[0744] Among them, 0≤i<8.

[0745] Every two bits in the 1024-bit array A are mapped to a PAM4 modulation symbol, resulting in a total of 512 PAM4 symbols. The two bits mapped to one PAM4 modulation symbol come from one inner codeword, and the 16 bits mapped to eight consecutive PAM4 modulation symbols come from eight inner codewords.

[0746] For the two KP4 outer code symbols of the same RS outer code word in the n1=1 first data stream, a total of 20 bits, which are processed by the above interleaving coding and mapped to 10 PAM4 symbols in the PAM4 symbol data stream, the offset constraint factor of the left cyclic shift is used. Any two PAM4 symbols among the 10 PAM4 symbols may be spaced apart by at least two PAM4 symbols in the PAM4 symbol data stream.

[0747] The interleaving coding processing method designed in this embodiment enables the bits in the outer codeword and the bits in the inner codeword to be discretely and evenly mapped to the modulation symbols, so that the cascaded FEC transmission scheme has a strong burst resistance capability.

[0748] It should be noted that in this embodiment, n0=4, n1=1, a0=8, and n2=n0 / n1=4 can be applied to 800GE scenarios, where n2=4 second data streams have a rate of approximately 200G and are carried and transmitted on four optical signals. The interleaving coding process used in this embodiment can be applied to 1.6TE scenarios, where n0=8, n1=1, a0=8, and n2=n0 / n1=8. In this case, the Physical Medium Attachment (PMA) sublayer of the transmitting end processing module performs first data processing on data from multiple synchronous client lanes to obtain n0=8 first data streams. The above n0=8 first data streams are all data streams encoded with outer codes. The interleaving coding process is performed on each n1=1 first data stream in the n0=8 first data streams to obtain a second data stream, resulting in a total of n2=8 second data streams. The n2=8 second data streams (each approximately 200G) are carried and sent out on 8 optical signals.

[0749] The following Examples X-8 to X-11 introduce the data processing flow as described in Figures 31 and 32.

[0750] Example X-8: n0=4, n1=1, a0=8, the data processing flow includes convolution interleaving, and taking the bit set representation as an example, a left cyclic shift is adopted.

[0751] The Physical Medium Attachment (PMA) sublayer of the transmitting end processing module performs first data processing on data from multiple synchronous client lanes to obtain n0=4 first data streams. These n0=4 first data streams are all outer-coded data streams. The interleaving encoding process is then performed on each n1=1 of the n0=4 first data streams to obtain a second data stream, resulting in a total of n2=4 second data streams.

[0752] Referring to Figure 31 , the interleaved encoding process first performs a cyclic shift, then inner code encoding, and then polling readout. For the n1 = 1 first data stream, m = n1 × a0 = 8 first bit sets containing K = 120 bits are obtained, totaling m × K = 960 bits. Before the cyclic shift, the first data stream also undergoes a convolutional interleaving process, so that the K = 120 bits come from 12 KP4 symbols of 12 different outer code KP4RS codewords.

[0753] In this application, the cyclic shift operation performs a cyclic shift to the left on the i-th (0≤i<8)th bit set. bits to get the ith bit set, where the 8 left cyclic shift offset constraint factors are The specific value of is one of the value items 1.

[0754] The inner code encoding performs inner code encoding on K=120 bits in the ith second bit set and adds P=8 check bits to obtain the ith inner code word containing N=128 bits, and a total of m=8 inner code words are obtained. The K=120 bits are also called the information bit sequence.

[0755] Referring to Figure 31, for the m=8 third bit sets output by the cyclic shift, the polling read polling obtains 2 bits from each of the third bit sets, and performs 512 consecutive operations to obtain all the bits in the m=8 third bit sets, and obtains a fourth bit set containing m×N=1024 bits.

[0756] Every two bits in the fourth bit set of 1024 bits are mapped to a PAM4 modulation symbol, resulting in a total of 512 PAM4 symbols. The two bits mapped to one PAM4 modulation symbol come from one inner codeword, and the 16 bits mapped to eight consecutive PAM4 modulation symbols come from eight inner codewords.

[0757] For the two KP4 outer code symbols of the same RS outer code word in the n1=1 first data stream, a total of 20 bits, which are processed by the above interleaving coding and mapped to 10 PAM4 symbols in the PAM4 symbol data stream, the offset constraint factor of the left cyclic shift is used. Any two PAM4 symbols among the 10 PAM4 symbols may be spaced apart by at least two PAM4 symbols in the PAM4 symbol data stream.

[0758] The interleaving coding processing method designed in this embodiment enables the bits in the outer codeword and the bits in the inner codeword to be discretely and evenly mapped to the modulation symbols, so that the cascaded FEC transmission scheme has a strong burst resistance capability.

[0759] It should be noted that in this embodiment, n0=4, n1=1, a0=8, and n2=n0 / n1=4 can be applied to 800GE scenarios, where n2=4 second data streams have a rate of approximately 200G and are carried and transmitted on four optical signals. The interleaving coding process used in this embodiment can be applied to 1.6TE scenarios, where n0=8, n1=1, a0=8, and n2=n0 / n1=8. In this case, the Physical Medium Attachment (PMA) sublayer of the transmitting end processing module performs first data processing on data from multiple synchronous client lanes to obtain n0=8 first data streams. The above n0=8 first data streams are all data streams encoded with outer codes. The interleaving coding process is performed on each n1=1 first data stream in the n0=8 first data streams to obtain a second data stream, resulting in a total of n2=8 second data streams. The n2=8 second data streams (each approximately 200G) are carried and sent out on 8 optical signals.

[0760] Example X-9: n0=4, n1=1, a0=8, the data processing flow includes convolution interleaving, and taking matrix representation as an example, a left cyclic shift is used.

[0761] Based on the solution of embodiment X-8, the m=8 first bit sets can be represented by a first bit matrix M1 with 8 rows and 120 columns. The 120 information bits in the i-th (0≤i<8)th row of the first bit matrix M1 are cyclically shifted to the left. bits, and the 120 bits in the i-th row of the second bit matrix M2 are obtained, which satisfies the following formula:

[0762] Where Y%Z represents the remainder after dividing integer Y by integer Z, 0≤i<8, 0≤j<120. The offset constraint factor of 8 left cyclic shifts The specific value of is one of the value items 1.

[0763] FIG38 is a schematic diagram of the twelfth embodiment of interleaving coding processing. As shown in FIG38, considering The K=120 bits in the i-th (0≤i<8) row of the second bit matrix M2 are respectively encoded with the inner code to obtain the i-th inner code word, and the inner code code word matrix M is obtained. c .

[0764] From the inner codeword matrix M c 2 bits are read out in each row of polling, and a total of 512 operations are performed to read all 1024 bits, thereby obtaining the array A containing m×N=1024 interleaved bits.c The bit in row i and column j in array A is output to the bits, satisfying the following formula:

[0765] Among them, 0≤i<8, 0≤j<128, Indicates a floor operation.

[0766] Every two bits in the 1024-bit array A are mapped to a PAM4 modulation symbol, resulting in a total of 512 PAM4 symbols. The two bits mapped to one PAM4 modulation symbol come from one inner codeword, and the 16 bits mapped to eight consecutive PAM4 modulation symbols come from eight inner codewords.

[0767] For the two KP4 outer code symbols of the same RS outer code word in the n1=1 first data stream, a total of 20 bits, which are processed by the above interleaving coding and mapped to 10 PAM4 symbols in the PAM4 symbol data stream, the offset constraint factor of the left cyclic shift is used. Any two PAM4 symbols among the 10 PAM4 symbols may be spaced apart by at least two PAM4 symbols in the PAM4 symbol data stream.

[0768] The interleaving coding processing method designed in this embodiment enables the bits in the outer codeword and the bits in the inner codeword to be discretely and evenly mapped to the modulation symbols, so that the cascaded FEC transmission scheme has a strong burst resistance capability.

[0769] It should be noted that in this embodiment, n0=4, n1=1, a0=8, and n2=n0 / n1=4 can be applied to 800GE scenarios, where n2=4 second data streams have a rate of approximately 200G and are carried and transmitted on four optical signals. The interleaving coding process used in this embodiment can be applied to 1.6TE scenarios, where n0=8, n1=1, a0=8, and n2=n0 / n1=8. In this case, the Physical Medium Attachment (PMA) sublayer of the transmitting end processing module performs first data processing on data from multiple synchronous client lanes to obtain n0=8 first data streams. The above n0=8 first data streams are all data streams encoded with outer codes. The interleaving coding process is performed on each n1=1 first data stream in the n0=8 first data streams to obtain a second data stream, resulting in a total of n2=8 second data streams. The n2=8 second data streams (each approximately 200G) are carried and sent out on 8 optical signals.

[0770] Example X-10: n0=8, n1=2, a0=4, the data processing flow includes convolution interleaving, and taking the bit set representation as an example, right cyclic shift is adopted.

[0771] The Physical Medium Attachment (PMA) sublayer of the transmitting end processing module performs first data processing on data from multiple synchronous client lanes to obtain n0 = 8 first data streams. These n0 = 8 first data streams are all outer-coded data streams. The interleaving coding process is performed on each n1 = 2 first data streams of the n0 = 8 first data streams to obtain a second data stream, resulting in a total of n2 = 4 second data streams.

[0772] Referring to Figure 31 , the interleaved coding process first performs a cyclic shift, then inner code encoding, and then polling readout. For the n1 = 2 first data streams, a0 = 4 first bit sets are obtained from each first data stream, resulting in a total of m = n1 × a0 = 8 first bit sets. Each first bit set contains K = 120 bits, and the 8 first bit sets contain a total of m × K = 960 bits. The first data stream also undergoes convolutional interleaving before cyclic shifting, so that the K = 120 bits come from 12 KP4 symbols of 12 different outer code KP4RS codewords. The four consecutive first bit sets in a first data stream are called the 0th first bit set, the 1st first bit set, the 2nd first bit set, and the 3rd first bit set; the four consecutive first bit sets in another first data stream are called the 4th first bit set, the 5th first bit set, the 6th first bit set, and the 7th first bit set.

[0773] In this application, the cyclic shift operation performs a right cyclic shift of the i-th (0≤i<8)th bit set by δ i bits to obtain the i-th second bit set, where the specific value of the 8 right cyclic shift offset constraint factors {δ0,δ1,δ2,δ3,δ4,δ5,δ6,δ7} is one of the value items 2.

[0774] The inner code encoding performs inner code encoding on K=120 bits in the ith second bit set and adds P=8 check bits to obtain the ith inner code word containing N=128 bits, and a total of m=8 inner code words are obtained. The K=120 bits are also called the information bit sequence.

[0775] Referring to Figure 31 , for the m = 8 third-bit sets output by the cyclic shift, the polling readout operation acquires 2 bits from each of the third-bit sets. This operation is repeated 512 times to acquire all bits in the m = 8 third-bit sets, resulting in a fourth-bit set consisting of m × N = 1024 bits. More specifically, 2 bits are acquired from the 0th third-bit set, 2 bits are acquired from the 1st third-bit set, ..., 2 bits are acquired from the 7th third-bit set, and 2 bits are acquired from the 0th third-bit set, until all 1024 bits are acquired.

[0776] It should be noted that, of the eight 3-bit sets, the 0th bit set, the 1st bit set, the 2nd bit set, and the 3rd bit set come from the same data stream; while the 4th bit set, the 5th bit set, the 6th bit set, and the 7th bit set come from another data stream. That is, the polling read operation first obtains 8 bits from one data stream and then obtains 8 bits from another data stream.

[0777] Every two bits in the fourth bit set of 1024 bits are mapped to a PAM4 modulation symbol, resulting in a total of 512 PAM4 symbols. The two bits mapped to one PAM4 modulation symbol come from one inner codeword, and the 16 bits mapped to eight consecutive PAM4 modulation symbols come from eight inner codewords.

[0778] For the two KP4 outer code symbols of the same RS outer code word in the n1=1 first data stream, a total of 20 bits, which are processed by the above interleaving coding and mapped to 10 PAM4 symbols in the PAM4 symbol data stream, the offset constraint factor δ of the right cyclic shift is adopted. i , so that any two PAM4 symbols among the 10 PAM4 symbols are spaced apart by at least two PAM4 symbols in the PAM4 symbol data stream.

[0779] The interleaving coding processing method designed in this embodiment enables the bits in the outer codeword and the bits in the inner codeword to be discretely and evenly mapped to the modulation symbols, so that the cascaded FEC transmission scheme has a strong burst resistance capability.

[0780] It should be noted that in this embodiment, n0 = 8, n1 = 2, a0 = 4, and n2 = n0 / n1 = 4, which can be applied to 800GE scenarios, where n2 = 4 second data streams have a rate of approximately 200G and are carried on four optical signals. The interleaving coding process used in this embodiment can be applied to 1.6TE scenarios, where n0 = 16, n1 = 2, a0 = 4, and n2 = n0 / n1 = 8. In this case, the Physical Medium Attachment (PMA) sublayer of the transmitting end processing module performs first data processing on data from multiple synchronous client lanes to obtain n0 = 16 first data streams. The above n0 = 16 first data streams are all data streams encoded with outer codes. The interleaving coding process is performed on each n1 = 2 first data streams in the n0 = 16 first data streams to obtain a second data stream, resulting in a total of n2 = 8 second data streams. The n2=8 second data streams (each approximately 200G) are carried and sent out on 8 optical signals.

[0781] It should be noted that in some other specific implementations, the four consecutive first-bit sets in a first data stream are referred to as the 0th first-bit set, the 2nd first-bit set, the 4th first-bit set, and the 6th first-bit set; and the four consecutive first-bit sets in another first data stream are referred to as the 1st first-bit set, the 3rd first-bit set, the 5th first-bit set, and the 7th first-bit set. For the m=8 third-bit sets output by the cyclic shift, the polling read obtains 2 bits from the 0th third-bit set, 2 bits from the 1st third-bit set, ..., 2 bits from the 7th third-bit set, and then 2 bits from the 0th third-bit set, until all 1024 bits are obtained. Correspondingly, among the eight 3-bit sets, the 0th, 2nd, 4th, and 8th bit sets of the 3-bit sequence are from the same data stream; the 1st, 3rd, 5th, and 7th bit sets of the 3-bit sequence are from another data stream. That is, the polling read operation first obtains two bits from one data stream and then obtains two bits from another data stream.

[0782] It should be noted that in some specific implementations, the four consecutive first-bit sets in a first data stream are referred to as the 0th first-bit set, the 1st first-bit set, the 4th first-bit set, and the 5th first-bit set; and the four consecutive first-bit sets in another first data stream are referred to as the 2nd first-bit set, the 3rd first-bit set, the 6th first-bit set, and the 7th first-bit set. For the m=8 third-bit sets output by the cyclic shift, the polling read obtains 2 bits from the 0th third-bit set, 2 bits from the 1st third-bit set, ..., 2 bits from the 7th third-bit set, and then 2 bits from the 0th third-bit set, until all 1024 bits are obtained. Correspondingly, among the eight 3-bit sets, the 0th bit set (first bit set), the 1st bit set (first bit set), the 4th bit set (first bit set), and the 5th bit set (first bit set) come from the same data stream; the 1st bit set (second bit set), the 3rd bit set (first bit set), the 6th bit set (first bit set), and the 7th bit set (first bit set) come from another data stream. That is, the polling read operation first obtains 4 bits from one data stream and then obtains 4 bits from another data stream.

[0783] Figure 39 is another schematic diagram of the structure of a data processing device according to an embodiment of the present application. As shown in Figure 39, the data processing device includes an interleaving encoding module 501 and a bit mapping module 502. Interleaving encoding module 501 is used to perform the operations in step 401 of the data processing method shown in Figure 26 above. Bit mapping module 502 is used to perform the operations in step 402 of the data processing method shown in Figure 26 above. For details, please refer to the relevant description of the data processing method shown in Figure 26 above, and will not be repeated here.

[0784] It should be understood that the device provided in this application can also be implemented in other ways. For example, the unit division in the above-mentioned device is only a logical functional division. There may be other division methods in actual implementation. For example, multiple units or components can be combined or integrated into another system. In addition, the functional units in the various embodiments of this application can be integrated into one processing unit, or they can be independent physical units, or two or more functional units can be integrated into one processing unit. The above-mentioned integrated units can be implemented in the form of hardware or in the form of software functional units.

[0785] Figure 40 is another structural diagram of a data processing device in an embodiment of the present application. As shown in Figure 40, the data processing device includes a processor 201, a memory 202, and a transceiver 203. The processor 201, the memory 202, and the transceiver 203 are interconnected via lines. The memory 202 is used to store program instructions and data. Specifically, the transceiver 203 is used to receive a first data stream. The processor 201 is used to perform the operations in the steps shown in Figure 3 or Figure 26 above. In one possible embodiment, the processor 201 may include the encoding module 101, the bit interleaving module 102, and the bit mapping module 103 shown in Figure 22 above. In another possible embodiment, the processor 201 may include the interleaving encoding module 501 and the bit mapping module 502 shown in Figure 39 above.

[0786] It should be noted that the processor shown in Figure 40 above can adopt a general central processing unit (CPU), a general-purpose processor, a digital signal processor (DSP), an application-specific integrated circuit (ASIC), a field programmable gate array (FPGA) or other programmable logic devices, transistor logic devices, hardware components or any combination thereof. The memory shown in Figure 40 above can store an operating system and other application programs. When the technical solution provided by the embodiment of the present application is implemented by software or firmware, the program code for implementing the technical solution provided by the embodiment of the present application is stored in the memory and executed by the processor. In one embodiment, the processor may include a memory inside. In another embodiment, the processor and the memory are two independent structures.

[0787] Those skilled in the art will clearly understand that, for the convenience and brevity of description, the specific working processes of the systems, devices and units described above can refer to the corresponding processes in the aforementioned method embodiments and will not be repeated here.

[0788] Those skilled in the art will appreciate that all or part of the steps in the above embodiments can be implemented by hardware or by programs instructing the relevant hardware to perform the steps. The programs can be stored in a computer-readable storage medium, which can be a read-only memory, a random access memory, or the like. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Professionals and technicians can use different methods to implement the described functions for each specific application, but such implementations should not be considered beyond the scope of this application.

[0789] When software is used for implementation, the method steps described in the above embodiment can be implemented in whole or in part in the form of a computer program product. The computer program product includes one or more computer instructions. When the computer program instructions are loaded and executed on a computer, the process or function described in the embodiment of the present application is generated in whole or in part. The computer can be a general-purpose computer, a special-purpose computer, a computer network, or other programmable devices. The computer instructions can be stored in a computer-readable storage medium, or transmitted from one computer-readable storage medium to another computer-readable storage medium. For example, the computer instructions can be transmitted from a website, computer, server or data center to another website, computer, server or data center via a wired (e.g., coaxial cable, optical fiber, digital subscriber line (DSL)) or wireless (e.g., infrared, wireless, microwave, etc.) mode. The computer-readable storage medium can be any available medium that a computer can access or a data storage device such as a server or data center that includes one or more available media integrations. The available medium can be a magnetic medium, (e.g., a floppy disk, a hard disk, a tape), an optical medium (e.g., a DVD), or a semiconductor medium (e.g., a solid-state drive (SSD)).

Claims

1. A data processing method, characterized in that: include: Performing inner code encoding on n first data streams respectively to obtain n second data streams, wherein the n first data streams are all outer code encoded, the inner code encoding and the outer code encoding are both forward error correction FEC encoding, the n second data streams include at least n inner code codewords, the n inner code codewords are respectively from the n second data streams, the n inner code codewords include n / m codeword sets, each of the codeword sets includes m inner codewords, each of the inner code codewords includes N bits, the N bits include K information bits and P check bits, and n is an integer greater than 1, and n is divisible by m; Performing bit interleaving on the n / m codeword sets respectively to obtain n / m target bit sets, each of the target bit sets including m×N bits; Mapping the m×N bits in each of the target bit sets to obtain m×N / L modulation symbols, so as to obtain a total of n×N / L modulation symbols, wherein each L bits are mapped to a modulation symbol, the m is divisible by the L, and the L bits mapped to one modulation symbol are respectively from L inner code words; If the L bits mapped to one modulation symbol all come from information bits of an inner code word, any two bits of the L bits mapped to one modulation symbol come from two different positions of two different inner code words.

2. The method according to claim 1, characterized in that The N is divisible by the L, the N bits of each of the inner code words are respectively mapped to N modulation symbols, the N bits of the inner code word include L first bit subsets, the bits in the same first bit subset are respectively mapped to the same bit positions of different modulation symbols, and the bits in different first bit subsets are respectively mapped to different bit positions of different modulation symbols.

3. The method according to claim 1 or 2, characterized in that: Performing bit interleaving on the codeword set to obtain the target bit set includes: Performing a first position transformation on K information bits of each inner code word in the code word set to obtain a first bit set; The target bit set is obtained by performing a second position transformation on bits located at the same position in the first bit set.

4. The method according to claim 3, characterized in that Performing a first position transformation on the K information bits of each inner code word in the code word set includes: The K information bits of each inner codeword in the codeword set are cyclically shifted leftward or cyclically shifted rightward.

5. The method according to claim 3 or 4, characterized in that: The codeword set and the first bit set are both represented as bit matrices, the target bit set is represented as a bit matrix or a one-dimensional array, the bit matrix includes m rows and N columns of bits, the one-dimensional array includes m×N bits, and the bits located at the same position in the first bit set are a column of m bits in the bit matrix corresponding to the first bit set.

6. The method according to claim 5, characterized in that The first position change satisfies a first condition, wherein the first condition includes: H1[i][j] represents the bit in the i-th row and j-th column of the bit matrix before the first position transformation, H2[i][j] represents the bit in the i-th row and j-th column of the bit matrix after the first position transformation, Y%Z represents the remainder after the integer Y is divided by the integer Z, Δ is a non-zero integer greater than -K and less than K, 0≤i <m。 7. The method according to any one of claims 3 to 6, characterized in that Each same - position in the first bit set includes m / L second - bit subsets, and each of the second - bit subsets includes L bits. The second - position transformation for the bits at the same position in the first bit set includes: Performing an upward circular shift or a downward circular shift on the m / L second - bit subsets at each same position in the first bit set.

8. The method according to claim 5, characterized in that The second position change satisfies a second condition, wherein the second condition includes: H2[i][j] represents the bit in the i-th row and j-th column of the bit matrix before the second position transformation, and H3[i][j] represents the bit in the i-th row and j-th column of the bit matrix after the second position transformation. Denotes the floor function, Y%Z represents the remainder when integer Y is divided by integer Z, θ is a non - zero integer greater than - L and less than L, 0 ≤ i < m, 0 ≤ j < N.

9. The method according to claim 5, characterized in that The second position change satisfies a third condition, and the third condition includes: H2[i][j] represents the bit in the i-th row and j-th column of the bit matrix before the second position transformation, and H3[i][j] represents the bit in the i-th row and j-th column of the bit matrix after the second position transformation. Denotes the floor function, Y%Z represents the remainder when integer Y is divided by integer Z, Y^Z represents the integer corresponding to the bit sequence obtained by performing an exclusive - OR operation on the bit sequence corresponding to integer Y and the bit sequence corresponding to integer Z, 0 ≤ i < m, 0 ≤ j < N.

10. The method according to claim 5, characterized in that The second - position transformation satisfies the fourth condition, and the fourth condition includes: H3[i][j]=H2[i^(j%L)][j] H2[i][j] represents the bit in the i - th row and j - th column of the bit matrix before the second - position transformation, H3[i][j] represents the bit in the i - th row and j - th column of the bit matrix after the second - position transformation, Y%Z represents the remainder when integer Y is divided by integer Z, Y^Z represents the integer corresponding to the bit sequence obtained by performing an exclusive - OR operation on the bit sequence corresponding to integer Y and the bit sequence corresponding to integer Z, 0 ≤ i < m, 0 ≤ j < N.

11. The method according to claim 1 or 2, characterized in that: The code - word set is represented as a bit matrix, the target bit set is represented as a bit matrix or a one - dimensional array. The bit matrix includes m rows and N columns of bits, and the one - dimensional array includes m×N bits.

12. The method according to claim 11, characterized in that The target bit set is a bit matrix, and the bit interleaving satisfies a fifth condition, wherein the fifth condition includes: H1[i][j] represents the bit in the i-th row and j-th column of the bit matrix before the bit interleaving is performed, H3[i][j] represents the bit in the i-th row and j-th column of the bit matrix after the bit interleaving is performed, Y%Z represents the remainder after the integer Y is divided by the integer Z, Δ is a non-zero integer greater than -K and less than K, Denotes the floor function, θ is a non - zero integer greater than - L and less than L, 0 ≤ i < m.

13. The method according to claim 11, characterized in that The target bit set is a one-dimensional array, and the bit interleaving satisfies a sixth condition, which includes: H1[i][j] represents the bit at the i-th row and j-th column in the bit matrix before the bit interleaving, A[t] represents the t-th bit in the one-dimensional array after the bit interleaving, where 0 ≤ t < m × N, Y % Z represents the remainder when the integer Y is divided by the integer Z, and Δ is a non-zero integer greater than -K and less than K. Denotes the floor function, θ is a non - zero integer greater than - L and less than L, 0 ≤ i < m.

14. The method according to claim 11, characterized in that The target bit set is a bit matrix, and the bit interleaving satisfies a seventh condition, wherein the seventh condition includes: H1[i][j] represents the bit in the i - th row and j - th column of the bit matrix before the bit interleaving, H3[i][j] represents the bit in the i - th row and j - th column of the bit matrix after the bit interleaving, Y%Z represents the remainder when integer Y is divided by integer Z, Δ is a non - zero integer greater than - K and less than K, Y^Z represents the integer corresponding to the bit sequence obtained by performing an exclusive - OR operation on the bit sequence corresponding to integer Y and the bit sequence corresponding to integer Z, 0 ≤ i < m.

15. The method according to claim 11, characterized in that The target bit set is a one-dimensional array, and the bit interleaving satisfies the eighth condition, which includes: H1[i][j] represents the bit in the i - th row and j - th column of the bit matrix before the bit interleaving, A[t] represents the t - th bit in the one - dimensional array after the bit interleaving, 0 ≤ t < m×N, Y%Z represents the remainder when integer Y is divided by integer Z, Δ is a non - zero integer greater than - K and less than K, Y^Z represents the integer corresponding to the bit sequence obtained by performing an exclusive - OR operation on the bit sequence corresponding to integer Y and the bit sequence corresponding to integer Z, 0 ≤ i < m.

16. The method according to any one of claims 1 to 15, characterized in that Mapping the m×N bits in each of the target bit sets to obtain m×N / L modulation symbols includes: Mapping every consecutive L bits at the same position in each of the target bit sets to one modulation symbol to obtain m×N / L modulation symbols.

17. The method according to claim 16, characterized in that The modulation symbol stream includes m×N / L modulation symbols obtained by mapping, and the m / L modulation symbols obtained by mapping the m bits located at the same position in each target bit set are continuous in the modulation symbol stream; Among them, when the target bit set is represented as a bit matrix, the m bits located at the same position in the target bit set are a column of m bits in the bit matrix; when the target bit set is represented as a one-dimensional array, the m bits located at the same position in the target bit set are consecutive m bits in the one-dimensional array.

18. The method according to claim 16, characterized in that The modulation symbol stream includes m×N / L modulation symbols obtained by mapping, each of the target bit sets is represented as a bit matrix including m rows and N columns of bits, the m bits located in one column of each target bit set are mapped to obtain m / L first modulation symbols, each consecutive T first modulation symbols among the m / L first modulation symbols are continuous in the modulation symbol stream, the m bits located in another column of each target bit set are mapped to obtain m / L second modulation symbols, each consecutive T second modulation symbols among the m / L second modulation symbols are continuous in the modulation symbol stream, one of the columns is adjacent to another of the columns, consecutive T first modulation symbols among the m / L first modulation symbols and consecutive T second modulation symbols among the m / L second modulation symbols are continuous in the modulation symbol stream, and m / L is divisible by T.

19. The method according to any one of claims 1 to 18, characterized in that The n first data streams are all processed by identification locking and channel de-skew. When W×L bits in W consecutive modulation symbols are all information bits of inner code words, the W×L bits come from more than 2 outer code words encoded by the outer code, where W≥2.

20. The method according to any one of claims 1 to 19, characterized in that Each of the modulation symbols is a dual-polarization quadrature amplitude modulation DP-16QAM modulation symbol, and each of the modulation symbols includes 8 bits; or, Each of the modulation symbols is a pulse amplitude modulation PAM4 modulation symbol, and each of the modulation symbols includes 2 bits.

21. A data processing method, characterized in that: include: Performing inner code encoding on n first data streams respectively to obtain n second data streams, wherein the n first data streams are all outer code encoded, the inner code encoding and the outer code encoding are both forward error correction FEC encoding, the n second data streams include at least n inner code codewords, the n inner code codewords are respectively from the n second data streams, the n inner code codewords include n / m codeword sets, each of the codeword sets includes m inner codewords, each of the inner code codewords includes N bits, the N bits include K information bits and P check bits, and n is an integer greater than 1, and n is divisible by m; Performing bit interleaving on n / m codeword sets respectively to obtain n / m target bit sets, each of the target bit sets including m×N bits, the bit interleaving comprising performing position transformation on K information bits of each inner codeword in the codeword set; Mapping the m×N bits in each target bit set to obtain m×N / L modulation symbols respectively, so as to obtain a total of n×N / L modulation symbols, wherein each L bits are mapped to a modulation symbol, the m is divisible by the L, and the L bits mapped to a modulation symbol come from the L r inner codewords, the L r Each of the inner code words has L c bits are mapped to the modulation symbol, and the 2L bits mapped to 2 consecutive modulation symbols come from 2L r Inner code words, L = L r ×L c ,L c >1.

22. The method according to claim 21, characterized in that Transforming the positions of the K information bits of each inner codeword in the codeword set includes: The K information bits of each inner codeword in the codeword set are cyclically shifted leftward or cyclically shifted rightward.

23. The method according to claim 21 or 22, characterized in that The codeword set is represented as a bit matrix, and the target bit set is represented as a bit matrix or a one-dimensional array. The bit matrix includes m rows and N columns of bits, and the one-dimensional array includes m×N bits.

24. The method according to claim 23, characterized in that The position change satisfies a target condition, and the target condition includes: H1[i][j] represents the bit in the i-th row and j-th column of the bit matrix before the position transformation, H2[i][j] represents the bit in the i-th row and j-th column of the bit matrix after the position transformation, Y%Z represents the remainder after the integer Y is divided by the integer Z, Δ is a non-zero integer greater than -K and less than K, 0≤i <m。 25. The method according to any one of claims 21 to 24, characterized in that Each of the target bit sets includes m rows and N columns of bits. r Line L c A total of L bits in a column are mapped to one modulation symbol.

26. The method according to claim 25, characterized in that The modulation symbol stream includes m×N / L modulation symbols obtained by mapping, and each L in the target bit set c m / L obtained by column bit mapping r The modulation symbols are continuous in the modulation symbol stream, and the m×N / L modulation symbols obtained by mapping every N columns of bits in the target bit set are continuous in the modulation symbol stream.

27. The method according to claim 25, characterized in that The modulation symbol stream includes m×N / L modulation symbols obtained by mapping, and each of the target bit sets is located in L c The bit mapping of the columns yields m / L r first modulation symbols, the m / L r Each of the T consecutive first modulation symbols in the first modulation symbols is continuous in the modulation symbol stream, and each of the target bit sets is located in another L c The bit mapping of the columns yields m / L r second modulation symbol, the m / L r Every consecutive T second modulation symbols in the modulation symbol stream are consecutive, wherein L c Column and said other L c Columns adjacent, the m / L r The first modulation symbols of the continuous T first modulation symbols are the m / L r T second modulation symbols are continuous in the modulation symbol stream, and the m / L r Divisible by T.

28. The method according to any one of claims 21 to 27, characterized in that Each of the modulation symbols is a dual-polarization quadrature amplitude modulation DP-16QAM modulation symbol, and each of the modulation symbols includes 8 bits; or, Each of the modulation symbols is a pulse amplitude modulation PAM4 modulation symbol, and each of the modulation symbols includes 2 bits.

29. A data processing device, characterized in that: include: Coding module, bit interleaving module and bit mapping module; The encoding module is used to: perform inner code encoding on n first data streams respectively to obtain n second data streams, wherein the n first data streams are all outer code encoded, the inner code encoding and the outer code encoding are both forward error correction FEC encoding, the n second data streams include at least n inner code codewords, the n inner code codewords are respectively from the n second data streams, the n inner code codewords include n / m codeword sets, each of the codeword sets includes m inner codewords, each of the inner code codewords includes N bits, the N bits include K information bits and P check bits, and n is an integer greater than 1, and n is divisible by m; The bit interleaving module is used to: perform bit interleaving on the n / m codeword sets respectively to obtain n / m target bit sets, each of which includes m×N bits; The bit mapping module is used to: respectively map the m×N bits in each of the target bit sets to obtain m×N / L modulation symbols, so as to obtain a total of n×N / L modulation symbols, wherein each L bits are mapped to a modulation symbol, the m is divisible by the L, and the L bits mapped to a modulation symbol are respectively from L inner code words; If the L bits mapped to one modulation symbol all come from information bits of an inner code word, any two bits of the L bits mapped to one modulation symbol come from two different positions of two different inner code words.

30. The data processing device according to claim 29, characterized in that: The N is divisible by the L, the N bits of each of the inner code words are respectively mapped to N modulation symbols, the N bits of the inner code word include L first bit subsets, the bits in the same first bit subset are respectively mapped to the same bit positions of different modulation symbols, and the bits in different first bit subsets are respectively mapped to different bit positions of different modulation symbols.

31. The data processing device according to claim 29 or 30, characterized in that: The bit mapping module is specifically used for: Performing a first position transformation on K information bits of each inner code word in the code word set to obtain a first bit set; The target bit set is obtained by performing a second position transformation on bits located at the same position in the first bit set.

32. The data processing device according to claim 31, characterized in that: The bit mapping module is specifically used for: The K information bits of each inner codeword in the codeword set are cyclically shifted leftward or cyclically shifted rightward.

33. The data processing device according to claim 31 or 32, characterized in that: The codeword set and the first bit set are both represented as bit matrices, the target bit set is represented as a bit matrix or a one-dimensional array, the bit matrix includes m rows and N columns of bits, the one-dimensional array includes m×N bits, and the bits located at the same position in the first bit set are a column of m bits in the bit matrix corresponding to the first bit set.

34. The data processing device according to claim 33, characterized in that: The first position change satisfies a first condition, wherein the first condition includes: H1[i][j] represents the bit in the i-th row and j-th column of the bit matrix before the first position transformation, H2[i][j] represents the bit in the i-th row and j-th column of the bit matrix after the first position transformation, Y%Z represents the remainder after the integer Y is divided by the integer Z, Δ is a non-zero integer greater than -K and less than K, 0≤i <m。 35. The data processing device according to any one of claims 31 to 34, characterized in that: Each same position in the first bit set includes m / L second bit subsets, each of the second bit subsets includes L bits, and the bit mapping module is specifically used to: Perform an upward cyclic shift or a downward cyclic shift on each m / L second bit subsets at the same position in the first bit set.

36. The data processing device according to claim 33, characterized in that: The second position change satisfies a second condition, wherein the second condition includes: H2[i][j] represents the bit in the i-th row and j-th column of the bit matrix before the second position transformation, and H3[i][j] represents the bit in the i-th row and j-th column of the bit matrix after the second position transformation. represents rounding down, Y%Z represents the remainder after the integer Y is divided by the integer Z, θ is a non-zero integer greater than -L and less than L, 0≤i <m,0≤j<N。 37. The data processing device according to claim 33, characterized in that: The second position change satisfies a third condition, and the third condition includes: H2[i][j] represents the bit in the i-th row and j-th column of the bit matrix before the second position transformation, and H3[i][j] represents the bit in the i-th row and j-th column of the bit matrix after the second position transformation. represents rounding down, Y%Z represents the remainder after dividing integer Y by integer Z, Y^Z represents the integer corresponding to the bit sequence obtained by performing an XOR operation on the bit sequence corresponding to integer Y and the bit sequence corresponding to integer Z, 0≤i <m,0≤j<N。 38. The data processing device according to claim 33, characterized in that: The second position transformation satisfies a fourth condition, wherein: H3[i][j]=H2[i^(j%L)][j] H2[i][j] represents the bit in the i-th row and j-th column of the bit matrix before the second position transformation, H3[i][j] represents the bit in the i-th row and j-th column of the bit matrix after the second position transformation, Y%Z represents the remainder after the integer Y is divided by the integer Z, Y^Z represents the integer corresponding to the bit sequence obtained by performing an XOR operation on the bit sequence corresponding to the integer Y and the bit sequence corresponding to the integer Z, 0≤i <m,0≤j<N。 39. The data processing device according to claim 29 or 30, characterized in that: The codeword set is represented as a bit matrix, and the target bit set is represented as a bit matrix or a one-dimensional array. The bit matrix includes m rows and N columns of bits, and the one-dimensional array includes m×N bits.

40. The data processing device according to claim 39, characterized in that: The target bit set is a bit matrix, and the bit interleaving satisfies a fifth condition, wherein the fifth condition includes: H1[i][j] represents the bit in the i-th row and j-th column of the bit matrix before the bit interleaving is performed, H3[i][j] represents the bit in the i-th row and j-th column of the bit matrix after the bit interleaving is performed, Y%Z represents the remainder after the integer Y is divided by the integer Z, Δ is a non-zero integer greater than -K and less than K, Indicates rounding down, θ is a non-zero integer greater than -L and less than L, 0≤i <m。 41. The data processing device according to claim 39, characterized in that: The target bit set is a one-dimensional array, and the bit interleaving satisfies a sixth condition, which includes: H1[i][j] represents the bit at the i-th row and j-th column in the bit matrix before the bit interleaving, A[t] represents the t-th bit in the one-dimensional array after the bit interleaving, where 0 ≤ t < m × N, Y % Z represents the remainder of the integer Y divided by the integer Z, and Δ is a non-zero integer greater than -K and less than K. Indicates rounding down, θ is a non-zero integer greater than -L and less than L, 0≤i <m。 42. The data processing device according to claim 39, characterized in that: The target bit set is a bit matrix, and the bit interleaving satisfies a seventh condition, wherein the seventh condition includes: H1[i][j] represents the bit at the i-th row and j-th column in the bit matrix before the bit interleaving, H3[i][j] represents the bit at the i-th row and j-th column in the bit matrix after the bit interleaving, Y % Z represents the remainder of integer Y divided by integer Z, Δ is a non-zero integer greater than -K and less than K, Y^Z represents the integer corresponding to the bit sequence obtained by performing an exclusive OR operation on the bit sequence corresponding to integer Y and the bit sequence corresponding to integer Z, and 0 ≤ i < m.

43. The data processing device according to claim 39, characterized in that: The target bit set is a one-dimensional array, and the bit interleaving satisfies the eighth condition, which includes: H1[i][j] represents the bit at the i-th row and j-th column in the bit matrix before the bit interleaving, A[t] represents the t-th bit in the one-dimensional array after the bit interleaving, 0 ≤ t < m × N, Y % Z represents the remainder of integer Y divided by integer Z, Δ is a non-zero integer greater than -K and less than K, Y^Z represents the integer corresponding to the bit sequence obtained by performing an exclusive OR operation on the bit sequence corresponding to integer Y and the bit sequence corresponding to integer Z, and 0 ≤ i < m.

44. The data processing device according to any one of claims 29 to 43, characterized in that: The bit mapping module is specifically configured to: Map every consecutive L bits at the same position in each of the target bit sets into a modulation symbol to obtain m × N / L modulation symbols.

45. The data processing device according to claim 44, characterized in that The modulation symbol stream includes the m × N / L modulation symbols obtained by mapping. The m / L modulation symbols obtained by mapping the m bits at the same position in each of the target bit sets are consecutive in the modulation symbol stream; Wherein, when the target bit set is represented as a bit matrix, the m bits at the same position in the target bit set are the m bits in one column of the bit matrix; when the target bit set is represented as a one-dimensional array, the m bits at the same position in the target bit set are m consecutive bits in the one-dimensional array.

46. ​​The data processing device according to claim 44, characterized in that The modulation symbol stream includes the m × N / L modulation symbols obtained by mapping. Each of the target bit sets is represented as a bit matrix including m rows and N columns of bits. The m bits in one column of each of the target bit sets are mapped to obtain m / L first modulation symbols. Every consecutive T of the m / L first modulation symbols are consecutive in the modulation symbol stream. The m bits in another column of each of the target bit sets are mapped to obtain m / L second modulation symbols. Every consecutive T of the m / L second modulation symbols are consecutive in the modulation symbol stream. The one column and the another column are adjacent. Every consecutive T of the m / L first modulation symbols and every consecutive T of the m / L second modulation symbols are consecutive in the modulation symbol stream, and m / L is divisible by T.

47. The data processing device according to any one of claims 29 to 46, characterized in that: All of the n first data streams undergo identification locking and channel deviation correction processing. When the W × L bits in W consecutive modulation symbols are all information bits of the inner code codewords, the W × L bits come from more than 2 outer code codewords that have undergone the outer code encoding, where W ≥ 2.

48. The data processing device according to any one of claims 29 to 47, characterized in that: Each of the modulation symbols is a dual-polarization quadrature amplitude modulation DP-16QAM modulation symbol, and each of the modulation symbols includes 8 bits; Or, Each of the modulation symbols is a pulse amplitude modulation PAM4 modulation symbol, and each of the modulation symbols includes 2 bits.

49. A data processing device, characterized in that: include: Coding module, bit interleaving module and bit mapping module; The encoding module is used to: perform inner code encoding on n first data streams respectively to obtain n second data streams, wherein the n first data streams are all outer code encoded, the inner code encoding and the outer code encoding are both forward error correction FEC encoding, the n second data streams include at least n inner code codewords, the n inner code codewords are respectively from the n second data streams, the n inner code codewords include n / m codeword sets, each of the codeword sets includes m inner codewords, each of the inner code codewords includes N bits, the N bits include K information bits and P check bits, and n is an integer greater than 1, and n is divisible by m; The bit interleaving module is used to: perform bit interleaving on n / m codeword sets respectively to obtain n / m target bit sets, each of which includes m×N bits, and the bit interleaving includes position transformation of K information bits of each inner codeword in the codeword set; The bit mapping module is used to: respectively map the m×N bits in each of the target bit sets to obtain m×N / L modulation symbols, so as to obtain a total of n×N / L modulation symbols, wherein each L bits are mapped to a modulation symbol, the m is divisible by the L, and the L bits mapped to a modulation symbol come from the L r inner codewords, the L r Each of the inner code words has L c bits are mapped to the modulation symbol, and the 2L bits mapped to 2 consecutive modulation symbols come from 2L r Inner code words, L = L r ×L c ,L c >1.

50. The data processing device according to claim 49, characterized in that: The bit interleaving module is specifically used for: The K information bits of each inner codeword in the codeword set are cyclically shifted leftward or cyclically shifted rightward.

51. The data processing device according to claim 49 or 50, characterized in that: The codeword set is represented as a bit matrix, and the target bit set is represented as a bit matrix or a one-dimensional array. The bit matrix includes m rows and N columns of bits, and the one-dimensional array includes m×N bits.

52. The data processing device according to claim 51, characterized in that: The position change satisfies a target condition, and the target condition includes: H1[i][j] represents the bit in the i-th row and j-th column of the bit matrix before the position transformation, H2[i][j] represents the bit in the i-th row and j-th column of the bit matrix after the position transformation, Y%Z represents the remainder after the integer Y is divided by the integer Z, Δ is a non-zero integer greater than -K and less than K, 0≤i <m。 53. The data processing device according to any one of claims 49 to 52, characterized in that: Each of the target bit sets includes m rows and N columns of bits. r Line L c A total of L bits in a column are mapped to one modulation symbol.

54. The data processing device according to claim 53, characterized in that: The modulation symbol stream includes m×N / L modulation symbols obtained by mapping, and each L in the target bit set c m / L obtained by column bit mapping r The modulation symbols are continuous in the modulation symbol stream, and the m×N / L modulation symbols obtained by mapping every N columns of bits in the target bit set are continuous in the modulation symbol stream.

55. The data processing device according to claim 53, characterized in that: The modulation symbol stream includes m×N / L modulation symbols obtained by mapping, and each of the target bit sets is located in L c The bit mapping of the columns yields m / L r first modulation symbols, the m / L r Each of the T consecutive first modulation symbols in the first modulation symbols is continuous in the modulation symbol stream, and each of the target bit sets is located in another L c The bit mapping of the columns yields m / L r second modulation symbol, the m / L r Every consecutive T second modulation symbols in the modulation symbol stream are consecutive, wherein L c Column and said other L c The columns are adjacent, the m / L r The first modulation symbols of the continuous T first modulation symbols are the m / L r T second modulation symbols are continuous in the modulation symbol stream, and the m / L r Divisible by T.

56. The data processing device according to any one of claims 49 to 55, characterized in that: Each of the modulation symbols is a dual-polarization quadrature amplitude modulation DP-16QAM modulation symbol, and each of the modulation symbols includes 8 bits; or, Each of the modulation symbols is a pulse amplitude modulation PAM4 modulation symbol, and each of the modulation symbols includes 2 bits.

57. A data processing method, characterized in that: include: Performing interleaving coding processing on each n1 first data streams among the n0 first data streams to obtain one second data stream, so as to obtain a total of n2 second data streams, n2=n0 / n1, wherein n0 is an integer greater than 1, and n1 is an integer greater than 0; Mapping each 2 bits in the n2 second data streams into one PAM4 symbol respectively, to obtain a total of n2 PAM4 symbol data streams; The interleaving encoding process comprises: Obtain a0 first bit sets from each of the n1 first data streams to obtain a total of m=n1×a0 first bit sets, wherein the n1 first data streams are all encoded by an outer code, each of the first bit sets includes K bits, and the n1, a0, and K are all integers greater than 1; Performing inner code encoding on the m first bit sets respectively to obtain m inner code codewords, wherein both the inner code encoding and the outer code encoding are forward error correction FEC encoding, and each of the inner code codewords includes a first bit set participating in the inner code encoding and a check bit set, which has a total of N bits, where N=K+P, and each of the check bit sets includes P bits, where P is an integer greater than or equal to 1; Cyclic shift is performed on the m inner code words respectively to obtain m third bit sets, each of the third bit sets includes a second bit set obtained by cyclic shifting the first bit set and a check bit set; Polling to obtain 2 bits from each of the third bit sets to obtain a fourth bit set, the fourth bit set including m×N bits, a total of m×K bits from the m second bit sets in the fourth bit set are continuous, and a total of m×P bits from the m check bit sets in the fourth bit set are continuous; Among them, each of the second data streams includes multiple fourth bit sets, and each of the fourth bit sets obtains a total of m×N / 2 PAM4 symbols after the mapping, wherein the m×2 bits mapped to m consecutive PAM4 symbols in the m×N / 2 PAM4 symbols come from the m inner code words.

58. The method according to claim 57, characterized in that Each of the first data streams is outer code encoded, and 20 consecutive bits in the first data stream are interleaved and mapped to obtain at least 10 PAM4 symbols, the consecutive 20 bits come from 2 outer code symbols of an outer code codeword, and any two of the at least 10 PAM4 symbols are separated by at least 2 PAM4 symbols in the PAM4 symbol data stream.

59. The method according to claim 57 or 58, characterized in that The number of bits cyclically shifted in any two of the m first bit sets is different.

60. The method according to any one of claims 57 to 59, characterized in that The m inner code words and the m third bit sets are both represented as a bit matrix, and the bit matrix includes m rows and N columns of bits.

61. The method according to claim 60, characterized in that The second bit set is cyclically shifted to the left by the first bit set bits are obtained, the left cyclic shift satisfies a first condition, and the first condition includes: Among them, M c [i][j] represents the bit in the i-th row and j-th column of the bit matrix corresponding to the m inner code words before the left cyclic shift, M3[i][j] represents the bit in the i-th row and j-th column of the bit matrix corresponding to the m third bit sets after the left cyclic shift, Y%Z represents the remainder after the integer Y is divided by the integer Z, 0≤i <m, 62. The method according to claim 60, characterized in that The second bit set is cyclically shifted right by δ from the first bit set i bits are obtained, the right cyclic shift satisfies the second condition, and the second condition includes: Among them, M c [i][j] represents the bit in the i-th row and j-th column of the bit matrix corresponding to the m inner code words before the right cyclic shift, M3[i][j] represents the bit in the i-th row and j-th column of the bit matrix corresponding to the m third bit sets after the right cyclic shift, Y%Z represents the remainder after the integer Y is divided by the integer Z, 0≤i <m,0≤δ i <K。 63. The method according to any one of claims 60 to 62, characterized in that The m third bit sets and the fourth bit set satisfy a third condition, and the third condition includes: Wherein, M3[i][j] represents the bit in the i-th row and j-th column in the bit matrix corresponding to the m third bit sets, Indicates the fourth bit set bits, 0≤i <m,0≤j<N, Indicates a floor operation.

64. The method of claim 57, 58, 59, 60, 61 or 63, wherein: K = 120, m = 8, the i-th second bit set is cyclically shifted to the left by the i-th first bit set bits are obtained, 0≤i<8, The value of satisfies the first value item Any one of the items, the first value item Including: {0,30,60,90,110,20,50,80}; {0,30,90,60,110,20,80,50}; {0,60,30,90,110,50,20,80}; {0,60,90,30,110,50,80,20}; {0,90,30,60,110,80,20,50}; {0,90,60,30,110,80,50,20}.

65. The method of claim 57, 58, 59, 60, 62 or 63, wherein: K = 120, m = 8, the i-th second bit set is cyclically shifted right by δ from the i-th first bit set i bits, 0≤i<8,δ i The value of satisfies any one of the second value items {δ0,δ1,δ2,δ3,δ4,δ5,δ6,δ7}, and the second value items {δ0,δ1,δ2,δ3,δ4,δ5,δ6,δ7} include: {0,30,60,90,10,40,70,100}; {0,30,90,60,10,40,100,70}; {0,60,30,90,10,40,40,100}; {0,60,90,30,10,70,100,40}; {0,90,30,60,10,100,40,70}; {0,90,60,30,10,100,70,40}.

66. A data processing method, characterized in that: include: Performing interleaving coding processing on each n1 first data streams among the n0 first data streams to obtain one second data stream, so as to obtain a total of n2 second data streams, n2=n0 / n1, wherein n0 is an integer greater than 1, and n1 is an integer greater than 0; Mapping each 2 bits in the n2 second data streams into one PAM4 symbol respectively, to obtain a total of n2 PAM4 symbol data streams; The interleaving encoding process comprises: Obtain a0 first bit sets from each of the n1 first data streams to obtain a total of m=n1×a0 first bit sets, wherein the n1 first data streams are all encoded by an outer code, each of the first bit sets includes K bits, and the n1, a0, and K are all integers greater than 1; Performing cyclic shift on the m first bit sets respectively to obtain m second bit sets, and performing inner code encoding on the m first bit sets respectively to obtain m check bit sets, wherein both the inner code encoding and the outer code encoding are forward error correction FEC encoding, each of the second bit sets includes K bits, and each of the check bit sets includes P bits, where P is an integer greater than or equal to 1; Polling to obtain 2 bits from each of the second bit sets to obtain a total of m×K consecutive bits, and polling to obtain 2 bits from each of the check bit sets to obtain a total of m×P consecutive bits, so as to obtain a third bit set including m×N bits, N=K+P; Among them, each of the second data streams includes multiple third bit sets, each of the third bit sets contains m×K bits of the second bit set and m×P bits of the check bit set, the m×K bits from the second bit set in each of the third bit sets are mapped to obtain a total of m×K / 2 PAM4 symbols, the m×P bits from the check bit set in each of the third bit sets are mapped to obtain a total of m×P / 2 PAM4 symbols, and the m×2 bits mapped to m consecutive PAM4 symbols in the total m×N / 2 PAM4 symbols come from the m second bit sets and / or the m check bit sets.

67. The method according to claim 66, characterized in that Each of the first data streams is outer code encoded, and 20 consecutive bits in the first data stream are interleaved and mapped to obtain at least 10 PAM4 symbols, the consecutive 20 bits come from 2 outer code symbols of an outer code codeword, and any two of the at least 10 PAM4 symbols are separated by at least 2 PAM4 symbols in the PAM4 symbol data stream.

68. The method according to claim 66 or 67, characterized in that The number of bits cyclically shifted in any two of the m first bit sets is different.

69. The method according to any one of claims 66 to 68, characterized in that The m first bit sets and the m second bit sets are both represented as a bit matrix, and the bit matrix includes m rows and K columns of bits.

70. The method according to claim 69, characterized in that The second bit set is cyclically shifted to the left by the first bit set bits are obtained, the left cyclic shift satisfies a first condition, and the first condition includes: Wherein, M1[i][j] represents the bit in the i-th row and j-th column of the bit matrix corresponding to the m first bit sets before the left cyclic shift, M2[i][j] represents the bit in the i-th row and j-th column of the bit matrix corresponding to the m second bit sets after the left cyclic shift, Y%Z represents the remainder after the integer Y is divided by the integer Z, and 0≤j <K,0≤i<m, 71. The method according to claim 69, characterized in that The second bit set is cyclically shifted right by δ from the first bit set i bits, the rightward cyclic shift satisfies the second condition, which includes: M2[i][j]=M1[i][(j-δ i )% K] Wherein, M1[i][j] represents the bit in the i-th row and j-th column of the bit matrix corresponding to the m first bit sets before the right cyclic shift, M2[i][j] represents the bit in the i-th row and j-th column of the bit matrix corresponding to the m second bit sets after the right cyclic shift, Y%Z represents the remainder after the integer Y is divided by the integer Z, and 0≤j <K,0≤i<m,0≤δ i <K。 72. The method according to any one of claims 66 to 70, characterized in that K = 120, m = 8, the i-th second bit set is cyclically shifted to the left by the i-th first bit set bits are obtained, 0≤i<8, The value of satisfies the first value item Any one of the items, the first value item Including: {0,30,60,90,110,20,50,80}; {0,30,90,60,110,20,80,50}; {0,60,30,90,110,50,20,80}; {0,60,90,30,110,50,80,20}; {0,90,30,60,110,80,20,50}; {0,90,60,30,110,80,50,20}.

73. The method of claim 66, 67, 68, 69 or 71, wherein: K = 120, m = 8, the i-th second bit set is cyclically shifted right by δ from the i-th first bit set i bits, 0≤i<8,δ i The value of satisfies any one of the second value items {δ0,δ1,δ2,δ3,δ4,δ5,δ6,δ7}, and the second value items {δ0,δ1,δ2,δ3,δ4,δ5,δ6,δ7} include: {0,30,60,90,10,40,70,100}; {0,30,90,60,10,40,100,70}; {0,60,30,90,10,40,40,100}; {0,60,90,30,10,70,100,40}; {0,90,30,60,10,100,40,70}; {0,90,60,30,10,100,70,40}.

74. A data processing method, characterized in that: include: Performing interleaving coding processing on each n1 first data streams among the n0 first data streams to obtain one second data stream, so as to obtain a total of n2 second data streams, n2=n0 / n1, wherein n0 is an integer greater than 1, and n1 is an integer greater than 0; Mapping each 2 bits in the n2 second data streams into one PAM4 symbol respectively, to obtain a total of n2 PAM4 symbol data streams; The interleaving encoding process comprises: Obtain a0 first bit sets from each of the n1 first data streams to obtain a total of m=n1×a0 first bit sets, wherein the n1 first data streams are all encoded by an outer code, each of the first bit sets includes K bits, and the n1, a0, and K are all integers greater than 1; Cyclic shift is performed on the m first bit sets respectively to obtain m second bit sets, each of the second bit sets includes K bits; Performing inner code encoding on the m second bit sets respectively to obtain m inner code codewords, the inner code encoding and the outer code encoding are both forward error correction FEC encoding, each of the inner code codewords includes one second bit set participating in the inner code encoding and one check bit set, totaling N bits, N=K+P, each of the check bit sets includes P bits, and P is an integer greater than or equal to 1; Polling to obtain 2 bits from each of the inner code words to obtain a third bit set, the third bit set includes m×N bits, a total of m×K bits from the m second bit sets in the third bit set are continuous, and a total of m×P bits from the m check bit sets in the third bit set are continuous; Among them, each of the second data streams includes multiple third bit sets, and each of the third bit sets obtains a total of m×N / 2 PAM4 symbols after the mapping, wherein the m×2 bits mapped to m consecutive PAM4 symbols in the m×N / 2 PAM4 symbols come from the m inner code words.

75. The method according to claim 74, characterized in that Each of the first data streams is outer code encoded, and 20 consecutive bits in the first data stream are interleaved and mapped to obtain at least 10 PAM4 symbols, the consecutive 20 bits come from 2 outer code symbols of an outer code codeword, and any two of the at least 10 PAM4 symbols are separated by at least 2 PAM4 symbols in the PAM4 symbol data stream.

76. The method according to claim 74 or 75, characterized in that The number of bits cyclically shifted in any two of the m first bit sets is different.

77. The method according to any one of claims 74 to 76, characterized in that The m first bit sets and the m second bit sets are both represented as a bit matrix, and the bit matrix includes m rows and K columns of bits.

78. The method according to claim 77, characterized in that The second bit set is cyclically shifted to the left by the first bit set bits are obtained, the left cyclic shift satisfies a first condition, and the first condition includes: Wherein, M1[i][j] represents the bit in the i-th row and j-th column of the bit matrix corresponding to the m first bit sets before the left cyclic shift, M2[i][j] represents the bit in the i-th row and j-th column of the bit matrix corresponding to the m second bit sets after the left cyclic shift, Y%Z represents the remainder after the integer Y is divided by the integer Z, 0≤i <m,0≤j<K, 79. The method according to claim 77, characterized in that The second bit set is cyclically shifted right by δ from the first bit set i bits, the rightward cyclic shift satisfies the second condition, which includes: M2[i][j]=M1[i][(j-δ i )% K] Wherein, M1[i][j] represents the bit in the i-th row and j-th column of the bit matrix corresponding to the m first bit sets before the right cyclic shift, M2[i][j] represents the bit in the i-th row and j-th column of the bit matrix corresponding to the m second bit sets after the right cyclic shift, Y%Z represents the remainder after the integer Y is divided by the integer Z, 0≤i <m,0≤j<K,0≤δ i <K。 80. The method according to any one of claims 77 to 79, characterized in that The m inner code words are represented as a bit matrix including m rows and N columns, and the m inner code words and the third bit set satisfy a third condition, and the third condition includes: Among them, M c [i][j] represents the bit in the i-th row and j-th column of the bit matrix corresponding to the m inner code words, Indicates the first bit in the third bit set bits, 0≤i <m,0≤j<N, Indicates a floor operation.

81. The method of claim 74, 75, 76, 77, 78 or 80, wherein: K = 120, m = 8, the i-th second bit set is cyclically shifted to the left by the i-th first bit set bits are obtained, 0≤i<8, The value of satisfies the first value item Any one of the items, the first value item Including: {0,30,60,90,110,20,50,80}; {0,30,90,60,110,20,80,50}; {0,60,30,90,110,50,20,80}; {0,60,90,30,110,50,80,20}; {0,90,30,60,110,80,20,50}; {0,90,60,30,110,80,50,20}.

82. The method of claim 74, 75, 76, 77, 79 or 80, wherein: K = 120, m = 8, the i-th second bit set is cyclically shifted right by δ from the i-th first bit set i bits, 0≤i<8,δ i The value of satisfies any one of the second value items {δ0,δ1,δ2,δ3,δ4,δ5,δ6,δ7}, and the second value items {δ0,δ1,δ2,δ3,δ4,δ5,δ6,δ7} include: {0,30,60,90,10,40,70,100}; {0,30,90,60,10,40,100,70}; {0,60,30,90,10,40,40,100}; {0,60,90,30,10,70,100,40}; {0,90,30,60,10,100,40,70}; {0,90,60,30,10,100,70,40}.

83. A data processing method, characterized in that: include: Performing interleaving coding processing on each n1 first data streams among the n0 first data streams to obtain one second data stream, so as to obtain a total of n2 second data streams, n2=n0 / n1, wherein n0 is an integer greater than 1, and n1 is an integer greater than 0; Mapping each 2 bits in the n2 second data streams into one PAM4 symbol respectively, to obtain a total of n2 PAM4 symbol data streams; The interleaving encoding process comprises: Obtain a0 first bit sets from each of the n1 first data streams to obtain a total of m=n1×a0 first bit sets, wherein the n1 first data streams are all encoded by an outer code, each of the first bit sets includes K bits, and the n1, a0, and K are all integers greater than 1; Performing inner code encoding on the m first bit sets respectively to obtain m inner code codewords, wherein both the inner code encoding and the outer code encoding are forward error correction FEC encoding, and each of the inner code codewords includes a first bit set participating in the inner code encoding and a check bit set, which has a total of N bits, where N=K+P, and each of the check bit sets includes P bits, where P is an integer greater than or equal to 1; The m inner code words are interleaved to obtain a second bit set, the second bit set includes m×N bits, and the first bit in the second bit set is bits satisfy the first condition or the second condition, 0≤i <m,0≤j<N; The first condition includes: in, Indicates the first bit in the second bit set bits, represents the first bits, C i [j] represents the j-th bit in the i-th inner code word; The second condition includes: in, Indicates the first bit in the second bit set bits, C i [(j-δ i )%K] represents the (j-δ i )% K bits, C i [j] represents the j-th bit in the i-th inner code word; Each of the second data streams includes multiple second bit sets, and each of the second bit sets obtains a total of m×N / 2 PAM4 symbols after the mapping, wherein the m×2 bits mapped to m consecutive PAM4 symbols in the m×N / 2 PAM4 symbols come from the m inner code words.

84. The method according to claim 83, characterized in that K = 120, m = 8, The value of satisfies the first value item Any one of the items, the first value item Includes: {0,30,60,90,110,20,50,80}; {0,30,90,60,110,20,80,50}; {0,60,30,90,110,50,20,80}; {0,60,90,30,110,50,80,20}; {0,90,30,60,110,80,20,50}; {0,90,60,30,110,80,50,20}; δ i The value of satisfies any one of the second value items {δ0,δ1,δ2,δ3,δ4,δ5,δ6,δ7}, and the second value items {δ0,δ1,δ2,δ3,δ4,δ5,δ6,δ7} include: {0,30,60,90,10,40,70,100}； {0,30,90,60,10,40,100,70}； {0,60,30,90,10,40,40,100}； {0,60,90,30,10,70,100,40}； {0,90,30,60,10,100,40,70}； {0,90,60,30,10,100,70,40}。 85. A data processing device, characterized in that: include: Interleaving coding module and bit mapping module; The interleaving coding module is used to: perform interleaving coding processing on each n1 first data streams among the n0 first data streams to obtain one second data stream, so as to obtain a total of n2 second data streams, n2=n0 / n1, wherein n0 is an integer greater than 1, and n1 is an integer greater than 0; The bit mapping module is used to: map each 2 bits in the n2 second data streams into 1 PAM4 symbol, so as to obtain a total of n2 PAM4 symbol data streams; The interleaving encoding module is specifically used to: obtain a0 first bit sets from each of the n1 first data streams to obtain a total of m=n1×a0 first bit sets, wherein the n1 first data streams are all encoded by outer codes, each of the first bit sets includes K bits, and the n1, a0 and K are all integers greater than 1; Performing inner code encoding on the m first bit sets respectively to obtain m inner code codewords, wherein both the inner code encoding and the outer code encoding are forward error correction FEC encoding, and each of the inner code codewords includes a first bit set participating in the inner code encoding and a check bit set, which has a total of N bits, where N=K+P, and each of the check bit sets includes P bits, where P is an integer greater than or equal to 1; Cyclic shift is performed on the m inner code words respectively to obtain m third bit sets, each of the third bit sets includes a second bit set obtained by cyclic shifting the first bit set and a check bit set; Polling to obtain 2 bits from each of the third bit sets to obtain a fourth bit set, the fourth bit set including m×N bits, a total of m×K bits from the m second bit sets in the fourth bit set are continuous, and a total of m×P bits from the m check bit sets in the fourth bit set are continuous; Among them, each of the second data streams includes multiple fourth bit sets, and each of the fourth bit sets obtains a total of m×N / 2 PAM4 symbols after the mapping, wherein the m×2 bits mapped to m consecutive PAM4 symbols in the m×N / 2 PAM4 symbols come from the m inner code words.

86. The data processing device according to claim 85, characterized in that: Each of the first data streams is outer code encoded, and 20 consecutive bits in the first data stream are interleaved and mapped to obtain at least 10 PAM4 symbols, the consecutive 20 bits come from 2 outer code symbols of an outer code codeword, and any two of the at least 10 PAM4 symbols are separated by at least 2 PAM4 symbols in the PAM4 symbol data stream.

87. The data processing device according to claim 85 or 86, characterized in that: The number of bits cyclically shifted in any two of the m first bit sets is different.

88. The data processing device according to any one of claims 85 to 87, characterized in that: The m inner code words and the m third bit sets are both represented as a bit matrix, and the bit matrix includes m rows and N columns of bits.

89. The data processing device according to claim 88, characterized in that: The second bit set is cyclically shifted to the left by the first bit set bits are obtained, the left cyclic shift satisfies a first condition, and the first condition includes: Among them, M c [i][j] represents the bit in the i-th row and j-th column of the bit matrix corresponding to the m inner code words before the left cyclic shift, M3[i][j] represents the bit in the i-th row and j-th column of the bit matrix corresponding to the m third bit sets after the left cyclic shift, Y%Z represents the remainder after the integer Y is divided by the integer Z, 0≤i <m, 90. The data processing device according to claim 88, characterized in that: The second bit set is cyclically shifted right by δ from the first bit set i bits are obtained, the right cyclic shift satisfies the second condition, and the second condition includes: Among them, M c [i][j] represents the bit in the i-th row and j-th column of the bit matrix corresponding to the m inner code words before the right cyclic shift, M3[i][j] represents the bit in the i-th row and j-th column of the bit matrix corresponding to the m third bit sets after the right cyclic shift, Y%Z represents the remainder after the integer Y is divided by the integer Z, 0≤i <m,0≤δ i <K。 91. The data processing device according to any one of claims 88 to 90, characterized in that: The m third bit sets and the fourth bit set satisfy a third condition, and the third condition includes: Wherein, M3[i][j] represents the bit in the i-th row and j-th column in the bit matrix corresponding to the m third bit sets, Indicates the fourth bit set bits, 0≤i <m,0≤j<N, Indicates a floor operation.

92. The data processing apparatus according to claim 85, 86, 87, 88, 89 or 91, characterized in that: K = 120, m = 8, the i-th second bit set is cyclically shifted to the left by the i-th first bit set bits are obtained, 0≤i<8, The value of satisfies the first value item Any one of the items, the first value item Including: {0,30,60,90,110,20,50,80}; {0,30,90,60,110,20,80,50}; {0,60,30,90,110,50,20,80}; {0,60,90,30,110,50,80,20}; {0,90,30,60,110,80,20,50}; {0,90,60,30,110,80,50,20}.

93. The data processing apparatus according to claim 85, 86, 87, 88, 90 or 91, characterized in that: K = 120, m = 8, the i-th second bit set is cyclically shifted right by δ from the i-th first bit set i bits, 0≤i<8,δ i The value of satisfies any one of the second value items {δ0,δ1,δ2,δ3,δ4,δ5,δ6,δ7}, and the second value items {δ0,δ1,δ2,δ3,δ4,δ5,δ6,δ7} include: {0,30,60,90,10,40,70,100}; {0,30,90,60,10,40,100,70}; {0,60,30,90,10,40,40,100}; {0,60,90,30,10,70,100,40}; {0,90,30,60,10,100,40,70}; {0,90,60,30,10,100,70,40}.

94. A data processing device, characterized in that: include: Interleaving coding module and bit mapping module; The interleaving coding module is used to: perform interleaving coding processing on each n1 first data streams among the n0 first data streams to obtain one second data stream, so as to obtain a total of n2 second data streams, n2=n0 / n1, wherein n0 is an integer greater than 1, and n1 is an integer greater than 0; The bit mapping module is used to: map each 2 bits in the n2 second data streams into 1 PAM4 symbol, so as to obtain a total of n2 PAM4 symbol data streams; The interleaving encoding module is specifically used to: obtain a0 first bit sets from each of the n1 first data streams to obtain a total of m=n1×a0 first bit sets, wherein the n1 first data streams are all encoded by outer codes, each of the first bit sets includes K bits, and the n1, a0 and K are all integers greater than 1; Performing cyclic shift on the m first bit sets respectively to obtain m second bit sets, and performing inner code encoding on the m first bit sets respectively to obtain m check bit sets, wherein both the inner code encoding and the outer code encoding are forward error correction FEC encoding, each of the second bit sets includes K bits, and each of the check bit sets includes P bits, where P is an integer greater than or equal to 1; Polling to obtain 2 bits from each of the second bit sets to obtain a total of m×K consecutive bits, and polling to obtain 2 bits from each of the check bit sets to obtain a total of m×P consecutive bits, so as to obtain a third bit set including m×N bits, N=K+P; Among them, each of the second data streams includes multiple third bit sets, each of the third bit sets contains m×K bits of the second bit set and m×P bits of the check bit set, the m×K bits from the second bit set in each of the third bit sets are mapped to obtain a total of m×K / 2 PAM4 symbols, the m×P bits from the check bit set in each of the third bit sets are mapped to obtain a total of m×P / 2 PAM4 symbols, and the m×2 bits mapped to m consecutive PAM4 symbols in the total m×N / 2 PAM4 symbols come from the m second bit sets and / or the m check bit sets.

95. The data processing device according to claim 94, characterized in that: Each of the first data streams is outer code encoded, and 20 consecutive bits in the first data stream are interleaved and mapped to obtain at least 10 PAM4 symbols, the consecutive 20 bits come from 2 outer code symbols of an outer code codeword, and any two of the at least 10 PAM4 symbols are separated by at least 2 PAM4 symbols in the PAM4 symbol data stream.

96. The data processing device according to claim 94 or 95, characterized in that: The number of bits cyclically shifted in any two of the m first bit sets is different.

97. The data processing device according to any one of claims 94 to 96, characterized in that: The m first bit sets and the m second bit sets are both represented as a bit matrix, and the bit matrix includes m rows and K columns of bits.

98. The data processing device according to claim 97, characterized in that: The second bit set is cyclically shifted to the left by the first bit set bits are obtained, the left cyclic shift satisfies a first condition, and the first condition includes: Wherein, M1[i][j] represents the bit in the i-th row and j-th column of the bit matrix corresponding to the m first bit sets before the left cyclic shift, M2[i][j] represents the bit in the i-th row and j-th column of the bit matrix corresponding to the m second bit sets after the left cyclic shift, Y%Z represents the remainder after the integer Y is divided by the integer Z, and 0≤j <K,0≤i<m, 99. The data processing device according to claim 97, characterized in that: The second bit set is cyclically shifted right by δ from the first bit set i bits, the rightward cyclic shift satisfies the second condition, which includes: M2[i][j]=M1[i][(j-δ i )% K] Wherein, M1[i][j] represents the bit in the i-th row and j-th column of the bit matrix corresponding to the m first bit sets before the right cyclic shift, M2[i][j] represents the bit in the i-th row and j-th column of the bit matrix corresponding to the m second bit sets after the right cyclic shift, Y%Z represents the remainder after the integer Y is divided by the integer Z, and 0≤j <K,0≤i<m,0≤δ i <K。 100. The data processing device according to any one of claims 94 to 98, characterized in that: K = 120, m = 8, the i-th second bit set is cyclically shifted to the left by the i-th first bit set bits are obtained, 0≤i<8, The value of satisfies the first value item Any item in Including: {0,30,60,90,110,20,50,80}; {0,30,90,60,110,20,80,50}; {0,60,30,90,110,50,20,80}; {0,60,90,30,110,50,80,20}; {0,90,30,60,110,80,20,50}; {0,90,60,30,110,80,50,20}.

101. The data processing device according to claim 94, 95, 96, 97 or 99, characterized in that: K = 120, m = 8, the i-th second bit set is cyclically shifted right by δ from the i-th first bit set i bits, 0≤i<8,δ i The value of satisfies any one of the second value items {δ0,δ1,δ2,δ3,δ4,δ5,δ6,δ7}, and the second value items {δ0,δ1,δ2,δ3,δ4,δ5,δ6,δ7} include: {0,30,60,90,10,40,70,100}; {0,30,90,60,10,40,100,70}; {0,60,30,90,10,40,40,100}; {0,60,90,30,10,70,100,40}; {0,90,30,60,10,100,40,70}; {0,90,60,30,10,100,70,40}.

102. A data processing device, characterized in that: include: Interleaving coding module and bit mapping module; The interleaving coding module is used to: perform interleaving coding processing on each n1 first data streams among the n0 first data streams to obtain one second data stream, so as to obtain a total of n2 second data streams, n2=n0 / n1, wherein n0 is an integer greater than 1, and n1 is an integer greater than 0; The bit mapping module is used to: map each 2 bits in the n2 second data streams into 1 PAM4 symbol, so as to obtain a total of n2 PAM4 symbol data streams; The interleaving encoding module is specifically used to: obtain a0 first bit sets from each of the n1 first data streams to obtain a total of m=n1×a0 first bit sets, wherein the n1 first data streams are all encoded by outer codes, each of the first bit sets includes K bits, and the n1, a0 and K are all integers greater than 1; Cyclic shift is performed on the m first bit sets respectively to obtain m second bit sets, each of the second bit sets includes K bits; Performing inner code encoding on the m second bit sets respectively to obtain m inner code codewords, the inner code encoding and the outer code encoding are both forward error correction FEC encoding, each of the inner code codewords includes one second bit set participating in the inner code encoding and one check bit set, totaling N bits, N=K+P, each of the check bit sets includes P bits, and P is an integer greater than or equal to 1; Polling to obtain 2 bits from each of the inner code words to obtain a third bit set, the third bit set includes m×N bits, a total of m×K bits from the m second bit sets in the third bit set are continuous, and a total of m×P bits from the m check bit sets in the third bit set are continuous; Among them, each of the second data streams includes multiple third bit sets, and each of the third bit sets obtains a total of m×N / 2 PAM4 symbols after the mapping, wherein the m×2 bits mapped to m consecutive PAM4 symbols in the m×N / 2 PAM4 symbols come from the m inner code words.

103. The data processing device according to claim 102, characterized in that: Each of the first data streams is outer code encoded, and 20 consecutive bits in the first data stream are interleaved and mapped to obtain at least 10 PAM4 symbols, the consecutive 20 bits come from 2 outer code symbols of an outer code codeword, and any two of the at least 10 PAM4 symbols are separated by at least 2 PAM4 symbols in the PAM4 symbol data stream.

104. The data processing device according to claim 102 or 103, characterized in that: The number of bits cyclically shifted in any two of the m first bit sets is different.

105. The data processing device according to any one of claims 102 to 104, characterized in that: The m first bit sets and the m second bit sets are both represented as a bit matrix, and the bit matrix includes m rows and K columns of bits.

106. The data processing device according to claim 105, characterized in that: The second bit set is cyclically shifted to the left by the first bit set bits are obtained, the left cyclic shift satisfies a first condition, and the first condition includes: Wherein, M1[i][j] represents the bit in the i-th row and j-th column of the bit matrix corresponding to the m first bit sets before the left cyclic shift, M2[i][j] represents the bit in the i-th row and j-th column of the bit matrix corresponding to the m second bit sets after the left cyclic shift, Y%Z represents the remainder after the integer Y is divided by the integer Z, 0≤i <m,0≤j<K, 107. The data processing device according to claim 105, characterized in that: The second bit set is cyclically shifted right by δ from the first bit set i bits, the rightward cyclic shift satisfies the second condition, which includes: M2[i][j]=M1[i][(j-δ i )% K] Wherein, M1[i][j] represents the bit in the i-th row and j-th column of the bit matrix corresponding to the m first bit sets before the right cyclic shift, M2[i][j] represents the bit in the i-th row and j-th column of the bit matrix corresponding to the m second bit sets after the right cyclic shift, Y%Z represents the remainder after the integer Y is divided by the integer Z, 0≤i <m,0≤j<K,0≤δ i <K。 108. The data processing device according to any one of claims 105 to 107, characterized in that: The m inner code words are represented as a bit matrix including m rows and N columns, and the m inner code words and the third bit set satisfy a third condition, and the third condition includes: Among them, M c [i][j] represents the bit in the i-th row and j-th column of the bit matrix corresponding to the m inner code words, Indicates the first bit in the third bit set bits, 0≤i <m,0≤j<N, Indicates a floor operation.

109. The data processing device according to claim 102, 103, 104, 105, 106 or 108, characterized in that: K = 120, m = 8, the i-th second bit set is cyclically shifted to the left by the i-th first bit set bits are obtained, 0≤i<8, The value of satisfies the first value item Any item in Including: {0,30,60,90,110,20,50,80}; {0,30,90,60,110,20,80,50}; {0,60,30,90,110,50,20,80}; {0,60,90,30,110,50,80,20}; {0,90,30,60,110,80,20,50}; {0,90,60,30,110,80,50,20}.

110. The data processing device according to claim 102, 103, 104, 105, 107 or 108, characterized in that: K = 120, m = 8, the i-th second bit set is cyclically shifted right by δ from the i-th first bit set i bits, 0≤i<8,δ i The value of satisfies any one of the second value items {δ0,δ1,δ2,δ3,δ4,δ5,δ6,δ7}, and the second value items {δ0,δ1,δ2,δ3,δ4,δ5,δ6,δ7} include: {0,30,60,90,10,40,70,100}; {0,30,90,60,10,40,100,70}; {0,60,30,90,10,40,40,100}; {0,60,90,30,10,70,100,40}; {0,90,30,60,10,100,40,70}; {0,90,60,30,10,100,70,40}.

111. A data processing device, characterized in that: include: Interleaving coding module and bit mapping module; The interleaving coding module is used to: perform interleaving coding processing on each n1 first data streams among the n0 first data streams to obtain one second data stream, so as to obtain a total of n2 second data streams, n2=n0 / n1, wherein n0 is an integer greater than 1, and n1 is an integer greater than 0; The bit mapping module is used to: map each 2 bits in the n2 second data streams into 1 PAM4 symbol, so as to obtain a total of n2 PAM4 symbol data streams; The interleaving encoding module is specifically used to: obtain a0 first bit sets from each of the n1 first data streams to obtain a total of m=n1×a0 first bit sets, wherein the n1 first data streams are all encoded by outer codes, each of the first bit sets includes K bits, and the n1, a0 and K are all integers greater than 1; Performing inner code encoding on the m first bit sets respectively to obtain m inner code codewords, wherein both the inner code encoding and the outer code encoding are forward error correction FEC encoding, and each of the inner code codewords includes a first bit set participating in the inner code encoding and a check bit set, which has a total of N bits, where N=K+P, and each of the check bit sets includes P bits, where P is an integer greater than or equal to 1; The m inner code words are interleaved to obtain a second bit set, the second bit set includes m×N bits, and the first bit in the second bit set is bits satisfy the first condition or the second condition, 0≤i <m,0≤j<N; The first condition includes: in, Indicates the first bit in the second bit set bits, represents the first bits, C i [j] represents the j-th bit in the i-th inner code word; The second condition includes: in, Indicates the first bit in the second bit set bits, C i [(j-δ i )%K] represents the (j-δ)th inner code word in the i-th inner code word i )% K bits, C i [j] represents the j-th bit in the i-th inner code word; Each of the second data streams includes multiple second bit sets, and each of the second bit sets obtains a total of m×N / 2 PAM4 symbols after the mapping, wherein the m×2 bits mapped to m consecutive PAM4 symbols in the m×N / 2 PAM4 symbols come from the m inner code words.

112. The data processing device according to claim 111, characterized in that: K = 120, m = 8, The value of satisfies the first value item Any item in Includes: {0,30,60,90,110,20,50,80}; {0,30,90,60,110,20,80,50}; {0,60,30,90,110,50,20,80}; {0,60,90,30,110,50,80,20}; {0,90,30,60,110,80,20,50}; {0,90,60,30,110,80,50,20}; δ i The value of satisfies any one of the second value items {δ0,δ1,δ2,δ3,δ4,δ5,δ6,δ7}, and the second value items {δ0,δ1,δ2,δ3,δ4,δ5,δ6,δ7} include: {0,30,60,90,10,40,70,100}； {0,30,90,60,10,40,100,70}； {0,60,30,90,10,40,40,100}； {0,60,90,30,10,70,100,40}； {0,90,30,60,10,100,40,70}； {0,90,60,30,10,100,70,40}。

Images