Method and apparatus for assessing power supply design, and device and storage medium

Abstract

According to the embodiments of the present disclosure, provided are a method and apparatus for assessing a power supply design, and a device and a storage medium. The method comprises determining a power supply network, which is designed for a chip, wherein the power supply network comprises a plurality of power lines for power transmission, and respective locations and patterns of the plurality of power lines in the chip are indicated. The method comprises generating, for the power supply network, an electrical configuration at least associated with predetermined power consumption of the chip. The method comprises determining predicted voltage losses of the power supply network, which has the electrical configuration, at different locations. In this way, rapid assessment and verification of a power supply solution can be realized, thereby facilitating the shortening of a chip design period.

Description

Method, apparatus, device and storage medium for evaluating power supply design

[0001] This application claims priority to the Chinese invention patent application entitled “Method, apparatus, device and storage medium for evaluating power supply design” filed on September 28, 2022, with application number 202211193069.1, the entire contents of which are incorporated by reference into this application. Technical Field

[0002] Example embodiments of the present disclosure relate generally to the field of semiconductors, and more particularly to methods, apparatuses, devices, and computer-readable storage media for evaluating power supply designs. Background Art

[0003] Power integrity refers to the quality of the power waveform, focusing on the power distribution network (PDN). Power integrity aims to comprehensively consider the system's power supply network and eliminate or mitigate the impact of noise on the power supply. The design goal of power integrity is to control power supply noise within operating limits and provide clean and stable voltage to the chip. With the evolution of chip technology, device integration is increasing, and power distribution networks are becoming increasingly complex. Power solution integrity issues can degrade chip performance and, in severe cases, even cause chip failure. Therefore, it is important to evaluate power solutions for integrity.

[0004] Summary of the Invention

[0005] In a first aspect of the present disclosure, a method for evaluating a power supply design is provided. The method includes: determining a power supply network designed for a chip, the power supply network including a plurality of power lines for power transmission and indicating the location and pattern of each of the plurality of power lines in the chip; generating an electrical configuration for the power supply network associated with at least a predetermined power consumption of the chip; and determining predicted voltage loss at different locations of the power supply network having the electrical configuration.

[0006] In a second aspect of the present disclosure, an apparatus for evaluating a power supply design is provided. The apparatus includes: a power network determination module configured to determine a power supply network designed for a chip, the power network including multiple power lines for power transmission and indicating the location and pattern of each of the multiple power lines in the chip; an electrical configuration generation module configured to generate an electrical configuration for the power network that is at least associated with a predetermined power consumption of the chip; and a voltage loss prediction module configured to determine predicted voltage losses at different locations of the power network having the electrical configuration.

[0007] In a third aspect of the present disclosure, an electronic device is provided. The device includes at least one processing unit; and at least one memory coupled to the at least one processing unit and storing instructions for execution by the at least one processing unit. When executed by the at least one processing unit, the instructions cause the device to perform the method of the first aspect.

[0008] In a fourth aspect of the present disclosure, a computer-readable storage medium is provided, wherein a computer program is stored on the computer-readable storage medium, and the computer program can be executed by a processor to implement the method of the first aspect.

[0009] It should be understood that the content described in this content section is not intended to limit the key features or important features of the embodiments of the present disclosure, nor is it intended to limit the scope of the present disclosure. Other features of the present disclosure will become easily understood through the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] The above and other features, advantages and aspects of the embodiments of the present disclosure will become more apparent with reference to the following detailed description in conjunction with the accompanying drawings. In the accompanying drawings, the same or similar reference numerals represent the same or similar elements, wherein:

[0011] FIG1 shows a schematic diagram of an example environment in which embodiments of the present disclosure can be implemented;

[0012] FIG2 is a schematic diagram illustrating an example evaluation process for power supply design evaluation according to some embodiments of the present disclosure;

[0013] FIG3 illustrates a flow chart of an example process for generating an electrical configuration according to some embodiments of the present disclosure;

[0014] FIG4A shows a schematic diagram of an example presentation of voltage loss according to some embodiments of the present disclosure;

[0015] FIG4B shows a schematic diagram of an example of a power line according to some embodiments of the present disclosure;

[0016] FIG4C is a schematic diagram showing an example of changing a power line according to some embodiments of the present disclosure;

[0017] FIG5 illustrates a flow chart of a process for evaluating a power supply design according to some embodiments of the present disclosure;

[0018] FIG6 shows a block diagram of an apparatus for evaluating a power supply design according to some embodiments of the present disclosure; and

[0019] FIG7 shows a block diagram of a device capable of implementing various embodiments of the present disclosure. DETAILED DESCRIPTION

[0020] The following describes embodiments of the present disclosure in more detail with reference to the accompanying drawings. Although certain embodiments of the present disclosure are shown in the accompanying drawings, it should be understood that the present disclosure can be implemented in various forms and should not be construed as limited to the embodiments described herein. Rather, these embodiments are provided to provide a more thorough and complete understanding of the present disclosure. It should be understood that the drawings and embodiments of the present disclosure are for illustrative purposes only and are not intended to limit the scope of protection of the present disclosure.

[0021] In the description of the embodiments of the present disclosure, the term "including" and similar terms should be understood as open inclusion, that is, "including but not limited to". The term "based on" should be understood as "based at least in part on". The term "one embodiment" or "the embodiment" should be understood as "at least one embodiment". The term "some embodiments" should be understood as "at least some embodiments". Other explicit and implicit definitions may be included below. The terms "first", "second", etc. may refer to different or the same objects. Other explicit and implicit definitions may be included below.

[0022] As used herein, the term "power scheme" may include the power network designed for a chip. The power network represents the location and pattern of power lines used for power delivery within the chip. The term "power line" refers to the electronic representation of the conductive medium (such as metal lines) used for power delivery within the chip in chip design tools. In this document, the terms "power scheme" and "power network" are used interchangeably.

[0023] As used herein, the term "outside the loss range" means not within the loss range, including being above the upper limit of the loss range or below the lower limit of the loss range. In embodiments of the present disclosure, the loss range may be predetermined or may depend on the power supply voltage.

[0024] Sample Environment

[0025] FIG1 illustrates a schematic diagram of an example environment 100 in which embodiments of the present disclosure can be implemented. In environment 100, a computing device 110 obtains a power network 101 designed for a chip. Power network 101 includes multiple power lines for power delivery. Power network 101 also indicates the location and pattern of each of these power lines within the chip.

[0026] These power lines can be located on different layers of the chip or run from one layer to another. These power lines can be different types of power lines, for example, a high voltage power line and a low voltage power line. The voltage provided by the high voltage power line can be represented by the symbol VDD, for example, and the voltage provided by the low voltage power line can be represented by the symbol VSS, for example. Typically, the high voltage power line and the low voltage power line appear in pairs.

[0027] The location of a power line in a chip may include, but is not limited to, the chip layer on which the power line is located, its extent within that layer, and its relative position to other power lines. The style of a power line may include, but is not limited to, its shape and size. Furthermore, although referred to as a "line," a power line may have a width and any suitable shape.

[0028] FIG1 schematically illustrates a portion of a power supply network 101. This portion includes a plurality of power lines 150-1, 150-2, 150-3, 150-4, 150-5, and 150-6, located in different layers of the chip, and referred to individually or collectively as power lines 150. Power lines 150-1 and 150-2 may be a pair of high-voltage and low-voltage power lines located in the same layer, power lines 150-3 and 150-4 may be a pair of high-voltage and low-voltage power lines located in another layer, and power lines 150-5 and 150-6 may be a pair of high-voltage and low-voltage power lines located in yet another layer. In the example of FIG1 , these power lines 150 have different styles. For example, power lines 150-5 and 150-6 are short, miniature power lines, while power lines 150-1, 150-2, 150-3, and 150-4 are long, thin power lines.

[0029] An evaluation system 120 is deployed in computing device 110 and generates evaluation results 102 for the designed power network 101. Evaluation results 102 include at least voltage loss at different locations in power network 101. The voltage loss may include absolute voltage loss, such as voltage drop or IR drop. Alternatively or additionally, the voltage loss may include relative voltage loss, such as the ratio of voltage drop to power supply voltage.

[0030] In some embodiments, if evaluation result 102 indicates that power network 101 has passed verification, computing device 110 may publish power network 101 for use in downstream tasks of chip design. In some embodiments, if evaluation result 102 indicates that power network 101 has failed verification, computing device 110 may update power network 101 based on evaluation result 101. If the evaluation result of updated power network 101 indicates that updated power network 101 has passed verification, computing device 120 may publish the updated power network 101 for use in downstream tasks.

[0031] In the environment 100, the computing device 110 can be any type of device with computing capabilities, including a terminal device or a server device. The terminal device can be any type of mobile terminal, fixed terminal or portable terminal, including a mobile phone, a desktop computer, a laptop computer, a notebook computer, a netbook computer, a tablet computer, a media computer, a multimedia tablet, a personal communication system (PCS) device, a personal navigation device, a personal digital assistant (PDA), an audio / video player, a digital camera / camcorder, a positioning device, a television receiver, a radio broadcast receiver, an e-book device, a gaming device or any combination thereof, including accessories and peripherals of these devices or any combination thereof. The server device can include, for example, a computing system / server, such as a mainframe, an edge computing node, a computing device in a cloud environment, and the like.

[0032] It should be understood that the structure and functionality of environment 100 are described for exemplary purposes only and are not intended to limit the scope of the present disclosure. Furthermore, the number, pattern, and number of layers of power lines shown in FIG1 are merely exemplary and are not intended to limit the scope of the present disclosure. In embodiments of the present disclosure, the power network may include any suitable power lines.

[0033] In traditional power solution evaluation, the power solution is first designed, followed by physical implementation, such as the place and route (PR) process. The PR process involves floorplanning, standard cell placement, clock tree synthesis (CTS), and routing. After completing the full PR process, the power solution is evaluated. If the power solution fails verification, adjustments are required. The adjusted power solution then undergoes another PR process before evaluation. This demonstrates the traditional approach of physical implementation first, followed by evaluation.

[0034] In this traditional approach, a single iteration takes a long time, potentially exceeding a week. Multiple iterations can significantly impact the chip design cycle. Furthermore, this traditional approach relies on a complete set of chip design data, which is not readily available in the early stages of chip design.

[0035] Embodiments of the present disclosure provide a scheme for evaluating power supply designs. According to various embodiments of the present disclosure, a power supply network designed for a chip is determined. The power supply network includes multiple power lines for power transmission and indicates the location and pattern of each of these power lines within the chip. An electrical configuration associated with at least a predetermined power consumption of the chip is generated for the power supply network. Voltage losses, such as voltage drops, at various locations within the power supply network under this electrical configuration are predicted. The predicted voltage losses are used to evaluate the designed power supply network.

[0036] In an embodiment of the present disclosure, the voltage loss at each point in the power supply network is predicted by generating an electrical configuration related to a predetermined power consumption. In this way, the designed power supply scheme can be pre-evaluated without considering the device placement and wiring in the chip. In other words, the embodiment of the present disclosure supports evaluation before physical implementation. Compared with the traditional method of physical implementation before evaluation, this method saves the lengthy cycle of the physical implementation process and realizes the rapid evaluation and verification of the power supply scheme. Therefore, the embodiment of the present disclosure helps to shorten the chip design cycle.

[0037] Some example embodiments of the present disclosure will be described below with continued reference to the accompanying drawings.

[0038] Example Assessment Process

[0039] FIG2 illustrates an exemplary evaluation process 200 for evaluating a power supply design according to some embodiments of the present disclosure. As shown in FIG2 , process 200 may include four stages: power solution acquisition 210 , power solution evaluation 220 , power solution update 230 , and power solution release 240 .

[0040] In the power scheme acquisition 210 stage, the computing device 110 determines the power network 101 designed for the chip. As described with reference to FIG1 , the power network 101 includes a plurality of power lines and indicates the locations and patterns of these power lines.

[0041] In some embodiments, the computing device 110 may be equipped with an electronic design automation (EDA) tool for chip design. A designer of a power supply solution may interact with the computing device 110 through the EDA tool to configure power lines layer by layer. Based on the designer's input, the EDA tool may generate the power supply network 101. In such an embodiment, the computing device 110 generates the power supply network. Alternatively or additionally, in some embodiments, the computing device 110 may receive a design file including the power supply network 101 from an external source. In such an embodiment, the computing device 110 may read the power supply network 101 from the design file.

[0042] Because a chip is a complex system, its design can be performed by chip portion (e.g., chip module). Therefore, the power supply scheme can also be designed by chip portion. Therefore, the power supply network 101 can also have dimensions to indicate the area of ​​the chip portion (e.g., chip module) in which it is used.

[0043] During power scheme evaluation 220, computing device 110 generates an electrical configuration for power network 101 that is at least associated with the chip's predetermined power consumption. Computing device 110 can configure the electrical properties and electrical environment of power network 101 in accordance with the predetermined power consumption. In embodiments of the present disclosure, power scheme evaluation 220 can occur early in chip design, prior to device placement. In this case, instead of calculating power consumption based on information such as device timing and capacitance, embodiments of the present disclosure use the predetermined power consumption.

[0044] The predetermined power consumption can be the expected power consumption of the chip portion for which power network 101 is used. Different chip portions may have different expected power consumptions due to the functions they cannot perform. Therefore, when process 200 is used to evaluate power solutions for different chip portions, the predetermined power consumptions used can be different.

[0045] FIG3 illustrates a flow chart of an example process 300 for generating an electrical configuration according to some embodiments of the present disclosure. As shown in FIG3 , at block 310, computing device 110 sets electrical parameters related to a predetermined power consumption. The values ​​of the electrical parameters may be included in a configuration file, and computing device 110 may set the values ​​by reading the configuration file.

[0046] In some embodiments, computing device 110 may set the current flowing through each power line to have a current value corresponding to a predetermined power consumption. For example, computing device 110 may calculate a current value based on the predetermined power consumption and the power supply voltage, and assign the current value to each power line. As another example, the current value corresponding to the predetermined power consumption may be included in a configuration file. Computing device 110 may read and set the current value from the configuration file. In such an embodiment, using the current value corresponding to the predetermined power consumption rather than directly using the power consumption value can simplify subsequent calculations of voltage loss.

[0047] At block 320, computing device 110 may determine the resistance value of each of the plurality of power lines in power network 101. Specifically, computing device 110 may calculate the resistance value of each power line based on the resistance per unit line width per unit line length (i.e., resistivity) and the connection relationship between the power lines. Information regarding the power line resistivity may be included in a configuration file. Computing device 110 may calculate the resistance value of each power line by reading the configuration file.

[0048] In block 330, the computing device 110 may specify a connection location between an external power source that supplies power to the chip and the chip, and a voltage at the connection location. The connection location may also be referred to as a power supply point. The computing device 110 may specify two types of power supply points, namely, a high-voltage power supply point and a low-voltage power supply point. A high-voltage power supply point may be considered a location where current flows from the external power source into the chip, while a low-voltage power supply point may be considered a location where current flows out of the chip. As an example, a high-voltage power supply point may include a power supply point that provides VDD, whose voltage may be a power supply voltage; a low-voltage power supply point may include a power supply point that provides VSS, whose voltage may be a ground voltage, such as zero.

[0049] The power point can be located in the top layer of the chip. The power point can be specified using its coordinates in the top layer. Furthermore, the designation of the power point may need to meet chip design requirements regarding power point density, spacing, and the like. The embodiments of the present disclosure are not limited in this respect.

[0050] At block 340 , the computing device 110 may set an operating temperature of the chip. The operating temperature of the chip may be related to, for example, the expected usage scenario of the chip.

[0051] It should be understood that the process 300 for generating an electrical configuration shown in FIG3 is merely exemplary and is not intended to limit the scope of this disclosure. The order in which the blocks in process 300 are executed is not limited. Furthermore, the electrical parameters or environmental parameters set in process 300 are merely exemplary, and computing device 110 may set fewer or more parameters. For example, computing device 110 may set the accuracy of the evaluation, enable or disable full-link resistance analysis, set voltage change thresholds for power supply points, and so on.

[0052] Continuing with FIG2 , during power scheme evaluation 220 , after generating an electrical configuration, computing device 110 may predict voltage drop at various locations of power network 101 having the electrical configuration. The voltage drop at various locations may include a continuous voltage drop along the power line, or voltage drop at multiple sampled locations along the power line. The voltage drop may include an absolute value of the voltage drop or a ratio of the voltage drop to the power supply voltage.

[0053] In some embodiments, computing device 110 may present the predicted voltage loss in association with power network 101 based on the magnitude of the predicted voltage loss. In one example, computing device 110 may output the coordinates of a location where the voltage loss is not within the loss range and the predicted voltage loss value at that location. In another example, computing device 110 may display power network 101 on a display device, with the colors of different locations on the displayed power network 101 corresponding to the predicted voltage loss at that location. The greater the predicted voltage loss, the more striking the color. In a two-dimensional display, the voltage loss in each layer may be displayed layer by layer. In a three-dimensional display, the voltage losses in different layers may be displayed together.

[0054] The power solution evaluation 220 described above can be implemented using a power analysis engine within an EDA tool. For example, the computing device 110 can invoke the power analysis engine to generate an electrical configuration and predict voltage loss. However, this is merely exemplary, and embodiments of the present disclosure are not limited in the implementation of the power solution evaluation 220.

[0055] Continuing with process 200, at block 250, a determination is made as to whether power network 101 passes verification based on the loss range. The loss range may include an upper limit. If the predicted voltage loss at a location is higher than the upper limit, this indicates a weak power design at that location. Such a location may also be referred to as a weak point. Such weak points should be eliminated whenever possible.

[0056] Additionally, in some embodiments, the loss range may include a lower limit. If the predicted voltage loss at a certain location is lower than the lower limit, it means that the voltage design at that location is relatively robust. Such a location may also be called a robust point.

[0057] If it is determined that power network 101 passes verification, that is, if the predicted voltage losses at different locations are all within the loss range, process 200 proceeds to power solution release 240. During power solution release 240, computing device 110 may generate a file indicating power network 101 for use in a target portion of the chip. The target portion has a power density corresponding to the area of ​​power network 101 and the predetermined power consumption. For example, the current density may be determined based on the area of ​​power network 101 and the current set in power solution evaluation 220. The target portion may be a portion of the chip (e.g., a chip module) where the difference between the expected current density and the current density is within a predetermined range.

[0058] The generated files can be released to downstream tasks in chip design. For example, the generated files can be used in the subsequent PR process.

[0059] If it is determined at block 250 that power network 101 has not passed validation, that is, if there are one or more locations (also referred to as first locations) where the predicted voltage loss exceeds the loss range, process 200 proceeds to power scheme update 230. During power scheme update 230, computing device 110 updates power network 101 by updating the power lines at the first locations. Updating the power lines may include, but is not limited to, adding new power lines, extending or shortening existing power lines, changing the spacing between adjacent power lines, etc.

[0060] In some embodiments, computing device 110 may update power network 101 based on interaction with a power solution designer. Specifically, computing device 110 may present predicted voltage loss in association with power network 101 based on the magnitude of predicted voltage loss at different locations. The presentation may be as described above.

[0061] While the predicted voltage loss is being presented, computing device 110 can detect an instruction to change the power line. This instruction can be given by the designer through interactive components of computing device 110 (e.g., a touch screen, keyboard, mouse, etc.). Furthermore, in some embodiments, computing device 110 can also present the power line at the first location in an enlarged manner in response to a selection from the designer. While presenting the power line at the first location in an enlarged manner, computing device 110 can detect the designer's instruction to change the power line.

[0062] The computing device 110 can then change the power line at the first position based on the detected indication, thereby updating the power supply network 101. For example, when the predicted voltage loss at the first position is higher than the upper limit of the loss range, the indication can be an indication to add a new power line at the first position or to extend an existing power line. In this way, the density of power lines near the weak point is increased, thereby helping to eliminate the weak point and improve the reliability of the power supply solution. For another example, when the predicted voltage loss at the first position is lower than the lower limit of the loss range, the indication can be an indication to remove a portion of the power line at the first position, or an indication to shorten the power line at the first position, etc. In this way, the density of power lines near the strong point is reduced. While ensuring the reliability of the power supply, some space can be appropriately freed up for signal lines.

[0063] An example is described below with reference to Figures 4A to 4C. Figure 4A shows a schematic diagram illustrating an example presentation of voltage loss according to some embodiments of the present disclosure. In the example of Figure 4A, legends 412 and 413 indicate that the predicted voltage loss is within the loss range, while legend 411 indicates that the predicted voltage loss is outside the loss range. Accordingly, the predicted voltage loss at various locations in regions 423 and 422 is within the loss range. The predicted voltage loss at location 421 is outside the loss range, for example, exceeding the upper limit of the loss range.

[0064] It should be understood that the presentation of the predicted voltage loss shown in FIG4A is merely exemplary and is not intended to limit the scope of the present disclosure. In embodiments of the present disclosure, the predicted voltage loss may be presented in a more refined manner. For example, the displayed color may be associated with the magnitude of the predicted voltage loss.

[0065] While the predicted voltage loss is being presented, computing device 110 detects the selection of location 421. For example, the power solution designer clicks on location 421 on the display or circles location 421 with a box. In response to detecting the selection of location 421, computing device 110 may present the power lines at location 421 in an enlarged manner, as shown in FIG4B . In the example of FIG4B , a power line is missing at location 421. Specifically, power lines 431, 432, 433, and 434 do not extend into area 435.

[0066] While the power lines at location 421 are presented in an enlarged manner, computing device 110 detects an indication to change the power lines. Based on the detected indication, computing device 110 may change the power lines at location 421, thereby updating power network 101. In the example of FIG4C , based on the detected indication, computing device 110 extends power lines 431, 432, 433, and 434, thereby increasing the density of power lines at location 421.

[0067] Continuing with reference to FIG. 2 , alternatively, in some embodiments, computing device 110 can autonomously update power network 101 . Specifically, if computing device 110 determines that the predicted voltage loss at a first location (also referred to as a first predicted voltage loss) is above an upper limit of a loss range, computing device 110 can increase the power line density at the first location to update power network 101 . Increasing power line density may include, but is not limited to, adding new power lines, extending existing power lines, reducing the spacing between adjacent power lines, and the like. In this way, weak points can be eliminated and the reliability of the power supply solution can be improved.

[0068] If computing device 110 determines that the predicted voltage loss at the first location is below the lower limit of the loss range, computing device 110 may reduce the power line density at the first location to update power network 101. Reducing power line density may include, but is not limited to, removing existing power lines, shortening existing power lines, and increasing the spacing between adjacent power lines. In this way, while ensuring power reliability, some space can be appropriately freed up for signal lines. This helps achieve a balance between power lines and signal lines.

[0069] In this case, process 200 may return to power scheme evaluation 220 to evaluate the updated power network. If the updated power network passes verification, computing device 110 may generate a file indicating the updated power network for distribution to downstream tasks. If the updated power network does not pass verification, computing device 110 may again execute power scheme update 230 to iteratively update the power network until it passes verification.

[0070] In the embodiments of the present disclosure, the robustness of the power supply network can be assessed early in the design process without implementing a physical process (such as a PR process). The power supply solution can be adjusted accordingly based on the robustness. This shortens the power supply design cycle, thereby facilitating a reduction in chip design cycles.

[0071] Furthermore, process 200 can be executed for different predetermined power consumptions. Different power supply solutions can be provided based on different power consumptions to accommodate chip modules with different power densities. For example, different current values ​​can be set to accommodate chip modules with different power consumptions, thereby enabling differentiated power supply solution design and verification.

[0072] Example Process

[0073] 5 shows a flow chart of a process 500 for evaluating a power supply design according to some embodiments of the present disclosure. The process 500 may be implemented at the computing device 110. The process 500 is described below with reference to FIG1.

[0074] At block 510 , the computing device 110 determines a power network 101 designed for a chip. The power network 101 includes a plurality of power lines for power delivery and indicates the location and pattern of each of the plurality of power lines in the chip.

[0075] At block 520 , computing device 110 generates an electrical configuration for power network 101 that is associated with at least a predetermined power consumption of the chip.

[0076] In some embodiments, to generate the electrical configuration, the computing device 110 may set the current flowing through the plurality of power lines to have a current value corresponding to a predetermined power consumption.

[0077] In some embodiments, computing device 110 can determine the resistance of each of the multiple power lines. Alternatively or additionally, computing device 110 can set the connection location between the external power supply supplying power to the chip and the chip, and the voltage at the connection location. Alternatively or additionally, computing device 110 can set the operating temperature of the chip.

[0078] At block 530 , computing device 110 determines predicted voltage losses at different locations of power network 101 having the electrical configuration. In some embodiments, if the predicted voltage losses at the different locations are determined to be within a loss range, computing device 110 may generate a file instructing power network 101 to be used in a target portion of a chip. The target portion has a power density corresponding to the area of ​​power network 101 and a predetermined power consumption.

[0079] In some embodiments, computing device 110 may update power network 101 by changing a power line at a first location among different locations. A first predicted voltage loss at the first location exceeds a loss range.

[0080] In some embodiments, computing device 110 may determine updated predicted voltage losses at different locations of updated power network 101. If the updated predicted voltage losses are within a loss range, computing device 110 may generate a file indicating updated power network 101 for use in a target portion of a chip. The target portion has a power density corresponding to the area of ​​updated power network 101 and a predetermined power consumption.

[0081] In some embodiments, to update power network 101, computing device 110 may present predicted voltage losses at different locations in association with power network 101 based on the magnitude of the predicted voltage losses at the different locations. While the predicted voltage losses at the different locations are presented, computing device 110 may detect an indication to change a power line. Computing device 110 may change the power line at a first location based on the detected indication to update power network 101.

[0082] In some embodiments, in response to detecting a selection of a first location while the predicted voltage loss at different locations is being presented, computing device 110 may present the power line at the first location in an enlarged manner. While presenting the power line at the first location in an enlarged manner, computing device 110 may detect an instruction to change the power line.

[0083] In some embodiments, if the first predicted voltage loss is higher than the upper limit of the loss range, computing device 110 may update power network 101 by increasing the power line density at the first location. If the first predicted voltage loss is lower than the lower limit of the loss range, computing device 110 may update power network 101 by decreasing the power line density at the first location.

[0084] Example devices and equipment

[0085] 6 shows a schematic block diagram of an apparatus 600 for evaluating a power supply design according to certain embodiments of the present disclosure. Apparatus 600 may be implemented as or included in computing device 110. Each module / component in apparatus 600 may be implemented by hardware, software, firmware, or any combination thereof.

[0086] As shown, apparatus 600 includes a power network determination module 610 configured to determine a power network designed for a chip, the power network including multiple power lines for power transmission and indicating the location and pattern of each of the multiple power lines within the chip. Apparatus 600 also includes an electrical configuration generation module 620 configured to generate an electrical configuration for the power network that is at least associated with a predetermined power consumption of the chip. Apparatus 600 further includes a voltage loss prediction module 630 configured to determine predicted voltage loss at different locations of the power network having the electrical configuration.

[0087] In some embodiments, the apparatus 600 further includes: a power network update module configured to update the power network by changing a power line at a first location among different locations, wherein a first predicted voltage loss at the first location exceeds a loss range.

[0088] In some embodiments, the voltage loss prediction module is further configured to determine updated predicted voltage losses at different locations of the updated power network. The apparatus 600 also includes a power network publishing module configured to generate a file indicating the updated power network if the updated predicted voltage loss is within a loss range, so as to apply the updated power network to a target portion of the chip, the target portion having a power density corresponding to the area of ​​the updated power network and a predetermined power consumption.

[0089] In some embodiments, the power network update module includes: a voltage loss presentation module, configured to present predicted voltage losses at different locations in association with the power network based on the magnitude of the predicted voltage losses at different locations; an indication detection module, configured to detect an indication of changing the power line while the predicted voltage losses at different locations are presented; and a power line change module, configured to change the power line at a first location based on the detected indication to update the power network.

[0090] In some embodiments, the indication detection module is further configured to: in response to detecting a selection of the first location while the predicted voltage loss at different locations is presented, present the power line at the first location in an enlarged manner; and while presenting the power line at the first location in an enlarged manner, detect an indication to change the power line.

[0091] In some embodiments, the power network update module includes one of the following: a density increase module, configured to update the power network by increasing the power line density at the first position if the first predicted voltage loss is higher than the upper limit of the loss range; a density reduction module, configured to update the power network by reducing the power line density at the first position if the first predicted voltage loss is lower than the lower limit of the loss range.

[0092] In some embodiments, the electrical configuration generation module includes a current setting module configured to set currents flowing through the plurality of power lines to have current values ​​corresponding to predetermined power consumption.

[0093] In some embodiments, the electrical configuration generation module also includes at least one of the following: a resistance derivation module, configured to derive the resistance value of each of a plurality of power lines, a power supply point designation module, configured to set the connection position between the external power supply supplying power to the chip and the chip and the voltage at the connection position, and a temperature setting module, configured to set the operating temperature of the chip.

[0094] In some embodiments, the apparatus 600 further includes: a power network publishing module configured to generate a file indicating the power network if it is determined that the predicted voltage loss at different locations is within a loss range, so as to use the power network for a target portion of the chip, the target portion having a power density corresponding to the area of ​​the power network and the predetermined power consumption.

[0095] FIG7 shows a block diagram of a computing device 700 in which one or more embodiments of the present disclosure may be implemented. It should be understood that the computing device 700 shown in FIG7 is merely exemplary and should not be construed as limiting the functionality and scope of the embodiments described herein. The computing device 700 shown in FIG7 can be used to implement the computing device 110 of FIG1 .

[0096] As shown in FIG7 , computing device 700 is in the form of a general-purpose computing device. Components of computing device 700 may include, but are not limited to, one or more processors or processing units 710, memory 720, storage device 730, one or more communication units 740, one or more input devices 750, and one or more output devices 760. Processing unit 710 may be a real or virtual processor and is capable of performing various processes according to a program stored in memory 720. In a multi-processor system, multiple processing units execute computer-executable instructions in parallel to increase the parallel processing capabilities of computing device 700.

[0097] The computing device 700 typically includes a plurality of computer storage media. Such media can be any accessible media that can be obtained by the computing device 700, including but not limited to volatile and non-volatile media, removable and non-removable media. The memory 720 can be a volatile memory (e.g., registers, cache, random access memory (RAM)), a non-volatile memory (e.g., read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), flash memory), or some combination thereof. The storage device 730 can be a removable or non-removable medium and can include a machine-readable medium, such as a flash drive, a disk, or any other medium that can be used to store information and / or data (e.g., training data for training) and can be accessed within the computing device 700.

[0098] The computing device 700 may further include additional removable / non-removable, volatile / non-volatile storage media. Although not shown in FIG. 7 , a disk drive for reading from or writing to a removable, non-volatile disk (e.g., a “floppy disk”) and an optical drive for reading from or writing to a removable, non-volatile optical disk may be provided. In these cases, each drive may be connected to a bus (not shown) by one or more data media interfaces. The memory 720 may include a computer program product 725 having one or more program modules configured to perform various methods or actions of various embodiments of the present disclosure.

[0099] The communication unit 740 enables communication with other computing devices via a communication medium. Additionally, the functionality of the components of the computing device 700 can be implemented as a single computing cluster or multiple computing machines that can communicate via a communication connection. Thus, the computing device 700 can operate in a networked environment using logical connections to one or more other servers, network personal computers (PCs), or other network nodes.

[0100] Input device 750 may be one or more input devices, such as a mouse, keyboard, or trackball. Output device 760 may be one or more output devices, such as a display, a speaker, or a printer. Computing device 700 may also communicate with one or more external devices (not shown) via communication unit 740, as needed, such as storage devices, display devices, or the like, with one or more devices that allow a user to interact with computing device 700, or with any device that allows computing device 700 to communicate with one or more other computing devices (e.g., a network card, a modem, etc.). Such communication may be performed via an input / output (I / O) interface (not shown).

[0101] According to an exemplary implementation of the present disclosure, a computer-readable storage medium is provided, on which computer-executable instructions are stored, wherein the computer-executable instructions are executed by a processor to implement the method described above. According to an exemplary implementation of the present disclosure, a computer program product is also provided, which is tangibly stored on a non-transitory computer-readable medium and includes computer-executable instructions, and the computer-executable instructions are executed by a processor to implement the method described above.

[0102] Various aspects of the present disclosure are described herein with reference to flowcharts and / or block diagrams of methods, apparatuses, devices, and computer program products implemented according to the present disclosure. It should be understood that each block of the flowcharts and / or block diagrams, and combinations of blocks in the flowcharts and / or block diagrams, can be implemented by computer-readable program instructions.

[0103] These computer-readable program instructions can be provided to a processing unit of a general-purpose computer, a special-purpose computer, or other programmable data processing device, thereby producing a machine, such that when these instructions are executed by the processing unit of the computer or other programmable data processing device, a device is generated that implements the functions / actions specified in one or more blocks in the flowchart and / or block diagram. These computer-readable program instructions can also be stored in a computer-readable storage medium, where these instructions cause the computer, programmable data processing device, and / or other device to operate in a specific manner. Thus, the computer-readable medium storing the instructions comprises an article of manufacture that includes instructions for implementing various aspects of the functions / actions specified in one or more blocks in the flowchart and / or block diagram.

[0104] Computer-readable program instructions can be loaded onto a computer, other programmable data processing apparatus, or other device so that a series of operational steps are performed on the computer, other programmable data processing apparatus, or other device to produce a computer-implemented process, thereby causing the instructions executed on the computer, other programmable data processing apparatus, or other device to implement the functions / actions specified in one or more boxes in the flowchart and / or block diagram.

[0105] The flow charts and block diagrams in the accompanying drawings show the possible architecture, functions and operations of the systems, methods and computer program products according to multiple implementations of the present disclosure. In this regard, each box in the flow chart or block diagram can represent a part of a module, program segment or instruction, and a part of a module, program segment or instruction comprises one or more executable instructions for realizing the logical function of the specification. In some alternative implementations, the functions marked in the box can also occur in a sequence different from that marked in the accompanying drawings. For example, two continuous boxes can actually be executed substantially in parallel, and they can sometimes be executed in the opposite order, depending on the functions involved. It should also be noted that each box in the block diagram and / or flow chart, and the combination of the boxes in the block diagram and / or flow chart can be implemented using a dedicated hardware-based system that performs the function or action of the specification, or can be implemented using a combination of dedicated hardware and computer instructions.

[0106] While various implementations of the present disclosure have been described above, the foregoing description is intended to be illustrative, not exhaustive, and not limited to the disclosed implementations. Many modifications and variations will be apparent to those skilled in the art without departing from the scope and spirit of the described implementations. The terminology used herein is selected to best explain the principles of the implementations, their practical applications, or improvements to existing technologies, or to enable others skilled in the art to understand the various implementations disclosed herein.

Claims

1. A method for evaluating a power supply design, comprising: determining a power supply network designed for a chip, the power supply network including a plurality of power lines for power transmission and indicating the position and pattern of each of the plurality of power lines in the chip; generating an electrical configuration for the power supply network that is at least associated with a predetermined power consumption of the chip; and determining predicted voltage losses at different positions of the power supply network having the electrical configuration.

2. The method according to claim 1, further comprising: updating the power supply network by changing a power line at a first position among the different positions, wherein a first predicted voltage loss at the first position exceeds a loss range.

3. The method according to claim 2, further comprising: determining updated predicted voltage losses at different positions of the updated power supply network; and if the updated predicted voltage losses are within the loss range, generating a file indicating the updated power supply network for use in a target portion of the chip, the target portion having a power density corresponding to the area of the updated power supply network and the predetermined power consumption.

4. The method according to claim 2, wherein updating the power supply network comprises: presenting the predicted voltage losses at the different positions in association with the power supply network based on the magnitudes of the predicted voltage losses at the different positions; detecting an indication to change a power line while the predicted voltage losses at the different positions are being presented; and changing the power line at the first position based on the detected indication to update the power supply network.

5. The method according to claim 4, wherein detecting the indication to change a power line comprises: in response to detecting a selection of the first position while the predicted voltage losses at the different positions are being presented, presenting the power line at the first position in an enlarged manner; and detecting the indication to change a power line while the power line at the first position is being presented in an enlarged manner.

6. The method according to claim 2, wherein updating the power supply network includes one of the following: if the first predicted voltage loss is higher than an upper limit of the loss range, updating the power supply network by increasing the power line density at the first position; if the first predicted voltage loss is lower than a lower limit of the loss range, updating the power supply network by decreasing the power line density at the first position.

7. The method according to claim 1, wherein generating the electrical configuration comprises: setting the current flowing through the plurality of power lines to a current value corresponding to the predetermined power consumption.

8. The method according to claim 2, generating the electrical configuration further includes at least one of the following: obtaining the resistance value of each of the plurality of power lines, setting the connection position of an external power supply supplying power to the chip and the voltage at the connection position, setting the operating temperature of the chip.

9. The method according to claim 1, further comprising: If it is determined that the predicted voltage losses at the different positions are within the loss range, a file indicating the power supply network is generated to use the power supply network for a target portion of the chip, the target portion having a power density corresponding to the area of the power supply network and the predetermined power consumption.

10. An apparatus for evaluating a power supply design, comprising: a power supply network determination module configured to determine a power supply network designed for a chip, the power supply network including a plurality of power lines for power transmission and indicating the respective positions and patterns of the plurality of power lines in the chip; an electrical configuration generation module configured to generate an electrical configuration for the power supply network that is at least associated with a predetermined power consumption of the chip; and a voltage loss prediction module configured to determine predicted voltage losses at different positions of the power supply network having the electrical configuration.

11. An electronic device, comprising: at least one processing unit; and at least one memory coupled to the at least one processing unit and storing instructions for execution by the at least one processing unit, the instructions, when executed by the at least one processing unit, causing the electronic device to perform the method according to any one of claims 1 to 9.

12. A computer-readable storage medium having stored thereon a computer program, the computer program being executable by a processor to implement the method according to any one of claims 1 to 9.

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