Display substrate and display device

Abstract

Provided are a display substrate and a display device. The display substrate comprises a driving transistor and a storage capacitor. The storage capacitor comprises a first electrode plate and a second electrode plate. The second electrode plate and a channel of the driving transistor are arranged on the same layer, the second electrode plate is closer to a base substrate than the first electrode plate, and the orthographic projection of the second electrode plate on the base substrate overlaps the orthographic projections of pixel openings on the base substrate. The display substrate satisfies the following relations: the value range of (W*L+S2)*M1 / M2 is [0.014, 0.133], and the value range of S2 / (W*L) is [2.82, 28.85], wherein W is the width of the channel of the driving transistor, L is the length of the channel of the driving transistor, S2 is the opposite area of the second electrode plate and the first electrode plate, M1 is the number of pixel openings of the display substrate, and M2 is the area of the display substrate. Therefore, the opposite area of the electrode plates of the storage capacitor is increased, the electric capacity is improved, the holding capacity of a capacitor is improved, the area ratio of the storage capacitor to the pixel openings is increased, the area proportion of the storage capacitor is improved, and the display quality is improved.

Description

Display substrate and display device Technical Field

[0001] Embodiments of the present disclosure relate to a display substrate and a display device. Background Art

[0002] With the rapid development of technology, display media has become an important part of people's lives. Organic light-emitting diode (OLED) displays have excellent color and image quality due to their self-luminous properties.

[0003] Summary of the Invention

[0004] Embodiments of the present disclosure provide a display substrate and a display device to improve display quality and / or reduce power consumption.

[0005] An embodiment of the present disclosure provides a display substrate, comprising: a base substrate and a plurality of sub-pixels arranged on the base substrate; the sub-pixels comprise: a pixel circuit, comprising a driving transistor and a storage capacitor, the storage capacitor comprising a first plate and a second plate, the first plate of the storage capacitor being connected to the gate of the driving transistor; and a light-emitting element electrically connected to the pixel circuit, the pixel circuit being configured to drive the light-emitting element, wherein the sub-pixel comprises a pixel opening, the pixel opening being configured to define a light-emitting area of ​​the sub-pixel, and the positive projection of the storage capacitor on the base substrate is aligned with the pixel opening on the base substrate. The orthographic projection of the second electrode plate and the first electrode plate overlap, the orthographic projection of the channel of the driving transistor on the base substrate overlaps with the orthographic projection of the pixel opening on the base substrate, and the display substrate satisfies the following relationship: the value range of (W*L+S2)*M1 / M2 is [0.014, 0.133], and the value range of S2 / (W*L) is [2.82, 28.85], wherein W is the width of the channel of the driving transistor, L is the length of the channel of the driving transistor, S2 is the facing area of ​​the second electrode plate and the first electrode plate, M1 is the number of pixel openings of the display substrate, and M2 is the area of ​​the display substrate.

[0006] For example, the second plate of the storage capacitor is connected to the first electrode of the driving transistor, and the storage capacitor also includes a third plate. The third plate and the second plate are connected to each other, and the third plate and the second plate are respectively arranged on both sides of the first plate.

[0007] For example, the second electrode plate includes a first plate-shaped portion, and the first plate-shaped portion and the channel of the driving transistor are an integrated structure.

[0008] For example, the second electrode further includes a second plate-shaped portion, the first plate-shaped portion and the second plate-shaped portion are separated from each other, the area of ​​the first plate-shaped portion is larger than the area of ​​the second plate-shaped portion, or the first plate-shaped portion and the second plate-shaped portion are both connected to the channel of the driving transistor.

[0009] For example, the channel of the driving transistor is made of a semiconductor material, and the material of the second electrode plate is a conductor obtained by doping the same semiconductor material as the channel of the driving transistor.

[0010] For example, the channel of the driving transistor extends along a first direction, the pixel opening has a central axis extending along the first direction, the maximum dimension of the pixel opening along the second direction is W0, the first direction intersects with the second direction, the distance from the channel of the driving transistor to the central axis is D1, and the value range of 2*D1 / W0 is [0.2, 0.4] or [0.6, 0.8].

[0011] For example, the display substrate also includes a plurality of signal lines located on one side of the storage capacitor, the signal lines extending along the second direction, and the orthographic projections of the plurality of signal lines on the base substrate overlap with the orthographic projections of the pixel opening on the base substrate, wherein the size of the pixel opening along the first direction is H0, the distance between the farthest edges of the plurality of signal lines in the first direction is Hs, and the value range of L / (H0-Hs) is [0.16, 0.61].

[0012] For example, the display substrate also includes a data line, a first gate line, a second gate line, and a first initialization line, wherein the pixel circuit also includes a data write transistor and a first reset transistor, the first electrode of the data write transistor is connected to the data line, the gate of the drive transistor is connected to the second electrode of the data write transistor, the gate of the data write transistor is connected to the first gate line, the first electrode of the first reset transistor is connected to the first initialization line, the second electrode of the first reset transistor is connected to the gate of the drive transistor, the gate of the first reset transistor is connected to the second gate line, and the multiple signal lines include the first gate line, the second gate line, and the first initialization line.

[0013] For example, the area of ​​the pixel opening is S0, the sum of the facing area of ​​the second electrode plate and the first electrode plate and the area of ​​the channel of the driving transistor is Ss, and the relationship between Ss and S0 satisfies: Ss=A*S0+B, the value range of A is [0.42, 0.82], and the value range of B is [-2700, -3100].

[0014] For example, the orthographic projection of the pixel opening on the substrate overlaps with the orthographic projection of the third plate on the substrate, the third plate includes a first edge extending along a first direction and a second edge extending along the first direction, the pixel opening includes a first edge extending along the first direction and a second edge extending along the first direction, the first edge of the third plate is closer to the first edge of the pixel opening than the second edge of the third plate, the second edge of the third plate is closer to the second edge of the pixel opening than the first edge of the third plate, and the sub-pixel is full The following formula is satisfied: △U=|U02-U01|, U01 is the coordinate distance between the chromaticity coordinate point at the first viewing angle and the chromaticity coordinate point at the 0-degree viewing angle, U02 is the coordinate distance between the chromaticity coordinate point at the second viewing angle and the chromaticity coordinate point at the 0-degree viewing angle, △U is the absolute value of the difference between U02 and U01, the chromaticity coordinate point at the 0-degree viewing angle is the chromaticity coordinate point at the normal line at the center of the display substrate, the first viewing angle and the second viewing angle are respectively arranged on opposite sides of the normal line and have the same angle value with the normal line, and △U≤0.0020.

[0015] For example, the display substrate also includes a first power line, which is configured to provide a first voltage signal to the pixel circuit. The first power line includes a first power connection line extending along a first direction and a first power signal line extending along a second direction. The orthographic projection of the first power connection line on the base substrate overlaps with the orthographic projection of the pixel opening on the base substrate. The facing area of ​​the third electrode and the first electrode is Sc1, and the overlapping area of ​​the orthographic projection of the third electrode on the base substrate and the orthographic projection of the pixel opening on the base substrate is Sc2, Sc2 / Sc1≥0.9; the width of the first power connection line is W1, and the overlapping width of the first power connection line and the pixel opening is W2, W2 / W1≥0.9.

[0016] For example, the maximum size of the pixel opening along the second direction is W0, the value range of 2×W2 / W0 is [0.71, 0.99], and the value range of the cross voltage Uc / size Lg is [0.32, 0.74], the cross voltage Uc is the cross voltage of the light-emitting element, the unit of the cross voltage Uc is volt, and the size Lg is the length of the diagonal of the display substrate, and the unit of the size Lg is inches.

[0017] For example, the pixel opening has a central axis extending along the first direction, the minimum distance from the first power connection line to the central axis is Xd1, the minimum distance from the third plate to the central axis is Xd2, and the value range of Xd1 / Xd2 is [0.9, 1.1].

[0018] For example, the display substrate also includes a plurality of signal lines located on one side of the storage capacitor, the orthographic projections of the plurality of signal lines on the base substrate overlap with the orthographic projections of the pixel opening on the base substrate, the plurality of signal lines are arranged along a first direction, and the signal lines extend along a second direction, wherein the first direction intersects with the second direction, the distance between the third electrode and the signal line closest to it is Xd3, the line width of the signal line is Xd4, and the value range of Xd3 / Xd4 is [0.9, 1.1].

[0019] For example, the display substrate also includes a first power line, which is configured to provide a first voltage signal to the pixel circuit. The first power line includes a first power connection line extending along a first direction and a first power signal line extending along a second direction. The pixel opening has a central axis extending along the first direction. The minimum distance from the first power connection line to the central axis is Xd1, and the minimum distance between the first power connection line and the third electrode plate is Xd0. DP = |Xd1-Xd0| / 2. The maximum size of the pixel opening along the second direction is W0, and the value range of DP / W0 is [0.01, 0.19].

[0020] For example, the display substrate also includes a first signal line, which extends along a first direction. The sub-pixel includes a first sub-pixel and a second sub-pixel adjacent to each other in the second direction. The first signal line is configured to provide a data signal to the pixel circuit of the first sub-pixel. The pixel opening of the first sub-pixel and the pixel opening of the second sub-pixel are spaced apart, and the first signal line is located between the pixel opening of the first sub-pixel and the pixel opening of the second sub-pixel.

[0021] For example, the minimum distances between the pixel opening of the first sub-pixel and the pixel opening of the second sub-pixel and the first signal line are Xa1 and Xa2 respectively, and the value range of Xa1 / Xa2 is [0.8, 1.2].

[0022] For example, the display substrate also includes a second signal line, which extends along the first direction. The first signal line and the second signal line are located on opposite sides of the same third electrode plate, and the orthographic projection of the second signal line on the base substrate overlaps with the orthographic projection of the pixel opening of the second sub-pixel on the base substrate.

[0023] For example, the distance between the third electrode plate and the second signal line is Xa3, the distance between the third electrode plate and the first signal line is Xa4, and the value range of Xa3 / Xa4 is [0.8, 1.2].

[0024] For example, the display substrate also includes a third signal line, which extends along the first direction. The orthographic projection of the third signal line on the base substrate overlaps with the orthographic projection of the pixel opening of the first sub-pixel on the base substrate. The minimum distance between the third electrode of the first sub-pixel and the third signal line is Xa5, and the minimum distance between the third signal line and the first signal line is Xa6. The value range of Xa5 / Xa6 is [0.8, 1.2].

[0025] For example, the first signal line includes a data line, and at least one of the second signal line and the third signal line includes a first power connection line.

[0026] For example, the display substrate also includes a data line and a first power line, the data line is configured to provide a data voltage to the pixel circuit, the data line extends along a first direction, the first power line is configured to provide a first voltage signal to the pixel circuit, the first power line includes a first power connection line extending along the first direction and a first power signal line extending along a second direction, the sub-pixel includes a first sub-pixel and a second sub-pixel adjacent to each other in the second direction, the orthographic projection of the first power connection line on the base substrate overlaps with the orthographic projection of the pixel opening of the first sub-pixel on the base substrate, and overlaps with the orthographic projection of the pixel opening of the second sub-pixel on the base substrate.

[0027] For example, two data lines are provided on both sides of the first power connection line, and the orthographic projections of the two data lines on the base substrate overlap with the orthographic projections of the pixel opening of the first sub-pixel and the pixel opening of the second sub-pixel on the base substrate respectively.

[0028] For example, two data lines are arranged on both sides of the first power connection line, and the orthographic projections of the two data lines on the base substrate do not overlap with the orthographic projections of the pixel opening of the first sub-pixel on the base substrate, and do not overlap with the orthographic projections of the pixel opening of the second sub-pixel on the base substrate.

[0029] For example, the display substrate also includes a first power line, which is configured to provide a first voltage signal to the pixel circuit. The first power line includes a first power connection line extending along a first direction and a first power signal line extending along a second direction. The orthographic projection of the first power connection line on the base substrate overlaps with the orthographic projection of the pixel opening on the base substrate. The maximum dimension of the pixel opening along the second direction is W0. The sub-pixel includes a first sub-pixel and a second sub-pixel adjacent to each other in the second direction. The dimension of one of the two first power connection lines in the second direction is Xb1, and the dimension of the other of the two first power connection lines in the second direction is Xb2. The value range of (Xb1+Xb2) / W0 is [0.08, 0.48].

[0030] For example, the display substrate further includes a driving circuit, which is located on one side of the display substrate. Subpixels away from the driving circuit have a first brightness L1; subpixels close to the driving circuit have a second brightness L2, and the value range of |L1-L2| is [1, 9].

[0031] For example, the display substrate further includes two driving circuits, which are respectively located on opposite sides of the display area of ​​the display substrate. The sub-pixels at the central axis of the display substrate have a third brightness L3, and the sub-pixels close to one of the two driving circuits have a fourth brightness L4. The extension direction of the central axis of the display substrate is the same as the extension direction of the driving circuit, and the value range of |L3-L4| is [1, 9].

[0032] For example, a first limiting portion is set between two adjacent pixel openings in a first direction, and a second limiting portion is set between two adjacent pixel openings in a second direction, and the first direction intersects with the second direction; the thickness of the first limiting portion is H1, and the thickness of the second limiting portion is H2, H1≠H2.

[0033] For example, H1 is smaller than H2.

[0034] For example, the display substrate further includes an insulating layer, a blocking dam and an encapsulation layer, wherein the light-emitting element includes a first electrode, a second electrode and a light-emitting functional layer located between the first electrode and the second electrode, the first electrode of the light-emitting element is connected to the pixel circuit through a via hole penetrating the insulating layer, the encapsulation layer is configured to encapsulate the light-emitting element, the encapsulation layer includes a stack of an inorganic encapsulation film and an organic encapsulation film, an encapsulation glue is provided on the outside of the encapsulation layer, the insulating layer includes a planarization layer, the planarization layer includes a first flat portion and a second flat portion, a groove is provided between the first flat portion and the second flat portion, the blocking dam is located at the periphery of the display area of ​​the display substrate, and the orthographic projection of the blocking dam on the base substrate covers the orthographic projection of the groove on the base substrate.

[0035] For example, the display substrate also includes a data line, a first gate line, a second gate line, and a first initialization line, wherein the pixel circuit also includes a data write transistor and a first reset transistor, the first electrode of the data write transistor is connected to the data line, the gate of the drive transistor is connected to the second electrode of the data write transistor, the gate of the data write transistor is connected to the first gate line, the first electrode of the first reset transistor is connected to the first initialization line, the second electrode of the first reset transistor is connected to the gate of the drive transistor, and the gate of the first reset transistor is connected to the second gate line, and the display substrate is provided with a dummy sub-pixel near its edge, the dummy sub-pixel has a dummy drive transistor and a first dummy reset transistor, the first dummy reset transistor is connected to the gate of the dummy drive transistor, and the first dummy reset transistor is disconnected from the first initialization line.

[0036] For example, the display substrate further includes a dummy data line extending along a first direction, the dummy data line being insulated from the data line, the dummy sub-pixel including at least two dummy sub-pixels adjacent in a second direction, and the dummy data lines of the at least two dummy sub-pixels being connected to each other.

[0037] For example, the dummy data line is connected to a constant voltage terminal to be configured to provide a constant voltage.

[0038] For example, the at least two dummy sub-pixels include a first dummy sub-pixel, a second dummy sub-pixel, and a third dummy sub-pixel, and three dummy data lines of the first dummy sub-pixel, the second dummy sub-pixel, and the third dummy sub-pixel are connected to each other.

[0039] For example, the display substrate also includes a first power line, the pixel circuit also includes a light-emitting control transistor, the first electrode of the light-emitting control transistor is connected to the first power line, and the second electrode of the light-emitting control transistor is connected to the second electrode of the driving transistor. The dummy sub-pixel also includes a dummy light-emitting control transistor, the first electrode of the dummy light-emitting control transistor is disconnected from the first power line, and the second electrode of the dummy light-emitting control transistor is connected to the second electrode of the dummy driving transistor.

[0040] For example, the display substrate also includes a pixel defining layer, the pixel defining layer includes a defining portion, the pixel opening is defined by the defining portion, the light-emitting element includes a first electrode and a light-emitting functional layer, the pixel defining layer is configured to expose at least a portion of the first electrode, and the light-emitting functional layer covers the side wall of the defining portion.

[0041] For example, the light-emitting element further includes a second electrode, the light-emitting functional layer is located between the first electrode and the second electrode, and the second electrode is in contact with the top wall of the defining portion.

[0042] For example, the display substrate also includes an insulating layer, the first electrode of the light-emitting element is connected to the pixel circuit through a via hole passing through the insulating layer, the limiting portion includes a first limiting portion and a second limiting portion, the thickness of the first limiting portion is less than the thickness of the second limiting portion, and the orthographic projection of the via hole on the base substrate overlaps with the orthographic projection of the first limiting portion on the base substrate.

[0043] For example, the display substrate also includes a dummy pixel defining layer, which includes a plurality of dummy defining portions, the extension direction of the dummy defining portions is the same as the extension direction of the second defining portions, and the spacing between two adjacent dummy defining portions is greater than the spacing between two adjacent second defining portions.

[0044] For example, the distance between two adjacent dummy defining portions is 2-20 times the distance between two adjacent second defining portions.

[0045] For example, the display substrate further includes a second reset transistor, a second initialization line and an initialization bus, wherein the initialization bus is arranged outside the display area of ​​the display substrate, the first electrode of the second reset transistor is connected to the initialization bus through the second initialization line, the second electrode of the second reset transistor is connected to the light-emitting element through the driving transistor, and the second reset transistor is connected to a row of sub-pixels. For the same row of sub-pixels, the number of the second reset transistors is less than the number of the sub-pixels.

[0046] For example, the display substrate also includes a light-emitting control transistor, a first power line and a first power bus, the first power line is configured to provide a first voltage signal to the pixel circuit, the first power line and the first power bus are connected, the first electrode of the light-emitting control transistor is connected to the first power line, the second electrode of the light-emitting control transistor is connected to the second electrode of the driving transistor, and the number of light-emitting control transistors in a row of sub-pixels is less than the number of sub-pixels in the row.

[0047] For example, the number of light emission control transistors in a row of sub-pixels is greater than the number of second reset transistors.

[0048] For example, the second electrode plate is arranged in the same layer as the channel of the driving transistor, the second electrode plate is closer to the base substrate than the first electrode plate, and the orthographic projection of the second electrode plate on the base substrate overlaps with the orthographic projection of the pixel opening on the base substrate.

[0049] An embodiment of the present disclosure also provides a display substrate, comprising: a base substrate and a plurality of sub-pixels arranged on the base substrate; the sub-pixels include: a pixel circuit, comprising a driving transistor and a storage capacitor, the storage capacitor including a first plate and a second plate, the first plate of the storage capacitor being connected to the gate of the driving transistor, and the second plate of the storage capacitor being connected to the first electrode of the driving transistor; and a light-emitting element electrically connected to the pixel circuit, the pixel circuit being configured to drive the light-emitting element; the sub-pixels include a pixel opening, the pixel opening being configured to define a light-emitting area of ​​the sub-pixel, the orthographic projection of the storage capacitor on the base substrate overlaps with the orthographic projection of the pixel opening on the base substrate, and the orthographic projection of the channel of the driving transistor on the base substrate overlaps with the orthographic projection of the channel of the driving transistor on the base substrate. The orthographic projection of the pixel opening on the base substrate overlaps, the second electrode plate is arranged in the same layer as the channel of the driving transistor, the second electrode plate is closer to the base substrate than the first electrode plate, and the display substrate satisfies the following relationship: the value range of (W*L+S2)*M1 / M2 is [0.014, 0.133], and P=k0*(W / L)*Uc, where the value range of k0 is [2.8*E-07, 5.8*E-06], where W is the width of the channel of the driving transistor, L is the length of the channel of the driving transistor, S2 is the facing area of ​​the second electrode plate and the first electrode plate, M1 is the number of pixel openings of the display substrate, M2 is the area of ​​the display substrate, Uc is the voltage across the light-emitting element, and P is the power consumption of the sub-pixel.

[0050] An embodiment of the present disclosure further provides a display substrate, comprising: a base substrate and a plurality of sub-pixels arranged on the base substrate; the sub-pixels comprising: a pixel circuit, comprising a driving transistor and a storage capacitor, the storage capacitor comprising a first plate and a second plate, the first plate of the storage capacitor being connected to the gate of the driving transistor, the second plate of the storage capacitor being connected to the first electrode of the driving transistor; and a light-emitting element electrically connected to the pixel circuit, the pixel circuit being configured to drive the light-emitting element, the sub-pixels comprising a pixel opening, the pixel opening being configured to define a light-emitting area of ​​the sub-pixel, the orthographic projection of the storage capacitor on the base substrate overlapping with the orthographic projection of the pixel opening on the base substrate, the channel of the driving transistor on the base substrate The orthographic projection overlaps with the orthographic projection of the pixel opening on the base substrate, the second electrode plate is arranged in the same layer as the channel of the driving transistor, the second electrode plate is closer to the base substrate than the first electrode plate, a first limiting portion is set between two adjacent pixel openings in the first direction, and a second limiting portion is set between two adjacent pixel openings in the second direction, and the first direction intersects with the second direction; the thickness of the first limiting portion is H1, the thickness of the second limiting portion is H2, H1≠H2; the display substrate satisfies the following relationship: the value range of S2 / (W*L) is [2.82, 28.85], where W is the width of the channel of the driving transistor, L is the length of the channel of the driving transistor, and S2 is the facing area of ​​the second electrode plate and the first electrode plate.

[0051] An embodiment of the present disclosure also provides a display substrate, comprising: a base substrate and a plurality of sub-pixels arranged on the base substrate; the sub-pixels include: a pixel circuit, comprising a driving transistor and a storage capacitor, the storage capacitor including a first plate and a second plate, the first plate of the storage capacitor being connected to the gate of the driving transistor, and the second plate of the storage capacitor being connected to the first electrode of the driving transistor; and a light-emitting element electrically connected to the pixel circuit, the pixel circuit being configured to drive the light-emitting element, wherein the sub-pixel includes a pixel opening, the pixel opening being configured to define a light-emitting area of ​​the sub-pixel, the orthographic projection of the storage capacitor on the base substrate overlaps with the orthographic projection of the pixel opening on the base substrate, the orthographic projection of the channel of the driving transistor on the base substrate overlaps with the orthographic projection of the pixel opening on the base substrate, the second plate is arranged on the same layer as the channel of the driving transistor, and the second plate is closer to the base substrate than the first plate, and the display substrate also includes an insulating layer , a blocking dam and an encapsulation layer, wherein the light-emitting element includes a first electrode, a second electrode and a light-emitting functional layer located between the first electrode and the second electrode, the first electrode of the light-emitting element is connected to the pixel circuit through a via hole penetrating the insulating layer, the encapsulation layer is configured to encapsulate the light-emitting element, the encapsulation layer includes a stack of an inorganic encapsulation film and an organic encapsulation film, and an encapsulation glue is provided on the outer side of the encapsulation layer, the insulating layer includes a planarization layer, the planarization layer includes a first flat portion and a second flat portion, a groove is provided between the first flat portion and the second flat portion, the blocking dam is located at the periphery of the display area of ​​the display substrate, and the orthographic projection of the blocking dam on the base substrate covers the orthographic projection of the groove on the base substrate; the display substrate satisfies the following relationship: the value range of S2 / (W*L) is [2.82, 28.85], wherein W is the width of the channel of the driving transistor, L is the length of the channel of the driving transistor, and S2 is the facing area of ​​the second electrode plate and the first electrode plate.

[0052] The embodiment of the present disclosure further provides a display substrate, comprising: a base substrate and a plurality of sub-pixels arranged on the base substrate; the sub-pixels comprising: a pixel circuit, comprising a driving transistor and a storage capacitor, the storage capacitor comprising a first plate and a second plate, the first plate of the storage capacitor being connected to the gate of the driving transistor, the second plate of the storage capacitor being connected to the first electrode of the driving transistor; and a light-emitting element electrically connected to the pixel circuit, the pixel circuit being configured to drive the light-emitting element, the sub-pixels comprising a pixel opening, the pixel opening being configured to define a light-emitting area of ​​the sub-pixel, the storage capacitor being arranged in the The orthographic projection on the substrate overlaps with the orthographic projection of the pixel opening on the substrate, the orthographic projection of the channel of the driving transistor on the substrate overlaps with the orthographic projection of the pixel opening on the substrate, the second electrode plate and the channel of the driving transistor are arranged on the same layer, the second electrode plate is closer to the substrate than the first electrode plate, and the display substrate satisfies the following relationship: the value range of S2 / (W*L) is [2.82, 28.85], where W is the width of the channel of the driving transistor, L is the length of the channel of the driving transistor, and S2 is the facing area of ​​the second electrode plate and the first electrode plate.

[0053] An embodiment of the present disclosure further provides a display substrate, comprising: a base substrate and a plurality of sub-pixels arranged on the base substrate; the sub-pixels comprising: a pixel circuit comprising a driving transistor and a storage capacitor, the storage capacitor comprising a first plate and a second plate, the first plate of the storage capacitor being connected to the gate of the driving transistor, and the second plate of the storage capacitor being connected to the first electrode of the driving transistor; and a light-emitting element electrically connected to the pixel circuit, the pixel circuit being configured to drive the light-emitting element, the sub-pixel comprising a pixel opening, the pixel opening being configured to define a light-emitting area of ​​the sub-pixel, the orthographic projection of the storage capacitor on the base substrate overlapping with the orthographic projection of the pixel opening on the base substrate, the orthographic projection of the channel of the driving transistor on the base substrate overlapping with the orthographic projection of the pixel opening on the base substrate, the second plate being arranged in the same layer as the channel of the driving transistor, and the second plate being closer to the base substrate than the first plate, and the display substrate further comprising a data line, a first gate line, a second gate line, and a first initialization line , wherein the pixel circuit further includes a data write transistor and a first reset transistor, a first electrode of the data write transistor is connected to the data line, a gate of the drive transistor is connected to the second electrode of the data write transistor, the gate of the data write transistor is connected to the first gate line, a first electrode of the first reset transistor is connected to the first initialization line, a second electrode of the first reset transistor is connected to the gate of the drive transistor, and the gate of the first reset transistor is connected to the second gate line, the display substrate is provided with a dummy sub-pixel near its edge, the dummy sub-pixel has a dummy drive transistor and a first dummy reset transistor, the first dummy reset transistor is connected to the gate of the dummy drive transistor, and the first dummy reset transistor is disconnected from the first initialization line; the display substrate satisfies the following relationship: the value range of S2 / (W*L) is [2.82, 28.85], wherein W is the width of the channel of the drive transistor, L is the length of the channel of the drive transistor, and S2 is the facing area of ​​the second electrode plate and the first electrode plate.

[0054] An embodiment of the present disclosure also provides a display substrate, comprising: a base substrate and a plurality of sub-pixels arranged on the base substrate; the sub-pixels include: a pixel circuit, comprising a driving transistor and a storage capacitor, the storage capacitor including a first plate and a second plate, the first plate of the storage capacitor being connected to the gate of the driving transistor, and the second plate of the storage capacitor being connected to the first electrode of the driving transistor; and a light-emitting element electrically connected to the pixel circuit, the pixel circuit being configured to drive the light-emitting element, the sub-pixels including a pixel opening, the pixel opening being configured to define a light-emitting area of ​​the sub-pixel, the orthographic projection of the storage capacitor on the base substrate overlapping with the orthographic projection of the pixel opening on the base substrate, the orthographic projection of the channel of the driving transistor on the base substrate overlapping with the orthographic projection of the channel of the driving transistor on the base substrate. The pixel opening overlaps with the orthographic projection of the base substrate, the second electrode is arranged in the same layer as the channel of the driving transistor, the second electrode is closer to the base substrate than the first electrode, the display substrate also includes a pixel defining layer, wherein the pixel defining layer includes a defining portion, the pixel opening is defined by the defining portion, the light-emitting element includes a first electrode and a light-emitting functional layer, the pixel defining layer is configured to expose at least a portion of the first electrode, the light-emitting functional layer covers the side wall of the defining portion, and the display substrate satisfies the following relationship: the value range of S2 / (W*L) is [2.82, 28.85], wherein W is the width of the channel of the driving transistor, L is the length of the channel of the driving transistor, and S2 is the facing area of ​​the second electrode and the first electrode.

[0055] For example, any of the above-mentioned display substrates that satisfies the value range of S2 / (W*L) of [2.82, 28.85] may also satisfy the following relationship: the value range of (W*L+S2)*M1 / M2 is [0.014, 0.133], where M1 is the number of pixel openings of the display substrate, and M2 is the area of ​​the display substrate.

[0056] For example, in any of the above-mentioned display substrates that satisfies the value range of S2 / (W*L) of [2.82, 28.85] and / or the value range of (W*L+S2)*M1 / M2 of [0.014, 0.133], the following relationship may also be satisfied: P=k0*(W / L)*Uc, where the value range of k0 is [2.8*E-07, 5.8*E-06], Uc is the cross-voltage of the light-emitting element, and P is the power consumption of the sub-pixel.

[0057] An embodiment of the present disclosure further provides a display device comprising any of the above-mentioned display substrates. BRIEF DESCRIPTION OF THE DRAWINGS

[0058] In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure, the drawings of the embodiments will be briefly introduced below. Obviously, the drawings in the following description only relate to some embodiments of the present disclosure, rather than limiting the present disclosure.

[0059] FIG. 1 is a schematic diagram showing a pixel arrangement of a display substrate.

[0060] FIG2 is a schematic diagram of a pixel circuit in a display substrate driving a light-emitting element to emit light according to an embodiment of the present disclosure.

[0061] FIG3 is a circuit diagram of a display substrate provided by another embodiment of the present disclosure.

[0062] FIG4 is a circuit diagram of a display substrate provided by another embodiment of the present disclosure.

[0063] FIG5 is a layout diagram of a display substrate provided in accordance with an embodiment of the present disclosure.

[0064] FIG6 is a cross-sectional view taken along line A1 - A2 of FIG5 .

[0065] 7A to 7G are plan views of a single layer of the display substrate in FIG. 5 .

[0066] 8A to 8E are plan views of a partial stack of display substrates in FIG. 5 .

[0067] FIG. 8F is a schematic diagram illustrating the width and length of a channel of a driving transistor in the display substrate of FIG. 5 .

[0068] FIG9 is a layout diagram of a display substrate provided in accordance with an embodiment of the present disclosure.

[0069] FIG10 is a layout diagram of a display substrate provided in another embodiment of the present disclosure.

[0070] FIG11 is a layout diagram of a display substrate provided in another embodiment of the present disclosure.

[0071] FIG12 is a layout diagram of a display substrate provided in another embodiment of the present disclosure.

[0072] FIG13 is a layout diagram of a display substrate provided in another embodiment of the present disclosure.

[0073] FIG14 is a layout diagram of a display substrate provided in another embodiment of the present disclosure.

[0074] FIG15 is a stack-up diagram of some film layers in FIG14 .

[0075] FIG16 is a layout diagram of a display substrate provided in another embodiment of the present disclosure.

[0076] FIG17 is a stack-up diagram of some film layers in FIG16 .

[0077] FIG18 is a stacking diagram of some film layers of a display substrate provided by one embodiment of the present disclosure.

[0078] FIG19 is a stacking diagram of some film layers of a display substrate provided by one embodiment of the present disclosure.

[0079] FIG20 is a stacking diagram of some film layers of a display substrate provided by one embodiment of the present disclosure.

[0080] FIG21 is a schematic diagram of a central point pixel of a display substrate provided by an embodiment of the present disclosure.

[0081] FIG22 is a cross-sectional view taken along line B1 - B2 of FIG21 .

[0082] FIG. 23 is a schematic diagram showing the coordinate distances of chromaticity coordinate points of a substrate at two different viewing angles.

[0083] FIG24 is a layout diagram of a display substrate provided in accordance with an embodiment of the present disclosure.

[0084] FIG25 is a plan view of a display substrate provided in accordance with an embodiment of the present disclosure.

[0085] FIG26 is a plan view of a display substrate provided in accordance with an embodiment of the present disclosure.

[0086] FIG27 is a plan view of a display substrate provided in accordance with an embodiment of the present disclosure.

[0087] FIG28 is a plan view of a display substrate provided in accordance with an embodiment of the present disclosure.

[0088] FIG29 is a layout diagram of a display substrate provided in accordance with an embodiment of the present disclosure.

[0089] FIG30 is a schematic diagram of a display substrate provided in accordance with an embodiment of the present disclosure.

[0090] FIG31 is a schematic diagram of a display substrate provided in accordance with an embodiment of the present disclosure.

[0091] FIG32 is a schematic diagram of a display substrate provided in accordance with an embodiment of the present disclosure.

[0092] FIG33A is a plan view of a pixel defining layer in a display substrate provided in an embodiment of the present disclosure.

[0093] FIG33B is a plan view of a pixel defining layer in a display substrate provided in an embodiment of the present disclosure.

[0094] FIG34 is a schematic diagram of a display substrate provided in accordance with an embodiment of the present disclosure.

[0095] FIG35 is an electron microscope image of a display substrate provided in accordance with an embodiment of the present disclosure.

[0096] FIG36 is a schematic diagram of a display substrate provided in accordance with an embodiment of the present disclosure.

[0097] FIG37 is a schematic diagram of a display substrate provided in accordance with an embodiment of the present disclosure.

[0098] FIG38 is a circuit diagram of a dummy sub-pixel in a display substrate provided in accordance with an embodiment of the present disclosure.

[0099] FIG39 is a layout diagram of a dummy pixel circuit in a display substrate provided in an embodiment of the present disclosure.

[0100] FIG40 is a schematic diagram of a display substrate provided in accordance with an embodiment of the present disclosure.

[0101] FIG41A is a schematic diagram of a display substrate provided in accordance with an embodiment of the present disclosure.

[0102] FIG41B is a schematic diagram of a display substrate provided in accordance with another embodiment of the present disclosure.

[0103] FIG42 is a schematic diagram of a display substrate provided in accordance with an embodiment of the present disclosure.

[0104] FIG43 is a schematic diagram of a display substrate provided in accordance with an embodiment of the present disclosure.

[0105] FIG44 is a circuit diagram of a display substrate provided in accordance with an embodiment of the present disclosure.

[0106] FIG45 is a schematic diagram of a display substrate provided in accordance with an embodiment of the present disclosure.

[0107] FIG46 is a schematic diagram of a brightness test of a display substrate provided in accordance with an embodiment of the present disclosure. DETAILED DESCRIPTION

[0108] To make the purpose, technical solutions, and advantages of the embodiments of the present disclosure more clear, the technical solutions of the embodiments of the present disclosure will be clearly and completely described below in conjunction with the accompanying drawings of the embodiments of the present disclosure. Obviously, the described embodiments are part of the embodiments of the present disclosure, not all of the embodiments. Based on the described embodiments of the present disclosure, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present disclosure.

[0109] Unless otherwise defined, the technical or scientific terms used in this disclosure should have the usual meanings understood by persons of ordinary skill in the field to which this disclosure belongs. The words "first", "second" and similar terms used in this disclosure do not indicate any order, quantity or importance, but are only used to distinguish different components. Similarly, words such as "include" or "comprise" mean that the elements or objects appearing before the word include the elements or objects listed after the word and their equivalents, without excluding other elements or objects. Words such as "connect" or "connected" are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. "Up", "down", "left", "right" and the like are only used to indicate relative positional relationships. When the absolute position of the object being described changes, the relative positional relationship may also change accordingly.

[0110] In conventional organic light-emitting diode displays, the organic light-emitting layer requires an evaporation process, which has stringent process conditions and is difficult to achieve on a large area.

[0111] Inkjet printing is the optimal method for producing OLED light-emitting material layers at low cost, enabling OLED displays to compete in the mid- to high-end market. Inkjet printing is a highly efficient process that produces less material waste than vapor deposition and is also very fast.

[0112] When inkjet printing forms the light-emitting functional layer of an organic light-emitting diode, a solvent is mainly used to dissolve the organic material to form a solution (ink), and then the solution (ink) is directly sprayed on the surface of the substrate to form a light-emitting functional layer of sub-pixels such as red (R), green (G), and blue (B). Inkjet printing OLED technology has obvious advantages over evaporation technology in terms of manufacturing process, yield and cost. For example, the light-emitting functional layer includes multiple film layers, such as a light-emitting layer (light-emitting material layer), and the light-emitting functional layer may also include at least one of a hole injection layer, a hole transport layer, an electron transport layer, and an electron injection layer. The organic light-emitting functional layer can be selected as needed. At least one film layer in the light-emitting functional layer can be produced using an inkjet printing process.

[0113] Due to the large molecular weight of polymers, films are primarily formed using solution processing methods, such as spin coating or printing. Inkjet printing is the optimal method for preparing light-emitting polymer solutions. In recent years, significant efforts have been made to improve the pixel resolution, film uniformity, and lifespan of displays, and research on inkjet printing for optoelectronic materials has become increasingly active. For example, layers such as the hole transport layer, hole injection layer, and light-emitting layer of displays can all be prepared using inkjet printing, laying the foundation for the adoption of fully printed methods for display production.

[0114] When using an inkjet printing process to produce the film layer in the light-emitting functional layer, the flatness requirements for the light-emitting functional layer are high. The flatter the light-emitting functional layer in each sub-pixel, the more it can reduce or avoid color shift, and the better the display effect of the display substrate. To achieve a flat light-emitting functional layer, this can be achieved by adjusting the structure of the display substrate. The display substrate provided in the embodiments of the present disclosure can solve the color shift problem of the entire display substrate at 45-degree and 60-degree left and right viewing angles.

[0115] Figure 1 is a schematic diagram of a pixel arrangement on a display substrate. As shown in Figure 1 , the display substrate includes a plurality of sub-pixels 100 disposed on a base substrate, and the plurality of sub-pixels 100 are arranged in an array. As shown in Figure 1 , the plurality of sub-pixels 100 are arranged in an array along a first direction Y and a second direction X. The embodiments of the present disclosure are described using the plurality of sub-pixels 100 arranged in an array as shown in Figure 1 , but the arrangement of the plurality of sub-pixels 100 is not limited to that shown in Figure 1 .

[0116] As shown in FIG1 , a display substrate includes a plurality of pixels PX, each pixel PX including a plurality of sub-pixels 100. As shown in FIG1 , the plurality of sub-pixels 100 include a first sub-pixel 101, a second sub-pixel 102, and a third sub-pixel 103. As shown in FIG1 , each pixel PX includes a first sub-pixel 101, a second sub-pixel 102, and a third sub-pixel 103. The first sub-pixel 101, the second sub-pixel 102, and the third sub-pixel 103 emit light of different colors. Sub-pixels in the same column emit light of the same color, and in the same row of sub-pixels, the plurality of pixels PX are arranged sequentially. The embodiments of the present disclosure are described by taking the first direction Y as the column direction and the second direction X as the row direction as an example. In other embodiments, the first direction Y may be the row direction, and the second direction X may be the column direction.

[0117] The embodiment of the present disclosure is described by taking as an example that the first sub-pixel 101 is a red sub-pixel, the second sub-pixel 102 is a green sub-pixel, and the third sub-pixel 103 is a blue sub-pixel.

[0118] As shown in Figure 1 , the base substrate BS includes a display area R01 and a peripheral area R02 located on at least one side of the display area R01. Figure 1 takes the peripheral area R02 surrounding the display area R01 as an example for explanation.

[0119] Figure 2 is a schematic diagram of a pixel circuit in a display substrate driving a light-emitting element to emit light according to an embodiment of the present disclosure. Figure 3 is a schematic diagram of a circuit of a display substrate according to another embodiment of the present disclosure. Figure 4 is a schematic diagram of a circuit of a display substrate according to another embodiment of the present disclosure.

[0120] As shown in Figures 2 to 4, each sub-pixel 100 includes a pixel circuit 100a and a light-emitting element 100b. The pixel circuit 100a is electrically connected to the light-emitting element 100b, and the pixel circuit 100a is configured to drive the light-emitting element 100b. For example, the pixel circuit 100a is configured to drive the light-emitting element 100b to emit light. The light-emitting element 100b includes a light-emitting area. The pixel arrangement shown in Figure 1 refers to the location of the light-emitting area of ​​the light-emitting element 100b in the sub-pixel 100.

[0121] Figures 2 and 3 include a pixel circuit and a light-emitting element in one sub-pixel. Figure 4 shows three sub-pixels. The three sub-pixels in Figure 4 are located in a row.

[0122] For example, as shown in Figures 2 to 4, in a sub-pixel 100, the pixel circuit 100a includes a data write transistor T1, a reset transistor T2, a drive transistor T3, and a storage capacitor Cst. The light-emitting element 100b is connected to the drive transistor T3. The reset transistor T2 is configured to reset the gate T3g of the drive transistor T3. As shown in Figures 2 to 4, the storage capacitor Cst includes a first terminal C1 and a second terminal C2.

[0123] For example, as shown in Figures 2 to 4, the display substrate includes a gate line G1, a gate line G2, a data line DT, a first power line PL1, a second power line PL2, an initialization line INT1, etc. The gate line G2 can also be called a reset control signal line. For example, the first power line PL1 is configured to provide a constant first voltage signal VDD to the sub-pixel 100, the second power line PL2 is configured to provide a constant second voltage signal VSS to the sub-pixel 100, and the first voltage signal VDD is greater than the second voltage signal VSS. The gate line G1 is configured to provide a scan signal SCAN to the sub-pixel 100, the gate line G2 is configured to provide a reset control signal RESET1 to the sub-pixel 100, and the data line DT is configured to provide a data signal (data voltage) DATA to the sub-pixel 100. The initialization line INT1 is configured to provide an initialization signal Vinit1 to the sub-pixel 100.

[0124] As shown in FIG. 2 to FIG. 4 , the driving transistor T3 is electrically connected to the light emitting element 100 b and outputs a driving current under the control of the scan signal SCAN, the data signal DATA, the first voltage signal VDD, the second voltage signal VSS and other signals to drive the light emitting element 100 b to emit light.

[0125] For example, the light emitting element 100 b includes an organic light emitting diode (OLED), and the light emitting element 100 b emits red light, green light, blue light, or white light when driven by its corresponding pixel circuit 100 a.

[0126] For example, as shown in Figures 2 to 4, the first electrode E1 of the light-emitting element 100b is connected to the first electrode T3a of the driving transistor T3, the second electrode E2 of the light-emitting element 100b is connected to the second power line PL2, the second electrode T3b of the driving transistor T3 is connected to the first power line PL1, the gate T3g of the driving transistor T3 is connected to the second electrode T1b of the data writing transistor T1, the first electrode T1a of the data writing transistor T1 is connected to the data line DT, and the gate T1g of the data writing transistor T1 is connected to the gate line G1.

[0127] For example, as shown in Figures 2 to 4, the gate T3g of the driving transistor T3 is connected to the first terminal C1 of the storage capacitor Cst, and the second terminal C2 of the storage capacitor Cst is connected to the first electrode T3a of the driving transistor T3. The first terminal C1 of the storage capacitor Cst is also connected to the second electrode T1b of the data writing transistor T1.

[0128] For example, as shown in Figures 2 to 4, a first electrode T2a of the reset transistor T2 is connected to the initialization line INT1, a second electrode T2b of the reset transistor T2 is connected to the gate T3g of the drive transistor T3, and the gate T2g of the reset transistor T2 is connected to the gate line G2. A first terminal C1 of the storage capacitor Cst is also connected to the second electrode T2b of the reset transistor T2.

[0129] For example, as shown in Figures 2 to 4, the gate T3g of the driving transistor T3, the first end C1 of the storage capacitor Cst, the second electrode T1b of the data writing transistor T1, and the second electrode T2b of the reset transistor T2 are connected to each other and are all connected to the node N1, which is at the same potential.

[0130] For example, as shown in FIG2 to FIG4, the second end C2 of the storage capacitor Cst, the first electrode E1 of the light emitting element 100b, and the first electrode T3a of the driving transistor T3 are connected to each other and are all connected to the node N2 and have the same potential.

[0131] For example, as shown in FIG. 3 and FIG. 4 , the display substrate further includes a reset transistor T4 , and the reset transistor T4 is configured to reset the first electrode E1 of the light emitting element 100 b .

[0132] For example, as shown in Figures 3 and 4, the display substrate further includes a gate line G4, which may also be referred to as a reset control signal line. The gate line G4 is configured to provide a reset control signal RESET2 to the reset transistor T4.

[0133] For example, as shown in FIG. 3 and FIG. 4 , the display substrate further includes an initialization line INT2 , and the initialization line INT2 is configured to provide an initialization signal Vinit2 to the reset transistor T4 .

[0134] For example, as shown in FIG3 and FIG4 , the first electrode T4a of the reset transistor T4 is connected to the initialization line INT2 , the second electrode T4b of the reset transistor T4 is connected to the first electrode E1 of the light emitting element 100b , and the gate T4g of the reset transistor T4 is connected to the gate line G4 .

[0135] For example, as shown in Figures 3 and 4, the second electrode T4b of the reset transistor T4 is connected to the first electrode E1 of the light-emitting element 100b through the driving transistor T3, the first electrode T3a of the driving transistor T3 is connected to the first electrode E1 of the light-emitting element 100b, and the second electrode T3b of the driving transistor T3 is connected to the second electrode T4b of the reset transistor T4.

[0136] For example, the initialization signal Vinit1 and the initialization signal Vinit2 are constant voltage signals, whose magnitudes may be between the first voltage signal VDD and the second voltage signal VSS, but are not limited thereto. For example, the initialization signal Vinit1 and the initialization signal Vinit2 may both be less than or equal to the second voltage signal VSS.

[0137] For example, in some embodiments of the present disclosure, the initialization line INT1 and the initialization line INT2 are connected and are both configured to provide the same initialization signal, that is, the initialization signal Vinit1 and the initialization signal Vinit2 are equal, but the present invention is not limited thereto. In other embodiments, the initialization line INT1 and the initialization line INT2 are insulated from each other to provide different initialization signals.

[0138] For example, as shown in FIG2 , the second electrode T3 b of the driving transistor T3 is directly connected to the first power line PL1. As shown in FIG3 and FIG4 , the display substrate further includes a gate line G5 and a light-emission control transistor T5. The gate line G5 is configured to provide a light-emission control signal EM to the light-emission control transistor T5. The second electrode T3 b of the driving transistor T3 is connected to the first power line PL1 through the light-emission control transistor T5.

[0139] 3 and 4 , the first electrode T5a of the emission control transistor T5 is connected to the first power line PL1 , the second electrode T5b of the emission control transistor T5 is connected to the second electrode T3b of the driving transistor T3 , and the gate T5g of the emission control transistor T5 is connected to the gate line G5 .

[0140] For example, as shown in FIG3 and FIG4 , the second electrode T5b of the light emission control transistor T5, the second electrode T4b of the reset transistor T4, and the second electrode T3b of the driving transistor T3 are connected to each other and are all connected to the node N3 and have the same potential.

[0141] For example, as shown in FIG4 , the plurality of sub-pixels 100 include a first sub-pixel 101, a second sub-pixel 102, and a third sub-pixel 103. For example, the first sub-pixel 101, the second sub-pixel 102, and the third sub-pixel 103 are sequentially arranged along the second direction X. Of course, the sub-pixels within a pixel may also be arranged in other ways.

[0142] For example, as shown in FIG4 , the driving transistor T3 is a dual-gate transistor, including a sub-transistor T31 and a sub-transistor T32. As shown in FIG4 , the sub-transistor T31 and the sub-transistor T32 are connected in series. FIG4 illustrates the driving transistor T3 as a dual-gate transistor. In other embodiments, in addition to the driving transistor T3, other transistors may also be configured as dual-gate transistors. That is, each transistor in the pixel circuit may be configured as a single-gate transistor or a dual-gate transistor as needed.

[0143] For example, as shown in FIG3 and FIG4 , the display substrate includes a reset signal transmission line INI, and the second electrode T4b of the reset transistor T4 is connected to the second electrode T3b (node ​​N3) of the driving transistor through the reset signal transmission line INI.

[0144] Figure 5 is a layout diagram of a display substrate provided in one embodiment of the present disclosure. Figure 6 is a cross-sectional view taken along line A1-A2 of Figure 5. Figures 7A to 7G are plan views of a single layer of the display substrate in Figure 5. Figures 8A to 8E are plan views of a portion of the stacked layers of the display substrate in Figure 5. Figure 8F is a schematic diagram illustrating the width and length of the channel of a drive transistor in the display substrate in Figure 5.

[0145] For example, as shown in Figure 6, the display substrate includes a base substrate BS, a barrier layer BR located on the base substrate BS, and a buffer layer BF. As shown in Figure 6, an active layer LY0 and a gate insulation layer GI located on the active layer LY0 are disposed on the buffer layer BF. A first conductive pattern layer LY1 is located on the gate insulation layer GI, an interlayer insulation layer ILD is located on the first conductive pattern layer LY1, a second conductive pattern layer LY2 is located on the interlayer insulation layer ILD, an insulation layer ISL is located on the second conductive pattern layer LY2, and a first electrode layer LY3 is located on the insulation layer ISL. Figures 5 and 6 illustrate the first terminal C1 and the second terminal C2 of the storage capacitor Cst. The first terminal C1 includes a first electrode plate Ca (as shown in Figure 7B), and the second terminal C2 includes a second electrode plate Cb (as shown in Figure 7A) and a third electrode plate Cc (as shown in Figure 7D).

[0146] For example, as shown in FIG. 6 , the first conductive pattern layer LY1 is closer to the base substrate BS than the second conductive pattern layer LY2 .

[0147] For example, as shown in Figures 5 and 6, a display substrate is provided according to an embodiment of the present disclosure, and the display substrate includes a base substrate BS and a sub-pixel 100 disposed on the base substrate BS. The sub-pixel 100 may be provided in plurality.

[0148] For example, as shown in Figures 5 and 6 , the display substrate further includes a pixel defining layer PDL, and the sub-pixel 100 includes a pixel opening P0, which is configured to expose at least a portion of the first electrode E1, and the pixel opening P0 is configured to define a light-emitting area of ​​the sub-pixel 100. For example, as shown in Figure 6 , the slope angle of the portion of the pixel defining layer PDL that defines the pixel opening P0 is 40-65 degrees.

[0149] For example, as shown in Figures 5 and 6, the sub-pixel 100 includes: a pixel circuit 100a and a light-emitting element 100b, the pixel circuit 100a includes a storage capacitor Cst, the second plate Cb is closer to the substrate BS than the first plate Ca, and the first plate Ca is closer to the substrate BS than the third plate Cc; the light-emitting element 100b includes a first electrode E1, a second electrode E2, and a light-emitting functional layer FL located between the first electrode E1 and the second electrode E2, and the pixel circuit 100a is configured to drive the light-emitting element 100b.

[0150] FIG6 takes the example of each film layer of the light-emitting functional layer FL being formed by inkjet printing, that is, each film layer of the light-emitting functional layer FL is disposed in the pixel opening P0. However, in other implementations, some film layers of the light-emitting functional layer FL may be formed by inkjet printing, while some film layers of the light-emitting functional layer FL may be formed by evaporation. The film layers formed by evaporation may be common layers. For an example of this situation, see FIG45 .

[0151] In some figures of the embodiments of the present disclosure, a plan view illustrates a first direction Y and a second direction X, while a cross-sectional view illustrates a third direction Z. The first direction Y and the second direction X are both parallel to the main surface of the base substrate BS. The third direction Z is perpendicular to the main surface of the base substrate BS. For example, the first direction Y and the second direction X intersect. The embodiments of the present disclosure are described using the example of the first direction Y and the second direction X being perpendicular. As shown in Figure 6, the main surface of the base substrate BS is the surface of the base substrate BS used to manufacture various components. As shown in Figure 6, the top surface of the base substrate BS is the main surface of the base substrate BS.

[0152] For example, as shown in FIG. 5 , FIG. 7B , and FIG. 7D , the first power line PL1 includes a first power signal line PL11 extending along the second direction X and a first power connection line PL12 extending along the first direction Y. The first power signal line PL11 and the first power connection line PL12 are connected.

[0153] For example, as shown in Figures 5, 7B, and 7D, the data line DT extends along the first direction Y, and the data line DT is formed in segments. The data line DT includes a first portion DTa, a second portion DTb, and a third portion DTc. The first portion DTa and the third portion DTc are connected through the second portion DTb. The first portion DTa and the third portion DTc are located in the first conductive pattern layer LY1, and the second portion DTb is located in the second conductive pattern layer LY2.

[0154] In an embodiment of the present disclosure, the elements located in the second conductive pattern layer LY2 can be connected to the elements located in the first conductive pattern layer LY1 and the elements located in the active layer LY0 through vias, and the elements located in the first conductive pattern layer LY1 and the elements located in the active layer LY0 can be connected through the elements located in the second conductive pattern layer LY2.

[0155] For example, the insulating layer that the via hole penetrates may be determined according to the condition of the insulating layer between two conductive pattern layers connected by the via hole.

[0156] As shown in Figures 5, 7B, and 7D, a display substrate according to some embodiments of the present disclosure employs an active layer LY0, a first conductive pattern layer LY1, and a second conductive pattern layer LY2 to form a pixel circuit 100a, thereby simplifying the manufacturing process and reducing the thickness of the display substrate. The initialization line INT1 and / or the first power line PL1 may be referred to as a conductive structure 40. The conductive structure 40 includes a signal transmission line 411 and a signal connection line 412. The conductive structure 40 is configured to provide a voltage signal to the sub-pixel 100. The signal transmission line 411 extends along the second direction X, and the signal connection line 412 extends along the first direction Y. The signal connection line 412 is electrically connected to the signal transmission line 411.

[0157] 5 , the conductive structure 40 includes a conductive structure 400 and a conductive structure 401. As shown in FIG5 , the first power line PL1 may be referred to as the conductive structure 400, and the initialization line INT1 may be referred to as the conductive structure 401.

[0158] For example, as shown in FIG. 5 , the conductive structure 40 adopts a mesh structure, including a portion extending along the first direction Y (ie, the signal connection line 412 ) and a portion extending along the second direction X (ie, the signal transmission line 411 ).

[0159] For example, as shown in Figures 5, 7B, and 7D, two conductive pattern layers are used to form the first power line PL1 of the pixel circuit 100a. As shown in Figures 5, 7B, and 7D, the portion of the first power line PL1 extending along the first direction Y is formed in segments. As shown in Figures 5 and 7D, the portion of the first power line PL1 extending along the second direction X is located in the second conductive pattern layer LY2.

[0160] For example, as shown in Figures 5, 7B, and 7D, the signal connection line 412 includes a first portion 412a, a second portion 412b, and a third portion 412c. The first portion 412a and the third portion 412c are connected by the second portion 412b. The first portion 412a and the third portion 412c are located on the first conductive pattern layer LY1, and the second portion 412b is located on the second conductive pattern layer LY2. The signal connection line 412 includes a first power connection line PL12.

[0161] For example, as shown in FIG5 , the first portion PLa and the second portion PLb of the first power connection line PL12 are connected through a via Va, and the second portion PLb and the third portion PLc of the first power connection line PL12 are connected through a via Vb.

[0162] For example, as shown in FIG5 , the first power signal line PL11 and the first power connection line PL12 are connected through a via V0 .

[0163] For example, as shown in FIG. 5 , the first portion DTa and the second portion DTb of the data line DT are connected through a via hole Vc, and the second portion DTb and the third portion DTc of the data line DT are connected through a via hole Vd.

[0164] 7A shows an active layer LY0. The active layer LY0 includes polysilicon, but is not limited thereto.

[0165] FIG7B shows the first conductive pattern layer LY1. As shown in FIG7B , the first conductive pattern layer LY1 includes a first terminal C1 (first electrode Ca), a connecting electrode CEa, a connecting electrode CEb, a connecting electrode CEc, a connecting electrode CEd, a connecting electrode CEe, a first portion DTa of a data line DT, a third portion DTc of a data line DT, a first portion PLa of a first power connection line PL12, and a third portion PLc of a first power connection line PL12.

[0166] Fig. 7C shows an interlayer insulating layer ILD, shown with vias in the interlayer insulating layer ILD. Fig. 7C shows vias V1 to V13, vias Va to Vd, and via V0.

[0167] FIG7D shows the second conductive pattern layer LY2. As shown in FIG7D, the second conductive pattern layer LY2 includes a third electrode plate Cc at the second end C2, a connecting electrode CEf, gate lines G1, G2, and G5, a reset signal transmission line INI, an initialization signal line INT11, and a first power signal line PL11.

[0168] Figure 7E shows the insulating layer ISL, shown with a via hole in the insulating layer ISL. Figure 7E shows a via hole VH.

[0169] Fig. 7F shows the first electrode layer LY3 of the light emitting element. Fig. 7F shows the first electrode E1.

[0170] Figure 7G shows the pixel defining layer (PDL), with pixel opening P0 in the PDL being used as an example. Pixel opening P0 corresponds to the effective light-emitting area of ​​the sub-pixel. When the display substrate utilizes an inkjet printing process to produce at least one film layer in the light-emitting functional layer FL, the inkjet-printed film layer is positioned within pixel opening P0 in the PDL.

[0171] 5 to 8E , the first power signal line PL11 and the first power connection line PL12 are connected through a via V0 .

[0172] 5 to 8E , the connection electrode CEa is connected to the gate line G5 through the via hole V9 , and the connection electrode CEa serves as the gate of the light emission control transistor T5 .

[0173] 5 to 8E , one end of the connection electrode CEb is connected to the first power line PL1 (first power signal line PL11 ) through a via V11 , and the other end of the connection electrode CEb is connected to the first electrode T5 a of the emission control transistor T5 through a via V10 .

[0174] 5 to 8E , the connection electrode CEc is connected to the gate line G1 through the via hole V12 , and the connection electrode CEc serves as the gate of the data writing transistor T1 .

[0175] 5 to 8E , the data line DT is connected to the first electrode T1 a of the data writing transistor T1 through a via V4 .

[0176] 5 to 8E , the connection electrode CEd is connected to the gate line G2 through the via hole V6 , and the connection electrode CEd serves as the gate of the reset transistor T2 .

[0177] 5 to 8E , one end of the connection electrode CEe is connected to the initialization line INT1 (initialization signal line INT11 ) through a via V7 , and the other end of the connection electrode CEe is connected to the first electrode T2 a of the reset transistor T2 through a via V8 .

[0178] 5 to 8E , one end of the connecting electrode CEf is connected to the first end C1 (the first electrode Ca, the gate of the driving transistor T3) through a via V3, and the other end of the connecting electrode CEf is connected to the first electrode T1b of the data writing transistor T1 (that is, the second electrode T2b of the reset transistor T2) through a via V5.

[0179] 5 to 8E , the third electrode plate Cc of the second end C2 is connected to the second electrode plate Cb of the second end C2 (ie, the first electrode T3 a of the driving transistor T3 ) through a via V2 .

[0180] 5 to 8E , the reset signal transmission line INI is connected to the first electrode T3 a of the driving transistor T3 through the via V1 , and the reset signal transmission line INI is connected to the second electrode T5 b of the emission control transistor T5 through the via V13 .

[0181] 5 to 8E , the second electrode T5 b of the light emitting control transistor T5 is connected to the second electrode T3 b of the driving transistor T3 through the reset signal transmission line INI.

[0182] As shown in FIG7A , the first plate-shaped portion Cba and the second plate-shaped portion Cbb may also be connected to the channel T3c of the driving transistor T3, and the first plate-shaped portion Cba, the second plate-shaped portion Cbb, and the channel T3c of the driving transistor T3 are located on the same layer. For example, the first plate-shaped portion Cba, the second plate-shaped portion Cbb, and the channel T3c of the driving transistor T3 may form an integrated structure.

[0183] The display substrate provided by the embodiment of the present disclosure optimizes the balance between luminous uniformity and power consumption by matching the pattern design of the active layer LY0 with the pattern design of the channel of the driving transistor and the capacitor plate located in the active layer, thereby improving the luminous uniformity of the display substrate and reducing power consumption.

[0184] As shown in FIG7A , the first plate-shaped portion Cba includes a first portion PR1 and a second portion PR2. The first portion PR1 extends along a first direction Y, and the second portion PR2 extends along a second direction X. The first portion PR1 and the second plate-shaped portion Cbb are disposed opposite each other and are disposed on either side of the channel T3c of the driving transistor T3 in the second direction X. FIG7A demarcates the first portion PR1, the second portion PR2, and the second plate-shaped portion Cbb with dotted lines.

[0185] For example, referring to Figures 5, 7A, 8B, and 8E, the second electrode plate Cb and the channel of the driving transistor T3 are an integrated structure and can be formed from the same thin film through the same patterning process. The channel of the driving transistor T3 is a semiconductor material, and the second electrode plate Cb is a conductor obtained by doping the semiconductor material.

[0186] 8B shows the channel T1 c of the data writing transistor T1 , the channel T2 c of the reset transistor T2 , the channel T3 c of the driving transistor T3 , and the channel T5 c of the light emission control transistor T5 .

[0187] Figure 9 is a layout diagram of a display substrate provided in one embodiment of the present disclosure. Figure 10 is a layout diagram of a display substrate provided in another embodiment of the present disclosure. Figure 11 is a layout diagram of a display substrate provided in another embodiment of the present disclosure.

[0188] Figure 9 shows two sub-pixels 100: a first sub-pixel 101 and a second sub-pixel 102. As shown in Figure 9, the first sub-pixel 101 and the second sub-pixel 102 are adjacent and arranged sequentially along the second direction X. As shown in Figure 9, the layout of the pixel circuit of the first sub-pixel 101 and the layout of the pixel circuit of the second sub-pixel 102 are designed to be mirror images. As shown in Figure 9, the pixel circuit of the first sub-pixel 101 and the pixel circuit of the second sub-pixel 102 are axially symmetrical with respect to a line extending along the first direction Y.

[0189] As shown in Figure 9, the pixel opening P0 (pixel opening P01) of the first sub-pixel 101 and the pixel opening P0 (pixel opening P02) of the second sub-pixel 102 both overlap with the first power line PL1 (first power connection line PL12). That is, the orthographic projection of the pixel opening P01 on the substrate overlaps with the orthographic projection of the first power line PL1 (first power connection line PL12), and the orthographic projection of the pixel opening P02 on the substrate overlaps with the orthographic projection of the first power line PL1 (first power connection line PL12). The portion of the first power line PL1 (first power connection line PL12) directly below the opening P0 can serve as a leveling pad, further improving the flatness of the light-emitting layer and reducing color shift, for example, from left to right viewing angles, further enhancing display quality. Specifically, the central axis of the third plate Cc of the storage capacitor in the first direction Y is brought closer to the central axis C0 of the pixel opening P0, which extends along the first direction Y. Signal lines are used to level the positions of the pixel opening P0 on both sides of the third plate Cc. Of course, the adjacent sub-pixels in FIG9 are not limited to the first sub-pixel 101 and the second sub-pixel 102, and may also be in other forms, for example, the second sub-pixel 102 and the third sub-pixel 103 may be adjacent, or the first sub-pixel 101 and the third sub-pixel 103 may be adjacent. In FIG9 , both adjacent sub-pixels overlap with the first power connection line PL12, and embodiments of the present disclosure include but are not limited to this. For example, in some embodiments, one of the two adjacent sub-pixels may overlap with the first power connection line PL12, while the other of the two adjacent sub-pixels may not overlap with the first power connection line PL12.

[0190] As shown in Figure 10, the third electrode plate Cc and the first power connection line PL12 are located on either side of the central axis C0. The first power line PL1 (first power connection line PL12) in the display substrate shown in Figure 10 accounts for a larger portion of the width of the pixel opening (the second direction X). That is, the first power connection line PL12 has a larger padding dimension in the width direction of the pixel opening. This allows the third electrode plate Cc and the first power connection line PL12, which are located on either side of the central axis C0, to jointly level the pixel opening, thereby improving the flatness of the light-emitting layer and reducing color shift, such as color shift between left and right viewing angles, to further enhance display quality. Figure 10 shows that the third sub-pixel 103 and the first sub-pixel 101 are adjacent and arranged sequentially along the second direction X.

[0191] As shown in FIG10 , the maximum dimension W0 of the pixel opening P03 of the third sub-pixel 103 along the second direction X is different from the maximum dimension W0 of the pixel opening P01 of the first sub-pixel 101 along the second direction X. Accordingly, the overlapping area between the first power connection line PL12 and the pixel opening P03 of the third sub-pixel 103 is different from the overlapping area between the first power connection line PL12 and the pixel opening P01 of the first sub-pixel 101. For example, the ratio of the overlapping area between the first power connection line PL12 and the pixel opening P03 of the third sub-pixel 103 to the area of ​​the pixel opening P03 of the third sub-pixel 103 is equal to or substantially equal to the ratio of the overlapping area between the first power connection line PL12 and the pixel opening P01 of the first sub-pixel 101 to the area of ​​the pixel opening P01 of the first sub-pixel 101.

[0192] As shown in FIG10 , the maximum dimension W0 of the pixel opening P03 of the third sub-pixel 103 along the second direction X is larger than the maximum dimension W0 of the pixel opening P01 of the first sub-pixel 101 along the second direction X. Accordingly, the overlapping area between the first power connection line PL12 and the pixel opening P03 of the third sub-pixel 103 is larger than the overlapping area between the first power connection line PL12 and the pixel opening P01 of the first sub-pixel 101.

[0193] As shown in FIG. 10 , the overlap between the first power connection line PL12 and the pixel opening P03 of the third sub-pixel 103 in the second direction X is greater than the overlap between the first power connection line PL12 and the pixel opening P01 of the first sub-pixel 101 in the second direction X.

[0194] 10 shows a maximum size W03 of the pixel opening P03 of the third sub-pixel 103 along the second direction X and a maximum size W01 of the pixel opening P01 of the first sub-pixel 101 along the second direction X. FIG.

[0195] FIG11 shows that one of the pixel openings P0 of two adjacent sub-pixels 100 overlaps with the first power connection line PL12, while the other of the pixel openings P0 of the two adjacent sub-pixels 100 does not overlap with the first power connection line PL12. In other words, the first power connection line PL12 acts as a leveling agent for one of the adjacent sub-pixels. For example, the first power connection line PL12 acts as a leveling agent for at least one of the adjacent sub-pixels.

[0196] With reference to Figures 3 to 11, embodiments of the present disclosure provide a display substrate comprising a base substrate BS and a plurality of sub-pixels 100 disposed on the base substrate BS. Each sub-pixel 100 includes a pixel circuit 100a and a light-emitting element 100b. The pixel circuit 100a includes a driving transistor T3 and a storage capacitor Cst. The storage capacitor Cst includes a first plate Ca and a second plate Cb. The first plate Ca of the storage capacitor Cst is connected to the gate T3g of the driving transistor T3, and the second plate Cb of the storage capacitor Cst is connected to the first electrode T3a of the driving transistor T3. The light-emitting element 100b is electrically connected to the pixel circuit 100a. The pixel circuit 100a is configured to drive the light-emitting element 100b. The sub-pixel 100 includes a pixel opening P0, which is configured to define the light-emitting area of ​​the sub-pixel 100.

[0197] As shown in FIG. 5 , the orthographic projection of the storage capacitor Cst on the base substrate BS overlaps with the orthographic projection of the pixel opening P0 on the base substrate BS.

[0198] Referring to Figures 5, 8E, 8F, and 9 to 11, the orthographic projection of the channel T3c of the driving transistor T3 on the base substrate BS overlaps with the orthographic projection of the pixel opening P0 on the base substrate BS. In Figures 8E and 8F, the portion of the active layer LY0 at the dashed cross is a semiconductor, such as polysilicon, while the remaining portion is a conductor, such as doped polysilicon. In embodiments of the present disclosure, a semiconductor can be converted into a conductor through a doping process. For example, the doping process can be performed before forming the first conductive pattern layer LY1, but is not limited thereto.

[0199] As shown in Figures 5, 6, 7A, 7B, 8A, 8B, 8E, and 9 to 11, the second electrode plate Cb is arranged in the same layer as the channel T3c of the driving transistor T3 (as shown in Figures 7A and 8E), the second electrode plate Cb is closer to the base substrate BS than the first electrode plate Ca, and the orthographic projection of the second electrode plate Cb on the base substrate BS overlaps with the orthographic projection of the pixel opening P0 on the base substrate BS.

[0200] For example, the display substrate satisfies the following relationship: the value range of (W*L+S2)*M1 / M2 is [0.014, 0.133], and the value range of S2 / (W*L) is [2.82, 28.85].

[0201] As shown in Figures 7A, 8E, and 8F, W is the width of the channel T3c of the driving transistor T3, L is the length of the channel T3c of the driving transistor T3, and as shown in Figures 5, 6, 9 to 11, S2 is the area of ​​the second electrode plate Cb and the first electrode plate Ca facing each other, M1 is the number of pixel openings P0 of the display substrate, and M2 is the area of ​​the display substrate. For example, M2 is the total area of ​​the display substrate in a plan view. For example, M2 is the sum of the area of ​​the display area R01 and the area of ​​the peripheral area R02.

[0202] The display substrate provided by the embodiment of the present disclosure maximizes the utilization of the area where the storage capacitor is located. The larger the area of ​​the pixel opening, the larger the proportion of the area where the storage capacitor is located. Correspondingly, the smaller the area of ​​the pixel opening, the smaller the proportion of the area where the storage capacitor is located. A high-resolution display substrate needs to maximize the utilization of the area where the storage capacitor is located. A display substrate that meets the above-mentioned value range, that is, a display substrate that meets the value range of (W*L+S2)*M1 / M2 of [0.014, 0.133] and the value range of S2 / (W*L) of [2.82, 28.85], can increase the facing area of ​​the storage capacitor's plate, increase the capacitance, improve the retention capacity of the capacitor, and is conducive to improving the ratio of the storage capacitor to the area of ​​the pixel opening, increasing the area proportion of the storage capacitor, and improving the display quality.

[0203] Of course, in other embodiments, the value range of S2 / (W*L) may not be limited, and the value range of (W*L+S2)*M1 / M2 can be satisfied to be [0.014, 0.133]. In this case, the facing area of ​​the storage capacitor's plate can be increased, the capacitance can be increased, the retention capacity of the capacitor can be improved, and it is beneficial to increase the ratio of the storage capacitor to the area of ​​the pixel opening, increase the area ratio of the storage capacitor, and improve the display quality.

[0204] For example, the value range of (W*L+S2)*M1 / M2 can be [0.02, 0.1].

[0205] For further example, the value range of (W*L+S2)*M1 / M2 may be [0.02, 0.05].

[0206] For further example, the value range of (W*L+S2)*M1 / M2 may be [0.03, 0.05].

[0207] For example, the value range of S2 / (W*L) can be [5, 28].

[0208] For example, the value range of S2 / (W*L) may be [6, 27.5].

[0209] For example, the value range of S2 / (W*L) may be [7, 27.5].

[0210] For example, in some embodiments, the display substrate may be a 27-inch product, W = 1.5-4 microns, for example, W may be 2.5 microns, 2.6 microns, or 2.7 microns; L = 10-20 microns, for example, L may be 13 microns, 14 microns, or 15 microns; M1 is the number of pixel openings (multiplied by the resolution, 4K): 3840*2160=8294400; for example, M2 ranges from 1900 square centimeters to 2100 square centimeters, for example, M2 = 59.8*33.6 = 2009.28 square centimeters; for example, S2 = 900-1200 square microns; for example, S2 may be 1020 square microns, 1030 square microns, or 1040 square microns.

[0211] For example, for a 27-inch product, W = 2.5 microns, L = 15 microns, M1 = 8,294,400, M2 = 2,009.28 square centimeters, and S2 = 1,030 square microns. (W*L+S2)*M1 / M2 is 0.04, and S2 / (W*L) is 27.4. When calculating, use the same units, for example, converting square centimeters to square microns.

[0212] For example, in some embodiments, the display substrate may be a 65-inch product, W = 1.5-4 microns, for example, W may be 2.5 microns, 2.6 microns, or 2.7 microns; L = 20-30 microns, for example, L may be 23 microns, 24 microns, or 25 microns; M1 is the number of pixel openings (multiplied by the resolution, 8K): 7680*4320=33177600, M2 ranges from 11600-11700 square centimeters, for example, M2 = 143.9*80.94=11647.27 square centimeters; for example, S2 = 900-1200 square microns, for example, it may be 1020 square microns, 1030 square microns, or 1040 square microns.

[0213] For example, for a 65-inch product, W = 2.7 microns; L = 25 microns; M1 = 7680*4320 = 33177600, M2 = 143.9*80.94 = 11647.27 square centimeters; S2 = 1200 square microns, the value of (W*L+S2)*M1 / M2 is 0.036, and the value of S2 / (W*L) is 17.7.

[0214] For example, in some embodiments, the display substrate may be a 75-inch product, for example, W = 1.5-4 microns, for example, W may be 2.5 microns, 2.6 microns, or 2.7 microns; for example, L = 35-45 microns, for example, L may be 39 microns, 40 microns, or 41 microns; M1 is the number of pixel openings (multiplied by the resolution, 8K) = 7680*4320 = 33177600; for example, M2 ranges from 14400 to 14500 square centimeters, for example, M2 = 154.96*93.38 = 14470.16 square centimeters; S2 = 900-1200 square microns, for example, S2 may be 1020 square microns, 1030 square microns, or 1040 square microns.

[0215] For example, for a 75-inch product, W = 4 microns, L = 39 microns, M1 = 33,177,600; M2 = 154.96*93.38 = 14,470.16 square centimeters; S2 = 1,200 square microns, the value of (W*L+S2)*M1 / M2 is 0.031, and the value of S2 / (W*L) is 7.69.

[0216] For example, referring to Figures 5, 6, 7D, 8A and 8D, and 9 to 11, the storage capacitor Cst further includes a third plate Cc, the third plate Cc and the second plate Cb are connected to each other, and the third plate Cc and the second plate Cb are respectively arranged on both sides of the first plate Ca. The provision of the second plate Cb below the first plate Ca and the third plate Cc above the first plate Ca is beneficial for increasing the capacitance of the storage capacitor and improving display quality. Of course, the provision of the third plate Cc can comprehensively consider the leveling design, capacitance, the position of the first plate Ca, and the position of the second plate Cb.

[0217] Figure 12 is a layout diagram of a display substrate provided by another embodiment of the present disclosure. Compared with the display substrate shown in Figure 5 , in the display substrate shown in Figure 12 , the connection electrode CEb is located in the active layer LY0 and is integrated with the first electrode T5a of the light emitting control transistor T5 .

[0218] Figure 13 is a layout diagram of a display substrate provided by another embodiment of the present disclosure. Compared with the display substrate shown in Figure 5 , in the display substrate shown in Figure 13 , the second electrode T5b of the light-emitting control transistor T5 is directly connected to the second electrode T3b of the driving transistor T3.

[0219] Figure 14 is a layout diagram of a display substrate provided in another embodiment of the present disclosure. Figure 15 is a stackup diagram of a portion of the film layers in Figure 14. As shown in Figures 14 and 15, the second electrode Cb includes a first plate-shaped portion Cba, which is integrally formed with the channel of the driving transistor T3.

[0220] For example, as shown in Figures 14 and 15 , the second plate Cb further includes a second plate-shaped portion Cbb. The first plate-shaped portion Cba and the second plate-shaped portion Cbb are separated from each other, and the area of ​​the first plate-shaped portion Cba is larger than that of the second plate-shaped portion Cbb. As shown in Figures 14 and 15 , the second plate-shaped portion Cbb and the first plate-shaped portion Cba are located on the same layer and spaced apart. The first plate-shaped portion Cba, the second plate-shaped portion Cbb, and the channel of the driving transistor T3 are located on the same layer and are all located in the active layer LY0.

[0221] As shown in FIG. 14 and FIG. 15 , the second plate-shaped portion Cbb is connected to the third electrode plate Cc through a via V22 .

[0222] As shown in FIG15 , the first plate-shaped portion Cba includes a first portion PR1 and a second portion PR2. The first portion PR1 extends along a first direction Y, and the second portion PR2 extends along a second direction X. The first portion PR1 and the second plate-shaped portion Cbb are disposed opposite each other and are disposed on either side of the channel T3c of the driving transistor T3 in the second direction X. For example, as shown in FIG15 , the first portion PR1 and the second portion PR2 form a 7-shaped portion. FIG15 is demarcated by a dotted line between the first portion PR1 and the second portion PR2.

[0223] Figure 16 is a layout diagram of a display substrate provided in another embodiment of the present disclosure. Figure 17 is a stackup diagram of a portion of the film layers in Figure 16. As shown in Figures 16 and 17, the driving transistor T3 adopts a dual-gate structure. Figure 17 shows the channel T3c1 and channel T3c2 of the driving transistor T3.

[0224] For example, the channel of the driving transistor T3 is made of a semiconductor material, and the material of the second electrode Cb is a conductor obtained by doping the same semiconductor material as the channel of the driving transistor T3 .

[0225] 5 , 9 to 14 , and 16 , the pixel opening P0 has a central axis C0 extending along the first direction Y. The pixel opening P0 is axisymmetric with respect to the central axis C0 .

[0226] 9 to 11 , the pixel openings P0 of the sub-pixels 100 include a pixel opening P01 of the first sub-pixel 101 , a pixel opening P02 of the second sub-pixel 102 , and a pixel opening P03 of the third sub-pixel 103 .

[0227] 9 to 11 , the central axis C0 includes the central axis C01 of the pixel opening P0 (pixel opening P01) of the first sub-pixel 101, the central axis C02 of the pixel opening P0 (pixel opening P02) of the second sub-pixel 102, and the central axis C03 of the pixel opening P0 (pixel opening P03) of the third sub-pixel 103.

[0228] Figure 18 is a stacking diagram of some film layers of a display substrate provided by an embodiment of the present disclosure. For example, as shown in Figure 18, the channel of the driving transistor T3 extends along the first direction Y, the pixel opening P0 has a central axis C0 extending along the first direction Y, the maximum dimension of the pixel opening P0 along the second direction X (the width of the pixel opening P0) is W0, the first direction Y intersects with the second direction X, the distance from the channel T3c of the driving transistor T3 to the central axis C0 is D1, and the value range of 2*D1 / W0 is [0.2, 0.4] or [0.6, 0.8]. The larger the value of D1, the smaller the proportion of the driving transistor T3 and the larger the area of ​​the storage capacitor. The ratio of 2*D1 / W0 is within the above-mentioned value range to limit the position of the channel or gate of the driving transistor, which is conducive to improving the retention capacity of the storage capacitor, and is conducive to improving the ratio of the area of ​​the storage capacitor to the pixel opening, increasing the area proportion of the storage capacitor, and improving the display quality.

[0229] For example, for a blue sub-pixel, W0 = 50 micrometers, D1 = 15.3 micrometers, and the value of 2*D1 / W0 is 0.6.

[0230] For example, for a green sub-pixel, W0 = 28 micrometers, D1 = 3.25 micrometers, and the value of 2*D1 / W0 is 0.2.

[0231] For example, for a red sub-pixel, W0 = 28 micrometers, D1 = 2.55 micrometers, and the value of 2*D1 / W0 is 0.2.

[0232] The above examples show that the values ​​of W0 and D0 can be determined as needed, as long as the value range of 2*D1 / W0 is [0.2, 0.4] or [0.6, 0.8]. For blue sub-pixels, the value range of 2*D1 / W0 is [0.6, 0.8], and for green sub-pixels and / or red sub-pixels, the value range of 2*D1 / W0 is [0.2, 0.4].

[0233] FIG19 is a stacking diagram of a portion of the film layers of a display surface substrate provided by an embodiment of the present disclosure. For example, as shown in FIG19 , the display substrate further includes a plurality of signal lines SGL located on one side of the storage capacitor Cst, the signal lines SGL extending along the second direction X, the orthographic projections of the plurality of signal lines SGL on the base substrate BS overlap with the orthographic projections of the pixel opening P0 on the base substrate BS, the size of the pixel opening P0 along the first direction Y (the height of the pixel opening P0) is H0, the distance between the farthest edges of the plurality of signal lines SGL in the first direction Y is Hs, and the value range of L / (H0-Hs) is [0.59, 1.19]. The smaller the value of the length L of the channel T3c, the larger the area of ​​the storage capacitor. The value of L / (H0-Hs) is within the above-mentioned value range to limit the position of the channel or gate of the driving transistor, which is conducive to obtaining a storage capacitor with a larger capacitance.

[0234] In some embodiments, the value of L is about 10-30 μm, the value of H0 is about 50-75 μm, and the value of Hs is about 10-25 μm, but is not limited thereto.

[0235] For example, L=30 μm, H0=75 μm, Hs=25 μm, and the value of L / (H0-Hs) is 0.6.

[0236] For example, as shown in FIG19 , the display substrate further includes a data line DT, a gate line G1, a gate line G2, and an initialization line INT1, and the pixel circuit 100 a further includes a data write transistor T1 and a reset transistor T2. The first electrode of the data write transistor T1 is connected to the data line DT, the gate of the drive transistor T3 is connected to the second electrode of the data write transistor T1, the gate of the data write transistor T1 is connected to the gate line G1, the first electrode of the reset transistor T2 is connected to the initialization line INT1, the second electrode of the reset transistor T2 is connected to the gate of the drive transistor T3, the gate of the reset transistor T2 is connected to the gate line G2, and the multiple signal lines SGL include the gate line G1, the gate line G2, and the initialization line INT1. Of course, in other embodiments, the multiple signal lines SGL may also include at least one of the gate line G1, the gate line G2, and the initialization line INT1, or include other signal lines that overlap with the pixel opening P0.

[0237] For example, the area of ​​the pixel opening P0 is S0, the sum of the area of ​​the second electrode plate Cb and the first electrode plate Ca facing each other, and the area of ​​the channel T3c of the driving transistor T3 is Ss. The relationship between Ss and S0 satisfies: Ss = A*S0 + B, where the value range of A is [0.42, 0.82], and the value range of B is [-2700, -3100]. Using the above formula, the design area of ​​the pixel opening, storage capacitor, and driving transistor is matched, which helps to improve the ratio of the storage capacitor area to the pixel opening, increase the area ratio of the storage capacitor, and improve display quality.

[0238] For example, in some embodiments, Ss=179, S0=4524, and the units of area S0 and area Ss are both square micrometers. In this case, A=0.686, and B=-2924.

[0239] For example, in some embodiments, Ss=2440, S0=7820, and the units of area S0 and area Ss are both square micrometers. In this case, A=0.686, and B=-2924.

[0240] For example, in some embodiments, Ss=370, S0=4802, and the units of area S0 and area Ss are both square micrometers. In this case, A=0.686, and B=-2924.

[0241] For example, in some embodiments, Ss=3219, S0=8955, and the units of area S0 and area Ss are both square micrometers. In this case, A=0.686, and B=-2924.

[0242] Figure 20 is a partial stackup diagram of a display substrate provided by an embodiment of the present disclosure. For example, as shown in Figures 5, 9 to 11, and 20, the orthographic projection of the pixel opening P0 on the base substrate BS overlaps with the orthographic projection of the third plate Cc on the base substrate BS.

[0243] For example, as shown in FIG. 20 , the third plate Cc includes a first edge CL1 extending along the first direction Y and a second edge CL2 extending along the first direction Y, and the pixel opening P0 includes a first edge KL1 extending along the first direction Y and a second edge KL2 extending along the first direction Y.

[0244] For example, as shown in FIG20 , the first edge CL1 of the third plate Cc is closer to the first edge KL1 of the pixel opening P0 than the second edge CL2 of the third plate Cc, and the second edge CL2 of the third plate Cc is closer to the second edge KL2 of the pixel opening P0 than the first edge CL2 of the third plate Cc. The sub-pixel 100 satisfies the following formula:

[0245] △U=|U02-U01|,

[0246] U01 is the coordinate distance between the chromaticity coordinate point at the first viewing angle and the chromaticity coordinate point at the viewing angle of 0 degrees, U02 is the coordinate distance between the chromaticity coordinate point at the second viewing angle and the chromaticity coordinate point at the viewing angle of 0 degrees, △U is the absolute value of the difference between U02 and U01, the chromaticity coordinate point at the viewing angle of 0 degrees is the chromaticity coordinate point at the normal line where the center of the display substrate is located, the first viewing angle and the second viewing angle are located on opposite sides of the normal line and have the same angle with the normal line, and △U ≤ 0.0020.

[0247] For example, as shown in FIG20 , the sub-pixel 100 satisfies the following formula:

[0248] △U=|U02-U01|≤k×|Xb-Xa| / KW,

[0249] Wherein, k is the color shift influence coefficient, 0.009≤k≤0.03, ΔU<0.0020, Xa is the minimum distance between the first edge CL1 of the third plate Cc and the first edge KL1 of the pixel opening P0 in the second direction X, Xb is the minimum distance between the second edge CL2 of the third plate Cc and the second edge KL2 of the pixel opening P0 in the second direction X, and the first direction Y and the second direction X intersect; KW is the maximum dimension of the pixel opening P0 in the second direction X, U01 is the coordinate distance between the chromaticity coordinate point at the first viewing angle and the chromaticity coordinate point at the viewing angle of 0 degrees, U02 is the coordinate distance between the chromaticity coordinate point at the second viewing angle and the chromaticity coordinate point at the viewing angle of 0 degrees, ΔU is the absolute value of the difference between U02 and U01, the chromaticity coordinate point at the viewing angle of 0 degrees is the chromaticity coordinate point at the normal line where the center of the display substrate is located, and the first viewing angle and the second viewing angle are respectively located on opposite sides of the normal line and have equal angles with the normal line.

[0250] The size of KW is the maximum size W0 of the pixel opening P0 along the second direction X (the width of the pixel opening P0 ).

[0251] 20 , the third plate Cc further includes a third edge CL3 extending along the second direction X and a fourth edge CL4 extending along the second direction X. The pixel opening P0 includes a third edge KL3 extending along the second direction X and a fourth edge KL4 extending along the second direction X.

[0252] As shown in FIG. 20 , the orthographic projection of the third edge CL3 on the base substrate is located outside the orthographic projection of the pixel opening P0 on the base substrate.

[0253] As shown in FIG. 20 , the orthographic projection of the fourth edge CL4 on the base substrate is located within the orthographic projection of the pixel opening P0 on the base substrate.

[0254] As shown in Figure 20, the first edge CL1 and the second edge CL2 are arranged opposite each other, and the third edge CL3 is connected to the first edge CL1 and the second edge CL2 via rounded corners. The third edge CL3 and the fourth edge CL4 are arranged opposite each other, and the fourth edge CL4 is connected to the first edge CL1 and the second edge CL2 via rounded corners. Of course, in other embodiments, adjacent edges of the opening may not be connected by rounded corners.

[0255] Figure 21 is a schematic diagram of a central pixel of a display substrate provided by an embodiment of the present disclosure. Figure 22 is a cross-sectional view along line B1-B2 of Figure 21. Figure 23 is a schematic diagram of the coordinate distance of chromaticity coordinate points at two different viewing angles of the display substrate.

[0256] 21 shows a central pixel PXc. For example, the central pixel PXc is a pixel PX located at the central point of the display area R01.

[0257] For example, a non-contact spectrometer (such as the PR630, 730; CS2000, 2000A) can be used to perform spot checks (selecting at least 10 panels and selecting the worst result) on the display substrates (display panels) to be tested in a darkroom (illuminance below 1lx). The test point is the center pixel of the display substrate. The u' and v' coordinates of this point in the 1976UV chromaticity coordinate system for the four colors RBGW are read. Measurements are performed at nine viewing angles: 0 degrees, ±15 degrees, ±30 degrees, ±45 degrees, and ±60 degrees. The u' and v' values ​​at each angle are measured. For example, color shift at a viewing angle of -60 degrees is used.

[0258]

[0259] u2' and v2' are the chromaticity coordinates at a viewing angle of -60 degrees. u1' and v1' are the chromaticity coordinates at a viewing angle of 0 degrees.

[0260] Substituting this into the formula yields Δu'v' at -60 degrees; similarly, Δu'v' at 60 degrees is calculated. By optimizing the display substrate structure, the difference between the two values ​​for the four colors (RGBW) can be reduced to less than 0.0015, and the Δu'v' value at each angle is less than 0.025. The first subpixel 101 is a red subpixel, the second subpixel 102 is a green subpixel, and the third subpixel 103 is a blue subpixel. When measuring the color shift of white light, the first, second, and third subpixels 101, 102, and 103 in the center pixel PXc are all illuminated.

[0261] The uniform color space CIE1976 is converted from CIE1931XYZ.

[0262] The calculation formula of CIE1976Luv includes:

[0263]

[0264] Where u' and v' are the chromaticity coordinates of the color sample, and X, Y, and Z are the tristimulus values ​​of the sample.

[0265] It should be noted that the color shift measurement method is not limited to the above description, and the measuring instruments used are not limited to the examples listed. The same measuring instrument can be used to measure chromaticity coordinates at different viewing angles to obtain the coordinate distance between the chromaticity coordinate point at each viewing angle and the chromaticity coordinate point at a viewing angle of 0 degrees.

[0266] The embodiment of the present disclosure is described by taking the measurement of the color deviation of the central pixel PXc as an example. Of course, the color deviation of each sub-pixel in other suitable pixels may also be measured.

[0267] Figure 23 shows the coordinate distance between chromaticity coordinate point P2 and chromaticity coordinate point P1. As shown in Figure 23, x0 is the coordinate distance between the horizontal coordinates of chromaticity coordinate point P2 and chromaticity coordinate point P1, y0 is the coordinate distance between the vertical coordinates of chromaticity coordinate point P2 and chromaticity coordinate point P1, and z0 is the coordinate distance between the chromaticity coordinate point P2 and chromaticity coordinate point P1.

[0268] For example, the coordinate distance between chromaticity coordinate points at two viewing angles refers to the square root of the sum of the squares of the difference between the abscissas and the squares of the difference between the ordinates of the two chromaticity coordinate points.

[0269] Figure 22 shows the normal line L0, which is located at the center of the display substrate. Normal line L0 is parallel to the third direction Z. Figure 22 also shows a first viewing angle VW1 and a second viewing angle VW2. The angle between the first viewing angle VW1 and the normal line L0 is +θ, and the angle between the second viewing angle VW2 and the normal line L0 is -θ. At a positive viewing angle θ, the angle from the normal line L0 to this viewing angle is a clockwise rotation of θ. At a negative viewing angle -θ, the angle from the normal line L0 to this viewing angle is a counterclockwise rotation of θ.

[0270] The situations shown in FIG. 21 and FIG. 22 are used to measure the color shift of the left and right viewing angles. When measuring the color shift of the top and bottom viewing angles, the first viewing angles VW1 and VW2 are set on both sides of the normal line L0 in the first direction Y.

[0271] Figure 24 is a layout diagram of a display substrate provided in one embodiment of the present disclosure. Figure 24 shows a first sub-pixel 101, a second sub-pixel 102, and a third sub-pixel 103. As shown in Figure 24, the first sub-pixel 101, the second sub-pixel 102, and the third sub-pixel 103 are arranged sequentially along the second direction X.

[0272] As shown in FIG24 , the initialization line INT1 includes an initialization signal line INT11 and an initialization connection line INT12, and the initialization signal line INT11 and the initialization connection line INT12 are connected. As shown in FIG24 , the initialization signal line INT11 and the initialization connection line INT12 are connected by a via Vj. As shown in FIG24 , the initialization signal line INT11 extends along the second direction X, and the initialization connection line INT12 extends along the first direction Y.

[0273] As shown in FIG. 24 , the initialization connection lines INT12 and the first power connection lines PL12 are alternately arranged in the second direction X at corresponding positions.

[0274] As shown in FIG. 24 , the first portion INTa and the second portion INTb of the initialization connection line INT12 are connected through a via Vg, and the second portion INTb and the third portion INTc of the initialization connection line INT12 are connected through a via Vh.

[0275] As shown in FIG24 , the initialization connection line INT12 passes through the first sub-pixel 101, and two adjacent first power connection lines PL1 pass through the second sub-pixel 102 and the third sub-pixel 103, respectively. That is, the initialization connection line INT12, one first power connection line PL12, and another first power connection line PL12 are sequentially arranged along the second direction X. The initialization connection line INT12 extends along the first direction Y, and the first power connection line PL12 extends along the first direction Y.

[0276] FIG25 is a plan view of a display substrate provided by an embodiment of the present disclosure. For example, the sub-pixel 100 shown in FIG25 is the third sub-pixel 103, and the third sub-pixel 103 is a blue sub-pixel.

[0277] For example, as shown in Figures 5 and 25, the display substrate also includes a first power line PL1, which is configured to provide a first voltage signal to the pixel circuit 100a. The first power line PL1 includes a first power connection line PL12 extending along the first direction Y and a first power signal line PL11 extending along the second direction X. The orthographic projection of the first power connection line PL12 on the base substrate BS overlaps with the orthographic projection of the pixel opening P0 on the base substrate BS.

[0278] As shown in Figures 5 and 25 , the first power connection line PL12 is formed by connecting multiple conductive portions located in two conductive pattern layers. The embodiments of the present disclosure include but are not limited to this. In other embodiments, the first power connection line PL12 may also be formed by connecting multiple conductive portions located in three or more conductive pattern layers.

[0279] For example, referring to Figures 5 and 25 , the area of ​​the third plate Cc is Sc1, the overlapping area of ​​the orthographic projection of the third plate Cc on the base substrate BS and the orthographic projection of the pixel opening P0 on the base substrate BS is Sc2, and Sc2 / Sc1 ≥ 0.9. The third plate Cc can act as a leveling pad, flattening the bottom surface of the pixel opening P0 of the sub-pixel 100 and improving the flatness of the light-emitting layer to enhance display quality. For example, the sub-pixel that satisfies Sc2 / Sc1 ≥ 0.9 can be a blue sub-pixel. This padding improves the flatness of the blue sub-pixel's light-emitting layer and enhances display quality. For a further example, to further enhance the leveling effect, Sc2 / Sc1 ≥ 0.95.

[0280] For example, referring to FIG5 and FIG25 , the width of the first power connection line PL12 is W1, and the overlap width between the first power connection line PL12 and the pixel opening P0 is W2. W2 / W1 ≥ 0.9, so that the first power connection line PL12 can better level the pixel opening P0 of the sub-pixel 100, thereby improving the flatness of the light-emitting layer. For another example, to further achieve a better leveling effect, W2 / W1 ≥ 0.95.

[0281] In the embodiments of the present disclosure, the line width refers to the dimension of the line perpendicular to the extending direction of the line.

[0282] For example, as shown in FIG25 , the maximum size of the pixel opening P0 along the second direction X is W0, and the value range of 2×W2 / W0 is [0.71, 0.99] to enhance the leveling effect of the first power connection line PL12 and improve the flatness of the light-emitting layer, and the value range of the cross voltage Uc (V) / size Lg (inch) is [0.32, 0.74] to facilitate improving current uniformity, and the size Lg is the length of the diagonal of the display substrate. For example, the cross voltage Uc is the voltage difference between the first electrode and the second electrode of the light-emitting element. For example, the cross voltage Uc is the difference between the first voltage signal VDD and the second voltage signal VSS. Referring to FIG1 , the largest rectangular box represents the display substrate, and the diagonal of the rectangle is the diagonal of the display substrate, and the unit of the diagonal length is inches.

[0283] For example, in some embodiments, the first voltage signal VDD is 17V, the second voltage signal VSS is 2V, Uc=15V, Lg=27 inches, and the value of cross voltage Uc (V) / size Lg (inch) is 0.55.

[0284] For further example, the value range of 2×W2 / W0 is [0.80, 0.99], and the value range of span voltage Uc (V) / size Lg (inch) is [0.52, 0.74].

[0285] For example, as shown in Figure 25, the pixel opening P0 has a central axis C0 extending along the first direction Y, the minimum distance from the first power connection line PL12 to the central axis C0 is Xd1, and the minimum distance from the third electrode Cc to the central axis C0 is Xd2, and the value range of Xd1 / Xd2 is [0.9, 1.1], so as to facilitate the first power connection line PL12 and the third electrode Cc to level the bottom surface of the pixel opening of the sub-pixel, improve the flatness of the light-emitting layer, and thus enhance the display quality.

[0286] For example, in some embodiments, Xd1 = 1.57 microns, Xd2 = 1.73 microns, and Xd1 / Xd2 = 0.9. For example, in other embodiments, Xd1 = 1.73 microns, Xd2 = 1.57 microns, and Xd1 / Xd2 = 1.1. Xd1 and Xd2 are not limited to the above values ​​and can be determined as needed.

[0287] For example, as shown in FIG25 , the display substrate further includes a plurality of signal lines 80 located on one side of the storage capacitor Cst (the storage capacitor Cst is shown by the third plate Cc in FIG25 ), and the orthographic projections of the plurality of signal lines 80 on the base substrate BS overlap with the orthographic projections of the pixel opening P0 on the base substrate BS. The signal line 80 extends along the second direction X, and the distance between the third plate Cc and the signal line closest to it is Xd3. The line width of the signal line is Xd4, and the value range of Xd3 / Xd4 is [0.9, 1.1], so as to enhance the leveling effect of the signal line 80 and the third plate Cc on the bottom surface of the pixel opening of the sub-pixel, reduce the color deviation in the up and down directions, and improve the consistency of the color deviation in the up and down directions.

[0288] For example, in some embodiments, Xd3 = 3 micrometers, Xd4 = 3 micrometers, and Xd3 / Xd4 = 1. Xd3 and Xd4 are not limited to the above values ​​and can be determined as needed.

[0289] Figure 26 is a plan view of a display substrate provided in accordance with an embodiment of the present disclosure. Figure 26 shows two sub-pixels 100. The first sub-pixel 101 is a red sub-pixel, and the second sub-pixel 102 is a green sub-pixel.

[0290] For example, as shown in FIG26 , the display substrate further includes a first power line PL1 configured to provide a first voltage signal to the pixel circuit 100 a. The first power line PL1 includes a first power connection line PL12 extending along a first direction Y and a first power signal line PL11 extending along a second direction X. The minimum distance between the first power connection line PL12 and the central axis C0 is Xd1, and the minimum distance between the first power connection line PL12 and the third electrode plate Cc is Xd0. DP = |Xd1-Xd0| / 2. The maximum dimension of the pixel opening P0 along the second direction X (the width of the pixel opening P0) is W0. The value range of DP / W0 is [0.01, 0.19]. This facilitates the first power connection line PL12 and the third electrode plate Cc to level the bottom surface of the sub-pixel pixel opening, thereby improving the flatness of the light-emitting layer. For example, a red sub-pixel or a green sub-pixel in the display substrate satisfies the value range of DP / W0 of [0.01, 0.19].

[0291] For example, in some embodiments, Xd1 = 22 microns, Xd0 = 8 microns, DP = 7 microns, W0 = 52 microns, and DP / W0 = 0.13.

[0292] For example, in some embodiments, the display substrate further satisfies at least one of the following conditions: W2 / W1 ≥ 0.9; 2×W2 / W0 has a value range of [0.71, 0.99]; cross voltage Uc (V) / dimension Lg (inch) has a value range of [0.32, 0.74]; Xd1 / Xd2 has a value range of [0.9, 1.1]; Xd3 / Xd4 has a value range of [0.9, 1.1]; and DP / W0 has a value range of [0.01, 0.19], so that the display substrate satisfies ΔU ≤ 0.0020. In other words, by designing at least one of the above dimensions, the color shift of the display substrate is minimized.

[0293] For example, as shown in Figure 26, the display substrate also includes a first signal line 801, the first signal line 801 extends along the first direction Y, the sub-pixel 100 includes a first sub-pixel 101 and a second sub-pixel 102 adjacent to each other in the second direction X, the first signal line 801 is configured to provide a data signal to the pixel circuit 100a of the first sub-pixel 101, the pixel opening P0 of the first sub-pixel 101 and the pixel opening P0 of the second sub-pixel 102 are arranged at intervals, and the first signal line 801 is located between the pixel opening P0 of the first sub-pixel 101 and the pixel opening P0 of the second sub-pixel 102.

[0294] For example, as shown in FIG26 , the minimum distances between the pixel opening P0 of the first sub-pixel 101 and the pixel opening P0 of the second sub-pixel 102 and the first signal line 801 are Xa1 and Xa2, respectively, and the value range of Xa1 / Xa2 is [0.8, 1.2]. The first signal line 801 extends along the first direction Y and is located between the pixel openings P0 of adjacent sub-pixels. The body material of the pixel defining layer is provided directly above the first signal line 801. By limiting the ratio of the minimum distance between adjacent pixel openings and the first signal line 801, voltage drop and color shift are reduced.

[0295] For example, in some embodiments, Xa1 = 12 microns, Xa2 = 12 microns, and Xa1 / Xa2 = 1. Of course, Xa1 and Xa2 can fluctuate based on the above values, as long as the value range of Xa1 / Xa2 is [0.8, 1.2].

[0296] For example, as shown in Figure 26, the display substrate also includes a second signal line 802, which extends along the first direction Y. The first signal line 801 and the second signal line 802 are located on opposite sides of the same third electrode plate Cc, and the orthographic projection of the second signal line 802 on the base substrate BS overlaps with the orthographic projection of the pixel opening P0 of the second sub-pixel 102 on the base substrate BS.

[0297] For example, as shown in FIG26 , the spacing between the third electrode Cc and the second signal line 802 is Xa3, the spacing between the third electrode Cc and the first signal line 801 is Xa4, and the value range of Xa3 / Xa4 is [0.8, 1.2], so as to enhance the leveling effect of the third electrode Cc and the second signal line 802 on the bottom surface of the pixel opening of the second sub-pixel 102, improve the flatness of the light-emitting layer, and reduce color deviation.

[0298] For example, in some embodiments, Xa3 = 8.6 microns, Xa4 = 10 microns, and Xa3 / Xa4 = 0.86. Of course, Xa3 and Xa4 can fluctuate based on the above values, as long as the value range of Xa3 / Xa4 is [0.8, 1.2].

[0299] For example, as shown in Figure 26, the display substrate also includes a third signal line 803, which extends along the first direction Y. The orthographic projection of the third signal line 803 on the base substrate BS overlaps with the orthographic projection of the pixel opening P0 of the first sub-pixel 101 on the base substrate BS. The minimum distance between the third electrode Cc of the first sub-pixel 101 and the third signal line 803 is Xa5, and the minimum distance between the third signal line 803 and the first signal line 801 is Xa6. The value range of Xa5 / Xa6 is [0.8, 1.2], so as to enhance the leveling effect of the third electrode Cc and the third signal line 803 on the bottom surface of the pixel opening of the first sub-pixel 101, improve the flatness of the light-emitting layer, and reduce color deviation.

[0300] For example, in some embodiments, Xa5 = 8.7 microns, Xa6 = 7.3 microns, and Xa5 / Xa6 = 1.2. Of course, Xa5 and Xa6 can fluctuate based on the above values ​​as long as the value range of Xa5 / Xa6 is [0.8, 1.2].

[0301] For example, as shown in FIG26 , the first signal line 801 includes a data line DT, and at least one of the second signal line 802 and the third signal line 803 includes a first power connection line PL12 or an initialization connection line INT12. FIG26 illustrates the example of both the second signal line 802 and the third signal line 803 being the first power connection line PL12. In another embodiment, the second signal line 802 is the first power connection line PL12, and the third signal line 803 is the initialization connection line INT12. As shown in FIG26 , the third signal line 803, the first signal line 801, and the second signal line 802 are arranged sequentially along the second direction X.

[0302] FIG27 is a plan view of a display substrate provided in accordance with an embodiment of the present disclosure. FIG28 is a plan view of a display substrate provided in accordance with an embodiment of the present disclosure. For example, as shown in FIG27 and FIG28 , the display substrate further includes a data line DT and a first power line PL1. The data line DT is configured to provide a data voltage to the pixel circuit 100a. The data line DT extends along a first direction Y. The first power line PL1 is configured to provide a first voltage signal VDD to the pixel circuit 100a. The first power line PL1 includes a first power connection line PL12 extending along the first direction Y and a first power signal line PL11 extending along a second direction X. The sub-pixel 100 includes a sub-pixel 121 and a sub-pixel 122 adjacent to each other in the second direction X. The orthographic projection of the first power connection line PL12 on the substrate overlaps with the orthographic projection of the pixel opening P0 of the sub-pixel 121 on the substrate, and also overlaps with the orthographic projection of the pixel opening P0 of the sub-pixel 122 on the substrate.

[0303] For example, as shown in FIG27 , two data lines DT are provided on either side of the first power supply line PL12. The orthographic projections of the two data lines DT on the substrate overlap with the orthographic projections of the pixel openings P0 of sub-pixel 121 and sub-pixel 122 on the substrate, respectively. FIG27 shows data lines DT1 and DT2, which provide data voltages to sub-pixels 121 and 122, respectively. The orthographic projections of data lines DT1 and DT2 on the substrate overlap with the orthographic projections of the pixel openings P01 and P02 of sub-pixel 121 and sub-pixel 122 on the substrate, respectively. Thus, by widening the first power supply line PL12 and cooperating with the two data lines DT (data lines DT1 and DT2) to level sub-pixels 121 and 122, the flatness of the light-emitting layer is improved, color shift is reduced, and voltage drop issues on medium- and large-sized display substrates are resolved, thereby enhancing brightness uniformity.

[0304] FIG27 illustrates an example in which the orthographic projections of two data lines DT on the substrate overlap with the orthographic projections of the pixel openings P0 of sub-pixel 121 and sub-pixel 122, respectively. However, the embodiments of the present disclosure are not limited thereto. For example, the layout design can be adjusted so that the orthographic projections of the two data lines DT on the substrate BS do not overlap with the orthographic projections of the pixel openings P0 of sub-pixel 121 and sub-pixel 122, respectively. Thus, by widening the first power connection line PL12, the first power connection line PL12, the third electrode plate Cc of sub-pixel 121, and the third electrode plate Cc of sub-pixel 122 cooperate to level sub-pixels 121 and 122, thereby improving the flatness of the light-emitting layer and reducing color shift.

[0305] For example, as shown in FIG28 , the display substrate further includes a first power line PL1, which is configured to provide a first voltage signal VDD to the pixel circuit 100 a. The first power line PL1 includes a first power connection line PL12 extending along a first direction Y and a first power signal line PL11 extending along a second direction X. The orthographic projection of the first power connection line PL12 on the base substrate BS overlaps with the orthographic projection of the pixel opening P0 on the base substrate BS. The maximum size of the pixel opening P0 of the sub-pixel 100 along the second direction X is W0. The sub-pixel 1 00 includes sub-pixels 131 and 132 adjacent to each other in a second direction X. One of the two first power supply lines PL12 has a dimension Xb1 in the second direction X, and the other of the two first power supply lines PL12 has a dimension Xb2 in the second direction X. The value range of (Xb1+Xb2) / W0 is [0.08, 0.48]. This enhances the leveling effect of the first power supply line PL12 on the bottom surfaces of the pixel openings of sub-pixels 131 and 132, thereby improving the flatness of the light-emitting layer and reducing color shift, for example, from left to right viewing angles. FIG28 illustrates a dimension W01 of the pixel opening P0 of sub-pixel 131 and a dimension W02 of the pixel opening P0 of sub-pixel 132 along the second direction X. The dimension W0 of sub-pixel 100 along the second direction X can be either dimension W01 or dimension W02, or an average of the two. For example, one of sub-pixel 131 and sub-pixel 132 may be a red sub-pixel, and the other of sub-pixel 131 and sub-pixel 132 may be a green sub-pixel. The embodiments of the present disclosure are described by taking sub-pixel 131 as a green sub-pixel and sub-pixel 132 as a red sub-pixel as an example.

[0306] For example, in some embodiments, Xb1 = 6 microns, Xb2 = 54 microns, and W0 = 163 microns, and the value of (Xb1 + Xb2) / W0 is 0.37. The values ​​of Xb1, Xb2, and W0 are not limited to the above examples, as long as the value of (Xb1 + Xb2) / W0 is in the range of [0.08, 0.48].

[0307] For example, in some embodiments, the sub-pixels include a red sub-pixel, a green sub-pixel, and a blue sub-pixel. The blue sub-pixel may be as shown in FIG. 25 , and the red sub-pixel and the green sub-pixel may be as shown in FIG. 26 .

[0308] FIG29 is a layout diagram of a display substrate provided in one embodiment of the present disclosure. Compared to the display substrate shown in FIG24 , the initialization connection line INT12 in the display substrate shown in FIG29 is located in the second sub-pixel 102, and the two first power connection lines PL1 are located in the first sub-pixel 101 and the third sub-pixel 103, respectively. That is, one first power connection line PL12, the initialization connection line INT12, and another first power connection line PL12 are sequentially arranged along the second direction X. It should be noted that the arrangement of the initialization connection line INT12 is not limited to that shown in the figure, as long as it can be connected to multiple initialization signal lines INT11 arranged in the first direction Y. Furthermore, the arrangement of the first power connection line PL12 is not limited to that shown in the figure, as long as it can be connected to multiple first power signal lines PL11 arranged in the first direction Y. The arrangement of the initialization connection line INT12 and the first power connection line PL12 can be determined as needed.

[0309] 24 and 29 , the first power connection line PL12 and the initialization connection line INT12 level the sub-pixels. The dimension of the first power connection line PL12 in the second direction X is approximately half the dimension of the pixel opening P0 that overlaps with it in the second direction X. The dimension of the initialization connection line INT12 in the second direction X is smaller than half the dimension of the pixel opening P0 that overlaps with it in the second direction X to accommodate the design of the storage capacitor in the second sub-pixel 102 and provide space for the storage capacitor.

[0310] Figure 30 is a schematic diagram of a display substrate provided by an embodiment of the present disclosure. For example, as shown in Figure 30 , the display substrate further includes a drive circuit CCT. The drive circuit CCT is located on one side of the display substrate. Subpixels 100 (subpixel 151) located away from the drive circuit CCT have a first brightness L1; subpixels 100 (subpixel 152) located closer to the drive circuit CCT have a second brightness L2. The value range of |L1-L2| is [1, 9], with the unit of brightness being nits. The brightness difference between subpixels at different distances from the drive circuit CCT is reduced, for example, to less than or equal to 9 nits. This improves current uniformity across the display substrate, ensuring that voltage drop meets design requirements. Figure 30 shows two drive circuits CCT located on the same side of the display substrate. Subpixels 151 and 152 are at different distances from the drive circuit CCT in the first direction Y. The distance between subpixels 151 and 152 in the second direction X is not limited. The drive circuit CCT can be a driver integrated circuit (IC).

[0311] For example, referring to Figures 28 and 30 , because the display substrate satisfies the (Xb1+Xb2) / W0 value range of [0.08, 0.48], the voltage drop and color shift issues are resolved while also minimizing brightness differences. For example, the value range of |L1-L2| is [1, 9]. That is, some display substrates satisfy the (Xb1+Xb2) / W0 value range of [0.08, 0.48], and the value range of |L1-L2| is [1, 9].

[0312] FIG31 is a schematic diagram of a display substrate provided by an embodiment of the present disclosure. For example, as shown in FIG31 , the display substrate further includes two drive circuits CCT. The two drive circuits CCT (drive circuit CCT1 and drive circuit CCT2) are located on opposite sides of the display region R01 of the display substrate. Subpixels 100 located at the central axis of the display substrate have a third brightness L3, while subpixels 100 located near one of the two drive circuits CCT have a fourth brightness L4. Furthermore, the value range of |L3-L4| is [1, 9], with the unit of brightness being nits. The brightness difference between subpixels at different distances from the drive circuits CCT is reduced, improving the current uniformity of the display substrate and ensuring that the voltage drop meets the design requirements. FIG31 shows a central axis CR extending along the second direction X. As shown in FIG31 , the central axis CR extends in the same direction as the drive circuits CCT. As shown in FIG31 , the central axis CR is located between the two drive circuits CCT. The distances between the sub-pixel 161 and the sub-pixel 162 and one of the two driving circuits CCT in the first direction Y are different, and the distances between the sub-pixel 161 and the sub-pixel 162 and the driving circuit CCT in the second direction X are not limited.

[0313] For example, referring to Figures 28 and 31 , because the display substrate satisfies the (Xb1+Xb2) / W0 value range of [0.08, 0.48], the voltage drop and color shift issues are resolved while also minimizing brightness differences. For example, the value range of |L1-L2| is [1, 9]. That is, some display substrates satisfy the (Xb1+Xb2) / W0 value range of [0.08, 0.48], and the value range of |L1-L2| is [1, 9].

[0314] In some embodiments, the display substrate satisfies the value range of |L1-L2| being [1, 9], and satisfies the value range of |L3-L4| being [1, 9].

[0315] Figure 32 is a schematic diagram of a display substrate provided in one embodiment of the present disclosure. For example, as shown in Figure 32, the display substrate includes a power bus 501, a power bus 502, an initialization bus 503, and an initialization bus 504. For example, the power bus 501 is connected to the first power line PL1, the power bus 502 is connected to the second power line PL2, the initialization bus 503 is connected to the initialization line INT1, and the initialization bus 504 is connected to the initialization line INT2. The display substrate shown in Figure 32 is provided with a driving circuit on the lower side. It should be noted that the setting positions of the power bus 501, the power bus 502, the initialization bus 503, and the initialization bus 504 are not limited to those shown in the figure. Figures 30 to 32 show the display area R01.

[0316] FIG33A is a plan view of a pixel defining layer in a display substrate according to an embodiment of the present disclosure. FIG33B is a plan view of a pixel defining layer in a display substrate according to an embodiment of the present disclosure. For example, as shown in FIG33A and FIG33B , the pixel defining layer (PDL) includes a plurality of first defining portions 301 and a plurality of second defining portions 302. The plurality of second defining portions 302 are arranged along a second direction X, and the second defining portions 302 extend along a first direction Y. The plurality of first defining portions 301 are arranged in a plurality of groups 0301, with each group of first defining portions 0301 located between two adjacent second defining portions 302. The first defining portions 301 extend along the second direction X, and the first defining portions 301 in each group are arranged along the first direction Y.

[0317] As shown in Figures 33A and 33B , grooves are formed between two adjacent second defining portions 302. Each groove extends along a first direction Y. During inkjet printing, ink flows through the grooves. For example, with the first direction Y being the column direction and the second direction X being the row direction, the display substrate includes multiple columns of grooves. Each column of grooves defines multiple pixel openings P0.

[0318] 6 , 33A and 33B , the maximum height H1 from the first defining portion 301 to the planarization layer PLN is smaller than the maximum height H2 from the second defining portion 302 to the planarization layer PLN. That is, the thickness of the first defining portion 301 is smaller than the thickness of the second defining portion 302 .

[0319] Figure 34 is a schematic diagram of a display substrate provided in accordance with an embodiment of the present disclosure. As shown in Figure 34 , the base substrate BS includes a display area R01 and a peripheral area R02 located on at least one side of the display area R01. As shown in Figure 34 , the orthographic projection of the portion of the data line DT located in the display area R01 on the base substrate BS lies within the orthographic projection of the second defining portion 302 on the base substrate BS. The orthographic projection of the data line DT on the base substrate BS overlaps with the orthographic projection of the second defining portion 302 of the pixel defining layer PDL on the base substrate BS. This allows the second defining portion 302 to have a protrusion, facilitating ink flow into the pixel openings in the pixel defining layer during inkjet printing. As shown in Figure 34 , the orthographic projection of the display area R01 on the base substrate BS overlaps with the orthographic projection of the pixel defining layer PDL on the base substrate BS. The orthographic projection of the pixel opening P0 of the pixel defining layer PDL on the base substrate BS falls within the orthographic projection of the display area R01 on the base substrate BS.

[0320] 34 only shows two data lines DT. For example, one second defining portion 302 may correspond to one data line, but the present invention is not limited thereto.

[0321] In the embodiments of the present disclosure, the pixel circuit is not limited to the one shown in the given circuit diagram, and other suitable pixel circuits may be used. The layout diagram of the display substrate is also not limited to the one shown in the given layout diagram, and may be adjusted based on the given layout diagram, or other layout methods may be used.

[0322] For example, as shown in FIG34 , a first defining portion 301 is provided between two adjacent pixel openings P0 in a first direction Y, and a second defining portion 302 is provided between two adjacent pixel openings P0 in a second direction X, where the first direction Y intersects the second direction X. As shown in FIG6 , the thickness of the first defining portion 301 is H1, and the thickness of the second defining portion 302 is H2, where H1 ≠ H2. For example, H1 is smaller than H2.

[0323] Figure 35 is an electron microscope image of a display substrate provided in one embodiment of the present disclosure. As shown in Figure 35 , at the via hole VH, the slope angle of the bottom angle θ1 is between 65 and 75 degrees, and the slope angle θ2 is between 45 and 55 degrees. Slope angle θ2 is the slope angle of the planarization layer PLN at the via hole VH, with the reference plane (half the thickness of the planarization layer PLN) as the bottom surface. Base angle θ1 is the angle between the planarization layer PLN at the bottom surface of the via hole VH and the underlying structure.

[0324] For example, as shown in Figures 6 and 35, the display substrate also includes an insulating layer ISL, the light-emitting element 100b includes a first electrode E1, a second electrode E2, and a light-emitting functional layer FL located between the first electrode E1 and the second electrode E2, and the first electrode E1 of the light-emitting element 100b is connected to the pixel circuit 100a through a via VH passing through the insulating layer ISL.

[0325] For example, as shown in Figure 6, the display substrate further includes an encapsulation layer EPS, which is configured to encapsulate the light-emitting element 100b. The encapsulation layer EPS includes a stack of inorganic encapsulation films and organic encapsulation films. As shown in Figure 6, the encapsulation layer EPS includes an inorganic encapsulation film EPS1, an organic encapsulation film EPS2, and an inorganic encapsulation film EPS3. It should be noted that the stacking order of the organic encapsulation film and the inorganic encapsulation film is not limited to that shown in the figure, and the structure of the encapsulation layer EPS is not limited to that shown in the figure.

[0326] Figure 36 is a schematic diagram of a display substrate provided in accordance with an embodiment of the present disclosure. For example, as shown in Figure 36 , the display substrate further includes a barrier dam 701. Encapsulation glue 702 is applied to the outer surface of the encapsulation layer EPS, which acts as a bonding agent. Figure 36 illustrates the encapsulation layer EPS at its boundary. As shown in Figures 6 and 36 , the insulating layer ISL includes a planarization layer PLN, which comprises a first flat portion PLN1 and a second flat portion PLN2. A groove GR is defined between the first and second flat portions PLN1 and PLN2. The barrier dam 701 is positioned around the periphery of the display region R01 of the display substrate. The orthographic projection of the barrier dam 701 on the base substrate BS overlaps the orthographic projection of the groove GR on the base substrate BS, mitigating or preventing moisture and oxygen from entering the display region R01 along the planarization layer PLN and affecting the light-emitting elements within the display region R01. Of course, in other embodiments, the orthographic projection of the barrier dam 701 on the base substrate BS may not overlap the orthographic projection of the groove GR on the base substrate BS.

[0327] For example, the minimum distance between the edge of the display area R01 and the edge of the peripheral area R02 is in the range of 1-5 mm, that is, the size of the frame is in the range of 1-5 mm.

[0328] For example, in order to obtain a better effect of blocking water and oxygen, the groove GR is a through hole that penetrates the planarization layer PLN. As shown in Figure 36, the portion of the planarization layer PLN located inside the groove GR is the first flat portion PLN1, and the portion of the planarization layer PLN located outside the groove GR is the second flat portion PLN2. Figure 36 shows the first flat portion PLN1 with the boundary of the first flat portion PLN1, and shows the second flat portion PLN2 with the boundary of the second flat portion PLN2. Figure 36 illustrates the setting of one groove GR as an example, but the number of grooves GR is not limited to one and can be set as needed. The number of grooves GR depends on the degree of narrowness of the frame. The narrower the frame, the fewer the number of grooves GR. Of course, in other embodiments, grooves GR may not be set.

[0329] For example, as shown in Figures 3 to 5, the display substrate also includes a data line DT, a gate line G1, a gate line G2, and an initialization line INT1, and the pixel circuit 100a also includes a data write transistor T1 and a reset transistor T2, a first electrode of the data write transistor T1 is connected to the data line DT, a gate of the drive transistor T3 is connected to the second electrode of the data write transistor T1, a gate of the data write transistor T1 is connected to the gate line G1, a first electrode of the reset transistor T2 is connected to the initialization line INT1, a second electrode of the reset transistor T2 is connected to the gate of the drive transistor T3, and a gate of the reset transistor T2 is connected to the gate line G2.

[0330] Figure 37 is a schematic diagram of a display substrate provided in accordance with an embodiment of the present disclosure. Figure 38 is a schematic diagram of a circuit for a dummy sub-pixel in a display substrate provided in accordance with an embodiment of the present disclosure. Figure 39 is a layout diagram of a dummy pixel circuit in a display substrate provided in accordance with an embodiment of the present disclosure.

[0331] As shown in Figure 37 , a dummy sub-pixel 100d is provided near the edge of the display substrate. For clarity, Figure 37 does not show all dummy sub-pixels, nor all sub-pixels 100. As shown in Figure 37 , dummy sub-pixel 100d is located in peripheral region R02, while sub-pixel 100 is located in display region R01. Dummy sub-pixel 100d does not emit light. The provision of dummy sub-pixel 100d improves etching uniformity and enhances display quality.

[0332] As shown in Figure 38, the dummy sub-pixel 100d has a dummy drive transistor dT3 and a dummy reset transistor dT2. The gates of the dummy reset transistor dT2 and the dummy drive transistor dT3 are connected, and the dummy reset transistor dT2 is disconnected from the initialization line INT1 to reduce power consumption. The dummy sub-pixel 100d is provided to improve etching uniformity rather than to achieve a light-emitting function. As shown in Figure 38, the dummy sub-pixel 100d includes a dummy pixel circuit 100da and a dummy light-emitting element 100db. As shown in Figure 38, the composition of the dummy pixel circuit 100da can refer to the composition of the pixel circuit 100a, and the composition of the dummy light-emitting element 100db can refer to the composition of the light-emitting element 100b. However, the dummy pixel circuit 100da may have a broken wire. The dummy pixel circuit 100da shown in FIG38 is illustrated by taking as an example a case where the first electrode E1 of the dummy light-emitting element 100db is not connected to the node N2 (the first electrode T3a of the dummy drive transistor dT3), and the dummy reset transistor dT2 is not connected to the initialization line INT1. In other embodiments, other disconnection methods can be used to disable the dummy sub-pixel 100d. The bold cross in FIG38 indicates a disconnection. For example, in order to disconnect the dummy reset transistor dT2 of the dummy sub-pixel 100d from the initialization line INT1, a via hole may not be provided.

[0333] As shown in Figure 38, the dummy sub-pixel 100d further includes a dummy data writing transistor dT1. Figures 38 and 39 also show a dummy data line dDT.

[0334] As shown in FIG. 38 , the dummy sub-pixel 100 d further includes a dummy storage capacitor dCst.

[0335] In the embodiment of the present disclosure, except for the main components such as transistors and storage capacitors in the dummy sub-pixel 100 d which are given new reference numerals, the reference numerals of the remaining components may refer to the reference numerals in the sub-pixel 100 .

[0336] Figure 40 is a schematic diagram of a display substrate provided in accordance with an embodiment of the present disclosure. For example, as shown in Figure 40 , the display substrate further includes a dummy data line dDT, which extends along a first direction Y and is insulated from the data line DT. A dummy sub-pixel 100d includes at least two adjacent dummy sub-pixels 100d in a second direction X, and the dummy data lines dDT of at least two dummy sub-pixels 100d are connected to each other. As shown in Figure 40 , the dummy data line dDT is located in a peripheral region R02. As shown in Figure 40 , the peripheral region R02 surrounds the display region R01.

[0337] For example, the dummy data line dDT is connected to a constant voltage terminal to be configured to provide a constant voltage. For example, the constant voltage terminal includes a port that provides a first voltage signal VDD, a port that provides a second voltage signal VSS, or a port that provides an initialization signal Vinit1. For example, the dummy data line dDT is connected to a first power line PL1, a second power line PL2, or an initialization line INT1. Connecting the dummy data line dDT to the constant voltage terminal reduces the resistance of the power line connected to the constant voltage terminal, thereby improving display quality.

[0338] For example, as shown in FIG40, at least two dummy sub-pixels 100d include a first dummy sub-pixel 100d1, a second dummy sub-pixel 100d2, and a third dummy sub-pixel 100d3, and three dummy data lines dDT of the first dummy sub-pixel 100d1, the second dummy sub-pixel 100d2, and the third dummy sub-pixel 100d3 are connected to each other. FIG40 shows the three dummy data lines dDT connected to each other.

[0339] For example, as shown in Figures 3 to 5, the display substrate further includes a first power line PL1, and the pixel circuit 100a further includes a light emitting control transistor T5, a first electrode of the light emitting control transistor T5 is connected to the first power line PL1, and a second electrode of the light emitting control transistor T5 is connected to the second electrode of the driving transistor T3.

[0340] For example, as shown in Figures 38 and 39, the dummy sub-pixel 100d also includes a dummy light-emitting control transistor dT5, the first electrode of the dummy light-emitting control transistor dT5 is disconnected from the first power line PL1, and the second electrode of the dummy light-emitting control transistor dT5 is connected to or disconnected from the second electrode of the dummy driving transistor T3.

[0341] As shown in FIG39 , no via is provided within the dashed box F1 (corresponding to via V7 in FIG5 ), thereby disconnecting the dummy reset transistor dT2 from the initialization line INT1. As shown in FIG39 , no via is provided within the dashed box F2 (corresponding to via VH in FIG5 ), thereby disconnecting the dummy pixel circuit 100da from the dummy light-emitting element 100db. As shown in FIG39 , no via is provided within the dashed box F3 (corresponding to via V11 in FIG5 ), thereby disconnecting the first electrode of the dummy light-emitting control transistor dT5 from the first power line PL1. As shown in FIG39 , no via is provided within the dashed box F4 (corresponding to via V13 in FIG5 ), thereby disconnecting the second electrode of the dummy light-emitting control transistor dT5 from the second electrode of the dummy drive transistor T3. Of course, to connect the second electrode of the dummy light-emitting control transistor dT5 to the second electrode of the dummy drive transistor T3, vias need to be provided at the corresponding locations, and the same applies to other locations.

[0342] For example, as shown in Figures 5, 6, 33A, and 33B, the display substrate further includes a pixel defining layer PDL, the pixel defining layer PDL includes a defining portion 300, the pixel opening P0 is defined by the defining portion 300, the light-emitting element 100b includes a first electrode E1 and a light-emitting functional layer FL, the pixel defining layer PDL is configured to expose at least a portion of the first electrode E1, and at least a portion of the film layer in the light-emitting functional layer FL covers the sidewall SW of the defining portion 300 (as shown in Figure 6). Figure 6 illustrates an example in which the light-emitting functional layer FL is located entirely within the pixel opening P0. In other embodiments, the light-emitting functional layer FL may include a common layer, as shown in Figure 45.

[0343] For example, as shown in FIG6 , the light-emitting element 100b further includes a second electrode E2. The light-emitting functional layer FL is positioned between the first electrode E1 and the second electrode E2, and the second electrode E2 contacts the top wall of the defining portion 300. Of course, as shown in FIG45 , if the light-emitting functional layer FL includes a common layer, the second electrode E2 contacts the common layer in the light-emitting functional layer FL. For example, the second electrode E2 contacts the common layer in the light-emitting functional layer FL that is adjacent to the second electrode E2. The common layer in FIG45 is the electron injection layer EIL. As shown in FIG6 and FIG45 , the orthographic projection of the second electrode E2 on the base substrate BS overlaps with the orthographic projection of the top wall of the defining portion 300 on the base substrate BS.

[0344] For example, as shown in FIG6 , the display substrate further includes an insulating layer ISL. The first electrode E1 of the light-emitting element 100b is connected to the pixel circuit 100a via a via VH extending through the insulating layer ISL. The orthographic projection of the via VH on the base substrate BS overlaps the orthographic projection of the first defining portion 301 on the base substrate BS. As shown in FIG6 , FIG33A , and FIG33B , the defining portion 300 includes a first defining portion 301 and a second defining portion 302. The thickness H1 of the first defining portion 301 is less than the thickness H2 of the second defining portion 302.

[0345] Figure 41A is a schematic diagram of a display substrate provided by an embodiment of the present disclosure. For example, as shown in Figure 41A, the display substrate also includes a dummy pixel defining layer dPDL, and the dummy pixel defining layer dPDL includes a plurality of dummy defining portions d300 (second dummy defining portions d302) arranged along the second direction X. The extension direction of the second dummy defining portion d302 is the same as the extension direction of the second defining portion 302, and the spacing W4 between two adjacent dummy defining portions d300 (second dummy defining portions d302) is greater than the spacing W3 between two adjacent second defining portions 302. Figure 41A also shows a plurality of first dummy defining portions d301 extending along the second direction X. As shown in Figure 41, a plurality of first dummy defining portions d301 are provided between adjacent second dummy defining portions d302. Figure 41A shows the display area R01 and the peripheral area R02. The spacing W4 is greater than the spacing W3, which facilitates the wiring of the peripheral area R02. For example, the spacing W4 can be the maximum spacing, i.e., the maximum spacing W4 between two adjacent dummy defining portions d300 is greater than the maximum spacing W3 between two adjacent second defining portions 302. For example, the spacing W4 can be the minimum spacing, i.e., the minimum spacing W4 between two adjacent dummy defining portions d300 is greater than the minimum spacing W3 between two adjacent second defining portions 302. FIG41A illustrates an example in which three columns of dummy sub-pixels 100d are provided between two adjacent second dummy defining portions d302. However, the present invention is not limited thereto. One, two, or more than three columns of dummy sub-pixels 100d may also be provided between two adjacent second dummy defining portions d302. In other words, at least one column of dummy sub-pixels 100d is provided between two adjacent second dummy defining portions d302.

[0346] It should be noted that Figure 41A takes the peripheral area R02 as an example in which a first dummy defining portion d301 extending along the second direction X is provided, but is not limited to this. In some embodiments, the peripheral area R02 may not be provided with a first dummy defining portion d301. In this case, the dummy pixel defining layer dPDL only includes the second dummy defining portion d302.

[0347] 41A , the spacing W4 between two adjacent dummy defining portions d300 is 2-20 times the spacing W3 between two adjacent second defining portions 302. When multiple columns of dummy sub-pixels 100d are provided between two adjacent second defining portions 302, the spacing W4 may be a multiple of the spacing W3.

[0348] 41A , the width W6 of the second dummy defining portion d302 in the second direction X is greater than the width W5 of the second defining portion 302 in the second direction X. For example, the width W6 and the width W5 may refer to maximum widths. Of course, the width W6 and the width W5 may also refer to minimum widths.

[0349] Figure 41B is a schematic diagram of a display substrate provided by another embodiment of the present disclosure. As shown in Figure 41B , width W6 is greater than width W5. For this purpose, please refer to the description of Figure 41A . Figure 41B illustrates an example in which a row of dummy sub-pixels 100d is provided between two adjacent second dummy defining portions d302. The dummy pixel defining layer dPDL in Figure 41B may also include only the second dummy defining portions d302, without the first dummy defining portion d301.

[0350] Of course, in other embodiments, the width W6 may be equal to the width W5.

[0351] FIG42 is a schematic diagram of a display substrate provided in accordance with an embodiment of the present disclosure. For example, as shown in FIG3 to FIG5 and FIG42, the display substrate further includes a reset transistor T4, an initialization line INT2, and an initialization bus 504. The initialization bus 504 is disposed outside the display region R01 of the display substrate. The first electrode of the reset transistor T4 is connected to the initialization bus 504. The first electrode T4a of the reset transistor T4 is connected to the initialization bus 504 via the initialization line INT2. The second electrode T4b of the reset transistor T4 is connected to the light-emitting element 100b via the driving transistor T3. The reset transistor T4 is connected to a row of sub-pixels 100. For the same row of sub-pixels 100, the number of reset transistors T4 is less than the number of sub-pixels 100 to reduce power consumption. FIG42 illustrates the example of a row of sub-pixels corresponding to one reset transistor T4.

[0352] As shown in FIG42 , the second electrode of the reset transistor T4 is connected to the reset signal transmission line INI. As shown in FIG42 , the reset signal transmission line INI is connected to the sub-pixel 100. As shown in FIG5 , the reset signal transmission line INI is connected to the first electrode E1 of the light-emitting element 100 b via the drive transistor T3. Referring to FIG5 to FIG8E , the second electrode T5 b of the light-emitting control transistor T5 is connected to the second electrode T3 b of the drive transistor T3 via the reset signal transmission line INI.

[0353] As shown in Figure 42, the reset transistor T4 is located in the peripheral region R02. As shown in Figure 42, the initialization bus 504 is located in the peripheral region R02.

[0354] FIG43 is a schematic diagram of a display substrate provided in accordance with an embodiment of the present disclosure. For example, as shown in FIG5 and FIG43 , the display substrate further includes a light-emission control transistor T5, a first power line PL1, and a first power bus 501. The first power line PL1 is configured to provide a first voltage signal to the pixel circuit 100a. The first power line PL1 is connected to the first power bus 501. The first power line PL1 includes a first power connection line PL12 extending along a first direction Y and a first power signal line PL11 extending along a second direction X. The first electrode of the light-emission control transistor T5 is connected to the first power line PL1, and the second electrode of the light-emission control transistor T5 is connected to the second electrode of the driving transistor T3. The number of light-emission control transistors T5 in a row of sub-pixels 100 can be equal to the number of sub-pixels 100 in the row.

[0355] Figure 44 is a circuit diagram of a display substrate provided in accordance with an embodiment of the present disclosure. As shown in Figure 44 , the number of emission control transistors T5 in a row of sub-pixels 100 is less than the total number of sub-pixels 100 in that row. For example, all three sub-pixels 100 in a pixel PX are connected to the same emission control transistor T5.

[0356] For example, when the three sub-pixels 100 in each pixel PX are connected to the same emission control transistor T5 and different pixels PX are connected to different emission control transistors T5, the number of emission control transistors T5 in a row of sub-pixels 100 is greater than the number of reset transistors T4.

[0357] 3 to 6 and 9 to 14 , an embodiment of the present disclosure further provides a display substrate, comprising: a base substrate BS and a plurality of sub-pixels 100 disposed on the base substrate BS; the sub-pixels 100 comprise: a pixel circuit 100 a and a light-emitting element 100 b, the pixel circuit 100 a comprising a driving transistor T3 and a storage capacitor Cst, the storage capacitor Cst comprising a first plate Ca and a second plate Cb, the first plate Ca of the storage capacitor Cst being connected to the gate of the driving transistor T3, the second plate Cb of the storage capacitor Cst being connected to the first electrode of the driving transistor T3; the light-emitting element 100 b being electrically connected to the pixel circuit 100 a, the pixel circuit 100 a being configured to drive the light-emitting element 100 b, the sub-pixel 100 comprising a pixel opening P0, the pixel opening P0 being configured to define a light-emitting area of ​​the sub-pixel 100, and the orthographic projection of the storage capacitor Cst on the base substrate BS being aligned with the pixel opening P 0 overlaps with the orthographic projection of the driving transistor T3 on the substrate BS, the orthographic projection of the channel of the driving transistor T3 on the substrate BS overlaps with the orthographic projection of the pixel opening P0 on the substrate BS, the second plate Cb and the channel of the driving transistor T3 are arranged on the same layer, and the second plate Cb is closer to the substrate BS than the first plate Ca. The display substrate satisfies the following relationship: the value range of (W*L+S2)*M1 / M2 is [0.014, 0.133], and P=k0*(W / L)*Uc, the value range of k0 is [2.8*E-07, 5.8*E-06], W is the width of the channel of the driving transistor T3, L is the length of the channel of the driving transistor T3, S2 is the facing area of ​​the second plate Cb and the first plate Ca, M1 is the number of pixel openings P0 of the display substrate, M2 is the area of ​​the display substrate, Uc is the voltage across the light-emitting element 100b, and P is the power consumption of the sub-pixel 100.

[0358] The display substrate provided by the embodiment of the present disclosure satisfies the following relationship: the value range of (W*L+S2)*M1 / M2 is [0.014, 0.133], and P=k0*(W / L)*Uc, so as to obtain a display substrate with lower power consumption.

[0359] 3 to 6, 9 to 14, 33A, 33B, and 34, an embodiment of the present disclosure further provides a display substrate, comprising: a base substrate BS and a plurality of sub-pixels 100 disposed on the base substrate BS; the sub-pixels 100 comprise: a pixel circuit 100a and a light-emitting element 100b, the pixel circuit 100a comprising a driving transistor T3 and a storage capacitor Cst, the storage capacitor Cst comprising a first plate Ca and a second plate Cb, the first plate Ca of the storage capacitor Cst being connected to the gate of the driving transistor T3, the second plate Cb of the storage capacitor Cst being connected to the first electrode of the driving transistor T3; the light-emitting element 100b being electrically connected to the pixel circuit 100a, the pixel circuit 100a being configured to drive the light-emitting element 100b, the sub-pixel 100 comprising a pixel opening P0, the pixel opening P0 being configured to define a light-emitting area of ​​the sub-pixel 100, the orthographic projection of the storage capacitor Cst on the base substrate BS being aligned with the pixel opening P0 on the base substrate BS The orthographic projections on the substrate BS overlap, the orthographic projection of the channel of the driving transistor T3 on the base substrate BS overlaps the orthographic projection of the pixel opening P0 on the base substrate BS, the second plate Cb is arranged on the same layer as the channel of the driving transistor T3, and the second plate Cb is closer to the base substrate BS than the first plate Ca. A first limiting portion 301 is provided between two adjacent pixel openings P0 in a first direction Y, and a second limiting portion 302 is provided between two adjacent pixel openings P0 in a second direction X, and the first direction Y intersects with the second direction X. The thickness of the first limiting portion 301 is H1, and the thickness of the second limiting portion 302 is H2, where H1≠H2. The display substrate satisfies the following relationship: P=k0*(W / L)*Uc, where the value range of k0 is [2.8*E-07, 5.8*E-06], W is the width of the channel of the driving transistor T3, L is the length of the channel of the driving transistor T3, Uc is the voltage across the light-emitting element 100b, and P is the power consumption of the sub-pixel 100.

[0360] 3 to 6 , 9 to 14 , 33A , 33B , and 36 , embodiments of the present disclosure further provide a display substrate, including: a base substrate BS and a plurality of sub-pixels 100 disposed on the base substrate BS; the sub-pixels 100 include: a pixel circuit 100 a and a light-emitting element 100 b ; the pixel circuit 100 a includes a driving transistor T3 and a storage capacitor Cst; the storage capacitor Cst includes a first plate Ca and a second plate Cb; the first plate Ca of the storage capacitor Cst is connected to the gate of the driving transistor T3; the second plate Cb of the storage capacitor Cst is connected to the first electrode of the driving transistor T3; The light-emitting element 100b is electrically connected to the pixel circuit 100a. The pixel circuit 100a is configured to drive the light-emitting element 100b. The sub-pixel 100 includes a pixel opening P0. The pixel opening P0 is configured to define a light-emitting area of ​​the sub-pixel 100. The orthographic projection of the storage capacitor Cst on the substrate BS overlaps with the orthographic projection of the pixel opening P0 on the substrate BS. The orthographic projection of the channel of the driving transistor T3 on the substrate BS overlaps with the orthographic projection of the pixel opening P0 on the substrate BS. The second electrode Cb is arranged on the same layer as the channel of the driving transistor T3. The second electrode Cb is closer to the substrate BS than the first electrode Ca. The substrate further includes an insulating layer ISL, a blocking dam 701, and an encapsulation layer EPS. The light-emitting element 100b includes a first electrode E1, a second electrode E2, and a light-emitting functional layer FL located between the first electrode E1 and the second electrode E2. The first electrode E1 of the light-emitting element 100b is connected to the pixel circuit 100a through a via VH penetrating the insulating layer ISL. The encapsulation layer EPS is configured to encapsulate the light-emitting element 100b. The encapsulation layer EPS includes a stack of an inorganic encapsulation film and an organic encapsulation film. An encapsulation glue 702 is provided on the outside of the encapsulation layer EPS. The insulating layer ISL includes a planarization layer PLN. The planarization layer PLN includes a first flat portion P LN1 and the second flat portion PLN2, a groove GR is provided between the first flat portion PLN1 and the second flat portion PLN2, the blocking dam 701 is located at the periphery of the display area R01 of the display substrate, and the orthographic projection of the blocking dam 701 on the base substrate BS covers the orthographic projection of the groove GR on the base substrate BS; the display substrate satisfies the following relationship: P = k0*(W / L)*Uc, the value range of k0 is [2.8*E-07, 5.8*E-06], W is the width of the channel of the driving transistor T3, L is the length of the channel of the driving transistor T3, Uc is the cross-voltage of the light-emitting element 100b, and P is the power consumption of the sub-pixel 100.

[0361] The display substrate provided by the embodiment of the present disclosure satisfies the following relationship: P=k0*(W / L)*Uc, so as to facilitate obtaining a display substrate with lower power consumption, and the orthographic projection of the blocking dam 701 on the base substrate BS covers the orthographic projection of the groove GR on the base substrate BS, so as to reduce the risk of water and oxygen entering the display area R01 along the planarization layer PLN, thereby avoiding affecting the light-emitting elements in the display area R01.

[0362] 3 to 5 and 9 to 13 , an embodiment of the present disclosure further provides a display substrate, comprising: a base substrate BS and a plurality of sub-pixels 100 disposed on the base substrate BS; the sub-pixels 100 comprise: a pixel circuit 100 a and a light-emitting element 100 b, the pixel circuit 100 a comprising a driving transistor T3 and a storage capacitor Cst, the storage capacitor Cst comprising a first plate Ca and a second plate Cb, the first plate Ca of the storage capacitor Cst being connected to the gate of the driving transistor T3, the second plate Cb of the storage capacitor Cst being connected to the first electrode of the driving transistor T3; the light-emitting element 100 b being electrically connected to the pixel circuit 100 a, the pixel circuit 100 a being configured to drive the light-emitting element 100 b, the sub-pixel 100 comprising a pixel opening P0, the pixel opening P1 being connected to the first electrode of the driving transistor T3, and the pixel opening P2 being connected to the second electrode of the driving transistor T3. 0 is configured to define the light-emitting area of ​​the sub-pixel 100, the orthographic projection of the storage capacitor Cst on the substrate BS overlaps with the orthographic projection of the pixel opening P0 on the substrate BS, the orthographic projection of the channel of the driving transistor T3 on the substrate BS overlaps with the orthographic projection of the pixel opening P0 on the substrate BS, the second electrode Cb is arranged on the same layer as the channel of the driving transistor T3, the second electrode Cb is closer to the substrate BS than the first electrode Ca, and the display substrate satisfies the following relationship: P = k0*(W / L)*Uc, the value range of k0 is [2.8*E-07, 5.8*E-06], W is the width of the channel of the driving transistor T3, L is the length of the channel of the driving transistor T3, Uc is the cross-voltage of the light-emitting element 100b, and P is the power consumption of the sub-pixel 100.

[0363] The display substrate provided by the embodiments of the present disclosure satisfies the following relationship: P = k0*(W / L)*Uc, which is conducive to obtaining a display substrate with lower power consumption, and the second electrode Cb is arranged in the same layer as the channel of the driving transistor T3, which is conducive to improving the retention capability of the capacitor and facilitating the improvement of the ratio of the storage capacitor to the area of ​​the pixel opening, thereby increasing the area share of the storage capacitor and improving the display quality.

[0364] The embodiments of the present disclosure further provide a display substrate, comprising: a base substrate BS and a plurality of sub-pixels 100 disposed on the base substrate BS; the sub-pixels 100 include: a pixel circuit 100a and a light-emitting element 100b, the pixel circuit 100a including a driving transistor T3 and a storage capacitor Cst, the storage capacitor Cst including a first plate Ca and a second plate Cb, the first plate Ca of the storage capacitor Cst being connected to the gate of the driving transistor T3, the second plate Cb of the storage capacitor Cst being connected to the first electrode of the driving transistor T3; the light-emitting element 100b is electrically connected to the pixel circuit 100a. The pixel circuit 100a is configured to drive the light-emitting element 100b. The sub-pixel 100 includes a pixel opening P0. The pixel opening P0 is configured to define a light-emitting area of ​​the sub-pixel 100. The orthographic projection of the storage capacitor Cst on the substrate BS overlaps with the orthographic projection of the pixel opening P0 on the substrate BS. The orthographic projection of the channel of the driving transistor T3 on the substrate BS overlaps with the orthographic projection of the pixel opening P0 on the substrate BS. The second electrode Cb is provided on the same layer as the channel of the driving transistor T3. The second electrode plate Cb is closer to the base substrate BS than the first electrode plate Ca. The display substrate further includes a data line DT, a gate line G1, a gate line G2, and an initialization line INT1. The pixel circuit 100a further includes a data writing transistor T1 and a reset transistor T2. The first electrode of the data writing transistor T1 is connected to the data line DT, the gate of the driving transistor T3 is connected to the second electrode of the data writing transistor T1, the gate of the data writing transistor T1 is connected to the gate line G1, the first electrode of the reset transistor T2 is connected to the initialization line INT1, the second electrode of the reset transistor T2 is connected to the gate of the driving transistor T3, and the gate of the reset transistor T2 is connected to the gate line G2. The display substrate is connected, and a dummy sub-pixel 100d is provided near its edge. The dummy sub-pixel 100d has a dummy driving transistor T3 and a dummy reset transistor dT2. The dummy reset transistor dT2 is connected to the gate of the dummy driving transistor T3, and the dummy reset transistor dT2 is disconnected from the initialization line INT1; the display substrate satisfies the following relationship: P = k0*(W / L)*Uc, the value range of k0 is [2.8*E-07, 5.8*E-06], W is the width of the channel of the driving transistor T3, L is the length of the channel of the driving transistor T3, Uc is the cross-voltage of the light-emitting element 100b, and P is the power consumption of the sub-pixel 100.

[0365] The display substrate provided by the embodiment of the present disclosure satisfies the following relationship: P=k0*(W / L)*Uc, so as to obtain a display substrate with lower power consumption, and the dummy reset transistor dT2 is disconnected from the initialization line INT1, which is conducive to reducing power consumption.

[0366] The embodiments of the present disclosure further provide a display substrate, comprising: a base substrate BS and a plurality of sub-pixels 100 arranged on the base substrate BS; the sub-pixels 100 comprise: a pixel circuit 100a and a light-emitting element 100b, the pixel circuit 100a comprises a driving transistor T3 and a storage capacitor Cst, the storage capacitor Cst comprises a first electrode Ca and a second electrode Cb, the first electrode Ca of the storage capacitor Cst is connected to the gate of the driving transistor T3, and the second electrode Cb of the storage capacitor Cst is connected to the first electrode of the driving transistor T3; the light-emitting element 100b is electrically connected to the pixel circuit 100a, the pixel circuit 100a is configured to drive the light-emitting element 100b, the sub-pixel 100 comprises a pixel opening P0, the pixel opening P0 is configured to define a light-emitting area of ​​the sub-pixel 100, and the positive projection of the storage capacitor Cst on the base substrate BS is aligned with the positive projection of the pixel opening P0 on the base substrate BS. The shadows overlap, the orthographic projection of the channel of the driving transistor T3 on the base substrate BS overlaps with the orthographic projection of the pixel opening P0 on the base substrate BS, the second electrode Cb is arranged on the same layer as the channel of the driving transistor T3, and the second electrode Cb is closer to the base substrate BS than the first electrode Ca. The display substrate further includes a pixel defining layer PDL, the pixel defining layer PDL includes a defining portion 300, and the pixel opening P0 is defined by the defining portion 300. The light-emitting element 100b includes a first electrode E1 and a light-emitting functional layer FL, the pixel defining layer PDL is configured to expose at least a portion of the first electrode E1, and the light-emitting functional layer FL covers the side wall SW of the defining portion 300 (as shown in FIG6 ). The display substrate satisfies the following relationship: P=k0*(W / L)*Uc, the value range of k0 is [2.8*E-07, 5.8*E-06], W is the width of the channel of the driving transistor T3, and L is the width of the driving transistor T3 , Uc is the cross voltage of the light-emitting element 100b, and P is the power consumption of the sub-pixel 100.

[0367] In the display substrate provided by the embodiment of the present disclosure, the light-emitting functional layer FL covers the sidewall SW of the defining portion 300 and satisfies the following relationship: P=k0*(W / L)*Uc, so as to obtain a display substrate with lower power consumption.

[0368] For example, in some embodiments, the first voltage signal VDD is 17V, the second voltage signal VSS is 2V, k0=2.8*E-07, W=2 microns, L=30 microns, Uc=15V, then according to P=k0*(W / L)*Uc, P=2.8*E-07 watts.

[0369] The power consumption P above refers to the power consumption of a single sub-pixel. For sub-pixels emitting different colors, differentiated designs can be used to match the power consumption of sub-pixels of different colors, thereby reducing the power consumption of the entire panel. For example, for red, green, and blue sub-pixels, the power consumption of the red sub-pixel should be less than that of the green sub-pixel, and the power consumption of the green sub-pixel should be less than that of the blue sub-pixel, thus matching the power consumption of the three colors and reducing the power consumption of the entire panel.

[0370] For example, in any of the above-mentioned display substrates that satisfies P=k0*(W / L)*Uc, the display substrate may also satisfy the following relationship: the value range of (W*L+S2)*M1 / M2 is [0.014, 0.133], S2 is the facing area of ​​the second electrode Cb and the first electrode Ca, M1 is the number of pixel openings P0 of the display substrate, and M2 is the area of ​​the display substrate, so as to facilitate the formation of a display substrate with better performance formed by an inkjet printing process.

[0371] For example, in an embodiment of the present disclosure, the display substrate may satisfy at least one of the following: the value range of (W*L+S2)*M1 / M2 is [0.014, 0.133], the value range of S2 / (W*L) is [2.82, 28.85], and P=k0*(W / L)*Uc. The meaning of each formula can be referred to the previous description and will not be repeated here.

[0372] In the embodiments of the present disclosure, the "*" in the formula represents a multiplication sign, the " / " represents a division sign, the range [Mx, My] represents greater than or equal to Mx, and less than or equal to My, Mx and My are numbers, and the numbers with E in [] are values ​​expressed in scientific notation.

[0373] FIG45 is a schematic diagram of a display substrate provided in an embodiment of the present disclosure. As shown in FIG45 , the light-emitting functional layer FL includes a hole injection layer HIL, a hole transport layer HTL, a light-emitting layer EML, and an electron injection layer EIL, and the materials of the hole injection layer HIL, the hole transport layer HTL, and the light-emitting layer EML are located in the pixel opening defined by the pixel defining layer PDL, and the electron injection layer EIL is a common layer. FIG45 also shows that the display substrate includes a light extraction layer CPL to improve the light extraction efficiency. For example, the hole injection layer HIL and the hole transport layer HTL can adopt a gradient doping mode or a single-layer stacking arrangement. Of course, the structure of the display substrate provided in the embodiment of the present disclosure is not limited to that shown in FIG45 .

[0374] FIG46 is a schematic diagram of a brightness test of a display substrate provided in an embodiment of the present disclosure. As shown in FIG46 , the display substrate includes a display area R01 and a peripheral area R02, and the sub-pixels are located in the display area R01. A plurality of test points are selected from the display area. 9 test points are selected in FIG46 , and the brightness of each test point can be measured. FIG46 shows that the sub-pixels can be divided into a plurality of sub-pixel groups PG. FIG46 shows sub-pixel group PG1, sub-pixel group PG2, and sub-pixel group PG3. For example, in some embodiments, each sub-pixel group PG may correspond to one or more rows of sub-pixels. For example, in some embodiments, each sub-pixel group PG may correspond to one or more columns of sub-pixels.

[0375] As shown in Figure 46, the first to third test points are three test points at different positions of sub-pixel group PG1, the fourth to sixth test points are three test points at different positions of sub-pixel group PG2, and the seventh to ninth test points are three test points at different positions of sub-pixel group PG3.

[0376] For example, the luminance of the subpixels in each subpixel group PG may be the average of the luminances at the test points corresponding to the subpixel group PG. As shown in FIG46 , the luminance of the subpixels in subpixel group PG1 is the average of the luminance values ​​at the first test point, the second test point, and the third test point; the luminance of the subpixels in subpixel group PG2 is the average of the luminance values ​​at the fourth test point, the fifth test point, and the sixth test point; and the luminance of the subpixels in subpixel group PG3 is the average of the luminance values ​​at the seventh test point, the eighth test point, and the ninth test point.

[0377] As shown in Figure 46 , for the same subpixel group, the test point located in the middle position can be the middle position of the test points near the boundary of the display area. For example, the distance from the second test point to the first test point is equal to the distance from the second test point to the third test point. Similarly, the distance from the fifth test point to the fourth test point is equal to the distance from the fifth test point to the sixth test point, and the distance from the eighth test point to the seventh test point is equal to the distance from the eighth test point to the ninth test point.

[0378] For example, as shown in FIG46 , when testing the brightness of the entire display substrate, the distance between the fourth test point and the first test point is equal to the distance between the fourth test point and the seventh test point, the distance between the fifth test point and the second test point is equal to the distance between the fifth test point and the eighth test point, and the distance between the sixth test point and the third test point is equal to the distance between the sixth test point and the ninth test point, but is not limited thereto.

[0379] As shown in Figure 46, the following principles can be applied when selecting test points. Figure 46 shows the length Ly and width Lx of display area R01. The distance Lx0 between the test point and the boundary of display area R01 in the second direction X is greater than or equal to Lx / 10, and the distance Ly0 between the test point and the boundary of display area R01 in the first direction Y is greater than or equal to Ly / 10.

[0380] 24 and 29 , the data lines DT include data lines DT1 , DT2 , and DT3 . Data line DT1 provides a data signal to the first sub-pixel 101 , data line DT2 provides a data signal to the second sub-pixel 102 , and data line DT3 provides a data signal to the third sub-pixel 103 .

[0381] As shown in Figures 5, 24, and 29, two conductive pattern layers are used to form the first power line PL1 and initialization line INT1 of pixel circuit 100a. The portions of the first power line PL1 and initialization line INT1 extending along the first direction Y are formed in segments. The portions of the first power line PL1 and initialization line INT1 extending along the second direction X are both located in the second conductive pattern layer LY2.

[0382] As shown in FIG. 5 , FIG. 24 and FIG. 29 , the signal connection line 412 includes at least one of a first power connection line PL12 and an initialization connection line INT12 .

[0383] For example, as shown in Figures 24 and 29, the display substrate also includes: a data line DT, the data line DT is configured to provide a data voltage to the sub-pixel 100, and the orthographic projection of at least one of the signal connection line 412 and the data line DT on the base substrate BS overlaps with the orthographic projection of the pixel opening P0 of at least one of the multiple sub-pixels 100 on the base substrate BS.

[0384] During inkjet printing, the flatter the bottom surface of the pixel opening P0 of the sub-pixel 100 (ie, the first electrode E1 of the light-emitting element) is, the more color shift can be reduced or avoided, and the better the display effect of the display substrate.

[0385] The portion of the data line DT or the signal connection line 412 in the second conductive pattern layer LY2 directly below the pixel opening P0 can play a leveling role to improve display quality.

[0386] For example, the signal connection line 412 includes at least one of a portion of the first power line PL1 extending along the first direction Y and a portion of the initialization line extending along the first direction Y.

[0387] For example, as shown in FIG. 5 , FIG. 24 and FIG. 29 , the signal connection line 412 and the signal transmission line 411 are connected through a via.

[0388] For example, as shown in Figures 5, 24, and 29, to level the bottom surface of the pixel opening P0 of the sub-pixel 100, the display substrate further includes a signal transmission line 512. The signal transmission line 512 is configured to provide a voltage signal to the sub-pixel 100. The signal transmission line 512 extends along the second direction X, and the orthographic projection of the signal transmission line 512 on the base substrate BS overlaps with the orthographic projection of the pixel opening P0 of at least one of the multiple sub-pixels 100 on the base substrate BS. This facilitates vertical leveling of the ink during inkjet printing and reduces color shift at vertical viewing angles.

[0389] For example, referring to FIG. 5 , FIG. 24 , and FIG. 29 , the signal transmission line 512 includes at least one of the gate line G1 , the gate line G2 , and a portion of the initialization line INT11 extending in the second direction X. As shown in FIG.

[0390] In the embodiment of the present disclosure, the pixel circuit 100a may not be provided with at least one of the reset transistor T4 and the light emission control transistor T5, and the structure of the pixel circuit 100a is not limited to that shown in the figure and may be configured as needed.

[0391] In the drawings of the embodiments of the present disclosure, the orthographic projection of the pixel opening P0 of the sub-pixel on the substrate and the orthographic projection of the via VH on the substrate are not overlapped for illustration, but in other embodiments, the orthographic projection of the pixel opening P0 of the sub-pixel on the substrate and the orthographic projection of the via VH on the substrate can also overlap.

[0392] For example, the embodiments of the present disclosure can adapt the pixel openings of different sizes of sub-pixels through the backplane film layer design, such as the design of the elements in the second conductive pattern layer, to improve the flatness of the light-emitting functional layer, thereby reducing the color deviation of the left and right viewing angles of the display substrate.

[0393] Since sub-pixels emitting different colors have different luminous efficiencies, color deviation can be reduced and display quality improved by adjusting the size of the pixel opening of the sub-pixel, adjusting the size of the third plate of the storage capacitor, and overlapping the opening and signal line.

[0394] For example, in the embodiments of the present disclosure, the thickness of an element refers to the dimension of the element in a direction perpendicular to the substrate.

[0395] For example, in some embodiments, the size of the pixel opening P0 of the first sub-pixel 101 in the second direction X is 28-36 microns, the size of the pixel opening P0 of the second sub-pixel 102 in the second direction X is 30-38 microns, and the size of the pixel opening P0 of the third sub-pixel 103 in the second direction X is 68-74 microns. Of course, the size of the pixel opening P0 of the sub-pixel 100 is not limited thereto and can be determined as needed.

[0396] 6 , the insulating layer ISL includes a passivation layer PVX and a planarization layer PLN. The passivation layer PVX is made of an inorganic insulating material, and the planarization layer PLN is made of an organic insulating material. For example, the thickness of the planarization layer PLN is 3-7 μm.

[0397] The display substrate provided by the embodiments of the present disclosure can reduce color shift to less than 0.015 under left-right viewing angles. Furthermore, by overlapping the pixel opening of a subpixel with a signal connection line (designed for the location of the longitudinal wiring), the color shift problem of the second subpixel (the green subpixel) is significantly improved, with minimal deviation under a 60-degree left-right viewing angle.

[0398] In conventional inkjet-printed products, the planarization layer PLN is thicker than that of vapor-deposited products. However, the display substrate provided in the embodiments of the present disclosure, through its backplane design, can achieve a limited reduction in the thickness of the planarization layer. This, in turn, reduces the width of the via hole VH, significantly improving color shift. For example, in the embodiments of the present disclosure, the planarization layer thickness is 3-7 microns.

[0399] For example, the insulating layer ISL shown in FIG6 can be composed of an inorganic material layer or an organic material layer, or an organic material layer and an organic material layer. The preparation of the vias in the insulating layer ISL is not limited to a single production. To reduce the via diameter, multiple vias are prepared in a form of trepanning to facilitate the flatness of the light-emitting functional layer and thereby reduce color shift. For example, the ratio of the diameter of the topmost via to the width of the pixel opening of the sub-pixel is less than 0.3. The width of the pixel opening of the sub-pixel may refer to the maximum dimension of the pixel opening of the sub-pixel in the second direction X.

[0400] For example, gate line G1 may be referred to as a first gate line, gate line G2 may be referred to as a second gate line, gate line G4 may be referred to as a third gate line, reset transistor T2 may be referred to as a first reset transistor, and reset transistor T4 may be referred to as a second reset transistor. In this case, the display substrate further includes: a data line, a first gate line, a second gate line, a third gate line, a first power line, a first initialization line, and a second initialization line, wherein the data line is configured to provide a data voltage to the pixel circuit, the first gate line is configured to provide a scan signal to the pixel circuit, the second gate line is configured to provide a first reset control signal to the pixel circuit, the third gate line is configured to provide a second reset control signal to the pixel circuit, the first power line is configured to provide a first voltage signal to the pixel circuit, the first initialization line is configured to provide a first initialization signal to the pixel circuit, the second initialization line is configured to provide a second initialization signal to the pixel circuit, the pixel circuit further includes a data write transistor, a first reset transistor, and a second reset transistor, the first electrode of the data write transistor is connected to the data line, the gate of the data write transistor is connected to the first gate line, and the second electrode of the data write transistor is connected to the gate of the drive transistor; the first electrode of the first reset transistor is connected to the first initialization line, and the second electrode of the first reset transistor is connected to the first reset line. The first electrode of the first reset transistor is connected to the gate of the driving transistor, and the gate of the first reset transistor is connected to the second gate line; the first electrode of the second reset transistor is connected to the second initialization line, the second electrode of the second reset transistor is connected to the first electrode of the light-emitting element, and the gate of the second reset transistor is connected to the third gate line; the first power line includes a first power signal line extending along the second direction and a first power connection line extending along the first direction, and the first power signal line is connected to the first power connection line; the first initialization line includes a first initialization signal line extending along the second direction and a first initialization connection line extending along the first direction, and the first initialization signal line is connected to the first initialization connection line; the second initialization line includes a second initialization signal line extending along the second direction and a second initialization connection line extending along the first direction, and the second initialization signal line is connected to the second initialization connection line; the orthographic projection of at least one of the first power connection line, the first initialization connection line, and the second initialization connection line on the substrate overlaps with the orthographic projection of the pixel opening of the sub-pixel on the substrate.

[0401] For example, the gate line G5 can be called the fourth gate line, and the display substrate further includes: a fourth gate line and a light-emitting control transistor, the fourth gate line is configured to provide a light-emitting control signal to the light-emitting control transistor, and the second electrode of the driving transistor is connected to the first power line through the light-emitting control transistor.

[0402] For example, the active layer of each transistor may include a source region, a drain region, and a channel located between the source region and the drain region. For example, the channel has semiconductor properties; the source region and the drain region are located on either side of the channel and may be doped with impurities, thereby having conductivity, and may serve as the first and second electrodes of the transistor, respectively. One of the first and second electrodes of the transistor is the source, and the other of the first and second electrodes of the transistor is the drain.

[0403] For example, the material used to make the semiconductor layer (semiconductor pattern) of the active layer may include an oxide semiconductor, an organic semiconductor, amorphous silicon, polycrystalline silicon, etc. For example, the oxide semiconductor includes a metal oxide semiconductor (such as indium gallium zinc oxide (IGZO)), and the polycrystalline silicon includes low-temperature polycrystalline silicon or high-temperature polycrystalline silicon, etc., and the embodiments of the present disclosure are not limited to this. It should be noted that the above-mentioned source region and drain region may be regions doped with n-type impurities or p-type impurities, and the embodiments of the present disclosure are not limited to this.

[0404] For example, the base substrate BS, the buffer layer BL, the barrier layer BR, the gate insulating layer GI, the interlayer insulating layer ILD, the planarization layer PLN, and the pixel defining layer PDL are all made of insulating materials. For example, the base substrate BS includes a flexible material such as polyimide, but is not limited thereto. At least one of the buffer layer BF, the barrier layer BR, the gate insulating layer GI, and the interlayer insulating layer ILD is made of an inorganic insulating material or an organic insulating material. For example, inorganic insulating materials include silicon oxide, silicon nitride, silicon oxynitride, etc., and organic insulating materials include resins, but are not limited thereto. For example, the pixel defining layer PDL and the planarization layer PLN can be made of organic materials, for example, organic materials include resins, but are not limited thereto.

[0405] For example, both the first conductive pattern layer LY1 and the second conductive pattern layer LY2 are made of metal materials, and the specific materials can be determined as needed. For example, the first conductive pattern layer LY1 is made of molybdenum (Mo). The second conductive pattern layer LY2 is made of titanium (Ti) and aluminum (Al), and a three-layer stacked structure of Ti / Al / Ti can be used, but is not limited to this.

[0406] For example, the material of the first electrode E1 of the light-emitting element includes a conductive material, such as, but not limited to, at least one of silver (Ag) or indium tin oxide (ITO). For example, the first electrode E1 of the light-emitting element has a three-layer stacked structure of ITO / Ag / ITO, but not limited to this. In other embodiments, the material of the first electrode E1 of the light-emitting element includes aluminum (Al) and tungsten oxide (WOx). For example, the first electrode E1 includes a stacked layer of aluminum and tungsten oxide, and the aluminum layer is closer to the substrate than the tungsten oxide layer.

[0407] For example, the material of the second electrode E2 of the light emitting element includes a conductive material, for example, silver (Ag), but is not limited thereto.

[0408] In the embodiments of the present disclosure, the patterns and vias of each single layer can be produced using a patterning process. For example, forming a specific pattern includes forming a thin film, forming a photoresist pattern on the thin film, and patterning the thin film using the photoresist pattern as a mask to form the specific pattern. The first conductive pattern layer LY1, the second conductive pattern layer LY2, the first electrode layer LY3, the third conductive pattern layer LY4, and the vias in the insulating layer can all be formed using this method. As for the active layer LY0, a semiconductor pattern can be formed first, and then doped using a doping process so that the semiconductor pattern forms an active layer including a channel, a source region, and a drain region. An insulating layer is formed on the active layer, and the first conductive pattern layer LY1 is formed on the insulating layer, and then subsequent film layers are formed in sequence.

[0409] It should be noted that the layout of the sub-pixels of a display substrate provided by the embodiment of the present disclosure is not limited to that shown in FIG5 , and can be transformed on the basis of FIG5 to form other layout diagrams. The above description is based on the pixel circuit in which the sub-pixels are 4T1C, but the embodiments of the present disclosure are not limited thereto. For example, each sub-pixel 101 can also include other numbers of transistors or other numbers of capacitors, and the pixel circuit operates under the control of the data signal transmitted through the data line, the gate scan signal transmitted through the gate line, and the light control signal provided by the light control signal line to drive the light-emitting element to emit light, thereby realizing display and other operations.

[0410] It should be noted that the embodiments of the present disclosure do not limit the number of thin film transistors and capacitors included in the pixel circuit.

[0411] The display substrate provided by the embodiment of the present disclosure may adopt other suitable layout diagrams, and the wiring method is not limited to that shown in the figure.

[0412] At least one embodiment of the present disclosure provides a display device comprising any of the above-mentioned display substrates. The display device may be a large-scale display device, wherein at least one film layer of the light-emitting functional layer is manufactured using an inkjet printing process.

[0413] For example, the display device may be an organic light emitting diode display device. The display device may be any product or component with a display function, such as a television, a digital camera, a mobile phone, a watch, a tablet computer, a laptop computer, a navigation system, etc., that includes an organic light emitting diode display device.

[0414] The above description is merely a specific embodiment of the present disclosure, but the scope of protection of the present disclosure is not limited thereto. Any changes or substitutions that can be easily conceived by a person skilled in the art within the technical scope disclosed in this disclosure should be included in the scope of protection of the present disclosure. Therefore, the scope of protection of the present disclosure should be based on the scope of protection of the claims.

Claims

1. A display substrate, comprising: A base substrate and a plurality of sub-pixels disposed on the base substrate; The sub-pixel comprises: A pixel circuit, comprising a driving transistor and a storage capacitor, wherein the storage capacitor comprises a first plate and a second plate, and the first plate of the storage capacitor is connected to the gate of the driving transistor; and a light emitting element electrically connected to the pixel circuit, wherein the pixel circuit is configured to drive the light emitting element, wherein the sub-pixel comprises a pixel opening, and the pixel opening is configured to define a light emitting area of ​​the sub-pixel, The orthographic projection of the storage capacitor on the substrate overlaps with the orthographic projection of the pixel opening on the substrate, and the orthographic projection of the channel of the driving transistor on the substrate overlaps with the orthographic projection of the pixel opening on the substrate. The display substrate satisfies the following relationship: the value range of (W*L+S2)*M1 / M2 is [0.014, 0.133], and the value range of S2 / (W*L) is [2.82, 28.85], Wherein, W is the width of the channel of the driving transistor, L is the length of the channel of the driving transistor, S2 is the facing area of ​​the second electrode plate and the first electrode plate, M1 is the number of pixel openings of the display substrate, and M2 is the area of ​​the display substrate.

2. The display substrate according to claim 1, wherein: The second electrode of the storage capacitor is connected to the first electrode of the driving transistor. The storage capacitor also includes a third electrode. The third electrode and the second electrode are connected to each other. The third electrode and the second electrode are respectively arranged on both sides of the first electrode.

3. The display substrate according to claim 1 or 2, wherein: The second electrode plate includes a first plate-shaped portion, and the first plate-shaped portion and the channel of the driving transistor are an integrated structure.

4. The display substrate according to claim 3, wherein: The second electrode plate further includes a second plate-shaped portion, the first plate-shaped portion and the second plate-shaped portion are separated from each other, the area of ​​the first plate-shaped portion is greater than the area of ​​the second plate-shaped portion, or the first plate-shaped portion and the second plate-shaped portion are both connected to the channel of the driving transistor.

5. The display substrate according to any one of claims 1 to 4, wherein: The channel of the driving transistor is made of semiconductor material, and the material of the second electrode plate is a conductor obtained by doping the semiconductor material that is the same as the channel of the driving transistor.

6. The display substrate according to any one of claims 1 to 5, wherein: The channel of the driving transistor extends along a first direction, the pixel opening has a central axis extending along the first direction, the maximum dimension of the pixel opening along a second direction is W0, the first direction intersects with the second direction, the distance from the channel of the driving transistor to the central axis is D1, and the value range of 2*D1 / W0 is [0.2, 0.4] or [0.6, 0.8].

7. The display substrate according to claim 6, further comprising a plurality of signal lines located on one side of the storage capacitor, wherein: The signal lines extend along the second direction, and the orthographic projections of the multiple signal lines on the substrate overlap with the orthographic projections of the pixel openings on the substrate, wherein a size of the pixel opening along the first direction is H0, a distance between the farthest edges of the multiple signal lines in the first direction is Hs, and a value range of L / (H0-Hs) is [0.16, 0.61].

8. The display substrate according to claim 7, further comprising a data line, a first gate line, a second gate line, and a first initialization line, wherein: The pixel circuit further includes a data writing transistor and a first reset transistor, wherein a first electrode of the data writing transistor is connected to the data line, a gate of the driving transistor is connected to a second electrode of the data writing transistor, and a gate of the data writing transistor is connected to the first gate line. The first electrode of the first reset transistor is connected to the first initialization line, the second electrode of the first reset transistor is connected to the gate of the driving transistor, and the gate of the first reset transistor is connected to the second gate line. The plurality of signal lines include the first gate line, the second gate line, and the first initialization line.

9. The display substrate according to any one of claims 1 to 4, wherein: The area of ​​the pixel opening is S0, the sum of the facing areas of the second electrode plate and the first electrode plate and the area of ​​the channel of the driving transistor is Ss, and the relationship between Ss and S0 satisfies: Ss=A*S0+B, the value range of A is [0.42, 0.82], and the value range of B is [-2700, -3100].

10. The display substrate according to claim 2, wherein: The orthographic projection of the pixel opening on the base substrate overlaps with the orthographic projection of the third electrode plate on the base substrate, The third electrode plate includes a first edge extending along a first direction and a second edge extending along the first direction, and the pixel opening includes a first edge extending along the first direction and a second edge extending along the first direction. The first edge of the third electrode plate is closer to the first edge of the pixel opening than the second edge of the third electrode plate, and the second edge of the third electrode plate is closer to the second edge of the pixel opening than the first edge of the third electrode plate. The sub-pixel satisfies the following formula: △U=|U02-U01|, U01 is the coordinate distance between the chromaticity coordinate point at the first viewing angle and the chromaticity coordinate point at the viewing angle of 0 degrees, U02 is the coordinate distance between the chromaticity coordinate point at the second viewing angle and the chromaticity coordinate point at the viewing angle of 0 degrees, △U is the absolute value of the difference between U02 and U01, the chromaticity coordinate point at the viewing angle of 0 degrees is the chromaticity coordinate point at the normal line where the center of the display substrate is located, the first viewing angle and the second viewing angle are respectively arranged on opposite sides of the normal line and have the same value of the angles with the normal line, And △U≤0.0020.

11. The display substrate according to claim 10, further comprising a first power line, wherein The first power line is configured to provide a first voltage signal to the pixel circuit, the first power line includes a first power connection line extending along a first direction and a first power signal line extending along a second direction, and an orthographic projection of the first power connection line on the base substrate overlaps with an orthographic projection of the pixel opening on the base substrate, The facing area of ​​the third electrode plate and the first electrode plate is Sc1, the overlapping area of ​​the orthographic projection of the third electrode plate on the base substrate and the orthographic projection of the pixel opening on the base substrate is Sc2, and Sc2 / Sc1≥0.9; The width of the first power connection line is W1, the overlapping width of the first power connection line and the pixel opening is W2, and W2 / W1≥0.

9.

12. The display substrate according to claim 10, wherein: The maximum size of the pixel opening along the second direction is W0, and the value range of 2×W2 / W0 is [0.71, 0.99], The value range of the cross voltage Uc / size Lg is [0.32, 0.74], the cross voltage Uc is the cross voltage of the light emitting element, the unit of the cross voltage Uc is volt, and the size Lg is the length of the diagonal of the display substrate, the unit of the size Lg is inch.

13. The display substrate according to claim 10, wherein: The pixel opening has a central axis extending along the first direction, the minimum distance from the first power connection line to the central axis is Xd1, the minimum distance from the third electrode plate to the central axis is Xd2, and the value range of Xd1 / Xd2 is [0.9, 1.1].

14. The display substrate according to claim 10, further comprising a plurality of signal lines located on one side of the storage capacitor, wherein: The orthographic projections of the multiple signal lines on the substrate overlap with the orthographic projections of the pixel opening on the substrate, the multiple signal lines are arranged along a first direction, and the signal lines extend along a second direction, wherein the first direction intersects with the second direction, the distance between the third electrode and the signal line closest to it is Xd3, the line width of the signal line is Xd4, and the value range of Xd3 / Xd4 is [0.9, 1.1].

15. The display substrate according to claim 10, further comprising a first power line, wherein The first power line is configured to provide a first voltage signal to the pixel circuit, the first power line includes a first power connection line extending along a first direction and a first power signal line extending along a second direction, the pixel opening has a central axis extending along the first direction, the minimum distance from the first power connection line to the central axis is Xd1, the minimum distance from the first power connection line to the third electrode plate is Xd0, DP=|Xd1-Xd0| / 2, the maximum size of the pixel opening along the second direction is W0, and the value range of DP / W0 is [0.01, 0.19].

16. The display substrate according to claim 10, further comprising a first signal line, wherein The first signal line extends along a first direction, the sub-pixel includes a first sub-pixel and a second sub-pixel adjacent to each other in the second direction, the first signal line is configured to provide a data signal to the pixel circuit of the first sub-pixel, the pixel opening of the first sub-pixel and the pixel opening of the second sub-pixel are spaced apart, and the first signal line is located between the pixel opening of the first sub-pixel and the pixel opening of the second sub-pixel.

17. The display substrate according to claim 16, wherein: The minimum distances between the pixel opening of the first sub-pixel and the pixel opening of the second sub-pixel and the first signal line are Xa1 and Xa2 respectively, and the value range of Xa1 / Xa2 is [0.8, 1.2].

18. The display substrate according to claim 16, further comprising a second signal line, wherein: The second signal line extends along the first direction, the first signal line and the second signal line are located on opposite sides of the same third electrode plate, and the orthographic projection of the second signal line on the base substrate overlaps with the orthographic projection of the pixel opening of the second sub-pixel on the base substrate.

19. The display substrate according to claim 18, wherein: The distance between the third electrode plate and the second signal line is Xa3, the distance between the third electrode plate and the first signal line is Xa4, and the value range of Xa3 / Xa4 is [0.8, 1.2].

20. The display substrate according to claim 18, further comprising a third signal line, wherein The third signal line extends along the first direction, The orthographic projection of the third signal line on the base substrate overlaps with the orthographic projection of the pixel opening of the first sub-pixel on the base substrate, The minimum distance between the third electrode of the first subpixel and the third signal line is Xa5, the minimum distance between the third signal line and the first signal line is Xa6, and the value range of Xa5 / Xa6 is [0.8, 1.2].

21. The display substrate according to claim 20, wherein: The first signal line includes a data line, and at least one of the second signal line and the third signal line includes a first power connection line.

22. The display substrate according to any one of claims 1 to 4, further comprising a data line and a first power line, wherein: The data line is configured to provide a data voltage to the pixel circuit, and the data line extends along a first direction. The first power line is configured to provide a first voltage signal to the pixel circuit, and the first power line includes a first power connection line extending along the first direction and a first power signal line extending along the second direction. The sub-pixels include a first sub-pixel and a second sub-pixel adjacent to each other in the second direction, and the orthographic projection of the first power connection line on the substrate overlaps with the orthographic projection of the pixel opening of the first sub-pixel on the substrate, and overlaps with the orthographic projection of the pixel opening of the second sub-pixel on the substrate.

23. The display substrate according to claim 22, wherein: Two data lines are arranged on both sides of the first power connection line, and the orthographic projections of the two data lines on the base substrate overlap with the orthographic projections of the pixel opening of the first sub-pixel and the pixel opening of the second sub-pixel on the base substrate respectively.

24. The display substrate according to claim 22, wherein: Two data lines are arranged on both sides of the first power connection line, and the orthographic projections of the two data lines on the base substrate do not overlap with the orthographic projections of the pixel opening of the first sub-pixel on the base substrate, and do not overlap with the orthographic projections of the pixel opening of the second sub-pixel on the base substrate.

25. The display substrate according to any one of claims 1 to 4, further comprising a first power line, wherein: The first power line is configured to provide a first voltage signal to the pixel circuit, the first power line includes a first power connection line extending along a first direction and a first power signal line extending along a second direction, and an orthographic projection of the first power connection line on the base substrate overlaps with an orthographic projection of the pixel opening on the base substrate, The maximum size of the pixel opening along the second direction is W0, The sub-pixels include a first sub-pixel and a second sub-pixel adjacent to each other in the second direction, The size of one of the two first power connection lines in the second direction is Xb1, and the size of the other of the two first power connection lines in the second direction is Xb2. The value range of (Xb1+Xb2) / W0 is [0.08, 0.48].

26. The display substrate according to any one of claims 1 to 4, further comprising a driving circuit, wherein: The driving circuit is located at one side of the display substrate, the sub-pixels far from the driving circuit have a first brightness L1, the sub-pixels close to the driving circuit have a second brightness L2, and the value range of |L1-L2| is [1, 9].

27. The display substrate according to any one of claims 1 to 4, further comprising two driving circuits, wherein: The two driving circuits are respectively located on opposite sides of the display area of ​​the display substrate, the sub-pixels at the central axis of the display substrate have a third brightness L3, the sub-pixels close to one of the two driving circuits have a fourth brightness L4, the extension direction of the central axis of the display substrate is the same as the extension direction of the driving circuit, and the value range of |L3-L4| is [1, 9].

28. The display substrate according to any one of claims 1 to 4, wherein: A first defining portion is provided between two adjacent pixel openings in a first direction, and a second defining portion is provided between two adjacent pixel openings in a second direction, wherein the first direction intersects the second direction; The thickness of the first limiting portion is H1, the thickness of the second limiting portion is H2, and H1≠H2.

29. The display substrate according to claim 28, wherein: H1 is smaller than H2.

30. The display substrate according to any one of claims 1 to 4, further comprising an insulating layer, a barrier dam and an encapsulation layer, wherein: The light-emitting element comprises a first electrode, a second electrode and a light-emitting functional layer located between the first electrode and the second electrode, and the first electrode of the light-emitting element is connected to the pixel circuit through a via hole penetrating the insulating layer. The encapsulation layer is configured to encapsulate the light emitting element, The encapsulation layer includes a stack of an inorganic encapsulation film and an organic encapsulation film, The outer side of the packaging layer is provided with packaging glue, The insulating layer includes a planarization layer, the planarization layer includes a first planar portion and a second planar portion, a groove is provided between the first planar portion and the second planar portion, The blocking dam is located at the periphery of the display area of ​​the display substrate, and the orthographic projection of the blocking dam on the base substrate covers the orthographic projection of the groove on the base substrate.

31. The display substrate according to any one of claims 1 to 4, further comprising a data line, a first gate line, a second gate line, and a first initialization line, wherein: The pixel circuit further includes a data writing transistor and a first reset transistor, wherein a first electrode of the data writing transistor is connected to the data line, a gate of the driving transistor is connected to a second electrode of the data writing transistor, and a gate of the data writing transistor is connected to the first gate line. The first electrode of the first reset transistor is connected to the first initialization line, the second electrode of the first reset transistor is connected to the gate of the driving transistor, and the gate of the first reset transistor is connected to the second gate line. The display substrate is provided with a dummy sub-pixel near an edge thereof, the dummy sub-pixel having a dummy drive transistor and a first dummy reset transistor, wherein the first dummy reset transistor is connected to a gate of the dummy drive transistor. The first dummy reset transistor is disconnected from the first initialization line.

32. The display substrate according to claim 31, further comprising a dummy data line, wherein The dummy data line extends along a first direction, and the dummy data line is insulated from the data line. The dummy sub-pixel includes at least two dummy sub-pixels adjacent to each other in the second direction. The dummy data lines of the at least two dummy sub-pixels are connected to each other.

33. The display substrate according to claim 32, wherein: The dummy data line is connected to a constant voltage terminal to be configured to provide a constant voltage.

34. The display substrate according to claim 31 or 32, wherein: The at least two dummy sub-pixels include a first dummy sub-pixel, a second dummy sub-pixel, and a third dummy sub-pixel, The three dummy data lines of the first dummy sub-pixel, the second dummy sub-pixel, and the third dummy sub-pixel are connected to each other.

35. The display substrate according to any one of claims 31 to 34, further comprising a first power line, wherein: The pixel circuit further includes a light emitting control transistor, a first electrode of the light emitting control transistor is connected to the first power line, a second electrode of the light emitting control transistor is connected to the second electrode of the driving transistor, The dummy sub-pixel further includes a dummy light emission control transistor, a first electrode of the dummy light emission control transistor is disconnected from the first power line, and a second electrode of the dummy light emission control transistor is connected to a second electrode of the dummy driving transistor.

36. The display substrate according to any one of claims 1 to 4, further comprising a pixel defining layer, wherein: The pixel defining layer includes a defining portion, the pixel opening is defined by the defining portion, the light emitting element includes a first electrode and a light emitting function layer, and the pixel defining layer is configured to expose at least a portion of the first electrode, The light emitting functional layer covers the side wall of the defining portion.

37. The display substrate according to claim 36, wherein: The light emitting element further includes a second electrode, the light emitting functional layer is located between the first electrode and the second electrode, and the second electrode is in contact with a top wall of the defining portion.

38. The display substrate according to claim 36, further comprising an insulating layer, wherein: The first electrode of the light-emitting element is connected to the pixel circuit through a via hole penetrating the insulating layer, the limiting portion includes a first limiting portion and a second limiting portion, the thickness of the first limiting portion is less than the thickness of the second limiting portion, and the orthographic projection of the via hole on the base substrate overlaps with the orthographic projection of the first limiting portion on the base substrate.

39. The display substrate according to claim 38, further comprising a dummy pixel defining layer, wherein: The dummy pixel defining layer includes a plurality of dummy defining portions, the extension direction of the dummy defining portions is the same as the extension direction of the second defining portions, and the spacing between two adjacent dummy defining portions is greater than the spacing between two adjacent second defining portions.

40. The display substrate according to claim 39, wherein: The distance between two adjacent dummy defining portions is 2-20 times the distance between two adjacent second defining portions.

41. The display substrate according to any one of claims 1 to 4, further comprising a second reset transistor, a second initialization line and an initialization bus, wherein: The initialization bus is arranged outside the display area of ​​the display substrate, The first electrode of the second reset transistor is connected to the initialization bus through the second initialization line, and the second electrode of the second reset transistor is connected to the light emitting element through the driving transistor. The second reset transistors are connected to a row of sub-pixels. For the same row of sub-pixels, the number of the second reset transistors is less than the number of the sub-pixels.

42. The display substrate according to claim 41, further comprising a light emission control transistor, a first power line and a first power bus, wherein: The first power line is configured to provide a first voltage signal to the pixel circuit, and the first power line is connected to the first power bus. The first electrode of the light emitting control transistor is connected to the first power line, and the second electrode of the light emitting control transistor is connected to the second electrode of the driving transistor. The number of light emission control transistors of a row of sub-pixels is smaller than the number of sub-pixels in the row.

43. The display substrate according to claim 42, wherein: The number of light emission control transistors in a row of sub-pixels is greater than the number of second reset transistors.

44. The display substrate according to any one of claims 1 to 43, wherein: The second electrode plate is arranged in the same layer as the channel of the driving transistor, the second electrode plate is closer to the base substrate than the first electrode plate, and the orthographic projection of the second electrode plate on the base substrate overlaps with the orthographic projection of the pixel opening on the base substrate.

45. A display substrate comprising: A base substrate and a plurality of sub-pixels disposed on the base substrate; The sub-pixel comprises: A pixel circuit, comprising a driving transistor and a storage capacitor, wherein the storage capacitor comprises a first plate and a second plate, the first plate of the storage capacitor is connected to the gate of the driving transistor, and the second plate of the storage capacitor is connected to the first electrode of the driving transistor; and a light emitting element electrically connected to the pixel circuit, wherein the pixel circuit is configured to drive the light emitting element, wherein the sub-pixel comprises a pixel opening, and the pixel opening is configured to define a light emitting area of ​​the sub-pixel, The orthographic projection of the storage capacitor on the substrate overlaps with the orthographic projection of the pixel opening on the substrate, and the orthographic projection of the channel of the driving transistor on the substrate overlaps with the orthographic projection of the pixel opening on the substrate. The second electrode plate is disposed in the same layer as the channel of the driving transistor, and the second electrode plate is closer to the substrate than the first electrode plate. The display substrate satisfies the following relationship: the value range of (W*L+S2)*M1 / M2 is [0.014, 0.133], and P=k0*(W / L)*Uc, wherein the value range of k0 is [2.8*E-07, 5.8*E-06], Among them, W is the width of the channel of the driving transistor, L is the length of the channel of the driving transistor, S2 is the facing area of ​​the second electrode plate and the first electrode plate, M1 is the number of pixel openings of the display substrate, M2 is the area of ​​the display substrate, Uc is the cross-voltage of the light-emitting element, and P is the power consumption of the sub-pixel.

46. ​​A display substrate comprising: A base substrate and a plurality of sub-pixels disposed on the base substrate; The sub-pixel comprises: A pixel circuit, comprising a driving transistor and a storage capacitor, wherein the storage capacitor comprises a first plate and a second plate, the first plate of the storage capacitor is connected to the gate of the driving transistor, and the second plate of the storage capacitor is connected to the first electrode of the driving transistor; and a light emitting element electrically connected to the pixel circuit, wherein the pixel circuit is configured to drive the light emitting element, wherein the sub-pixel comprises a pixel opening, and the pixel opening is configured to define a light emitting area of ​​the sub-pixel, The orthographic projection of the storage capacitor on the substrate overlaps with the orthographic projection of the pixel opening on the substrate, and the orthographic projection of the channel of the driving transistor on the substrate overlaps with the orthographic projection of the pixel opening on the substrate. The second electrode plate is disposed in the same layer as the channel of the driving transistor, and the second electrode plate is closer to the base substrate than the first electrode plate. A first defining portion is provided between two adjacent pixel openings in a first direction, and a second defining portion is provided between two adjacent pixel openings in a second direction, wherein the first direction intersects the second direction; The thickness of the first limiting portion is H1, the thickness of the second limiting portion is H2, H1≠H2; The display substrate satisfies the following relationship: the value range of S2 / (W*L) is [2.82, 28.85], Wherein, W is the width of the channel of the driving transistor, L is the length of the channel of the driving transistor, and S2 is the facing area of ​​the second electrode plate and the first electrode plate.

47. The display substrate according to claim 46, wherein: The display substrate satisfies the following relationship: the value range of (W*L+S2)*M1 / M2 is [0.014, 0.133], Wherein, M1 is the number of pixel openings of the display substrate, and M2 is the area of ​​the display substrate.

48. The display substrate according to claim 46 or 47, wherein: The display substrate satisfies the following relationship: P=k0*(W / L)*Uc, wherein the value range of k0 is [2.8*E-07, 5.8*E-06], Uc is the cross voltage of the light-emitting element, and P is the power consumption of the sub-pixel.

49. A display substrate comprising: A base substrate and a plurality of sub-pixels disposed on the base substrate; The sub-pixel comprises: A pixel circuit, comprising a driving transistor and a storage capacitor, wherein the storage capacitor comprises a first plate and a second plate, the first plate of the storage capacitor is connected to the gate of the driving transistor, and the second plate of the storage capacitor is connected to the first electrode of the driving transistor; and a light emitting element electrically connected to the pixel circuit, wherein the pixel circuit is configured to drive the light emitting element, wherein the sub-pixel comprises a pixel opening, and the pixel opening is configured to define a light emitting area of ​​the sub-pixel, The orthographic projection of the storage capacitor on the substrate overlaps with the orthographic projection of the pixel opening on the substrate, and the orthographic projection of the channel of the driving transistor on the substrate overlaps with the orthographic projection of the pixel opening on the substrate. The second electrode plate is disposed in the same layer as the channel of the driving transistor, and the second electrode plate is closer to the base substrate than the first electrode plate. The display substrate further comprises an insulating layer, a barrier dam and an encapsulation layer, wherein the light-emitting element comprises a first electrode, a second electrode and a light-emitting functional layer located between the first electrode and the second electrode, and the first electrode of the light-emitting element is connected to the pixel circuit through a via hole penetrating the insulating layer. The encapsulation layer is configured to encapsulate the light emitting element, The encapsulation layer includes a stack of an inorganic encapsulation film and an organic encapsulation film, The outer side of the packaging layer is provided with packaging glue, The insulating layer includes a planarization layer, the planarization layer includes a first planar portion and a second planar portion, a groove is provided between the first planar portion and the second planar portion, The blocking dam is located at the periphery of the display area of ​​the display substrate, and the orthographic projection of the blocking dam on the base substrate covers the orthographic projection of the groove on the base substrate; The display substrate satisfies the following relationship: the value range of S2 / (W*L) is [2.82, 28.85], Wherein, W is the width of the channel of the driving transistor, L is the length of the channel of the driving transistor, and S2 is the facing area of ​​the second electrode plate and the first electrode plate.

50. The display substrate according to claim 49, wherein: The display substrate satisfies the following relationship: the value range of (W*L+S2)*M1 / M2 is [0.014, 0.133], Wherein, M1 is the number of pixel openings of the display substrate, and M2 is the area of ​​the display substrate.

51. The display substrate according to claim 49 or 50, wherein: The display substrate satisfies the following relationship: P=k0*(W / L)*Uc, wherein the value range of k0 is [2.8*E-07, 5.8*E-06], Uc is the cross voltage of the light-emitting element, and P is the power consumption of the sub-pixel.

52. A display substrate, comprising: A base substrate and a plurality of sub-pixels disposed on the base substrate; The sub-pixel comprises: A pixel circuit, comprising a driving transistor and a storage capacitor, wherein the storage capacitor comprises a first plate and a second plate, the first plate of the storage capacitor is connected to the gate of the driving transistor, and the second plate of the storage capacitor is connected to the first electrode of the driving transistor; and a light emitting element electrically connected to the pixel circuit, wherein the pixel circuit is configured to drive the light emitting element, wherein the sub-pixel comprises a pixel opening, and the pixel opening is configured to define a light emitting area of ​​the sub-pixel, The orthographic projection of the storage capacitor on the substrate overlaps with the orthographic projection of the pixel opening on the substrate, and the orthographic projection of the channel of the driving transistor on the substrate overlaps with the orthographic projection of the pixel opening on the substrate. The second electrode plate is disposed in the same layer as the channel of the driving transistor, and the second electrode plate is closer to the base substrate than the first electrode plate. The display substrate satisfies the following relationship: the value range of S2 / (W*L) is [2.82, 28.85], Wherein, W is the width of the channel of the driving transistor, L is the length of the channel of the driving transistor, and S2 is the facing area of ​​the second electrode plate and the first electrode plate.

53. The display substrate according to claim 52, wherein: The display substrate satisfies the following relationship: the value range of (W*L+S2)*M1 / M2 is [0.014, 0.133], Wherein, M1 is the number of pixel openings of the display substrate, and M2 is the area of ​​the display substrate.

54. The display substrate according to claim 52 or 53, wherein: The display substrate satisfies the following relationship: P=k0*(W / L)*Uc, wherein the value range of k0 is [2.8*E-07, 5.8*E-06], Uc is the cross voltage of the light-emitting element, and P is the power consumption of the sub-pixel.

55. A display substrate, comprising: A base substrate and a plurality of sub-pixels disposed on the base substrate; The sub-pixel comprises: A pixel circuit, comprising a driving transistor and a storage capacitor, wherein the storage capacitor comprises a first plate and a second plate, the first plate of the storage capacitor is connected to the gate of the driving transistor, and the second plate of the storage capacitor is connected to the first electrode of the driving transistor; and a light emitting element electrically connected to the pixel circuit, wherein the pixel circuit is configured to drive the light emitting element, wherein the sub-pixel comprises a pixel opening, and the pixel opening is configured to define a light emitting area of ​​the sub-pixel, The orthographic projection of the storage capacitor on the substrate overlaps with the orthographic projection of the pixel opening on the substrate, and the orthographic projection of the channel of the driving transistor on the substrate overlaps with the orthographic projection of the pixel opening on the substrate. The second electrode plate is disposed in the same layer as the channel of the driving transistor, and the second electrode plate is closer to the base substrate than the first electrode plate. The display substrate further includes a data line, a first gate line, a second gate line, and a first initialization line, wherein the pixel circuit further includes a data writing transistor and a first reset transistor, the first electrode of the data writing transistor is connected to the data line, the gate of the driving transistor is connected to the second electrode of the data writing transistor, and the gate of the data writing transistor is connected to the first gate line, The first electrode of the first reset transistor is connected to the first initialization line, the second electrode of the first reset transistor is connected to the gate of the driving transistor, and the gate of the first reset transistor is connected to the second gate line. The display substrate is provided with a dummy sub-pixel near an edge thereof, the dummy sub-pixel having a dummy drive transistor and a first dummy reset transistor, wherein the first dummy reset transistor is connected to a gate of the dummy drive transistor. The first dummy reset transistor is disconnected from the first initialization line; The display substrate satisfies the following relationship: the value range of S2 / (W*L) is [2.82, 28.85], Wherein, W is the width of the channel of the driving transistor, L is the length of the channel of the driving transistor, and S2 is the facing area of ​​the second electrode plate and the first electrode plate.

56. The display substrate according to claim 55, wherein: The display substrate satisfies the following relationship: the value range of (W*L+S2)*M1 / M2 is [0.014, 0.133], Wherein, M1 is the number of pixel openings of the display substrate, and M2 is the area of ​​the display substrate.

57. The display substrate according to claim 55 or 56, wherein: The display substrate satisfies the following relationship: P=k0*(W / L)*Uc, wherein the value range of k0 is [2.8*E-07, 5.8*E-06], Uc is the cross voltage of the light-emitting element, and P is the power consumption of the sub-pixel.

58. A display substrate, comprising: A base substrate and a plurality of sub-pixels disposed on the base substrate; The sub-pixel comprises: A pixel circuit, comprising a driving transistor and a storage capacitor, wherein the storage capacitor comprises a first plate and a second plate, the first plate of the storage capacitor is connected to the gate of the driving transistor, and the second plate of the storage capacitor is connected to the first electrode of the driving transistor; and a light emitting element electrically connected to the pixel circuit, wherein the pixel circuit is configured to drive the light emitting element, wherein the sub-pixel comprises a pixel opening, and the pixel opening is configured to define a light emitting area of ​​the sub-pixel, The orthographic projection of the storage capacitor on the substrate overlaps with the orthographic projection of the pixel opening on the substrate, and the orthographic projection of the channel of the driving transistor on the substrate overlaps with the orthographic projection of the pixel opening on the substrate. The second electrode plate is disposed in the same layer as the channel of the driving transistor, and the second electrode plate is closer to the base substrate than the first electrode plate. The display substrate further includes a pixel defining layer, wherein the pixel defining layer includes a defining portion, the pixel opening is defined by the defining portion, the light emitting element includes a first electrode and a light emitting function layer, and the pixel defining layer is configured to expose at least a portion of the first electrode. The light-emitting functional layer covers the side wall of the defining portion, The display substrate satisfies the following relationship: the value range of S2 / (W*L) is [2.82, 28.85], Wherein, W is the width of the channel of the driving transistor, L is the length of the channel of the driving transistor, and S2 is the facing area of ​​the second electrode plate and the first electrode plate.

59. The display substrate according to claim 58, wherein: The display substrate satisfies the following relationship: the value range of (W*L+S2)*M1 / M2 is [0.014, 0.133], Wherein, M1 is the number of pixel openings of the display substrate, and M2 is the area of ​​the display substrate.

60. The display substrate according to claim 58 or 59, wherein: The display substrate satisfies the following relationship: P=k0*(W / L)*Uc, wherein the value range of k0 is [2.8*E-07, 5.8*E-06], Uc is the cross voltage of the light-emitting element, and P is the power consumption of the sub-pixel.

61. A display device comprising a display substrate according to any one of claims 1-60.

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