Communication method based on LDPC code, and communication apparatus

Abstract

Provided in the present application is a method for constructing an LDPC basis matrix. An LDPC basis matrix can be obtained according to a storage matrix and indication information, which is used for indicating correspondences between rows of the storage matrix or correspondences between rows of an expected LDPC basis matrix, and during the process of obtaining the LDPC basis matrix, it is possible not to change the total number of edges of a non-expansion column that correspond to a Tanner graph. Therefore, the method provided in the present application is conducive to maintaining the computational complexity of an LDPC code, and is particularly conducive to reducing the computational complexity of a low-code-rate LDPC code in a scenario of expansion from a high code rate to a low code rate, thereby improving the efficiency of decoding.

Description

A communication method and communication device based on LDPC code Technical Field

[0001] The present application relates to the field of channel coding, and more particularly, to a communication method and a communication device based on LDPC codes. Background Art

[0002] In the field of channel coding, low-density parity check (LDPC) codes are the most mature and widely used channel coding scheme. The high-rate portion (i.e., the core matrix) of new radio (NR) LDPC codes only supports parallel decoding of quasi-cyclic (QC) blocks, not entire rows, limiting decoding efficiency. 802.11ay LDPC codes store a separate parity check matrix for each code rate, do not support flexible code rates, and therefore do not support the incremental redundancy-hybrid automatic repeat request (IR-HARQ) mechanism.

[0003] Summary of the Invention

[0004] The embodiments of the present application provide a communication method and a communication device based on LDPC codes, which help to improve the decoding efficiency of LDPC codes.

[0005] In a first aspect, a communication method based on LDPC codes is provided. The method can be executed by a transmitter or a module or unit in the transmitter, which is collectively referred to as the transmitter below for ease of description. Optionally, the transmitter can be a terminal or a network device.

[0006] The method includes: obtaining an information bit sequence; performing LDPC encoding on the information bit sequence according to an LDPC base matrix to obtain an LDPC codeword sequence, wherein the LDPC base matrix is ​​obtained based on a storage matrix and indication information, the indication information is used to indicate the correspondence between rows of the storage matrix or the correspondence between rows of the LDPC base matrix, and the sum of the column weights of non-extended columns of the LDPC base matrix is ​​equal to the sum of the column weights of the non-extended columns of the storage matrix; and sending the LDPC codeword sequence.

[0007] Based on the above method, the LDPC base matrix can be obtained according to the storage matrix and the indication information for indicating the correspondence between the rows of the storage matrix or the correspondence between the rows of the desired LDPC base matrix, and in the process of obtaining the LDPC base matrix, the total number of edges corresponding to the non-extended columns on the Tanner graph can be unchanged. The number of edges on the Tanner graph is one of the key factors affecting the computational complexity of the LDPC code. Therefore, the method provided by the present application helps to maintain the computational complexity of the LDPC code, especially in the scenario of expanding from a high code rate to a low code rate, which helps to reduce the computational complexity of the low code rate LDPC code and improve the decoding efficiency.

[0008] In addition, the above method supports flexible code rate and thus supports IR-HARQ mechanism.

[0009] In combination with the first aspect, in some implementations of the first aspect, a code rate corresponding to the LDPC base matrix is ​​different from a code rate corresponding to the storage matrix.

[0010] Based on the above method, an LDPC base matrix with a different code rate than the storage matrix can be obtained based on the storage matrix and the indicative information indicating the correspondence between the rows of the storage matrix or the correspondence between the rows of the desired LDPC base matrix. Furthermore, in the process of obtaining the LDPC base matrix, the total number of edges corresponding to the non-extended columns on the Tanner graph can be maintained. In scenarios where code rates are being expanded from high to low rates, this method helps reduce the computational complexity of low-rate LDPC codes.

[0011] In combination with the first aspect or any implementation thereof, in some other implementations of the first aspect, the LDPC base matrix includes a first submatrix and a second submatrix, the first submatrix includes non-extended columns of the LDPC base matrix, and the second submatrix includes extended columns of the LDPC base matrix; the column weight of each column in the Q columns of the second submatrix is ​​2; one of the two non-zero elements contained in the qth column of the Q columns corresponds to the i1th row of the first submatrix, and the other of the two non-zero elements contained in the qth column of the Q columns corresponds to the i2th row of the first submatrix, the i1th row and the i2th row are orthogonal to each other, and the qth column is any column in the Q columns; wherein Q, q, i1, and i2 are all positive integers.

[0012] In other words, the degree of some or all of the extended nodes in the LDPC base matrix is ​​2, and the two rows corresponding to these extended nodes are orthogonal to each other except for the extended portion. LDPC base matrices with these characteristics can support row-parallel decoding, helping to improve decoding efficiency.

[0013] In combination with the first aspect or any implementation thereof, in some other implementations of the first aspect, the LDPC base matrix is ​​an X×Y matrix, and the y2+1 to Y columns of the LDPC base matrix are extended columns; the LDPC base matrix includes submatrix A1, submatrix B1, submatrix C1, submatrix D1 and submatrix E1, the submatrix A1 is the 1st to x1 rows and 1st to y1 columns of the LDPC base matrix, the submatrix B1 is the 1st to x1 rows and y1+1 to y2 columns of the LDPC base matrix, and the submatrix C1 is the LDPC base matrix. The submatrix D1 is the x1+1 to X rows and the y2+1 to Y columns of the LDPC base matrix, the submatrix E1 is the x1+1 to X rows and the y2+1 to Y columns of the LDPC base matrix, 1≤x1≤X, 1≤y1≤y2≤Y, and x1, X, y1, y2, and Y are all integers; wherein, the diagonal of the submatrix E1 is a non-zero element, the submatrix E1 includes non-zero elements above the diagonal and / or the submatrix E1 includes non-zero elements below the diagonal, and the submatrix C1 includes non-zero elements.

[0014] It should be noted that if the row position adjustment and / or column position adjustment are performed in the process of obtaining the LDPC base matrix based on the above method, the extended rows and / or extended columns satisfy: the X-x1 extended rows and / or Y-y2 extended columns are sorted in the splitting order, and the sorted extended rows and extended columns have the characteristics described here.

[0015] Based on the above method, submatrix C1 includes non-zero elements, which helps avoid false leveling caused by a small degree of the expanded node (i.e., the column weight of the expanded column). Furthermore, when submatrix E1 also includes non-zero elements above the diagonal, false leveling caused by a small degree of the expanded node can be further avoided.

[0016] In combination with the first aspect or any implementation thereof, in some other implementations of the first aspect, the indication information is in a form including: an indication sequence, a mapping table, or at least one of a mapping pair.

[0017] In combination with the first aspect or any implementation thereof, in some other implementations of the first aspect, the indication information is used to indicate the correspondence between rows of the LDPC basis matrix, the storage matrix is ​​used to store the connection relationship between variable nodes and check nodes, the offset values ​​of the non-zero elements of the storage matrix are obtained according to an offset value table, and the offset value table is used to store the offset values ​​of each position of the non-extended row of the storage matrix.

[0018] Based on the above method, only the offset values ​​of each position of the non-extended row of the storage matrix may be stored, that is, only the offset values ​​of each position of the core part may be stored, which helps to reduce the occupation of storage space.

[0019] In combination with the first aspect or any implementation thereof, in some other implementations of the first aspect, the indication information is in the form of an indication sequence, the LDPC base matrix is ​​obtained by reading the storage matrix and the offset value table according to the indication sequence, the indication sequence includes at least one row number, the i3th row number in the at least one row number indicates that the offset value of the i3th row of the LDPC base matrix is ​​determined based on the offset value of the row identified by the i3th row number in the at least one row number, and i3 is a positive integer.

[0020] That is, the LDPC base matrix used for encoding is obtained by reading the stored matrix and offset value table according to the indication sequence.

[0021] For example, the desired LDPC base matrix is ​​a matrix with 7 rows and 29 columns. The storage matrix stores the connection relationships between each variable node and each check node. The offset value table stores the offset values ​​for each position in the 6 rows and 28 columns of the core portion. The seventh row of the indication information is numbered 2. For the seventh row of the LDPC base matrix, the transmitter can determine the offset value for the seventh row from the offset value corresponding to the second row of the storage matrix in the offset value table based on the connection relationship of the seventh row of the storage matrix.

[0022] In combination with the first aspect or any implementation thereof, in some other implementations of the first aspect, the indication information is in the form of an indication sequence, the LDPC base matrix is ​​obtained by splitting the storage matrix according to the indication sequence, the indication sequence includes at least one row number, the m1+r-th row number in the at least one row number indicates the m1+r-th row of the LDPC base matrix, which is used to perform elimination processing on the row identified by the m1+r-th row number in the at least one row number, the sorting order of the at least one row number is the splitting order, m1 is the number of non-extended rows of the storage matrix, and r is a positive integer.

[0023] In combination with the first aspect or any implementation thereof, in some other implementations of the first aspect, the at least one row number includes at least one segment, each segment in the at least one segment corresponds to a round of splitting, and the row number in the segment corresponding to the t-th round of splitting in at least one round of splitting corresponding to the at least one segment is {1, ..., 2 t-1 m1} or {1, ..., 2 t-1 m1}, where t is a positive integer.

[0024] Based on the above method, since the row numbers of the segments corresponding to the t-th round split are {1, ..., 2 t-1m1} or {1, ..., 2 t-1 Therefore, each row number appears only once in a round of splitting, so the multiple splits included in each round can be executed in parallel, which helps to improve the splitting efficiency.

[0025] In combination with the first aspect or any implementation manner thereof, in other implementation manners of the first aspect, the storage matrix is ​​an M×N matrix, and the m1+1 to Mth rows of the storage matrix are extended rows; the storage matrix includes submatrix A2, submatrix B2, submatrix C2, submatrix D2 and submatrix E2, the submatrix A2 is the 1st to m1th rows and the 1st to n1th columns of the storage matrix, the submatrix B2 is the 1st to m1th rows and the n1+1 to n2th columns of the storage matrix, and the submatrix C2 is the 1st to m1th rows and the n2+1th columns of the storage matrix. ~N columns, the submatrix D2 is the m1+1~Mth rows and the 1~n2th columns of the storage matrix, the submatrix E2 is the m1+1~Mth rows and the n2+1~Nth columns of the storage matrix, 1≤m1≤M, 1≤n1≤n2≤N, m1, M, n1, n2, N are all integers; wherein, the a1th row of the submatrix D2 is truly included in the b1th row of the third submatrix and / or the a2th row of the submatrix D2, the third submatrix is ​​composed of the submatrix A2 and the submatrix B2, and the a1th row is any row of the submatrix D2.

[0026] In other words, the variable nodes (excluding the extended nodes) contained in the rows of the storage matrix other than the core part are truly contained in the variable nodes contained in their parent nodes.

[0027] In combination with the first aspect or any implementation thereof, in some other implementations of the first aspect, the difference between the offset value of each non-zero element in the a1-th row and the offset value of the non-zero element at the corresponding position in the b1-th row is the same, and / or the difference between the offset value of each non-zero element in the a1-th row and the offset value of the non-zero element at the corresponding position in the b1-th row is the same.

[0028] In other words, the offset values ​​of the rows of the storage matrix excluding the core part differ from the offset values ​​of the corresponding positions of their parent nodes by a fixed constant. Optionally, the constant can be 0.

[0029] In combination with the first aspect or any implementation thereof, in some other implementations of the first aspect, the multiple rows in the submatrix D2 corresponding to the b2th row of the third submatrix are different, and the b2th row is any row of the third submatrix.

[0030] Based on the above method, it helps to ensure the row weight of the core part of the storage matrix.

[0031] In combination with the first aspect or any implementation thereof, in some other implementations of the first aspect, the correspondence between the a1th row and the b1th row, and the correspondence between the a1th row and the a2th row are determined based on the indication information.

[0032] In combination with the first aspect or any implementation thereof, in some other implementations of the first aspect, the method further includes: determining the number of splits R based on the code length corresponding to the LDPC base matrix, the number of information bits corresponding to the LDPC base matrix, and the number of information columns of the LDPC base matrix; splitting the storage matrix R times to obtain the LDPC base matrix; wherein the r-th split in the R splits includes the following operations: obtaining the m1+r-th row number of the indication sequence; using the m1+r-th row of the storage matrix to perform elimination processing on the rows in the storage matrix corresponding to the m1+r-th row number; wherein m1 is the number of non-extended rows of the storage matrix, the r-th split is any one of the R splits, and r is a positive integer.

[0033] In combination with the first aspect or any implementation thereof, in some other implementations of the first aspect, the storage matrix does not include an extended column.

[0034] In other words, the sending end stores the core matrix or the high bit rate matrix.

[0035] In combination with the first aspect or any implementation thereof, in some other implementations of the first aspect, the m1+rth row of the LDPC basis matrix is ​​obtained based on the rth row of the partition table, and a row in the partition table is used to construct an extended row of the LDPC basis matrix.

[0036] In combination with the first aspect or any implementation thereof, in some other implementations of the first aspect, the method further includes: determining the number of splits R based on the code length corresponding to the LDPC base matrix, the number of information bits corresponding to the LDPC base matrix, and the number of information columns of the LDPC base matrix; splitting the storage matrix R times to obtain the LDPC base matrix; wherein the r-th split in the R splits includes the following operations: obtaining the r-th row of the partition table, and constructing the r-th extended row of the storage matrix based on the r-th row; obtaining the M+r-th row number of the indication sequence; using the r-th extended row to perform elimination processing on the k-th row, the k-th row being the row corresponding to the M+r-th row number in the storage matrix or the first r-1 extended rows of the storage matrix; wherein M is the number of rows of the storage matrix, the r-th split is any one of the R splits, and r is a positive integer.

[0037] In combination with the first aspect or any implementation thereof, in other implementations of the first aspect, R satisfies RZ c The smallest integer ≥N0-K0; where Z c is the improvement value, and Z c Z c The list satisfies KZ c The smallest Z ≥ K0 c ; N0 is the code length corresponding to the LDPC base matrix; K0 is the number of information bits corresponding to the LDPC base matrix; K is the number of information columns of the LDPC base matrix.

[0038] In combination with the first aspect or any implementation thereof, in other implementations of the first aspect, if some check bits corresponding to the last column of the LDPC basis matrix are punctured, the last split of the R splits is Z c The promoted row is used as the granularity; where Z c is the improvement value, and Z c Z c The list satisfies KZ c The smallest Z ≥ K0 c ; K0 is the number of information bits corresponding to the LDPC base matrix; K is the number of information columns of the LDPC base matrix.

[0039] Based on the above method, when it is necessary to puncture some check bits corresponding to the last column of the LDPC matrix, the basic granularity of the split can be changed from Z to c The row before promotion becomes Z c The promoted row, i.e. from Z c Change to 1 to achieve fine-grained rate matching.

[0040] In combination with the first aspect or any implementation thereof, in some other implementations of the first aspect, the indication information is in the form of an indication sequence, the LDPC base matrix is ​​obtained by merging the storage matrix according to the indication sequence, the indication sequence includes multiple sub-information, each of the multiple sub-information is used to indicate two rows to be merged in the storage matrix, and the arrangement order of the multiple sub-information is the merging order.

[0041] Optionally, the sub-information may be the number of the expansion node, and the merged row may be the row corresponding to the expansion node. The number of the expansion node may refer to the numbering of only the expansion node. For example, if the storage matrix includes 10 expansion nodes, the numbers thereof may be 1 to 10, respectively. The number of the expansion node may also refer to the numbering of all variable nodes. For example, if the storage matrix includes 28 variable nodes, including 4 expansion nodes, the numbers of the expansion nodes may be 25 to 28, respectively.

[0042] Optionally, the sub-information may be the number of the merged row. For example, when the 5th row and the 6th row of the storage matrix need to be merged, the sub-information may include the number of the 5th row and the number of the 6th row.

[0043] In combination with the first aspect or any implementation thereof, in other implementations of the first aspect, the plurality of sub-information includes at least one segment, each segment in the at least one segment corresponds to one round of merging, and the label of the extended column of the storage matrix corresponding to the sub-information included in the t-th segment in the at least one segment is {(2 T-t -1)s1+1,…,(2 T-t+1 -1)s1} or the substitution form {(2 T-t -1)s1+1,…,(2 T-t+1 -1)s1}, T is the upper bound of the number of merging rounds, s1 is the number of non-extended rows of the storage matrix, and T and t are positive integers.

[0044] Based on the above method, since the label of the expanded column of the storage matrix corresponding to the sub-information included in the t-th segment is {(2 T-t -1)s1+1,…,(2 T-t+1 -1)s1} or the substitution form {(2 T-t -1)s1+1,…,(2 T-t+1 -1)s1}, therefore, each label appears only once in a round of merging, so multiple merges included in each round can be executed in parallel, which helps to improve the merging efficiency.

[0045] In combination with the first aspect or any implementation thereof, in some other implementations of the first aspect, the storage matrix includes a fourth submatrix and a fifth submatrix, the fourth submatrix includes non-extended columns of the storage matrix, and the fifth submatrix includes extended columns of the storage matrix; the column weight of each column in the P columns of the fifth submatrix is ​​2; one of the two non-zero elements contained in the p-th column in the P columns corresponds to the j1-th row of the first submatrix, and the other of the two non-zero elements contained in the p-th column in the P columns corresponds to the j2-th row of the first submatrix, the j1-th row and the j2-th row are orthogonal to each other, and the p-th column is any column in the P columns; wherein P, p, j1, and j2 are all positive integers.

[0046] Based on the above method, the degree of some or all of the extended nodes of the storage matrix is ​​2, and the two rows corresponding to these extended nodes are orthogonal to each other except the extended part, so merging these two rows will not change the number of variables in the part of the storage matrix except the extended part.

[0047] In combination with the first aspect or any implementation thereof, in some other implementations of the first aspect, the storage matrix is ​​an S×G matrix, the s1+1 to S rows of the storage matrix are extended rows, and the g2+1 to G columns of the storage matrix are extended columns; the storage matrix includes sub-matrix A3, sub-matrix B3, sub-matrix C3, sub-matrix D3 and sub-matrix E3, the sub-matrix A3 is the 1st to s1 rows and 1st to g1 columns of the storage matrix, the sub-matrix B3 is the 1st to s1 rows and g1+1 to g2 columns of the storage matrix, and the sub-matrix C3 is the storage matrix. The storage matrix is ​​the 1st to s1th rows and the g2+1th to Gth columns, the submatrix D3 is the s1+1th to Sth rows and the 1st to g2th columns of the storage matrix, the submatrix E3 is the s1+1th to Sth rows and the g2+1th to Gth columns of the storage matrix, 1≤s1≤S, 1≤g1≤g2≤G, s1, S, g1, g2, G are all integers; wherein, the diagonal of the submatrix E3 is non-zero elements, the submatrix E3 includes non-zero elements above the diagonal and / or the submatrix E3 includes non-zero elements below the diagonal, and the submatrix C3 includes non-zero elements.

[0048] In combination with the first aspect or any implementation thereof, in some other implementations of the first aspect, the method further includes: determining the number of mergers W based on the code rate corresponding to the LDPC base matrix, the number of information columns of the LDPC base matrix, the number of non-extended rows of the storage matrix, the number of non-extended columns of the storage matrix, and the upper bound T of the number of merging rounds; merging the storage matrix W times to obtain the LDPC base matrix; wherein the w-th merger in the W splits includes the following operations: obtaining the w-th sub-information of the indication sequence; merging the two rows indicated by the w-th sub-information; wherein the w-th merger is any one of the W mergers, and w is a positive integer.

[0049] In combination with the first aspect or any implementation thereof, in other implementations of the first aspect, W satisfies wherein R0 is the code rate corresponding to the LDPC base matrix; K is the number of information columns of the LDPC base matrix; s1 is the number of non-extended rows of the storage matrix; g1 is the number of non-extended columns of the storage matrix; and T1 is the upper bound of the number of merging rounds.

[0050] In combination with the first aspect or any implementation thereof, in other implementations of the first aspect, if some check bits corresponding to the last column of the LDPC basis matrix are punctured, the last merging of the W mergings is performed with Z c The promoted row is used as the granularity; where Z c is the improvement value, and Z c Z cThe list satisfies KZ c The smallest Z ≥ K0 c ; K0 is the number of information bits corresponding to the LDPC base matrix; K is the number of information columns of the LDPC base matrix.

[0051] Based on the above method, when it is necessary to puncture some check bits corresponding to the last column of the LDPC matrix, the basic granularity of the merger can be changed from Z to c The row before promotion becomes Z c The promoted row, i.e. from Z c Change to 1 to achieve fine-grained rate matching.

[0052] In a second aspect, a communication method based on LDPC codes is provided, which can be executed by a receiving end or by a module or unit in the receiving end. Optionally, the receiving end can be a terminal or a network device.

[0053] The technical effects of the method shown in the second aspect and its possible implementation methods can be referred to the first aspect and its possible implementation methods, and will not be repeated here.

[0054] The method includes: receiving an LDPC codeword sequence from a transmitting end; and decoding the LDPC codeword sequence according to an LDPC base matrix, wherein the LDPC base matrix is ​​obtained based on a storage matrix and indication information, the indication information is used to indicate a correspondence between rows of the storage matrix or a correspondence between rows of the LDPC base matrix, and the sum of the column weights of non-extended columns of the LDPC base matrix is ​​equal to the sum of the column weights of the non-extended columns of the storage matrix.

[0055] In combination with the second aspect, in some implementations of the second aspect, a code rate corresponding to the LDPC base matrix is ​​different from a code rate corresponding to the storage matrix.

[0056] In combination with the second aspect or any implementation thereof, in some other implementations of the second aspect, the LDPC base matrix includes a first submatrix and a second submatrix, the first submatrix includes non-extended columns of the LDPC base matrix, and the second submatrix includes extended columns of the LDPC base matrix; the column weight of each column in the Q columns of the second submatrix is ​​2; one of the two non-zero elements contained in the qth column of the Q columns corresponds to the i1th row of the first submatrix, and the other of the two non-zero elements contained in the qth column of the Q columns corresponds to the i2th row of the first submatrix, the i1th row and the i2th row are orthogonal to each other, and the qth column is any column in the Q columns; wherein Q, q, i1, and i2 are all positive integers.

[0057] In combination with the second aspect or any implementation thereof, in some other implementations of the second aspect, the LDPC base matrix is ​​an X×Y matrix, and the y2+1 to Y columns of the LDPC base matrix are extended columns; the LDPC base matrix includes submatrix A1, submatrix B1, submatrix C1, submatrix D1 and submatrix E1, the submatrix A1 is the 1st to x1 rows and 1st to y1 columns of the LDPC base matrix, the submatrix B1 is the 1st to x1 rows and y1+1 to y2 columns of the LDPC base matrix, and the submatrix C1 is the LDPC base matrix. The submatrix D1 is the x1+1 to X rows and the y2+1 to Y columns of the LDPC base matrix, the submatrix E1 is the x1+1 to X rows and the y2+1 to Y columns of the LDPC base matrix, 1≤x1≤X, 1≤y1≤y2≤Y, and x1, X, y1, y2, and Y are all integers; wherein, the diagonal of the submatrix E1 is a non-zero element, the submatrix E1 includes non-zero elements above the diagonal and / or the submatrix E1 includes non-zero elements below the diagonal, and the submatrix C1 includes non-zero elements.

[0058] In combination with the second aspect or any implementation thereof, in some other implementations of the second aspect, the indication information is in a form including: an indication sequence, a mapping table, or at least one of a mapping pair.

[0059] In combination with the second aspect or any implementation thereof, in some other implementations of the second aspect, the indication information is used to indicate the correspondence between rows of the LDPC basis matrix, the storage matrix is ​​used to store the connection relationship between variable nodes and check nodes, the offset values ​​of the non-zero elements of the storage matrix are obtained according to an offset value table, and the offset value table is used to store the offset values ​​of each position of the non-extended row of the storage matrix.

[0060] In combination with the second aspect or any implementation thereof, in some other implementations of the second aspect, the indication information is in the form of an indication sequence, the LDPC base matrix is ​​obtained by reading the storage matrix and the offset value table according to the indication sequence, the indication sequence includes at least one row number, the i3th row number in the at least one row number indicates that the offset value of the i3th row of the LDPC base matrix is ​​determined based on the offset value of the row identified by the i3th row number in the at least one row number, and i3 is a positive integer.

[0061] In combination with the second aspect or any implementation thereof, in some other implementations of the second aspect, the indication information is in the form of an indication sequence, the LDPC base matrix is ​​obtained by splitting the storage matrix according to the indication sequence, the indication sequence includes at least one row number, the m1+rth row number in the at least one row number indicates the m1+rth row of the LDPC base matrix, which is used to perform elimination processing on the row identified by the m1+rth row number in the at least one row number, the sorting order of the at least one row number is the splitting order, m1 is the number of non-extended rows of the storage matrix, and r is a positive integer.

[0062] In combination with the second aspect or any implementation thereof, in some other implementations of the second aspect, the at least one row number includes at least one segment, each segment in the at least one segment corresponds to a round of splitting, and the row number in the segment corresponding to the t-th round of splitting in at least one round of splitting corresponding to the at least one segment is {1, ..., 2 t-1 m1} or {1, ..., 2 t-1 m1}, where t is a positive integer.

[0063] In combination with the second aspect or any implementation thereof, in some other implementations of the second aspect, the storage matrix is ​​an M×N matrix, and the m1+1 to Mth rows of the storage matrix are extended rows; the storage matrix includes submatrix A2, submatrix B2, submatrix C2, submatrix D2 and submatrix E2, the submatrix A2 is the 1st to m1th rows and the 1st to n1th columns of the storage matrix, the submatrix B2 is the 1st to m1th rows and the n1+1 to n2th columns of the storage matrix, and the submatrix C2 is the 1st to m1th rows and the n2+1th columns of the storage matrix. ~N columns, the submatrix D2 is the m1+1~Mth rows and the 1~n2th columns of the storage matrix, the submatrix E2 is the m1+1~Mth rows and the n2+1~Nth columns of the storage matrix, 1≤m1≤M, 1≤n1≤n2≤N, m1, M, n1, n2, N are all integers; wherein, the a1th row of the submatrix D2 is truly included in the b1th row of the third submatrix and / or the a2th row of the submatrix D2, the third submatrix is ​​composed of the submatrix A2 and the submatrix B2, and the a1th row is any row of the submatrix D2.

[0064] In combination with the second aspect or any implementation thereof, in some other implementations of the second aspect, the difference between the offset value of each non-zero element in the a1-th row and the offset value of the non-zero element at the corresponding position in the b1-th row is the same, and / or the difference between the offset value of each non-zero element in the a1-th row and the offset value of the non-zero element at the corresponding position in the b1-th row is the same.

[0065] In combination with the second aspect or any implementation thereof, in some other implementations of the second aspect, the multiple rows in the submatrix D2 corresponding to the b2th row of the third submatrix are different, and the b2th row is any row of the third submatrix.

[0066] In combination with the second aspect or any implementation thereof, in some other implementations of the second aspect, the correspondence between the a1th row and the b1th row, and the correspondence between the a1th row and the a2th row are determined based on the indication information.

[0067] In combination with the second aspect or any implementation thereof, in some other implementations of the second aspect, the method further includes: determining the number of splits R based on the code length corresponding to the LDPC base matrix, the number of information bits corresponding to the LDPC base matrix, and the number of information columns of the LDPC base matrix; splitting the storage matrix R times to obtain the LDPC base matrix; wherein the r-th split in the R splits includes the following operations: obtaining the m1+r-th row number of the indication sequence; using the m1+r-th row of the storage matrix to perform elimination processing on the rows in the storage matrix corresponding to the m1+r-th row number; wherein m1 is the number of non-extended rows of the storage matrix, the r-th split is any one of the R splits, and r is a positive integer.

[0068] In combination with the second aspect or any implementation thereof, in some other implementations of the second aspect, the storage matrix does not include an extended column.

[0069] In combination with the second aspect or any implementation thereof, in some other implementations of the second aspect, the m1+rth row of the LDPC basis matrix is ​​obtained based on the rth row of the partition table, and a row in the partition table is used to construct an extended row of the LDPC basis matrix.

[0070] In combination with the second aspect or any implementation thereof, in some other implementations of the second aspect, the method further includes: determining the number of splits R based on the code length corresponding to the LDPC base matrix, the number of information bits corresponding to the LDPC base matrix, and the number of information columns of the LDPC base matrix; splitting the storage matrix R times to obtain the LDPC base matrix; wherein the r-th split in the R splits includes the following operations: obtaining the r-th row of the partition table, and constructing the r-th extended row of the storage matrix based on the r-th row; obtaining the M+r-th row number of the indication sequence; using the r-th extended row to perform elimination processing on the k-th row, the k-th row being the row corresponding to the M+r-th row number in the storage matrix or the first r-1 extended rows of the storage matrix; wherein M is the number of rows of the storage matrix, the r-th split is any one of the R splits, and r is a positive integer.

[0071] In combination with the second aspect or any implementation thereof, in other implementations of the second aspect, R satisfies RZ c The smallest integer ≥N0-K0; where Z c is the improvement value, and Z c Z c The list satisfies KZ c The smallest Z ≥ K0 c ; N0 is the code length corresponding to the LDPC base matrix; K0 is the number of information bits corresponding to the LDPC base matrix; K is the number of information columns of the LDPC base matrix.

[0072] In combination with the second aspect or any implementation thereof, in other implementations of the second aspect, if some check bits corresponding to the last column of the LDPC basis matrix are punctured, the last split of the R splits is Z c The promoted row is used as the granularity; where Z c is the improvement value, and Z c Z c The list satisfies KZ c The smallest Z ≥ K0 c ; K0 is the number of information bits corresponding to the LDPC base matrix; K is the number of information columns of the LDPC base matrix.

[0073] In combination with the second aspect or any implementation thereof, in some other implementations of the second aspect, the indication information is in the form of an indication sequence, the LDPC base matrix is ​​obtained by merging the storage matrix according to the indication sequence, the indication sequence includes multiple sub-information, each of the multiple sub-information is used to indicate two rows to be merged in the storage matrix, and the arrangement order of the multiple sub-information is the merging order.

[0074] In combination with the second aspect or any implementation thereof, in other implementations of the second aspect, the plurality of sub-information includes at least one segment, each segment in the at least one segment corresponds to one round of merging, and the label of the extended column of the storage matrix corresponding to the sub-information included in the t-th segment in the at least one segment is {(2 T-t -1)s1+1,…,(2 T-t+1 -1)s1} or the substitution form {(2 T-t -1)s1+1,…,(2 T-t+1 -1)s1}, T is the upper bound of the number of merging rounds, s1 is the number of non-extended rows of the storage matrix, and T and t are positive integers.

[0075] In combination with the second aspect or any implementation thereof, in some other implementations of the second aspect, the storage matrix includes a fourth submatrix and a fifth submatrix, the fourth submatrix includes non-extended columns of the storage matrix, and the fifth submatrix includes extended columns of the storage matrix; the column weight of each column in the P columns of the fifth submatrix is ​​2; one of the two non-zero elements contained in the p-th column in the P columns corresponds to the j1-th row of the first submatrix, and the other of the two non-zero elements contained in the p-th column in the P columns corresponds to the j2-th row of the first submatrix, the j1-th row and the j2-th row are orthogonal to each other, and the p-th column is any column in the P columns; wherein P, p, j1, and j2 are all positive integers.

[0076] In combination with the second aspect or any implementation thereof, in some other implementations of the second aspect, the storage matrix is ​​an S×G matrix, the s1+1 to S rows of the storage matrix are extended rows, and the g2+1 to G columns of the storage matrix are extended columns; the storage matrix includes sub-matrix A3, sub-matrix B3, sub-matrix C3, sub-matrix D3 and sub-matrix E3, the sub-matrix A3 is the 1st to s1 rows and 1st to g1 columns of the storage matrix, the sub-matrix B3 is the 1st to s1 rows and g1+1 to g2 columns of the storage matrix, and the sub-matrix C3 is the storage matrix. The storage matrix is ​​the 1st to s1th rows and the g2+1th to Gth columns, the submatrix D3 is the s1+1th to Sth rows and the 1st to g2th columns of the storage matrix, the submatrix E3 is the s1+1th to Sth rows and the g2+1th to Gth columns of the storage matrix, 1≤s1≤S, 1≤g1≤g2≤G, s1, S, g1, g2, G are all integers; wherein, the diagonal of the submatrix E3 is non-zero elements, the submatrix E3 includes non-zero elements above the diagonal and / or the submatrix E3 includes non-zero elements below the diagonal, and the submatrix C3 includes non-zero elements.

[0077] In combination with the second aspect or any implementation thereof, in some other implementations of the second aspect, the method further includes: determining the number of mergers W based on the code rate corresponding to the LDPC base matrix, the number of information columns of the LDPC base matrix, the number of non-extended rows of the storage matrix, the number of non-extended columns of the storage matrix, and the upper bound T of the number of merging rounds; merging the storage matrix W times to obtain the LDPC base matrix; wherein the w-th merger in the W splits includes the following operations: obtaining the w-th sub-information of the indication sequence; merging the two rows indicated by the w-th sub-information; wherein the w-th merger is any one of the W mergers, and w is a positive integer.

[0078] In combination with the second aspect or any implementation thereof, in some other implementations of the second aspect, W satisfies wherein R0 is the code rate corresponding to the LDPC base matrix; K is the number of information columns of the LDPC base matrix; s1 is the number of non-extended rows of the storage matrix; g1 is the number of non-extended columns of the storage matrix; and T1 is the upper bound of the number of merging rounds.

[0079] In combination with the second aspect or any implementation thereof, in other implementations of the second aspect, if some check bits corresponding to the last column of the LDPC basis matrix are punctured, the last merging of the W mergings is performed with Z c The promoted row is used as the granularity; where Z c is the improvement value, and Z c Z c The list satisfies KZ c The smallest Z ≥ K0 c ; K0 is the number of information bits corresponding to the LDPC base matrix; K is the number of information columns of the LDPC base matrix.

[0080] In one possible implementation, a receiving end performs channel decoding on an LDPC codeword sequence based on an LDPC base matrix, including: employing a first decoding method to decode the row corresponding to the i1th row and the row corresponding to the i2th row in the LDPC codeword sequence; and employing a second decoding method to decode the row corresponding to the i1th row of the second submatrix and the row corresponding to the i2th row in the second submatrix in the LDPC codeword sequence. The first decoding method is row-parallel decoding, and the second decoding method is different from the first decoding method.

[0081] In other words, for the i1th row and the i2th row of the LDPC basis matrix, the first decoding method (i.e., row parallel decoding) is used for the positions in these two rows except the extended nodes, and the second decoding method is used for the positions corresponding to the extended nodes in these two rows.

[0082] A possible implementation method is to take the i1th row and the i2th row of the LDPC base matrix as an example, assuming that the i1th row corresponds to the first check node and the i2th row corresponds to the second extended node. For the first extended node corresponding to the i1th row and the i2th row (the corresponding relationship can be as described in Feature 2), the following decoding operation can be performed: obtain the first information stored in the first extended node and the second information stored in the first check node, wherein the first information is the information sent by the first extended node to the first check node during the last decoding iteration, and the second information is the information sent by the first check node to the first extended node during the last decoding iteration; obtain the third information stored in the second check node, wherein the third information is information sent by the second check node to the first extended node during the previous decoding iteration; determining fourth information based on the first information, the second information, and the third information, and storing the fourth information in the second check node, where the fourth information is the information sent by the second check node to the first extended node during the current decoding iteration; determining fifth information based on the fourth information and the first information, and storing fifth information in the first extended node, where the fifth information is the information sent by the first extended node to the first check node during the current decoding iteration; determining sixth information based on the fourth information, and storing the sixth information in the first check node, where the sixth information is the information sent by the first check node to the first extended node during the current decoding iteration.

[0083] In the above decoding process, in addition to being used to update the storage of the second check node, the information sent by the second check node to the first extension node during the current decoding iteration can also be directly used, without storage, to calculate the information sent by the first extension node to the first check node during the current decoding iteration and the information sent by the first check node to the first extension node during the current decoding iteration. In this way, decoding can be performed without error, which can reduce the number of times the first extension node, the first check node, and the second check node are read and updated.

[0084] In a third aspect, a communication method based on LDPC codes is provided. The method can be executed by a transmitter or a module or unit in the transmitter. For ease of description, the transmitter is collectively referred to as the transmitter below. Optionally, the transmitter can be a terminal or a network device.

[0085] The method includes: obtaining an information bit sequence; performing LDPC encoding on the information bit sequence according to a storage matrix to obtain a first LDPC codeword sequence, wherein the storage matrix includes a fourth submatrix and a fifth submatrix, the fourth submatrix includes non-extended columns of the storage matrix, and the fifth submatrix includes extended columns of the storage matrix; each of P columns in the fifth submatrix has a column weight of 2; one of two non-zero elements contained in the p-th column in the P columns corresponds to the j1-th row of the first submatrix, the other of the two non-zero elements contained in the p-th column in the P columns corresponds to the j2-th row of the first submatrix, the j1-th row and the j2-th row are mutually orthogonal, and the p-th column is any column in the P columns; wherein P, p, j1, and j2 are all positive integers; and sending a second LDPC codeword sequence according to indication information, wherein the indication information is used to indicate punctured columns in the fifth submatrix, and the second LDPC codeword sequence includes codewords in the first LDPC codeword sequence except for codewords corresponding to the punctured columns in the fifth submatrix.

[0086] The LDPC base matrix may be a matrix stored at the transmitter, that is, a storage matrix. The matrix may be a check matrix with the lowest code rate.

[0087] Based on the above method, the degree of some or all of the extended nodes in the LDPC base matrix is ​​2, and the two rows corresponding to these extended nodes are mutually orthogonal, excluding the extended portions. Therefore, puncturing these extended nodes can be used to achieve a merge effect, thereby achieving a higher bit rate from a low bit rate. Furthermore, since the two rows corresponding to these extended nodes are mutually orthogonal, merging these two rows does not change the number of variables in the LDPC base matrix excluding the extended portions.

[0088] In addition, the method supports flexible code rates and thus supports the IR-HARQ mechanism.

[0089] In addition, since the code rate is changed by puncturing, the LDPC base matrix used does not change, so the computing units used for encoding and decoding at the transmitting and receiving ends can be fixed.

[0090] In combination with the third aspect, in some implementations of the third aspect, the storage matrix is ​​an S×G matrix, the s1+1 to S rows of the storage matrix are extended rows, and the g2+1 to G columns of the storage matrix are extended columns; the storage matrix includes sub-matrix A3, sub-matrix B3, sub-matrix C3, sub-matrix D3 and sub-matrix E3, the sub-matrix A3 is the 1st to s1 rows and the 1st to g1 columns of the storage matrix, the sub-matrix B3 is the 1st to s1 rows and the g1+1 to g2 columns of the storage matrix, and the sub-matrix C3 is the The 1st to s1th rows and the g2+1th to Gth columns, the submatrix D3 is the s1+1th to Sth rows and the 1st to g2th columns of the storage matrix, the submatrix E3 is the s1+1th to Sth rows and the g2+1th to Gth columns of the storage matrix, 1≤s1≤S, 1≤g1≤g2≤G, s1, S, g1, g2, G are all integers; wherein, the diagonal of the submatrix E3 is a non-zero element, the submatrix E3 includes non-zero elements above the diagonal and / or the submatrix E3 includes non-zero elements below the diagonal, and the submatrix C3 includes non-zero elements.

[0091] In combination with the third aspect or any implementation thereof, in some other implementations of the third aspect, the indication information is in a form including: an indication sequence, a mapping table, or at least one of a mapping pair.

[0092] In combination with the third aspect or any implementation thereof, in some other implementations of the third aspect, the indication information is in the form of an indication sequence, the indication sequence includes multiple sub-information, each of the multiple sub-information is used to indicate a column in the extended column of the storage matrix, and the arrangement order of the multiple sub-information is the punching order.

[0093] Optionally, the sub-information may be the number of the expansion node. The number of the expansion node may refer to the numbering of only the expansion nodes. For example, if the storage matrix includes 10 expansion nodes, the numbers thereof may be 1 to 10. The number of the expansion node may also refer to the numbering of all variable nodes. For example, if the storage matrix includes 28 variable nodes, including 4 expansion nodes, the numbers of the expansion nodes may be 25 to 28.

[0094] In combination with the third aspect or any implementation thereof, in other implementations of the third aspect, the plurality of sub-information includes at least one segment, each segment in the at least one segment corresponds to a round of puncturing, and the label of the extended column indicated by the sub-information included in the t-th segment in the at least one segment is {(2 T-t -1)s1+1,…,2 T-t+1 -1)s1} or the substitution form {(2 T-t -1)s1+1,…,2T-t+1 -1)s1}, T is the upper bound of the number of merging rounds, s1 is the number of non-extended rows of the storage matrix, and T and t are positive integers.

[0095] Based on the above method, since the number of the extended column corresponding to the sub-information included in the t-th segment is {(2 T-t -1)s1+1,…,(2 T-t+1 -1)s1} or the substitution form {(2 T-t -1)s1+1,…,(2 T-t+1 -1)s1}, therefore, each label appears only once in a round of puncturing, so the multiple puncturing included in each round can be executed in parallel, which helps to improve the puncturing efficiency.

[0096] In combination with the third aspect or any implementation thereof, in some other implementations of the third aspect, the number J of sub-information included in the indication sequence satisfies wherein R0 is the target bit rate; K is the target number of information columns; s1 is the number of non-extended rows of the storage matrix; g2 is the number of non-extended columns of the storage matrix; and T2 is the upper bound of the number of merging rounds.

[0097] In a fourth aspect, a communication method based on LDPC codes is provided, which can be executed by a receiving end or by a module or unit in the receiving end. Optionally, the receiving end can be a terminal or a network device.

[0098] The technical effects of the method shown in the fourth aspect and its possible implementation methods can be referred to the third aspect and its possible implementation methods, and will not be repeated here.

[0099] The method includes: receiving an LDPC codeword sequence from a transmitting end; decoding the LDPC codeword sequence according to a storage matrix and indication information, wherein the storage matrix includes a fourth submatrix and a fifth submatrix, the fourth submatrix includes non-extended columns of the storage matrix, and the fifth submatrix includes extended columns of the storage matrix; each of P columns in the fifth submatrix has a column weight of 2; one of two non-zero elements contained in the p-th column in the P columns corresponds to the j1-th row of the first submatrix, the other of the two non-zero elements contained in the p-th column in the P columns corresponds to the j2-th row of the first submatrix, the j1-th row and the j2-th row are mutually orthogonal, the p-th column is any column in the P columns, and P, p, j1, and j2 are all positive integers; the indication information is used to indicate a punctured column in the fifth submatrix, and the second LDPC codeword sequence includes codewords in the first LDPC codeword sequence except for codewords corresponding to the punctured columns in the fifth submatrix.

[0100] In combination with the fourth aspect, in some implementations of the fourth aspect, the storage matrix is ​​an S×G matrix, the s1+1 to S rows of the storage matrix are extended rows, and the g2+1 to G columns of the storage matrix are extended columns; the storage matrix includes sub-matrix A3, sub-matrix B3, sub-matrix C3, sub-matrix D3 and sub-matrix E3, the sub-matrix A3 is the 1st to s1 rows and the 1st to g1 columns of the storage matrix, the sub-matrix B3 is the 1st to s1 rows and the g1+1 to g2 columns of the storage matrix, and the sub-matrix C3 is the The 1st to s1th rows and the g2+1th to Gth columns, the submatrix D3 is the s1+1th to Sth rows and the 1st to g2th columns of the storage matrix, the submatrix E3 is the s1+1th to Sth rows and the g2+1th to Gth columns of the storage matrix, 1≤s1≤S, 1≤g1≤g2≤G, s1, S, g1, g2, G are all integers; wherein, the diagonal of the submatrix E3 is a non-zero element, the submatrix E3 includes non-zero elements above the diagonal and / or the submatrix E3 includes non-zero elements below the diagonal, and the submatrix C3 includes non-zero elements.

[0101] In combination with the fourth aspect or any implementation thereof, in some other implementations of the fourth aspect, the indication information is in a form including: an indication sequence, a mapping table, or at least one of a mapping pair.

[0102] In combination with the fourth aspect or any implementation thereof, in some other implementations of the fourth aspect, the indication information is in the form of an indication sequence, the indication sequence includes multiple sub-information, each of the multiple sub-information is used to indicate a column in the extended column of the storage matrix, and the arrangement order of the multiple sub-information is the punching order.

[0103] In combination with the fourth aspect or any implementation thereof, in other implementations of the fourth aspect, the plurality of sub-information includes at least one segment, each segment in the at least one segment corresponds to a round of puncturing, and the label of the extension column indicated by the sub-information included in the t-th segment in the at least one segment is {(2 T-t -1)s1+1,…,2 T-t+1 -1)s1} or the substitution form {(2 T-t -1)s1+1,…,2 T-t+1 -1)s1}, T is the upper bound of the number of merging rounds, s1 is the number of non-extended rows of the storage matrix, and T and t are positive integers.

[0104] In combination with the fourth aspect or any implementation thereof, in some other implementations of the fourth aspect, the number J of sub-information included in the indication sequence satisfies wherein R0 is the target bit rate; K is the target number of information columns; s1 is the number of non-extended rows of the storage matrix; g2 is the number of non-extended columns of the storage matrix; and T2 is the upper bound of the number of merging rounds.

[0105] In a fifth aspect, a communication device is provided, which is configured to execute the method provided by any of the above aspects or implementations thereof. Specifically, the device may include units and / or modules, such as a processing unit and / or a communication unit, configured to execute the method provided by any of the above aspects or implementations thereof.

[0106] In one implementation, the device is a transmitter or receiver. When the device is a transmitter or receiver, the communication unit may be a transceiver, an input / output interface, or a communication interface; and the processing unit may be at least one processor. Optionally, the transceiver is a transceiver circuit. Optionally, the input / output interface is an input / output circuit.

[0107] In another implementation, the device is a chip, chip system, or circuit used in a transmitter or receiver. When the device is a chip, chip system, or circuit used in a transmitter or receiver, the communication unit may be an input / output interface, interface circuit, output circuit, input circuit, pin, or related circuit on the chip, chip system, or circuit; and the processing unit may be at least one processor, processing circuit, or logic circuit.

[0108] In a sixth aspect, a communication device is provided, which includes: a memory for storing programs; and at least one processor for executing computer programs or instructions stored in the memory to execute the method provided by any one of the above aspects or its implementation.

[0109] In one implementation, the device is a transmitting end or a receiving end.

[0110] In another implementation, the device is a chip, a chip system, or a circuit used in a transmitting end or a receiving end.

[0111] In a seventh aspect, a communication device is provided, comprising: at least one processor and a communication interface, wherein the at least one processor is configured to retrieve a computer program or instruction stored in a memory through the communication interface to execute the method provided by any one of the above aspects or implementations thereof. The communication interface may be implemented in hardware or software.

[0112] In one implementation, the device further includes the memory.

[0113] In an eighth aspect, a processor is provided for executing the methods provided in the above aspects.

[0114] For the operations such as sending and acquiring / receiving involved in the processor, unless otherwise specified, or if they do not conflict with their actual functions or internal logic in the relevant descriptions, they can be understood as operations such as processor output, reception, and input, or as sending and receiving operations performed by the radio frequency circuit and antenna. This application does not limit this.

[0115] In a ninth aspect, a computer-readable storage medium is provided, which stores a program code for execution by a device, wherein the program code includes a method for executing any one of the above aspects or its implementation.

[0116] In a tenth aspect, a computer program product comprising instructions is provided, which, when run on a computer, enables the computer to execute the method provided by any one of the above aspects or its implementation.

[0117] In an eleventh aspect, a chip is provided, comprising a processor and a communication interface, wherein the processor reads instructions stored in a memory through the communication interface and executes the method provided by any of the above aspects or implementations thereof. The communication interface may be implemented in hardware or software.

[0118] Optionally, as an implementation method, the chip also includes a memory, in which a computer program or instruction is stored, and the processor is used to execute the computer program or instruction stored in the memory. When the computer program or instruction is executed, the processor is used to execute the method provided by any of the above aspects or its implementation methods.

[0119] When the method provided in this application is executed by a chip, this application does not limit the number of chips that implement the method. For example, the method can be executed by one chip or by two or more chips. Furthermore, when the number of chips implementing the method of this application is two or more, the chip manufacturers are not limited and can be the same manufacturer or different manufacturers.

[0120] In a twelfth aspect, a communication system is provided, comprising the above-mentioned transmitting end and / or receiving end.

[0121] In a thirteenth aspect, a computer program is provided, which, when executed on a computer, enables the method provided by any one of the above aspects or its implementation to be executed. BRIEF DESCRIPTION OF THE DRAWINGS

[0122] FIG1 is a schematic diagram of a communication scenario applicable to an embodiment of the present application.

[0123] FIG2 is a schematic diagram of the LDPC check matrix H.

[0124] FIG3 is a Tanner graph of the LDPC check matrix H.

[0125] Figure 4 is a schematic diagram of the structure of the LDPC parity check matrix of 5G NR.

[0126] FIG5 is a schematic diagram of the information transmission process.

[0127] FIG6 is a schematic flowchart of a communication method 600 based on LDPC codes provided in this application.

[0128] FIG7 is an example of an LDPC base matrix.

[0129] FIG8 is a schematic diagram of one splitting of a high-rate matrix.

[0130] FIG9 is a schematic diagram of a progressive splitting method.

[0131] FIG10 is a schematic diagram of a complete 2-round splitting of a high-rate matrix.

[0132] FIG11 is a schematic diagram of a split sequence.

[0133] FIG12 is a schematic diagram showing the correspondence between the partition table and the split sequence.

[0134] FIG13 is an example of a partition table.

[0135] FIG14 is a schematic diagram of 1 split.

[0136] FIG15 is another schematic diagram of 1 split.

[0137] FIG16 is a schematic diagram of fine-grained rate matching.

[0138] FIG17 is a schematic diagram of one merge.

[0139] FIG18 is a schematic flowchart of a communication method 1800 based on LDPC codes provided in the present application.

[0140] FIG19 is a schematic structural diagram of the device provided in an embodiment of the present application.

[0141] FIG20 is another schematic structural diagram of the device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0142] To facilitate understanding of the embodiments of the present application, the following points are explained before introducing the embodiments of the present application.

[0143] In this application, "used to indicate" or "indicate" can include direct indication and indirect indication, or "used to indicate" or "indicate" can indicate explicitly and / or implicitly. For example, when describing that a certain information is used to indicate information I, it can include that the information directly indicates I or indirectly indicates I, but it does not mean that the information necessarily carries I. For another example, implicit indication can be based on the location and / or resources used for transmission; explicit indication can be based on one or more parameters, and / or one or more indexes, and / or one or more bit patterns represented by it.

[0144] The definitions of many characteristics listed in this application are only used to explain the functions of the characteristics by way of example. For details, please refer to the prior art.

[0145] In the embodiments shown below, the first, second, third, fourth, and various numbers are only used for the convenience of description and are not intended to limit the scope of the embodiments of the present application. For example, they are used to distinguish different fields, different information, etc.

[0146] "Pre-definition" can be achieved by pre-storing corresponding codes, tables, or other methods that can be used to indicate relevant information in the device. This application does not limit the specific implementation method. Here, "storage" can mean storing in one or more memories. The type of memory can be any form of storage medium, which is not limited by this application.

[0147] The “protocol” involved in the embodiments of the present application may refer to a standard protocol in the field of communications, for example, it may include a long term evolution (LTE) protocol, a new radio (NR) protocol, and related protocols used in future communication systems, which are not limited in this application.

[0148] This application will present various aspects, embodiments, or features around systems including multiple devices, components, modules, etc. It should be understood and appreciated that each system may include additional devices, components, modules, etc., and / or may not include all of the devices, components, modules, etc. discussed in conjunction with the figures. Furthermore, combinations of these aspects may also be used.

[0149] In the embodiments of this application, words such as "exemplary," "for example," "illustratively," and "as another example" are used to indicate examples, illustrations, or descriptions. Any embodiment or design described as an "exemplary" in this application should not be construed as being preferred or advantageous over other embodiments or designs. Rather, the use of the word "exemplary" is intended to present concepts in a concrete manner.

[0150] The terms "include", "comprising", "having" and variations thereof mean "including but not limited to", unless specifically emphasized otherwise.

[0151] "At least one" means one or more, and "more" means two or more. "And / or" describes the association relationship of associated objects, indicating that three relationships may exist. For example, A and / or B can mean: A exists alone, A and B exist at the same time, and B exists alone, where A and B can be singular or plural. The character " / " generally indicates that the previous and next associated objects are in an "or" relationship. "At least one of the following items" or similar expressions refers to any combination of these items, including any combination of single items or plural items. For example, at least one of a, b and c can mean: a, or b, or c, or a and b, or a and c, or b and c, or a, b and c. Where a, b and c can be single or multiple, respectively.

[0152] In the embodiments of the present application, the descriptions of network element A sending a message, information or data to network element B, and network element B receiving a message, information or data from network element A are intended to illustrate to which network element the message, information or data is to be sent, but do not limit whether they are sent directly or indirectly via other network elements.

[0153] In the embodiments of the present application, descriptions such as "when...", "in the case of...", "if" and "if" all mean that the device will perform corresponding processing under certain objective circumstances. It does not limit the time, nor does it require the device to perform judgment actions when implemented, nor does it mean that there are other limitations.

[0154] The technical solutions of the embodiments of the present application can be applied to various communication systems, including but not limited to: fifth generation (5G) system or NR system, LTE system, long term evolution-advanced (LTE-A) system, LTE frequency division duplex (FDD) system, LTE time division duplex (TDD) system, etc. It can also be applied to future communication systems, such as the sixth generation mobile communication system. In addition, it can also be applied to device to device (D2D) communication, vehicle-to-everything (V2X) communication, machine to machine (M2M) communication, machine type communication (MTC), and Internet of Things (IoT) communication system or other communication systems, etc. In addition, the present invention can also be extended to similar wireless communication systems, such as wireless-fidelity (WiFi), worldwide interoperability for microwave access (WIMAX), and communication systems related to the 3rd Generation Partnership Project (3GPP), without limitation.

[0155] A communication system applicable to the present application may include one or more transmitting ends and one or more receiving ends. Optionally, one of the transmitting end and the receiving end may be a terminal, and the other may be a network device. Optionally, both the transmitting end and the receiving end may be terminals. Optionally, both the transmitting end and the receiving end may be network devices.

[0156] Exemplarily, FIG1 is a schematic diagram of a communication scenario applicable to an embodiment of the present application.

[0157] As shown in Figure 1, the embodiments of the present application are applicable to both uplink data transmission and downlink data transmission. Figure 1 only takes uplink data transmission or downlink data transmission between a network device and two terminals (such as terminal 1 and terminal 2) as an example. In uplink data transmission, the transmitting end in this article is the terminal and the receiving end is the network device; conversely, in downlink data transmission, the transmitting end is the network device and the receiving end is the terminal. In addition, the applicability of the embodiments of the present application in other communication scenarios is not limited. For example, it can also be applied to sidelink communication.

[0158] The terminal of the present application may also be referred to as user equipment (UE), access terminal, user unit, user station, mobile station, mobile station, mobile terminal (MT), remote station, remote terminal, mobile device, user terminal, terminal device, drone, wireless communication device, user agent or user device. The terminal device in the embodiments of the present application can be a device that provides voice and / or data connectivity to the user and can be used to connect people, objects and machines, such as a handheld device with wireless connection function, a vehicle-mounted device, etc. The terminal device in the embodiments of the present application can be a mobile phone, a tablet computer, a laptop computer, a PDA, a mobile internet device (MID), a wearable device, a virtual reality (VR) device, an augmented reality (AR) device, a wireless terminal in industrial control, a wireless terminal in self-driving, a wireless terminal in remote medical surgery, a wireless terminal in a smart grid, a wireless terminal in transportation safety, a wireless terminal in a smart city, a wireless terminal in a smart home, etc.

[0159] The network device of the present application may be a device with wireless transceiver functions, and the network device may be a device that provides wireless communication function services, usually located on the network side, including but not limited to the next-generation base station (gNodeB, gNB) in the 5G system, the base station in the sixth-generation mobile communication system, the base station in the future mobile communication system, or the access node in the wireless fidelity (WiFi) system, the evolved node B (eNB) in the long-term evolution (LTE) system, the radio network controller (RNC), the node B (NB), the base station controller (BSC), the home base station (for example, home evolved NodeB, or home Node B, HNB), the base band unit (BBU), the transmission reception point (TRP), the transmitting point (TP), the base transceiver station (BTS), the satellite, the drone, etc. In a network structure, the network device may include a centralized unit (CU) node, or a distributed unit (DU) node, or a RAN device including a CU node and a DU node, or a RAN device including a control plane CU node and a user plane CU node, and a DU node, or the network device may also be a wireless controller, relay station, vehicle-mounted device, and wearable device in a cloud radio access network (CRAN) scenario. In addition, the base station may be a macro base station, a micro base station, a relay node, a donor node, or a combination thereof. The base station may also refer to a communication module, a modem, or a chip for being set in the aforementioned device or apparatus. The base station may also be a mobile switching center and a device that performs the base station function in D2D, V2X, and M2M communications, a network-side device in a 6G network, or a device that performs the base station function in future communication systems. The base station can support networks with the same or different access technologies without limitation.

[0160] It should be noted that the device used to implement the function of a terminal or network device in this application can be a terminal or network device, or it can be a device that can support the terminal or network device to implement the function, such as a chip system or chip, which can be installed in the terminal or network device. In the embodiments of this application, the chip system can be composed of chips, or it can include chips and other discrete devices.

[0161] It should also be noted that some embodiments herein use the 5G system as an example to describe specific solution details. It is understood that when this solution is applied to other communication systems, such as the LTE system or future communication systems, the messages, channels, or information in the solution can be replaced with messages, channels, or information in other communication systems that can implement corresponding functions, and this application does not limit this.

[0162] In order to facilitate understanding of the solution of this application, the terms involved in this application are first introduced.

[0163] 1. LDPC Code

[0164] LDPC codes are linear block codes whose parity check matrices are sparse. The number of zero elements in an LDPC parity check matrix far outnumbers the number of nonzero elements. In other words, the row and column weights of the parity check matrix are very small compared to the LDPC code length. An LDPC code with an information bit sequence length equal to k and a code length equal to n can be uniquely identified by its parity check matrix.

[0165] In 1981, Tanner represented LDPC codewords using a graph, now called a Tanner graph. There is a one-to-one correspondence between a Tanner graph and a parity check matrix. A Tanner graph consists of two types of vertices: one type represents codeword bits, called variable nodes, and the other type is called check nodes, representing check constraints. Each check node represents a check constraint. This is explained below with reference to Figures 2 and 3.

[0166] FIG2 is a schematic diagram of the LDPC check matrix H.

[0167] In Figure 3, {V i} represents a variable node set, {C i} represents the set of check nodes. Each row of the check matrix H represents a check equation, each check equation corresponds to a check node, and each column represents a codeword bit, each codeword bit corresponds to a variable node. In Figure 1, there are eight variable nodes and four check nodes. If a codeword bit is included in the corresponding check equation, a line is connected between the variable node and the check node involved, resulting in a Tanner graph.

[0168] FIG3 is a Tanner graph of the LDPC check matrix H.

[0169] As shown in Figure 3, the Tanner graph represents the LDPC parity check matrix. For example, for a parity check matrix H with m rows and n columns, the Tanner graph contains two types of nodes: n variable nodes and m check nodes. The n variable nodes correspond to the n columns of the parity check matrix H, and the m check nodes correspond to the m rows of the parity check matrix H. A cycle in a Tanner graph consists of interconnected vertices. The cycle starts and ends at a vertex in this group and passes through each node only once. The length of a cycle is defined as the number of edges it contains, while the girth of the graph, also known as the graph size, is defined as the minimum cycle length in the graph. In Figure 3, the girth is 6, as indicated by the black lines. The variable nodes in the Tanner graph correspond to each column of the parity check matrix H, that is, to each LDPC codeword bit. The check nodes in the Tanner graph correspond to each row of the parity check matrix H, that is, to each LDPC parity bit. The connections between the two types of nodes correspond to the values ​​of the elements in the H matrix. If there is a connection between the i-th check node and the j-th variable node, the value of the element (i, j) in the H matrix is ​​1. If there is no connection, the corresponding element is 0. The connection between the variable node and the check node can also be called an edge.

[0170] In addition, in the Tanner graph, a cycle refers to a closed loop consisting of variable nodes, check nodes, and edge terminations.

[0171] As mentioned above, LDPC is a linear block code. It divides the information sequence to be encoded into groups of k bits. The encoder then performs a linear operation on these k information bits to obtain m parity bits. These k information bits are then combined with the m parity bits to form a code group of length n = k + m. The mapping from k information bits to n-bit code groups is typically represented by a corresponding parity check matrix H. Based on the parity check matrix H, a coding sequence is generated to complete the encoding process. After the coding sequence is transmitted over the channel, the receiver decodes the received signal and determines the original information bits.

[0172] 2. QC-LDPC

[0173] Quasi-cyclic low density parity check (QC-LDPC) codes are a type of structured LDPC. Due to the unique structure of its parity check matrix, encoding can be implemented using a simple feedback shift register, reducing the coding complexity of LDPC. When the code length is long, the LDPC parity check matrix H will be very large. Therefore, H is usually represented in blocks: the complete parity check matrix H is considered to be composed of multiple Z c ×Zc Specifically, the complete check matrix H can be generated by a base matrix H b Indicates that H b Each element in corresponds to a Z c ×Z c Each submatrix can be represented by the number of cyclic shift bits, thus greatly reducing the storage space required for the complete check matrix H. b The elements in can also be called quasi-cyclic (QC) blocks.

[0174] Based on the basis matrix H b and the expansion factor Z c , the basis matrix H can be b Expanded to a complete check matrix for encoding or decoding. c (lifting size) may also be referred to as a lifting factor, lifting value, expansion value, expansion coefficient, lifting size, etc., and the description of lifting value is used in this application.

[0175] For example, the basis matrix H of QC-LDPC b As shown below:

[0176]

[0177] It can be seen that the basis matrix H b The size of the matrix is ​​4 rows and 24 columns, and the basis matrix H b Each element in represents a Z c = code length / 24-order square matrix, element Represents the cyclic permutation matrix, i represents the cyclic shift value, where 0≤i≤Z c -1, i is an integer. In addition, the basis matrix H b The "-1" in represents an all-zero matrix, and "0" represents an identity matrix.

[0178] For example, As shown below:

[0179]

[0180] It should be noted that the basis matrix H b In addition to "-1", the zero elements in can also have other representations, such as using "-" or null values ​​to represent an all-zero matrix.

[0181] 3. Basic structure of basis matrix

[0182] The fifth generation (5 thFor example, 5G NR's LDPC adopts a Raptor-like structure, where its parity check matrix can be gradually extended to lower bit rates using a high-rate kernel matrix. This allows for flexible support of various bit rate encodings.

[0183] Figure 4 is a schematic diagram of the parity check matrix structure of the LDPC parity check matrix for 5G NR. As shown in Figure 4, the LDPC parity check matrix for 5G NR consists of five parts: A, B, C, D, and E. A and B together form the high-rate core matrix. A corresponds to the information bits (or information bits), and B is a square matrix corresponding to the high-rate parity bits (or check bits). C is an all-zero matrix. E is the identity matrix, corresponding to the parity bits for the low-spread code rate. D and E together form a single parity check relationship.

[0184] 4. IR-HARQ

[0185] The incremental redundancy-hybrid automatic repeat request (IR-HARQ) mechanism involves the transmitter sending information bits and some redundant bits during the initial transmission, and sending additional redundant bits during retransmissions. If the initial transmission is not correctly decoded, the transmitter retransmits more redundant bits to reduce the channel bit rate, thereby improving the decoding success rate. If the receiver still cannot correctly decode the signal after combining the redundant bits from the first retransmission, the transmitter retransmits again. As the number of retransmissions increases, the number of redundant bits increases, and the signal-to-code rate decreases, resulting in better decoding results.

[0186] The IR HARQ mechanism needs to be compatible with LDPC coding schemes of multiple rates so that new incremental redundancy bits can be introduced during retransmission.

[0187] 4. LDPC Codes for 5G NR

[0188] The parity check matrix of the 5G NR LDPC code includes the following main features.

[0189] 1) Large column weight and punching design

[0190] This feature refers to the presence of variable nodes with very large degrees in the parity check matrix of the 5G NR LDPC code. The columns corresponding to these variable nodes can be punctured by the transmitter after encoding. That is, the transmitter does not send the encoded columns corresponding to these variable nodes, and the receiving device sets the log-likelihood ratio (LLR) corresponding to the punctured columns to 0 for decoding.

[0191] 2) Raptor-like expansion node structure design

[0192] This feature means that the extended nodes of the check matrix of the 5G NR LDPC code have a single diagonal structure, that is, the extended node degree is 1 and only appears in one check equation.

[0193] 3) QC block structure

[0194] This feature means that the LDPC code actually used is the basis matrix H b The non-negative elements in are boosted to Z c The expansion of into a circulant shift matrix.

[0195] 4) Dense core region

[0196] The parity check matrix of the 5G NR LDPC code has very dense connections in rows 1-4 and columns 1-26 (relative to other locations). This portion is called the kernel matrix. The kernel matrix has high edge density, and the parity check bits do not have a degree of 1. The parity check bits in the non-core matrix are all Raptor-like nodes with a degree of 1.

[0197] 5G NR LDPC codes support IR-HARQ, but the high-rate portion of the 5G NR LDPC code (i.e., the core matrix) can only support parallel decoding of QC blocks, not entire rows. The low-rate portion supports parallel decoding of entire rows, which can lead to imbalanced computational units between the high- and low-rate portions. For example, to support parallel decoding of QC blocks in the high-rate portion, more computational units are set up per row. When decoding the low-rate portion, only a portion of these computational units may be used, resulting in significant wasted computational unit area. Furthermore, the peak throughput of 5G NR LDPC codes cannot reach 100Gbps, and decoding latency is significant.

[0198] 5. 802.11ay LDPC code

[0199] The parity check matrix of the 802.11ay LDPC code has the following main features.

[0200] 1) Each code rate stores a separate check matrix. There are only a few specific code rates and code lengths. Flexible code lengths and code rates are not supported. There is no nesting feature and IR-HARQ is not supported.

[0201] 2) The low-rate parity check matrix has multiple rows that are orthogonal, and row-parallel decoding can be performed.

[0202] 3) QC block structure, the same as 5G NRLDPC code.

[0203] 4) The edge density of the high-rate check matrix is ​​dense, while the edge density of the low-rate check matrix is ​​sparse. From the perspective of the entire check matrix, the overall edge density is relatively dense.

[0204] The 802.11ay LDPC code has large code rate restrictions, matrix storage redundancy, poor flexibility, no nesting between different code rates, and does not support IR-HARQ.

[0205] 6. Non-zero elements and zero elements

[0206] In this application, a zero element in the check matrix indicates that there is no connection between the variable node and the check node, and a non-zero element in the check matrix indicates that there is a connection between the variable node and the check node.

[0207] This application does not limit the specific representation of zero elements and non-zero elements. For example, in the basis matrix H b In the check matrix H, "-1" can be used to represent a zero element, and "non-negative value" can be used to represent a non-zero element. For another example, in the check matrix H, "0" can be used to represent a zero element, and "1" can be used to represent a non-zero element.

[0208] 7. Column weight and row weight

[0209] For a matrix column, column weight refers to the number of 1s in that column. For a matrix row, row weight refers to the number of 1s in that row. Column weight is also called column degree. For a check matrix, column weight is also called the degree of the variable node.

[0210] 8. Expanded columns, non-expanded columns, expanded rows, and non-expanded rows

[0211] For LDPC codes, each additional extended node adds a row and column. In this application, the added row and column are referred to as the extended column and extended row. The extended column is the column corresponding to the extended node; in other words, the extended column corresponds to the extended parity bit. Columns outside the extended column are non-extended columns. Rows outside the extended row are non-extended rows. Taking Figure 4 as an example, the columns in C and E are extended columns, and the rows in D and E are extended rows.

[0212] 9. Information transmission process

[0213] Figure 5 is a schematic diagram of the information transmission process. As shown in Figure 5, information is transmitted from the source and undergoes processing such as source coding, channel coding, modulation, air interface transmission, demodulation, channel decoding, and source recovery before reaching the destination, completing the information transmission from the source to the destination. The processing shown in the upper layer of Figure 5 (including source coding, channel coding, and modulation) is performed at the transmitting end, while the processing shown in the lower layer (including demodulation, channel decoding, and source recovery) is performed at the transmitting end.

[0214] The embodiments of the present application mainly relate to source coding, channel coding, channel decoding and source recovery shown in FIG5 .

[0215] As can be seen from the above, the high-rate portion of the 5G NR LDPC code (i.e., the core matrix) only supports parallel decoding of quasi-cyclic QC blocks, not entire rows, limiting decoding efficiency. The 802.11ay LDPC code stores a separate parity check matrix for each code rate, does not support flexible code rates, and therefore does not support the IR-HARQ mechanism.

[0216] In response to the above-mentioned problems, the present application provides a communication method based on LDPC codes, which can obtain an LDPC base matrix according to a storage matrix and indication information for indicating the correspondence between rows of the storage matrix or the correspondence between rows of the desired LDPC base matrix, and in the process of obtaining the LDPC base matrix, the total number of edges corresponding to the non-extended columns on the Tanner graph can be unchanged. The number of edges on the Tanner graph is one of the key factors affecting the computational complexity of the LDPC code. Therefore, the method provided by the present application helps to maintain the computational complexity of the LDPC code, especially in the scenario of expanding from a high code rate to a low code rate, which helps to reduce the computational complexity of the low-code-rate LDPC code and improve the decoding efficiency.

[0217] The communication method based on LDPC code provided by this application is described below.

[0218] FIG6 is a schematic flowchart of a communication method 600 based on LDPC codes provided in this application.

[0219] Method 600 may be executed by the transmitting end and the receiving end, or by modules or units in the transmitting end and the receiving end. For ease of description, the transmitting end and the receiving end are collectively referred to as the transmitting end and the receiving end. Method 600 may include at least part of the following contents.

[0220] Step 601: The transmitting end obtains an information bit sequence.

[0221] That is, if the sending end needs to communicate with the receiving end, that is, the sending end needs to send a signal to the receiving end, the sending end needs to first obtain the information bit sequence corresponding to the signal to be sent to the receiving end.

[0222] Optionally, the transmitting end obtaining the information sequence to be transmitted may refer to: the transmitting end performing source encoding on source symbols to generate an information bit sequence. The transmitting end obtaining the information sequence to be transmitted may also refer to: the transmitting end receiving the information bit sequence from another communication device.

[0223] In step 602, the transmitting end performs LDPC encoding on the information bit sequence according to the LDPC base matrix to obtain an LDPC codeword sequence.

[0224] In step 603, the transmitting end sends the LDPC codeword sequence to the receiving end, or in other words, the receiving end receives the LDPC codeword sequence from the transmitting end.

[0225] Step 604: The receiving end decodes the LDPC codeword sequence according to the LDPC base matrix.

[0226] Among them, the above-mentioned LDPC base matrix can be obtained based on the storage matrix and indication information. The indication information is used to indicate the correspondence between the rows of the storage matrix or the correspondence between the rows of the LDPC base matrix. The specific correspondence will be described in combination with the following methods 1 to 4.

[0227] The present application does not limit the specific form of the indication information. In one possible implementation, the indication information may be in the form of at least one of an indication sequence, a mapping table, or a mapping pair.

[0228] The following describes the format of the indication information with reference to examples.

[0229] Taking the indication information used to indicate the correspondence between rows of the LDPC basis matrix as an example, it is assumed that the LDPC basis matrix includes 8 rows, and the rows numbered 0 to 7 correspond to the 1st to 8th rows respectively, where the 3rd to 8th rows are extended rows, and the 3rd row and the 1st row have a corresponding relationship, the 4th row and the 2nd row have a corresponding relationship, the 5th row and the 2nd row have a corresponding relationship, the 6th row and the 1st row have a corresponding relationship, the 7th row and the 3rd row have a corresponding relationship, and the 8th row and the 4th row have a corresponding relationship.

[0230] 1) When the indication information is in a sequence, for example, the indication sequence may be {0, 1, 1, 0, 2, 3}, etc.

[0231] 2) When the indication information is in the form of a mapping table, for example, the mapping table may be as shown in Table 1 or Table 2.

[0232] Table 1

[0233]

[0234] Table 2

[0235]

[0236] 3) When the indication information is in the form of mapping pairs, for example, the mapping pairs may include (2, 0), (3, 1), (4, 1), (5, 0), (6, 2), and (7, 3).

[0237] In this application, the row number may also be referred to as a row index.

[0238] For the convenience of description, the technical solution of the present application is described below by taking an indication sequence as an example, wherein the indication sequence can be replaced by an equivalent mapping table or a mapping equivalent form.

[0239] The LDPC base matrix here may refer to a matrix actually used by the transmitter or receiver, and the storage matrix may refer to a matrix stored in the transmitter or receiver or a matrix predefined by the protocol.

[0240] Optionally, the code rate corresponding to the LDPC base matrix and the code rate corresponding to the storage matrix may be the same or different, depending on whether the target code rate is the same as the code rate corresponding to the storage matrix. For example, if the current target code rate is the same as the code rate corresponding to the storage matrix, the transmitter or receiver may directly use the storage matrix for encoding or decoding. In this case, the transmitter or receiver may not split or merge the rows of the storage matrix according to the indicator sequence. For another example, if the current target code rate is the same as or different from the code rate corresponding to the storage matrix, the transmitter or receiver may split or merge the storage matrix according to the indicator sequence to obtain the LDPC base matrix corresponding to the target code rate.

[0241] It should be noted that the LDPC base matrices used by the transmitter and receiver can be the same or different. For example, when a storage matrix can be used for encoding, the transmitter can use the storage matrix to encode the information bit sequence. That is, the LDPC base matrix used by the transmitter is the storage matrix. After receiving the LDPC codeword sequence, the receiver can split or merge the storage matrix according to the indicator sequence to obtain the LDPC base matrix used by the transmitter.

[0242] FIG7 is an example of an LDPC base matrix.

[0243] In this application, the LDPC base matrix has at least some of the following features:

[0244] Feature 1: The sum of the column weights of the non-extended columns of the LDPC basis matrix is ​​equal to the sum of the column weights of the non-extended columns of the storage matrix.

[0245] In other words, in the process of obtaining the LDPC base matrix according to the storage matrix and the indicator sequence, the sum of the column weights corresponding to the variable nodes other than the extended node remains unchanged.

[0246] Feature 2: The LDPC base matrix includes a first submatrix and a second submatrix, the first submatrix includes the non-extended columns of the LDPC base matrix, and the second submatrix includes the extended columns of the LDPC base matrix; the column weight of each column in the Q columns of the second submatrix is ​​2; one of the two non-zero elements contained in the qth column in the Q columns corresponds to the i1th row of the first submatrix, and the other of the two non-zero elements contained in the qth column in the Q columns corresponds to the i2th row of the first submatrix, the i1th row and the i2th row are orthogonal to each other, and the qth column is any column in the Q columns; wherein Q, q, i1, and i2 are all positive integers.

[0247] In other words, the degree of some or all of the extended nodes of the LDPC base matrix is ​​2, and the two rows corresponding to these extended nodes are orthogonal to each other except for the extended parts.

[0248] Feature 3: The LDPC base matrix is ​​an X×Y matrix. Columns y2+1 to Y of the LDPC base matrix are extended columns. The LDPC base matrix consists of submatrix A1, submatrix B1, submatrix C1, submatrix D1, and submatrix E1. Submatrix A1 and submatrix B1 constitute the core of the storage matrix. Submatrix A1 consists of rows 1 to x1 and columns 1 to y1 of the LDPC base matrix. Submatrix B1 consists of rows 1 to x1 and columns y1+1 to y2 of the LDPC base matrix. Submatrix C1 consists of rows 1 to x1 and columns y2+1 to Y of the LDPC base matrix. Submatrix D1 consists of rows x1+1 to X and columns 1 to y2 of the LDPC base matrix. Submatrix E1 consists of rows x1+1 to X and columns y2+1 to Y of the LDPC base matrix. 1≤x1≤X, 1≤y1≤y2≤Y, and x1, X, y1, y2, and Y are all integers. The diagonal of the submatrix E1 is non-zero elements, the submatrix E1 includes non-zero elements above the diagonal and / or the submatrix E1 includes non-zero elements below the diagonal, and the submatrix C1 includes non-zero elements.

[0249] Here, rows 1 to x1 and columns 1 to y1 of the LDPC base matrix refer to all positions in the LDPC base matrix whose row number is greater than or equal to 1 and less than or equal to x1, and whose column number is greater than or equal to 1 and less than or equal to y1. Similarly, rows 1 to x1 and columns y1+1 to y2 of the LDPC base matrix, rows x1+1 to X and columns 1 to y2 of the LDPC base matrix, and rows x1+1 to X and columns y2+1 to Y of the LDPC base matrix are similar and are not further described. Similar content below will not be explained.

[0250] Because the two rows corresponding to the columns of the LDPC base matrix with a column weight of 2 are mutually orthogonal except for the extended nodes, the receiver can perform row-parallel decoding on the LDPC codeword sequence based on this LDPC base matrix. The LDPC decoding process is described below.

[0251] In one possible implementation, a receiving end performs channel decoding on an LDPC codeword sequence based on an LDPC base matrix, including: employing a first decoding method to decode the row corresponding to the i1th row and the row corresponding to the i2th row in the LDPC codeword sequence; and employing a second decoding method to decode the row corresponding to the i1th row of the second submatrix and the row corresponding to the i2th row in the second submatrix in the LDPC codeword sequence. The first decoding method is row-parallel decoding, and the second decoding method is different from the first decoding method.

[0252] In other words, for the i1th row and the i2th row of the LDPC basis matrix, the first decoding method (i.e., row parallel decoding) is used for the positions in these two rows except the extended nodes, and the second decoding method is used for the positions corresponding to the extended nodes in these two rows.

[0253] There are many ways to implement the second decoding method, which is not limited in this application.

[0254] One possible implementation method is to take the i1th row and the i2th row of the LDPC base matrix as an example. Assuming that the i1th row corresponds to the first check node and the i2th row corresponds to the second extended node, the following decoding operation can be performed for the first extended node corresponding to the i1th row and the i2th row (the corresponding relationship can be as described in Feature 2):

[0255] Obtaining first information stored by the first extension node and second information stored by the first check node, wherein the first information is information sent by the first extension node to the first check node during a previous decoding iteration, and the second information is information sent by the first check node to the first extension node during the previous decoding iteration;

[0256] Acquire third information stored in the second check node, wherein the third information is information sent by the second check node to the first extension node during a previous decoding iteration;

[0257] Determine fourth information based on the first information, the second information, and the third information, and store the fourth information in the second check node, where the fourth information is information sent by the second check node to the first extension node during this decoding iteration;

[0258] Determine fifth information based on the fourth information and the first information, and store fifth information in the first extension node, where the fifth information is information sent by the first extension node to the first check node during this decoding iteration;

[0259] Determine sixth information based on the fourth information and store the sixth information in the first check node. The sixth information is information sent by the first check node to the first extension node during this decoding iteration.

[0260] In the above decoding process, in addition to being used to update the storage of the second check node, the information sent by the second check node to the first extension node during the current decoding iteration can also be directly used, without storage, to calculate the information sent by the first extension node to the first check node during the current decoding iteration and the information sent by the first check node to the first extension node during the current decoding iteration. In this way, decoding can be performed without error, which can reduce the number of times the first extension node, the first check node, and the second check node are read and updated.

[0261] In the present application, there are many ways to obtain the above-mentioned LDPC base matrix based on the storage matrix and the indicator sequence, which are not limited, for example, they may include the following method 1, method 2 and method 3.

[0262] Method 1: The transmitter stores a high code rate matrix (ie, the stored matrix is ​​a high code rate matrix), an indicator sequence, and a partition table, and splits the high code rate matrix based on the indicator sequence and the partition table to generate a low code rate LDPC base matrix.

[0263] In mode 1, the indicator sequence can also be called a split sequence or an extended interleaver, and is collectively referred to as the split sequence below. The split sequence is used to indicate the split row. For example, if the 8th element of the split sequence indicates row number 3, it means that the 8th row of the LDPC base matrix is ​​used to eliminate the row number 3 of the LDPC base matrix, where the 8th row of the LDPC base matrix is ​​obtained according to the partition table. In other words, the row number 3 of the LDPC base matrix is ​​split into the 8th row of the LDPC base matrix and the row number 3 of the LDPC base matrix after elimination (assuming the row number remains unchanged). In other words, the indicator information is used to indicate the split relationship between rows of the LDPC base matrix.

[0264] To facilitate understanding, the division of this application is first explained.

[0265] Assume that a parity check equation in a high-rate matrix is ​​c1:x1+x2+x3+x4=0. When performing low-rate extension or IR-HARQ, the newly added parity check equation is c2:x1+x3+x5=0, where x5 is an extension node (or a newly added variable node). Using c2:x1+x3+x5=0 to eliminate c1:x1+X2+x3+x4=0 for low-rate extension, the elimination of 2x1+x2+2x3+x4+x5=0 is equivalent to c′1:x2+x4+x5=0. Therefore, c′1:x2+x4+x5=0 can be used to replace c1. Eliminating c1 with c2 to obtain c′1 can be understood as splitting c1 into c′1 and c2.

[0266] It can be seen that except for the extended node x5, the variable nodes contained in c′1 and c2 are completely orthogonal, supporting the design of a row-parallel decoding scheme.

[0267] Figure 8 is a schematic diagram of a single split of a high-rate matrix. In Figure 8, the high-rate matrix is ​​a 4×28 core matrix, and the splitting of the second row of the high-rate matrix is ​​used as an example. As shown in Figure 8, to ensure performance and convergence speed, the 4×28 core matrix has a high edge density, with almost all elements in the matrix being nonzero, resulting in an equivalent number of decoding rows of 4. To perform a low-rate expansion, a row and a column are added to the 4×28 core matrix, namely the 5th row and the 29th column, resulting in a 5×29 decoding matrix. The last element of the newly added row is a nonzero element (such as 1 in Figure 8), and the row weight is approximately equal to 0.5 * the number of columns in the core matrix, which is approximately equal to 14. In this case, the equivalent number of decoding rows is 5. Then, row 5 is used to eliminate rows 2, resulting in a 5×29 equivalent decoding matrix. The original row 2 is split into rows 4 and 5 of the equivalent decoding matrix shown in Figure 8. Since rows 4 and 5 of the equivalent decoding matrix are orthogonal to each other except for the newly added check bits, the number of equivalent decoding rows is 4.

[0268] In addition, the newly added fifth row can be called the elimination row or elimination check node of the original second row.

[0269] It should be noted that in FIG8 , the rows of the 5×29 equivalent decoding matrix are transformed, and the row numbers may be changed accordingly or remain unchanged. Of course, after the split, the equivalent decoding matrix may not undergo the row transformation, and this application does not limit this.

[0270] As shown in Figure 8, the splitting method described above does not increase the number of edges in the Tanner graph as the code rate decreases. That is, the total number of edges in the base matrix for all code rates, excluding the expanded nodes, remains constant. The computational complexity of LDPC codes depends primarily on the number of edges and orthogonality in the Tanner graph. Therefore, using the splitting method described above to obtain a low-rate matrix helps maintain the computational complexity of LDPC codes.

[0271] FIG8 shows only one splitting of the high code rate matrix. In fact, multiple splitting may be required from the high code rate matrix to the low code rate matrix of the target code rate, that is, the splitting process of the low code rate expansion is completed gradually.

[0272] Figure 9 is a schematic diagram of a progressive splitting method. Figure 9 shows the first to third splits of the splitting process for low-rate expansion. After the first split, the second row of the 4×28 high-rate matrix is ​​split into the second and fifth rows, resulting in a 5×29 equivalent decoding matrix. After the second split, the fourth row of the high-rate matrix is ​​split into the fourth and sixth rows, resulting in a 6×30 equivalent decoding matrix. After the third split, the first row of the high-rate matrix is ​​split into the first and seventh rows, resulting in a 6×30 equivalent decoding matrix. The portions of the matrix in Figure 9 with marked values ​​can be understood as zero elements. For example, the element in the first row and 29th column of the 5×29 equivalent decoding matrix is ​​a zero element.

[0273] The splitting process for low-code rate expansion can be completed layer by layer, and a complete round of splitting can be regarded as a process of splitting all existing check nodes once. For example, assuming that the current matrix is ​​the initial matrix of a 4×28 high-code rate matrix, in which each row needs to be split, then a complete round of splitting means that rows 1 to 4 are all split once. For another example, assuming that the current matrix is ​​an 8×32 equivalent decoding matrix, in which each row needs to be split, then a complete round of splitting means that rows 1 to 8 are all split once. After a complete round of splitting, the depth of the forest increases by 1. The matrix obtained by the i-th split in the t-th round corresponds to a forest with a depth of t+1, and the number of check nodes with a depth of t+1 is i*2. Combined with Figure 9, the forest depth corresponding to the 1st, 2nd, and 3rd splits in the 1st round is 2, and the number of check nodes with a depth of 2 is 2, 4, and 6, respectively.

[0274] It should be noted that a splitting round can be a complete splitting round or a partial splitting round. For example, to achieve the target code rate, only some check nodes may need to be split in the final splitting round. For another example, if the row weight of some check nodes in a high-rate matrix is ​​not large, they may not be split.

[0275] Since the splitting process of low bit rate expansion is performed layer by layer, the depth of the subtree corresponding to each root node can remain consistent.

[0276] Figure 10 is a schematic diagram of a complete two-round split of a high-rate matrix. The matrix shown in Figure 10 shows the two-round split only by indicating the zero and non-zero elements in the shaded and unshaded areas, without indicating the offset values ​​of each element. Shaded squares represent non-zero elements, and unshaded squares represent zero elements. The order of the first round of splitting is row 2, row 4, row 1, row 3; the order of the second round of splitting is row 2, row 5, row 4, row 6, row 7, row 1, row 8, row 3.

[0277] Optionally, during the splitting process, the check node density (i.e., row weight) can be kept as regular as possible, so that the number of QC blocks for parallel decoding in each region of the LDPC base matrix is ​​similar, the corresponding hardware resources can be kept the same, and the latency of row parallel decoding can be kept consistent, meeting the density requirements of density evolution.

[0278] The specific process of splitting is described below in combination with the splitting sequence and the partitioning table.

[0279] Assume that the number of rows of the high-rate matrix is ​​M, the number of columns is N, the number of non-extended rows is m1, and the number of non-extended columns is n2. When the high-rate matrix does not contain extended rows and extended columns, M=m1, N=n2.

[0280] In this application, the split sequence is used to indicate the split rows, and the partition table is used to construct the rows added by each split.

[0281] 1) Split sequence

[0282] A split sequence can include multiple row numbers, and the sorting order of the row numbers in the split sequence is the split order.

[0283] In one possible implementation, the splitting sequence includes at least one segment, and each segment in the at least one segment corresponds to a round of splitting.

[0284] Optionally, the row number included in at least one segment may be a random value.

[0285] Optionally, the row number included in the at least one segment is related to the row weight of each row of the storage matrix.

[0286] Optionally, the row numbers of the segments corresponding to the t-th round of splitting in at least one round of splitting corresponding to at least one segment are {1, ..., 2 t-1 m1} or {1, ..., 2 t-1 m1}, m1 is the number of non-extended rows of the high-rate matrix, and t is a positive integer. Since the row numbers of the segments corresponding to the t-th round of splitting are {1, ..., 2 t-1 m1} or {1, ..., 2 t-1Therefore, multiple splits included in each round can be executed in parallel, which helps to improve the splitting efficiency.

[0287] Optionally, the t-th segment of the splitting sequence corresponds to the t-th round of splitting.

[0288] Optionally, the t+1th segment of the splitting sequence corresponds to the tth round splitting, and the 1st segment corresponds to the 0th round splitting or the initial matrix (ie, the storage matrix).

[0289] The following description takes the t+1th segment of the split sequence corresponding to the tth round of splitting as an example.

[0290] FIG11 is a schematic diagram of a split sequence.

[0291] Assume the initial matrix is ​​BG0 = (H0) M×N , let the matrix after the t-th round split be BG t , define BG t To BG t-1 The matrix generated after all the rows of BG are split, let t =G[C t ∪V t ]. If the initial matrix does not include extended rows and extended columns, then M=m1, N=n2.

[0292] In the splitting phase, if row i is generated by splitting the initial row j (i.e., i is the elimination row of j), then j = f(i). If there exists a node i = i0, i1, i2, ..., i l =j, so that i k =f(i k-1 ), for k=1,…,l, then we call i~j; in BG t In the definition of set g t (j)={i∈C t |i~j}, then g1(j)=j, i=p+M(2 t -1)}; by BG t-1 Construct BG t The split sequence is [g t-1 (1),…,g t-1 ()], construct BG from BG1 t The split sequence 1 is [g1(1)…g1(M)][g2(1)…g2(M)]…[g t-1 (1)…g t-1 (M)]; Construct BG from BG1 t The split sequence 2 is [h1(1,…,M)][h2(1,…,M)]…[h t-1 (1,…,M)], where [ht (1,…,M)]=[g t (1){1}g t (2){1}…g t (M){1},…,g t (1){2 t-1}g t (2){2 t-1}…g t (M){2 t-1}].

[0293] Split sequences 1 and 2 are basic split sequences, and the actual split sequence can be a permuted form of sequence 1 and sequence 2.

[0294] The basic meaning of the split sequence is as follows:

[0295] a) The length of the split sequence: that is, the number of row numbers contained, which is the total number of rows in the matrix generated by the split.

[0296] b) Segmentation of the split sequence: The split sequence is segmented according to the number of split rounds. The t+1th segment corresponds to the tth round split or the tth segment corresponds to the t-1th round split. The length of the segment corresponding to the tth round split is 2 t-1 M.

[0297] c) The meaning of each number in the split sequence: for positions 1,…,M, the number corresponds to the row number of the initial matrix; for positions greater than M, the number corresponds to the row number of the current split.

[0298] d) Order of numbers in the split sequence: The order of row numbers in positions greater than M in the split sequence corresponds to the split order.

[0299] e) The number of a certain number in the split sequence: For positions greater than M, the number of times a certain number appears is the number of splits in the row, and also corresponds to the number of nodes containing expansions.

[0300] The split sequence is described below with examples.

[0301] Combined with Figure 10, the split sequence can be {1, 2, 3, 4, 2, 4, 1, 3, 2, 5, 4, 6, 7, 1, 8, 3}, which includes three segments: {1, 2, 3, 4}, {2, 4, 1, 3} and {2, 5, 4, 6, 7, 1, 8, 3}, among which {1, 2, 3, 4} corresponds to the 0th round of splitting or the initial matrix, {2, 4, 1, 3} corresponds to the 1st round of splitting, and {2, 5, 4, 6, 7, 1, 8, 3} corresponds to the 2nd round of splitting.

[0302] The characteristics of the split sequence are as follows:

[0303] a) In the tth round of splitting, the element of the corresponding sequence is 2 t-1 M+1-2 t M can be a permutation p t (1,…,2 t-1 M), that is, the labels (i.e., row numbers) of all the current check equations are present only once in the sequence segment corresponding to this round of splitting.

[0304] In this case, the replacement p t (1,…,2 t-1 M) can be p(1,…,M)×…×p(2 t-2 M+1,…,2 t-1 M), or p({i∈C t |i~1})×…×p({i∈C t |i~M}). The “×” mark indicates splicing.

[0305] b) The calculation formula for the i-th position element of the split sequence is: Where t1 satisfies The largest non-negative integer.

[0306] 2) Divide the table

[0307] The partition table can also be called a partition sequence. The partition table corresponds to the split sequence. Except for the segment composed of the initial M positions, each segment of the split sequence corresponds to a block or row of the partition table.

[0308] Figure 12 is a schematic diagram of the correspondence between the partition table and the splitting sequence. It should be noted that the form of the partition table in Figure 12 is only an example. As shown in Figure 12, the splitting sequence includes 4 segments, the first segment corresponds to the initial matrix, and the second to fourth segments correspond to the first to third rounds of splitting, respectively. The partition table includes 3 rows, each of which can be regarded as a block. The positions of the same numbers in the splitting sequence and the partition table correspond to each other. For example, the position of 1 in the splitting sequence corresponds to the position of 1 in the partition table.

[0309] Combined with Figure 12, the basic meaning of the partition table is as follows:

[0310] a) Rows of the partition table: corresponds to the number of splitting rounds, each row corresponds to one splitting round.

[0311] b) Divide the columns of the table: the number of columns corresponding to the t-th round of splitting is 2 t-1 , that is, the number of numbers in each row.

[0312] c) Divide the numbers in the table: Each number corresponds to M rows and 1 column. To avoid confusion, the M rows corresponding to each number are called subdivision rows. Each subdivision row corresponds to one split and to an extended row of the resulting LDPC basis matrix.

[0313] d)(t,i,j): The jth column of the tth row of the i-th subdivision row of the partition table is represented as (t,i,j). The set stored at this position is the label (i.e., column number) of the variable node included or not included in the i+(j-1)M elimination check equations. The corresponding elimination parent node (i.e., the check equation to be eliminated) is p t (i+(j-1)M).

[0314] The following describes the partitioning table with examples.

[0315] Figure 13 is an example of a partition table. As shown in Figure 13, the partition table includes 2 rows, each of which corresponds to 2 rounds of splits. Each row includes 4 sub-rows, each of which corresponds to one split. The variable nodes stored at positions (2, 3, 2) are numbered 1, 8, 11, 13, 19, and 24. Assuming that the numbers of these variable nodes are the numbers of the variable nodes included in the verification equation, the elimination verification equation for the 7th split in the 2nd round is x1+x8+x 11 +x 13 +x 19 +x 24 +x 39 =0.

[0316] Characteristics of partition table:

[0317] a) The (t, i, j) in the partition table stores the labels of the variable nodes contained in the elimination check equation or the labels of the variable nodes remaining after the parent node is eliminated.

[0318] b) The weight of the row in the tth round of splitting is equal to or approximately equal to 1 / 2 of the weight of the row in the t-1th round of splitting. This way, the sum of the total number of elements in all columns of each sub-row of the tth row of the partition table is close to the same, and the table is compact.

[0319] c) The set of labels of the variable node stored at position (t, i, j) is truly included in the set of labels of the variable node contained in its parent node.

[0320] d) In addition to storing the variable node's index, the position (t,i,j) can also store additional information. For example, the position (t,i,j) can also store the fixed difference between the shifting value and its parent node. In particular, if the fixed difference of all shifting values ​​is 0, storage of this information can be omitted. For another example, the position (t,i,j) can also store the index of its parent node, thus omitting the split sequence.

[0321] The following describes the splitting process based on the splitting sequence and the partitioning table with a specific example.

[0322] FIG14 is a schematic diagram of 1 split.

[0323] Assume that the number of columns N=28 and the number of rows M=4 of the stored high code rate matrix H0, that is, the code rate is 0.857, as shown in Figure 14 (a). Assume that the split sequence is The first row corresponds to the initial matrix H0, the second row corresponds to the first round of splitting, and the third row corresponds to the second round of splitting. Assume that the partition table is the partition table shown in Figure 13, where the row with column number 1 constitutes the first round of splitting, and the row with column number 2 constitutes the second round of splitting.

[0324] The first M=4 positions (row 1) of the split sequence correspond to the initial matrix (H0) 4×28 The second row of the split sequence is 1234 (the current matrix (H0) 4×28 The first number in the second row is 2, and the index of the check equation for the first split of the first round is 2, which is denoted as c2. The variable nodes contained in the elimination check equation for c2 are determined by the first subdivision row of the first row of the partition table, that is, the variable nodes corresponding to the index set of the first row of the first split of the partition table, that is, the following check equation c5 (containing an expansion node x 29 ):

[0325] x2+x4+x6+x8+X 10 +x 11 +x 14 +x 16 +x 18 +x 20 +x 22 +x 23 +x 29 =0

[0326] Perform XOR addition on c5 and c2 to obtain the new verification equation c′2: x1+x3+x5+x7+x9+x 12 +x 13 +x 15 +x 17 +x 19 +x 21 +x 24 +x 25 +x 26 +x 27 +x 28 +x 29= 0; c′2 is used to replace c2. c′2 and c5 are different except for the expansion node x 29 The remaining positions are completely orthogonal, and the check equation matrix after splitting (H1) 5×29 As shown in Figure 14(b).

[0327] The label of the newly added check equation c5 is the same as the position currently used in the split sequence.

[0328] Subsequently, the 2nd, 3rd, and 4th elements of the 2nd row of the split sequence are used to split the resulting matrix (H2) 6×30 、(H3) 7×31 、(H4) 8×32 , completing the first round of splitting process; then go to the third row of the splitting sequence and perform the second round of splitting process.

[0329] The split sequence and partition table are described above. The rate matching process based on the split sequence and partition table is described below.

[0330] In one possible implementation, assume that the number of rows in the high-rate matrix is ​​M, the number of columns is N, and the extended rows and columns are not included. The rate matching process based on the split sequence and partition table is mainly implemented by the following steps:

[0331] Step 1: Determine the number of rows X and columns Y of the LDPC basis matrix to be constructed according to the target code rate and target code length;

[0332] Step 2: Determine the splitting according to the number of columns Y of the LDPC base matrix, including the complete splitting rounds 1, ..., t0 and the first i splits of the t0+1 round;

[0333] For example, select Z c The list satisfies KZ c The smallest Z ≥ K0 c , where K is the number of information columns of the LDPC basis matrix (that is, the number of information columns of the storage matrix), K0 is the number of information bits corresponding to the LDPC basis matrix (that is, the target number of information bits), and KZ c -K0+1 to KZ c The position is shortened; the number of splits R is determined, R is to meet RZ c ≥N0-K0; Next, select t0, which satisfies 2 t The maximum positive integer M≤R, which requires a complete split in the first t0 rounds and i=R-2 in the t0+1 round t M splits.

[0334] Step 3: For the t-th round of splitting, 0≤t≤t0, read the 2nd of the split sequence. t-1 M+1~2t M-bit elements and corresponding partition tables complete the complete splitting process of the first t0 rounds; for the t0+1 round split, read 2 of the split sequence t The M+1~i-bit elements and the corresponding partitioning table complete the incomplete splitting process of the t0+1th round.

[0335] For example, the split sequence and the position corresponding to the first t0 round of complete splits in the partition table and the first R-2 of the t0+1 round of splits are selected in sequence. t The position corresponding to M is found, and the high code rate matrix is ​​split R times according to the obtained split sequence and partition table.

[0336] Since the split sequence has the permutation property described above, multiple splits in each round of splitting can be performed in parallel.

[0337] After the above splitting process, the obtained LDPC basis matrix supports row parallelism of at most Decoding.

[0338] It should be pointed out that the above Z c The conditions that need to be met, such as R, t0, etc., are all exemplary and can be replaced by other achievable conditions.

[0339] It should also be noted that the R splits can be divided into multiple rounds as described above, and the multiple splits in each round are executed in parallel. Of course, the R splits can also be executed sequentially or serially. In this case, the split sequence can be non-segmented, and the partition table can be non-blocked. After determining the number of splits R, the first M+R row numbers of the split sequence and the first R rows of the partition table (the rows here refer to the subdivision rows described above) can be obtained based on R, and then the R splits can be performed sequentially.

[0340] It should be noted that for the first R-1 splits in the above R splits, Z c The rows before promotion are used as the granularity for splitting, in other words, in the QC structure or Z c As the granularity for splitting; for the Rth split, that is, the last split, Z c The row before promotion is used as the granularity for splitting, or Z c The promoted row (i.e. 1) is used as the granularity for splitting. For example, when the check bits corresponding to the last column of the LDPC matrix are punctured, the R-th split can be Z c The promoted rows are used as the granularity. c The promoted rows are described as the Rth split of the granularity.

[0341] When performing fine-grained rate matching, the basic granularity of the split can be changed from Z toc The row before promotion becomes Z c The promoted row, i.e. from Z c Change to 1 to achieve fine-grained rate matching.

[0342] Assume that the LDPC matrix size is X rows and Y columns, and the lifting value used is Z c .

[0343] If the check bits corresponding to the last column of the LDPC matrix are not punctured, then Z c It is sufficient to perform rate matching for the basic unit; if it is necessary to puncture some check bits corresponding to the last column of the LDPC basis matrix during rate matching, the last row of the check equation is constructed without following the Z c For example, based on the above, assuming that RZc-N0+K0 can correspond to the puncture position of the largest numbered extended node, for (R-1)Z c -N0 is split according to the granularity of 1, where N0 is the target code length.

[0344] For example, suppose that after rate matching, the 1st to zth rows of the check equation c with the largest number of the LDPC basis matrix are used. When c is used to split f(c), the 1st to zth rows of c are used to eliminate the 1st to zth rows of f(c) in sequence with a fine granularity of 1, and the z+1 to Zcth rows of f(c) are not eliminated. Suppose the check equations of the check matrix after elimination are c1′ and f(c′1), then

[0345] The parity check matrix is ​​constructed by splitting at a fine granularity. c1′ still has the property of complete row orthogonality (except for the extended nodes) during the decoding process using the partial sum f(c′1), and the parallelism remains unchanged.

[0346] The following is an example of how to divide the table.

[0347] Let Z c = 3, the parent node (or the eliminated check equation) is c1, and the eliminated check equation is c2. Assume that the current rate matching only uses the first check equation of c2, meaning that check bits 2 and 3 corresponding to c2 are punctured. In this case, the first check equation of c2 is used to eliminate the first check equation of c1, while the second and third check equations of c1 are not eliminated.

[0348] The fine-grained splitting helps maintain edge density, thereby helping to improve encoding and decoding performance.

[0349] In addition, it should be noted that if the row position adjustment and / or column position adjustment are performed in the process of obtaining the LDPC base matrix in step 602 based on method 1, the extended rows and / or extended columns satisfy: the X-x1 extended rows and / or Y-y2 extended columns are sorted in the splitting order, and the sorted extended rows and extended columns have the feature 3 described above.

[0350] Method 2: The transmitter stores the minimum code rate matrix (i.e., the stored matrix is ​​the minimum code rate matrix) and the indicator sequence, and splits the stored matrix based on the indicator sequence to generate the corresponding decoding check matrix, i.e., the LDPC base matrix in step 602 above.

[0351] Unlike method 1, method 2 does not store the partition table separately. Instead, the elimination check equations required for splitting are stored in the storage matrix. In other words, method 2 uses the rows with smaller row weights in the storage matrix to eliminate the rows with larger row weights in the storage matrix.

[0352] In mode 2, the indicator sequence may be a split sequence.

[0353] The description of splitting and splitting sequence can refer to method 1 and will not be repeated here.

[0354] The storage matrix in method 2 is described below.

[0355] Assume that the storage matrix is ​​an M×N matrix, the number of non-extended rows is m1, and the number of non-extended columns is n2.

[0356] The storage matrix includes submatrix A2, submatrix B2, submatrix C2, submatrix D2, and submatrix E2. Submatrix A2 is the 1st to m1th rows and 1st to n1th columns of the storage matrix, submatrix B2 is the 1st to m1th rows and n1+1 to n2th columns of the storage matrix, submatrix C2 is the 1st to m1th rows and n2+1 to Nth columns of the storage matrix, submatrix D2 is the m1+1 to Mth rows and 1st to n2th columns of the storage matrix, and submatrix E2 is the m1+1 to Mth rows and n2+1 to Nth columns of the storage matrix, where 1≤m1≤M, 1≤n1≤n2≤N, and m1, M, n1, n2, and N are all integers. Submatrix A2 and submatrix B2 constitute the core of the storage matrix.

[0357] The storage matrix has at least some of the following characteristics:

[0358] 1) The a1th row of the submatrix D2 is truly contained in the b1th row of the third submatrix and / or the a2th row of the submatrix D2, the third submatrix is ​​composed of the submatrix A2 and the submatrix B2, and the a1th row is any row of the submatrix D2;

[0359] In other words, the variable nodes (excluding the extended nodes) contained in the rows of the storage matrix other than the core part are truly contained in the variable nodes contained in their parent nodes.

[0360] The corresponding relationship between the a1th row and the b1th row, and the corresponding relationship between the a1th row and the a2th row can be determined according to the split sequence.

[0361] 2) The difference between the offset value of each non-zero element in row a1 and the offset value of the corresponding non-zero element in row b1 is the same, and / or the difference between the offset value of each non-zero element in row a1 and the offset value of the corresponding non-zero element in row b1 is the same;

[0362] In other words, the offset values ​​of the rows of the storage matrix excluding the core part differ from the offset values ​​of the corresponding positions of their parent nodes by a fixed constant. Optionally, the constant can be 0.

[0363] 3) The multiple rows in the submatrix D2 corresponding to the b2-th row of the third submatrix are different, and the b2-th row is any row of the third submatrix.

[0364] “A plurality of rows in the submatrix D2 corresponding to the b2-th row of the third submatrix” may refer to: all child nodes having the b2-th row of the third submatrix as a parent node.

[0365] For example, taking the first row of the third submatrix as an example, in the first round of splitting, the first row is split into the first row and the seventh row (that is, the seventh row is used to eliminate the elements of the first row). In the second round of splitting, the first row is split into the first row and the fourteenth row (that is, the fourteenth row is used to eliminate the elements of the first row), and the seventh row is split into the seventh row and the thirteenth row (that is, the thirteenth row is used to eliminate the elements of the seventh row). In this way, the seventh row, the thirteenth row, and the fourteenth row all correspond to the first row (a common parent node).

[0366] 4) The degree of the extended node of the storage matrix is ​​1;

[0367] 5) The rows of the storage matrix correspond one-to-one to the elements in the split sequence, that is, the number of rows of the storage matrix is ​​equal to the length of the split sequence;

[0368] 6) The core part of the storage matrix, i.e. A2 and B2, corresponds to the first segment of the split sequence and has no expansion nodes;

[0369] 7) The rows of the storage matrix corresponding to the first round of splitting, the second round of splitting, ... the tth round of splitting are stored, with the row weight decreasing, and the row weight decreases by 1 / 2 or approximately equal to 1 / 2 of the previous round in each round;

[0370] 8) The storage matrix can be directly used as the encoding matrix.

[0371] The Tanner graph corresponding to the storage matrix with the above characteristics contains a large number of 4- and 6-cycles, which is completely different from the existing check matrix.

[0372] In one possible implementation, the offset values ​​of each non-zero element of the storage matrix can be stored in a manner such that: the storage matrix is ​​used to store the connection relationship between the variable nodes and the check nodes, the offset values ​​of the non-zero elements of the storage matrix are obtained according to an offset value table, and the offset value table is used to store the offset values ​​of each position of the non-extended row of the storage matrix. In this case, the i3th row number in the at least one row number included in the splitting sequence indicates that the offset value of the i3th row of the LDPC base matrix is ​​determined based on the offset value of the row identified by the i3th row number in the at least one row number, and the row identified by the i3th row number in the at least one row number is the row to be split, and i3 is a positive integer. For example, if the 8th element of the splitting sequence indicates row number 3, it means that the 8th row of the LDPC base matrix is ​​used to eliminate the row with row number 3 of the LDPC base matrix, and the offset value of the 8th row is determined based on the offset value of the row with row number 3 of the LDPC base matrix.

[0373] In another possible implementation, the offset value of each non-zero element of the storage matrix may be directly stored in the storage matrix.

[0374] The following describes method 2 with reference to a specific example.

[0375] FIG15 is another schematic diagram of 1 split.

[0376] Assume that the low-rate matrix H0 is stored, with N=49 columns and M=16 rows, and H0 is shown in FIG15(a). Assume that the split sequence The first 6 positions of the split sequence (i.e., the first row) correspond to the initial matrix (i.e., the low-rate matrix H0), positions 7 to 12 (i.e., the second row) correspond to the first round of splitting, and positions 13 to 16 (i.e., the third row) correspond to the second round of splitting. The numbers in the second and third rows are a permutation of the row number to be split, so that each row number will only appear once in a round of splitting.

[0377] The first number in the second row of the split sequence is 2. The check matrix generated by the first split in the first round must be generated by using the seventh check equation (i.e., the seventh row of the storage matrix) to eliminate the second check equation (i.e., the second row of the storage matrix).

[0378] First, intercept 7 rows and 40 columns of the storage matrix, and check equations c2 and c7 as follows:

[0379] c2:x1+x2+x3+x4+x6+x7+x8+x9+x 10 +x 11 +x 12 +X13 +x 14 +x 15 +x 16 +x 17 +x 18 +x 23 +x 24 +x 32 +x 33 +x 35 +x 37 =0;

[0380] c7:x2+x3+x4+x7+x9+x 10 +x 11 +x 14 +x 15 +x 32 +x 37 +x 40 =0.

[0381] Perform XOR addition on c2 and c7 to obtain the new verification equation c′2: x1+x6+x8+x 12 +x 13 +x 16 +x 17 +x 18 +x 23 +x 24 +x 33 +x 35 +x 40 =0; replace c2 with c′2, and note that the expanded node x 40 Appears in c′2; the check equation matrix after splitting (H1) 7×40 As shown in Figure 15(b).

[0382] Sequentially use the 2nd, 3rd, 4th, 5th, and 6th elements of the 1st row of the split sequence to split and generate the matrix (H2) 8×41 …(H6) 12×45 , completing the first round of complete merging process; then go to the third row of the split sequence and perform the second round of splitting process.

[0383] In mode 2, the rate matching process based on the split sequence is similar to mode 1. The difference is that in mode 2, instead of obtaining information for constructing the elimination check equation from the partition table, the rows in the storage matrix are used as the elimination check equation.

[0384] For Z c The promoted rows are used as the R-th split of the granularity, which is similar to method 1 and is explained below with reference to FIG16 .

[0385] FIG16 is a schematic diagram of fine-grained rate matching.

[0386] Let Z c = 3. The storage matrix contains parity check equations c1 and c2. c1 is the parity check equation to be eliminated, and the elimination parity check equation is c2, that is, c1 is c1's parent. Assume that the current rate matching only uses the first parity check equation of c2, that is, parity check bits 2 to 3 corresponding to c2 are punctured. In this case, the first parity check equation of c2 is used to eliminate the first parity check equation of c1, and parity check equations 2 to 3 of c1 are not eliminated.

[0387] Figure 16 (a) shows c1 and c2 in the storage matrix, and Figure 16 (b) shows the Z c Schematic diagram of eliminating variables using the row before lifting as the granularity. Figure 16 (c) shows the Z c Schematic diagram of the lifted row as the granularity for elimination. As can be seen from Figure 16 (b) and (c), when it is necessary to puncture some check bits corresponding to the last column of the LDPC matrix, Z c Splitting the edge density for different granularities will result in a loss, while using 1 as the granularity helps to maintain the edge density, thereby helping to improve the performance of encoding and decoding.

[0388] In addition, it should be noted that if the row position adjustment and / or column position adjustment are performed in the process of obtaining the LDPC base matrix in step 602 based on method 2, the extended rows and / or extended columns satisfy: the X-x1 extended rows and / or Y-y2 extended columns are sorted in the splitting order, and the sorted extended rows and extended columns have the feature 3 described above.

[0389] Method 3: The transmitter stores the minimum code rate matrix (i.e., the stored matrix is ​​the minimum code rate matrix) and the indicator sequence, and combines the stored matrix based on the indicator sequence to generate the corresponding decoding check matrix, i.e., the LDPC base matrix in step 602 above.

[0390] In mode 3, the indication sequence may also be referred to as a merge sequence, and for ease of understanding, is referred to as the merge sequence hereinafter. The merge sequence is used to indicate the rows to be merged in the storage matrix, that is, the indication information is used to indicate the merge relationship between rows of the storage matrix.

[0391] The storage matrix and merging sequence in method 3 are described below.

[0392] 1) Storage matrix

[0393] The storage matrix in method 3 can be a low-rate matrix obtained by splitting the highest-rate matrix T times in advance according to method 1. Of course, the storage matrix can also be determined in advance using methods other than method 1, but the final matrix has the same characteristics as the low-rate matrix in method 1.

[0394] In one possible implementation, the storage matrix has at least some of the following features:

[0395] Feature A: The storage matrix includes a fourth submatrix and a fifth submatrix, the fourth submatrix includes non-extended columns of the storage matrix, and the fifth submatrix includes extended columns of the storage matrix; the column weight of each column in the P columns of the fifth submatrix is ​​2; one of the two non-zero elements contained in the p-th column in the P columns corresponds to the j1-th row of the first submatrix, and the other of the two non-zero elements contained in the p-th column in the P columns corresponds to the j2-th row of the first submatrix, the j1-th row and the j2-th row are orthogonal to each other, and the p-th column is any column in the P columns; wherein P, p, j1, and j2 are all positive integers.

[0396] In other words, the degree of some or all of the extended nodes of the storage matrix is ​​2, and the two rows corresponding to these extended nodes are orthogonal to each other except for the extended parts.

[0397] Feature B: The storage matrix is ​​an S×G matrix, the s1+1 to S rows of the storage matrix are extended rows, and the g2+1 to G columns of the storage matrix are extended columns; the storage matrix includes sub-matrix A3, sub-matrix B3, sub-matrix C3, sub-matrix D3 and sub-matrix E3, sub-matrix A3 is the 1 to s1 rows and 1 to g1 columns of the storage matrix, sub-matrix B3 is the 1 to s1 rows and g1+1 to g2 columns of the storage matrix, sub-matrix C3 is the 1 to s1 rows and g2+1 to G columns of the storage matrix, sub-matrix D3 is the s1+1 to S rows and 1 to g2 columns of the storage matrix, sub-matrix E3 is the s1+1 to S rows and g2+1 to G columns of the storage matrix, 1≤s1≤S, 1≤g1≤g2≤G, s1, S, g1, g2, G are all integers. The diagonal of the submatrix E3 is non-zero elements, the submatrix E3 includes non-zero elements above the diagonal and / or the submatrix E3 includes non-zero elements below the diagonal, and the submatrix C3 includes non-zero elements.

[0398] In addition, it should be noted that if the position of the rows and / or the position of the columns are adjusted in the process of obtaining the storage matrix, the expanded rows and / or expanded columns of the storage matrix satisfy: the S-s1 expanded rows and / or G-g2 expanded columns are sorted in the splitting order, and the sorted expanded rows and expanded columns have the above-mentioned feature B.

[0399] 2) Merge Sequences

[0400] The merging sequence may include multiple sub-information, and the order in which the multiple sub-information is arranged is the merging order. Each sub-information in the multiple sub-information is used to indicate two rows to be merged in the storage matrix.

[0401] Optionally, the sub-information may be the number of the expansion node, and the merged row may be the row corresponding to the expansion node. For the specific correspondence, see Feature A above. The number of the expansion node may refer to the numbering of only the expansion node. For example, if the storage matrix includes 10 expansion nodes, they may be numbered 1 to 10. The number of the expansion node may also refer to the numbering of all variable nodes. For example, if the storage matrix includes 28 variable nodes, including 4 expansion nodes, the numbers of the expansion nodes may be 25 to 28.

[0402] Optionally, the sub-information may be the number of the merged row. For example, when the 5th row and the 6th row of the storage matrix need to be merged, the sub-information may include the number of the 5th row and the number of the 6th row.

[0403] The following description will be made by taking the label of the extension node as an example. The label of the extension node is the label when numbering is performed only on the extension node.

[0404] In a possible implementation, multiple sub-information in the merge sequence are combined to form at least one segment, and each segment in the at least one segment corresponds to one round of merging.

[0405] Optionally, the number of the expanded column of the storage matrix corresponding to the sub-information included in at least one segment (ie, the number of the expanded node) may be a random value.

[0406] Optionally, the number of the expanded column (ie, the number of the expanded node) of the storage matrix corresponding to the sub-information included in at least one segment is related to the row weight of each row of the storage matrix.

[0407] Optionally, the number of the expanded column (ie, the number of the expanded node) of the storage matrix corresponding to the sub-information included in the t-th segment in at least one segment is {(2 T1-t -1)s1+1,…,(2 T-t+1 -1)s1} or the substitution form {(2 T1-t -1)s1+1,…,(2 T1-t+1 -1)s1}, T1 is the upper bound of the number of merging rounds, s1 is the number of non-expanded rows in the storage matrix, T1 and t are positive integers. The labels of the expanded nodes are the labels when only the expanded nodes are numbered.

[0408] Optionally, the t-th segment of the merge sequence corresponds to the t-th round of merging.

[0409] Since the sub-information corresponding to the segment of the t-th round of merging includes the expansion node numbered {(2 T1-t -1)s1+1,…,(2 T1-t+1 -1)s1} or the substitution form {(2 T1-t-1)s1+1,…,(2 T1-t+1 -1)s1}, therefore, multiple merges included in each round can be executed in parallel, which helps to improve the merge efficiency.

[0410] Assuming that each extended column of the storage matrix has the above feature A and the sub-information is the label of the extended node, the basic meaning of the merge sequence is as follows:

[0411] a) Length of the merge sequence: the total number of expanded nodes in the storage matrix.

[0412] b) Segmentation of the merge sequence: The merge sequence is segmented according to the number of merge rounds, and the t-th segment corresponds to the t-th merge round.

[0413] c) Meaning of the numbers in the merge sequence: The i-th position in the merge sequence corresponds to the expansion node corresponding to the i-th check equation to be merged in the storage matrix.

[0414] d) The order of the numbers in the combined sequence: The order of the high-rate matrix is ​​obtained by combining the storage matrices.

[0415] In one possible implementation, the merge sequence can be given by a calculation formula. Specifically, the element at position i in round t is, Where t2 satisfies s1 is the number of rows in the core part of the storage matrix, and T1 is the upper bound of the number of merges.

[0416] The following describes the merging process based on the merging sequence with a specific example.

[0417] FIG17 is a schematic diagram of one merge.

[0418] Assume that the stored low-rate matrix H0 has 40 columns and 16 rows, i.e., a code rate of 0.4, as shown in FIG17(a). Assume that the combined sequence The first row corresponds to the first round of merging. The numbers in the first row are a permutation of 5 to 12 (the numbers of the expansion nodes corresponding to the check equations to be merged in the current storage matrix). In this way, each number will only appear once in a round of merging. The first number in the first row is 7, which corresponds to the check equation for the first merge in the first round, which is the check equation corresponding to the 7th expansion node, that is, the following check equations c5 and c6 (the common expansion node included is the 7th expansion node x 35 ):

[0419] c5:x3+x8+x9+X 13 +x 23 +x 26 +x 30 +x 35 =0

[0420] c6:x2+x6+x 12 +x 16 +x 17 +x 22 +x 27 +x 35 =0

[0421] Perform XOR addition on c5 and c6 to obtain the new verification equation c′5: x2+x3+x6+x8+x9+x 12 +x 13 +x 16 +x 17 +x 22 +x 23 +x 26 +x 27 +x 30 = 0; replace c5 and c6 with c′5, noting that x 35 The extended nodes are eliminated, and the merged check equation matrix (H1) 15×39 As shown in Figure 17(b).

[0422] Subsequently, the 2nd, 3rd, 4th, 5th, 6th, 7th, and 8th elements of the 1st row of the merge sequence are used to merge and generate the matrix (H2) 14×38 …(H8) 8×32 , complete the first round of the complete merging process; then go to the second row of the merge sequence and perform the second round of merging process.

[0423] In addition, it should be noted that the low-rate matrix shown in FIG17( a ) is a matrix after the positions of the rows have been adjusted.

[0424] The above describes the combined sequence and the storage matrix. The following describes the rate matching process based on the combined sequence. Assume that the number of rows of the storage matrix is ​​S and the number of columns is G, S = 2 T1 s1, G=g2+(2 T1 -1)s1, where s1 is the number of rows in the core part of the storage matrix, g2 is the number of columns in the core part of the storage matrix, and T1 is the upper bound of the number of merges.

[0425] In one possible implementation, the rate matching process based on the combined sequence is mainly implemented by the following steps:

[0426] Step 1: Determine the number of rows X and columns Y of the LDPC basis matrix to be constructed according to the target code rate and target code length;

[0427] Step 2: Determine the merge according to the number of columns Y of the LDPC basis matrix, including the complete merge rounds 1, ..., t3-1 and the first i merges of the t3th round;

[0428] For example, select Z c The list satisfies KZ c The smallest Z ≥ K0 c , where K is the number of information columns of the LDPC basis matrix (that is, the number of information columns of the storage matrix), K0 is the number of information bits corresponding to the LDPC basis matrix (that is, the target number of information bits), and KZ c -K0+1 to KZ c The position is shortened; the number of merges W is determined, and W is the number that satisfies The maximum integer, where R0 is the target bit rate; then select t3, t3 is the maximum integer that satisfies 2 T1-t s1(2 t -1)≤W, which requires a complete merger of the first t3-1 rounds and the t3 round Merger.

[0429] Step 3, sequentially select W elements of the merge sequence to complete the complete merge of the first t3-1 rounds and the t3 round Merger.

[0430] Since the merge sequence has the permutation property described above, multiple merges in each merge round can be performed in parallel.

[0431] It should be pointed out that the above Z c The conditions that need to be met, such as t, W, and t3, are all exemplary and can be replaced by other achievable conditions.

[0432] It should also be noted that the W merges can be divided into multiple merge rounds as described above, and the multiple merges in each merge round are performed in parallel. Of course, the W merges can also be performed sequentially or serially. In this case, the merge sequence can be unsegmented. After determining the number of merges W, the first W sub-information of the merge sequence can be obtained based on W, and then the W merges can be performed sequentially.

[0433] Similar to splitting, for the first W-1 merges among the W merges above, Z c The rows before promotion are merged as granularity, in other words, in QC structure or Z c As the granularity for merging; for the Wth merge, that is, the last merge, Z c The rows before promotion are merged as granularity, or Z c The promoted row (i.e. 1) is used as the granularity for merging. For example, when the check bits corresponding to the last column of the LDPC matrix are punctured, the Wth merging can be done with Z cThe promoted row is used as the granularity. For another example, combined with the above, assuming that WZc-N0 can correspond to the puncture position of the largest-numbered extended node, for (W-1)Z c -N0 is merged with a granularity of 1, where N0 is the target code length.

[0434] Mode 4: The transmitter stores the lowest code rate matrix (ie, the stored matrix is ​​the lowest code rate matrix), the offset value table, and the indicator sequence, and reads the stored matrix and the offset value table based on the indicator sequence to obtain the LDPC base matrix to be used.

[0435] The storage matrix is ​​used to store the connection relationship between the variable nodes and the check nodes. The offset values ​​of the non-zero elements of the storage matrix are obtained according to an offset value table. The offset value table is used to store the offset values ​​of each position of the non-extended row of the storage matrix. The indicator sequence includes at least one row number, the i3th row number in the at least one row number indicates that the offset value of the i3th row of the LDPC base matrix is ​​determined based on the offset value of the row identified by the i3th row number in the at least one row number, and i3 is a positive integer.

[0436] For example, the desired LDPC base matrix is ​​a matrix with 7 rows and 29 columns. The storage matrix stores the connection relationships between each variable node and each check node. The offset value table stores the offset values ​​for each position in the core portion of the 6 rows and 28 columns, indicating that the 7th row of the sequence is numbered 2. For the 7th row of the LDPC base matrix, the transmitter can determine the offset value for the 7th row from the offset value corresponding to the 2nd row of the storage matrix in the offset value table based on the connection relationship of the 7th row of the storage matrix.

[0437] That is, the LDPC base matrix used for encoding is obtained by reading the stored matrix and offset value table according to the indication sequence.

[0438] The description of the storage matrix can refer to Method 2 and the description of the indication sequence can refer to Method 1, which will not be repeated here.

[0439] In mode 4, the rate matching process is similar to that in mode 1 and will not be described in detail.

[0440] The present application also provides another communication method based on LDPC codes, in which the degree of some or all of the extended nodes of the storage matrix is ​​2, and the two rows corresponding to these extended nodes are orthogonal to each other except for the extended parts. Therefore, the merging effect can be achieved by punching these extended nodes, thereby achieving a transition from low code rate to high code rate.

[0441] The communication method based on LDPC codes is described below.

[0442] FIG18 is a schematic flowchart of a communication method 1800 based on LDPC codes provided in the present application.

[0443] Method 1800 may be executed by a transmitting end and a receiving end, or by modules or units in the transmitting end and the receiving end. For ease of description, the transmitting end and the receiving end are collectively referred to as the transmitting end and the receiving end. Method 1800 may include at least part of the following contents.

[0444] Step 1801: The transmitting end obtains an information bit sequence.

[0445] That is, if the sending end needs to communicate with the receiving end, that is, the sending end needs to send a signal to the receiving end, the sending end needs to first obtain the information bit sequence corresponding to the signal to be sent to the receiving end.

[0446] Optionally, the transmitting end obtaining the information sequence to be transmitted may refer to: the transmitting end performing source encoding on source symbols to generate an information bit sequence. The transmitting end obtaining the information sequence to be transmitted may also refer to: the transmitting end receiving the information bit sequence from another communication device.

[0447] In step 1802, the transmitter performs LDPC encoding on the information bit sequence according to the LDPC base matrix to obtain an LDPC codeword sequence.

[0448] The LDPC base matrix is ​​the matrix stored at the transmitter, also known as the storage matrix. The storage matrix can be a low-rate matrix obtained by pre-split-ing the highest-rate matrix T times according to Method 1. The storage matrix can also be determined in advance using methods other than Method 1. However, the resulting matrix shares the same characteristics as the low-rate matrix in Method 1.

[0449] In one possible implementation, the storage matrix has at least some of the following features:

[0450] Feature A: The storage matrix includes a fourth submatrix and a fifth submatrix, the fourth submatrix includes non-extended columns of the storage matrix, and the fifth submatrix includes extended columns of the storage matrix; the column weight of each column in the P columns of the fifth submatrix is ​​2; one of the two non-zero elements contained in the p-th column in the P columns corresponds to the j1-th row of the first submatrix, and the other of the two non-zero elements contained in the p-th column in the P columns corresponds to the j2-th row of the first submatrix, the j1-th row and the j2-th row are orthogonal to each other, and the p-th column is any column in the P columns; wherein P, p, j1, and j2 are all positive integers.

[0451] In other words, the degree of some or all of the extended nodes of the storage matrix is ​​2, and the two rows corresponding to these extended nodes are orthogonal to each other except for the extended parts.

[0452] Feature B: The storage matrix is ​​an S×G matrix, the s1+1 to S rows of the storage matrix are extended rows, and the g2+1 to G columns of the storage matrix are extended columns; the storage matrix includes sub-matrix A3, sub-matrix B3, sub-matrix C3, sub-matrix D3 and sub-matrix E3, sub-matrix A3 is the 1 to s1 rows and 1 to g1 columns of the storage matrix, sub-matrix B3 is the 1 to s1 rows and g1+1 to g2 columns of the storage matrix, sub-matrix C3 is the 1 to s1 rows and g2+1 to G columns of the storage matrix, sub-matrix D3 is the s1+1 to S rows and 1 to g2 columns of the storage matrix, sub-matrix E3 is the s1+1 to S rows and g2+1 to G columns of the storage matrix, 1≤s1≤S, 1≤g1≤g2≤G, s1, S, g1, g2, G are all integers. The diagonal of the submatrix E3 is non-zero elements, the submatrix E3 includes non-zero elements above the diagonal and / or the submatrix E3 includes non-zero elements below the diagonal, and the submatrix C3 includes non-zero elements.

[0453] In addition, it should be noted that if the position of the rows and / or the position of the columns are adjusted in the process of obtaining the storage matrix, the expanded rows and / or expanded columns of the storage matrix satisfy: the S-s1 expanded rows and / or G-g2 expanded columns are sorted in the splitting order, and the sorted expanded rows and expanded columns have the above-mentioned feature B.

[0454] In step 1803 , the transmitting end sends the second LDPC codeword sequence to the receiving end according to the indication information, or in other words, the receiving end receives the second LDPC codeword sequence from the transmitting end.

[0455] This application does not limit the specific form of the indication information. In one possible implementation, the form of the indication information may include: an indication sequence, a mapping table, or at least one of a mapping pair. For details, please refer to the description in Figure 6, which will not be repeated here. Similarly, for the convenience of description, the following describes the technical solution of this application using the indication sequence as an example, wherein the indication sequence can be replaced by an equivalent mapping table or mapping pair.

[0456] The indicator sequence can also be called a puncture sequence. For ease of understanding, it is referred to as the puncture sequence below. The puncture sequence is used to indicate the extended columns in the storage matrix that are punctured. It should be noted that the extended columns in the storage matrix that are punctured here belong to the P columns mentioned in Feature A above.

[0457] The second LDPC codeword sequence sent by the transmitter includes codewords in the first LDPC codeword sequence except for the codewords corresponding to the punctured extended columns of the storage matrix. In other words, the second LDPC codeword does not include the codewords in the first LDPC codeword sequence corresponding to the punctured extended columns of the storage matrix.

[0458] When some or all of the extended columns of the storage matrix are punctured, the storage matrix itself remains unchanged. However, because the column with degree 2 is punctured, the XOR result of the two check equations corresponding to that column (i.e., the two rows of the storage matrix) is 0, which is equivalent to merging the two rows. In this way, puncturing can achieve the merging effect shown in Method 3 above.

[0459] The puncturing sequence is described below.

[0460] The puncturing sequence is similar to the above-mentioned merging sequence and may include multiple sub-information, and the arrangement order of the multiple sub-information is the puncturing sequence. Each sub-information in the multiple sub-information is used to indicate the extended column to be punctured in the memory matrix.

[0461] Optionally, the sub-information may be the number of the expansion node. The number of the expansion node may refer to the numbering of only the expansion nodes. For example, if the storage matrix includes 10 expansion nodes, the numbers thereof may be 1 to 10. The number of the expansion node may also refer to the numbering of all variable nodes. For example, if the storage matrix includes 28 variable nodes, including 4 expansion nodes, the numbers of the expansion nodes may be 25 to 28.

[0462] The following description takes the case where the label of the extended node is numbered only for the extended node as an example.

[0463] In a possible implementation, multiple sub-information in the puncturing sequence constitute at least one segment, and each segment in the at least one segment corresponds to a round of puncturing.

[0464] Optionally, the number of the expanded column of the storage matrix corresponding to the sub-information included in at least one segment (ie, the number of the expanded node) may be a random value.

[0465] Optionally, the number of the expanded column (ie, the number of the expanded node) of the storage matrix corresponding to the sub-information included in at least one segment is related to the row weight of each row of the storage matrix.

[0466] Optionally, the number of the expanded column (ie, the number of the expanded node) of the storage matrix corresponding to the sub-information included in the t-th segment in at least one segment is {(2 T2-t -1)s1+1,…,(2 T2-t+1 -1)s1} or the substitution form {(2 T2-t -1)s1+1,…,(2 T2-t+1 -1)s1}, T2 is the upper bound of the number of puncturing rounds, s1 is the number of non-extended rows of the storage matrix, and T2 and t are positive integers.

[0467] Optionally, the tth segment of the puncturing sequence corresponds to the tth round of puncturing.

[0468] Since the sub-information corresponding to the segment of the t-th round of punching includes the extension node numbered {(2 T2-t -1)s1+1,…,(2 T2-t+1 -1)s1} or the substitution form {(2 T2-t -1)s1+1,…,(2 T-t+1 -1)s1}, therefore, multiple puncturing operations in each round can be performed in parallel, which helps to improve the puncturing efficiency.

[0469] Assuming that each extended column of the storage matrix has the above feature A, the basic meaning of the puncturing sequence is as follows:

[0470] a) Length of the puncturing sequence: the total number of extended nodes in the storage matrix.

[0471] b) Segmentation of the puncturing sequence: The puncturing sequence is segmented according to the number of puncturing rounds, and the t-th segment corresponds to the t-th puncturing round.

[0472] c) Meaning of the numbers in the puncture sequence: The i-th position in the puncture sequence corresponds to the number of the i-th expansion node of the storage matrix to be punctured.

[0473] d) The order of the numbers in the puncturing sequence: the order of the high-rate matrix obtained by puncturing the storage matrix.

[0474] In one possible implementation, the punching sequence can be given by a calculation formula. Specifically, the element at position i in round t is Where t4 satisfies , s1 is the number of rows in the core part of the storage matrix, and T2 is the upper bound of the number of puncturing times.

[0475] The rate matching process based on the puncturing sequence is described below.

[0476] Assume the number of rows of the storage matrix is ​​S and the number of columns is G, S = 2 T2 s1, G=g2+(2 T2 -1)s1, where s1 is the number of rows in the core part of the storage matrix, g2 is the number of columns in the core part of the storage matrix, and T2 is the upper bound of the number of puncturing times.

[0477] In one possible implementation, the rate matching process based on the puncturing sequence is mainly implemented by the following steps:

[0478] Step 1: Determine the puncturing process based on the target bit rate and target code length, including the number of complete puncturing rounds 1, ..., t5-1 and the first i puncturing rounds of the t5th round.

[0479] For example, select Z c The list satisfies KZc The smallest Z ≥ K0 c , where K is the number of information columns of the LDPC matrix (that is, the number of information columns of the storage matrix), K0 is the target number of information bits, and KZ c -K0+1 to KZ c The position is shortened; the number of punching times J is determined, and J is to meet The maximum integer, where R0 is the target bit rate; then select t5, t5 is the maximum integer that satisfies 2 T2-t s1(2 t -1)≤J, which requires the first t5-1 rounds of complete punching and the t5 round Punch a hole.

[0480] Step 3, sequentially select J elements of the punch sequence to complete the first t5-1 rounds of complete punching and the t5 rounds of complete punching. Punch a hole.

[0481] Since the puncturing sequence has the permutation property described above, multiple puncturing operations in each round can be performed in parallel.

[0482] It should be pointed out that the above Z c The conditions that need to be met, such as , J, t5, etc., are all exemplary and can be replaced by other achievable conditions.

[0483] It should also be noted that the J rounds of puncturing can be divided into multiple rounds as described above, with the multiple puncturing rounds in each round being performed in parallel. Of course, the J rounds of puncturing can also be performed sequentially or serially. In this case, the puncturing sequence can be non-segmented. After determining the number of puncturing times J, the first J sub-information of the puncturing sequence can be obtained based on J, and then the J rounds of puncturing can be performed sequentially. The J rounds of puncturing can also be performed in one go. The puncturing sequence can also be non-segmented. After determining the number of puncturing times J, the first J sub-information of the puncturing sequence can be obtained based on J, and then the J extended nodes can be punctured in one go.

[0484] Similar to splitting, for the first J-1 punches in the above J punches, Z c The rows before lifting are used as the granularity for punching, in other words, in the QC structure or Z c Punch as the granularity; for the Jth punch, that is, the last punch, Z c The row before promotion is used as the granularity for punching, or Z c The promoted row (i.e. 1) is used as the granularity for punching. c When the promoted row is used as the granularity for puncturing, it is possible to puncture part of the check bits corresponding to the last punctured column.

[0485] Step 1804: The receiving end decodes the second LDPC codeword according to the puncturing sequence and the LDPC base matrix.

[0486] Specifically, the receiving end may pad the corresponding positions of the LLR sequence corresponding to the second LDPC codeword with zeros according to the puncturing sequence, and decode the LLR sequence after the zero padding, wherein the corresponding positions of the LLR sequence are the positions indicated by the puncturing sequence.

[0487] The puncturing sequence, LDPC base matrix, and rate matching process based on the puncturing sequence used by the receiving end are the same as those of the transmitting end. Please refer to the description of the transmitting end and will not be repeated here.

[0488] The following describes the puncturing sequence, storage matrix, and their usage with reference to a specific example.

[0489] Assume that the stored low code rate matrix H0 has 40 columns G and 16 rows S, i.e. the code rate is 0.4, as shown in FIG17 (a). Assume that the puncturing sequence The first row corresponds to the first round of punching. The numbers in the first row are a permutation of 5 to 12 (the numbers of the expansion nodes to be punched in the current storage matrix). In this way, each number will only appear once in a round of punching. The first number in the first row is 7, and the expansion node corresponding to the first punching in the first round is the 7th expansion node x. 35 .

[0490] Note that the 7th expansion node x 35 After the node is expanded and punched, the storage matrix itself does not change, but due to x 35 The degree is 2, and x 35 The corresponding check equations c5 and c6 are equivalent to This is equivalent to merging c5 and c6. Subsequently, the storage matrix is ​​punctured using the 2nd, 3rd, 4th, 5th, 6th, 7th, and 8th elements of the 1st row of the puncture sequence, completing the first round of puncturing. The next round of puncturing is performed on the 2nd row of the puncture sequence.

[0491] It should be noted that the above embodiments of the present application can be implemented independently or combined together in an appropriate manner, and the present application is not limited thereto.

[0492] The above describes in detail the method provided by the present application in conjunction with Figures 6 to 18 , and the following describes in detail an embodiment of the device of the present application in conjunction with Figures 19 to 20 .

[0493] It is understood that, in order to implement the functions in the above embodiments, the apparatus in FIG. 19 or FIG. 20 includes hardware structures and / or software modules corresponding to the functions. Those skilled in the art should readily appreciate that, in conjunction with the various exemplary units and method steps described in the embodiments disclosed herein, the present application can be implemented in the form of hardware or a combination of hardware and computer software.

[0494] Figures 19 and 20 are schematic diagrams of possible devices provided by embodiments of the present application. These devices can be used to implement the functions of the transmitter or receiver in the above method embodiments, thereby also achieving the beneficial effects of the above method embodiments.

[0495] As shown in FIG19 , the device 10 includes a transceiver unit 11 and a processing unit 12 .

[0496] In some implementations:

[0497] When the device 10 is used to implement the function of the transmitting end in the above-mentioned method embodiment, the transceiver unit 11 is used to obtain an information bit sequence. The processing unit 12 is used to perform LDPC encoding on the information bit sequence according to the LDPC base matrix to obtain an LDPC codeword sequence, wherein the LDPC base matrix is ​​obtained based on a storage matrix and indication information, and the indication information is used to indicate the correspondence between rows of the storage matrix or the correspondence between rows of the LDPC base matrix, and the sum of the column weights of the non-extended columns of the LDPC base matrix is ​​equal to the sum of the column weights of the non-extended columns of the storage matrix. The transceiver unit 11 is also used to send the LDPC codeword sequence.

[0498] When the device 10 is used to implement the function of the receiving end in the above method embodiment, the transceiver unit 11 is used to: receive an LDPC codeword sequence from the transmitting end; and decode the LDPC codeword sequence according to an LDPC base matrix, wherein the LDPC base matrix is ​​obtained based on a storage matrix and indication information, and the indication information is used to indicate the correspondence between rows of the storage matrix or the correspondence between rows of the LDPC base matrix, and the sum of the column weights of the non-extended columns of the LDPC base matrix is ​​equal to the sum of the column weights of the non-extended columns of the storage matrix.

[0499] Optionally, a code rate corresponding to the LDPC base matrix is ​​different from a code rate corresponding to the storage matrix.

[0500] Optionally, the LDPC base matrix includes a first submatrix and a second submatrix, the first submatrix includes non-extended columns of the LDPC base matrix, and the second submatrix includes extended columns of the LDPC base matrix; the column weight of each column in the Q columns of the second submatrix is ​​2; one of the two non-zero elements contained in the qth column in the Q columns corresponds to the i1th row of the first submatrix, and the other of the two non-zero elements contained in the qth column in the Q columns corresponds to the i2th row of the first submatrix, the i1th row and the i2th row are orthogonal to each other, and the qth column is any column in the Q columns; wherein Q, q, i1, and i2 are all positive integers.

[0501] Optionally, the LDPC base matrix is ​​an X×Y matrix, and the y2+1 to Y columns of the LDPC base matrix are extended columns; the LDPC base matrix includes submatrix A1, submatrix B1, submatrix C1, submatrix D1 and submatrix E1, the submatrix A1 is the 1st to x1 rows and 1st to y1 columns of the LDPC base matrix, the submatrix B1 is the 1st to x1 rows and y1+1 to y2 columns of the LDPC base matrix, and the submatrix C1 is the 1st to x1 rows and y2+1 to Y columns, the submatrix D1 is the x1+1 to X rows and the 1 to y2 columns of the LDPC base matrix, the submatrix E1 is the x1+1 to X rows and the y2+1 to Y columns of the LDPC base matrix, 1≤x1≤X, 1≤y1≤y2≤Y, x1, X, y1, y2, Y are all integers; wherein, the diagonal of the submatrix E1 is non-zero elements, the submatrix E1 includes non-zero elements above the diagonal and / or the submatrix E1 includes non-zero elements below the diagonal, and the submatrix C1 includes non-zero elements.

[0502] Optionally, the indication information is in a form including at least one of an indication sequence, a mapping table, or a mapping pair.

[0503] Optionally, the indication information is used to indicate the correspondence between rows of the LDPC base matrix, the storage matrix is ​​used to store the connection relationship between variable nodes and check nodes, the offset values ​​of the non-zero elements of the storage matrix are obtained according to the offset value table, and the offset value table is used to store the offset values ​​of each position of the non-extended row of the storage matrix.

[0504] Optionally, the indication information is in the form of an indication sequence, and the LDPC base matrix is ​​obtained by reading the storage matrix and the offset value table according to the indication sequence, the indication sequence includes at least one row number, and the i3th row number in the at least one row number indicates that the offset value of the i3th row of the LDPC base matrix is ​​determined based on the offset value of the row identified by the i3th row number in the at least one row number, and i3 is a positive integer.

[0505] Optionally, the indication information is in the form of an indication sequence, and the LDPC base matrix is ​​obtained by splitting the storage matrix according to the indication sequence. The indication sequence includes at least one row number, and the m1+r-th row number in the at least one row number indicates the m1+r-th row of the LDPC base matrix, which is used to perform elimination processing on the row identified by the m1+r-th row number in the at least one row number. The sorting order of the at least one row number is the splitting order, m1 is the number of non-extended rows of the storage matrix, and r is a positive integer.

[0506] Optionally, the at least one row number includes at least one segment, each segment in the at least one segment corresponds to a round of splitting, and the row number in the segment corresponding to the t-th round of splitting in at least one round of splitting corresponding to the at least one segment is {1, ..., 2 t-1 m1} or {1, ..., 2 t-1 m1}, where t is a positive integer.

[0507] Optionally, the storage matrix is ​​an M×N matrix, and the m1+1 to Mth rows of the storage matrix are extended rows; the storage matrix includes submatrix A2, submatrix B2, submatrix C2, submatrix D2 and submatrix E2, the submatrix A2 is the 1st to m1th rows and 1st to n1th columns of the storage matrix, the submatrix B2 is the 1st to m1th rows and n1+1 to n2th columns of the storage matrix, the submatrix C2 is the 1st to m1th rows and n2+1 to Nth columns of the storage matrix, and the submatrix D2 is the The m1+1 to Mth rows and the 1 to n2th columns of the storage matrix, the submatrix E2 is the m1+1 to Mth rows and the n2+1 to Nth columns of the storage matrix, 1≤m1≤M, 1≤n1≤n2≤N, m1, M, n1, n2, N are all integers; wherein, the a1th row of the submatrix D2 is truly included in the b1th row of the third submatrix and / or the a2th row of the submatrix D2, the third submatrix is ​​composed of the submatrix A2 and the submatrix B2, and the a1th row is any row of the submatrix D2.

[0508] Optionally, the difference between the offset value of each non-zero element in the a1th row and the offset value of the non-zero element at the corresponding position in the b1th row is the same, and / or the difference between the offset value of each non-zero element in the a1th row and the offset value of the non-zero element at the corresponding position in the b1th row is the same.

[0509] Optionally, the multiple rows in the submatrix D2 corresponding to the b2th row of the third submatrix are different, and the b2th row is any row of the third submatrix.

[0510] Optionally, the correspondence between the a1th row and the b1th row, and the correspondence between the a1th row and the a2th row are determined according to the indication information.

[0511] Optionally, the processing unit 12 is also used to: determine the number of splits R based on the code length corresponding to the LDPC base matrix, the number of information bits corresponding to the LDPC base matrix, and the number of information columns of the LDPC base matrix; split the storage matrix R times to obtain the LDPC base matrix; wherein the r-th split in the R splits includes the following operations: obtaining the m1+r-th row number of the indication sequence; using the m1+r-th row of the storage matrix to perform elimination processing on the rows in the storage matrix corresponding to the m1+r-th row number; wherein m1 is the number of non-extended rows of the storage matrix, the r-th split is any one of the R splits, and r is a positive integer.

[0512] Optionally, the storage matrix does not include an extended column.

[0513] Optionally, the LDPC base matrix is ​​obtained based on the storage matrix, the indicator sequence and a partition table, wherein a row in the partition table is used to construct an extended row of the LDPC base matrix.

[0514] Optionally, the processing unit 12 is also used to: determine the number of splits R according to the code length corresponding to the LDPC base matrix, the number of information bits corresponding to the LDPC base matrix, and the number of information columns of the LDPC base matrix; split the storage matrix R times to obtain the LDPC base matrix; wherein the r-th split in the R splits includes the following operations: obtaining the r-th row of the partition table, and constructing the r-th extended row of the storage matrix based on the r-th row; obtaining the M+r-th row number of the indication sequence; using the r-th extended row to perform elimination processing on the k-th row, the k-th row being the row corresponding to the M+r-th row number in the storage matrix or the first r-1 extended rows of the storage matrix; wherein M is the number of rows of the storage matrix, the r-th split is any one of the R splits, and r is a positive integer.

[0515] Optionally, the R satisfies RZ c The smallest integer ≥N0-K0; where Z c is the improvement value, and Z c Z c The list satisfies KZ c The smallest Z ≥ K0 c ; N0 is the code length corresponding to the LDPC base matrix; K0 is the number of information bits corresponding to the LDPC base matrix; K is the number of information columns of the LDPC base matrix.

[0516] Optionally, if some check bits corresponding to the last column of the LDPC matrix are punctured, the last split of the R splits is Z c The promoted row is used as the granularity; where Z c is the improvement value, and Z c Z c The list satisfies KZ c The smallest Z ≥ K0 c ; K0 is the number of information bits corresponding to the LDPC base matrix; K is the number of information columns of the LDPC base matrix.

[0517] Optionally, the indication information is in the form of an indication sequence, and the LDPC base matrix is ​​obtained by merging the storage matrix according to the indication sequence. The indication sequence includes multiple sub-information, and each sub-information in the multiple sub-information is used to indicate two rows to be merged in the storage matrix. The arrangement order of the sub-information is the merging order.

[0518] Optionally, the plurality of sub-information include at least one segment, each segment in the at least one segment corresponds to one round of merging, and the label of the extended column of the storage matrix corresponding to the sub-information included in the t-th segment in the at least one segment is {(2 T-t -1)s1+1,…,(2 T-t+1 -1)s1} or the substitution form {(2 T-t -1)s1+1,…,(2 T-t+1 -1)s1}, T is the upper bound of the number of merging rounds, s1 is the number of non-extended rows of the storage matrix, and T and t are positive integers.

[0519] Optionally, the storage matrix includes a fourth submatrix and a fifth submatrix, the fourth submatrix includes non-extended columns of the storage matrix, and the fifth submatrix includes extended columns of the storage matrix; the column weight of each column in the P columns of the fifth submatrix is ​​2; one of the two non-zero elements contained in the p-th column in the P columns corresponds to the j1-th row of the first submatrix, and the other of the two non-zero elements contained in the p-th column in the P columns corresponds to the j2-th row of the first submatrix, the j1-th row and the j2-th row are orthogonal to each other, and the p-th column is any column in the P columns; wherein P, p, j1, and j2 are all positive integers.

[0520] Optionally, the storage matrix is ​​an S×G matrix, the s1+1 to S rows of the storage matrix are extended rows, and the g2+1 to G columns of the storage matrix are extended columns; the storage matrix includes submatrix A3, submatrix B3, submatrix C3, submatrix D3 and submatrix E3, the submatrix A3 is the 1st to s1 rows and 1st to g1 columns of the storage matrix, the submatrix B3 is the 1st to s1 rows and g1+1 to g2 columns of the storage matrix, and the submatrix C3 is the 1st to s1 rows and g1+1 to g2 columns of the storage matrix. 2+1~G columns, the submatrix D3 is the s1+1~S rows and the 1~g2 columns of the storage matrix, the submatrix E3 is the s1+1~S rows and the g2+1~G columns of the storage matrix, 1≤s1≤S, 1≤g1≤g2≤G, s1, S, g1, g2, G are all integers; wherein, the diagonal of the submatrix E3 is non-zero elements, the submatrix E3 includes non-zero elements above the diagonal and / or the submatrix E3 includes non-zero elements below the diagonal, and the submatrix C3 includes non-zero elements.

[0521] Optionally, the processing unit 12 is also used to: determine the number of mergers W based on the code rate corresponding to the LDPC base matrix, the number of information columns of the LDPC base matrix, the number of non-extended rows of the storage matrix, the number of non-extended columns of the storage matrix, and the upper bound T of the number of merging rounds; merge the storage matrix W times to obtain the LDPC base matrix; wherein the w-th merger in the W splits includes the following operations: obtaining the w-th sub-information of the indication sequence; merging the two rows indicated by the w-th sub-information; wherein the w-th merger is any one of the W mergers, and w is a positive integer.

[0522] Optionally, W satisfies wherein R0 is the code rate corresponding to the LDPC base matrix; K is the number of information columns of the LDPC base matrix; s1 is the number of non-extended rows of the storage matrix; g1 is the number of non-extended columns of the storage matrix; and T1 is the upper bound of the number of merging rounds.

[0523] Optionally, if some check bits corresponding to the last column of the LDPC basis matrix are punctured, the last merging of the W mergings is performed with Z c The promoted row is used as the granularity; where Z c is the improvement value, and Z c Z c The list satisfies KZ c The smallest Z ≥ K0 c ; K0 is the number of information bits corresponding to the LDPC base matrix; K is the number of information columns of the LDPC base matrix.

[0524] In other implementations:

[0525] When the device 10 is used to implement the function of the transmitting end in the above-mentioned method embodiment, the transceiver unit 11 is used to: obtain an information bit sequence. The processing unit 12 is used to: perform LDPC encoding on the information bit sequence according to the storage matrix to obtain a first LDPC codeword sequence, wherein the storage matrix includes a fourth submatrix and a fifth submatrix, the fourth submatrix includes non-extended columns of the storage matrix, and the fifth submatrix includes extended columns of the storage matrix; each column in the P columns of the fifth submatrix has a column weight of 2; one of the two non-zero elements contained in the p-th column of the P columns corresponds to the j1-th row of the first submatrix, and the other of the two non-zero elements contained in the p-th column of the P columns corresponds to the j2-th row of the first submatrix, the j1-th row and the j2-th row are mutually orthogonal, and the p-th column is any column in the P columns; wherein P, p, j1, and j2 are all positive integers. The transceiver unit 11 is also used to: send a second LDPC codeword sequence according to the indication information, where the indication information is used to indicate the punctured columns in the fifth sub-matrix, and the second LDPC codeword sequence includes codewords in the first LDPC codeword sequence except for the codewords corresponding to the punctured columns in the fifth sub-matrix.

[0526] When the device 10 is used to implement the function of the transmitting end in the above method embodiment, the transceiver unit 11 is used to receive the LDPC codeword sequence from the transmitting end. The processing unit 12 is configured to decode the LDPC codeword sequence according to the storage matrix and the indication information, wherein the storage matrix includes a fourth submatrix and a fifth submatrix, the fourth submatrix includes non-extended columns of the storage matrix, and the fifth submatrix includes extended columns of the storage matrix; each of the P columns in the fifth submatrix has a column weight of 2; one of the two non-zero elements included in the p-th column in the P columns corresponds to the j1-th row of the first submatrix, the other of the two non-zero elements included in the p-th column in the P columns corresponds to the j2-th row of the first submatrix, the j1-th row and the j2-th row are mutually orthogonal, the p-th column is any column in the P columns, and P, p, j1, and j2 are all positive integers; the indication information is used to indicate a punctured column in the fifth submatrix, and the second LDPC codeword sequence includes codewords in the first LDPC codeword sequence other than codewords corresponding to the punctured columns in the fifth submatrix.

[0527] Optionally, the storage matrix is ​​an S×G matrix, the s1+1 to S rows of the storage matrix are extended rows, and the g2+1 to G columns of the storage matrix are extended columns; the storage matrix includes submatrix A3, submatrix B3, submatrix C3, submatrix D3 and submatrix E3, the submatrix A3 is the 1st to s1 rows and 1st to g1 columns of the storage matrix, the submatrix B3 is the 1st to s1 rows and g1+1 to g2 columns of the storage matrix, and the submatrix C3 is the 1st to s1 rows and g1+1 to g2 columns of the storage matrix. 2+1~G columns, the submatrix D3 is the s1+1~S rows and the 1~g2 columns of the storage matrix, the submatrix E3 is the s1+1~S rows and the g2+1~G columns of the storage matrix, 1≤s1≤S, 1≤g1≤g2≤G, s1, S, g1, g2, G are all integers; wherein, the diagonal of the submatrix E3 is non-zero elements, the submatrix E3 includes non-zero elements above the diagonal and / or the submatrix E3 includes non-zero elements below the diagonal, and the submatrix C3 includes non-zero elements.

[0528] Optionally, the indication information is in a form including at least one of an indication sequence, a mapping table, or a mapping pair.

[0529] Optionally, the indication information is in the form of an indication sequence, the indication sequence includes multiple sub-information, each of the multiple sub-information is used to indicate a column in the extended column of the storage matrix, and the arrangement order of the multiple sub-information is a puncturing order.

[0530] Optionally, the plurality of sub-information include at least one segment, each segment in the at least one segment corresponds to a round of puncturing, and the number of the extended column indicated by the sub-information included in the t-th segment in the at least one segment is {(2 T-t -1)s1+1,…,2 T-t+1 -1)s1} or the substitution form {(2 T-t -1)s1+1,…,2 T-t+1 -1)s1}, T is the upper bound of the number of merging rounds, s1 is the number of non-extended rows of the storage matrix, and T and t are positive integers.

[0531] Optionally, the number J of sub-information included in the indication sequence satisfies wherein R0 is the target bit rate; K is the target number of information columns; s1 is the number of non-extended rows of the storage matrix; g2 is the number of non-extended columns of the storage matrix; and T2 is the upper bound of the number of merging rounds.

[0532] For a more detailed description of the transceiver unit 11 and the processing unit 12 , please refer to the relevant description in the above method embodiment, which will not be described again here.

[0533] As shown in FIG20 , the apparatus 20 includes a processor 21. The processor 21 is coupled to a memory 23, which is used to store instructions. When the apparatus 20 is used to implement the method described above, the processor 21 is used to execute the instructions in the memory 23 to implement the functions of the processing unit 12 described above.

[0534] Optionally, the device 20 further includes a memory 23 .

[0535] Optionally, the apparatus 20 further includes an interface circuit 22. The processor 21 and the interface circuit 22 are coupled to each other. It will be appreciated that the interface circuit 22 may be a transceiver or an input / output interface. When the apparatus 20 is used to implement the method described above, the processor 21 is configured to execute instructions to implement the functions of the processing unit 12, and the interface circuit 22 is configured to implement the functions of the transceiver unit 11.

[0536] Exemplarily, when device 20 is a chip applied to a transmitter or receiver, the chip implements the functions of the transmitter or receiver in the above-described method embodiments. The chip receives information from other modules (such as a radio frequency module or antenna) in the transmitter or receiver, where the information is sent to the transmitter or receiver by other devices; or the chip sends information to other modules (such as a radio frequency module or antenna) in the transmitter or receiver, where the information is sent to other devices by the transmitter or receiver.

[0537] The present application also provides a communication device, comprising a processor coupled to a memory, the memory being configured to store computer programs or instructions and / or data, the processor being configured to execute the computer programs or instructions stored in the memory, or to read data stored in the memory, to perform the methods described in the above method embodiments. Optionally, there are one or more processors. Optionally, the communication device includes a memory. Optionally, there are one or more memories. Optionally, the memory is integrated with the processor or provided separately.

[0538] The present application also provides a computer-readable storage medium storing computer instructions for implementing the methods executed by the sending end or the receiving end in the above-mentioned method embodiments.

[0539] The present application also provides a computer program product comprising instructions, which, when executed by a computer, implement the methods performed by a sending end or a receiving end in the above-mentioned method embodiments.

[0540] The present application also provides a communication system, which includes at least one of the transmitting end or the receiving end in the above embodiments.

[0541] The explanation of the relevant contents and beneficial effects of any of the above-mentioned devices can be referred to the corresponding method embodiments provided above, which will not be repeated here.

[0542] It is understood that the processor in the embodiments of the present application may be a central processing unit (CPU), or may be other general-purpose processors, digital signal processors (DSP), application-specific integrated circuits (ASIC), field programmable gate arrays (FPGA), or other programmable logic devices, transistor logic devices, hardware components, or any combination thereof. The general-purpose processor may be a microprocessor or any conventional processor.

[0543] The method steps in the embodiments of the present application can be implemented by hardware or by a processor executing software instructions. The software instructions can be composed of corresponding software modules, which can be stored in random access memory, flash memory, read-only memory, programmable read-only memory, erasable programmable read-only memory, electrically erasable programmable read-only memory, registers, hard disks, mobile hard disks, compact disc read-only memory (CD-ROM) or any other form of storage medium well known in the art. An exemplary storage medium is coupled to the processor so that the processor can read information from the storage medium and write information to the storage medium. Of course, the storage medium can also be an integral part of the processor. The processor and storage medium can be located in an ASIC. In addition, the ASIC can be located in a transmitting end or a receiving end. Of course, the processor and storage medium can also be present in a transmitting end or a receiving end as discrete components.

[0544] In the above embodiments, all or part of the embodiments may be implemented using software, hardware, firmware, or any combination thereof. When implemented using software, all or part of the embodiments may be implemented in the form of a computer program product. The computer program product includes one or more computer programs or instructions. When the computer program or instructions are loaded and executed on a computer, the processes or functions described in the embodiments of the present application are performed in whole or in part. The computer may be a general-purpose computer, a special-purpose computer, a computer network, a network device, a user device, or other programmable device. The computer program or instructions may be stored in a computer-readable storage medium or transferred from one computer-readable storage medium to another. For example, the computer program or instructions may be transferred from one website, computer, server, or data center to another website, computer, server, or data center via wired or wireless means. The computer-readable storage medium may be any available medium that can be accessed by a computer or a data storage device such as a server or data center that integrates one or more available media. The available medium may be a magnetic medium, such as a floppy disk, hard disk, or magnetic tape; an optical medium, such as a digital video disk; or a semiconductor medium, such as a solid-state drive.

[0545] In the various embodiments of the present application, unless otherwise specified or there is a logical conflict, the terms and / or descriptions between different embodiments are consistent and can be referenced by each other. The technical features in different embodiments can be combined to form new embodiments according to their inherent logical relationships.

[0546] It is understood that the various numbers used in the embodiments of this application are merely for ease of description and are not intended to limit the scope of the embodiments of this application. The order of the sequence numbers of the above-mentioned processes does not necessarily imply a specific order of execution; the order of execution of the processes should be determined by their functions and inherent logic.

[0547] Unless otherwise indicated, all technical and scientific terms used in the embodiments of the present application have the same meaning as those generally understood by those skilled in the art in the technical field of the application. The terms used in this application are only for the purpose of describing specific embodiments and are not intended to limit the scope of the application. It should be understood that the above are for illustration, and the examples above are only for helping those skilled in the art to understand the embodiments of the present application, rather than limiting the application embodiments to the specific numerical values ​​or specific scenarios illustrated. Those skilled in the art can obviously carry out various equivalent modifications or changes based on the examples given above, and such modifications and changes also fall within the scope of the embodiments of the present application.

[0548] The above description is merely a specific embodiment of the present application, but the scope of protection of the present application is not limited thereto. Any changes or substitutions that can be easily conceived by a person skilled in the art within the technical scope disclosed in this application should be included in the scope of protection of this application. Therefore, the scope of protection of this application should be based on the scope of protection of the claims.

Claims

1. A communication method based on low-density parity check (LDPC) codes, characterized in that: include: obtaining an information bit sequence; Performing LDPC encoding on the information bit sequence according to an LDPC base matrix to obtain an LDPC codeword sequence; wherein the LDPC base matrix is ​​obtained based on a storage matrix and indication information, the indication information is used to indicate a correspondence between rows of the storage matrix or a correspondence between rows of the LDPC base matrix, and the sum of the column weights of non-extended columns of the LDPC base matrix is ​​equal to the sum of the column weights of the non-extended columns of the storage matrix; The LDPC codeword sequence is sent.

2. A communication method based on low-density parity check (LDPC) codes, characterized in that: include: Receive an LDPC codeword sequence from a transmitter; The LDPC codeword sequence is decoded according to an LDPC base matrix, wherein the LDPC base matrix is ​​obtained based on a storage matrix and indication information, the indication information is used to indicate a correspondence between rows of the storage matrix or a correspondence between rows of the LDPC base matrix, and the sum of the column weights of non-extended columns of the LDPC base matrix is ​​equal to the sum of the column weights of the non-extended columns of the storage matrix.

3. The method according to claim 1 or 2, characterized in that The code rate corresponding to the LDPC base matrix is ​​different from the code rate corresponding to the storage matrix.

4. The method according to any one of claims 1 to 3, characterized in that The LDPC base matrix includes a first submatrix and a second submatrix, the first submatrix includes non-extended columns of the LDPC base matrix, and the second submatrix includes extended columns of the LDPC base matrix; the column weight of each column in the Q columns of the second submatrix is ​​2; one of the two non-zero elements contained in the qth column of the Q columns corresponds to the i1th row of the first submatrix, and the other of the two non-zero elements contained in the qth column of the Q columns corresponds to the i2th row of the first submatrix, the i1th row and the i2th row are orthogonal to each other, and the qth column is any column in the Q columns; wherein Q, q, i1, and i2 are all positive integers.

5. The method according to any one of claims 1 to 4, characterized in that The LDPC base matrix is ​​an X×Y matrix, and the y2+1 to Y columns of the LDPC base matrix are extended columns; the LDPC base matrix includes submatrix A1, submatrix B1, submatrix C1, submatrix D1 and submatrix E1, the submatrix A1 is the 1st to x1th rows and the 1st to y1th columns of the LDPC base matrix, the submatrix B1 is the 1st to x1th rows and the y1+1 to y2th columns of the LDPC base matrix, the submatrix C1 is the 1st to x1th rows and the y2+1 to Yth columns of the LDPC base matrix, the submatrix D1 is the x1+1 to Xth rows and the 1st to y2th columns of the LDPC base matrix, and the submatrix E1 is the x1+1 to Xth rows and the y2+1 to Yth columns of the LDPC base matrix, 1≤x1≤X, 1≤y1≤y2≤Y, and x1, X, y1, y2, and Y are all integers; The diagonal of the submatrix E1 is non-zero elements, the submatrix E1 includes non-zero elements above the diagonal and / or the submatrix E1 includes non-zero elements below the diagonal, and the submatrix C1 includes non-zero elements.

6. The method according to any one of claims 1 to 5, characterized in that The indication information may be in the form of at least one of an indication sequence, a mapping table, or a mapping pair.

7. The method according to any one of claims 1 to 6, characterized in that The storage matrix is ​​an M×N matrix, and the m1+1 to Mth rows of the storage matrix are extended rows; the storage matrix includes submatrix A2, submatrix B2, submatrix C2, submatrix D2 and submatrix E2, the submatrix A2 is the 1st to m1th rows and the 1st to n1th columns of the storage matrix, the submatrix B2 is the 1st to m1th rows and the n1+1 to n2th columns of the storage matrix, the submatrix C2 is the 1st to m1th rows and the n2+1 to Nth columns of the storage matrix, the submatrix D2 is the m1+1 to Mth rows and the 1st to n2th columns of the storage matrix, and the submatrix E2 is the m1+1 to Mth rows and the n2+1 to Nth columns of the storage matrix, 1≤m1≤M, 1≤n1≤n2≤N, and m1, M, n1, n2, and N are all integers; The a1th row of the submatrix D2 is truly included in the b1th row of the third submatrix and / or the a2th row of the submatrix D2. The third submatrix is ​​composed of the submatrix A2 and the submatrix B2. The a1th row is any row of the submatrix D2.

8. The method according to claim 7, characterized in that The difference between the offset value of each non-zero element in the a1-th row and the offset value of the non-zero element at the corresponding position in the b1-th row is the same, and / or the difference between the offset value of each non-zero element in the a1-th row and the offset value of the non-zero element at the corresponding position in the b1-th row is the same.

9. The method according to claim 7 or 8, characterized in that The multiple rows in the submatrix D2 corresponding to the b2-th row of the third submatrix are different, and the b2-th row is any row of the third submatrix.

10. The method according to any one of claims 7 to 9, characterized in that The corresponding relationship between the a1th row and the b1th row, and the corresponding relationship between the a1th row and the a2th row are determined according to the indication information.

11. The method according to any one of claims 1 to 10, characterized in that The indication information is used to indicate the correspondence between rows of the LDPC base matrix, the storage matrix is ​​used to store the connection relationship between variable nodes and check nodes, the offset values ​​of the non-zero elements of the storage matrix are obtained according to the offset value table, and the offset value table is used to store the offset values ​​of each position of the non-extended row of the storage matrix.

12. The method according to claim 11, characterized in that The indication information is in the form of an indication sequence, and the LDPC base matrix is ​​obtained by reading the storage matrix and the offset value table according to the indication sequence. The indication sequence includes at least one row number, and the i3th row number in the at least one row number indicates that the offset value of the i3th row of the LDPC base matrix is ​​determined based on the offset value of the row identified by the i3th row number in the at least one row number, and i3 is a positive integer.

13. The method according to any one of claims 1 to 11, characterized in that The indication information is in the form of an indication sequence, the LDPC base matrix is ​​obtained by splitting the storage matrix according to the indication sequence, the indication sequence includes at least one row number, the m1+rth row number in the at least one row number indicates the m1+rth row of the LDPC base matrix, which is used to perform elimination processing on the row identified by the m1+rth row number in the at least one row number, the sorting order of the at least one row number is the splitting order, m1 is the number of non-extended rows of the storage matrix, and r is a positive integer.

14. The method according to claim 13, characterized in that The at least one row number includes at least one segment, each segment in the at least one segment corresponds to a round of splitting, and the row number in the segment corresponding to the t-th round of splitting in the at least one round of splitting corresponding to the at least one segment is {1, ..., 2 t-1 m1} or {1, ..., 2 t-1 m1}, where t is a positive integer.

15. The method according to claim 13 or 14, characterized in that The method further comprises: Determine a splitting number R according to a code length corresponding to the LDPC base matrix, a number of information bits corresponding to the LDPC base matrix, and a number of information columns of the LDPC base matrix; Splitting the storage matrix R times to obtain the LDPC basis matrix; Among them, the rth split in the R splits includes the following operations: obtaining the m1+rth row number of the indication sequence; using the m1+rth row of the storage matrix to perform elimination processing on the row in the storage matrix identified by the m1+rth row number, and the rth split is any one of the R splits.

16. The method according to claim 13 or 14, characterized in that The storage matrix does not include an extended column, the m1+rth row of the LDPC base matrix is ​​obtained based on the rth row of the partition table, and a row in the partition table is used to construct an extended row of the LDPC base matrix.

17. The method according to claim 16, characterized in that The method further comprises: Determine a splitting number R according to a code length corresponding to the LDPC base matrix, a number of information bits corresponding to the LDPC base matrix, and a number of information columns of the LDPC base matrix; Splitting the storage matrix R times to obtain the LDPC basis matrix; Among them, the rth split in the R splits includes the following operations: obtaining the rth row of the partition table, and constructing the rth extended row of the storage matrix based on the rth row; obtaining the M+rth row number of the indication sequence; using the rth extended row to perform elimination processing on the kth row, and the kth row is the row corresponding to the M+rth row number in the storage matrix or the first r-1 extended rows of the storage matrix; wherein M is the number of rows of the storage matrix, and the rth split is any one of the R splits.

18. The method according to claim 15 or 17, characterized in that The R is satisfied by RZ c The smallest integer ≥N0-K0; Among them, Z c is the improvement value, and Z c Z c The list satisfies KZ c The smallest Z ≥ K0 c ; N0 is the code length corresponding to the LDPC base matrix; K0 is the number of information bits corresponding to the LDPC base matrix; K is the number of information columns of the LDPC base matrix.

19. The method according to claim 15, 17 or 18, characterized in that If the part of the check bits corresponding to the last column of the LDPC matrix is ​​punctured, the last split of the R splits is Z c The promoted row is used as the granularity; Among them, Z c is the improvement value, and Z c Z c The list satisfies KZ c The smallest Z ≥ K0 c ; K0 is the number of information bits corresponding to the LDPC base matrix; K is the number of information columns of the LDPC base matrix.

20. The method according to any one of claims 1 to 6, characterized in that The indication information is in the form of an indication sequence, the LDPC base matrix is ​​obtained by merging the storage matrix according to the indication sequence, the indication sequence includes multiple sub-information, each of the multiple sub-information is used to indicate two rows to be merged in the storage matrix, and the arrangement order of the multiple sub-information is the merging order.

21. The method according to claim 20, characterized in that The plurality of sub-information include at least one segment, each segment in the at least one segment corresponds to a round of merging, and the label of the extended column of the storage matrix corresponding to the sub-information included in the t-th segment in the at least one segment is {(2 T1-t -1)s1+1,…,(2 T1-t+1 -1)s1} or the substitution form {(2 T1-t -1)s1+1,…,(2 T1-t+1 -1)s1}, T1 is the upper bound of the number of merging rounds, s1 is the number of non-extended rows of the storage matrix, and T1 and t are positive integers.

22. The method according to claim 21, characterized in that The storage matrix includes a fourth submatrix and a fifth submatrix, the fourth submatrix includes non-extended columns of the storage matrix, and the fifth submatrix includes extended columns of the storage matrix; the column weight of each column in the P columns of the fifth submatrix is ​​2; one of the two non-zero elements contained in the p-th column in the P columns corresponds to the j1-th row of the first submatrix, and the other of the two non-zero elements contained in the p-th column in the P columns corresponds to the j2-th row of the first submatrix, the j1-th row and the j2-th row are orthogonal to each other, and the p-th column is any column in the P columns; wherein P, p, j1, and j2 are all positive integers.

23. The method according to claim 20 or 21, characterized in that The storage matrix is ​​an S×G matrix, the s1+1 to S rows of the storage matrix are extended rows, and the g2+1 to G columns of the storage matrix are extended columns; the storage matrix includes submatrix A3, submatrix B3, submatrix C3, submatrix D3 and submatrix E3, the submatrix A3 is the 1 to s1 rows and 1 to g1 columns of the storage matrix, the submatrix B3 is the 1 to s1 rows and g1+1 to g2 columns of the storage matrix, the submatrix C3 is the 1 to s1 rows and g2+1 to G columns of the storage matrix, the submatrix D3 is the s1+1 to S rows and 1 to g2 columns of the storage matrix, and the submatrix E3 is the s1+1 to S rows and g2+1 to G columns of the storage matrix, 1≤s1≤S, 1≤g1≤g2≤G, s1, S, g1, g2, G are all integers; The diagonal of the submatrix E3 is non-zero elements, the submatrix E3 includes non-zero elements above the diagonal and / or the submatrix E3 includes non-zero elements below the diagonal, and the submatrix C3 includes non-zero elements.

24. The method according to any one of claims 20 to 23, characterized in that The method further comprises: Determine the number of merging times W according to the code rate corresponding to the LDPC base matrix, the number of information columns of the LDPC base matrix, the number of non-extended rows of the storage matrix, the number of non-extended columns of the storage matrix, and an upper bound T1 of the number of merging rounds; Merging the storage matrix W times to obtain the LDPC basis matrix; The w-th merge in the W splits includes the following operations: obtaining the w-th sub-information of the indication sequence; merging the two rows indicated by the w-th sub-information; wherein the w-th merge is any one of the W merges, and w is a positive integer.

25. The method according to claim 24, characterized in that The W is satisfied The smallest integer; Among them, R0 is the code rate corresponding to the LDPC base matrix; K is the number of information columns of the LDPC base matrix; s1 is the number of non-extended rows of the storage matrix; g1 is the number of non-extended columns of the storage matrix; T1 is the upper bound of the number of merging rounds.

26. The method according to claim 24 or 25, characterized in that If the part of the check bits corresponding to the last column of the LDPC base matrix is ​​punctured, the last merging of the W merging times is Z c The promoted row is used as the granularity; Among them, Z c is the improvement value, and Z c Z c The list satisfies KZ c The smallest Z ≥ K0 c ; K0 is the number of information bits corresponding to the LDPC base matrix; K is the number of information columns of the LDPC base matrix.

27. A communication method based on low-density parity check (LDPC) codes, characterized in that: include: obtaining an information bit sequence; Performing LDPC encoding on the information bit sequence according to a storage matrix to obtain a first LDPC codeword sequence, wherein the storage matrix includes a fourth submatrix and a fifth submatrix, the fourth submatrix includes non-extended columns of the storage matrix, and the fifth submatrix includes extended columns of the storage matrix; the column weight of each column in the P columns of the fifth submatrix is ​​2; one of the two non-zero elements contained in the p-th column in the P columns corresponds to the j1-th row of the first submatrix, and the other of the two non-zero elements contained in the p-th column in the P columns corresponds to the j2-th row of the first submatrix, the j1-th row and the j2-th row are orthogonal to each other, and the p-th column is any column in the P columns; wherein P, p, j1, and j2 are all positive integers; According to the indication information, a second LDPC codeword sequence is sent, where the indication information is used to indicate the punctured columns in the fifth submatrix, and the second LDPC codeword sequence includes codewords in the first LDPC codeword sequence except for the codewords corresponding to the punctured columns in the fifth submatrix.

28. A communication method based on low-density parity check (LDPC) codes, characterized in that: include: Receive an LDPC codeword sequence from a transmitter; The LDPC codeword sequence is decoded according to a storage matrix and indication information, wherein the storage matrix includes a fourth submatrix and a fifth submatrix, the fourth submatrix includes non-extended columns of the storage matrix, and the fifth submatrix includes extended columns of the storage matrix; each of P columns in the fifth submatrix has a column weight of 2; one of the two non-zero elements included in the p-th column in the P columns corresponds to the j1-th row of the first submatrix, the other of the two non-zero elements included in the p-th column in the P columns corresponds to the j2-th row of the first submatrix, the j1-th row and the j2-th row are mutually orthogonal, the p-th column is any column in the P columns, and P, p, j1, and j2 are all positive integers; the indication information is used to indicate punctured columns in the fifth submatrix, and the second LDPC codeword sequence includes codewords in the first LDPC codeword sequence except for codewords corresponding to the punctured columns in the fifth submatrix.

29. The method according to claim 27 or 28, characterized in that The storage matrix is ​​an S×G matrix, the s1+1 to S rows of the storage matrix are extended rows, and the g2+1 to G columns of the storage matrix are extended columns; the storage matrix includes submatrix A3, submatrix B3, submatrix C3, submatrix D3 and submatrix E3, the submatrix A3 is the 1 to s1 rows and 1 to g1 columns of the storage matrix, the submatrix B3 is the 1 to s1 rows and g1+1 to g2 columns of the storage matrix, the submatrix C3 is the 1 to s1 rows and g2+1 to G columns of the storage matrix, the submatrix D3 is the s1+1 to S rows and 1 to g2 columns of the storage matrix, and the submatrix E3 is the s1+1 to S rows and g2+1 to G columns of the storage matrix, 1≤s1≤S, 1≤g1≤g2≤G, s1, S, g1, g2, G are all integers; The diagonal of the submatrix E3 is non-zero elements, the submatrix E3 includes non-zero elements above the diagonal and / or the submatrix E3 includes non-zero elements below the diagonal, and the submatrix C3 includes non-zero elements.

30. The method according to any one of claims 27 to 29, characterized in that The indication information may be in the form of at least one of an indication sequence, a mapping table, or a mapping pair.

31. The method according to claim 30, wherein The indication information is in the form of an indication sequence, which includes multiple sub-information. Each sub-information in the multiple sub-information is used to indicate a column in the extended column of the storage matrix. The arrangement order of the multiple sub-information is a puncturing order.

32. The method according to claim 31, characterized in that The plurality of sub-information include at least one segment, each segment in the at least one segment corresponds to a round of puncturing, and the label of the extended column indicated by the sub-information included in the t-th segment in the at least one segment is {(2 T2-t -1)s1+1,…,2 T2-t+1 -1)s1} or the substitution form {(2 T2-t -1)s1+1,…,2 T2-t+1 -1)s1}, T2 is the upper bound of the number of merging rounds, s1 is the number of non-extended rows of the storage matrix, and T2 and t are positive integers.

33. The method according to claim 31 or 32, characterized in that The number of sub-information J included in the indication sequence satisfies The smallest integer; Among them, R0 is the target bit rate; K is the target number of information columns; s1 is the number of non-extended rows of the storage matrix; g2 is the number of non-extended columns of the storage matrix; T2 is the upper limit of the number of merging rounds.

34. A communication device, characterized in that: Comprising modules or units for performing the method of any one of claims 1, 3 to 26, the method of any one of claims 2 to 26, the method of any one of claims 27, 29 to 33, or the method of any one of claims 28 to 33.

35. A communication device, characterized in that: include: A processor, configured to execute a computer program stored in a memory, so that the apparatus performs the method according to any one of claims 1, 3 to 26, or the method according to any one of claims 2 to 26, or the method according to any one of claims 27, 29 to 33, or the method according to any one of claims 28 to 33.

36. The device according to claim 35, characterized in that The apparatus further comprises the memory.

37. The device according to claim 35 or 36, characterized in that The device is a chip.

38. A computer-readable storage medium, characterized in that The computer-readable storage medium stores a computer program, which, when executed on a computer, causes the computer to execute the method according to any one of claims 1, 3 to 26, or the method according to any one of claims 2 to 26, or the method according to any one of claims 27, 29 to 33, or the method according to any one of claims 28 to 33.

39. A computer program product, characterized in that The computer program product comprises instructions for performing the method of any one of claims 1, 3-26, the method of any one of claims 2-26, the method of any one of claims 27, 29-33, or the method of any one of claims 28-33.

40. A communication system, characterized in that include: A transmitting end for executing the method according to any one of claims 1 and 3 to 26, and a receiving end for executing the method according to any one of claims 2 to 26; or A transmitting end for executing the method according to any one of claims 27, 29 to 33, and a receiving end for executing the method according to any one of claims 28 to 33.

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