Display substrate and display device

Abstract

The present disclosure provides a display substrate and a display device. The display substrate comprises: a first power wire and a multiplexer circuit. The first power wire comprises a first power unit, a second power unit, and a plurality of power connection units; the plurality of power connection units are located between the orthographic projection of the first power unit on a base substrate and the orthographic projection of the second power unit on the base substrate; the power connection units are respectively coupled to the first power unit and the second power unit; the orthographic projection of the multiplexer circuit on the base substrate is at least partially located between the orthographic projection of the first power unit on the base substrate and the orthographic projection of the second power unit on the base substrate; the multiplexer circuit comprises a plurality of multiplexer units; and the multiplexer units and the power connection units are alternately arranged.

Description

Display substrate and display device

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to Chinese patent application No. 202310212569.3 filed in China on February 28, 2023, the entire contents of which are incorporated herein by reference. Technical Field

[0003] The present disclosure relates to the field of display technology, and in particular to a display substrate and a display device. Background Art

[0004] Organic Light-Emitting Diode (OLED) displays combine the advantages of traditional liquid crystal displays (LCDs) with self-luminescence, a wide color gamut, high contrast, low power consumption, and a thin and lightweight design. Consequently, they are widely used in smartphones, wearable devices, notebooks, TVs, VR, and other fields. To better meet consumer demand for diverse functions and provide a superior screen experience, full-screen, borderless displays are becoming the mainstream form factor for OLED displays. Consequently, narrowing the bezel is gaining increasing attention in OLED display design research. In particular, with advancements in flexible active-matrix OLED display technology, device form factors are evolving, with foldable and rollable forms emerging. This creates a higher demand for narrower display bezels. Consequently, the bezel size of flexible active-matrix OLED displays needs to be continuously optimized to meet the growing trend of flexible products.

[0005] However, existing display products have the problem of poor brightness uniformity while meeting the narrow frame requirement.

[0006] Summary of the Invention

[0007] An object of the present disclosure is to provide a display substrate and a display device.

[0008] In order to achieve the above objectives, the present disclosure provides the following technical solutions:

[0009] A first aspect of the present disclosure provides a display substrate, comprising a base substrate, the base substrate comprising a display area and a frame area located around the display area, the frame area comprising a sealing frame area; the display substrate further comprising:

[0010] a plurality of sub-pixels, wherein the plurality of sub-pixels are located in the display area;

[0011] a plurality of power supply units, each of which is located at least in the display area and electrically connected to the plurality of sub-pixels;

[0012] a first power line, the first power line comprising a first power supply portion, a second power supply portion, and a plurality of power connection portions, the first power supply portion being located between the second power supply portion and the display area, at least a portion of the second power supply portion being located between the display area and the sealing frame area, the first power supply portion being coupled to the plurality of power supply portions, and the plurality of power connection portions being located between the first power supply portion and the second power supply portion and coupled to the first power supply portion and the second power supply portion;

[0013] a multiplexer circuit, wherein at least a portion of an orthographic projection of the multiplexer circuit on the base substrate is located between an orthographic projection of the first power supply portion on the base substrate and an orthographic projection of the second power supply portion on the base substrate;

[0014] The multiplexer circuit includes a plurality of multiplexer units, and the plurality of multiplexer units are alternately arranged with the plurality of power connection portions.

[0015] Optionally, the multiple power connection portions include a first power connection portion and a plurality of second power connection portions, the plurality of second power connection portions include two groups of connection portion groups, and the orthographic projection of the first power connection portion on the base substrate is located between the orthographic projections of the two groups of connection portion groups on the base substrate;

[0016] The width of the first power connection portion in a direction perpendicular to its own extension direction is greater than the width of the second power connection portion in a direction perpendicular to its own extension direction.

[0017] Optionally, a line width d3 of the second power supply portion perpendicular to its own extension direction satisfies: 15 μm≤d3≤25 μm.

[0018] Optionally, the display substrate includes a first gate metal layer, a second gate metal layer, a first source-drain metal layer and a second source-drain metal layer stacked in sequence in a direction away from the base substrate; the power connection part is arranged on the same layer as at least one of the first gate metal layer, the second gate metal layer, the first source-drain metal layer and the second source-drain metal layer.

[0019] Optionally, the first power line further includes at least one third power supply unit, the third power supply unit is coupled to the second power supply unit, and at least a portion of the third power supply unit is located in the sealing frame area;

[0020] The third power supply unit is arranged in the same layer as at least one of the first gate metal layer, the second gate metal layer and the first source-drain metal layer in the display substrate.

[0021] Optionally, the display substrate also includes a first signal input terminal; the first power line includes two third power supply units, and the two third power supply units are symmetrically arranged; the first power line also includes two fourth power supply units, and the fourth power supply units are respectively coupled to the corresponding third power supply units and the first signal input terminal.

[0022] Optionally, the first power line also includes a fifth power supply unit and a sixth power supply unit, the fifth power supply unit is located between the two fourth power supply units, the fifth power supply unit is coupled to the two fourth power supply units respectively, and at least part of the sixth power supply unit is located in the sealing frame area, and the sixth power supply unit is coupled to the fifth power supply unit and the second power supply unit respectively.

[0023] Optionally, the display substrate also includes a first signal input terminal; the first power line includes a sixth power supply unit and a seventh power supply unit, the sixth power supply unit is coupled to the second power supply unit, the seventh power supply unit includes a first part and two second parts, the first part extends along a first direction, the first part is respectively coupled to the sixth power supply unit and the two second parts, the second part extends along a second direction, the second part is coupled to the first signal input terminal, and the first direction intersects with the second direction.

[0024] Optionally, the display substrate further includes:

[0025] a second power line, the second power line comprising an eighth power supply unit and two ninth power supply units, the eighth power supply unit being arranged around the display area, the two ninth power supply units being coupled to two ends of the eighth power supply unit in a one-to-one correspondence;

[0026] The ninth power supply unit is coupled to the second signal input terminal.

[0027] Optionally, the display substrate includes a first gate metal layer, a second gate metal layer, a first source-drain metal layer, and a second source-drain metal layer stacked in sequence in a direction away from the base substrate;

[0028] At least a portion of the ninth power supply unit is located in the sealing frame area, and the ninth power supply unit is provided in the same layer as the first source / drain metal layer in the display substrate.

[0029] Optionally, the display substrate includes a first gate metal layer, a second gate metal layer, a first source-drain metal layer, and a second source-drain metal layer stacked in sequence in a direction away from the base substrate;

[0030] At least a portion of the eighth power supply unit is located in the sealing frame area, and the eighth power supply unit is provided in the same layer as the first gate metal layer in the display substrate.

[0031] Optionally, the display substrate further includes a fan-out line, and at least a portion of an orthographic projection of the fan-out line on the base substrate is located between an orthographic projection of the eighth power supply unit on the base substrate and the display area.

[0032] Optionally, the display substrate includes a first gate metal layer, a second gate metal layer, a first source-drain metal layer, and a second source-drain metal layer stacked in sequence in a direction away from the base substrate;

[0033] The ninth power supply unit includes a third part and a fourth part coupled to each other, at least a portion of the third part is located in the sealing frame area, and the fourth part is located in an area outside the sealing frame area, the third part is arranged in the same layer as the first gate metal layer in the display substrate, the third part and the eighth power supply unit are an integrated structure, and the fourth part is arranged in the same layer as the first source and drain metal layer in the display substrate.

[0034] Optionally, the display substrate further includes a fan-out line; the eighth power supply unit includes a fifth portion and a sixth portion, the orthographic projection of the fifth portion on the base substrate is located between the orthographic projection of the sixth portion on the base substrate and the display area; the fifth portion and the sixth portion are respectively coupled to the ninth power supply unit;

[0035] At least a portion of an orthographic projection of the fan-out line on the substrate is located between an orthographic projection of the fifth portion on the substrate and an orthographic projection of the sixth portion on the substrate.

[0036] Optionally, the display substrate further includes a plurality of fan-out lines, at least some of the fan-out lines include fan-out compensation portions, and at least some of the fan-out compensation portions are located in the sealing frame area.

[0037] Optionally, the display substrate further includes: a frame compensation portion, the frame compensation portion is located in the frame area, and in the frame area, a layout density of the frame compensation portion is the same as a layout density of the fan-out lines.

[0038] Optionally, the display substrate further includes a plurality of fan-out lines, at least some of the fan-out lines include fan-out compensation parts, the fan-out compensation parts included in each fan-out line have substantially the same length, and the fan-out compensation parts are evenly arranged in the sealing frame area.

[0039] A second aspect of the present disclosure provides a display substrate, comprising a base substrate, the base substrate comprising a display area and a frame area located around the display area, the frame area comprising a sealing frame area; the display substrate further comprising:

[0040] a plurality of sub-pixels, wherein the plurality of sub-pixels are located in the display area;

[0041] a plurality of power supply units, each of which is located at least in the display area and electrically connected to the plurality of sub-pixels;

[0042] a first power line, the first power line comprising a first power supply portion, a second power supply portion, and a plurality of power connection portions, the first power supply portion being located between the second power supply portion and the display area, at least a portion of the second power supply portion being located between the display area and the sealing frame area, the first power supply portion being coupled to the plurality of power supply portions, the plurality of power connection portions being located between the first power supply portion and the second power supply portion, and coupled to the first power supply portion and the second power supply portion; the first power line further comprising two third power supply portions and a sixth power supply portion, the third power supply portion and the sixth power supply portion being coupled to the second power supply portion, the orthographic projection of the sixth power supply portion on the base substrate being located between the orthographic projections of the two third power supply portions on the base substrate;

[0043] A plurality of fan-out lines, at least some of the fan-out lines include a fan-out portion extending along the second direction, and at least a portion of an orthographic projection of the fan-out portion on the substrate is located between an orthographic projection of the third power supply portion on the substrate and an orthographic projection of the sixth power supply portion on the substrate.

[0044] Optionally, a multiplexer circuit is further included, and at least part of the orthographic projection of the multiplexer circuit on the base substrate is located in an area surrounded by the first power supply unit, the second power supply unit and the multiple power connection units.

[0045] Based on the technical solution of the above-mentioned display substrate, a third aspect of the present disclosure provides a display device including the above-mentioned display substrate. BRIEF DESCRIPTION OF THE DRAWINGS

[0046] The drawings described herein are used to provide a further understanding of the present disclosure and constitute a part of the present disclosure. The exemplary embodiments of the present disclosure and their descriptions are used to explain the present disclosure and do not constitute an improper limitation of the present disclosure. In the drawings:

[0047] FIG1 is a schematic structural diagram of a display substrate provided by an embodiment of the present disclosure;

[0048] FIG2 is an enlarged schematic diagram of portion A1 in FIG1 ;

[0049] FIG3 is a schematic diagram of the layout of the first power line and the multiplexer circuit in FIG1 ;

[0050] FIG4 is a schematic diagram of a first layout of a first power line and a second power line at the lower left frame of a display substrate provided by an embodiment of the present disclosure;

[0051] FIG5 is a schematic diagram of a second layout of a first power line and a multiplexer at a lower frame of a display substrate provided by an embodiment of the present disclosure;

[0052] FIG6 is a schematic diagram of a second layout of the first power line and the second power line at the lower left frame of the display substrate provided by an embodiment of the present disclosure;

[0053] FIG7 is a schematic diagram showing the layout of the first power line and the second power line at the lower right frame of the display substrate according to an embodiment of the present disclosure;

[0054] FIG8 is a schematic diagram of the layout of a second power line and a multiplexer circuit at the lower left frame of a display substrate provided by an embodiment of the present disclosure;

[0055] FIG9 is a schematic diagram of a third layout of the first power line and the multiplexer at the lower frame of the display substrate provided by an embodiment of the present disclosure;

[0056] FIG10 is a schematic diagram of a third layout of the first power line and the second power line at the lower left frame of the display substrate provided by an embodiment of the present disclosure;

[0057] FIG11 is an enlarged schematic diagram of portion A2 in FIG1 ;

[0058] FIG12 is an enlarged schematic diagram of portion A3 in FIG1 ;

[0059] FIG13 is a schematic diagram of the layout of a multiplexer circuit provided in an embodiment of the present disclosure;

[0060] FIG14 is a schematic diagram of a first layout of fan-out lines provided in an embodiment of the present disclosure;

[0061] FIG15 is a schematic diagram of a second layout of fan-out lines provided in an embodiment of the present disclosure;

[0062] FIG16 is a schematic diagram of a third layout of fan-out lines provided in an embodiment of the present disclosure;

[0063] FIG17 is a schematic diagram of the layout of a second power line and sub-pixels provided in an embodiment of the present disclosure;

[0064] FIG18 is a schematic cross-sectional view of the film layer along the B1B2 direction in FIG17 ;

[0065] FIG19 is a schematic diagram of a fourth layout of the first power line and the multiplexer at the lower frame of the display substrate provided by an embodiment of the present disclosure;

[0066] FIG20 is a schematic diagram of a fifth layout of the first power line and the multiplexer at the lower frame of the display substrate provided by an embodiment of the present disclosure;

[0067] FIG21 is a schematic diagram of a cross-section of the film layer along the C1C2 direction in FIG20 . DETAILED DESCRIPTION

[0068] In order to further illustrate the display substrate and the display device provided by the embodiments of the present disclosure, a detailed description is given below with reference to the accompanying drawings.

[0069] Based on the technical issues existing in the background technology, research has found that due to the attenuation of the input voltage of the power lines connecting the sub-pixels in each row of the display area of ​​the display panel, the brightness at different locations on the display panel also varies. Therefore, in order to improve the brightness uniformity (English: Launch Range Uniformity, abbreviated: LRU) of the display panel, it is necessary to minimize the voltage differences of the power lines connecting the sub-pixels in each row or column, thereby improving the brightness uniformity at all locations in the display area. Moreover, to ensure LRU, the power lines in conventional designs are very wide, which takes up a lot of space in the lower bezel, making it more difficult to achieve a narrow bezel.

[0070] Referring to FIG. 1 to FIG. 3 , an embodiment of the present disclosure provides a display substrate, including a base substrate, wherein the base substrate includes a display area 1 and a frame area 2 located around the display area 1 , wherein the frame area 2 includes a sealing frame area 20 ; the display substrate further includes:

[0071] a plurality of sub-pixels, wherein the plurality of sub-pixels are located in the display area 1;

[0072] a plurality of power supply units 218 , each of which is located at least in the display area 1 and electrically connected to the plurality of sub-pixels;

[0073] a first power line 21, the first power line 21 comprising a first power supply portion 211, a second power supply portion 212, and a plurality of power connection portions 210, the first power supply portion 211 being located between the second power supply portion 212 and the display area 1, at least a portion of the second power supply portion 212 being located between the display area 1 and the sealing frame area 20, the first power supply portion 211 being coupled to the plurality of power supply portions 218, the plurality of power connection portions 210 being located between the first power supply portion 211 and the second power supply portion 212, and being coupled to the first power supply portion 211 and the second power supply portion 212;

[0074] a multiplexer circuit 3, wherein at least a portion of an orthographic projection of the multiplexer circuit 3 on the base substrate is located between an orthographic projection of the first power supply unit 211 on the base substrate and an orthographic projection of the second power supply unit 212 on the base substrate;

[0075] The multiplexer circuit 3 includes a plurality of multiplexer units 30 , and the plurality of multiplexer units 30 and the plurality of power connection portions 210 are alternately arranged.

[0076] Illustratively, the orthographic projections of the plurality of power connection portions 210 on the base substrate are located between the orthographic projections of the first power portion 211 on the base substrate and the orthographic projections of the second power portion 212 on the base substrate.

[0077] Exemplarily, the display area 1 includes a plurality of sub-pixels, and the plurality of sub-pixel driving circuits included in the plurality of sub-pixels are distributed in an array. The plurality of sub-pixel driving circuits are divided into a plurality of rows of sub-pixel driving circuits and a plurality of columns of sub-pixel driving circuits. The plurality of rows of sub-pixel driving circuits are arranged along a second direction, and each row of sub-pixel driving circuits includes a plurality of sub-pixel driving circuits arranged along a first direction. The plurality of columns of sub-pixel driving circuits are arranged along a first direction, and each column of sub-pixel driving circuits includes a plurality of sub-pixel driving circuits arranged along a second direction. Exemplarily, the first direction and the second direction intersect. For example, the first direction includes a horizontal direction, and the second direction includes a vertical direction.

[0078] Exemplarily, the sub-pixel includes a sub-pixel driving circuit and a light-emitting element. The sub-pixel driving circuit is coupled to an anode of the light-emitting element and is configured to provide a driving signal to the light-emitting element to drive the light-emitting element to emit light.

[0079] Exemplarily, the first power line 21 further includes a plurality of power supply units 218, at least a portion of which is located in the display area 1. The power supply units 218 are coupled to each sub-pixel driving circuit in a corresponding column of sub-pixel driving circuits. Exemplarily, the first power line 21 is used to transmit a positive power signal, but is not limited thereto.

[0080] Exemplarily, the plurality of power supply portions are arranged along the first direction, and each of the power supply portions includes at least a portion extending along the second direction. The first power supply portion 211 is coupled to the plurality of power supply portions respectively.

[0081] Exemplarily, the border area 2 includes an upper border area, a lower border area, a left border area and a right border area, and the first power supply part 211, the second power supply part 212 and the multiple power connection parts 210 are located in the lower border area, but are not limited to this.

[0082] Exemplarily, the frame area 2 includes a sealing area 20 , which surrounds the display area 1 , and is used to form a sealing glue.

[0083] Exemplarily, the first power line 21 includes a positive power signal line for transmitting a positive power signal.

[0084] Exemplarily, the first power supply portion 211 includes at least a portion extending along the first direction, the second power supply portion 212 includes at least a portion extending along the first direction, and the power connection portion 210 includes at least a portion extending along the second direction. The plurality of power connection portions 210 are spaced apart along the first direction. Exemplarily, the first power supply portion 211 and the second power supply portion 212 are disposed on the same layer as a first source / drain metal layer in the display substrate.

[0085] As shown in FIG13 , the layout structure of the multiplexer is illustrated. SW11 to SW16 illustrated in FIG13 are multiple switch control signal lines.

[0086] Exemplarily, the multiplexer circuit 3 includes a plurality of multiplexer units 30 , the number of transistors included in each of the multiplexer units 30 may be the same or different, and the plurality of multiplexer units 30 are arranged along the first direction.

[0087] Exemplarily, the multiplexer units 30 are arranged alternately with the power connection parts 210. Exemplarily, the power connection parts 210 pass through the layout area of ​​the multiplexer circuit 3 to achieve coupling with the first power part 211 and the second power part 212.

[0088] As shown in FIG. 3 , illustratively, a width d1 of at least a portion of the power connection portion 210 perpendicular to its own extension direction is smaller than a width d2 of the first power portion 211 perpendicular to its own extension direction.

[0089] As shown in FIG. 3 , illustratively, a width d1 of at least a portion of the power connection portion 210 perpendicular to its own extension direction is smaller than a width d3 of the second power portion 212 perpendicular to its own extension direction.

[0090] According to the specific structure of the display substrate described above, in the display substrate provided by the embodiment of the present disclosure, by configuring the first power line 21 to include the first power supply unit 211, the second power supply unit 212, and the multiple power connection units 210, and arranging the multiplexer units 30 and the power connection units 210 alternately, the first power line 21 is formed into a mesh structure that can be interspersed between the multiplexer circuits 3, so that the first power line 21 can be introduced into the display area 1 in multiple ways. On the one hand, the above configuration can reduce the line width of the first power supply unit 211, the second power supply unit 212, and the power connection units 210, thereby reducing the space occupied by the first power line 21, thereby enabling the display substrate to better achieve a narrow frame. On the other hand, the multiple-way introduction of the mesh structure can effectively improve the uniformity of the power signal transmitted by the first power line 21, improve the LRU, and improve the display brightness uniformity of the display substrate.

[0091] As shown in Figure 3, in some embodiments, the multiple power connection parts 210 include a first power connection part 2101 and multiple second power connection parts 2102, and the multiple second power connection parts 2102 include two groups of connection parts. The orthographic projection of the first power connection part 2101 on the substrate is located between the orthographic projections of the two groups of connection parts on the substrate; the width d4 of the first power connection part 2101 in the direction perpendicular to its own extension direction is greater than the width d1 of the second power connection part 2102 in the direction perpendicular to its own extension direction.

[0092] Illustratively, the numbers of the second power connection parts 2102 included in the two groups of connection parts are the same or different.

[0093] Exemplarily, the first power connection portion 2101 is provided in the same layer as the first source / drain metal layer in the display substrate, but is not limited thereto.

[0094] Exemplarily, the first power connection portion 2101 and the second power connection portion 2102 are arranged in different layers, but the present invention is not limited thereto.

[0095] Exemplarily, the number of multiplexer units 30 located on both sides of the first power connection portion 2101 is the same.

[0096] Exemplarily, the multiplexer units 30 located on both sides of the first power connection portion 2101 are symmetrically arranged.

[0097] Illustratively, the number of the second power connection parts 2102 located on both sides of the first power connection part 2101 is the same.

[0098] Illustratively, the second power connection portions 2102 located on both sides of the first power connection portion 2101 are symmetrically arranged.

[0099] In the display substrate provided in the above embodiment, by setting the width of the first power connection portion 2101 in the direction perpendicular to its own extension to be greater than the width of the second power connection portion 2102 in the direction perpendicular to its own extension, not only can the second power connection portion 2102 pass through the layout area of ​​the multiplexer circuit 3 without short-circuiting with the multiplexer circuit 3, but the power signal transmitted by the first power line 21 can also be transmitted to the first power portion 211 through the wider first power connection portion 2101, which is more conducive to the writing of the power signal and the uniformity of the display brightness of the display substrate.

[0100] As shown in FIG. 3 , in some embodiments, a line width d3 of the second power supply portion 212 perpendicular to its own extending direction satisfies: 15 μm≤d3≤25 μm.

[0101] Exemplarily, the line width d3 of the second power supply portion 212 perpendicular to its own extension direction includes 15 μm, 18 μm, 20 μm, 22 μm, and 25 μm, but is not limited thereto.

[0102] Setting the line width of the second power supply unit 212 within the above range not only ensures the transmission capability of the power signal, but also facilitates narrowing the frame of the display substrate.

[0103] In some embodiments, the display substrate includes a first gate metal layer, a second gate metal layer, a first source-drain metal layer, and a second source-drain metal layer stacked in sequence in a direction away from the base substrate; the power connection portion 210 is arranged on the same layer as at least one of the first gate metal layer, the second gate metal layer, the first source-drain metal layer, and the second source-drain metal layer.

[0104] As shown in FIG18 , the display substrate exemplarily includes a buffer layer BF, an active layer poly, a first gate insulating layer GI1, a first gate metal layer gate1, a second gate insulating layer GI2, a second gate metal layer gate2, an interlayer insulating layer ILD, a first source / drain metal layer SD1, a first planarizing layer PLN1, a second source / drain metal layer SD2, a second planarizing layer PLN2, an anode layer ANO, a light-emitting functional layer EL, a cathode layer cath, a first inorganic encapsulation layer CVD1, an organic encapsulation layer IJP, and a second inorganic encapsulation layer CVD2, which are sequentially stacked in a direction away from the base substrate 70. The display substrate may further include, but is not limited to, a passivation layer PVX.

[0105] In the display substrate provided in the above embodiment, the power connection portion 210 is arranged in the same layer as at least one of the first gate metal layer, the second gate metal layer, the first source-drain metal layer and the second source-drain metal layer, so that the power connection portion 210 can be formed simultaneously with other film layers in the display substrate in the same patterning process, avoiding the addition of an additional patterning process to form the power connection portion 210, effectively simplifying the manufacturing process flow of the display substrate, and reducing the manufacturing cost of the display substrate.

[0106] As shown in FIG3 , FIG4 , FIG5 , FIG6 , FIG7 , FIG9 , and FIG10 , in some embodiments, the first power line 21 further includes at least one third power supply portion 213 , the third power supply portion 213 being coupled to the second power supply portion 212 , and at least a portion of the third power supply portion 213 being located in the sealing frame area 20 ;

[0107] The third power supply unit 213 is disposed in the same layer as at least one of the first gate metal layer, the second gate metal layer and the first source / drain metal layer in the display substrate.

[0108] Exemplarily, the third power supply unit 213 and the second power supply unit 212 form an integrated structure, and the third power supply unit 213 and the second power supply unit 212 are both provided in the same layer as the first source-drain metal layer.

[0109] Illustratively, the third power supply unit 213 is provided in the same layer as the first gate metal layer or the second gate metal layer, and the second power supply unit 212 is provided in the same layer as the first source / drain metal layer.

[0110] Exemplarily, the third power supply unit 213 is located in the sealing region 20 and is disposed on the same layer as the first source / drain metal layer. The third power supply unit 213 located in the sealing region 20 serves as the sealing base of the sealing region 20 and is in contact with the sealant. Except for the region where the third power supply unit 213 is located, the structures in other regions of the sealing region 20 are fabricated using the first gate metal layer and / or the second gate metal layer.

[0111] Exemplarily, the third power supply unit 213 is located in the sealing region 20 and is co-located with the first gate metal layer. The third power supply unit 213 located in the sealing region 20 serves as the sealing base of the sealing region 20 and is in contact with the sealant. The portion of the display substrate located in the sealing region 20 is co-located with at least one of the first and second gate metal layers of the display substrate.

[0112] In the display substrate provided by the above embodiment, the third power supply unit 213 is provided in the same layer as the first gate metal layer and / or the second gate metal layer, which can reduce the step difference generated by the third power supply unit 213 in the sealing area 20, and is conducive to improving the sealing reliability of the frame sealing glue.

[0113] In the display substrate provided by the above embodiment, the third power supply unit 213 is arranged on the same layer as the first source-drain metal layer or the second source-drain metal layer, and the other structures in the sealing frame area 20 are all made of the first gate metal layer or the second gate metal layer. This can greatly reduce the proportion of the first source-drain metal layer in the sealing frame area 20, reduce the step difference in the sealing frame area 20 caused by the first source-drain metal layer, improve the bonding reliability of the frame sealing glue, and significantly improve the problem of the whole device falling.

[0114] As shown in Figures 4, 5, 6, 7, 9, and 10, in some embodiments, the display substrate also includes a first signal input terminal 61; the first power line 21 includes two third power supply units 213, and the two third power supply units 213 are symmetrically arranged; the first power line 21 also includes two fourth power supply units 214, and the fourth power supply units 214 are respectively coupled to the corresponding third power supply units 213 and the first signal input terminal 61.

[0115] Illustratively, the two fourth power supply units 214 are symmetrically arranged, and the fourth power supply units 214 are coupled to the third power supply units 213 in a one-to-one correspondence.

[0116] Illustratively, the fourth power supply unit 214 is located on a side of the sealing frame area 20 away from the display area 1 .

[0117] Exemplarily, the fourth power supply unit 214 is provided in the same layer as the first source-drain metal layer.

[0118] For example, a hollow area is provided on the third power supply unit 213 , so as to increase the adhesion between the frame sealing glue in the frame sealing area 20 and the frame base.

[0119] As shown in FIG. 5 , illustratively, a width d5 ​​of a portion of the third power supply unit 213 located in the frame-sealing area 20 is greater than a width d6 of a portion of the third power supply unit 213 located in the non-frame-sealing area 20 .

[0120] As shown in Figures 5, 6, and 7, in some embodiments, the first power line 21 also includes a fifth power supply unit 215 and a sixth power supply unit 216, the fifth power supply unit 215 is located between the two fourth power supply units 214, and the fifth power supply unit 215 is coupled to the two fourth power supply units 214 respectively, and at least a portion of the sixth power supply unit 216 is located in the sealing frame area 20, and the sixth power supply unit 216 is coupled to the fifth power supply unit 215 and the second power supply unit 212 respectively.

[0121] Illustratively, the fifth power supply unit 215 and the fourth power supply unit 214 form an integrated structure.

[0122] Exemplarily, the fifth power supply unit 215 is provided in the same layer as the first source / drain metal layer in the display substrate.

[0123] Exemplarily, the fifth power supply unit 215 is located on a side of the sealing frame area 20 away from the display area 1 .

[0124] Exemplarily, the sixth power supply unit 216 is provided in the same layer as the first gate metal layer in the display substrate.

[0125] In the display substrate provided in the above embodiment, by setting the first power line 21 to include the fifth power supply unit 215 and the sixth power supply unit 216, the second power supply unit 212, the third power supply unit 213, the fourth power supply unit 214, the fifth power supply unit 215 and the sixth power supply unit 216 can jointly form a mesh structure. This setting method further improves the brightness uniformity of the display of the display substrate.

[0126] As shown in Figure 19, in some embodiments, the first power line 21 further includes at least one compensation power supply unit 219, which is coupled to the second power supply unit 212 and the fifth power supply unit 215 respectively, and at least a portion of the compensation power supply unit 219 is located in the sealing frame area 20.

[0127] Exemplarily, the compensation power supply unit 219 is provided in the same layer and with the same material as the first source / drain metal layer.

[0128] Exemplarily, the compensation power supply unit 219 and the second source / drain metal layer are provided in the same layer and with the same material.

[0129] Exemplarily, the compensation power supply unit 219 forms an integrated structure with the second power supply unit 212 and the fifth power supply unit 215 .

[0130] The above configuration of the first power line 21 further includes at least one compensation power supply unit 219 , which improves the transmission performance of the first power line 21 and improves the IR Drop of the first power line 21 .

[0131] As shown in Figures 20 and 21, in some embodiments, the fifth power supply unit 215 includes a first sub-unit 2151 and a second sub-unit 2152 arranged in a stacked manner, and the orthographic projection of the first sub-unit 2151 on the base substrate 70 and the orthographic projection of the second sub-unit 2152 on the base substrate 70 have an overlapping area, and in this overlapping area, the first sub-unit 2151 and the second sub-unit 2152 are coupled through at least one via Via3.

[0132] Exemplarily, the first sub-portion 2151 is provided in the same layer and material as the first source / drain metal layer, and the second sub-portion 2152 is provided in the same layer and material as the second source / drain metal layer.

[0133] The fifth power supply unit 215 includes a first sub-unit 2151 and a second sub-unit 2152 that are stacked, which improves the transmission performance of the first power line 21 and improves the IR Drop of the first power line 21 .

[0134] As shown in Figure 3, in some embodiments, the display substrate also includes a first signal input terminal; the first power line 21 includes a sixth power supply unit 216 and a seventh power supply unit 217, the sixth power supply unit 216 is coupled to the second power supply unit 212, the seventh power supply unit 217 includes a first part 2171 and two second parts 2172, the first part 2171 extends along the first direction, the first part 2171 is respectively coupled to the sixth power supply unit 216 and the two second parts 2172, the second part 2172 extends along the second direction, the second part 2172 is coupled to the first signal input terminal, and the first direction intersects with the second direction.

[0135] Illustratively, the sixth power supply portion 216 and the first power connection portion 2101 are arranged along the second direction.

[0136] Illustratively, the sixth power supply unit 216 is arranged in the same layer as the first gate metal layer in the display substrate, the sixth power supply unit 216 is coupled to the second power supply unit 212 through a via, and the sixth power supply unit 216 is coupled to the seventh power supply unit 217 through a via.

[0137] Exemplarily, the first part 2171 and the two second parts 2172 form an integral structure.

[0138] Illustratively, both ends of the first portion 2171 are coupled to the two second portions 2172 in a one-to-one correspondence, and the middle portion of the first portion 2171 is coupled to the sixth power supply unit 216 .

[0139] Illustratively, the seventh power supply unit 217 is located on a side of the sealing frame area 20 away from the display area 1 .

[0140] Exemplarily, the seventh power supply unit 217 is provided in the same layer as the first source / drain metal layer in the display substrate.

[0141] In the display substrate provided in the above embodiment, the sixth power supply unit 216 is arranged on the same layer as the first gate metal layer and / or the second gate metal layer, and other structures in the sealing frame area 20 are all made of the first gate metal layer and / or the second gate metal layer. This design makes it possible for the structures located in the sealing frame area 20 to only use the first gate metal layer and / or the second gate metal layer, thereby avoiding the step difference in the sealing frame area 20 caused by the first source and drain metal layer, improving the bonding reliability of the frame sealing glue, and significantly improving the problem of the entire device falling.

[0142] As shown in FIG1 , FIG2 , FIG4 , FIG6 , FIG7 , FIG8 , and FIG10 , in some embodiments, the display substrate further includes:

[0143] a second power line 22, the second power line 22 comprising an eighth power supply unit 220 and two ninth power supply units 221, the eighth power supply unit 220 being arranged around the display area 1, the two ninth power supply units 221 being coupled to two ends of the eighth power supply unit 220 in a one-to-one correspondence;

[0144] The ninth power supply unit 221 is coupled to the second signal input terminal 62 .

[0145] Exemplarily, the second power line 22 includes a negative power signal line, but is not limited thereto. The second power line 22 is coupled to a cathode in the display substrate to provide a signal to the cathode.

[0146] Exemplarily, the eighth power supply unit 220 is at least partially arranged around the display area 1, the two ends of the eighth power supply unit 220 form openings in the lower frame of the display substrate, and the two ninth power supply units 221 are coupled to the two ends of the eighth power supply unit 220 in a one-to-one manner.

[0147] Exemplarily, the second signal input terminal 62 is used to provide a second power signal to the second power line 22 .

[0148] Illustratively, at least a portion of the ninth power supply unit 221 extends along the second direction.

[0149] As shown in FIG6 , FIG7 and FIG10 , in some embodiments, the display substrate includes a first gate metal layer, a second gate metal layer, a first source-drain metal layer and a second source-drain metal layer stacked in sequence in a direction away from the base substrate;

[0150] At least a portion of the ninth power supply portion 221 is located in the sealing frame area 20 , and the ninth power supply portion 221 is disposed in the same layer as the first source / drain metal layer in the display substrate.

[0151] Illustratively, the two ninth power supply units 221 included in the display substrate are symmetrically arranged, and the axis of symmetry is located between the two ninth power supply units 221 .

[0152] Illustratively, a hollow area is provided on the ninth power supply unit 221 , so as to increase the adhesion between the frame sealing glue in the frame sealing area 20 and the frame base.

[0153] Illustratively, the ninth power supply unit 221 and at least a portion of the eighth power supply unit 220 form an integrated structure.

[0154] As shown in FIG. 6 , illustratively, a width d7 of a portion of the ninth power supply unit 221 located in the frame sealing area 20 is greater than a width d8 of a portion of the ninth power supply unit 221 located in the non-frame sealing area 20 .

[0155] Exemplarily, the ninth power supply unit 221 and the third power supply unit 213 included in the first power line 21 are both provided in the same layer as the first source-drain metal layer.

[0156] The above-mentioned setting of the ninth power supply unit 221 and the first source-drain metal layer in the same layer enables the ninth power supply unit 221 to be formed in the same patterning process as the first source-drain metal layer, avoiding the introduction of an additional patterning process for the production of the ninth power supply unit 221, thereby effectively simplifying the production process flow of the display substrate and reducing the production cost of the display substrate.

[0157] In the display substrate provided by the above embodiment, the ninth power supply unit 221 and the third power supply unit 213 included in the first power line 21 are both arranged on the same layer as the first source-drain metal layer, and the other structures in the sealing frame area 20 are all made of the first gate metal layer or the second gate metal layer. This can greatly reduce the proportion of the first source-drain metal layer in the sealing frame area 20, and reduce the step difference in the sealing frame area 20 caused by the first source-drain metal layer, thereby improving the bonding reliability of the frame sealing glue and significantly improving the problem of the whole machine falling.

[0158] As shown in FIG8 , in some embodiments, the display substrate includes a first gate metal layer, a second gate metal layer, a first source / drain metal layer, and a second source / drain metal layer stacked in sequence in a direction away from the base substrate;

[0159] At least a portion of the eighth power supply unit 220 is located in the sealing frame area 20 , and at least a portion of the eighth power supply unit 220 (such as the sixth portion 2202 ) is disposed in the same layer as the first gate metal layer in the display substrate.

[0160] Illustratively, a portion of the eighth power supply unit 220 located in the sealing frame area 20 is reused as a sealing frame substrate and is in contact with the sealing glue.

[0161] The above arrangement increases the area of ​​the structure made of the first gate metal layer in the sealing frame area 20, reduces the step difference caused by the first source and drain metal layer in the sealing frame area 20, improves the bonding reliability of the frame sealing glue, and significantly improves the problem of the whole device falling.

[0162] The above-mentioned setting of the eighth power supply unit 220 and the first gate metal layer on the same layer enables the eighth power supply unit 220 to be formed in the same patterning process as the first gate metal layer, avoiding the introduction of an additional patterning process for the production of the eighth power supply unit 220, thereby effectively simplifying the production process flow of the display substrate and reducing the production cost of the display substrate.

[0163] As shown in Figures 6, 7 and 17, in some embodiments, the display substrate further includes a fan-out line 4, and at least a portion of the orthographic projection of the fan-out line 4 on the base substrate is located between the orthographic projection of the eighth power supply unit 220 on the base substrate and the display area 1.

[0164] As shown in Figure 1, exemplarily, the display substrate also includes a plurality of data lines DA, at least part of the data lines DA is located in the display area 1, the plurality of data lines DA are arranged along the first direction, the data line DA includes at least a part extending along the second direction, the data line DA is coupled to the corresponding fan-out line 4, the fan-out line 4 is coupled to the corresponding data signal input end, and the data signal provided by the data signal input end is transmitted to the data line DA via the fan-out line 4.

[0165] In the display substrate provided in the above embodiment, the eighth power supply unit 220 extends around part of the fan-out line 4, extends from the lower frame of the display substrate to the corners of the left frame and the right frame of the display substrate, is connected to the first gate metal layer and the interlayer insulating layer at the corners of the left frame and the right frame, and is then electrically connected to the first source and drain metal layer that transmits the second power supply signal through vias.

[0166] As shown in FIG4 , in some embodiments, the display substrate includes a first gate metal layer, a second gate metal layer, a first source-drain metal layer, and a second source-drain metal layer stacked in sequence in a direction away from the base substrate;

[0167] The ninth power supply unit 221 includes a third part 2210 and a fourth part 2211 coupled to each other, at least a portion of the third part 2210 is located in the sealing frame area 20, and the fourth part 2211 is located in an area outside the sealing frame area 20, the third part 2210 is arranged in the same layer as the first gate metal layer in the display substrate, the third part 2210 and the eighth power supply unit 220 are an integrated structure, and the fourth part 2211 is arranged in the same layer as the first source and drain metal layer in the display substrate.

[0168] Exemplarily, the third portion 2210 and the fourth portion 2211 are electrically connected through a via.

[0169] Exemplarily, the third portion 2210 includes multiple openings, the source / drain metal layer includes multiple groups of vias, each group of vias includes multiple vias distributed in an array, and the orthographic projection of each group of vias on the substrate is located within the orthographic projection of a corresponding opening on the substrate. This arrangement can increase the bonding area between the frame sealant and the frame base, improving the bonding between the frame sealant and the frame base. It is worth noting that the third power supply unit 213 can also be provided with this structure of openings and multiple groups of vias.

[0170] Disposing the third portion 2210 in the same layer as the first gate metal layer can reduce the step difference generated by the first source / drain metal layer in the sealing region 20 , thereby better improving the adhesive reliability of the sealing adhesive.

[0171] As shown in FIG4 , FIG6 , FIG7 and FIG8 , in some embodiments, the display substrate further includes a fan-out line 4; the eighth power supply unit 220 includes a fifth portion 2201 and a sixth portion 2202 , wherein the orthographic projection of the fifth portion 2201 on the base substrate is located between the orthographic projection of the sixth portion 2202 on the base substrate and the display area 1 ; the fifth portion 2201 and the sixth portion 2202 are respectively coupled to the ninth power supply unit 221 ;

[0172] At least a portion of the orthographic projection of the fan-out line 4 on the substrate is located between the orthographic projection of the fifth portion 2201 on the substrate and the orthographic projection of the sixth portion 2202 on the substrate.

[0173] As shown in Figures 11 and 12, in the border areas at the lower left and lower right corners of the display substrate, the fifth part 2201 is arranged in the same layer as the first source and drain metal layer, and the sixth part 2202 is arranged in the same layer as the first gate metal layer. The sixth part 2202 includes a plurality of protrusions, and the orthographic projection of the protrusions on the base substrate overlaps with the orthographic projection of the fifth part 2201 on the base substrate. The fifth part 2201 and the sixth part 2202 are coupled through vias in the overlapping area.

[0174] As shown in Figures 11 and 12, a first via Via1 is provided on the sixth part, and a second via Via2 is formed on the subsequently formed interlayer insulating layer. The size of the second via Via2 is smaller than the size of the first via Via1. The second vias Via2 are divided into multiple groups, and the orthographic projection of each group on the substrate is located inside the orthographic projection of the corresponding first via Via1 on the substrate.

[0175] Exemplarily, the fifth portion 2201 is provided on the same layer as the first source / drain metal layer in the display substrate, and the sixth portion 2202 is provided on the same layer as the first gate metal layer in the display substrate. The fifth portion 2201 and the ninth power supply portion 221 form an integrated structure.

[0176] The above configuration enables the fifth portion 2201 , the sixth portion 2202 and the ninth power supply portion 221 to form a mesh structure. This mesh structure makes the second power signal transmitted by the second power line 22 more uniform without any mutation points, which is more conducive to LRU.

[0177] As shown in FIG. 14 to FIG. 16 , in some embodiments, the display substrate further includes a plurality of fan-out lines 4 , at least some of the fan-out lines 4 include fan-out compensation portions 40 , and at least some of the fan-out compensation portions 40 are located in the sealing frame area 20 .

[0178] Exemplarily, in order to ensure uniformity of loads on various data lines, a fan-out compensation portion 40 is provided for some fan-out lines 4 . The fan-out compensation portion 40 may include a folded bow-shaped trace, but is not limited thereto.

[0179] Exemplarily, the lengths of the fan-out compensation parts 40 included in each fan-out line 4 are different, but not limited thereto.

[0180] Exemplarily, all fan-out compensation parts 40 are disposed in the sealing frame area 20 and reused as the sealing frame substrate.

[0181] The fan-out compensation portion 40 is arranged in the sealing frame area 20 and reused as the sealing frame substrate, which can effectively increase the contact area between the sealing glue and the sealing frame substrate, improve the packaging capability, and achieve better water and oxygen barrier properties and sealing effects.

[0182] As shown in Figures 14 and 15, in some embodiments, the display substrate further includes: a frame compensation portion 50, which is located in the frame area 20. In the frame area 20, the layout density of the frame compensation portion 50 is the same as the layout density of the fan-out line 4.

[0183] Exemplarily, the sealing frame compensation portion 50 is provided in the same layer as the first gate metal layer and / or the second gate metal layer in the display substrate.

[0184] Exemplarily, the sealing frame compensation portion 50 includes a strip-shaped pattern extending along the second direction. The packaging compensation portion is disposed in the sealing frame area 20 , in the spacing area between adjacent fan-out lines 4 .

[0185] Exemplarily, the sealing frame compensation portion 50 is insulated from the fan-out line 4 .

[0186] Exemplarily, the sealing frame compensation portion 50 is reused as the sealing frame substrate.

[0187] The above-mentioned provision of the frame sealing compensation portion 50 in the frame sealing area 20 can effectively increase the contact area between the frame sealing glue and the frame sealing base, improve the packaging capability, and achieve better water and oxygen barrier properties and sealing effects.

[0188] As shown in Figure 16, in some embodiments, the display substrate also includes multiple fan-out lines 4, at least some of the fan-out lines 4 include fan-out compensation parts 40, the lengths of the fan-out compensation parts 40 included in each fan-out line 4 are approximately the same, and the fan-out compensation parts 40 are evenly arranged in the sealing frame area 20.

[0189] Exemplarily, the lengths of the fan-out compensation parts 40 included in each fan-out line 4 are the same or similar.

[0190] The above-mentioned provision of the frame sealing compensation portion 50 in the frame sealing area 20 can effectively increase the contact area between the frame sealing glue and the frame sealing base, improve the packaging capability, and achieve better water and oxygen barrier properties and sealing effects.

[0191] In some embodiments, a portion of the display substrate located in the sealing frame area 20 is disposed in the same layer as at least one of the first gate metal layer and the second gate metal layer in the display substrate.

[0192] Illustratively, in the display substrate, a portion located in the sealing region 20 serving as a sealing frame base is provided in the same layer as at least one of the first gate metal layer and the second gate metal layer in the display substrate.

[0193] The above configuration can avoid the step difference caused by the first source / drain metal layer in the sealing frame area 20 , thereby better improving the adhesive reliability of the sealing adhesive and improving the drop NG of the entire device.

[0194] As shown in FIG5 and FIG6 , an embodiment of the present disclosure further provides a display substrate, including a base substrate, wherein the base substrate includes a display area 1 and a frame area 2 located around the display area 1, wherein the frame area 2 includes a sealing frame area 20; the display substrate further includes:

[0195] a plurality of sub-pixels, wherein the plurality of sub-pixels are located in the display area 1;

[0196] a plurality of power supply units 218 , each of which is located at least in the display area 1 and electrically connected to the plurality of sub-pixels;

[0197] a first power line 21, the first power line 21 comprising a first power supply portion 211, a second power supply portion 212 and a plurality of power connection portions 210, the first power supply portion 211 being located between the second power supply portion 212 and the display area 1, at least a portion of the second power supply portion 212 being located between the display area 1 and the sealing frame area 20, the first power supply portion 211 being coupled to the plurality of power supply portions 218, the plurality of power connection portions 210 being located between the first power supply portion 211 and the second power supply portion 212, and being coupled to the first power supply portion 211 and the second power supply portion 212; the first power line further comprising two third power supply portions 213 and a sixth power supply portion 216, the third power supply portion 213 and the sixth power supply portion 216 being coupled to the second power supply portion 212, the orthographic projection of the sixth power supply portion 216 on the substrate being located between the orthographic projections of the two third power supply portions 213 on the substrate;

[0198] Multiple fan-out lines 4, at least some of the fan-out lines 4 include a fan-out portion extending along the second direction, and at least part of the orthographic projection of the fan-out portion on the substrate is located between the orthographic projection of the third power supply portion 213 on the substrate and the orthographic projection of the sixth power supply portion 216 on the substrate.

[0199] The above-mentioned setting method can concentrate the fan-out part between the third power supply unit 213 and the sixth power supply unit 216, and then extend it to the position where the driver chip is located and connect with the driver chip to receive the corresponding signal. This method is conducive to reducing the difficulty of binding the driver chip and reducing the border width of the display substrate.

[0200] In some embodiments, a multiplexer circuit 3 is further included, and at least part of the orthographic projection of the multiplexer circuit 3 on the substrate is located in an area surrounded by the first power supply unit 211 , the second power supply unit 212 and the multiple power connection units 210 .

[0201] The above configuration can disperse the multiplexer circuits, so that the display substrate can better achieve a narrow frame.

[0202] An embodiment of the present disclosure further provides a display device, comprising the display substrate provided by the above embodiment.

[0203] It should be noted that the display device can be any product or component with a display function, such as a television, monitor, digital photo frame, mobile phone, tablet computer, etc., wherein the display device also includes a flexible circuit board, printed circuit board, and backplane. The display device can also be a flexible wearable OLED display product or a rigid wearable OLED display product.

[0204] In the display substrate provided in the above embodiment, the first power line is configured to include the first power supply unit, the second power supply unit, and the multiple power connection units, and the multiplexer units and the power connection units are arranged alternately, so that the first power line forms a mesh structure that can be interspersed between the multiplexer circuits, allowing the first power line to be introduced into the display area in multiple ways. This arrangement can, on the one hand, reduce the line widths of the first power supply unit, the second power supply unit, and the power connection units, thereby reducing the space occupied by the first power line and enabling the display substrate to achieve a narrow frame. On the other hand, the multiple-way introduction of the mesh structure can effectively improve the uniformity of the power signal transmitted by the first power line, enhance the LRU, and improve the display brightness uniformity of the display substrate.

[0205] The display device provided by the embodiment of the present disclosure also has the above-mentioned beneficial effects when it includes the above-mentioned display substrate, which will not be described in detail here.

[0206] It should be noted that the signal line extending along the X-direction means that the signal line includes a main portion and a secondary portion connected to the main portion, the main portion is a line, a line segment, or a strip-shaped body, the main portion extends along the X-direction, and the length of the main portion extending along the X-direction is greater than the length of the secondary portion extending along other directions.

[0207] It should be noted that the "same layer" in the embodiment of the present disclosure may refer to a film layer on the same structural layer. Or, for example, a film layer in the same layer may be a film layer formed by using the same film forming process to form a specific pattern, and then patterning the film layer using the same mask through a single composition process to form a layer structure. Depending on the specific pattern, a single composition process may include multiple exposure, development or etching processes, and the specific pattern in the formed layer structure may be continuous or discontinuous. These specific patterns may also be at different heights or have different thicknesses.

[0208] In the various method embodiments of the present disclosure, the serial numbers of the steps cannot be used to limit the order of the steps. For ordinary technicians in this field, without paying any creative work, changes to the order of the steps are also within the scope of protection of the present disclosure.

[0209] It should be noted that the various embodiments in this specification are described in a progressive manner. Similar parts between the various embodiments can be referred to in conjunction with each other. Each embodiment focuses on the differences from other embodiments. In particular, the method embodiments are described briefly because they are generally similar to the product embodiments. For relevant parts, refer to the description of the product embodiments.

[0210] Unless otherwise defined, the technical or scientific terms used in this disclosure should have the usual meanings understood by persons of ordinary skill in the field to which this disclosure belongs. The words "first", "second" and similar terms used in this disclosure do not indicate any order, quantity or importance, but are only used to distinguish different components. Words such as "include" or "comprise" mean that the elements or objects appearing before the word include the elements or objects listed after the word and their equivalents, without excluding other elements or objects. Words such as "connect", "couple" or "connected" are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. "Up", "down", "left", "right" and the like are only used to indicate relative positional relationships. When the absolute position of the object being described changes, the relative positional relationship may also change accordingly.

[0211] It will be understood that when an element such as a layer, film, region, or substrate is referred to as being “on” or “under” another element, it can be “directly on” or “under” the other element or intervening elements may be present.

[0212] In the description of the above embodiments, specific features, structures, materials or characteristics may be combined in an appropriate manner in any one or more embodiments or examples.

[0213] The above description is merely a specific embodiment of the present disclosure, but the scope of protection of the present disclosure is not limited thereto. Any changes or substitutions that can be easily conceived by a person skilled in the art within the technical scope disclosed in this disclosure should be included in the scope of protection of the present disclosure. Therefore, the scope of protection of the present disclosure should be based on the scope of protection of the claims.

Claims

1. A display substrate comprising a base substrate, the base substrate comprising a display area and a frame area located around the display area, the frame area comprising a sealing frame area; the display substrate further comprising: a plurality of sub-pixels, wherein the plurality of sub-pixels are located in the display area; a plurality of power supply units, each of which is located at least in the display area and electrically connected to the plurality of sub-pixels; a first power line, the first power line comprising a first power supply portion, a second power supply portion, and a plurality of power connection portions, the first power supply portion being located between the second power supply portion and the display area, at least a portion of the second power supply portion being located between the display area and the sealing frame area, the first power supply portion being coupled to the plurality of power supply portions, and the plurality of power connection portions being located between the first power supply portion and the second power supply portion and coupled to the first power supply portion and the second power supply portion; a multiplexer circuit, wherein at least a portion of an orthographic projection of the multiplexer circuit on the base substrate is located between an orthographic projection of the first power supply portion on the base substrate and an orthographic projection of the second power supply portion on the base substrate; The multiplexer circuit includes a plurality of multiplexer units, and the plurality of multiplexer units are alternately arranged with the plurality of power connection portions.

2. The display substrate according to claim 1, wherein The plurality of power connection portions include a first power connection portion and a plurality of second power connection portions, the plurality of second power connection portions include two groups of connection portion groups, and the orthographic projection of the first power connection portion on the base substrate is located between the orthographic projections of the two groups of connection portion groups on the base substrate; The width of the first power connection portion in a direction perpendicular to its own extension direction is greater than the width of the second power connection portion in a direction perpendicular to its own extension direction.

3. The display substrate according to claim 1, wherein A line width d3 of the second power supply portion perpendicular to its own extending direction satisfies: 15 μm≤d3≤25 μm.

4. The display substrate according to claim 1, wherein: The display substrate includes a first gate metal layer, a second gate metal layer, a first source-drain metal layer, and a second source-drain metal layer, which are stacked in sequence in a direction away from the base substrate; the power connection portion is arranged on the same layer as at least one of the first gate metal layer, the second gate metal layer, the first source-drain metal layer, and the second source-drain metal layer.

5. The display substrate according to any one of claims 1 to 4, wherein The first power line further includes at least one third power portion, the third power portion is coupled to the second power portion, and at least a portion of the third power portion is located in the sealing frame area; The third power supply unit is arranged in the same layer as at least one of the first gate metal layer, the second gate metal layer and the first source-drain metal layer in the display substrate. The display substrate according to claim 5 , wherein: The display substrate also includes a first signal input terminal; the first power line includes two third power supply units, which are symmetrically arranged; the first power line also includes two fourth power supply units, which are respectively coupled to the corresponding third power supply units and the first signal input terminal.

7. The display substrate according to claim 6, wherein: The first power line also includes a fifth power supply unit and a sixth power supply unit, the fifth power supply unit is located between the two fourth power supply units, the fifth power supply unit is coupled to the two fourth power supply units respectively, at least part of the sixth power supply unit is located in the sealing frame area, and the sixth power supply unit is coupled to the fifth power supply unit and the second power supply unit respectively.

8. The display substrate according to any one of claims 1 to 4, wherein The display substrate also includes a first signal input terminal; the first power line includes a sixth power supply unit and a seventh power supply unit, the sixth power supply unit is coupled to the second power supply unit, the seventh power supply unit includes a first part and two second parts, the first part extends along a first direction, the first part is coupled to the sixth power supply unit and the two second parts respectively, the second part extends along a second direction, the second part is coupled to the first signal input terminal, and the first direction intersects with the second direction.

9. The display substrate according to any one of claims 1 to 4, wherein The display substrate further includes: a second power line, the second power line comprising an eighth power supply unit and two ninth power supply units, the eighth power supply unit being arranged around the display area, the two ninth power supply units being coupled to two ends of the eighth power supply unit in a one-to-one correspondence; The ninth power supply unit is coupled to the second signal input terminal.

10. The display substrate according to claim 9, wherein: The display substrate comprises a first gate metal layer, a second gate metal layer, a first source-drain metal layer and a second source-drain metal layer stacked in sequence in a direction away from the base substrate; At least a portion of the ninth power supply unit is located in the sealing frame area, and the ninth power supply unit is provided in the same layer as the first source / drain metal layer.

11. The display substrate according to claim 9, wherein: The display substrate comprises a first gate metal layer, a second gate metal layer, a first source-drain metal layer and a second source-drain metal layer stacked in sequence in a direction away from the base substrate; At least a portion of the eighth power supply unit is located in the sealing frame area, and at least a portion of the eighth power supply unit is disposed in the same layer as the first gate metal layer.

12. The display substrate according to claim 11, wherein: The display substrate further includes a fan-out line, and at least a portion of an orthographic projection of the fan-out line on the base substrate is located between an orthographic projection of the eighth power supply unit on the base substrate and the display area.

13. The display substrate according to claim 9, wherein: The display substrate comprises a first gate metal layer, a second gate metal layer, a first source-drain metal layer and a second source-drain metal layer stacked in sequence in a direction away from the base substrate; The ninth power supply unit includes a third part and a fourth part coupled to each other, at least a portion of the third part is located in the sealing frame area, and the fourth part is located in an area outside the sealing frame area. The third part is arranged in the same layer as the first gate metal layer in the display substrate, the third part and the eighth power supply unit are an integrated structure, and the fourth part is arranged in the same layer as the first source and drain metal layer.

14. The display substrate according to claim 9, wherein: The display substrate further includes a fan-out line; the eighth power supply unit includes a fifth portion and a sixth portion, the orthographic projection of the fifth portion on the base substrate being located between the orthographic projection of the sixth portion on the base substrate and the display area; The fifth portion and the sixth portion are respectively coupled to the ninth power supply portion; At least a portion of an orthographic projection of the fan-out line on the substrate is located between an orthographic projection of the fifth portion on the substrate and an orthographic projection of the sixth portion on the substrate.

15. The display substrate according to claim 1, wherein The display substrate further includes a plurality of fan-out lines, at least some of the fan-out lines include fan-out compensation portions, and at least some of the fan-out compensation portions are located in the sealing frame area.

16. The display substrate according to claim 15, wherein: The display substrate further includes a frame compensation portion, which is located in the frame area. In the frame area, a layout density of the frame compensation portion is the same as a layout density of the fan-out lines.

17. The display substrate according to claim 1, wherein The display substrate further includes a plurality of fan-out lines, at least some of the fan-out lines include fan-out compensation parts, the fan-out compensation parts included in each fan-out line have substantially the same length, and the fan-out compensation parts are evenly arranged in the sealing frame area.

18. A display substrate comprising a base substrate, the base substrate comprising a display area and a frame area located around the display area, the frame area comprising a sealing frame area; the display substrate further comprising: a plurality of sub-pixels, wherein the plurality of sub-pixels are located in the display area; a plurality of power supply units, each of which is located at least in the display area and electrically connected to the plurality of sub-pixels; a first power line, the first power line comprising a first power supply portion, a second power supply portion, and a plurality of power connection portions, the first power supply portion being located between the second power supply portion and the display area, at least a portion of the second power supply portion being located between the display area and the sealing frame area, the first power supply portion being coupled to the plurality of power supply portions, the plurality of power connection portions being located between the first power supply portion and the second power supply portion, and coupled to the first power supply portion and the second power supply portion; the first power line further comprising two third power supply portions and a sixth power supply portion, the third power supply portion and the sixth power supply portion being coupled to the second power supply portion, the orthographic projection of the sixth power supply portion on the base substrate being located between the orthographic projections of the two third power supply portions on the base substrate; A plurality of fan-out lines, at least some of the fan-out lines include a fan-out portion extending along the second direction, and at least a portion of an orthographic projection of the fan-out portion on the substrate is located between an orthographic projection of the third power supply portion on the substrate and an orthographic projection of the sixth power supply portion on the substrate.

19. The display substrate according to claim 18, wherein: A multiplexer circuit is further included, wherein at least a portion of an orthographic projection of the multiplexer circuit on the base substrate is located within an area surrounded by the first power supply unit, the second power supply unit, and the plurality of power connection units.

20. A display device comprising the display substrate according to any one of claims 1 to 19.

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