Device and method for configuring operating range of adaptive synchronization

Abstract

According to various embodiments of the present disclosure, provided is an operation method of a source device, the method comprising the steps of: receiving a hot plug detection (HPD) signal from a sink device; receiving extended display identification data (EDID) and a DisplayID from the sink device; determining an adaptive sync data block and a frame rate on the basis of the EDID and the DisplayID of the sink device; and transmitting a session description protocol (SDP) generated on the basis of the determined adaptive sync data block and information on the determined frame rate to the sink device.

Description

Device and method for setting the operating range of adaptive synchronization

[0001] The present disclosure relates to a device and method for performing an adaptive sync operation. Specifically, the present disclosure relates to a device and method for setting an accurate frame range based on relevant information for performing an adaptive sync operation in a display device.

[0002]

[0003] Adaptive-Sync is a technology used in computer graphics that synchronizes the graphics card and monitor to eliminate screen flickering and tearing. Adaptive-Sync was standardized by the Video Electronics Standards Association (VESA) on DisplayPort Adaptive-Sync and HDMI VRR (Variable Refresh Rate) technologies.

[0004] Adaptive-Sync technology includes a communication protocol for communication between the graphics card and the monitor, as well as time-splitting technology for synchronization between the two. Therefore, Adaptive-Sync technology encompasses the following technical areas:

[0005] (1) Graphics card technology: To support Adaptive-Sync, the graphics card must support Variable Refresh Rate (VRR) technology. AMD provides FreeSync, and NVIDIA provides G-Sync, each with their own VRR technology.

[0006] (2) Communication Protocol Technology: Display connection interfaces supporting Adaptive-Sync require DisplayPort 1.2a or higher and HDMI 2.1 or higher. Furthermore, to use Adaptive-Sync, the graphics card and monitor must use the same communication protocol.

[0007] (3) Monitor Technology: A monitor that supports Adaptive-Sync must support the graphics card's VRR technology. Additionally, a monitor that supports Adaptive-Sync must support a protocol for communication with the graphics card.

[0008] (4) Time-slicing technology: Adaptive-Sync uses time-slicing technology to synchronize the monitor and graphics card. To achieve this, both the graphics card and monitor must use the same time-slicing technology.

[0009] Adaptive-Sync technology encompasses a variety of technologies, including graphics cards, communication protocols, monitors, and time-slicing technology, all of which work together to make Adaptive-Sync possible.

[0010] For Adaptive-Sync operation, the Sink can indicate the frame range in each of the three blocks: Base EDID1.4 - Range Limit Block, DisplayID1.x - Video Timing Range Limits Data Block, and DisplayID2.x - Adaptive-Sync Data Block. This may make it difficult for the Source to perform accurate Adaptive-Sync operation if the frame ranges of the three blocks are different. In addition, the maximum frame rate and whether multiple frame ranges can be indicated are different for each block, as shown below.

[0011] (1) EDID1.4 Display Range Limit Block: Only one frame range can be displayed, and only up to 510 Hz can be displayed.

[0012] (2) DisplayID1.x Video Timing Range Limits Data Block: Only one frame range is displayed, and a maximum of 255 Hz can be displayed.

[0013] (3) DisplayID2.x Adaptive-Sync Data Block: Multiple frame ranges can be displayed, and up to 1024 Hz can be displayed.

[0014] Therefore, when the Frame Range is expressed differently for each Block, a method needs to be introduced for the Source to read the Frame range information of the Sink and use it consistently for normal Adaptive-Sync operation.

[0015]

[0016] In order to solve the above-described problem, the present disclosure can provide a method and device for setting an accurate frame range according to relevant information to perform an adaptive-sync operation in a display device.

[0017] The present disclosure can provide a device and method for a source to read and consistently use frame range information of a sink for normal adaptive-sync operation when the frame range is expressed differently for each block.

[0018] The technical problems to be achieved in the present disclosure are not limited to the technical problems mentioned above, and other technical problems not mentioned can be clearly understood by a person having ordinary skill in the technical field to which the present disclosure belongs from the description below.

[0019]

[0020] According to various embodiments of the present disclosure, a method of operating a source device is provided, comprising: receiving a hot plug detection (HPD) signal from a sink device; receiving an extended display identification (EDID) and a display ID from the sink device; determining an adaptive sync data block and a frame rate based on the EDID and the display ID of the sink device; and transmitting an SDP (session description protocol) generated based on the determined adaptive sync data block and information on the determined frame rate to the sink device.

[0021] According to various embodiments of the present disclosure, a Source device is provided, comprising: a processor; a memory; and a transceiver, wherein the memory stores instructions for performing operations based on what is executed by the processor, the operations including: receiving a hot plug detection (HPD) signal from a Sink device; receiving an Extended Display Identification (EDID) and a DisplayID from the Sink device; determining an Adaptive Sync Data Block and a frame rate based on the EDID and the DisplayID of the Sink device; and transmitting an SDP (Session Description Protocol) generated based on the determined Adaptive Sync Data Block and information on the determined frame rate to the Sink device.

[0022] According to various embodiments of the present disclosure, there is provided a computer-readable medium storing one or more non-transitory commands, wherein the one or more commands perform operations based on being executed by one or more processors, the operations including: receiving a hot plug detection (HPD) signal from a Sink device; receiving an Extended Display Identification (EDID) and a DisplayID from the Sink device; determining an Adaptive Sync Data Block and a frame rate based on the EDID and the DisplayID of the Sink device; and transmitting an SDP (Session Description Protocol) generated based on the determined Adaptive Sync Data Block and information on the determined frame rate to the Sink device.

[0023]

[0024] In order to solve the above-described problem, the present disclosure can provide a method and device for setting an accurate frame range according to relevant information to perform an adaptive-sync operation in a display device.

[0025] The present disclosure can provide a device and method for a source to read and consistently use frame range information of a sink for normal adaptive-sync operation when the frame range is expressed differently for each block.

[0026]

[0027] The accompanying drawings are intended to aid in understanding the present disclosure and, together with detailed descriptions, may provide embodiments of the present disclosure. However, the technical features of the present disclosure are not limited to specific drawings, and the features disclosed in each drawing may be combined with each other to form new embodiments. Reference numerals in each drawing may indicate structural elements.

[0028] FIG. 1 is a block diagram illustrating a system according to various embodiments of the present disclosure.

[0029] FIG. 2 is a diagram illustrating an example of Adaptive-Sync SDP transmission timing according to various embodiments of the present disclosure.

[0030] FIG. 3 is a diagram illustrating an example of an AUX flowchart related to Adaptive-Sync operation according to various embodiments of the present disclosure.

[0031] FIG. 4 is a diagram illustrating an example of the structure of an EDID in which an EDID block, a CTA block, and a DisplayID block are mixed according to various embodiments of the present disclosure.

[0032] FIG. 5 is a diagram illustrating an example of the structure of a Display Range Limit Block in EDID1.4 according to various embodiments of the present disclosure.

[0033] FIG. 6 is a diagram illustrating an example of the structure of a Video Timing Range Limits Data Block in DisplayID 1.3 according to various embodiments of the present disclosure.

[0034] FIG. 7 is a diagram illustrating an example of the structure of an Adaptive-Sync Data Block in DisplayID 2.0 according to various embodiments of the present disclosure.

[0035] FIG. 8 is a diagram illustrating an example of a case where Range Limit Block & Video Timing Range (175 Hz) > Adaptive Sync Data Block (144 Hz) according to various embodiments of the present disclosure.

[0036] FIG. 9 is a diagram illustrating an example of a case where Range Limit Block & Video Timing Range (175 Hz) < Adaptive Sync Data Block (500 Hz) according to various embodiments of the present disclosure.

[0037] Figure 10 is a diagram illustrating an example of a process for determining a Frame Range during conventional Adaptive-Sync operation.

[0038] FIG. 11 is a diagram illustrating an example of a process for determining a Frame Range during Adaptive-Sync operation according to various embodiments of the present disclosure.

[0039] FIG. 12 is a diagram illustrating an example of a process for determining a Frame Range during Adaptive-Sync operation according to various embodiments of the present disclosure.

[0040] FIG. 13 is a diagram illustrating an example of a process for determining a Frame Range during Adaptive-Sync operation according to various embodiments of the present disclosure.

[0041] FIG. 14 is a diagram illustrating an example of an operation method of a source device according to various embodiments of the present disclosure.

[0042]

[0043] In various embodiments of the present disclosure, “A or B” may mean “only A,” “only B,” or “both A and B.” In other words, in various embodiments of the present disclosure, “A or B” may be interpreted as “A and / or B.” For example, in various embodiments of the present disclosure, “A, B or C” may mean “only A,” “only B,” “only C,” or “any combination of A, B and C.”

[0044] In various embodiments of the present disclosure, a slash ( / ) or a comma may mean "and / or." For example, "A / B" may mean "A and / or B." Accordingly, "A / B" may mean "only A," "only B," or "both A and B." For example, "A, B, C" may mean "A, B, or C."

[0045] In various embodiments of the present disclosure, “at least one of A and B” may mean “only A,” “only B,” or “both A and B.” Furthermore, in various embodiments of the present disclosure, the expressions “at least one of A or B” or “at least one of A and / or B” may be interpreted as equivalent to “at least one of A and B.”

[0046] Additionally, in various embodiments of the present disclosure, “at least one of A, B and C” can mean “only A,” “only B,” “only C,” or “any combination of A, B and C.” Additionally, “at least one of A, B or C” or “at least one of A, B and / or C” can mean “at least one of A, B and C.”

[0047]

[0048] FIG. 1 is a block diagram illustrating a system according to various embodiments of the present disclosure.

[0049] Hereinafter, devices that transmit and receive video / audio / control data will be collectively referred to as an AV (audio / video) system. Examples of AV systems include HDMI and DisplayPort.

[0050] Referring to FIG. 1, an AV system may include a source device (100) and a sink device (200). In particular, a device transmitting audio / video data in the AV system may correspond to the source device (100), and a device receiving video / audio data may correspond to the sink device (200). In this case, cables and connectors may be provided as physical devices that connect the two devices to support data transmission and reception.

[0051] Cables and connectors can pair four channels, each providing a Transition Minimized Differential Signaling (TMDS) data channel and a TMDS clock channel. The TMDS data channels can be used to carry video data, audio data, and auxiliary data.

[0052] Additionally, the AV system provides the Video Electronics Standards Association (VESA) Display Data Channel (DDC). DDC is used to exchange configuration and status information between source and sink devices. The CEC protocol can provide high-level control functions between various audiovisual products in the user environment and can also be used optionally. In addition, the optional HEAC (HDMI Ethernet and Audio Return Channel) can provide ARC (Audio Return Channel) and Ethernet-compatible data networking between connected devices in the opposite direction from TMDS.

[0053] Video data, audio data, and additional data can be transmitted / received over three TMDS data channels. The TMDS clock, which typically runs the video pixel rate, is transmitted over the TMDS clock channel. The TMDS clock can be used as a frequency reference for data recovery on the three TMDS data channels at the receiver. At the source device, 8 bits of data per TMDS data channel can be converted into a 10-bit DC-balanced, transition-minimized sequence that can be serially transmitted at a rate of 10 bits per TMDS clock period.

[0054] To transmit audio data and additional data over TMDS channels, AV systems use a packet structure. To achieve high reliability for audio and control data, data can be transmitted as 10-bit words generated using BCH error correction and error reduction coding.

[0055] A source device can read the Enhanced Extended Display Identification Data (E-EDID) of a Display Data Channel (DDC) sink device to determine the sink device's configuration information and capabilities. E-EDID may also be referred to as EDID information hereinafter.

[0056] The utility line can be used for optional extensions such as HEAC.

[0057] The source device (100) can receive EDID (Extended Display Identification Data) information from the sink device (200) via a DDC channel. The source device (100) can parse the received EDID information to recognize configuration information and supported functions of the sink device (200). The EDID information can include at least one block containing various information regarding the sink device (200).

[0058] In particular, EDID information according to one embodiment of the present invention may include information on the function and power supply capability of the sink device (200) in power transmission and reception. The source device (100) recognizes the power transmission / reception capability of the sink device (200) through this EDID information, and accordingly transmits power to the sink device (200) or receives power from the sink device (200).

[0059] The source device (100) includes at least one of a display unit (110), a user input interface unit (120), a control unit (180), a transmitter (Tx), a memory unit (140), a storage unit (150), a multimedia unit (160), a power control unit (130), and a power supply unit (170).

[0060] The sink device (200) includes at least one of an EDID EEPROM (210), a power control unit (220), a display unit (230), a user input interface unit (240), a receiver (Rx), a control unit (280), a power supply unit (250), a memory unit (260), and a multimedia unit (270). Hereinafter, descriptions of units performing the same operation will not be repeated.

[0061] The source device (100) represents a physical device that transmits or streams content stored in the storage unit (150) to the sink device (200). The source device (100) can send a request message to the sink device (200) or receive and process a request message received from the sink device (200). The source device (100) can provide a UI that processes and transmits a response message transmitted by the sink device (200) in response to the transmitted request message to the user, and when the source device (100) includes a display unit (110), this UI can be provided as a display. In addition, the source device (100) can request the sink device (200) to supply power.

[0062] The sink device (200) receives content from the source device (100) and can transmit a request message to the source device (100) or process a message received from the source device (100) and transmit a response message. The sink device (200) can also provide a UI (User Interface) that processes the response message received from the source device (100) and transmits it to the user. If the sink device (200) includes a display unit, this UI can be provided as a display. In addition, the sink device (200) can supply power requested by the source device (100) to the source device (100).

[0063] The user input interface unit (120, 240) can receive a user's action or input, and as an example, the user input interface (120, 240) can correspond to a remote controller, a voice receiving / recognition device, a touch input sensing / receiving device, etc.

[0064] The control unit (180, 280) can control the overall operation of each device. In particular, the control unit (180, 280) can perform communication between units included in each device and control the operation of each unit.

[0065] The memory unit (140, 260) represents a volatile physical device in which various types of data are temporarily stored.

[0066] The storage unit (150) represents a non-volatile physical device capable of storing various types of data.

[0067] EDID EEPROM (210) represents an EEPROM that stores EDID information.

[0068] The above-described memory unit (140, 260), storage unit (150), and EDID EEPROM (210) all serve to store data, and they may all be collectively referred to as memory units.

[0069] The display unit (110, 230) can display received data or content, data stored in the memory unit, UI, etc. under the control of the control unit (180, 280).

[0070] The multimedia unit (160, 270) can play various types of multimedia. The multimedia unit (160, 270) may be implemented separately from the control unit (180, 280), or may be implemented as a single physical configuration with the control unit (180, 280).

[0071] The power supply unit (170, 250) can supply power required for the operation of the source device (100), the sink device (200) and the units included therein.

[0072] A transmitter (Tx) is a unit equipped in a source device (100) that transmits and receives data, and performs data transmission and reception including not only audio / video data but also messages such as commands, requests, actions, and responses between devices.

[0073] The receiver (Rx) is a unit equipped in the sink device (200) that transmits and receives data, and performs data transmission and reception including not only audio / video data but also messages such as commands, requests, actions, and responses between devices.

[0074] The power control unit (130, 220) can manage and control power transmission and reception between devices via a transmitter and receiver.

[0075] Among the above-described units, units other than the transmitter (Rx), receiver (Tx), and control unit (180, 280) may be optionally included in the source device (100) or the sink device (200) depending on the embodiment, and may not be essential component units.

[0076] Previously, AV systems did not support power transfer between source and sink devices. As a result, when operating portable devices for extended periods, the inconvenience of always having to connect an external power cable for optimal operation existed. To address this issue, this specification proposes a method for ensuring optimal AV system operation without the need for external devices by enabling the wired interface to support power transfer.

[0077] For convenience of explanation, below, a device that supplies (or transmits) power will be referred to as a P-source device, and a device that supplies (or receives) power will be referred to as a P-sync device. Additionally, a device that simultaneously supports the functions of a P-source device and a P-sync device will be referred to as a dual device.

[0078]

[0079] Background to various embodiments of the present disclosure

[0080] Adaptive-Sync operation

[0081] Adaptive-Sync is a technology used in computer graphics that synchronizes graphics cards and monitors to eliminate screen flickering and tearing. Adaptive-Sync was standardized by the Video Electronics Standards Association (VESA) along with DisplayPort Adaptive-Sync and HDMI VRR (Variable Refresh Rate) technologies.

[0082] Adaptive-Sync technology includes a communication protocol for communication between the graphics card and the monitor, as well as time-splitting technology for synchronization between the two. Therefore, Adaptive-Sync technology encompasses the following technical areas:

[0083] - Graphics Card Technology: To support Adaptive-Sync, the graphics card must support Variable Refresh Rate (VRR) technology. AMD offers FreeSync, and NVIDIA offers G-Sync, each with their own VRR technology.

[0084] - Communication Protocol Technology: Display connection interfaces supporting Adaptive-Sync require DisplayPort 1.2a or higher and HDMI 2.1 or higher. Furthermore, to use Adaptive-Sync, the graphics card and monitor must use the same communication protocol.

[0085] Monitor Technology: A monitor that supports Adaptive-Sync must support the graphics card's VRR technology. Additionally, a monitor that supports Adaptive-Sync must support the protocol for communicating with the graphics card.

[0086] - Time-slicing technology: Adaptive-Sync uses time-slicing technology to synchronize the monitor and graphics card. To achieve this, both the graphics card and monitor must use the same time-slicing technology.

[0087] Adaptive-Sync technology encompasses a variety of technologies, including graphics cards, communication protocols, monitors, and time-slicing technology, all of which work together to make Adaptive-Sync possible.

[0088]

[0089] Source Device Operation during Live Frame Transmission

[0090] A Source device that has set both the Source Device Enables Panel Replay Mode in Sink Device bitin the PANEL REPLAY ENABLE register (DPCD 001B0h[0] = 1) and ALPM Enable bit in theRECEIVER_ALPM_CONFIGURATION register (DPCD 00116h[0] = 1) shall transmit the Adaptive-Sync SDP at the VBlank line that corresponds to either of the following:

[0091] (1) The VSync pulse's leading edge, -or-

[0092] (2) One line before the VSync pulse's leading edge, starting with the first video frame,as illustrated in Figure 2-155

[0093] When a Source device has not set both bits (DPCD 001B0h[0] = 0 and / or DPCD 00116h[0] = 0), the Source device may transmit at the line specified above -or- earlier during the VBlank period.

[0094]

[0095] 도 2는 본 개시의 다양한 실시 예들에 따른 Adaptive-Sync SDP 전송 타이밍의 일례를 도시한 도면이다.

[0096] As for whether to transmit the Adaptive-Sync SDP on the VSync pulse's leading edge or one line earlier, the following mandates apply for the Source device:

[0097] (1) When the Sink device's DPCD 02214h[1] = 0, the Source device shall keep DPCD 0011Bh[7] = 0 and transmit the Adaptive-Sync SDP in the first half line -or- the first 3,840 pixel cycles, whichever comes first, on the line that corresponds to the VSync pulse's leading edge

[0098] (2) When the Sink device's DPCD 02214h[1] = 1, the Source device may perform either of the following:

[0099] (3) Set DPCD 0011Bh[7] = 1 during video mode set, and then transmit the entire Adaptive-Sync SDP one line earlier, at any time during the line, -or-

[0100] (4) Clear DPCD 0011Bh[7] = 0 during video mode set, and then transmit the Adaptive-Sync

[0101] SDP in the first half line -or- the first 1,920 pixel cycles, whichever comes first, on the line that corresponds to the VSync pulse's leading edge

[0102]

[0103] Adaptive-Sync operation AUX Flow chart

[0104] FIG. 3 is a diagram illustrating an example of an AUX flowchart related to Adaptive-Sync operation according to various embodiments of the present disclosure.

[0105] Referring to FIG. 3, the Source device receives a hot plug detection (HPD) signal from the Sink device.

[0106] The Source device reads the EDID / DisplayID of the Sink device (EDID / DisplayID Read). That is, the Source device receives the EDID / DisplayID of the Sink device from the Sink device.

[0107] The source device reads the DisplayPort Configuration Data (DPCD) of the sink device. DPCD corresponds to 00000h to 000FFh and 02200h to 022FFh. The source device can determine whether the sink device supports Adaptive-Sync through DPCD.

[0108] The Source device writes 00107h = 1 to DPCD and transmits the DPCD to the Sink device. By writing 00107 = 1 to DPCD, the Source device enables the Adaptive-Sync feature. The Sink device ignores the MSA Timing parameter value.

[0109] Assuming Adaptive-Sync is enabled, the Source device transmits video stream data and Adaptive-Sync SDP to the Sink device. The Adaptive-Sync SDP and Vsync Pulse are synchronized.

[0110]

[0111] DPCD related to Adaptive-Sync operation

[0112] DPCD (DisplayPort Configuration Data Channel) is part of the DisplayPort connection interface and is a data channel for communication between a display device and a graphics card. DPCD is used by the graphics card to recognize the display device, configure its features, and share the DP connection status with the monitor. The following configurations are related to Adaptive-Sync DPCD operation.

[0113] (1) Source device adaptive synchronization operation requirements

[0114] This section defines the source device rules for the following Adaptive-Sync policies:

[0115] (1-1) Before and during setting the video mode

[0116] (1-2) Transmitting live frames

[0117] Before working on setting the video mode, the source device must check the following:

[0118] (1-3) The Stream Sink of the connected Sink device meets the following VESA AdaptiveSync requirements:

[0119] (1-3-1) DisplayID Adaptive-Sync data block support

[0120] (1-3-2) Supports detailed timing with CVT v2.0 RB v3 timing or 350ppm offset exposed in DisplayID.

[0121] (1-4) The DPRX of the connected sink device complies with the VESA AdaptiveSync specification.

[0122] (1-4-1) DPCD 00007h[6] = 1 and DPCD 02207h[6] = 1

[0123] (1-4-2) DPCD 02214h[0] = 1

[0124] (1) Source Device Adaptive-Sync Operation Mandates

[0125] This section defines Source device mandates for the following Adaptive-Sync policies:

[0126] (1-1) Before and during video mode set

[0127] (1-2) During live frame transmission

[0128] Before video mode set operation, a Source device shall verify the following:

[0129] (1-3) Stream Sink in the connected Sink device meets the following VESA AdaptiveSync mandates:

[0130] (1-3-1) Supports the DisplayID Adaptive-Sync data block

[0131] (1-3-2) Supports the CVT v2.0 RB v3 timing -or- detailed timing with 350-ppm offset exposed in the DisplayID

[0132] (1-4) DPRX in the connected Sink device meets the VESA AdaptiveSync mandates:

[0133] (1-4-1) DPCD 00007h[6] = 1 and DPCD 02207h[6] = 1

[0134] (1-4-2) DPCD 02214h[0] = 1

[0135]

[0136] (2) Requirements for adaptive synchronization operation of sink devices

[0137] This section defines the sink device rules for the following Adaptive-Sync policies:

[0138] (2-1) Before and during video mode setting

[0139] (2-2) Transmitting live frames

[0140] VESA AdaptiveSync sync devices must meet the following:

[0141] (2-3) DisplayID Adaptive-Sync data block support

[0142] (2-4) CVT v2.0 RB v3 timing support or detailed timing support with 350ppm offset exposed in DisplayID

[0143] (2-5) Adaptive-Sync SDP v2 support (HB2[4:0] = 02h)

[0144] (2-6) Set the following Adaptive-Sync DPCD function register bits to their default values.

[0145] (2-6-1) DPCD 00007h[6] = 1 and DPCD 02207h[6] = 1

[0146] (2-6-2) DPCD 02214h[0] = 1

[0147] (2-7) Set DPCD 02214h[1] = 1 as needed

[0148] (2-8) Arm for Adaptive-Sync operation when the source device writes DPCD 00107h[7] = 1 while video mode is set.

[0149] (2-9) Since the sink device may be connected to a legacy source device that sets DPCD 00107h[7] = 1 and starts receiving the video stream after the video mode setting operation, it must check for the presence of an Adaptive-Sync SDP, but it does not transmit an Adaptive-Sync SDP. As long as all of the following conditions are met, the VESA AdaptiveSync Sink device must parse the Adaptive-Sync SDP payload data bytes and display the image within the latency constraints while meeting the Adaptive-Sync display CTS visual performance requirements (e.g., flicker performance greater than -50 dB, panel overdrive compensation, and responsive gray-to-gray transitions that do not cause ghosting):

[0150] (2-10) The source device follows the frame period increase and decrease limits of the sink device listed in the Adaptive-Sync data block (bytes 1 and 5, respectively).

[0151] (2-11) The Adaptive-Sync SDP payload content is true. VESA AdaptiveSync sink devices must also meet the minimum visual performance requirements (e.g., -45 dB flicker performance) as long as the source device adheres to the min-max refresh range. This also applies if the Adaptive-Sync SDP payload content is false for one frame during the Adaptive-Sync operating mode transition.

[0152] (2) Sink Device Adaptive-Sync Operation Mandates

[0153] This section defines Sink device mandates for the following Adaptive-Sync policies:

[0154] (2-1) Before and during video mode set

[0155] (2-2) During live frame transmission

[0156] A VESA AdaptiveSync Sink device shall:

[0157] (2-3) Support the DisplayID Adaptive-Sync data block

[0158] (2-4) Support the CVT v2.0 RB v3 timing -or- detailed timing with 350-ppm offset exposed in the DisplayID

[0159] (2-5) Support Adaptive-Sync SDP v2 (HB2[4:0] = 02h)

[0160] (2-6) Set the following Adaptive-Sync DPCD capability register bits as default:

[0161] (2-6-1) DPCD 00007h[6] = 1 and DPCD 02207h[6] = 1

[0162] (2-6-2) DPCD 02214h[0] = 1

[0163] (2-7) Set DPCD 02214h[1] = 1, as needed

[0164] (2-8) Arm for Adaptive-Sync operation when a Source device writes DPCD 00107h[7] = 1 during video mode set

[0165] (2-9) Sink device shall check for the presence of an Adaptive-Sync SDP as the Sink device starts receiving a video stream after video mode set operation because the Sink device may be connected to a legacy Source device that sets DPCD 00107h[7] = 1 but does not transmit an Adaptive-Sync SDP A VESA AdaptiveSync Sink device shall parse Adaptive-Sync SDP payload data bytes and display an image within a latency limit while meeting Adaptive-Sync Display CTS visual performance mandates (e.g., flicker performance of -50 dB or better, a responsive gray-to-gray transition without causing panel overdrive compensation ghosting), as long as both of the following conditions are met:

[0166] (2-10) Source device honors the Sink device's Frame Duration Increase and Decrease Limits that are enumerated in the Adaptive-Sync data block (Bytes 1 and 5, respectively)

[0167] (2-11) Adaptive-Sync SDP payload content is true

[0168] The VESA AdaptiveSync Sink device shall also meet the minimum visual performance mandates (e.g., a flicker performance of -45 dB) as long as the Source device honors the minimum-to-maximum refresh range even when the Adaptive-Sync SDP payload content is false for one frame during an Adaptive-Sync operation mode transition.

[0169]

[0170] (3) Adaptive-Sync에 사용되는 DPCD 레지스터

[0171] (3) DPCD Registers used for Adaptive-Sync

[0172] 다음의 표 1은 Table 2-220: DPCD Registers Used for Adaptive-Sync를 나타낸다.

[0173] TypeDPCD Register AddressNameCapability0007h[6]DOWN_STREAM_PORT_COUNT register,MSA_TIMING_PAR_IGNORED bitExtended Capability02207h[6]DOWN_STREAM_PORT_COUNT register,MSA_TIMING_PAR_IGNORED bit02215h[2,1,0]DPRX_FREATURE_ENUMERATION_LIST_CONT_1 register,FAVT_PAYLOAD_FIELDS_PARSING_SUPPORTED,AS_SDP_FIRST_HALF_LINE_OR_3840_PIXEL_CYCLE_WINDOW_NOT_SUPPORTED, andADAPTIVE_SYNC_SDP_SUPPORTED bits, respectively02218h[6]DPRX_FEATURE_ENUMERATION_LIST_CONT_2 register,ADAPTIVE SYNC SDP T2 SUPPORTED IN ALL PR ACTIVE STATES bitConfiguration00107h[7,6]DOWNSPREAD_CTRL register, MSA_TIMING_PAR_IGNORE_EN andFIXED_VTOTAL_AS_SDP_EN_IN_PR_ACTIVE bits0011Ah[7:6]PANEL REPLAY CONFIGURATION 3 register,AS_SDP_SETUP_CONFIG_PR_ACTIVE field0011Bh[7]ADAPTIVE_SYNC_SDP_TRANSMISSION_TIMING_CONFIG register,AS_SDP_ONE_LINE_EARLIER_ENABLE bit

[0174] Adaptive-Sync 동작 관련 EDID

[0175] 도 4은 본 개시의 다양한 실시 예들에 따른 EDID block, CTA block 및 DisplayID block이 혼합된 EDID의 구조의 일례를 도시한 도면이다.

[0176] EDID (Extended Display Identification Data) is a data structure used by the display adapter (graphics card) to read information built into the monitor. When the monitor provides EDID information, the graphics card can automatically recognize and set the monitor's basic settings, such as the optimal resolution and refresh rate. The structure of EDID can be a mixture of EDID block, CTA block, and DisplayID block, and can be configured as an example as in Figure 4. In addition, since the Adaptive-Sync operation parameters are different for each block, the Sink may display two or more Adaptive-Sync operation parameters for compatibility with legacy sources.

[0177] EDID is transmitted via the Data Display Channel (DDC). The DDC uses the I²C interface to enable communication between the graphics card and the monitor. The graphics card requests EDID information from the monitor via the DDC, and the monitor responds.

[0178] Adaptive-Sync operation parameters for each block can be expressed in a total of three types of blocks as described below.

[0179]

[0180] 1. Display Range Limit Block in EDID1.4

[0181] FIG. 5 is a diagram illustrating an example of the structure of a Display Range Limit Block in EDID1.4 according to various embodiments of the present disclosure.

[0182] Table 2 below shows Table 3.26: Display Range Limits & Timing Descriptor Block Definition.

[0183] Byte #ValueDisplay Range Limits Definitions0,1(0000h)Indicates that this 18 byte descriptor is a Display Descriptor200hReserved: Set to 00h when 18 byte descriptor is used as a Display Descriptor3FDhTag Number for Display Range Limits Descriptor476543210Display Range Limits Offsets: FLAGs0000__00Vertical Rate Offsets are zero0000__10Max. Vertical Rate + 255 Hz Offset; Min. Vertical Rate is not offset0000__11Max. Vertical Rate + 255 Hz Offset; Min. Vertical Rate + 255 Hz Offset000000Horizontal Rate Offsets are zero000010__Max. Vertical Rate + 255 kHz Offset; Min. Vertical Rate is not offset000011__Max. Vertical Rate + 255 kHz Offset; Min. Vertical Rate + 255 kHz Offset01h,04h→07h,09h,0Dh10h→FFhReserved: Do not use501h→FFhMinimum Vertical Rate: (for interlace this refers to the field rate)[Byte 4,Bits 1,0]≠11Binary coded rate in Hz, integer only (range is 1 Hz to 255 Hz)[Byte 4,Bits 1,0]=11Binary coded rate in Hz,integer only (range is 256 Hz to 510 Hz)00hReserved: Do not use601h→FFhMaximum Vertical Rate: (for interlace this refers to the field rate)[Byte 4,Bits 1]≠1Binary coded rate in Hz, integer only (range is 1 Hz to 255 Hz)[Byte 4,Bits 1]=1Binary coded rate in Hz, integer only (range is 256 Hz to 510 Hz)Note: Minimum rate value shall be less than or equal to maximum rate value00hReserved: Do not use701h→FFhMinimum Horizontal Rate:[Byte 4,Bits 3,2]≠11Binary coded rate in kHz, integer only (range is 1 kHz to 255 kHz)[Byte 4,Bits 3,2]=11Binary coded rate in kHz, integer only (range is 256 kHz to 510 kHz)00hReserved: Do not use801h→FFhMaximum Horizontal Rate:[Byte 4,Bit 3]≠1Binary coded rate in kHz, integer only (range is 1 kHz to 255 kHz)[Byte 4,Bit 3]=1Binary coded rate in kHz, integer only (range is 256 kHz to 510 kHz)Note: Maximum rate value shall be less than or equal to maximum rate value00hReserved: Do not use901h→FFhMaximum Pixel Clock:Binary coded rate in MHz / 10,Example: 130MHz is '0Dh'Note: Maximum Pixel Clock shall be rounded to the nearest multiple of 10 MHzReserved: Do not use10Video Timing Support Flags: Bytes 10→17 indicate support for additional video timings00hDefault GTF supported if bit 0 in Feature Support Byte at address 18h=101hRange Limits Only --- no additional timing information is provided02hSecondary GTF supported --- requires support for Default GTF04hCVT supported if bit 0 in Feature Support Byte at address 18h=103h,05h→FFhReserved for future timing definitions --- Do not use110AhLine Feed (if Byte 10 = 00h or 01h)00h→FFhVideo Timing Data (if Byte 10 = 02h or 04h) --- Refer to Tables 3.27 → 3.2812→1720hSpace (if Byte 10 = 00h or 01h)00h→FFhVideo Timing Data (if Byte 10 = 02h or 04h) ---Refer to Tables 3.27 → 3.28,

[0184] 2. DisplayID 1.3에서의 Video Timing Range Limits Data Block

[0185] 도 6은 본 개시의 다양한 실시 예들에 따른 DisplayID 1.3에서의 Video Timing Range Limits Data Block의 구조의 일례를 도시한 도면이다.

[0186] OffsetValueDescription / Format00 h 09 h VIDEO TIMING RANGE LIMITS DATA BLOCKTAG01 h 76543210BLOCK Revision and other Data_____000REVISION '0'VALUE 0→700000___RESERVED BITS

[0187] 02 h 0F h Number of Payload Bytes in BLOCKAll Other Values RESERVED1505 h 04 h 03 h 00 h 00 h 00 h → FF FF FF h Minimum pixel clock / 10,0000.01→167,772.16 MHz08 h 07 h 06 h 00 h 00 h 00 h → FF FF FF h Maximum pixel clock / 10,0000.01→167,772.16 MHz09 h 00 h → FF h Minimum horizontal frequency0→255 kHz0A h 00 h → FF h Maximum horizontal frequency0→255 kHz0C h 0B h 00 00 h → FF FF h Minimum horizontal blanking0→65,535 Pixels0Dh 00 h → FF h Minimum vertical refresh (field / frame) rate0→255 Hz0E h 00 h → FF h Maximum vertical refresh (field / frame) rate0→255 Hz10 h 0F h 00 00 h → FF FF h Minimum vertical blanking0→65,535 Lines11 h 76543210Video Timing Support over this rangeFlag1_______Supports interlaced operation_1______VESA CVT, standard-blanking timings__1_____VESA CVT, reduced-blanking timings___1_Discrete frequency display device____0000RESERVED

[0188] 3. Adaptive-Sync Data Block in DisplayID 2.0

[0189] FIG. 7 is a diagram illustrating an example of the structure of an Adaptive-Sync Data Block in DisplayID 2.0 according to various embodiments of the present disclosure.

[0190] Table 5 below shows Table 4.51: Adaptive-Sync Data Block.

[0191] In Table 5, N represents the number of detailed timing descriptors in the data block. M represents the value of offset 01h[6:4]. The source device implementation should accommodate varying fields for future extensibility. (N represents the number of detailed timing descriptors in the data block. M represents the value of offset 01h[6:4]. The source device implementation should accommodate varying fields for future extensibility.)

[0192] OffsetBit #Definition / Priority00h7:0Adaptive-Sync Data Block2Bh01hBlock Revision and Other Data2:0Block RevisionRevision ranges from 0 through 7000b=Revision 0All other values are RESERVED3RESERVEDCleared to 06:4Number of Payload Bytes (M) in an Adaptive-Sync Operation ModeAnd Range DescriptorWhere M (bytes) = 6 (initial descriptor size) + field value000b = 6 + 0 bytes / descriptor (defined as part of Adaptive0Sync, Revision 0)All other values are RESERVED7RESERVEDCleared to 002h7:0Number of Payload Bytes in BlockNumber of payload bytes within the block is based on the number of descriptors (N) * size of each descriptor (M) bytesAll other values are RESERVED03h through03h+M-1(M*8-1):0First Adaptive-Sync Operation Mode and Range DescriptorM-byte descriptor03h+M through 03h + 2M - 1(M*8-1):0Second Adaptive-Sync Operation Mode and Range DescriptorM-byte descriptor, if present......03h +(N-1) * M through03h+ (N*M) - 1(M*8-1):0Nth Adaptive-Sync Operation Mode and Range DescriptorM-byte descriptor, if present.

[0193] 다음의 표 6은 Table 4.52: Adaptive-Sync Operation Mode and Range Descriptor를 나타낸다.

[0194] Byte #Bit #Definition0Adaptive-Sync Operation and Range Information0Adaptive-Sync Range0 = Non-native panel range. (The display implements buffering to support the declared Adaptive-Sync range, and may repeat frames as necessary.)1 = Native panel range. (The display does not implement buffering to support the declared Adaptive-Sync range, and does not repeat frames.)1Successive Frame Duration Increase Tolerance for Meeting VESA Adaptive Sync Flicker Performance0 = Flicker performance is met in any duration increase within the refresh rate range, but may cause up to a single base video frame period jitter impact.1 = Flicker performance is met in any duration increase within Byte 1.Note: Flicker performance is met in any duration increase within the refresh rate range without jitter impact when either of the following conditions are met:(1) Byte 1 = 00h,-or-(2) Byte 1 >= the delta between the maximum frame duration ( = minimum refresh rate) and the minimum frame duration (= maximum refresh rate)3:2Supported Adaptive-Sync Modes00b = Fixed-Average VTotal (FAVT) mode is supported01b = Both Fixed-Average VTotal and Adaptive VTotal modes (FAVT and AVT, respectively) are supportedAll other values are RESERVED4Seamless Transition of Adaptive-Sync Mode and Range Not Supportd0 = Seamless transition to and from current Adaptive-Sync mode and range is supported1 = Seamless transition to and from current Adaptive-Sync mode and range is not supported5Successive Frame Duration Decrease Tolerance for Meeting VESA Adaptive Sync Flicker Performance0 = Flicker performance is met in any duration decrease within the refresh rate range,but may cause up to a single base video frame period jitter impact1 = Flicker performance is met in any duration decrease within Byte 5Note: Flicker performance is met in any duration decrease within the refresh rate range without jitter impact when either of the following conditions are met:(1) Byte 5 = 00h, -or-(2) Byte 5 >= the delta between the maximum frame duration(= minimum refresh rate) and the minimum frame duration (= maximum refresh rate)7:6RESERVEDCleared to all 0s17:0Maximum Single Frame Duration Increase Allowed for Meeting VESA Adaptive Sync Flicker Performance6.2 format (six integer bits and two fractional bits) that results in a value range of 0.00 to 63.75 ms, inclusive00h = Flicker performance is met in any duration increase within the refresh rate range without jitter impact27:0Minimum Refresh RateMinimum refresh rate ranges from 0 through 255 Hz,divided by 1.00100h = 0 Hz01h = (1 / 1.001) Hz...FFh = (255 / 1.001) Hz4:3Maximum Refresh RateMaximum refresh rate ranges from 1 through 1,024 Hz, plus 350 ppm. Note that the value stored in this field shall match that of at least one CVT v2.0 RB Timing v3 timing supported by the Sink device000h = (1*1.00035) Hz...3FFh = (1,024 * 1.00035) Hz37:0Maximum Refresh Rate 7:041:0Maximum Refresh Rate 9:87:2RESERVEDCleared to all 0s57:0Maximum Single Frame Duration Decrease Allowed for Meeting VESA Adaptive Sync Flicker Performance6.2 format (six integer bits and two fractional bits) that results in a value range of 0.00 to 63.75 ms, inclusive00h = Flicker performance is met in any duration decrease within the refresh rate range without jitter impact,

[0195] Adaptive-Sync SDP

[0196] The Adaptive-Sync Second data packet is used for communication between the graphics card and the display. The graphics card sends the Adaptive-Sync Second data packet to the display, which then informs the graphics card of its supported refresh rate range and VRR mode. Based on this information, the graphics card synchronizes with the display, preventing screen tearing and stutter, and enabling smoother display. The information and size of the Adaptive-Sync SDP may vary depending on the Adaptive-Sync operation parameters for each EDID block.

[0197] The Adaptive-Sync SDP operation and the information on Header and Payload Data Bytes are as follows.

[0198] In addition to setting the MSA_TIMING_PAR_IGNORED bit in the DOWN_STREAM_PORT_COUNT register (DPCD), an Adaptive-Sync capable DP protocol converter indicates Adaptive-Sync SDP support by setting the ADAPTIVE_SYNC_SDP_SUPPORTED bit in the DPRX_FEATURE_ENUMERATION_LIST_CONT_1 register (DPCD 02214h[0] = 1, 00007h[6] = 1 and DPCD 02207h[6] = 1). An Adaptive-Sync capable DP protocol converter must support SDP splitting in SST and MST modes and indicate the splitting capability by setting the SST_SPLIT_SDP_CAP bit in the DPRX_FEATURE_ENUMERATION_LIST register (DPCD 02210h[1] = 1). An Adaptive-Sync-capable DP source device can enable Adaptive-Sync video transmission to a connected DP protocol converter only after verifying the following:

[0199] (1) The connected DP protocol converter has DPCD 00007h[6] = 1 and DPCD 02214h[0] = 1.

[0200] (2) A stream sink connected to a DP protocol converter indicates support for the Adaptive-Sync refresh rate range in its DisplayID or legacy EDID. As always for Adaptive-Sync video transmission, an Adaptive-Sync capable DP source device must use an AUX write transaction to set the MSA_TIMING_PAR_IGNORE_EN bit in the DOWNSPREAD_CTRL register (DPCD 00107h[7] = 1) before enabling Adaptive-Sync video transmission. If the connected DP device has DPCD 02214h[0] = 1, the DP source device must transmit an Adaptive-Sync SDP before enabling Adaptive-Sync video transmission.

[0201] When transmitting Adaptive-Sync SDP, the DP source device must:

[0202] (3) Transmit Adaptive-Sync SDP in every video frame. For multi-field video modes such as interlaced and 3D, Adaptive-Sync SDP must be transmitted in every video field.

[0203] (4) Ensure that the start and end of the Adaptive-Sync SDP transmission occur within the first half of the line corresponding to the start of the VSync pulse (indicated by the BS symbol sequence).

[0204] (5) Send valid HTotal[15:0], HStart[15:0], HSyncPolarity[0](HSP), HSyncWidth[14:0].

[0205] (HSW), VStart[15:0], VSyncPolarity[0](VSP) 및 VSyncWidth[14:0](VSW)는 Adaptive-Sync SDP를 전송하는 동안 유효한 HWidth[15:0] 및 VHeight[15:0]. 즉, Adaptive-Sync 가능 DP 프로토콜 변환기는 Adaptive-Sync SDP를 수신하는 동안 VTotal[15:0]만 무시해야 한다.

[0206] An Adaptive-Sync-capable DP protocol converter shall indicate Adaptive-Sync SDP support by setting the ADAPTIVE_SYNC_SDP_SUPPORTED bit in the DPRX_FEATURE_ENUMERATION_LIST_CONT_1 register (DPCD 02214h[0] = 1) in addition to setting the MSA_TIMING_PAR_IGNORED bit in the DOWN_STREAM_PORT_COUNT register(s) (DPCD 00007h[6] = 1 and DPCD 02207h[6] = 1). An Adaptive-Sync-capable DP protocol converter shall support SDP splitting in SST and MST modes, and indicates its splitting capability by setting the SST_SPLIT_SDP_CAP bit in the DPRX_FEATURE_ENUMERATION_LIST register (DPCD 02210h[1] = 1). An Adaptive-Sync-capable DP Source device may enable an Adaptive-Sync video transmission to a plugged DP protocol converter only after verifying the following:

[0207] (1) Plugged DP protocol converter has DPCD 00007h[6] = 1 and DPCD 02214h[0] = 1

[0208] (2) Stream sink plugged to the DP protocol converter indicates support for the Adaptive-Sync

[0209] refresh rate range in the DisplayID or legacy EDID As is always the case with Adaptive-Sync video transmission, an Adaptive-Sync-capable DP Source device shall use an AUX write transaction to write 1 to the MSA_TIMING_PAR_IGNORE_EN bit in the DOWNSPREAD_CTRL register (DPCD 00107h[7] = 1) prior to enabling an Adaptive-Sync video transmission. When the plugged DP device has DPCD 02214h[0] = 1, a DP Source device shall transmit an Adaptive-Sync SDP before enabling an Adaptive-Sync video transmission.

[0210] When transmitting an Adaptive-Sync SDP, a DP Source device shall do the following:

[0211] (3) Transmit an Adaptive-Sync SDP on every video frame. For multi-field video modes such as Interlaced and 3D, the Adaptive-Sync SDP shall be transmitted on every video field.

[0212] (4) Ensure that the start and end of the Adaptive-Sync SDP transmission occur within the 1st half of the line (marked by BS symbol sequences) that corresponds to the start of the VSync pulse.

[0213] (5) Transmit valid HTotal[15:0], HStart[15:0], HSyncPolarity[0] (HSP), HSyncWidth[14:0]

[0214] (HSW), VStart[15:0], VSyncPolarity[0] (VSP), and VSyncWidth[14:0] (VSW) while transmitting an Adaptive-Sync SDP, as well as valid HWidth[15:0] and VHeight[15:0]. That is, an Adaptive-Sync-capable DP protocol converter shall ignore only VTotal[15:0] while receiving an Adaptive-Sync SDP.

[0215]

[0216] 표 7은 Table 2-126: Adaptive-Sync SDP Header Bytes를 나타낸다.

[0217] Byte #Bit #ContentHB07:0Secondary-data Packet IDSpecific to stream (usually 00h)HB17:0Secondary-data Packet Type22h = Adaptive-SyncHB24:0Version Number01h = Version 1. No payload data bytes (same as DP v2.0, as released in June 2019).02h = Version 2. VESA AdaptiveSync shall support both the DisplayID Adaptive-Sync data block and Adaptive-Sync SDP data structure version 2.All other values are RESERVED for future versions.7:5RESERVEDRead all 0sHB35:0Number of Valid Data BytesVersion 100h = No payload data bytes.Version 209h = Nine payload data bytes.The Adaptive-Sync SDP has 32 payload data bytes. Unused data bytes shall be zero-padded.7:6RESERVEDRead all 0s.

[0218] 표 8은 Table 2-127: Adaptive-Sync SDP Version 2 Payload Data Bytes를 나타낸다.

[0219] Byte #Bit #ContentDB0Timing Options01VARIABLE_FRAME_RATE_DISABLEAdaptive Sync Operation ModeWhen a Source device sets the MSA_TIMING_PAR_IGNORE_EN and FIXED_VTOTAL_AS_SDP_EN_IN_PR_ACTIVE bits in the DOWNSPREAD_CTRL register (DPCD 00107h [7,6] = 11b, respectively):00b = AVT mode, and video frame duration is bound to change from frame-to-frame.01b = AVT mode; however, video frame duration is currently fixed.10b = FAVT mode, and TRR is yet to be reached.11b = FAVT mode, and TRR is reached.When a Source device programs DPCD 00107h[7,6] = 01b (see Section 2.18 for details):01b = Adaptive-Sync operation is disabled and the VTotal line count is fixed.00b, 10b, and 11b = RESERVED.2Adaptive Sync SDP Transmission Disable in PR Active StateCleared to 0 when the Sink device does not support PR.0 = Source-to-Sink device timing sync using the Adaptive-Sync SDP is enabled.1 = Source-to-Sink device timing sync using the Adaptive-Sync SDP is disabled.3Remote Frame Buffer (RFB) Update in PR Active StateValid only during a PR Active state. Shall be driven to 0 in PR_State 0_0 (Disabled) -or-PR_State 0_1 (Inactive). Cleared to 0 when the Sink device does not support PR.0 = No RFB update in the current active video image time interval.1 = Update the RFB - Capture the incoming video frame / Sus to the RFB.7:4RESERVEDRead all 0s.DB17:0Minimum Vertical Total7:0Minimum Vertical Total15:8Source device shall program DB2:DB1 to the VTotal value that corresponds to the enabled base timing. The value is statically programmed and is valid in both FAVT mode and AVT mode.DB27:0DB37:0Target Refresh Rate7:0Target Refresh Rate9:8AVT modeSource device shall clear DB4[1:0] = 00b and DB3 = 00h.FAVT modeSource device shall program DB4[1:0] and DB3 and DV4[5] to match the average video frame rate.DB41:04:2RESERVEDRead all 0s.5Target Refresh Rate DividerValid only in FAVT mode. Sink device ignores the bit in AVT mode.0 = 1.000.1 = 1.001.6Successive Frame Duration Increase ConfigurationIf the Source device engages in a bounded transition for low-flicker performance by using information in the DisplayID Adaptive-Sync data block and setting this bit to 1, the Source device shall:(1) Use the CVT v2.0 RB Timing v3 -or- detailed timing descriptor with 350-ppm offset exposed in the DisplayID, and(2) Constrain the duration increase to the value reported in the DisplayID Adaptive-Sync data block for a guarantee of low-flicker performance0 = Video frame duration increase transitions are unbounded.1 = Video frame duration increase transitions are bounded by the time specified in DB5.7Successive Frame Duration Decrease ConfigurationIf the Source device engages in a bounded transition for low-flicker performance by using the information in the DisplayID Adaptive-Sync data block and setting this bit to 1, the Source device shall:(1) Use the CVT v2.0 RB Timing v3 -or- detailed timing descriptor with 350-ppm offset exposed in the DisplayID, and(2) Constrain the duration decrease to the value reported in the DisplayID Adaptive-Sync data block for a guarantee of low-flicker performance0 = Video frame duration decrease transitions are unbounded.1 = Video frame duration decrease transitions are bounded by the time specified in DB6.DB57:0Duration Increase Constraint Value in ms Unit6.2 format (six integer bits and two fractional bits) that results in a value range of 0.00 to 63.75 ms, inclusive.When the Source device clears DB4[6] = 0, the Source device shall clear DB5 = 00h.When the Source device sets DV4[6] = 1, the Source device shall program DB5 to the value that the Source device is using for the maximum duration increase. The value does not indicate the instantaneous video frame-to-frame duration delta.A 0.00 value indicates that the Source device may invoke a maximum-to-minimum refresh rate transition across a single video frame boundary.To attain optimum flicker performance without jitter impact, the Source device shall keep the DB5 value less than or equal to the limit value reported by the Sink device in the Max Single Frame Duration Increase Allowed for Attaining the Low Flicker Performance byte (Byte 1) of the DisplayID Adaptive-Sync data block's Operation Mode and Range descriptor.DB67:0Duration Decrease Constraint Value in ms Unit6.2 format (six integer bits and two fractional bits) that results in a value range of 0.00 to 63.75 ms, inclusive.When the Source device clears DB4[7] = 0, the Source device shall clear DB6 = 00h.When the Source device sets DB4[7] = 1, the Source device shall program DB6 to the value that the Source device is using for the maximum duration decrease. The value does not indicate the instantaneous video frame-to-frame duration delta.A 0.00 value indicates that the Source device may invoke a maximum-to-minimum refresh rate transition across a single video frame boundary.To attain optimum flicker performance without jitter impact, the Source device shall keep the DB6 value less than or equal to the limit value reported by the Sink device in the Max Single Frame Duration Decrease Allowed for Attaining the Low Flicker Performance byte (Byte 5) of the DisplayID Adaptive-Sync data block's Operation Mode and Range descriptor.DB77:0Coasting VTotal7:0 in PR Active StateShall be programmed to the Coasting Vtotal LSB value that the Sink device shall use to maintain the refresh rate when the DPTX has suspended transmission of the Adaptive-Sync SDP in a PR Active state.DB7 = 00h when the Sink device does not support PR.DB87:0Coasting VTotall15:8 in PR Active StateShall be programmed to the Coasting VTotal MSB value that the Sink device shall use to maintain the refresh rate when the DPTX has suspended transmission of the Adpative-Sync SDP in a PR Active state.DB8 = 00h when the Sink device does not support PR.DB9throughDB31191:0RESERVEDRead all 0s.

[0220] The technical task that the invention seeks to achieve

[0221] For Adaptive-Sync operation, the Sink can indicate the frame range in three blocks: Base EDID1.4 - Range Limit Block, DisplayID1.x - Video Timing Range Limits Data Block, and DisplayID2.x - Adaptive-Sync Data Block. This may make it difficult for the Source to perform accurate Adaptive-Sync operation if the frame ranges of the three blocks are different. In addition, the maximum frame rate and whether multiple frame ranges can be indicated differ for each block, as shown below.

[0222] EDID1.4 Display Range Limit Block: Only one frame range can be displayed, and only up to 510 Hz can be displayed.

[0223] DisplayID1.x Video Timing Range Limits Data Block: Only one frame range can be displayed, up to a maximum of 255 Hz.

[0224] DisplayID2.x Adaptive-Sync Data Block: Can display multiple frame ranges and up to 1024 Hz.

[0225] Therefore, when the Frame Range is expressed differently for each Block, a method needs to be introduced for the Source to read the Frame range information of the Sink and use it consistently for normal Adaptive-Sync operation.

[0226]

[0227] Composition and operation of the invention

[0228] The Source operates by referencing the Frame range based on the criteria described in the Case below, with reference to the four conditions below.

[0229] (1) Whether or not DisplayID exists in Sink's EDID

[0230] (2) Sink's DisplayID Version

[0231] (3) When the Max Frame range of the Adaptive-Sync Data Block is > 510Hz

[0232] (4) DP2.x Sink's Base EDID 1.4 - Range Limit Block, DisplayID 1.x - Video Timing Range Limits Data Block, and DisplayID 2.x - Adaptive-Sync Data Block's Frame range

[0233] [reference]

[0234] F min : Minimum Frame Rate for Adapitve-Sync Operation

[0235] F max : Adapitve-Sync Driven Maximum Frame Rate

[0236]

[0237] Case 1) Presence or absence of Sink's DisplayID

[0238] - If the DisplayID does not exist in the Sink's EDID

[0239] → Source operates as the Range Limit of the EDID Base Block or the Frame range in the Video Timing Range Limits Data Block of DisplayID1.x.

[0240]

[0241] Case 2) Sink’s DisplayID Version

[0242] - If there is a block with Sink's DisplayID Version >= 2.0

[0243] → Source operates as the Frame range of the DisplayID2.x Adaptive-Sync Data Block.

[0244]

[0245] Case 3) DisplayID 2.x - When the Frame range of the Adaptive-Sync Data Block is Fmax > 510Hz

[0246] → Source operates as the Frame range of the DisplayID2.x Adaptive-Sync Data Block.

[0247]

[0248] Case 4) If DP2.x Sink's Base EDID 1.4 - Range Limit Block, DisplayID 1.x - Video Timing Range Limits Data Block, and DisplayID 2.x - Adaptive-Sync Data Block have frame ranges, it operates with the Data Block with the highest Max Frame Rate (Fmax).

[0249]

[0250] FIG. 8 is a diagram illustrating an example of a case where Range Limit Block & Video Timing Range (175 Hz) > Adaptive Sync Data Block (144 Hz) according to various embodiments of the present disclosure.

[0251] According to the embodiment of FIG. 8, when Range Limit Block & Video Timing Range (175 Hz) > Adaptive Sync Data Block (144 Hz), the source device operates based on the Range Limit Block & Video Timing Range when performing Adaptive-Sync.

[0252]

[0253] FIG. 9 is a diagram illustrating an example of a case where Range Limit Block & Video Timing Range (175 Hz) < Adaptive Sync Data Block (500 Hz) according to various embodiments of the present disclosure.

[0254] According to the embodiment of FIG. 9, when Range Limit Block & Video Timing Range (175 Hz) < Adaptive Sync Data Block (500 Hz), the source device operates based on the Adaptive Sync Data Block Range when performing Adaptive-Sync.

[0255]

[0256] Figure 10 is a diagram illustrating an example of a process for determining a Frame Range during conventional Adaptive-Sync operation.

[0257] Specifically, Fig. 10 illustrates an example of the operation process of the Source device.

[0258] Referring to Figure 10, the Source device receives the HPD from the Sink device (Receiving the HPD).

[0259] The Source device reads the EDID / DisplayID of the Sink device (EDID / DisplayID Read). That is, the Source device receives the EDID / DisplayID of the Sink device from the Sink device.

[0260] The Source device determines whether the Sink device has DisplayID2.x.

[0261] If the Sink device is determined to have DisplayID2.x, the Source device uses the DisplayID2.x Adaptive-Sync Data Block's Frame rate.

[0262] If the Sink device determines that it does not have DisplayID2.x, the Source device uses the Base Block Range Limit's Frame rate, or, Using DisplayID1.x Video Timing Range Limits Data Block's Frame rate.

[0263]

[0264] FIG. 11 is a diagram illustrating an example of a process for determining a Frame Range during Adaptive-Sync operation according to various embodiments of the present disclosure.

[0265] Specifically, Fig. 11 illustrates an example of the operation process of the Source device.

[0266] Referring to Figure 11, the Source device receives the HPD from the Sink device (Receiving the HPD).

[0267] The Source device reads the EDID / DisplayID of the Sink device (EDID / DisplayID Read). That is, the Source device receives the EDID / DisplayID of the Sink device from the Sink device.

[0268] The Source device determines whether the Sink device has the DisplayID blocks.

[0269] If the Sink device determines that it has DisplayID blocks, the Source device determines whether the Sink device has a block with DisplayID Version >= 2.0.

[0270] If the Sink device determines that it has a Block with DisplayID Version >= 2.0, the Source device determines whether the Adaptive-Sync Data Block Fmax < 510Hz.

[0271] If the Adaptive-Sync Data Block Fmax < 510Hz is determined, the Source device uses the DisplayID2.x Adaptive-Sync Data Block's Frame rate.

[0272] If the Sink device determines that it has not the DisplayID blocks, or if it determines that Fmax: Range Limit Block & Video Timing Range < Adaptive Sync Data Block, the Source device uses the Base Block Range Limit's Frame rate, or, Using DisplayID1.x Video Timing Range Limits Data Block's Frame rate.

[0273] If the Sink device determines that there is no Block with DisplayID Version >= 2.0, the Source device uses the Base Block Range Limit's Frame rate, or, Using DisplayID1.x Video Timing Range Limits Data Block's Frame rate.

[0274] If it is determined that the Adaptive-Sync Data Block Fmax >= 510Hz, the Source device determines whether Fmax: Range Limit Block & Video Timing Range < Adaptive Sync Data Block.

[0275] If Fmax: Range Limit Block & Video Timing Range < Adaptive Sync Data Block is determined, the Source device uses the DisplayID2.x Adaptive-Sync Data Block's Frame rate.

[0276] If Fmax: Range Limit Block & Video Timing Range >= Adaptive Sync Data Block is determined, the Source device uses the Base Block Range Limit's Frame rate, or, Using DisplayID1.x Video Timing Range Limits Data Block's Frame rate.

[0277]

[0278] FIG. 12 is a diagram illustrating an example of a process for determining a Frame Range during Adaptive-Sync operation according to various embodiments of the present disclosure.

[0279] Specifically, Fig. 12 illustrates an example of the operation process of the Source device.

[0280] Referring to Figure 12, the Source device receives the HPD from the Sink device (Receiving the HPD).

[0281] The Source device reads the EDID / DisplayID of the Sink device (EDID / DisplayID Read). That is, the Source device receives the EDID / DisplayID of the Sink device from the Sink device.

[0282] The Source device determines whether the Sink device has the DisplayID2.x blocks.

[0283] If the Sink device determines that it has the DisplayID2.x blocks, the Source device determines whether the Adaptive-Sync Data Block's Fmax is < 510Hz.

[0284] If the Adaptive-Sync Data Block Fmax < 510Hz is determined, the Source device uses the DisplayID2.x Adaptive-Sync Data Block's Frame rate.

[0285] If the Sink device determines that it does not have the DisplayID2.x blocks, the Source device uses the Base Block Range Limit's Frame rate, or, Using DisplayID1.x Video Timing Range Limits Data Block's Frame rate.

[0286] If the Adaptive-Sync Data Block Fmax >= 510Hz is determined, the Source device uses the Base Block Range Limit's Frame rate, or, Using DisplayID1.x Video Timing Range Limits Data Block's Frame rate.

[0287]

[0288] FIG. 13 is a diagram illustrating an example of a process for determining a Frame Range during Adaptive-Sync operation according to various embodiments of the present disclosure.

[0289] Specifically, Fig. 13 illustrates an example of the operation process of the Source device.

[0290] Referring to Figure 13, the Source device receives the HPD from the Sink device (Receiving the HPD).

[0291] The Source device reads the EDID / DisplayID of the Sink device (EDID / DisplayID Read). That is, the Source device receives the EDID / DisplayID of the Sink device from the Sink device.

[0292] The source device determines whether the Adaptive-Sync Data Block's Fmax < 510Hz.

[0293] If the Adaptive-Sync Data Block Fmax < 510Hz is determined, the Source device uses the DisplayID2.x Adaptive-Sync Data Block's Frame rate.

[0294] If the Adaptive-Sync Data Block Fmax >= 510Hz is determined, the Source device uses the Base Block Range Limit's Frame rate, or, Using DisplayID1.x Video Timing Range Limits Data Block's Frame rate.

[0295]

[0296] [Source device claim related description]

[0297] The embodiments described below are specifically described with reference to FIG. 14 in terms of terminal operation. The methods described below are distinguished for convenience of explanation, and it is understood that some components of one method may be substituted for or combined with some components of another method, as long as they are not mutually exclusive.

[0298] FIG. 14 is a diagram illustrating an example of an operation process of a source device according to various embodiments of the present disclosure.

[0299] According to various embodiments of the present disclosure, a method is provided that is performed by a source device.

[0300] The source device includes a processor; a memory; and a transceiver. The memory stores instructions for performing operations based on those executed by the processor.

[0301] At step S1401, the Source device receives a hot plug detection (HPD) signal from the Sink device.

[0302] At step S1402, the Source device receives EDID (Extended Display Identification) and DisplayID from the Sink device.

[0303] At step S1403, the Source device determines the Adaptive Sync Data Block and frame rate based on the EDID and DisplayID of the Sink device.

[0304] At step S1404, the source device transmits information on the determined frame rate and the generated SDP (Session Description Protocol) based on the determined Adaptive Sync Data Block to the sink device.

[0305]

[0306] According to various embodiments of the present disclosure, when the maximum frame rate of the Adaptive-Sync Data Block is less than 510 Hz: the SDP may be generated using DisplayID2.x, and the frame rate may be determined based on DisplayID2.x.

[0307] According to various embodiments of the present disclosure, when the frame rate range of the Adaptive-Sync Data Block is included within the frame rate range of the range limit block and the video timing range: the SDP is generated using DisplayID2.x, and the frame rate can be determined based on the frame rate range of the Adaptive-Sync Data Block.

[0308] According to various embodiments of the present disclosure, when there are a plurality of Adaptive-Sync Data Block frame rate ranges, and at least one of the plurality of Adaptive-Sync Data Block frame rate ranges is included within a frame rate range of a range limit block and a video timing range: the SDP is generated using DisplayID2.x, and the frame rate can be determined based on at least one Adaptive-Sync Data Block frame rate range included within the frame rate range of the range limit block and the video timing range.

[0309] According to various embodiments of the present disclosure, when there are a plurality of Adaptive-Sync Data Block frame rate ranges, and a plurality of Adaptive-Sync Data Block frame rate ranges among the plurality of Adaptive-Sync Data Block frame rate ranges are included within a frame rate range of a range limit block and a video timing range: the SDP is generated using DisplayID2.x, and the frame rate can be determined based on a widest range of Adaptive-Sync Data Block frame rate ranges among the plurality of Adaptive-Sync Data Block frame rate ranges that are included within a frame rate range of a range limit block and a video timing range.

[0310] According to various embodiments of the present disclosure, when the frame rate range of the Adaptive-Sync Data Block is not included within the frame rate range of the Range Limit Block and the Video Timing Range: the SDP may be generated using DisplayID1.x, and the frame rate may be determined based on the frame rate range of the Range Limit Block and the Video Timing Range.

[0311] According to various embodiments of the present disclosure, when the maximum frame rate of the Adaptive-Sync Data Block is greater than or equal to 510 Hz: the SDP is generated using DisplayID1.x, and the frame rate can be determined based on the frame rate range of the range limit block and the video timing range.

[0312]

[0313] According to various embodiments of the present disclosure, a source device is provided. The source device includes a processor; a memory; and a transceiver, wherein the processor may be configured to perform a method of operating the source device according to FIG. 14.

[0314]

[0315] According to various embodiments of the present disclosure, a device for controlling a source device is provided. The device includes at least one processor and at least one memory operably connected to the at least one processor. The at least one memory may be configured to store instructions for performing an operating method of the source device according to FIG. 14 based on instructions executed by the at least one processor.

[0316]

[0317] According to various embodiments of the present disclosure, one or more non-transitory computer-readable media (CRM) storing one or more commands are provided. The one or more commands, when executed by one or more processors, perform operations, and the operations may include an operating method of a source device according to FIG. 14.

[0318]

[0319] The claims described in the various embodiments of the present disclosure may be combined in various ways. For example, the technical features of the method claims of the various embodiments of the present disclosure may be combined and implemented as a device, and the technical features of the device claims of the various embodiments of the present disclosure may be combined and implemented as a method. Furthermore, the technical features of the method claims of the various embodiments of the present disclosure may be combined and implemented as a device, and the technical features of the method claims of the various embodiments of the present disclosure may be combined and implemented as a method.

Claims

1. In the method of operation of the source device, A step of receiving a HPD (hot plug detection) signal from a sink device; A step of receiving EDID (Extended Display Identification) and DisplayID from the Sink device; A step of determining an Adaptive Sync Data Block and a frame rate based on the EDID and the DisplayID of the Sink device; A step of transmitting information on a determined frame rate to the Sink device, including an SDP (Session Description Protocol) generated based on a determined Adaptive Sync Data Block. method.

2. In paragraph 1, If the maximum frame rate of the Adaptive-Sync Data Block is less than 510 Hz: The above SDP is generated using DisplayID2.x, The frame rate is determined based on DisplayID2.x, method.

3. In paragraph 1, If the frame rate range of the Adaptive-Sync Data Block falls within the frame rate range of the Range Limit Block and the Video Timing Range: The above SDP is generated using DisplayID2.x, The frame rate is determined based on the frame rate range of the Adaptive-Sync Data Block. method.

4. In paragraph 1, If there are multiple Adaptive-Sync Data Block frame rate ranges, and at least one of the multiple Adaptive-Sync Data Block frame rate ranges falls within the frame rate range of the Range Limit Block and the Video Timing Range: The above SDP is generated using DisplayID2.x, The frame rate is determined based on at least one Adaptive-Sync Data Block frame rate range that falls within the frame rate range of the Range Limit Block and the Video Timing Range. method.

5. In paragraph 1, If there are multiple Adaptive-Sync Data Block frame rate ranges, and a majority of the multiple Adaptive-Sync Data Block frame rate ranges fall within the frame rate range of the range limit block and the video timing range: The above SDP is generated using DisplayID2.x, The frame rate is determined based on the widest range of Adaptive-Sync Data Block frame rate ranges that fall within the frame rate ranges of the range limit block and the video timing range among the multiple Adaptive-Sync Data Block frame rate ranges. method.

6. In paragraph 1, If the frame rate range of the Adaptive-Sync Data Block does not fall within the frame rate range of the Range Limit Block and the Video Timing Range: The above SDP is generated using DisplayID1.x, The frame rate is determined based on the frame rate range of the range limit block and the video timing range. method.

7. In paragraph 1, If the maximum frame rate of the Adaptive-Sync Data Block is greater than or equal to 510 Hz: The above SDP is generated using DisplayID1.x, The frame rate is determined based on the frame rate range of the range limit block and the video timing range. method.

8. For the source device, A processor; memory; and a transceiver, The above memory stores instructions for performing operations based on what is executed by the processor, The above actions are, A step of receiving a HPD (hot plug detection) signal from a sink device; A step of receiving EDID (Extended Display Identification) and DisplayID from the Sink device; A step of determining an Adaptive Sync Data Block and a frame rate based on the EDID and the DisplayID of the Sink device; A step of transmitting information on a determined frame rate to the Sink device, including an SDP (Session Description Protocol) generated based on a determined Adaptive Sync Data Block. Source device.

9. In paragraph 8, If the maximum frame rate of the Adaptive-Sync Data Block is less than 510 Hz: The above SDP is generated using DisplayID2.x, The frame rate is determined based on DisplayID2.x, Source device.

10. In paragraph 8, If the frame rate range of the Adaptive-Sync Data Block falls within the frame rate range of the Range Limit Block and the Video Timing Range: The above SDP is generated using DisplayID2.x, The frame rate is determined based on the frame rate range of the Adaptive-Sync Data Block. Source device.

11. In paragraph 8, If there are multiple Adaptive-Sync Data Block frame rate ranges, and at least one of the multiple Adaptive-Sync Data Block frame rate ranges falls within the frame rate range of the Range Limit Block and the Video Timing Range: The above SDP is generated using DisplayID2.x, The frame rate is determined based on at least one Adaptive-Sync Data Block frame rate range that falls within the frame rate range of the Range Limit Block and the Video Timing Range. Source device.

12. In paragraph 8, If there are multiple Adaptive-Sync Data Block frame rate ranges, and a majority of the multiple Adaptive-Sync Data Block frame rate ranges fall within the frame rate range of the range limit block and the video timing range: The above SDP is generated using DisplayID2.x, The frame rate is determined based on the widest range of Adaptive-Sync Data Block frame rate ranges that fall within the frame rate ranges of the range limit block and the video timing range among the multiple Adaptive-Sync Data Block frame rate ranges. Source device.

13. In paragraph 8, If the frame rate range of the Adaptive-Sync Data Block does not fall within the frame rate range of the Range Limit Block and the Video Timing Range: The above SDP is generated using DisplayID1.x, The frame rate is determined based on the frame rate range of the range limit block and the video timing range. Source device.

14. In paragraph 8, If the maximum frame rate of the Adaptive-Sync Data Block is greater than or equal to 510 Hz: The above SDP is generated using DisplayID1.x, The frame rate is determined based on the frame rate range of the range limit block and the video timing range. Source device.

15. In one or more non-transitory computer-readable media storing one or more instructions, The one or more instructions perform operations based on being executed by one or more processors, The above actions are, A step of receiving a HPD (hot plug detection) signal from a sink device; A step of receiving EDID (Extended Display Identification) and DisplayID from the Sink device; A step of determining an Adaptive Sync Data Block and a frame rate based on the EDID and the DisplayID of the Sink device; A step of transmitting information on a determined frame rate to the Sink device, including an SDP (Session Description Protocol) generated based on a determined Adaptive Sync Data Block. Computer readable medium.

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