Memory and preparation method therefor, and electronic device

Abstract

The present disclosure relates to the technical field of integrated circuit design and manufacturing, and in particular relates to a memory and a preparation method therefor, and an electronic device, which are used for reducing the processing complexity and costs of a prepared product while improving the data bandwidth each time the prepared product is accessed. The memory comprises a plurality of memory cells 100 stacked in the thickness direction perpendicular to the surface of a substrate (10); a write word line (20) and a read word line (30), both extending in a second direction parallel to the surface of the substrate (10); a write bit line (60) and a read bit line (90), both extending to the substrate (10) in a direction perpendicular to the substrate (10); a write transistor (70), comprising a source contact region, a channel region, and a drain contact region sequentially distributed in the second direction; a read transistor (101), comprising a back gate and a source contact region, a channel region, and a drain contact region sequentially distributed in the second direction, the back gate being located between the write word line (20) and the read transistor (101).

Description

Memory and preparation method thereof, and electronic device

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This disclosure claims priority to a Chinese patent application filed with the Patent Office of China on May 12, 2023, with application number 202310534005.1 and invention name “Memory and its preparation method, electronic device”. The entire contents of the patent application are incorporated into this disclosure by reference. Technical Field

[0003] The present disclosure relates to the technical field of integrated circuit design and manufacturing, and in particular to a memory and a preparation method thereof, and an electronic device. Background Art

[0004] With the continuous development of integrated circuit manufacturing technology, the market has increasingly higher requirements for the capacity, preparation cost, and data transmission rate of storage products, and three-dimensional stacked storage structure has become an important development direction.

[0005] For example, in the field of dynamic random access memory (DRAM), two-dimensional memory arrays pose great challenges to processes and manufacturing equipment in terms of miniaturization. Stacking multiple layers of two-dimensional memory cell arrays in the vertical direction has become a technological development direction to achieve high-density storage.

[0006] Summary of the Invention

[0007] According to various embodiments of the present disclosure, a memory, a method for manufacturing the same, and an electronic device are provided.

[0008] In some embodiments, an aspect of the present disclosure provides a memory comprising a substrate, a write word line, a read word line, a write bit line, a read bit line, and a plurality of memory cells stacked in a direction perpendicular to the substrate; each memory cell comprises a write transistor and a read transistor located between the write word line and the read word line and sequentially distributed along a first direction parallel to the substrate; the write bit line and the read bit line are located between the write word line and the read word line and are connected to the write transistor and the read transistor, respectively; wherein the write word line and the read word line both extend in a second direction parallel to the substrate; the write bit line and the read bit line both extend in a direction perpendicular to the substrate; the read transistor comprises a back gate and a first semiconductor layer extending in the second direction and surrounding the read word line, the first semiconductor layer having a source contact region, a drain contact region, and a channel region located between the source contact region and the drain contact region sequentially distributed in the second direction, the back gate being located between the write word line and the channel region of the read transistor; the write transistor comprises a second semiconductor layer extending in the second direction and surrounding the write word line, the second semiconductor layer having a source contact region, a drain contact region, and a channel region located between the source contact region and the drain contact region sequentially distributed in the second direction; the first direction intersects with the second direction.

[0009] In some embodiments, the back gate includes at least a gate conductive layer and a gate dielectric layer; the memory includes: at least one first through hole between the write word line and the read word line and passing through each memory cell, and a gate dielectric layer and a gate conductive layer sequentially arranged on the side walls of each first through hole; wherein, the gate conductive layers corresponding to memory cells in different layers are insulated from each other by a dielectric layer; the gate conductive layer in the first through hole is connected to the corresponding source contact area in an area close to the write transistor, and is connected to the read transistor through the gate dielectric layer.

[0010] In some embodiments, an opening is provided on the gate dielectric layer in a region close to the write transistor, and the gate conductive layer is connected to the corresponding write transistor in the opening region.

[0011] In some embodiments, the gate conductive layer in at least one first through-hole surrounds a sidewall of the first through-hole.

[0012] In some embodiments, the aperture of the first through hole corresponding to the gate conductive layer near the middle region of the gate conductive layer is larger than the aperture of the regions near both ends of the gate conductive layer, and the gate dielectric layer forms an adaptive structure according to the shape of the first through hole.

[0013] In some embodiments, the first semiconductor layer has two opposite main surfaces, which are respectively a first side and a second side of the first semiconductor layer, the first side faces away from the read word line, and the second side faces the read word line. The first semiconductor layer includes a source contact region and a drain contact region of the read transistor spaced apart on the first side, and a channel region located between the source contact region and the drain contact region.

[0014] In some embodiments, the first semiconductor layer surrounds the side wall of the read word line and is insulated from the read word line; the first side of the first semiconductor layer includes an upper surface, a lower surface and a side surface, and the source contact area, the channel area and the drain contact area of ​​the read transistor are at least partially located on the side surface and are arranged in sequence along the extension direction of the read word line.

[0015] In some embodiments, the memory further includes: a second through hole close to the channel region of the write transistor and passing through each layer of storage cells, and multiple conductive layers located on the side walls of the second through hole, wherein the conductive layers corresponding to different layers of storage cells are insulated from each other; the second through hole exposes the source contact region and gate conductive layer of the write transistor of each layer of storage cells; each conductive layer is located on the side wall of the second through hole and forms a ring structure, and the ring structure is simultaneously connected to the source contact region of the write transistor and the gate conductive layer exposed in the second through hole.

[0016] In some embodiments, the channel region of the read transistor, the first through-hole, the second through-hole, and the source contact region of the write transistor all cover at least one straight line parallel to the first direction.

[0017] In some embodiments, the second semiconductor layer has two opposite main surfaces, which are respectively a first side and a second side of the second semiconductor layer, the first side faces away from the write word line, and the second side faces the write word line. The second semiconductor layer includes a source contact region and a drain contact region of the write transistor spaced apart on the first side, and a channel region located between the source contact region and the drain contact region.

[0018] In some embodiments, the second semiconductor layer surrounds the side wall of the write word line and is insulated from the write word line; the first side of the second semiconductor layer includes an upper surface, a lower surface and a side surface, and the source contact area, the channel area and the drain contact area of ​​the write transistor are at least partially located on the side surface and are arranged in sequence along the extension direction of the write word line.

[0019] In some embodiments, the memory further includes a reference line along a direction perpendicular to the substrate, the reference line extending along a direction perpendicular to the substrate through each memory cell and connected to the read transistor of each memory cell; the read bit line, back gate and reference line are arranged in sequence along the second direction.

[0020] In some embodiments, the write bit line and the read bit line are located on the same side away from the back gate along the second direction.

[0021] In some embodiments, another aspect of the present disclosure provides an electronic device, comprising the memory as described in any of the embodiments of the present disclosure.

[0022] In some embodiments, another aspect of the present disclosure provides a method for preparing a memory, comprising: providing a substrate; forming a stacked structure on the substrate, the stacked structure comprising sacrificial layers and dielectric layers alternately stacked in a direction perpendicular to the substrate; forming a write word line, a read word line, a write bit line, a read bit line, and a plurality of memory cells stacked in a direction perpendicular to the substrate on the substrate based on the stacked structure; each memory cell comprises a write transistor and a read transistor located between the write word line and the read word line and sequentially distributed in a first direction parallel to the substrate; the write word line and the read word line both extend in a second direction parallel to the substrate; the write bit line and the read bit line both extend in a direction perpendicular to the substrate, and the write bit line and the read bit line both extend in a direction perpendicular to the substrate. The line and the read bit line are both located between the write word line and the read word line and are connected to the write transistor and the read transistor respectively; the read transistor includes a back gate and a first semiconductor layer extending along the second direction and surrounding the read word line, the first semiconductor layer is sequentially distributed with a source contact area, a drain contact area and a channel area between the source contact area and the drain contact area in the second direction, and the back gate is located between the write word line and the channel area of ​​the read transistor; the write transistor includes a second semiconductor layer extending along the second direction and surrounding the write word line, the second semiconductor layer is sequentially distributed with a source contact area, a drain contact area and a channel area between the source contact area and the drain contact area in the second direction; the first direction intersects with the second direction.

[0023] In some embodiments, a write word line, a read word line, a write bit line, a read bit line, and a plurality of memory cells stacked in a direction perpendicular to the substrate are formed on a substrate based on a stacked structure, including: forming two isolation trenches extending along a second direction and penetrating the stacked structure on the stacked structure, the two isolation trenches respectively exposing a sacrificial layer and a dielectric layer on two opposite sidewalls of a stacked structure, etching back the exposed sacrificial layer to form a first accommodating groove and a second accommodating groove on the two opposite sidewalls; and forming a plurality of isolation trenches on the inner wall of the first accommodating groove and the inner wall of the second accommodating groove according to the embodiment of the present invention. An initial semiconductor layer, a gate dielectric layer, and a word line material layer are formed, wherein the word line material layer in the first accommodating groove is used to form a write word line, and the word line material layer in the second accommodating groove is used to form a read word line; the initial semiconductor layer, the gate dielectric layer, and the word line material layer in the isolation groove are removed, so that the semiconductor layers and word lines of two adjacent storage cells along the first direction are disconnected, forming initial first semiconductor layers disconnected from each other, initial second semiconductor layers disconnected from each other, read word lines disconnected from each other, and write word lines disconnected from each other.

[0024] In some embodiments, after forming the write word line and the read word line, the method further includes: forming a first trench and a second trench extending along the first direction and spaced apart along the second direction in the stacked structure to define the shape and position of a single memory cell, the first trench and the second trench disconnecting each initial first semiconductor layer and each initial second semiconductor layer, exposing a portion of the outer surface of the gate dielectric layer on the substrate and the word line material layer close to the sacrificial layer to disconnect the second semiconductor layer between different memory cells connected to the same write word line and the first semiconductor layer between different memory cells connected to the same read word line; and filling the first trench and the second trench with an insulating layer to form a first insulating structure and a second insulating structure.

[0025] In some embodiments, the first insulating structure has a bending portion extending along the second direction, the second semiconductor layer has two opposite main surfaces, the two opposite main surfaces are respectively a first side and a second side of the second semiconductor layer, the first side is away from the write line, and the second side is toward the write line, the second semiconductor layer includes a source contact area, a drain contact area and a channel area located between the source contact area and the drain contact area of ​​the write transistor spaced apart on the first side; after forming the first insulating structure and the second insulating structure, it also includes: etching the stacked structure along a direction perpendicular to the substrate to obtain a first sub-through hole exposing a portion of the substrate and located in the area enclosed by the first insulating structure and the write line; etching the sacrificial layer along the first direction and the second direction through the first sub-through hole to obtain a first accommodating groove for defining the channel length of the write transistor; the portion of the side surface of the second semiconductor layer exposed by the first accommodating groove is used to form the channel region of the write transistor; forming an isolation layer in the first accommodating groove to form write transistors insulated from each other along a direction perpendicular to the substrate.

[0026] In some embodiments, the first semiconductor layer has two opposing main surfaces, which are respectively a first side and a second side of the first semiconductor layer, the first side facing away from the read word line, and the second side facing the read word line, the first semiconductor layer including a source contact region, a drain contact region, and a channel region located between the source contact region and the drain contact region of the read transistor spaced apart on the first side; after forming an isolation layer in the first accommodating groove, the method further includes: etching the stacked structure in a direction perpendicular to the substrate to obtain a second sub-through hole exposing a portion of the substrate and located between the bent portion of the first insulating structure and the first semiconductor layer; etching the sacrificial layer along the first direction and the second direction through the second sub-through hole to obtain a second accommodating groove for defining the channel length of the read transistor; the portion of the side surface of the first semiconductor layer exposed by the second accommodating groove is used to form the channel region of the read transistor; forming a gate dielectric layer and a gate conductive layer in sequence in the second accommodating groove to obtain a second sub-through hole, the gate dielectric layer covering the inner wall of the second sub-through hole; forming an insulating layer in the second sub-through hole to form a back gate insulated from each other in a direction perpendicular to the substrate, the insulating layer, the gate conductive layer, and the gate dielectric layer being used to jointly form the back gate.

[0027] In some embodiments, after forming the insulating layer in the second sub-through hole, the method further includes: etching the stacked structure in a direction perpendicular to the substrate to obtain a third sub-through hole that exposes a portion of the substrate and is located in the enclosed area of ​​the second insulating structure, the back gate, the first insulating structure, and the second semiconductor layer; etching the sacrificial layer along the first direction and the second direction through the third sub-through hole to obtain a third accommodating groove that exposes the source contact area of ​​the write transistor and the gate conductive layer of the back gate; forming a conductive layer in the third accommodating groove to obtain a third sub-through hole; forming an insulating layer in the third sub-through hole; and etching the sacrificial layer in the second direction through the third sub-through hole to obtain a third accommodating groove that exposes the source contact area of ​​the write transistor and the gate conductive layer of the back gate. A fourth sub-through hole is formed in the enclosed area between the bent portion of the structure and the first semiconductor layer, and the fourth sub-through hole exposes the source contact area of ​​the read transistor; a reference line is formed in the fourth sub-through hole; a fifth sub-through hole is formed in the enclosed area between the bent portion of the first insulating structure and the first semiconductor layer, and the fifth sub-through hole exposes the drain contact area of ​​the read transistor; a read bit line is formed in the fifth sub-through hole; a sixth sub-through hole is formed in the enclosed area between the bent portion of the first insulating structure and the second semiconductor layer, and the sixth sub-through hole exposes the drain contact area of ​​the write transistor; and a write bit line is formed in the sixth sub-through hole.

[0028] The details of one or more embodiments of the present disclosure are set forth in the accompanying drawings and the description below. Other features, objects, and advantages of the present disclosure will become apparent from the description, drawings, and claims. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present disclosure. For ordinary technicians in this field, without paying any creative work, they can also obtain drawings of other embodiments based on these drawings.

[0030] FIG1 is a schematic flow chart of a method for preparing a semiconductor device provided in some embodiments of the present disclosure;

[0031] FIG2 a is a schematic top view of a stacked structure provided in step S20 in some embodiments of the present disclosure;

[0032] FIG2b is a schematic diagram of a cross-sectional structure of the three-dimensional structure shown in FIG2a along the AA' direction;

[0033] FIG3 a is a schematic top view of another stacked structure provided in step S20 in some embodiments of the present disclosure;

[0034] FIG3b is a schematic diagram of a cross-sectional structure of the three-dimensional structure shown in FIG3a along the AA' direction;

[0035] FIG4 a is a schematic top view of a structure obtained after forming a word line material layer in step S614 in some embodiments of the present disclosure;

[0036] FIG4b is a schematic diagram of a cross-sectional structure of the three-dimensional structure shown in FIG4a along the AA' direction;

[0037] FIG5a is a schematic cross-sectional view of the three-dimensional structure obtained along the AA′ direction after forming an isolation trench in the three-dimensional structure shown in FIG4a;

[0038] FIG5 b is a schematic cross-sectional view of the three-dimensional structure obtained along the AA′ direction after forming an isolation structure within the three-dimensional structure shown in FIG5 a ;

[0039] FIG6 a is a schematic top view of a three-dimensional structure obtained after forming a first insulating structure and a second insulating structure within the three-dimensional structure shown in FIG5 b ;

[0040] FIG6b is a schematic diagram of a cross-sectional structure of the three-dimensional structure shown in FIG6a along the AA' direction;

[0041] FIG6c is a schematic diagram of a cross-sectional structure of the three-dimensional structure shown in FIG6a along the EE' direction;

[0042] FIG7 a is a schematic top view of the structure obtained after a first accommodating groove is formed in the three-dimensional structure shown in FIG6 a ;

[0043] FIG7b is a schematic diagram of a cross-sectional structure of the three-dimensional structure shown in FIG7a along the BB' direction;

[0044] FIG8 is a schematic cross-sectional view of the three-dimensional structure obtained along the BB′ direction after forming an isolation layer in the three-dimensional structure shown in FIG7a;

[0045] FIG9 a is a schematic top view of the structure obtained after a second accommodating groove is formed in the structure shown in FIG8 ;

[0046] FIG9b is a schematic diagram of a cross-sectional structure of the three-dimensional structure shown in FIG9a along the CC' direction;

[0047] FIG10 is a schematic cross-sectional view of the three-dimensional structure obtained along the CC' direction after a gate conductive layer is formed in the three-dimensional structure shown in FIG9b;

[0048] FIG11a is a schematic top view of the structure obtained after forming a back gate in the structure shown in FIG10;

[0049] FIG11b is a schematic diagram of a cross-sectional structure of the three-dimensional structure shown in FIG11a along the CC' direction;

[0050] FIG12a is a schematic top view of the structure obtained after a third accommodating groove is formed in the structure shown in FIG11a;

[0051] FIG12b is a schematic diagram of a cross-sectional structure of the three-dimensional structure shown in FIG12a along the CC' direction;

[0052] FIG13a is a schematic top view of the structure obtained after forming an interlayer conductive layer within the structure shown in FIG12a;

[0053] FIG13b is a schematic diagram of a cross-sectional structure of the three-dimensional structure shown in FIG13a along the CC' direction;

[0054] FIG14a is a schematic top view of the structure obtained after forming an interlayer dielectric layer in the structure shown in FIG13a;

[0055] FIG14b is a schematic diagram of a cross-sectional structure of the three-dimensional structure shown in FIG14a along the CC' direction;

[0056] FIG15a is a schematic top view of the structure obtained after forming a fifth sub-through hole in the structure shown in FIG14a;

[0057] FIG15b is a schematic diagram of a cross-sectional structure of the three-dimensional structure shown in FIG15a along the BB' direction;

[0058] FIG16 is a schematic cross-sectional view of the three-dimensional structure obtained along the BB′ direction after forming a read bit line in the three-dimensional structure shown in FIG15 a;

[0059] FIG17a is a schematic top view of the structure obtained after forming a fourth sub-through hole in the structure shown in FIG16;

[0060] FIG17b is a schematic diagram of a cross-sectional structure of the three-dimensional structure shown in FIG17a along the DD' direction;

[0061] FIG18 is a schematic cross-sectional view of the three-dimensional structure obtained along the DD′ direction after a reference line is formed in the three-dimensional structure shown in FIG17a;

[0062] FIG19a is a schematic top view of the structure obtained after forming a sixth sub-through hole in the structure shown in FIG18;

[0063] FIG19b is a schematic diagram of a cross-sectional structure of the three-dimensional structure shown in FIG19a along the AA' direction;

[0064] FIG20 is a schematic top view of the structure obtained after forming a write bit line in the structure shown in FIG19a;

[0065] FIG21a is a schematic diagram of a cross-sectional structure of the three-dimensional structure shown in FIG20 along the AA′ direction;

[0066] FIG21 b is a schematic diagram of a cross-sectional structure of the three-dimensional structure shown in FIG20 along the BB′ direction;

[0067] FIG21c is a schematic diagram of a cross-sectional structure of the three-dimensional structure shown in FIG20 along the CC' direction;

[0068] FIG21d is a schematic diagram of a cross-sectional structure of the three-dimensional structure shown in FIG20 along the DD' direction;

[0069] FIG21e is a schematic diagram of a cross-sectional structure of the three-dimensional structure shown in FIG20 along the EE' direction;

[0070] FIG22 is a circuit diagram of a memory cell circuit provided in some embodiments of the present disclosure;

[0071] FIG23 is a circuit diagram of a memory array circuit provided in some embodiments of the present disclosure. DETAILED DESCRIPTION

[0072] To facilitate understanding of the present disclosure, a more comprehensive description of the present disclosure will be provided below with reference to the accompanying drawings. The drawings illustrate preferred embodiments of the present disclosure. However, the present disclosure can be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided to provide a more thorough and comprehensive understanding of the present disclosure.

[0073] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art in the art of the present disclosure. The terms used herein in the specification of the present disclosure are only for the purpose of describing specific embodiments and are not intended to limit the present disclosure.

[0074] It should be understood that when an element or layer is referred to as being "on," "adjacent to," "connected to," or "coupled to" another element or layer, it can be directly on, adjacent to, connected to, or coupled to the other element or layer, or there can be intervening elements or layers. Conversely, when an element is referred to as being "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" another element or layer, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers, doping types, and / or portions, these elements, components, regions, layers, doping types, and / or portions should not be limited by these terms. These terms are merely used to distinguish one element, component, region, layer, doping type, or portion from another element, component, region, layer, doping type, or portion. Therefore, without departing from the teachings of the present invention, the first element, component, region, layer, doping type or portion discussed below may be represented as a second element, component, region, layer or portion; for example, the first doping type may be referred to as the second doping type, and similarly, the second doping type may be referred to as the first doping type; the first doping type and the second doping type are different doping types, for example, the first doping type may be P-type and the second doping type may be N-type, or the first doping type may be N-type and the second doping type may be P-type.

[0075] Spatially relative terms such as "under," "beneath," "beneath," "under," "above," "above," etc., may be used herein to describe the relationship of an element or feature shown in the figures to other elements or features. It should be understood that in addition to the orientations shown in the figures, spatially relative terms also include different orientations of the device in use and operation. For example, if the device in the drawings is turned over, the element or feature described as "under" or "beneath" or "beneath" the other elements will be oriented as "above" the other elements or features. Thus, the exemplary terms "under" and "under" can include both upper and lower orientations. In addition, the device can also include alternative orientations (e.g., rotated 90 degrees or other orientations), and the spatial descriptors used herein are interpreted accordingly.

[0076] As used herein, the singular forms "a," "an," and "the" may also include the plural forms, unless the context clearly indicates otherwise. It should also be understood that when the terms "comprising" and / or "including" are used in this specification, they may specify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups. At the same time, when used herein, the term "and / or" includes any and all combinations of the relevant listed items.

[0077] It should be noted that the illustrations provided in this embodiment are only used to schematically illustrate the basic concept of the present disclosure. Although the illustrations only show components related to the present disclosure and are not drawn according to the number, shape and size of components in actual implementation, the type, quantity and proportion of each component in actual implementation can be changed arbitrarily, and the component layout type may also be more complex.

[0078] Please note that the mutual insulation between the two in the embodiments of the present disclosure includes, but is not limited to, the presence of at least one of insulating material, insulating air, or a gap between the two. The direction perpendicular to the substrate in the embodiments of the present disclosure may be a direction perpendicular to the substrate surface, such as the top surface, and the direction parallel to the substrate may be a direction parallel to the substrate surface, such as the top surface.

[0079] In the disclosed stacking schemes, the word line extension direction is generally perpendicular to the top surface of the substrate, resulting in the number of bytes of data accessed each time being limited by the number of stacked layers of the storage structure, affecting the bandwidth of each data access.

[0080] Referring to FIG. 1 , in some embodiments of the present disclosure, a method for manufacturing a semiconductor device is provided, comprising the following steps:

[0081] Step S20: providing a substrate;

[0082] Step S40: forming a stacked structure on the substrate, the stacked structure including sacrificial layers and dielectric layers alternately stacked in a direction perpendicular to the substrate;

[0083] Step S60: Based on the stacked structure, a write word line, a read word line, a write bit line, a read bit line, and a plurality of memory cells stacked in a direction perpendicular to the substrate are formed on the substrate; each memory cell includes a write transistor and a read transistor located between the write word line and the read word line and sequentially distributed along a first direction parallel to the substrate; the write word line and the read word line both extend along a second direction parallel to the substrate; the write bit line and the read bit line both extend along a direction perpendicular to the substrate, the write bit line and the read bit line are both located between the write word line and the read word line and are connected to the write transistor and the read transistor respectively; the read transistor includes a back gate and a first semiconductor layer extending along the second direction and surrounding the read word line, the first semiconductor layer having a source contact region, a drain contact region, and a channel region located between the source contact region and the drain contact region sequentially distributed in the second direction, and the back gate is located between the write word line and the channel region of the read transistor; the write transistor includes a second semiconductor layer extending along the second direction and surrounding the write word line, the second semiconductor layer having a source contact region, a drain contact region, and a channel region located between the source contact region and the drain contact region sequentially distributed in the second direction; the first direction intersects with the second direction.

[0084] Specifically, please continue to refer to Figure 1. After a stacked structure is formed on a substrate, the stacked structure is patterned to form a number of sub-stacked structures spaced apart in a first direction, with isolation trenches formed between the sub-stacked structures, exposing the sacrificial layer and the dielectric layer on the sidewalls of the isolation trenches; based on the sub-stacked structures, a number of memory cells stacked in a direction perpendicular to the substrate are formed on the substrate, and by setting the write word lines and the read word lines in the memory cells to be spaced apart along the first direction and both extending along a second direction parallel to the substrate surface, the source contact region, the drain contact region of the write transistor and the read transistor located between the write word line and the read word line, and the channel region located between the source contact region and the drain contact region are sequentially distributed along the second direction, and the write bit line and the read bit line located between the write word line and the read word line are both extended in a direction perpendicular to the substrate. This invention is completely different from the technical solution in the related art in which "both word lines and bit lines extend in a direction parallel to the substrate surface". It facilitates forming a memory array with a three-dimensional arrangement along the first direction, the second direction and the thickness direction using the memory cell. Since two adjacent columns of memory cells along the first direction in the memory array can share a common read bit line / common write bit line, it is possible to simultaneously access write word lines adjacent to the first direction or read word lines adjacent to the first direction. Therefore, a memory cell is proposed in which the word line extension direction is parallel to the substrate surface and the bit line extension direction is perpendicular to the substrate surface. This overcomes the technical prejudice that "the number of bytes accessed each time depends on the number of memory cells sharing a word line", effectively improves the bandwidth of each data access, and thus improves the data transmission rate of the manufactured product. In addition, the memory cell can provide an electrical signal to the storage node via the write bit line and the write transistor when the write transistor is turned on to realize data writing. A storage data readout path including the read word line, the read bit line and the read transistor is formed, so that the relative size of the output electrical signal value is obtained by using the storage data readout path, and data is read out via the storage data readout path. Therefore, the embodiment of the present disclosure uses two transistors to realize the writing and reading of storage data without the aid of a capacitor structure. It can reduce the volume of the manufactured product while ensuring that the storage capacity is not reduced, improve the storage density and integration of the memory, effectively reduce the process difficulty and manufacturing cost of the memory, and improve the performance and reliability of the manufactured memory.

[0085] As an example, please refer to Figures 2a-2b. The substrate 10 provided in step S20 can be made of semiconductor material, insulating material, conductor material or any combination thereof. The substrate 10 can be a single-layer structure or a multi-layer structure. For example, the substrate 10 can be a silicon (Si) substrate, a silicon germanium (SiGe) substrate, a silicon germanium carbon (SiGeC) substrate, a silicon carbide (SiC) substrate, a gallium arsenide (GaAs) substrate, an indium arsenide (InAs) substrate, an indium phosphide (InP) substrate or other III / V semiconductor substrates or II / VI semiconductor substrates. Alternatively, for example, the substrate 10 can be a layered substrate including Si / SiGe, Si / SiC, silicon on insulator (SOI) or silicon germanium on insulator. Therefore, the type of substrate 10 should not limit the scope of protection of the present disclosure.

[0086] The above-mentioned substrate may also be other structures with supporting functions, such as peripheral circuits. The multilayer array of the present application is arranged on a supporting structure composed of peripheral circuits, and the supporting structure may also be understood as a substrate.

[0087] As an example, please refer to Figures 2a to 3b. In step S40, a deposition process and / or an epitaxial growth process can be used to form a stacked structure 1001 on the substrate 10. The stacked structure 1001 includes a sacrificial material layer 111 and a dielectric material layer 121 stacked in sequence along the thickness direction of the substrate 10 (for example, the oz direction). In some embodiments, the sacrificial material layer 111 may be adjacent to the substrate 10. A first mask layer 131 is then formed on the top surface of the top dielectric material layer 121. After patterning the first mask layer 131, a first patterned mask layer 13 including a first opening pattern (not shown) is formed. The first opening pattern is used to define the shape and position of the isolation trench 1031. Using the first patterned mask layer 13 as a mask, the stacked sacrificial material layer 111 and dielectric material layer 121 are etched along the oz direction to form the isolation trench 1031 that exposes a portion of the substrate 10. The remaining sacrificial material layer 111 is used to form the sacrificial layer 11, and the remaining dielectric material layer 121 is used to form the dielectric layer 12. The sacrificial layers 11 and dielectric layers alternately stacked along the oz direction constitute a sub-stack structure 1010. Each isolation trench 1031 is located between two sub-stack structures 1010, and each sub-stack structure has two isolation trenches 1031. FIG. 3 b shows two sub-stack structures 1010, resulting in a total of three isolation trenches 1031.

[0088] The material of the sacrificial layer 11 can be a semiconductor material or a conductor material. The semiconductor material can be silicon germanium (SiGe); the conductor material can be a conductive metal or metal silicide. The material of the dielectric layer 12 can be selected from electrically insulating materials such as silicon dioxide, silicon oxynitride, silicon carbide, and combinations thereof. The first mask layer 131 can be a hard mask layer. The deposition process can include, but is not limited to, at least one of chemical vapor deposition (CVD), atomic layer deposition (ALD), high-density plasma deposition (HDP), plasma-enhanced deposition, and spin-on dielectric (SOD). The etching process can include, but is not limited to, dry etching and / or wet etching. The dry etching process can include, but is not limited to, at least one of reactive ion etching (RIE), inductively coupled plasma etching (ICP), and high-density plasma etching (HDP). In some embodiments, the first patterned mask layer 13 may be retained in subsequent process steps to protect the dielectric layer 12 directly below it and prevent subsequent processes from damaging the dielectric layer 12. In other embodiments, the first patterned mask layer 13 may be removed in subsequent process steps to meet the actual needs of various different application scenarios.

[0089] As an example, referring to Figures 3a-5b, an isolation trench 1031 extending along the oy direction and penetrating the stacked structure 1001 is formed between adjacent sub-stacked structures 1010 along the ox direction. Two adjacent isolation trenches 1031 along the ox direction expose the sacrificial layer 11 and the dielectric layer 12 on two oppositely disposed sidewalls. The exposed sacrificial layer 11 and the dielectric layer 12 on the two oppositely disposed sidewalls belong to one sub-stacked structure 1010. In step S60, a plurality of memory cells are formed on the substrate 10 in a direction perpendicular to the substrate 10 based on the sub-stacked structures 1010, including:

[0090] Step S612: etching back the exposed sacrificial layer 11 through the two adjacent isolation trenches 1031 along the ox direction, for example, etching back the opposite sidewalls of the sacrificial layer 11 along the ox direction, to form a first receiving groove 1002 and a second receiving groove 1003 on two opposite sidewalls of a sub-stack structure 1010;

[0091] Step S614: By depositing a film layer in the isolation trench 1031, an initial semiconductor layer 1004, a gate dielectric layer 22 and a word line material layer 211 are formed in sequence on the inner wall of the first accommodating groove 1002 and the inner wall of the second accommodating groove 1003. The word line material layer 211 located in the first accommodating groove 1002 is used to form the write word line 20, and the word line material layer 211 located in the second accommodating groove 1003 is used to form the read word line 30.

[0092] Step S616: Remove the initial semiconductor layer 1004, the gate dielectric layer 22 and the word line material layer 211 in the isolation trench 1031, so that the semiconductor layers and word lines of two adjacent storage cells along the ox direction are disconnected, forming initial first semiconductor layers that are disconnected from each other in different layers, initial second semiconductor layers that are disconnected from each other in different layers, read word lines that are disconnected from each other in different layers, and write word lines that are disconnected from each other in different layers.

[0093] This step has formed independent semiconductor layers and word lines. The formation methods will be described later.

[0094] As an example, please continue to refer to Figures 4a and 4b. In step S614, an atomic layer deposition process can be used to form an initial semiconductor layer 1004 on the inner wall of the first containing groove 1002 and the inner wall of the second containing groove 1003 in the isolation trench 1031. The film thickness of the initial semiconductor layer 1004 can be accurately controlled, which is conducive to optimizing the film formation process of the initial semiconductor layer 1004, improving the uniformity and density of the formed initial semiconductor layer 1004, and thus optimizing the performance of the semiconductor device. The material of the initial semiconductor layer 1004 can be selected from indium gallium zinc oxide, indium zinc oxide, transition metals, transition metal oxides and combinations thereof. In this embodiment, the material of the initial semiconductor layer 1004 is a metal oxide semiconductor material, and the material of the metal oxide can be indium gallium zinc oxide (IGZO). When the metal oxide material is IGZO, the leakage current of the transistor is small (the leakage current is less than or equal to 10 -15 A), thereby ensuring a low refresh rate of the dynamic memory. It should be noted that the material of the metal oxide can also be ITO, IWO, ZnO x 、InO x 、In2O3、InWO、SnO2、TiO x 、InSnO x 、Zn x O y N z Mg x Zn y O z 、In x Zn y O z、In x Ga y Zn z O a 、Zr x In y Zn z O a , Hf x In y Zn z O a 、Sn x In y Zn z O a 、Al x Sn y In z Zn a O d 、Si x In y Zn z O a 、Zn x Sn y O z 、Al x Zn y Sn z O a 、Ga x Zn y Sn z O a 、Zr x Zn y Sn z O a , InGaSiO and other materials, as long as the leakage current of the transistor can meet the requirements, it can be adjusted according to actual conditions.

[0095] In step S614, at least one of an in-situ steam generation (ISSG) process, an atomic layer deposition (ALD) process, a plasma vapor deposition (PVM) process, and a rapid thermal oxidation (RTO) process may be used to form a gate dielectric layer 22 on the outer surface of the initial semiconductor layer 1004 in the first receiving groove 1002 and the second receiving groove 1003. The material of the gate dielectric layer 22 may be selected from silicon dioxide (SiO2), silicon oxynitride (SiON), silicon nitride, aluminum oxide (Al2O3), aluminum oxynitride (AlON), and combinations thereof. The gate dielectric layer 22 may also be a high-k dielectric material (a dielectric material having a dielectric constant greater than or equal to 3.9), a low-k dielectric material (a dielectric constant greater than or equal to 2.5 and less than 3.9), an ultra-low-k dielectric material (a dielectric constant less than 2.5), a ferroelectric material, an anti-ferroelectric material, silicon carbide (SiC), or any combination thereof. In step S614, a deposition process can be used to form a wordline material layer 211 that at least fills the isolation trench 1031. The top surface of the wordline material layer 211 can then be processed using at least one of a planarization process, a push-on process, an etching process, and a chemical mechanical polishing process, so that the top surface of the wordline material layer 211 is flush with the top surface of the sub-stack structure 1010. The deposition process can include, but is not limited to, at least one of CVD, ALD, HDP, and SOD. The material of the wordline material layer 211 is selected from indium tin oxide, polysilicon, copper, tungsten, aluminum, copper alloy, titanium, titanium nitride, palladium nitride, tantalum nitride, and combinations thereof.

[0096] As an example, referring again to Figures 5a and 5b, in step S614, a dry etching process can be used to etch the sub-stack structure 1010 along the oz direction to remove the wordline material layer 211, the gate dielectric layer 22, and the portion of the initial semiconductor layer 1004 located within the isolation trench 1031. The wordline material layer 211 located within the first receiving trench 1002 is used to form the write wordline 20, and the wordline material layer 211 located within the second receiving trench 1003 is used to form the read wordline 30. An isolation structure 103 is then filled within the isolation trench 1031, so that the write wordline 20 and the read wordline 30 between adjacent memory cells along the ox direction are insulated from each other via the isolation structure 103. Furthermore, adjacent memory cells along the oz direction are insulated from each other via the dielectric layer 12, and adjacent memory cells along the ox direction are insulated from each other via the isolation structure 103. Then, at least one of a planarization process, a push-flat process, an etching process, and a chemical mechanical polishing process may be used to process the top surface of the isolation structure 103 so that the top surface of the isolation structure 103 is flush with the top surface of the sub-stack structure 1010 .

[0097] As an example, referring to FIG. 6 a to FIG. 6 c , after forming the write word line 20 and the read word line 30 , the following steps are further included:

[0098] Step S622: Forming a first trench and a second trench in the sub-stack structure 1010, extending along a first direction and spaced apart along a second direction. The first trench can disconnect the first semiconductor layer and the second semiconductor layer connected to a word line via the gate insulating layer. Both the first and second trenches expose a portion of the substrate 10 and the outer surface of the gate dielectric layer 22 near the sacrificial layer 11, thereby disconnecting the second semiconductor layer between different memory cells connected to the same write word line and the first semiconductor layer between different memory cells connected to the same read word line. Step S624: Filling the first and second trenches with an insulating layer to form a first insulating structure 40 in the first trench and a second insulating structure 50 in the second trench.

[0099] As an example, please continue to refer to Figures 6a, 7a, 8, 9a, 11a, 12a, 13a, 14a, 15a, 17a, 19a, and 20. In the top view schematic diagram shown in Figure 6a, in order to illustrate the specific structure of the write word line 20 and the read word line 30, the dielectric layer 12 and the first patterned mask layer 13 located directly above the write word line 20 and the read word line 30 are partially transparent. This allows the write word line 20 and the read word line 30 to be seen directly below the dielectric layer 12, as well as the write word line 20 and the read word line 30 directly below the first patterned mask layer 13. For example, in order to illustrate the key structural features of the covered film layer in subsequent figures, the practice of partially transparently displaying the upper film layer will not be repeated.

[0100] As an example, please continue to refer to Figures 6a to 6c. In step S624, an etching process can be used to form a first trench (not shown) for filling the first insulating structure 40 and a second trench (not shown) for forming the second insulating structure 50 in the sub-stack structure 1010. The first trench and the second trench are used to define the shape and position of a single storage unit. The first trench and the second trench both expose part of the outer surface of the substrate 10 and the gate dielectric layer 22 close to the sacrificial layer 11; the outer surface of the gate dielectric layer 22 exposed by the first trench and the second trench includes the upper surface, the lower surface and the side surface; the gate dielectric layer in the first trench and the second trench is completely exposed to ensure that the initial semiconductor layer 1004 there is completely removed.

[0101] The initial semiconductor layer 1004 that is continuously distributed around the write word line 20 and the read word line 30 is disconnected to form a first semiconductor layer 104 and a second semiconductor layer 105 that are independent of each other. In step S622, a portion of the initial semiconductor layer 1004 is removed during the process of etching to form the first trench and the second trench, so that the first trench and the second trench expose the outer surface of the gate dielectric layer 22, including the upper surface, the lower surface and the side surface, so that the initial semiconductor layer 1004 is disconnected by the first trench and the second trench. After the first insulating structure 40 is formed in the first trench and the second insulating structure 50 is formed in the second trench, the first semiconductor layers 104 adjacent to each other along the oy direction are insulated from each other via the first insulating structure 40 or the second insulating structure 50, and the second semiconductor layers 105 adjacent to each other along the oy direction are insulated from each other via the first insulating structure 40 or the second insulating structure 50, thereby ensuring the independence, operational stability and reliability of the "2T0C" memory cell with respect to the external environment, and can effectively reduce the complexity of forming a three-dimensional stacked structure based on the "2T0C" memory cell while improving the storage density per unit volume of the three-dimensional stacked structure.

[0102] As an example, referring again to Figures 6a-6c, during the etching process to form the first and second trenches in step S622, the gate dielectric layer 22 is used as an etch stop layer to define the lengths of the first and second trenches along the ox direction. The lengths of the first and second trenches along the oy direction can be defined by controlling the etching rate and time, thereby defining the length of a single memory cell along the oy direction based on the spacing between the first and second trenches along the oy direction. In step S624, a deposition process can be used to form a first insulating structure 40 within the first trench and a second insulating structure 50 within the second trench. The material of the first insulating structure 40 is selected from silicon oxide, silicon nitride, silicon oxynitride, silicon carbide nitride, and combinations thereof; the material of the second insulating structure 50 is selected from silicon oxide, silicon nitride, silicon oxynitride, silicon carbide nitride, and combinations thereof. The material of the first insulating structure 40 can be the same as that of the second insulating structure 50. The first and second trenches can be connected, in which case the first and second insulating structures 40 and 50 can be formed in a single filling process.

[0103] Although the shapes and volumes of the first insulating structure 40 and the second insulating structure 50 in the drawings provided in this disclosure are substantially the same, the shapes and volumes of the first insulating structure 40 and the second insulating structure 50 may be different, and the shapes and volumes of the first insulating structure 40 and the second insulating structure 50 are not limited to those shown in the drawings. The first insulating structure 40 and the second insulating structure 50 are used to jointly define the shape and volume of a single memory cell, thereby making the layout of a single memory cell more compact and smaller in size. Under the same or similar inventive concepts as the present application, equivalent / equivalent modifications to the shape and volume of the first insulating structure 40 and / or the second insulating structure 50 shall fall within the scope of protection of the present application.

[0104] Please note that for the sake of simplicity of the specification, in the structural diagrams given in the embodiments below, unless the corresponding cross-sectional structural diagrams are given separately, other structural diagrams from different perspectives of structures related to the inventive points of the embodiments of the present disclosure can be referenced to each other.

[0105] As an example, please continue to refer to Figures 6a to 6c. The first insulating structure 40 includes a first horizontal portion 41 extending along a first direction (for example, the ox direction), a second horizontal portion 42, and a first vertical portion 43 extending along a second direction (for example, the oy direction); the first vertical portion 43 has a first end and a second end opposite to each other along the oy direction, and the first end is connected to an end of the first horizontal portion 41 away from the write line 20 along the ox direction to form a bending portion. The first vertical portion 43 is used to isolate the write transistor and the read line that are subsequently prepared and located on opposite sides of it along the ox direction.

[0106] As an example, please continue to refer to Figures 6a to 6c. The second insulating structure 50 includes a third horizontal portion 51 and a fourth horizontal portion 52 extending along a first direction (for example, the ox direction), and a second vertical portion 53 extending along a second direction (for example, the oy direction); the second vertical portion 53 has a first end and a second end opposite to each other along the oy direction, the first end of the second vertical portion 53 is connected to an end of the third horizontal portion 51 away from the write word line 20 along the ox direction to form a bend, and the second end of the second vertical portion 53 is connected to an end of the fourth horizontal portion 52 away from the read word line 30 along the ox direction to form a bend. The bend ensures that the write bit line 60, write transistor 70, read bit line 90, read transistor 101, and reference line 102 are all located within the area enclosed by the write word line 20 and read word line 30 spaced apart along the ox direction, and the first insulating structure 40 and second insulating structure 50 spaced apart along the oy direction. This ensures the independence of the "2T0C" memory cell from the external environment, operational stability, and reliability, effectively reducing the complexity of forming a three-dimensional stacked structure based on the "2T0C" memory cell while increasing the storage density per unit volume of the three-dimensional stacked structure.

[0107] As an example, referring to Figures 7a-8, a first insulating structure 40 extends simultaneously from the gate dielectric layer of the write transistor 70 to the gate dielectric layer of the read transistor 101, thereby simultaneously disconnecting the semiconductor layers of the two transistors between adjacent memory cells on a word line. The first insulating structure 40 has a bend extending along a second direction (e.g., the oy direction). The second semiconductor layer 105 has two opposing main surfaces, which are a first side and a second side of the second semiconductor layer 105, respectively. The first side of the second semiconductor layer 105 faces away from the write word line 20, and the second side of the second semiconductor layer 105 faces the write word line 20. The second semiconductor layer 105 includes a source contact region and a drain contact region of the write transistor 70 spaced apart on the first side, as well as a channel region located between the source contact region and the drain contact region. After forming the first insulating structure 40 and the second insulating structure 50 in step S624, the following steps are further included:

[0108] Step S632 : etching the sub-stack structure 1010 in a direction perpendicular to the substrate (eg, oz direction) to obtain a first sub-via 7011 exposing a portion of the substrate 10 and located in the area enclosed by the first insulating structure 40 and the write word line 20 ;

[0109] Step S634: etching the sacrificial layer 11 along the first direction and the second direction through the first sub-through hole 7011 to obtain a first accommodating groove 701 for defining the channel length of the write transistor 70; a portion of the side surface of the second semiconductor layer 105 exposed by the first accommodating groove 701 is used to form a channel region of the write transistor 70;

[0110] Step S636 : forming an isolation layer 71 in the first receiving groove 701 to form write transistors 70 that are insulated from each other along a direction perpendicular to the substrate.

[0111] As an example, referring to Figures 7a to 8, in step S632, a dry etching process can be used to etch the sub-stack structure 1010 along the oz direction to obtain a first sub-through hole 7011 that exposes a portion of the substrate 10 and is located between the first vertical portion 43 and the write word line 20; in step S634, a dry etching process and / or a wet etching process can be used to etch the sacrificial layer 11 along the first direction (for example, the ox direction) and the second direction (for example, the oy direction) through the first sub-through hole 7011, using the second semiconductor layer 105 as an etching stop layer to obtain a portion of the second semiconductor layer 105 exposed. A first accommodating recess 701 is formed on a portion of the side surface. The portion of the side surface of the second semiconductor layer 105 exposed by the first accommodating recess 701 is used to form a channel region of the write transistor 70. The length of the first accommodating recess 701 along the oy direction is used to define the channel length of the write transistor 70. Subsequently, an isolation layer 71 can be formed in the first accommodating recess 701 and the first sub-through hole 7011 using a deposition process to form a write transistor 70 that is mutually insulated along the oz direction. The top surface of the isolation layer 71 is then planarized to form an isolation layer 71 whose top surface is flush with the top surface of the sub-stack structure 1010. The material of the isolation layer 71 can be selected from silicon oxide, silicon nitride, silicon oxynitride, silicon carbide nitride, and the like, and combinations thereof. Because one major surface of the second semiconductor layer 105 used to form the write transistor 70 covers at least a portion of the upper surface, at least a portion of the lower surface, and at least a portion of the side surface of the write word line 20, and the source contact region, drain contact region, and channel region located between the source contact region and the drain contact region of the write transistor 70 are formed on the other major surface of the second semiconductor layer 105, the gate length of the write transistor 70 is L, and the gate width is t+2W. This effectively increases the gate width without increasing the volume of the write transistor 70, thereby significantly improving the performance of the write transistor 70. Because the initial semiconductor layer used to form the second semiconductor layer 105 is formed on the surface of the write word line 20 during the process of preparing the write word line 20, the process complexity and cost of preparing the write transistor 70 are effectively reduced.

[0112] As an example, referring to FIG. 9 a - FIG. 11 b , the first semiconductor layer 104 has two opposing main surfaces, which are a first side and a second side of the first semiconductor layer 104 , respectively. The first side of the first semiconductor layer 104 faces away from the read word line 30 , and the second side of the first semiconductor layer 104 faces the read word line 30 . The first semiconductor layer 104 includes a source contact region and a drain contact region of the read transistor 101 spaced apart on the first side, and a channel region located between the source contact region and the drain contact region. After forming the isolation layer in the first accommodating recess 701 in step S636 , the following steps are further included:

[0113] Step S642 : etching the sub-stack structure 1010 in a direction perpendicular to the substrate (eg, oz direction) to obtain a second sub-through hole 10111 exposing a portion of the substrate 10 and located between the bent portion of the first insulating structure 40 and the first semiconductor layer 104 ;

[0114] Step S644: etching the sacrificial layer 11 along the first direction and the second direction through the second sub-through hole 10111 to obtain a second accommodating groove 1011 for defining the channel length of the read transistor 101; a portion of the side surface of the first semiconductor layer 104 exposed by the second accommodating groove 1011 is used to form a channel region of the read transistor 101;

[0115] Step S646 : forming a gate dielectric layer 22 and a gate conductive layer 21 in sequence in the second accommodating recess 1011 to obtain a second sub-through hole 10111 , wherein the gate dielectric layer 22 covers the inner wall of the second sub-through hole 10111 ;

[0116] Step S648 : forming an insulating layer 23 in the second sub-through hole 10111 to form a back gate 1012 insulated from each other in a direction perpendicular to the substrate. The insulating layer 23 , the gate conductive layer 21 and the gate dielectric layer 22 are used to jointly form the back gate 1012 .

[0117] As an example, please refer to Figures 9a-11b. In step S642, a dry etching process can be used to etch the sub-stack structure 1010 along the oz direction to obtain a second sub-through hole 10111 that exposes a portion of the substrate 10 and is located between the second end of the first vertical portion 43 and the read word line 30; in step S644, a dry etching process and / or a wet etching process can be used to etch the sacrificial layer 11 along the first direction (for example, the ox direction) and the second direction (for example, the oy direction) through the second sub-through hole 10111 to obtain a second accommodating groove 1011 that exposes a portion of the side surface of the first semiconductor layer 104. The portion of the side surface of the first semiconductor layer 104 exposed by the second accommodating groove 1011 is used to form a channel region of the read transistor 101. The length of the second accommodating groove 1011 along the oy direction is used to define the channel length of the read transistor 101. The second sub-through hole 10111 and the second accommodating groove 1011 are used to jointly constitute a first through hole. In step S646, at least one of an in-situ steam generation (ISSG) process, an atomic layer deposition (ALD) process, a plasma vapor deposition (PVM) process, and a rapid thermal oxidation (RTO) process may be used to form a gate dielectric layer 22 on the inner surface of the second accommodating recess 1011. In step S646, a deposition process may be used to form a gate conductive layer 21 in the second accommodating recess 1011, at least filling the second accommodating recess 1011 and the second sub-through hole 10111. Then, the portion of the gate conductive layer 21 located in the second sub-through hole 10111 may be etched and removed along the oz direction. In step S648, an insulating layer 23 may be formed in the second sub-through hole 10111 by a deposition process to form a back gate 1012 that is insulated from each other along the oz direction. The insulating layer 23, the gate conductive layer 21, and the gate dielectric layer 22 are used to collectively form the back gate 1012. Since the fabrication of different read transistors 101 in the stacked structure is completed simultaneously in the same process step, the complexity of the process fabrication is effectively reduced. Since the gate dielectric layer 22 of the back gate 1012 circumferentially surrounds the gate conductive layer 21 of the back gate 1012, the on-resistance of the read transistor 101 can be reduced while ensuring that the performance of the read transistor 101 is not reduced. In addition, the side surface of the back gate 1012 near the write word line 20 along the ox direction can be electrically connected to the storage node (SN), the side surface of the back gate 1012 near the read word line 30 along the ox direction is used to electrically connect to the channel region of the read transistor 101, the side surface of the back gate 1012 near the first insulating structure 40 along the oy direction is used to electrically connect to the read bit line 90, and the side surface of the back gate 1012 near the second insulating structure 50 along the oy direction is used to electrically connect to the reference line 102, which can effectively reduce the volume of the "2T0C" memory cell.

[0118] As an example, referring to FIG. 12 a to FIG. 14 b , after forming the insulating layer 23 in the second sub-through hole 10111 in step S648 , the process further includes:

[0119] Step S652 : etching the sub-stack structure 1010 in a direction perpendicular to the substrate to obtain a third sub-through hole 8011 exposing a portion of the substrate 10 and located within the area enclosed by the second insulating structure 50 , the back gate 1012 , the first insulating structure 40 and the second semiconductor layer 105 ;

[0120] Step S654 : etching the sacrificial layer 11 along the first direction and the second direction through the third sub-through hole 8011 to obtain a third accommodating groove 801 exposing the source contact region of the write transistor 70 and the gate conductive layer 21 of the back gate 1012 ;

[0121] Step S656: forming a conductive layer 82 in the third receiving groove 801 to obtain a third sub-through hole 8011;

[0122] Step S658 : forming an insulating layer in the third sub-through hole 8011 .

[0123] As an example, referring to Figures 12a-14b, the top view schematic diagram shown in Figure 14a partially transparently displays the film layer directly above the top gate dielectric layer 22 to illustrate the shape and position of the back gate 1012 in the top view schematic diagram. In step S652, a dry etching process can be used to etch the sub-stack structure 1010 along the oz direction to form a third sub-via 8011 that exposes a portion of the substrate 10 and is located between the second end of the first vertical portion 43 and the third horizontal portion 51, and between the read transistor 101 and the write word line 20. In step S654, a dry etching process and / or a wet etching process can be used to etch the sacrificial layer 11 along the ox and oy directions through the third sub-via 8011 to form a third accommodating recess 801 that exposes the source contact region of the write transistor 70 and the gate conductive layer 21 of the back gate 1012. The third sub-via 8011 and the third accommodating recess 801 together constitute a second through-hole. In step S656, a deposition process can be used to form a conductive layer 82 within the third accommodating recess 801 and the third sub-through hole 8011. The top surface of the conductive layer 82 is then planarized to obtain a conductive layer 82 whose top surface is flush with the top surface of the sub-stack structure 1010. In step S656, a dry etching process can be used to etch and remove the portion of the conductive layer 82 located within the third sub-through hole 8011 along the oz direction. In step S658, a deposition process can be used to form an insulating layer within the third sub-through hole 8011 to form a storage node that is mutually insulated along the oz direction. The equipotential point between the source contact region of the write transistor 70 and the back gate 1012 is used to jointly constitute the storage node (SN). The material of the conductive layer 82 can be selected from doped polysilicon, copper, tungsten, aluminum, copper alloy, and combinations thereof. The material of the insulating layer can be selected from silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, and combinations thereof. The channel region of the read transistor 101, the first through hole, the second through hole and the source contact region of the write transistor 70 all cover at least one straight line parallel to the ox direction, so as to reduce the volume of the “2T0C” memory cell.

[0124] As an example, referring to FIG. 15 a to FIG. 16 , in step S60 , forming a plurality of memory cells stacked in a direction perpendicular to the substrate on the substrate based on the stacked structure may include:

[0125] Step S662 : forming a fifth sub-through hole 901 in the area enclosed by the bent portion of the first insulating structure 40 and the first semiconductor layer 104 , wherein the fifth sub-through hole 901 exposes the drain contact region of the read transistor 101 ;

[0126] Step S664 : forming a read bit line 90 in the fifth sub-via 901 .

[0127] As an example, referring to Figures 15a-16, in step S662, a dry etching process can be used to etch the sub-stack structure 1010 along the oz direction, forming a first initial sub-via (not shown) that exposes a portion of the substrate 10 and is located between the second horizontal portion 42 and the read transistor 101, and between the first vertical portion 43 and the read word line 30. In step S662, a dry etching process and / or a wet etching process can be used to etch the sacrificial layer 11 along the ox and oy directions through the first initial sub-via, forming a fifth sub-via 901 that exposes a portion of the first semiconductor layer 104. In step S466, a deposition process can be used to form the read bit line 90 within the fifth sub-via 901. A cross-section of the read bit line 90 parallel to the oz and ox directions includes several "T" shapes. The read bit line 90 includes multiple main portions extending along the oz direction and branches extending from the sidewalls of the main portions toward the read transistor. The material of the read bit line 90 may be selected from copper, tungsten, aluminum, copper alloys, and combinations thereof.

[0128] As an example, referring to FIG. 17 a to FIG. 18 , the second insulating structure 50 has a bent portion extending along the second direction (eg, the oy direction) and away from the insulating layer; after forming the insulating layer in the third sub-through hole 8011 in step S658, the method further includes:

[0129] Step S672 : forming a fourth sub-through hole 1021 in the area enclosed by the bent portion of the second insulating structure 50 and the first semiconductor layer 104 , wherein the fourth sub-through hole 1021 exposes the source contact region of the read transistor 101 ;

[0130] Step S674 : forming a reference line 102 in the fourth sub-through hole 1021 .

[0131] As an example, referring again to Figures 17a-18, in step S672, a dry etching process can be used to etch the sub-stack structure 1010 along the oz direction, forming a second initial sub-via (not shown) that exposes a portion of the substrate 10 and is located between the fourth horizontal portion 52 and the channel region of the read transistor 101, and between the second vertical portion 53 and the read word line 30. In step S674, a dry etching process and / or a wet etching process can be used to etch the sacrificial layer 11 along the ox and oy directions through the second initial sub-via, forming a fourth sub-via 1021 that exposes the source contact region of the read transistor 101. In step S674, a deposition process can be used to form a reference line 102 within the fourth sub-via 1021. The reference line 102 is connected to the source contact region of the read transistor 101. Reference line 102 can be a ground line. A cross-section of reference line 102 parallel to the oz and ox directions includes several "T" shapes. The reference line 102 includes a plurality of main portions extending along the oz direction and branches extending from the sidewalls of the main portions toward the read transistor. The material of the reference line 102 can be selected from conductive metal, metal silicide, doped polysilicon, and combinations thereof.

[0132] As an example, referring to FIG. 19 a to FIG. 21 e , in step S60 , a storage structure arranged in an array is formed on the substrate 10 based on the sub-stack structure 1010 , and further includes:

[0133] Step S682 : forming a sixth sub-through hole 601 in the enclosed area between the bent portion of the first insulating structure 40 and the second semiconductor layer 105 , wherein the sixth sub-through hole 601 exposes the drain contact region of the write transistor 70 ;

[0134] Step S684 : forming a write bit line 60 in the sixth sub-through hole 601 .

[0135] As an example, referring again to Figures 19a-21e, in step S682, a dry etching process can be used to etch the sub-stack structure 1010 along the oz direction, forming a third initial sub-via (not shown) that exposes a portion of the substrate 10 and is located between the first horizontal portion 41 and the channel region of the write transistor 70, and between the first vertical portion 43 and the write word line 20. In step S683, a dry etching process and / or a wet etching process can be used to etch the sacrificial layer 11 along the ox and oy directions through the third initial sub-via, forming a sixth sub-via 601 that exposes the drain contact region of the write transistor 70. In step S684, a deposition process can be used to form the write bit line 60 within the sixth sub-via 601. A cross-section of the write bit line 60 parallel to the oz and ox directions includes several "T" shapes. The write bit line 60 includes multiple main portions extending along the oz direction and branches extending from the sidewalls of the main portions toward the write transistor. The material of the write bit line 60 may be selected from copper, tungsten, aluminum, copper alloys, and combinations thereof.

[0136] It should be understood that although the steps in FIG1 and the process steps described above are shown in sequence according to arrows or step sequence indications, these steps are not necessarily executed in the order indicated by the arrows. Unless otherwise specified herein, there is no strict order restriction on the execution of these steps, and these steps can be executed in other orders. Moreover, at least a portion of the steps in FIG1 and the process steps described above may include multiple steps or multiple stages, and these steps or stages are not necessarily executed at the same time, but can be executed at different times. The order of execution of these steps or stages is not necessarily sequential, but can be executed in turn or alternately with other steps or at least a portion of steps or stages in other steps.

[0137] The order of preparing the write bit line, write transistor, storage node, read bit line, read transistor, and reference line in the foregoing embodiments can be arbitrarily swapped or combined. For example, the first sub-via and the second sub-via can be prepared in the same process step, and the fourth sub-via, the fifth sub-via, and the sixth sub-via can also be prepared in the same process step. Therefore, those skilled in the art, without inventive effort, can combine and / or swap the preparation processes of any number of the write bit line, write transistor, storage node, read bit line, read transistor, and reference line, and all of these should fall within the scope of protection of the embodiments of the present disclosure.

[0138] In some embodiments, please continue to refer to Figures 20 to 21e, which provide a memory including a substrate 10 and a plurality of memory cells 100 stacked along a thickness direction perpendicular to the surface of the substrate 10; the memory cell 100 includes a write word line 20, a write transistor 70, a read transistor 101, and a read word line 30 sequentially distributed along a first direction, and a write bit line 60 and a read bit line 90 located between the write word line 20 and the read word line 30; the write word line 20 and the read word line 30 are both extended along a second direction parallel to the surface of the substrate 10. The first direction and the second direction intersect each other.

[0139] The memory in the above embodiment is configured such that the write word line 20 and the read word line 30 are spaced apart along a first direction, such as the ox direction, and both extend along a second direction, such as the oy direction, parallel to the surface of the substrate 10. The source contact region, the drain contact region, and the channel region between the source contact region and the drain contact region of the write transistor 70 and the read transistor 101 located between the write word line 20 and the read word line 30 are sequentially distributed along the oy direction. The write bit line 60 and the read bit line 90 located between the write word line 20 and the read word line 30 are both extended along a direction perpendicular to the substrate, such as the oz direction. This is completely different from the technical solution in the related art that "both the word line and the bit line extend along a direction parallel to the surface of the substrate 10". This facilitates the formation of a memory array with the memory cell arranged three-dimensionally along the first direction, the second direction, and the thickness direction. Since two columns of memory cells adjacent to each other along the first direction in the memory array can share a common read bit line / common The write bit line can simultaneously access the write word line 20 adjacent to the first direction or the read word line 30 adjacent to the first direction, thereby proposing a storage cell 100 in which the word line extension direction is parallel to the surface of the substrate 10 and the bit line extension direction is perpendicular to the surface of the substrate 10, overcoming the technical prejudice that "the number of bytes accessed each time depends on the number of storage cells sharing a word line", effectively improving the bandwidth of each data access, thereby improving the data transmission rate of the manufactured product; and the storage cell 100 can provide an electrical signal to the storage node SN via the write bit line 60 and the write transistor 70 when the write transistor 70 is turned on to realize writing data; and form a storage data readout path including the read word line 30, the read bit line 90 and the read transistor 101, so as to use the storage data readout path to obtain the relative size of the output electrical signal value, and realize reading data via the storage data readout path. Therefore, the embodiment of the present disclosure uses two transistors to realize the writing and reading of storage data without the aid of a capacitor structure. It can reduce the volume of the manufactured product while ensuring that the storage capacity is not reduced, improve the storage density and integration of the memory, effectively reduce the process difficulty and manufacturing cost of the memory, and improve the performance and reliability of the manufactured memory.

[0140] In some embodiments, please continue to refer to Figures 20-21e. The back gate 1012 includes a gate conductive layer 21 and a gate dielectric layer 22, and a dielectric layer 12 is arranged between any two adjacent memory cells stacked in the direction perpendicular to the substrate; the memory includes: at least one first through hole between the write word line 20 and the read word line 30 and passing through each memory cell. The embodiment of the present application takes a first through hole as an example.

[0141] A gate dielectric layer 22 and a gate conductive layer 21 are sequentially arranged on the side walls of the first through hole; wherein, the gate conductive layers 21 corresponding to different layers of storage cells are insulated from each other by a dielectric layer 12; the area of ​​the gate conductive layer 21 in the first through hole close to the write transistor 70 is connected to the corresponding source contact area, and the area close to the read transistor 101 is connected to the channel area of ​​the read transistor 70 through the gate dielectric layer 22.

[0142] In some embodiments, referring to FIG. 20 to FIG. 21 e , an opening is provided in a region of the gate dielectric layer 22 near the write transistor 70 , and the gate conductive layer 21 is electrically connected to the corresponding write transistor 70 in the opening region.

[0143] In some embodiments, please continue to refer to FIG. 20 to FIG. 21 e , the gate conductive layer 21 in at least one first through hole surrounds the sidewall of the first through hole.

[0144] In some embodiments, please continue to refer to Figures 20-21e. The aperture of the area of ​​the gate conductive layer 21 corresponding to the first through hole is larger than the aperture of the area near the two end areas of the gate conductive layer 21, and the gate dielectric layer 22 forms an adaptive structure according to the shape of the first through hole.

[0145] In some embodiments, referring to Figures 20-21e, the gate conductive layer 21 is located between the write word line 20 and the channel region of the read transistor 101. Adjacent gate conductive layers 21 are insulated from each other along a direction perpendicular to the substrate, such as the oz direction. The gate conductive layer 21 includes a first surface close to the substrate 10 along the oz direction, a second surface facing away from the substrate 10 along the oz direction, a third surface close to the channel region of the read transistor 101 along a second direction, such as the oy direction, and a fourth surface facing away from the channel region of the read transistor 101 along the oy direction. The fourth surface is electrically connected to the write transistor 70. The gate dielectric layer 22 includes a first surface covering the first surface of the gate conductive layer 21, a second surface covering the second surface of the gate conductive layer 21, and a third surface covering the third surface of the gate conductive layer 21. The third surface of the gate dielectric layer 22 is adjacent to the channel region of the read transistor 101. The adjacent gate dielectric layers 22 along the direction perpendicular to the substrate are insulated from each other. The insulating layer passes through the first surface of the gate conductive layer 21, the first surface of the gate dielectric layer 22, the second surface of the gate conductive layer 21, and the second surface of the gate dielectric layer 22 along the direction perpendicular to the substrate, and extends to the surface or interior of the substrate 10.

[0146] In some embodiments, please continue to refer to Figures 20-21e. The memory also includes a first semiconductor layer 104 extending along a second direction, such as the oy direction. The first semiconductor layer 104 has two opposite main surfaces, and the two opposite main surfaces are respectively a first side and a second side of the first semiconductor layer 104. The first side of the first semiconductor layer 104 is away from the read word line 30, and the second side of the first semiconductor layer 104 is toward the read word line 30. The first semiconductor layer 104 includes a source contact region, a drain contact region, and a channel region located between the source contact region and the drain contact region of the read transistor 101 spaced apart on the first side.

[0147] In some embodiments, referring again to Figures 20-21e, the first semiconductor layer 104 surrounds the sidewalls of the read word line 30 and is insulated from the read word line 30. The first side of the first semiconductor layer 104 includes an upper surface, a lower surface, and a side surface. The source contact region, channel region, and drain contact region of the read transistor 101 are at least partially located on the side surface and are sequentially arranged along the extension direction of the read word line 30. Since the gate length of the read transistor 101 is L and the gate width is t+2W, the gate width is effectively increased without increasing the size of the read transistor 101, thereby significantly improving the performance of the read transistor 101.

[0148] In some embodiments, referring again to Figures 20-21e, the memory device further includes a second through-hole proximate to the channel region of the write transistor and extending through each layer of memory cells, as well as multiple conductive layers 82 located on the sidewalls of the second through-hole. The conductive layers 82 corresponding to different layers of memory cells are insulated from each other by a dielectric layer 12. The second through-hole exposes the source contact region of the write transistor 70 and the gate conductive layer 21 of each layer of memory cells. Each conductive layer 82 is located on the sidewall of the second through-hole and forms a ring structure, which is connected to both the source contact region of the write transistor and the gate conductive layer 21 exposed within the second through-hole. For example, the conductive layer 82 is pore-shaped, and the pore-shaped conductive layer 82 is filled with an insulating layer. In another example, the insulating layer extends along the oz direction to the surface or interior of the substrate 10, located between the write word line 20 and the fourth surface of the gate conductive layer 21. The conductive layer 82 circumferentially surrounds the outer sidewalls of the insulating layer, and the fourth surface of the gate conductive layer 21 is electrically connected to the write transistor 70 via the conductive layer 82. The equipotential point between the source contact region of the write transistor 70 and the back gate 1012 collectively constitutes a storage node. The channel region of the read transistor 101, the first through hole, the second through hole and the source contact region of the write transistor 70 may be arranged to cover at least one straight line parallel to the first direction, such as the ox direction, to reduce the volume of the "2T0C" memory cell.

[0149] In some embodiments, referring again to Figures 20-21e, the memory device further includes a second semiconductor layer 105 extending along a second direction, such as the oy direction. The second semiconductor layer 105 has two opposing major surfaces, namely a first side and a second side of the second semiconductor layer 105. The first side of the second semiconductor layer 105 faces away from the write word line 20, while the second side of the second semiconductor layer 105 faces the write word line 20. The second semiconductor layer 105 includes a source contact region and a drain contact region for the write transistor 70 spaced apart on the first side, as well as a channel region located between the source contact region and the drain contact region. Because the second semiconductor layer 105 used to form the source contact region, the channel region, and the drain contact region of the write transistor 70 are fabricated during the fabrication of the write word line 20, the complexity of the fabrication process for the write transistor 70 is effectively reduced.

[0150] In some embodiments, referring again to Figures 20-21e, the second semiconductor layer 105 surrounds the sidewalls of the write wordline 20 and is insulated from the write wordline 20. The first side of the second semiconductor layer 105 includes an upper surface, a lower surface, and a side surface. The source contact region, channel region, and drain contact region of the write transistor 70 are at least partially located on the side surface. Because the gate length of the write transistor 70 is L and the gate width is t+2W, the gate width is effectively increased without increasing the size of the write transistor 70, thereby significantly improving the performance of the write transistor 70.

[0151] In some embodiments, referring again to Figures 20-21e, the memory device further includes a reference line 102, which extends perpendicular to the substrate, through each memory cell, and connects to the read transistor 101 of each memory cell. For example, the reference line 102 extends along the oz direction to the surface or interior of the substrate 10. The read bit line 90, the read transistor 101, and the reference line 102 are sequentially arranged along a second direction, such as the oy direction. It is clear that the positions of the reference line 102 and the read bit line 90 are interchangeable. The reference line 102 may include multiple main portions extending along the oz direction, and branches extending from the sidewalls of the main portions toward the read transistor 101. The reference line 102 may be a ground line.

[0152] In some embodiments, referring again to Figures 20-21e, write bit line 60 and read bit line 90 are located on the same side of back gate 1012 along a second direction, such as the oy direction. For example, write bit line 60 and read bit line 90 are located on the same side of read transistor 101 along the second direction, such as the oy direction, away from reference line 102. Write bit line 60 and read bit line 90 are spaced apart and insulated from each other in the oy direction. Read bit line 90 and write transistor 70 are spaced apart and insulated from each other in the first direction (e.g., the ox direction). This reduces the size of the memory cell while satisfying various layout scenarios, thereby increasing the integration of memory cells in the memory and reducing fabrication complexity and cost.

[0153] In some embodiments, referring again to Figures 20-21e, write word lines 20 connect different memory cells arranged in the second direction on the same layer, and write bit lines 60 and read bit lines 90 respectively connect write transistors 70 and read transistors 101 in the vertically stacked memory cells. For example, the memory device further includes functional layers and dielectric layers stacked alternately in a direction perpendicular to the substrate, such as the oz direction, on substrate 10. The functional layers include a plurality of memory cells 100 spaced apart along a first direction, such as the ox direction, and / or a plurality of memory cells 100 spaced apart along a second direction, such as the oy direction. In the same functional layer, adjacent memory cells 100 along the oy direction share the same write word line 20 extending in the oy direction and the same read word line 30 extending in the oy direction. In different functional layers, adjacent memory cells 100 along a direction perpendicular to the substrate, such as the oz direction, share the same write bit line 60 extending in the oz direction and the same read bit line 90 extending in the oz direction.

[0154] 20-21e , in some embodiments, the write bit line 60 includes a plurality of main portions extending along the oz direction, and branches extending from sidewalls of the main portions toward the write transistor 70. A cross section of the write bit line 60 parallel to the thickness direction, such as the oz direction, and the first direction, such as the ox direction, includes a plurality of "T" shapes.

[0155] 20-21e , read bit line 90 includes a plurality of main portions extending along the oz direction and branches extending from sidewalls of the main portions toward read transistor 101. A cross section of read bit line 90 parallel to the thickness direction, such as the oz direction, and the first direction, such as the ox direction, includes a plurality of T-shaped sections.

[0156] In some embodiments, please continue to refer to Figures 20-21e and Figures 22-23, the memory also includes a common write bit line and / or a common read bit line; the write bit lines 60 of the memory cells 100 adjacent along the first direction are all connected to the same common write bit line; the read bit lines 90 of the memory cells 100 adjacent along the first direction, such as the ox direction, are all connected to the same common read bit line; the write bit lines 60 of the memory cells 100 adjacent along the second direction, such as the oy direction, are connected to different common write bit lines; the read bit lines 90 of the memory cells 100 adjacent along the second direction, such as the oy direction, are connected to different common read bit lines.

[0157] In some embodiments, please continue to refer to Figures 22-23, the common write bit line and / or the common read bit line both extend along a first direction (e.g., ox direction) and are located on the same side of the functional layer away from the substrate 10 along a direction perpendicular to the substrate, such as oz direction.

[0158] In some embodiments, an electronic device is provided, comprising a memory as described in any of the embodiments of the present disclosure. The electronic device may be, for example, but not limited to, a suitable type of electronic product, such as a consumer electronic product, a home electronic product, a vehicle-mounted electronic product, or a financial terminal product. Consumer electronic products include mobile phones, tablet computers, laptop computers, desktop monitors, all-in-one computers, and the like. Home electronic products include smart door locks, televisions, refrigerators, wearable devices, and the like. Vehicle-mounted electronic products include vehicle-mounted navigation systems and vehicle-mounted DVD players. Financial terminal products include ATMs and self-service terminals.

[0159] In some embodiments, please refer to Figure 22, which provides a storage cell circuit 200, including a write word line 20, a read word line 30, a write transistor 70 and a read transistor 101, the write transistor 70 is configured as follows: the first end is electrically connected to the write bit line 60, the control end is electrically connected to the write word line 20, and the second end is electrically connected to the storage node SN; the read transistor 101 is configured as follows: the first end is electrically connected to the read bit line 90, the first control end is electrically connected to the storage node SN, the second control end is electrically connected to the read word line 30, and the second end is electrically connected to the reference line 102; wherein, when the write word line 20 controls the write transistor 70 to be turned on, data is written to the storage node SN by providing a write signal to the write bit line 60; when the write transistor 70 is turned off, the conduction characteristics of the read transistor 101 are controlled by the read word line 30, and the data is read out through the amplitude of the electrical signal obtained from the read bit line 90.

[0160] In the memory circuit 200 of the above embodiment, when the write transistor 70 is turned on by the write word line 20, data is written to the storage node SN by providing a write signal to the write bit line 60. When the write transistor 70 is turned off, the conduction characteristics of the read transistor 101 are controlled by the read word line 30, and the data is read via the amplitude of the electrical signal obtained from the read bit line 90. For example, if the conduction characteristics of the read transistor 101 are good, the amplitude of the electrical signal (e.g., voltage signal or current signal) obtained via the read bit line 90 is relatively large, and the read data is determined to be "1". Conversely, if the conduction characteristics of the read transistor 101 are poor, the amplitude of the electrical signal obtained via the read bit line 90 is relatively small, and the read data is determined to be "0". Since the writing and reading of stored data are achieved by using two transistors without the aid of a capacitor structure, the spatial volume generated by the capacitor structure can be avoided while ensuring that the storage capacity per unit volume is not reduced, thereby improving the storage density of the memory cell while improving the performance and reliability of the memory cell.

[0161] In some embodiments, referring to FIG. 22 , the write transistor 70 and the read transistor 101 may be N-type transistors. The write transistor 70 and the read transistor 101 may also be P-type transistors. The write transistor 70 and the read transistor 101 may be the same type of transistors or different types of transistors.

[0162] As an example, referring to FIG. 22 and FIG. 23 , a memory array circuit 300 is provided, including memory cell circuits 200 arranged in an array, as described in any of the embodiments of the present disclosure; wherein the write word line includes a write word line WWLxy, the read word line includes a read word line RWLxy, the write bit line includes a write bit line WBLxy, and the read bit line includes a read bit line RBLxy, where x∈[0,2]. Memory cell circuits 200 adjacent along a second direction (e.g., the oy direction) share the write word line and the read word line; and memory cell circuits 200 adjacent along the thickness direction of the write word line 20 (e.g., the oz direction) share the write bit line and the read bit line, thereby reducing the complexity of the circuit structure of the memory array circuit 300, lowering wiring costs, and improving the performance and reliability of the memory array circuit 300.

[0163] As an example, referring to FIG. 23 , the write word lines of the memory cell circuits 200 adjacent to each other along a first direction (eg, ox direction) are enabled at different times, thereby avoiding operation conflicts between the memory cell circuits 200 adjacent to each other along the ox direction.

[0164] As an example, please refer to Figure 23, the write bit lines of the memory cell circuits 200 adjacent along the first direction (for example, the ox direction) are all connected to a common write bit line; the read bit lines of the memory cell circuits 200 adjacent along the ox direction are all connected to a common read bit line; the memory cell circuits 200 adjacent along the second direction (for example, the oy direction) are connected to different common write bit lines / common read bit lines, which is convenient for simplifying the complexity of peripheral circuit wiring while improving the efficiency of data transmission of semiconductor devices.

[0165] As an example, please continue to refer to Figures 22 and 23. A method for reading and writing a memory cell circuit 200 is provided. The memory cell circuit 200 includes a write word line 20, a read word line 30, a write transistor 70, and a read transistor 101. The write transistor 70 is configured such that: a first terminal is electrically connected to the write bit line 60, a control terminal is electrically connected to the write word line 20, and a second terminal is electrically connected to the storage node SN; the read transistor 101 is configured such that: a first terminal is electrically connected to the read bit line 90, a first control terminal is electrically connected to the storage node SN, a second control terminal is electrically connected to the read word line 30, and a second terminal is electrically connected to the reference line 102. The method for reading and writing the memory cell circuit 200 includes:

[0166] When the write word line 20 controls the write transistor 70 to be turned on, a write signal is provided to the write bit line 60 to write data to the storage node SN;

[0167] When the write transistor 70 is turned off, the conduction characteristics of the read transistor 101 are controlled by the read word line 30 , an electrical signal is obtained via the read bit line 90 , and read data is obtained according to the amplitude of the electrical signal.

[0168] As an example, referring again to Figures 22 and 23, when write word line WWL00 is selected, if the write transistor of the memory cell circuit 200 electrically connected thereto is turned on via write word line WWL00, data can be written to the adjacent storage node via write bit line WBL0y (y∈[0,2]). When read word line RWL00 is selected, if the conduction characteristics of the read transistor of the memory cell circuit 200 electrically connected thereto are controlled via read word line RWL00, data can be read from the adjacent storage node via read bit line RBL0y (y∈[0,2]). When the write transistor in memory cell circuit 200 is turned off, the conduction characteristics of the read transistor are controlled by the read word line, and data is read based on the amplitude of the electrical signal obtained from the adjacent read bit line. For example, if the amplitude of the electrical signal (e.g., voltage signal or current signal) obtained via the read bit line is relatively large, the read data is determined to be "1", and if the amplitude of the electrical signal obtained via read bit line 90 is relatively small, the read data is determined to be "0". Since the writing and reading of storage data can be achieved by using two transistors without the aid of a capacitor structure, the storage capacity per unit volume can be ensured not to be reduced while avoiding the generation of spatial volume by the capacitor structure, thereby improving the storage density of the storage unit while improving the performance and reliability of the storage unit.

[0169] As an example, referring to FIG. 22 and FIG. 23 , a method for reading and writing a memory array circuit 300 is provided. The memory array circuit 300 includes memory cell circuits 200 described in any of the disclosed embodiments arranged in an array along a first direction, a second direction, and a third direction. Adjacent memory cell circuits 200 along the first direction share a write word line 20 and a read word line 30. Adjacent memory cell circuits 200 along the third direction share a write bit line 60 and a read bit line 90. The third direction is perpendicular to the first direction and the second direction, and the first and second directions intersect. The method for reading and writing the memory array circuit 300 includes:

[0170] When the selected write word line 20 controls the write transistor 70 to be turned on, a write signal is provided to the write bit line 60 adjacent to the write transistor 70 to write data to the storage node SN adjacent to the write transistor 70;

[0171] When the write transistor 70 adjacent to the selected read bit line 90 is turned off, the conduction characteristics of the read transistor 101 adjacent to the selected read bit line 90 are controlled to obtain an electrical signal through the selected read bit line 90, and the read data is obtained according to the amplitude of the electrical signal; the selection moments of the write word lines 20 of the adjacent storage unit circuits 200 along the second direction are different.

[0172] As an example, referring to Figures 22 and 23, the write word line includes a write word line WWLxy, the read word line includes a read word line RWLxy, the write bit line includes a write bit line WBLxy, and the read bit line includes a read bit line RBLxy, where x∈[0,2]. Adjacent memory cell circuits 200 along a second direction (e.g., the oy direction) share the write word line and the read word line; and adjacent memory cell circuits 200 along the thickness direction of the write word line 20 (e.g., the oz direction) share the write bit line and the read bit line, thereby reducing the complexity of the circuit structure of the memory array circuit 300, lowering wiring costs, and improving the performance and reliability of the memory array circuit 300.

[0173] As an example, referring to Figures 22 and 23, when write word line WWL00 is selected, if the write transistor of the memory cell circuit 200 electrically connected thereto is controlled to be conductive via write word line WWL00, data can be written to the adjacent storage node via write bit line WBL0y (y∈[0,2]). When read word line RWL00 is selected, if the conductive characteristics of the read transistor of the memory cell circuit 200 electrically connected thereto are controlled via read word line RWL00, data can be read from the adjacent storage node via read bit line RBL0y (y∈[0,2]). When the write transistor in memory cell circuit 200 is turned off, data is read by controlling the conduction characteristics of the read transistor adjacent to the selected read bit line. For example, if the amplitude of the electrical signal (e.g., voltage or current) obtained via the read bit line is relatively large, the read data "1" is determined, while if the amplitude of the electrical signal obtained via read bit line 90 is relatively small, the read data "0" is determined. By utilizing two transistors to write and read stored data without resorting to a capacitor structure, the capacitor structure can be avoided from creating bulk while ensuring that the storage capacity per unit volume is not reduced. This improves the storage density of the memory cell while also enhancing the performance and reliability of the memory cell.

[0174] In some embodiments, a computer device is provided, including a memory and a processor. The memory stores a computer program, and when the processor executes the computer program, the steps of any one of the above-mentioned storage unit circuit reading and writing methods / storage array circuit reading and writing methods are implemented.

[0175] In some embodiments, a computer-readable storage medium is provided, on which a computer program is stored. When the computer program is executed by a processor, the steps of any one of the above-mentioned storage unit circuit reading and writing methods / storage array circuit reading and writing methods are implemented.

[0176] In some embodiments, a computer program product is provided, comprising a computer program, which, when executed by a processor, implements the steps of any one of the above-mentioned memory cell circuit reading and writing methods / memory array circuit reading and writing methods.

[0177] Those skilled in the art will appreciate that all or part of the processes in the above-mentioned embodiment methods can be implemented by instructing the relevant hardware through a computer program, and the computer program can be stored in a non-volatile computer-readable storage medium. When the computer program is executed, it can include the processes of the embodiments of the above-mentioned methods. Among them, any reference to memory, database or other media used in the embodiments provided in this application may include at least one of non-volatile and volatile memory. Non-volatile memory may include read-only memory (ROM), magnetic tape, floppy disk, flash memory, optical memory, high-density embedded non-volatile memory, resistive random access memory (ReRAM), magnetic random access memory (MRAM), ferroelectric random access memory (FRAM), phase change memory (PCM), graphene memory, etc. Volatile memory may include random access memory (RAM) or external cache memory, etc. As an illustration and not limitation, RAM can be in various forms, such as static random access memory (SRAM) or dynamic random access memory (DRAM). The database involved in each embodiment provided in this application may include at least one of a relational database and a non-relational database. Non-relational databases may include distributed databases based on blockchains, etc., but are not limited thereto. The processors involved in each embodiment provided in this application may be a general-purpose processor, a central processing unit, a graphics processing unit, a digital signal processor, a programmable logic device, a data processing logic device based on quantum computing, etc., but are not limited thereto. The technical features of the above embodiments can be combined arbitrarily. In order to make the description concise, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0178] Please note that the above embodiments are for illustrative purposes only and are not intended to limit the present disclosure.

[0179] The various embodiments in this specification are described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same or similar parts between the various embodiments can be referenced to each other.

[0180] The above embodiments merely illustrate several implementation methods of the present application. While the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the disclosed patent. It should be noted that a person skilled in the art could make numerous variations and improvements without departing from the spirit of the present application, all of which fall within the scope of protection of the present application.

Claims

1. A memory comprising a substrate, a write word line, a read word line, a write bit line, a read bit line, and a plurality of memory cells stacked in a direction perpendicular to the substrate; Each of the memory cells comprises a write transistor and a read transistor located between the write word line and the read word line and sequentially distributed along a first direction parallel to the substrate; The write bit line and the read bit line are located between the write word line and the read word line and are connected to the write transistor and the read transistor respectively; in, The write word line and the read word line both extend in a second direction parallel to the substrate; the write bit line and the read bit line both extend in a direction perpendicular to the substrate; The read transistor comprises a back gate and a first semiconductor layer extending along the second direction and surrounding the read word line, wherein the first semiconductor layer is sequentially provided with a source contact region, a drain contact region and a channel region located between the source contact region and the drain contact region in the second direction, and the back gate is located between the write word line and the read transistor; The write transistor comprises a second semiconductor layer extending along the second direction and surrounding the write word line, wherein the second semiconductor layer has a source contact region, a drain contact region, and a channel region between the source contact region and the drain contact region sequentially distributed in the second direction; The first direction intersects the second direction.

2. The memory according to claim 1, wherein: The back gate at least includes a gate conductive layer and a gate dielectric layer; The memory comprises: at least one first through hole between the write word line and the read word line and penetrating each of the memory cells, and the gate dielectric layer and the gate conductive layer sequentially arranged on the side walls of each of the first through holes; wherein the gate conductive layers corresponding to the memory cells in different layers are insulated from each other by a dielectric layer; the gate conductive layer in the first through hole is connected to the corresponding source contact region in an area close to the write transistor, and is connected to the read transistor in an area close to the read transistor through the gate dielectric layer.

3. The memory according to claim 2, wherein: An opening is provided on the gate dielectric layer in a region close to the write transistor, and the gate conductive layer is connected to the corresponding write transistor in the opening region.

4. The memory according to claim 2, wherein: The gate conductive layer in at least one first through hole surrounds a sidewall of the first through hole.

5. The memory according to claim 2, wherein: The first through hole corresponds to a region of the gate conductive layer, the aperture of the middle region close to the gate conductive layer is larger than the aperture of the two end regions close to the gate conductive layer, and the gate dielectric layer forms an adaptive structure according to the shape of the first through hole.

6. The memory according to any one of claims 1 to 5, wherein: The first semiconductor layer has two opposite main surfaces, which are respectively a first side and a second side of the first semiconductor layer, the first side faces away from the read word line, and the second side faces the read word line. The first semiconductor layer includes a source contact region and a drain contact region of the read transistor spaced apart on the first side, and a channel region located between the source contact region and the drain contact region.

7. The memory according to claim 6, wherein: The first semiconductor layer surrounds the side wall of the read word line and is insulated from the read word line; the first side of the first semiconductor layer includes an upper surface, a lower surface and a side surface, and the source contact area, the channel area and the drain contact area of ​​the read transistor are at least partially located on the side surface and are arranged in sequence along the extension direction of the read word line.

8. The memory according to any one of claims 2 to 5, wherein: It also includes a second through hole close to the channel region of the write transistor and penetrating each layer of storage cells, and a plurality of conductive layers located on the sidewalls of the second through hole, wherein the conductive layers corresponding to the storage cells in different layers are insulated from each other; The second through hole exposes the source contact region of the write transistor and the gate conductive layer of each layer of memory cells; Each of the conductive layers is located on the sidewall of the second through hole and forms an annular structure, and the annular structure is simultaneously connected to the source contact region of the write transistor and the gate conductive layer exposed in the second through hole.

9. The memory according to claim 8, wherein: The channel region of the read transistor, the first through hole, the second through hole, and the source contact region of the write transistor all cover at least one straight line parallel to the first direction.

10. The memory according to any one of claims 1 to 5, wherein: The second semiconductor layer has two opposite main surfaces, which are respectively a first side and a second side of the second semiconductor layer, the first side faces away from the write word line, and the second side faces the write word line. The second semiconductor layer includes a source contact region and a drain contact region of the write transistor spaced apart on the first side, and a channel region located between the source contact region and the drain contact region.

11. The memory according to claim 10, wherein: The second semiconductor layer surrounds the side wall of the write word line and is insulated from the write word line; the first side of the second semiconductor layer includes an upper surface, a lower surface and a side surface, and the source contact area, the channel area and the drain contact area of ​​the write transistor are at least partially located on the side surface and are arranged in sequence along the extension direction of the write word line.

12. The memory according to any one of claims 1 to 5, wherein: Also includes: A reference line extending in a direction perpendicular to the substrate, penetrating each memory cell and connected to a read transistor of each memory cell; The read bit line, the back gate and the reference line are arranged in sequence along the second direction.

13. The memory according to claim 11, wherein: The write bit line and the read bit line are located on the same side away from the back gate along the second direction.

14. An electronic device, comprising: A memory as claimed in any one of claims 1 to 13.

15. A method for preparing a memory, comprising: providing a substrate; forming a stacked structure on the substrate, the stacked structure comprising sacrificial layers and dielectric layers alternately stacked in sequence in a direction perpendicular to the substrate; Based on the stacked structure, a write word line, a read word line, a write bit line, a read bit line, and a plurality of memory cells stacked in a direction perpendicular to the substrate are formed on the substrate; each memory cell includes a write transistor and a read transistor located between the write word line and the read word line and sequentially distributed in a first direction parallel to the substrate; the write word line and the read word line both extend in a second direction parallel to the substrate; The write bit line and the read bit line both extend in a direction perpendicular to the substrate, and are both located between the write word line and the read word line and are connected to the write transistor and the read transistor respectively; the read transistor comprises a back gate and a first semiconductor layer extending in a second direction and surrounding the read word line, the first semiconductor layer having a source contact area, a drain contact area, and a channel area between the source contact area and the drain contact area sequentially distributed in the second direction, and the back gate is located between the write word line and the channel area of ​​the read transistor; the write transistor comprises a second semiconductor layer extending in the second direction and surrounding the write word line, the second semiconductor layer having a source contact area, a drain contact area, and a channel area between the source contact area and the drain contact area sequentially distributed in the second direction; the first direction intersects with the second direction.

16. The preparation method according to claim 15, wherein: The method comprises forming a write word line, a read word line, a write bit line, a read bit line and a plurality of storage cells stacked in a direction perpendicular to the substrate on the substrate based on the stacked structure, comprising: Making two isolation grooves extending along the second direction and penetrating the stacked structure on the stacked structure, the two isolation grooves respectively exposing the sacrificial layer and the dielectric layer on two oppositely disposed side walls of one stacked structure, and etching back the exposed sacrificial layer to form a first accommodating groove and a second accommodating groove on the two oppositely disposed side walls; An initial semiconductor layer, a gate dielectric layer and a word line material layer are sequentially formed on the inner wall of the first containing groove and the inner wall of the second containing groove, wherein the word line material layer in the first containing groove is used to form the write word line, and the word line material layer in the second containing groove is used to form the read word line; The initial semiconductor layer, gate dielectric layer and word line material layer in the isolation trench are removed, so that the semiconductor layer and word line of two adjacent storage units along the first direction are disconnected, forming the initial first semiconductor layers disconnected from each other in different layers, the initial second semiconductor layers disconnected from each other in different layers, the read word lines disconnected from each other in different layers, and the write word lines disconnected from each other in different layers.

17. The preparation method according to claim 16, wherein: After forming the write word line and the read word line, the method further includes: A first trench and a second trench extending along the first direction and spaced apart along the second direction are formed in the stacked structure to define the shape and position of a single memory cell, wherein the first trench and the second trench disconnect each of the initial first semiconductor layers and each of the initial second semiconductor layers, exposing a portion of the substrate and a portion of the outer surface of the gate dielectric layer on the word line material layer close to the sacrificial layer, so as to disconnect the second semiconductor layers between different memory cells connected to the same write word line and the first semiconductor layers between different memory cells connected to the same read word line; An insulating layer is filled in the first trench and the second trench to form a first insulating structure and a second insulating structure.

18. The preparation method according to claim 17, wherein: The first insulating structure has a bent portion extending along the second direction, the second semiconductor layer has two opposite main surfaces, the two opposite main surfaces are respectively a first side and a second side of the second semiconductor layer, the first side is away from the write word line, and the second side faces the write word line, and the second semiconductor layer includes a source contact region and a drain contact region of the write transistor spaced apart on the first side, and a channel region located between the source contact region and the drain contact region; After forming the first insulating structure and the second insulating structure, the method further includes: Etching the stacked structure in a direction perpendicular to the substrate to obtain a first sub-through hole exposing a portion of the substrate and located in a region enclosed by the first insulating structure and the write word line; The sacrificial layer is etched along the first direction and the second direction via the first sub-through hole to obtain a first accommodating groove for defining the channel length of the write transistor; a portion of the side surface of the second semiconductor layer exposed by the first accommodating groove is used to form a channel region of the write transistor; An isolation layer is formed in the first accommodating groove to form write transistors that are insulated from each other along a direction perpendicular to the substrate.

19. The preparation method according to claim 18, wherein: The first semiconductor layer has two opposite main surfaces, the two opposite main surfaces are respectively a first side and a second side of the first semiconductor layer, the first side is away from the read word line, and the second side faces the read word line, the first semiconductor layer includes a source contact region and a drain contact region of the read transistor spaced apart on the first side, and a channel region located between the source contact region and the drain contact region; After forming the isolation layer in the first accommodating groove, the method further includes: Etching the stacked structure in a direction perpendicular to the substrate to obtain a second sub-through hole exposing a portion of the substrate and located between the bent portion of the first insulating structure and the first semiconductor layer; The sacrificial layer is etched along the first direction and the second direction through the second sub-through hole to obtain a second accommodating groove for defining the channel length of the read transistor; a portion of the side surface of the first semiconductor layer exposed by the second accommodating groove is used to form a channel region of the read transistor; forming a gate dielectric layer and a gate conductive layer in sequence in the second accommodating groove to obtain the second sub-through hole, wherein the gate dielectric layer covers the inner wall of the second sub-through hole; An insulating layer is formed in the second sub-through hole to form a back gate that is insulated from each other in a direction perpendicular to the substrate. The insulating layer, the gate conductive layer and the gate dielectric layer are used to jointly form the back gate.

20. The preparation method according to claim 19, wherein: After forming the insulating layer in the second sub-through hole, the method further includes: Etching the stacked structure in a direction perpendicular to the substrate to obtain a third sub-through hole exposing a portion of the substrate and located in an area enclosed by the second insulating structure, the back gate, the first insulating structure and the second semiconductor layer; Etching the sacrificial layer along the first direction and the second direction through the third sub-through hole to obtain a third accommodating groove exposing the source contact region of the write transistor and the gate conductive layer of the back gate; forming a conductive layer in the third accommodating groove to obtain a third sub-through hole; forming an insulating layer in the third sub-through hole; forming a fourth sub-through hole in the enclosed area of ​​the bending portion of the second insulating structure and the first semiconductor layer, wherein the fourth sub-through hole exposes the source contact region of the read transistor; forming a reference line in the fourth sub-through hole; forming a fifth sub-through hole in the enclosed area of ​​the bending portion of the first insulating structure and the first semiconductor layer, wherein the fifth sub-through hole exposes the drain contact area of ​​the read transistor; forming the read bit line in the fifth sub-through hole; forming a sixth sub-through hole in the enclosed area of ​​the bending portion of the first insulating structure and the second semiconductor layer, wherein the sixth sub-through hole exposes the drain contact area of ​​the write transistor; The write bit line is formed in the sixth sub-through hole.

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