Semiconductor non-volatile memory device

Abstract

The invention relates to a semiconductor non-volatile memory device. Provided is a semiconductor nonvolatile memory device or the like capable of narrowing a cell voltage distribution range while suppressing write delay. The semiconductor nonvolatile memory device includes: a plurality of gate lines; a plurality of bit lines intersecting the plurality of gate lines; and a plurality of memory cells connected to intersections between the gate lines and the bit lines, respectively. The plurality of memory cells are respectively connected to one gate line selected from the plurality of gate lines via different bit lines, and the semiconductor nonvolatile memory device further includes a plurality of write bit line current or voltage control circuits respectively controlling the bit line current so as to simultaneously perform writing to the plurality of memory cells.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] The disclosure of Japanese Patent Application No. 2023-190734 filed on November 8, 2023 including the specification, drawings and abstract is incorporated herein by reference in its entirety. Background Art

[0003] The present disclosure relates to a semiconductor non-volatile memory device.

[0004] The flash memory is a nonvolatile memory that performs data recording by storing electrons in a floating gate while using a semiconductor element called a floating gate MOSFET (Metal Oxide Semiconductor Field Effect Transistor).

[0005] Focus on "multi-bit (value) technology" to achieve an increase in flash memory capacity. In general multi-bit writing, writing to a large number of cells on the same row is performed simultaneously. Since each of the memory cells has physical variations, its cell voltage can have a write distribution range. In multi-level cells (MLC) and the like, it is also important to control the write distribution range from the perspective of reliability and the like.

[0006] The method for controlling the writing speed by gradually increasing the gate voltage is the main trend. This is because, for example, if other conditions are the same, this method increases the gate voltage Vtm, which is easier to control than in SL / BL due to the smaller load current, and is easier to control due to its larger voltage range.

[0007] The disclosed techniques are listed below.

[0008] [Patent Document 1] Japanese Patent Application Publication No. 2023-92938 Summary of the invention

[0009] However, in the related art, for example, a reduction in the rising range of a pulse voltage for narrowing the distribution range of a write intermediate level of a multi-level cell (MLC) may cause a problem of write time delay due to insufficient operating margin (ie, write / erase window).

[0010] The present disclosure is to solve such a problem, and an object thereof is to provide a semiconductor nonvolatile memory device or the like capable of reducing the distribution range of a cell voltage while suppressing a write delay.

[0011] Other objects and novel features will become apparent from the description of this specification and the accompanying drawings.

[0012] According to one embodiment, a semiconductor nonvolatile memory device includes: a plurality of gate lines; a plurality of bit lines respectively intersecting the plurality of gate lines; and a plurality of memory cells respectively connected to intersections between the gate lines and the bit lines, wherein the plurality of memory cells are respectively connected to a gate line selected from the plurality of gate lines via different bit lines, and the semiconductor nonvolatile memory device further includes a plurality of write bit line current or voltage control circuits respectively controlling bit line currents so as to perform writes into the plurality of memory cells simultaneously.

[0013] According to one embodiment, a semiconductor nonvolatile memory device or the like capable of narrowing a cell voltage distribution range while suppressing a write delay can be provided. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] Figure 1 is a distribution diagram of a cell current for explaining a data writing operation based on a reference current type of a flash memory;

[0015] Figure 2 is a diagram illustrating a cell cross-sectional structure of a general memory chip;

[0016] Figure 3 is a diagram used to explain general multi-bit writing;

[0017] Figure 4 is a circuit diagram for explaining general multi-bit writing;

[0018] Figure 5 is a graph used to explain general multi-bit writing;

[0019] Figure 6 is a graph used to explain general multi-bit writing;

[0020] Figure 7 is a circuit diagram for explaining multi-bit writing according to an embodiment;

[0021] Figure 8 is a graph for explaining multi-bit writing according to an embodiment;

[0022] Fig. 9 is a diagram for explaining an electronic device including a semiconductor nonvolatile memory device according to the present embodiment;

[0023] Fig.10 is a circuit diagram including a write bit line current control circuit according to the present embodiment;

[0024] Fig.11 is a circuit diagram illustrating a write bit line current control circuit according to the present embodiment;

[0025] Fig.12 is a graph for explaining a write operation in an initial stage of writing;

[0026] Fig.13 is a circuit diagram for explaining a write operation in an initial stage of writing;

[0027] Fig.14 is a graph for explaining a write operation in an intermediate stage of writing;

[0028] Fig.15 is a circuit diagram for explaining a write operation in an intermediate stage of writing;

[0029] Fig.16 is a graph for explaining a write operation in the final stage of writing;

[0030] Fig.17 is a circuit diagram for explaining a write operation in the final stage of writing;

[0031] Fig.18 is a flow chart of distributed shrink writing according to this embodiment;

[0032] Fig.19 is a diagram for explaining general multi-bit writing according to another embodiment;

[0033] Fig. 20 is a graph for explaining a write operation according to another embodiment;

[0034] Fig.21 is a circuit diagram for explaining a write operation according to another embodiment;

[0035] Fig. 22 is a circuit diagram for explaining a write operation according to another embodiment; and

[0036] Fig.23 is a circuit diagram including a write bit line voltage control circuit according to another embodiment. DETAILED DESCRIPTION

[0037] For the purpose of explanation clarity, the following description and drawings are appropriately omitted and simplified. In the drawings, the same elements are denoted by the same reference numerals, and repeated explanations thereof are omitted as necessary.

[0038] First, an overview of flash memory will be explained. Flash memory is a storage medium in which data is readable and writable, and has various types ranging from built-in type to portable type. As types of flash memory, USB memory, SD card, memory card, memory stick and solid state drive (SSD) etc. are exemplified. Depending on the difference in circuit structure, the types of flash memory are classified into NAND type and NOR type. Flash memory includes billions of or more cells, and each of the cells stores data "0" or "1". The smaller the cell size, and in addition, the more cells included in the memory chip, the larger the capacity of the storage medium.

[0039] When the threshold voltage (Vt) is negative in the erase state in which the charge is discharged from its floating gate, the storage data in the memory cell in the flash memory is "1". On the other hand, in the erase state, when a write operation for supplying charge to the floating gate is performed, the memory cell becomes a write state. When the threshold voltage (Vt) in the write state is positive, the storage data in the memory cell is "0". That is, the threshold voltage (Vt) in the erase state of the memory cell made of the field effect transistor is lower than the threshold voltage in the write state.

[0040] When a read voltage (positive voltage) is input to its gate, the memory cell as the read target generates a cell current (also called a source-drain current) depending on the threshold voltage. In the same memory cell, the cell current in the erased state is greater than the cell current in the written state, which is a rise in the threshold voltage caused by the supply of charge (see Figure 1 ). The sense amplifier compares the reference current with the cell current to read out the data "1" or "0".

[0041] Figure 1 is a distribution diagram of a cell current for explaining a data write operation based on a reference current type of a flash memory. Figure 1 The cell current distribution curve in the case where the storage data in all the multiple memory cells configuring the nonvolatile memory device is "0" and the cell current distribution curve in the case where the storage data therein is "1" are illustrated. The cell current distribution curve in the case where the storage data is "1" is also called an erase cell distribution curve, and the cell current distribution curve in the case where the storage data is "0" is also called a write cell distribution curve. In the reference current reading type, it is necessary to set a reference current in a current region where the erase cell distribution curve and the write cell distribution curve do not overlap with each other. This is because the occurrence of a current region where the erase cell distribution curve and the write cell distribution curve overlap with each other can erroneously verify the storage data.

[0042] Figure 2 is a diagram illustrating a cell cross-sectional structure of a general memory chip. Figure 2It is a diagram for explaining the corresponding normal potential arrangement when reading, writing and erasing. A cell includes a transistor structure made of an n-type semiconductor and a p-type semiconductor, a gate structure and a tunnel oxide film sandwiched between the transistor structure and the gate structure. The gate structure includes a control gate (CG), a floating gate (FG) and a memory gate (MG).

[0043] In normal writing, when SSI (Source Side Injection) writing is performed in, for example, a FMONOS (Flash Metal Oxide Nitride Oxide Semiconductor) cell, Figure 2 Writing is performed in the potential arrangement illustrated in the middle figure of . That is, the MG voltage is set to a high voltage (such as 10.5V), and the CG voltage is set to 1.0V. The source voltage is set to 4.5V, and the drain voltage is set to 0.7V. Due to the potential arrangement, electrons flowing out from the source (S) are stored in the floating gate FG after passing through the tunnel oxide film. Therefore, since the threshold voltage (Vt) in the written state is positive, the stored data is "0". In MLC (multi-level cell) and the like, due to requests for reliability, it may be desirable to control writing more finely (by gradually changing the MG voltage).

[0044] On the other hand, at the time of data erasing, the drain voltage is set to 0 V, and the source voltage is set to 7 V. The MG voltage is set to -7 V. Due to the band-to-band tunneling effect, the high voltage applied to the source generates holes near the source, and the holes are sucked into the floating gate FG by the negative voltage of MG to offset the electrons in the floating gate FG.

[0045] When reading, the MG voltage is set to 0V, and the CG voltage is set to a low voltage (1.5V). The drain voltage is set to 1.5V. Therefore, the current flowing from the source to the drain is detected. When electrons are stored in the floating gate FG, it is difficult for the current to flow. Therefore, the stored data is detected as "0". On the other hand, when there are no electrons in the floating gate FG, the current flows easily. Therefore, the stored data is detected as "1".

[0046] Figure 3 is a diagram for explaining general multi-bit writing. Figure 2 Drain current "Ion" is shown flowing between the source and drain. Figure 3 The left figure of illustrates the cell distribution in a single level cell (SLC), and Figure 3 The right figure of illustrates the cell distribution in a multi-level cell (MLC).

[0047] The single level cell (SLC) is one of the NAND type flash memory systems, and is a system for storing 1-bit data consisting of a binary value in a storage element (memory cell). In the case of a "1" erase cell, no electrons are stored in the floating gate FG. Therefore, a relatively high current flows. In the case of a "0" write cell, electrons are stored in the floating gate FG. Therefore, a relatively low current flows. In the SLC, the corresponding write and erase ranges are determined from the relationship between the minimum value of the cell current in the erase cell distribution curve and the maximum value of the cell current in the write cell distribution curve, and the reliability of the number of writes, etc. is determined. Even in the SLC, the memory cell is greatly degraded by a write cell that is too deep. Therefore, it may be desirable to narrow the write distribution range to prevent cell degradation.

[0048] On the other hand, a multi-level cell (MLC) is a system for storing multi-bit data consisting of ternary values ​​in one storage element (memory cell). Figure 3 The illustrated example includes four distributions. MLC can store four states "00", "01", "10" and "11" (i.e., two bits). Specifically, in the "00" erase cell, no electrons are stored in the floating gate FG. Therefore, a relatively high current flows. On the other hand, in the "10" write cell, the "01" write cell, and the "00" write cell, the electrons stored in the floating gate FG are progressive in this order. Therefore, a relatively low current flows. In MLC, the write and erase window of the cell is increased by increasing the cell Vt distribution between the "00" write cell and the "11" erase cell. Therefore, reliability and operational issues increase. Some embodiments may use a four-level cell (QLC) and a three-level cell (TLC) for multi-bit writing, and the present disclosure is applicable.

[0049] Figure 4 : is a circuit diagram for explaining general multi-bit writing. The terms "Vcg" and "Vsl" represent fixed potentials, respectively. In this example, Vcg is 1.0V, and Vsl is 4.5V. The potential "Vmg" is variable and can be gradually increased from 4.0V to 10.5V by a voltage source. Each Vbl is about 0.7V, and Ibl is 1.66μA.

[0050] For example, in SLC, data in a write cell is set to "0", and data not to be written (remaining erased) is set to "1". The bit line write current performs control of writing of data "0" or "1". When writing is performed to all cells (cell A, cell B, and cell C), as shown in FIG. Figure 4As shown, the bit line current is caused to flow through all cells. In this case, the bit line voltage is approximately about 0.7 V. On the other hand, when a write operation is not performed in an individual cell, the bit line current in the individual cell stops.

[0051] Figure 5 is a graph used to explain general multi-bit writing. Figure 4 As illustrated, a write operation is performed in a plurality of cells (cells A, B, and C) by applying a predetermined Vmg pulse voltage and a predetermined write bit line current Ibl to the target memory cell. The larger the amount of electron storage in the floating gate FG, the higher the cell voltage Vt gradually becomes. It should be noted that the cell voltage Vt is the lower limit of the gate voltage through which the drain current flows, and is also referred to as the "threshold voltage." Then, when the Vmg voltage (or reference current) is applied to each of the cells (cell A, cell B, and cell C) to perform a read, it is possible to verify whether writing to each of the cells has ended, depending on whether a drain current corresponding to the cell Vt verification level flows. This system is called verification. Therefore, it is possible to verify for each of the cells whether the cell voltage exceeds the target cell voltage Vt verification level. In Figure 5 , a verification period indicated as (Verify) is illustrated between the Vmg pulse voltages. If the cell voltage Vt does not reach the verification level, the Vmg pulse voltage is increased by a predetermined amount and applied, and then a verification operation is performed, and it is verified whether the cell voltage Vt reaches the verification level indicating the end of writing. Therefore, multi-bit writing is performed by gradually increasing the Vmg pulse voltage and then repeating the above-mentioned verification operation.

[0052] In MLC, it should be noted that the same write level (such as "10") can be written to all cells (cell A, cell B, and cell C). In this case, Figure 5 As illustrated, the verification level indicating the end of writing is the same in all cells (cell A, cell B, and cell C). Different write levels may be written into the cells (cell A, cell B, and cell C) (such as "10", "01", and "00" may be written into cells A, cell B, and cell C, respectively). In this case, the verification level indicating the end of writing may be different in the cells (cell A, cell B, and cell C).

[0053] like Figure 6 As shown, in order to reduce the cell Vt distribution, it is necessary to reduce the rising range of the Vmg pulse voltage. However, the corresponding number of repetitions of writing and retrying increases, and it takes some time until the cell in which writing is finally performed ( Figure 6 The cell voltage Vt of cell A)) in reaches the verification level, and multi-bit writing is delayed.

[0054] Generally, in multi-bit writing, writing is performed simultaneously in a large number of cells on the same word line. Since the writing speed and initial position of each of the cells are different, the cell voltage Vt thereof has a predetermined distribution range. Writing is sequentially terminated starting from the cell whose cell voltage Vt reaches the verification level among the large number of cells in which writing is performed simultaneously. In particular, in order to reduce the cell Vt distribution, when the rising range of the Vmg pulse voltage is reduced, among the large number of cells in which writing is performed simultaneously, the cell in which writing is performed last ( Figure 6 Unit A) in is significantly delayed.

[0055] Deterioration of memory cells can be suppressed by reducing the distribution range of the cell voltage Vt, and the amount of information can be increased by storing a large number of bits in the memory.

[0056] As described above, in the related art, the operation margin (write and erase window) is insufficient, and thus there is a problem in that the write time is delayed because the distribution range of the write mid-level of the MLC is narrowed.

[0057] Figure 7 is a circuit diagram for explaining multi-bit writing according to an embodiment. In this embodiment, the current flowing through each of the bit lines bl is controlled at multiple levels (two levels of 1.66μA or 0.83μA in this example). The Vmg voltage is common in the word line w1 in the row direction. Therefore, it is impossible to write to the cell ( Figure 7 A different voltage is applied to each of the cells A, B, and C in the bit lines. Therefore, in the present embodiment, the adjustment of the current flowing through each of the bit lines b1 at multiple levels allows the cells ( Figure 7 Different voltages are applied to cells A, B, and C in the MLC. Therefore, in the MLC, in cells other than the cell having a cell voltage Vt exceeding the verification level indicating the end of writing, the current Ibl decreases, and the writing speed in the cell decreases. Therefore, the writing distribution range of the cell voltage can be narrowed.

[0058] Figure 8 is a graph for explaining multi-bit writing according to an embodiment. In this embodiment, different verification levels (which are Figure 8 The verification level B in the write operation is lower than the cell voltage Vt verification level indicating the end of writing (which is Figure 8Verification level A in the bit line bl). Verification level B is used to control the current Ibl flowing through each bit line bl. Specifically, a Vmg voltage (or reference current) corresponding to verification level A or verification level B of the cell voltage Vt is predetermined. When a predetermined Vmg voltage (or reference current) is applied to perform a read, it can be verified whether the cell voltage Vt exceeds the target cell Vt level. That is, if the current value data corresponding to the verification level A or verification level B can be read out by applying a cell voltage corresponding to verification level A or verification level B, it can be verified that the cell voltage Vt exceeds the target cell voltage Vt level. On the other hand, if the current value data corresponding to the verification level A or verification level B cannot be read out by applying a cell voltage corresponding to verification level A or verification level B, it can be verified that the cell voltage Vt does not exceed the target cell voltage Vt level.

[0059] After the Vmg pulse voltage gradually increases to reach the Vmg pulse voltage, where the cell voltage Vt reaches the verification level B at the Vmg pulse voltage, the cell voltage is applied to the corresponding cell to perform data reading. If the desired current value data can be read out, the current Ibl will decrease (from 1.66μA to 0.83μA). Therefore, the write speed is reduced, and the distribution range of the cell voltage can be reduced. For example, if it is desired to halve the distribution range, the write speed at the end is halved, and the number of write times is increased by 1 at most. However, the number of retries is generally tens of times (20 times or more in this design). Therefore, this increment will not produce significant differences. That is, when the distribution range is reduced, the delay of the write time in the MLC can be suppressed. The write speed at this time is changed by the bit line current Ibl. In the bit line, it is impossible to achieve so many stages of level adjustment. However, in the case where the resolution is about a low single-digit level magnitude, the current can be roughly controlled. The current can be controlled for each of the bit lines. Therefore, it is not necessary to perform writing from the beginning again.

[0060] Fig. 9 An electronic device 3 including a semiconductor non-volatile memory device 1 is illustrated. The electronic device 3 includes at least one control circuit 5 that controls the operation of the entire circuit. The processing circuit in the control circuit 5 may be based on one or more microprocessors, application processors, microcontrollers, digital signal processors, baseband processors, power management units, audio chips, application-specific integrated circuits, etc. Specifically, the processing circuit may control the Y selector described later, instruct the gate driver circuit in the write bit line current or voltage control circuit (regarding writing flag 1 or flag 2), and control the voltage source, etc. The control circuit may be used to execute software (such as an operating system or application, etc.) on the device.

[0061] Fig.101 is a circuit diagram illustrating a memory device according to an embodiment. The semiconductor nonvolatile memory device 1 is a flash memory, which includes a memory cell array 10, a plurality of Y selectors 50, a plurality of write bit line current control circuits 100, and a gate driver circuit 30. The write bit line current control circuits 100 are provided to correspond to the Y selectors 50, respectively.

[0062] The Y selector 50 receives a bit line address signal input from the outside (from the control circuit 5) and selects a write or read bit line from a plurality of write and read bit lines. The write bit line current control circuit 100 controls the write bit line current to be supplied to the bit line selected by the Y selector 50. The gate driver circuit 30 is configured to turn on the write flag 1 or the write flag 2 in each of the transistors in the write bit line current control circuit 100.

[0063] Fig.11 1 is an enlarged view of the write bit line current control circuit 100. The bit line bl coupled to the Y selector 50 is connected to the current ( Fig.11 The transistor Tr3 and the transistor Tr4 of the bit line bl coupled to the Y selector 50 are connected to the transistor Tr5 and the transistor Tr6 for the current during normal writing. The transistor Tr3 and the transistor Tr4 and the transistor Tr5 and the transistor Tr6 are connected in parallel with each other. The gate electrode of the transistor Tr3 and the gate electrode of the transistor Tr5 are connected to each other. When a gate voltage exceeding the threshold voltage is applied as a write flag 1 during normal writing, the normal write current Inor (Ibl=1.66μA) flows through the transistor Tr3 and the transistor Tr4 and the transistor Tr5 and the transistor Tr6.

[0064] On the other hand, the bit line b1 coupled to the Y selector 50 is connected to the current ( Fig.11 When a gate voltage exceeding the threshold voltage is applied as a write flag 2 at low speed writing, a low speed write current Ilow (Ibl=0.83μA) flows through transistor Tr1 and transistor Tr2. The low speed write current Ilow (Ibl=0.83μA) can be half of the normal write current Inor (Ibl=1.66μA).

[0065] although Fig.10 , but a voltage source for gradually increasing and applying the Vmg voltage is provided. The gate driver circuit 30 can be installed as part of an integrated circuit. Each Vbl is about 0.7V, and Ibl is 1.66μA. The gate line of each of the transistors Tr2 and Tr6 in each of the write bit line current control circuits 100 is connected to the transistor Tr7.

[0066] Fig.12 is a graph for explaining a write operation in an initial stage of writing, and Fig.13 1 is a circuit diagram for explaining the write operation in the initial stage of write. In the initial stage of write (i.e., until the cell voltage Vt exceeds the verification level B), when the Vmg voltage gradually increases, write is performed in the cell with the Ibl current (i.e., 1.66 μA) using the current source in normal write. Fig.13 As illustrated in the circuit diagram, for all cells A, cell B and cell C, when a gate voltage exceeding the threshold voltage is applied thereto as a write flag 1 during normal writing, each of the write bit line current control circuits 100 performs control so that the normal write current Inor (Ibl=1.66μA) flows through transistor Tr3 and transistor Tr4 as well as transistor Tr5 and transistor Tr6.

[0067] Fig.14 is a graph for explaining a write operation at an intermediate stage of writing, and Fig.15 1 is a circuit diagram for explaining a write operation in the middle stage of write. In the middle stage of write, the Vmg voltage further gradually increases, and a cell having a cell voltage Vt exceeding the verification level B appears (as Fig.14 It should be noted that the cell voltage Vt of cell C has exceeded the verification level A, and thus the writing is completed. Fig.15 As illustrated in the circuit diagram of , for cell A, when a gate voltage exceeding the threshold voltage is applied as a write flag 1 during normal writing, the write bit line current control circuit 100 performs control so that the normal write current Inor (Ibl=1.66μA) flows through transistors Tr3 and Tr4 and transistors Tr5 and Tr6. For cell B, when a gate voltage exceeding the threshold voltage is applied as a write flag 2 during low-speed writing, the write bit line current control circuit 100 performs control so that the low-speed write current Ilow (Ibl=0.83μA) flows through transistors Tr1 and Tr2. For cell C, writing has ended, and therefore the write bit line current control circuit 100 does not allow the normal write current Inor (Ibl=1.66μA) and the low-speed write current Ilow (Ibl=0.83μA) to flow.

[0068] Fig.16 is a graph for explaining a write operation in the final stage of writing, and Fig.17 1 is a circuit diagram for explaining the write operation in the final stage of the write. In the final stage of the write, the Vmg voltage gradually increases, and the corresponding cell voltage Vt of almost all cells exceeds the verification level B ( Fig.16 ).like Fig.17As shown, for cell A, when a gate voltage exceeding the threshold voltage is applied as a write flag 2 at low speed writing, the write bit line current control circuit 100 performs control so that the low speed write current Ilow (Ibl=0.83μA) flows through transistor Tr1 and transistor Tr2. For cells B and C, the respective cell voltages Vt of cells B and C exceed the verification level A, and writing has been completed, and therefore each of the write bit line current control circuits 100 does not flow the normal write current Inor (Ibl=1.66μA) and the low speed write current Ilow (Ibl=0.83μA).

[0069] For all cells (cell A, cell B, and cell C), when the corresponding cell voltage exceeds the verification level A, all write bit line current control circuits 100 each stop the current, and writing ends.

[0070] Fig.18 is a flow chart of distributed shrink writing. This flow chart can be controlled by the control circuit 5 ( Fig. 9 ) is executed by at least one of the following. The control circuit 5 receives data to be written into each of the memory cells from the outside (step S101). For each of the memory cells, the control circuit 5 checks whether the write flag 1 is "H" (when writing) or "L" (when not writing), and whether the write flag 2 is "H" (when writing or) or "L" (when not writing) (step S102). If the write flag 1 is "H" (when writing) and the write flag 2 is "H" (when writing) ("No" in step S102), the control circuit 5 checks whether its cell voltage exceeds the verification level A based on the read result of each of the memory cells (step S104). If the cell voltage does not exceed the verification level A ("No" in step S105), the control circuit 5 checks whether the cell voltage exceeds the verification level B based on the read result of each of the cells (step S106). On the other hand, if the cell voltage exceeds the verification level A (Yes in step S105), the control circuit 5 sets both the write flag 1 and the write flag 2 to "L" (at the time of non-writing) (step S1051). Thus, writing into the cell stops.

[0071] If the cell voltage exceeds level B ("Yes" in step S107), write mark 2 is "H" (when writing) and write mark 1 is "L" (when not writing). The control circuit 5 causes the write bit line current control circuit 100 to cause a low-speed write current to flow through the bit line to the corresponding cell to perform low-speed writing (step S108). On the other hand, if the cell voltage does not exceed level B ("No" in step S107), write mark 1 is "H" (when writing). The control circuit 5 causes the write bit line current control circuit 100 to cause a normal write current to flow through the bit line to the corresponding cell to perform normal writing (step S109). If write data 2 or write data 1 in all IOs is "L" (when not writing) ("Yes" in step S110), the processing ends. On the other hand, if the write data 2 or the write data 1 in all IOs is not "L" (when not writing) (that is, either one is "H" (when writing)) ("No" in step S110), the write operation is performed (step S111), and the processing from step S102 to step S110 is repeated.

[0072] In the above-described embodiments, the distribution of the cell voltage Vt can be reduced. In addition, the present disclosure is also applicable to high-speed writing as described below. The plurality of memory cells may include at least one of a multi-level cell (MLC), a three-level cell (TLC), and a four-level cell (QLC).

[0073] Other embodiments

[0074] Fig.19 is a diagram for explaining general multi-bit writing according to another embodiment. In the case of general MLC, in order to write multiple cell voltage levels at the same time, the write start voltage is started to match the distribution "B" corresponding to the verification level B, which is lower than the verification level A indicating the end of writing. This requires starting from a relatively low Vmg voltage. Therefore, it takes a long time until the writing of the distribution "A" corresponding to the verification level A indicating the end of writing is completed.

[0075] Therefore, in this embodiment, the write current Ibl is controllable for each of the target distributions corresponding to the memory cells through the write bit line current control circuit 100 which is the same as the above-mentioned embodiment, so as to realize the high-speed write operation.

[0076] Fig. 20is a graph for explaining a write operation according to another embodiment. For a cell corresponding to distribution A (such as cell A or cell C), a normal write current Inor (Ibl=1.66 μA) is set to achieve a normal write speed. On the other hand, for a cell corresponding to distribution B having a cell voltage level lower than that of distribution A (such as cell B), a low-speed write current Inor (Ibl=0.83 μA) is set to achieve a low-speed write speed. It should be noted that, for example, distribution A may be Figure 3 The illustrated "01" write cell corresponds to the distribution B, while the distribution B can be Figure 3 The illustrated "10" corresponds to the write unit.

[0077] Therefore, the Vmg voltage at the start of writing can be set to Fig.19 The Vmg voltage in the illustrated case is relatively high in comparison, and the number of write retries can be reduced to increase the speed of the write operation.

[0078] Fig.21 is a circuit diagram for explaining a write operation according to the present embodiment. Fig.21 The circuit diagram and Fig.10 However, in the above-described embodiment, the normal write current or the low-speed write current may be selected depending on a target distribution that is different for each of the memory cells without changing the write speed during the process described in the present embodiment.

[0079] Fig. 22 is a circuit diagram for explaining a write operation according to the present embodiment. For a cell A or a cell C corresponding to distribution A, a normal write current Inor (Ibl=1.66 μA) is set to achieve a normal write speed. On the other hand, for a cell B corresponding to distribution B having a cell voltage level lower than that of distribution A, a low-speed write current Inor (Ibl=0.83 μA) is set to achieve a low-speed write speed.

[0080] like Fig. 22 As shown, for cell A, when a gate voltage exceeding the threshold voltage is applied as normal writing corresponding to distribution A, the write bit line current control circuit 100 performs control so that a normal write current Inor (Ibl=1.66μA) flows through transistors Tr3 and Tr4 as well as transistors Tr5 and Tr6. Similarly, for cell C, when a gate voltage exceeding the threshold voltage is applied at the time of normal writing corresponding to distribution A, the write bit line current control circuit 100 performs control so that a normal write current Inor (Ibl=1.66μA) flows through transistors Tr3 and Tr4 as well as transistors Tr5 and Tr6.

[0081] On the other hand, for cell B, when a gate voltage exceeding the threshold voltage is applied as a low-speed write corresponding to distribution B, the write bit line current control circuit 100 performs control so that a low-speed write current Ilow (Ibl=0.83 μA) flows through transistor Tr1 and transistor Tr2.

[0082] For unit A, unit B and unit C, if Fig. 20 As shown in the figure, the same Vmg voltage is gradually increased and applied. In this case, the Vmg voltage at startup can be set higher than Fig.19 The voltage in the illustrated comparative example, and therefore, the write operation can be ended in a short time.

[0083] In some embodiments, it should be noted that a normal write current corresponding to target distribution A can be made to flow for cell A, a medium-speed write current corresponding to target distribution B can be made to flow for cell B, and a low-speed write current corresponding to target distribution C can be made to flow for cell C. In this case, in the write bit line current control circuit, a circuit for normal write current, a circuit for medium-speed write current, and a circuit for low-speed write current can be arranged in parallel. In this case, in the circuit for normal write current, at least three transistors can be arranged in parallel. In the circuit for medium-speed write current, at least two transistors can be arranged in parallel. In the circuit for low-speed write current, at least one transistor can be arranged in parallel. Therefore, as can be appreciated by those skilled in the art, the present disclosure is also applicable to n-bit ("n" is an optional integer) MLC cells (such as TLC or QLC).

[0084] Fig.23 is a circuit diagram including a write bit line voltage control circuit according to another embodiment. Fig.10 The write bit line current control circuit 100 described in the examples can also be used Fig.23 The basic operating principle is similar to Fig.10 The operating principles in the embodiments described in etc. are similar.

[0085] The bit line b1 coupled to the Y selector 50 is connected to a current ( Fig.11 The write voltage V1 is applied to the source electrode of the transistor Tr2. When a gate voltage exceeding the threshold voltage is applied as a write flag 1 during normal writing, a normal write current Inor flows through the transistor Tr2.

[0086] On the other hand, the bit line b1 coupled to the Y selector 50 is connected to the current ( Fig.11The write voltage V2 is applied to the source electrode of the transistor Tr1. In the write bit line current control circuit 100b, the write voltage V1 for normal writing is controlled to be lower than the write current V2 for low-speed writing. When a gate voltage exceeding the threshold voltage is applied as a write flag 2 during low-speed writing, the low-speed write current Ilow flows through the transistor Tr2.

[0087] According to some embodiments, a semiconductor non-volatile memory device may be provided. The semiconductor non-volatile memory device includes: a plurality of gate lines; a plurality of bit lines, respectively intersecting the plurality of gate lines; and a plurality of memory cells, respectively connected to intersections between the gate lines and the bit lines, wherein the plurality of memory cells are respectively connected to one gate line selected from the plurality of gate lines via different bit lines, and the semiconductor non-volatile memory device further includes a plurality of write bit line current or voltage control circuits that respectively control the bit line currents so as to simultaneously perform writes to the plurality of memory cells. In another embodiment, the semiconductor non-volatile memory device may be configured such that a plurality of cell voltage verification levels for checking cell states are respectively provided for a plurality of target cell voltage distributions, and such that the write bit line current or voltage control circuits respectively control the write speed by using a plurality of bit line currents selected based on a plurality of gate voltages and a read result corresponding to the verification level. A semiconductor non-volatile memory device can be configured such that a first cell voltage verification level indicating the end of cell writing and a second cell voltage verification level lower than the first cell voltage verification level are respectively provided for a target cell voltage distribution, and such that if a cell voltage is verified to exceed the second cell voltage verification level from a read result of a memory cell, a write bit line current or voltage control circuit controls the write bit line current of the memory cell to a current lower than a normal current.

[0088] In yet another embodiment, the write bit line current control circuit 100 may include: a first transistor Tr4 and a second transistor Tr6, each having a gate receiving a reference potential and connected in parallel to each other to pass a first write bit line current; and a third transistor Tr2, having a gate receiving a reference potential and passing a second write bit line current that is smaller than the first write bit line current (see Fig.11 ). In addition, the write bit line current control circuit 100 may include: a fourth transistor Tr3 and a fifth transistor Tr5, each having a gate for receiving a write flag signal and connected in series to the first transistor Tr4 and the second transistor Tr6, respectively; and a sixth transistor Tr1, having a gate for receiving a write flag signal and directly connected to the third transistor Tr2 (see Fig.11 ).

[0089] The write bit line voltage control circuit 100b may include: a first transistor Tr1 having a gate receiving a first write flag signal and a source receiving a write voltage, and passing a first write bit line current; and a second transistor Tr2 having a gate receiving a second write flag signal and a source receiving a write voltage, and passing a second write bit line current that is smaller than the first write bit line current, and a source potential V1 of the first transistor Tr1 may be controlled to be lower than a source potential V2 of the second transistor Tr2 (see Fig.23 ).

[0090] In yet another embodiment, the semiconductor non-volatile memory device may include: a first Y selector that selects one of a plurality of gate lines; a second Y selector that selects one of a plurality of gate lines; and a third Y selector that selects one of a plurality of gate lines, and may include a first write bit line current or voltage control circuit, a second write bit line current or voltage control circuit, and a third write bit line current or voltage control circuit corresponding to the first Y selector, the second Y selector, and the third Y selector, respectively.

[0091] A pulse voltage may be applied to corresponding gate electrodes of the plurality of memory cells via the gate lines for multiple times, the pulse voltage may be applied thereto multiple times when the pulse voltage is gradually increased, and a verification period may be provided in each of the multiple times of applying the pulse voltage, and verification is performed during the verification period. The plurality of memory cells may include at least one of a multi-level cell (MLC), a three-level cell (TLC), and a four-level cell (QLC).

[0092] In the foregoing, the present invention made by the inventors of the present application has been specifically described based on the embodiments. However, the present invention is not limited to the foregoing embodiments, and various modifications can be made within the scope of the present invention.

Claims

1. A semiconductor non-volatile memory device, comprising: a plurality of gate lines; a plurality of bit lines respectively intersecting the plurality of gate lines; as well as A plurality of memory cells are connected to intersections between the gate lines and the bit lines, respectively. wherein the plurality of memory cells are connected to a gate line selected from the plurality of gate lines via different bit lines, respectively, and The semiconductor nonvolatile memory device further includes a plurality of write bit line current or voltage control circuits that respectively control bit line currents so as to simultaneously perform writing to the plurality of memory cells.

2. The semiconductor nonvolatile memory device according to claim 1, wherein a plurality of cell voltage verification levels for checking cell states are provided for the plurality of target cell voltage distributions respectively, and The write bit line current or voltage control circuit controls write speeds respectively by using the plurality of bit line currents selected based on a plurality of gate voltages and a read result corresponding to the verification level.

3. The semiconductor nonvolatile memory device according to claim 2, wherein a first cell voltage verification level indicating the end of cell writing and a second cell voltage verification level lower than the first cell voltage verification level are provided for the target cell voltage distribution, and If the cell voltage is verified to exceed the second cell voltage verification level according to a read result of the memory cell, the write bit line current or voltage control circuit controls the write bit line current of the memory cell to a current lower than a normal current.

4. The semiconductor nonvolatile memory device according to claim 2, The write bit line current control circuit comprises: a first transistor and a second transistor, each having a gate receiving a reference potential and connected in parallel with each other to pass a first write bit line current; as well as A third transistor has a gate receiving a reference potential and passes a second write bit line current that is smaller than the first write bit line current.

5. The semiconductor nonvolatile memory device according to claim 4, The write bit line current control circuit comprises: a fourth transistor and a fifth transistor, each having a gate receiving a write flag signal, and connected in series to the first transistor and the second transistor, respectively; as well as The sixth transistor has a gate receiving a write flag signal and is directly connected to the third transistor.

6. The semiconductor nonvolatile memory device according to claim 2, The write bit line voltage control circuit comprises: A first transistor having a gate receiving a first write flag signal and a source receiving a write voltage, and transmitting a first write bit line current; as well as a second transistor having a gate receiving a second write flag signal and a source receiving a write voltage and passing a second write bit line current smaller than the first write bit line current, and A source potential of the first transistor is controlled to be lower than a source potential of the second transistor.

7. The semiconductor nonvolatile memory device according to claim 1, wherein pulse voltages are applied multiple times to corresponding gate electrodes of the plurality of memory cells via the gate lines, applying the plurality of pulse voltages while gradually increasing the pulse voltage, and Verification periods are provided respectively in the plurality of applications of the pulse voltage, and verification is performed during the verification periods.

8. The semiconductor nonvolatile memory device according to claim 1, The plurality of memory cells include n-bit (n is a selectable integer) multi-level cells (MLC), that is, at least one of a three-level cell (TLC) and a four-level cell (QLC).

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