Memory and access control method therefor, and electronic device

Abstract

A memory and an access control method therefor, and an electronic device. The memory comprises: at least one storage array layer and a plurality of common bit lines (CBL) having one-to-one correspondence to each storage array layer. Each storage array layer comprises a plurality of read bit lines (BLr) and a plurality of write bit lines (BLw) extending in a first direction parallel to a substrate. The read bit lines (BLr) and the write bit lines (BLw) on the same layer are connected to a corresponding common bit line (CBL). Each write bit line (BLw) is connected to a corresponding common bit line (CBL) by means of a first write gating sub-circuit (11), and each read bit line (BLr) is connected to a corresponding common bit line by means of a first read gating sub-circuit (12). The first write gating sub-circuit (11) is further connected to a first write gating control line, and is configured to connect / disconnect the write bit line to / from the common bit line under the control of the first write gating control line. The first read gating sub-circuit (12) is further connected to a first read gating control line, and is configured to connect / disconnect the read bit line to / from the common bit line under the control of the first read gating control line.

Description

Memory and access control method thereof, and electronic device

[0001] This application claims priority to the Chinese patent application filed on April 2, 2024, with application number 202410394588.7 and invention name “A memory and its access control method, and electronic device”, the contents of which should be understood as incorporated into this application by reference. Technical Field

[0002] The embodiments of the present disclosure relate to, but are not limited to, device design and manufacturing in the field of semiconductor technology, and in particular to a memory and an access control method thereof, and an electronic device. Background Art

[0003] With the development of integrated circuit technology, the critical dimensions of devices are shrinking, and the types and numbers of devices contained in a single chip are increasing accordingly, so that any slight difference in process production may affect device performance.

[0004] To minimize product costs, people hope to create as many device units as possible on a limited substrate. Since the advent of Moore's Law, the industry has proposed various semiconductor structure designs and process optimizations to meet people's current product needs.

[0005] Summary of the Invention

[0006] The following is a summary of the subject matter described in detail herein. This summary is not intended to limit the scope of the claims.

[0007] An embodiment of the present application provides a memory device, comprising: at least one layer of memory arrays, and multiple common bit lines corresponding to each layer of memory arrays; each layer of memory arrays comprising multiple memory cells, multiple read bit lines extending along a first direction parallel to a substrate, and multiple write bit lines extending along the first direction, wherein the read bit lines and write bit lines of the same layer are connected to the common bit lines corresponding to the memory array layer; the memory cells comprising at least read transistors and write transistors, the read transistors being connected to the read bit lines, the write transistors being connected to the write bit lines, each of the write bit lines being connected to the common bit lines via a first write gate subcircuit, and each of the read bit lines being connected to the common bit lines via a first read gate subcircuit; the first write gate subcircuit being further connected to a first write gate control line, the first read gate subcircuit being further connected to a first read gate control line; the first write gate subcircuit being configured to connect or disconnect the write bit lines and the common bit lines according to control of the first write gate control line; and the first read gate subcircuit being configured to connect or disconnect the read bit lines and the common bit lines according to control of the first read gate control line.

[0008] In some embodiments, the memory includes a multi-layer memory array stacked in a direction perpendicular to the substrate, the first write enable sub-circuits connected to the write bit lines of the same row in different layers are connected to the same first write enable control line, and the first write enable sub-circuits connected to the write bit lines of different rows are connected to different first write enable control lines; the first read enable sub-circuits connected to the read bit lines of the same row in different layers are connected to the same first read enable control line, and the first read enable sub-circuits connected to the read bit lines of different rows are connected to different first read enable control lines.

[0009] In some embodiments, the common bit line extends along a second direction parallel to the substrate, the first write gate control line extends along a direction perpendicular to the substrate, the first read gate control line extends along a direction perpendicular to the substrate, and the first direction intersects the second direction.

[0010] In some embodiments, a first end of each of the write bit lines is connected to the common bit line via a first write gating subcircuit, a second end of each of the write bit lines is connected to a preset voltage terminal via a second write gating subcircuit, and the second write gating subcircuit is further connected to a second write gating control line; a first end of each of the read bit lines is connected to the common bit line via a first read gating subcircuit, a second end of each of the read bit lines is connected to the preset voltage terminal via a second read gating subcircuit, and the second read gating subcircuit is further connected to a second read gating control line;

[0011] The second write gate subcircuit is configured to: connect or disconnect the write bit line and the preset voltage terminal according to control of the second write gate control line;

[0012] The second read gate sub-circuit is configured to connect or disconnect the read bit line and the preset voltage terminal according to control of the second read gate control line.

[0013] In some embodiments, the second write enable sub-circuits connected to the write bit lines of the same row in different layers are connected to the same second write enable control line, and the second write enable sub-circuits connected to the write bit lines of different rows are connected to different second write enable control lines; the second read enable sub-circuits connected to the read bit lines of the same row in different layers are connected to the same second read enable control line, and the second read enable sub-circuits connected to the read bit lines of different rows are connected to different second read enable control lines.

[0014] In some embodiments, the first write gating subcircuit and the second write gating subcircuit connected to the same write bit line are configured in opposite states; the first read gating subcircuit and the second read gating subcircuit connected to the same read bit line are configured in opposite states.

[0015] In some embodiments, the second write gate control line extends in a direction perpendicular to the substrate, and the second read gate control line extends in a direction perpendicular to the substrate.

[0016] In some embodiments, the memory includes a plurality of voltage lines extending in a direction perpendicular to the substrate, the plurality of voltage lines being distributed along the second direction, and the voltage lines being connected to the preset voltage terminal; write bit lines in the same row of different layers being connected to the same voltage line extending in a direction perpendicular to the substrate via different second write selection sub-circuits, and write bit lines in different rows being connected to different voltage lines extending in a direction perpendicular to the substrate via different second write selection sub-circuits; read bit lines in the same row of different layers being connected to the same voltage line extending in a direction perpendicular to the substrate via different second read selection sub-circuits, and read bit lines in different rows being connected to different voltage lines extending in a direction perpendicular to the substrate via different second read selection sub-circuits;

[0017] Alternatively, the memory includes a conductive slot extending along the second direction, the conductive slot is connected to the preset voltage terminal, multiple write bit lines are connected to the conductive slot through different second write enable sub-circuits, and multiple read bit lines are connected to the conductive slot through different second read enable sub-circuits.

[0018] An embodiment of the present disclosure provides an electronic device, comprising the memory described in any of the above embodiments.

[0019] An embodiment of the present disclosure provides a method for accessing a memory, including:

[0020] In the data writing phase or the data reading phase, according to the target layer and the target row where the storage unit to be operated is located, an on-level signal is loaded on the first write select control line or the first read select control line connected to the write bit line or the read bit line of the target row, and an off-level signal is loaded on the first write select control line or the first read select control line connected to the write bit line or the read bit line of the non-target row.

[0021] In some embodiments, the method further includes: loading a turn-off level signal on a second write gate control line or a second read gate control line connected to the write bit line or the read bit line of the target row, and loading a turn-on level signal on a second write gate control line connected to the write bit line or the read bit line of a non-target row.

[0022] Other features and advantages of the present application will be described in the following description, and in part will become apparent from the description, or will be understood by practicing the present application. Other advantages of the present application can be realized and obtained by the solutions described in the description and the drawings.

[0023] Still other aspects will become apparent upon reading and understanding the accompanying drawings and detailed description.

[0024] Summary of the Figures

[0025] The accompanying drawings are used to provide an understanding of the technical solution of the present application and constitute a part of the specification. Together with the embodiments of the present application, they are used to explain the technical solution of the present application and do not constitute a limitation on the technical solution of the present application.

[0026] FIG1 is a schematic diagram of a memory provided in an embodiment of the present application.

[0027] Details

[0028] The embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings. Unless there is a conflict, the embodiments of the present disclosure and the features therein may be combined with each other in any manner.

[0029] Unless otherwise defined, technical or scientific terms used in the present disclosure should have the same meaning as commonly understood by a person having ordinary skills in the field to which the present disclosure belongs.

[0030] The embodiments of the present disclosure are not necessarily limited to the dimensions shown in the drawings, and the shapes and sizes of the components in the drawings do not reflect the true proportions. In addition, the drawings schematically illustrate ideal examples, and the embodiments of the present disclosure are not limited to the shapes or values ​​shown in the drawings.

[0031] In the present disclosure, ordinal numbers such as “first”, “second” and “third” are provided to avoid confusion among constituent elements and do not indicate any order, quantity or importance.

[0032] In this disclosure, for convenience, words and phrases indicating orientation or positional relationships, such as "middle," "upper," "lower," "front," "back," "vertical," "horizontal," "top," "bottom," "inside," and "outside," are used to illustrate the positional relationships of constituent elements with reference to the accompanying drawings. This is merely for the convenience of describing this specification and simplifying the description, and does not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operate in a specific orientation. Therefore, it should not be understood as a limitation of this disclosure. The positional relationships of constituent elements may be appropriately changed according to the direction in which each constituent element is described. Therefore, the words and phrases described in this disclosure are not limited and may be appropriately replaced according to the circumstances.

[0033] In this disclosure, unless otherwise expressly specified or limited, the terms "mounted," "connected," and "connected" should be interpreted broadly. For example, they can refer to physical or signal connections, contact connections, or integral connections. They can be direct connections, indirect connections through intermediaries, or internal connections between two components. Those skilled in the art will understand the specific meanings of these terms in this disclosure based on the specific circumstances.

[0034] In this disclosure, a transistor refers to an element comprising at least three terminals: a gate electrode, a drain electrode, and a source electrode. A transistor has a channel region between a drain electrode (drain electrode terminal, drain region, or drain electrode) and a source electrode (source electrode terminal, source region, or source electrode), and current can flow through the drain electrode, the channel region, and the source electrode. In this disclosure, the channel region refers to the region through which current primarily flows.

[0035] In the present disclosure, the first electrode may be a drain electrode and the second electrode may be a source electrode, or vice versa. The functions of the "source electrode" and "drain electrode" may be reversed when using transistors with opposite polarities or when the direction of current changes during circuit operation. Therefore, in the present disclosure, the terms "source electrode" and "drain electrode" may be reversed.

[0036] In this disclosure, "connection" includes the connection of components via an element having some electrical function. There are no particular limitations on the "element having some electrical function" as long as it enables the transfer of electrical signals between the connected components. Examples of "element having some electrical function" include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other components with various functions.

[0037] In this disclosure, "parallel" means approximately parallel or nearly parallel. For example, the angle formed by two straight lines is greater than -10° and less than 10°, and thus also includes the angle of greater than -5° and less than 5°. In addition, "perpendicular" means approximately perpendicular. For example, the angle formed by two straight lines is greater than 80° and less than 100°, and thus also includes the angle of greater than 85° and less than 95°.

[0038] The phrase "A and B disposed in the same layer" in this disclosure encompasses layers formed of the same material or different materials located on the same film layer. For example, A and B are formed by forming the same film layer from the same material and then undergoing the same patterning process or different patterning processes. A and B disposed in the same layer can be located on the same horizontal plane, but not necessarily on the same film layer, or located in different regions of the same film layer, but not necessarily on the same horizontal plane.

[0039] A 2T0C memory array may include multiple memory cells, each of which may be connected to a write word line (WLw), a write bit line (BLw), and a read word line (WLr) and a read bit line (BLr), with independent control of reading and writing. When the memory array is 3D stacked, the read word line and the write word line may extend in a direction perpendicular to the substrate, and the read word line and the write word line may be shared by multiple layers. Each layer includes multiple read bit lines and multiple write bit lines extending in a direction parallel to the substrate, and the multiple read bit lines and multiple write bit lines of each layer need to be connected to the peripheral circuit through stepped vias. When the number of stacked layers is relatively large, many stepped vias are required, thereby occupying a larger area and reducing the area efficiency of the chip. In the embodiment of the present disclosure, by setting a common bit line, the read bit line and the write bit line of the same layer are connected to a common bit line, and the common bit line is then connected to the peripheral circuit through the stepped via, the number of stepped vias can be greatly reduced, and the area efficiency can be improved.

[0040] Figure 1 is a schematic diagram of a memory provided by an embodiment of the present disclosure. The memory provided by this embodiment includes a multi-layer memory array stacked in a direction perpendicular to a substrate (but the present disclosure is not limited thereto; the memory may include a single layer of memory array). Each layer of the memory array may include multiple memory cells arranged along a first direction X parallel to the substrate and a second direction Y parallel to the substrate, multiple read bit lines extending along the first direction X, and multiple write bit lines extending along the first direction X. The multiple read bit lines in each layer are spaced apart along the second direction Y. The memory cells include at least read transistors and write transistors, the write transistors connecting the write bit lines, and the read transistors connecting the read bit lines. The multiple write bit lines in each layer are spaced apart along the second direction Y. The first direction X and the second direction Y intersect. In some embodiments, the first direction X and the second direction Y may be perpendicular. The memory may also include multiple write word lines and read word lines extending in a direction perpendicular to the substrate. The multiple write word lines may be arranged in an array along the first direction X and the second direction Y. The multiple read word lines may be arranged in an array along the first direction X and the second direction Y. The memory may include n rows and m columns of read word lines, and n rows and m columns of write word lines. The write word line in the i-th row and j-th column is a write word line WLw_i_j, and the read word line in the i-th row and j-th column is a read word line WLr_i_j, where i ranges from 1 to n and j ranges from 1 to m. Each layer of the memory array includes n write bit lines and n read bit lines, wherein the write bit line in the i-th row of the k-th layer is a write bit line BLw_i_k, and the read bit line in the i-th row of the k-th layer is a read bit line BLr_i_k, where i ranges from 1 to n and k ranges from 1 to K, where K is the number of layers in the memory array stack. The memory cell may be a 2T0C memory cell. The memory cell in the i-th row and j-th column of the k-th layer is connected to the write word line WLw_i_j and the read word line WLr_i_j, and is also connected to the write bit line BLw_i_k and the read bit line BLr_i_k. As represented by area 10 in FIG. 1 , the memory cell in the first row and first column of the kth layer is connected to the write word line WLw_1_1 and the read word line WLr_1_1 , as well as to the write bit line BLw_1_k and the read bit line BLr_1_k.

[0041] The memory may also include multiple common bit lines CBL, each layer of storage array corresponds to a common bit line CBL, and the read bit line and write bit line of each layer are connected to the common bit line CBL corresponding to the layer. For example, the k-th layer of storage array corresponds to the common bit line CBLk, the write bit line BLw_i_k of the k-th layer, i is 1 to n, is connected to the common bit line CBLk, and the read bit line BLr_i_k of the k-th layer, i is 1 to n, is connected to the common bit line CBLk. The write bit lines of different layers are connected to different common bit lines CBL, and the read bit lines of different layers are connected to different common bit lines CBL. Figure 1 only shows the common bit line CBLk corresponding to the k-th layer of storage array. The common bit lines of other layers can refer to Figure 1.

[0042] In some embodiments, the common bit line CBL may extend in a direction perpendicular to the directions of the read bit lines and the write bit lines. For example, the common bit line CBL may extend along the second direction Y. The common bit line CBL may be provided on the same layer as the read bit line or the write bit line to which the common bit line CBL is connected. That is, the common bit line may be formed at the same time as the read bit line and the write bit line.

[0043] In some embodiments, the plurality of common bit lines CBL may be disposed on the same side of the memory array, but not limited thereto, the plurality of common bit lines CBL may be disposed on different sides of the memory array.

[0044] In some embodiments, each of the write bit lines can be connected to the common bit line CBL via a first write gate sub-circuit 11. The first write gate sub-circuit 11 is also connected to a first write gate control line. The first write gate sub-circuit 11 is configured to connect (i.e., electrically connect) or disconnect the write bit line and the common bit line CBL under the control of the first write gate control line. In other words, under the control of the first write gate control line, the signal of the common bit line CBL is applied to or not applied to the write bit line.

[0045] In some embodiments, each of the read bit lines can be connected to the common bit line CBL via a first read gating sub-circuit 12. The first read gating sub-circuit 12 is also connected to a first read gating control line. The first read gating sub-circuit 12 is configured to connect or disconnect the read bit line and the common bit line CBL under the control of the first read gating control line. In other words, the first read gating sub-circuit 12 applies or does not apply the signal of the common bit line CBL to the read bit line under the control of the first read gating control line.

[0046] In some embodiments, the first write gate sub-circuits 11 connected to write bit lines in the same row on different layers are connected to the same first write gate control line, while the first write gate sub-circuits 11 connected to write bit lines in different rows are connected to different first write gate control lines. For example, the first write gate sub-circuits 11 connected to write bit lines BLw_1_k in the first row on different layers are all connected to the first first write gate control line S_BLw_1, and the first write gate sub-circuits 11 connected to write bit lines BLw_n_k in the nth row on different layers are all connected to the nth first write gate control line S_BLw_n. The number of first write gate control lines can be consistent with the number of rows of write bit lines included in a layer of the memory array. For example, if each layer of the memory array includes n rows of write bit lines, then there are n first write gate control lines. Thus, a write bit line can be selected via the common bit line CBL and the first write gate control line. For example, the common bit line CBLk corresponding to the k-th layer of the storage array is loaded with an activation signal (the common bit lines corresponding to the remaining layers are loaded with a non-activation signal), the i-th first write enable control line S_BLw_i enables the corresponding first write enable sub-circuit 11 (the remaining first write enable control lines do not enable the corresponding first write enable sub-circuit 11), then the write bit line BLw_i_k of the i-th row of the k-th layer is loaded with an activation signal, so that a write operation can be performed through the selected write bit line.

[0047] In some embodiments, the first write gate control line extends in a direction perpendicular to the substrate and passes through memory arrays at different layers.

[0048] In some embodiments, the first read gating sub-circuits 12 connected to read bit lines in the same row on different layers are connected to the same first read gating control line, while the first read gating sub-circuits 12 connected to read bit lines in different rows are connected to different first read gating control lines. For example, the first read gating sub-circuits 12 connected to read bit lines BLr_1_k in the first row of different layers are all connected to the first first read gating control line S_BLr_1, and the first read gating sub-circuits 12 connected to read bit lines BLr_n_k in the nth row of different layers are all connected to the nth first read gating control line S_BLr_n. The number of first read gating control lines can be consistent with the number of rows of read bit lines included in a layer of the memory array. For example, if each layer of the memory array includes n rows of read bit lines, then there are n first read gating control lines. Thus, a read bit line can be selected via the common bit line CBL and the first read gating control line. For example, the common bit line CBLk corresponding to the k-th layer of the storage array is loaded with an activation signal (the common bit lines corresponding to the remaining layers are loaded with a non-activation signal), the i-th first read enable control line S_BLr_i enables the corresponding first read enable sub-circuit 12 (the remaining first read enable control lines do not enable the corresponding first read enable sub-circuit 12), then the read bit line BLr_i_k of the i-th row of the k-th layer is loaded with an activation signal, so that a read operation can be performed through the selected read bit line.

[0049] In some embodiments, the first read gate control line may extend in a direction perpendicular to the substrate and penetrate memory arrays at different layers.

[0050] In some embodiments, the first write gating sub-circuit 11 may include a first transistor T1, wherein a gate electrode of the first transistor T1 is connected to the first write gating control line, a first electrode is connected to the write bit line, and a second electrode is connected to the common bit line CBL. The structure of the first write gating sub-circuit 11 described in this embodiment is merely an example, and other circuits capable of implementing gating may be used.

[0051] In some embodiments, the first transistor T1 is, for example, an N-type transistor, but the embodiments of the present disclosure are not limited thereto. The first transistor T1 may be a P-type transistor.

[0052] In some embodiments, the first read gating sub-circuit 12 may include a second transistor T2, wherein a gate electrode of the second transistor T2 is connected to the first read gating control line, a first electrode is connected to the read bit line, and a second electrode is connected to the common bit line CBL. The structure of the first read gating sub-circuit 12 described in this embodiment is merely an example, and other circuits capable of implementing gating may be used.

[0053] In some embodiments, the second transistor T2 is, for example, an N-type transistor, but the embodiments of the present disclosure are not limited thereto. The second transistor T2 may be a P-type transistor.

[0054] In some embodiments, the write bit line may include a first end and a second end. The first end of the write bit line may be connected to the first write gate sub-circuit 11, and the second end of the write bit line may be connected to a preset voltage terminal V_ref through a second write gate sub-circuit 21. The preset voltage terminal V_ref may be a low-level signal terminal, such as a ground terminal. The second write gate sub-circuit 21 may also be connected to a second write gate control line. The second write gate sub-circuit 21 is configured to connect or disconnect the write bit line and the preset voltage terminal V_ref under the control of the second write gate control line. The second write gate sub-circuit 21 may connect unselected write bit lines to the preset voltage terminal V_ref to reduce interference. A memory cell may be connected to a position between the first and second ends of the write bit line.

[0055] In some embodiments, the second write gate control line may extend in a direction perpendicular to the substrate and pass through memory arrays at different layers.

[0056] In some embodiments, the second write gate sub-circuits 21 connected to write bit lines in the same row across different layers are connected to the same second write gate control line, while the second write gate sub-circuits 21 connected to write bit lines in different rows are connected to different second write gate control lines. For example, the second write gate sub-circuit 21 connected to the write bit lines in the first row across different layers is connected to the first second write gate control line S_BLw_1', and the second write gate sub-circuit 21 connected to the write bit lines in the nth row across different layers is connected to the nth second write gate control line S_BLw_n'. The number of second write gate control lines can be consistent with the number of rows of write bit lines included in a layer of a memory array. For example, if each layer of a memory array includes n rows of write bit lines, then the number of second write gate control lines is n.

[0057] In some embodiments, the second write gating sub-circuit 21 may include a third transistor T3, wherein a gate electrode of the third transistor T3 is connected to the second write gating control line, a first electrode is connected to the second end of the write bit line, and a second electrode is connected to the preset voltage terminal V_ref. The structure of the second write gating sub-circuit 21 described in this embodiment is merely an example, and other circuits capable of implementing gating may be used.

[0058] In some embodiments, the third transistor T3 is, for example, an N-type transistor, but the embodiments of the present disclosure are not limited thereto. The third transistor T3 may be a P-type transistor.

[0059] In some embodiments, the states of the first write gate sub-circuit 11 and the second write gate sub-circuit 21 connected to the same write bit line are opposite. That is, when the first write gate sub-circuit 11 is in the connected state, the second write gate sub-circuit 21 is in the disconnected state; when the first write gate sub-circuit 11 is in the disconnected state, the second write gate sub-circuit 21 is in the connected state. Accordingly, when the first transistor T1 and the third transistor T3 are transistors of the same type (for example, the first transistor T1 and the third transistor T3 are both N-type MOS transistors, or both are P-type MOS transistors), the signal polarity of the first write gate control line connected to the first write gate sub-circuit 11 connected to the same write bit line and the signal polarity of the second write gate control line connected to the second write gate sub-circuit 21 connected to the same write bit line are opposite. For example, when the first write gate control line S_BLw_1 connected to the write bit line BLw_1_k is at a high level, the second write gate control line S_BLw_1' connected to the write bit line BLw_1_k is at a low level. When the first transistor T1 and the third transistor T3 are transistors with opposite polarities (for example, one of the first transistor T1 and the third transistor T3 is an N-type MOS transistor and the other is a P-type MOS transistor), the signal polarity of the first write gate control line connected to the first write gate sub-circuit 11 connected to the same write bit line and the second write gate control line connected to the second write gate sub-circuit 21 connected to the write bit line are the same. For example, when the first write gate control line S_BLw_1 connected to the write bit line BLw_1_k is at a high level, the second write gate control line S_BLw_1' connected to the write bit line BLw_1_k is at a high level, thereby achieving opposite states of the first write gate sub-circuit 11 and the second write gate sub-circuit 21 connected to the same write bit line. In the solution provided by this embodiment, when a write bit line is selected (i.e., the signal of the common bit line is loaded onto the write bit line), the second write enable sub-circuit 21 connected to the write bit line is disconnected; when the write bit line is not selected, the second write enable sub-circuit 21 connected to the write bit line is turned on, so that the unselected write bit line is connected to the preset voltage terminal V_ref, thereby reducing the interference of the unselected write bit line on the selected write bit line.

[0060] In some embodiments, the read bit line may include a first end and a second end. The first end of the read bit line is connected to the first read gating sub-circuit 12, and the second end of the read bit line may be connected to a preset voltage terminal V_ref through a second read gating sub-circuit 22. The preset voltage terminal V_ref may be a low-level signal terminal, such as a ground terminal. The second read gating sub-circuit 22 is also connected to a second read gating control line. The second read gating sub-circuit 22 is configured to connect or disconnect the read bit line and the preset voltage terminal V_ref under the control of the second read gating control line. The second read gating sub-circuit 22 may connect unselected read bit lines to the preset voltage terminal V_ref to reduce interference. A memory cell may be connected to a position between the first and second ends of the read bit line.

[0061] In some embodiments, the second read gate control line may extend in a direction perpendicular to the substrate and penetrate memory arrays at different layers.

[0062] In some embodiments, the memory may include multiple voltage lines extending in a direction perpendicular to the substrate, the multiple voltage lines being distributed along the second direction Y, the voltage lines being connected to the preset voltage terminal V_ref, the write bit lines in the same row of different layers being connected to the same voltage line extending in a direction perpendicular to the substrate via different second write strobe sub-circuits 21, and the write bit lines in different rows being connected to different voltage lines extending in a direction perpendicular to the substrate via different second write strobe sub-circuits 21; the read bit lines in the same row of different layers being connected to the same voltage line extending in a direction perpendicular to the substrate via different second read strobe sub-circuits 22, and the read bit lines in different rows being connected to different voltage lines extending in a direction perpendicular to the substrate via different second read strobe sub-circuits 22. That is, multiple conductive lines may be provided to connect the bit lines (the read bit lines and the write bit lines) to the preset voltage terminal V_ref.

[0063] In some embodiments, the memory may include a conductive slot extending along the second direction Y, the conductive slot being connected to the preset voltage terminal V_ref, multiple write bit lines being connected to the conductive slot via different second write strobe sub-circuits 21, and multiple read bit lines being connected to the conductive slot via different second read strobe sub-circuits 22. That is, all read bit lines and write bit lines are connected to the conductive slot via the second read strobe sub-circuit 21 or the second write strobe sub-circuit 22. The conductive slot may be a surface electrode extending along the second direction Y, and the surface electrode is connected to the preset voltage terminal V_ref.

[0064] In some embodiments, the second read gating sub-circuits 22 connected to read bit lines in the same row across different layers are connected to the same second read gating control line, while the second read gating sub-circuits 22 connected to read bit lines in different rows are connected to different second read gating control lines. For example, the second read gating sub-circuit 22 connected to the read bit lines in the first row across different layers is connected to the first second read gating control line S_BLr_1', and the second read gating sub-circuit 22 connected to the read bit lines in the nth row across different layers is connected to the nth second read gating control line S_BLr_n'. The number of second read gating control lines can be consistent with the number of rows of read bit lines included in a layer of a memory array. For example, if each layer of a memory array includes n rows of read bit lines, then the number of second read gating control lines is n.

[0065] In some embodiments, the second read gating sub-circuit 22 may include a fourth transistor T4, wherein a gate electrode of the fourth transistor T4 is connected to the second read gating control line, a first electrode of the fourth transistor T4 is connected to the second end of the read bit line, and a second electrode of the fourth transistor T4 is connected to the preset voltage terminal V_ref. The structure of the second read gating sub-circuit 22 described in this embodiment is merely an example, and other circuits capable of implementing gating may be used.

[0066] In some embodiments, the fourth transistor T4 is, for example, an N-type transistor, but the embodiments of the present disclosure are not limited thereto. The fourth transistor T4 may be a P-type transistor.

[0067] In some embodiments, the states of the first read gating sub-circuit 12 and the second read gating sub-circuit 22 connected to the same read bit line are opposite. That is, when the first read gating sub-circuit 12 is in the on state, the second read gating sub-circuit 22 is in the off state; when the first read gating sub-circuit 12 is in the off state, the second read gating sub-circuit 22 is in the on state. Accordingly, when the second transistor T2 and the fourth transistor T4 are transistors of the same type (for example, the second transistor T2 and the fourth transistor T4 are both N-type MOS transistors, or both are P-type MOS transistors), the signal polarities of the first read gating control line connected to the first read gating sub-circuit 12 connected to the same read bit line and the second read gating control line connected to the second read gating sub-circuit 22 connected to the same read bit line are opposite. For example, when the first read gating control line S_BLr_1 connected to the read bit line BLr_1_k is at a high level, the second read gating control line S_BLr_1′ connected to the read bit line BLr_1_k is at a low level. When the second transistor T2 and the fourth transistor T4 are transistors with opposite polarities (for example, one of the second transistor T2 and the fourth transistor T4 is an N-type MOS transistor and the other is a P-type MOS transistor), the first read gating control line connected to the first read gating sub-circuit 12 connected to the same read bit line and the second read gating control line connected to the second read gating sub-circuit 22 connected to the same read bit line have the same signal polarity. For example, when the first read gating control line S_BLr_1 connected to the read bit line BLr_1_k is at a high level, the second read gating control line S_BLr_1' connected to the read bit line BLr_1_k is at a high level, thereby achieving opposite states of the first read gating sub-circuit 12 and the second read gating sub-circuit 22 connected to the same read bit line. In the solution provided by this embodiment, when a read bit line is selected (i.e., the signal of the common bit line is loaded onto the read bit line), the second read enable sub-circuit 22 connected to the read bit line is disconnected; when the read bit line is not selected, the second read enable sub-circuit 22 connected to the read bit line is turned on, so that the unselected read bit line is connected to the preset voltage terminal V_ref, thereby reducing the interference of the unselected read bit line on the selected read bit line.

[0068] An embodiment of the present disclosure provides a method for controlling access to a memory, which may include:

[0069] During the data reading or writing stage, according to the target layer and target row where the storage unit to be operated is located, an on-level signal is loaded on the first write select control line or the first read select control line connected to the write bit line or the read bit line of the target row (so that the first write select sub-circuit connected to the write bit line of the target row of different layers is in a connected state, or the first read select sub-circuit connected to the read bit line of the target row of different layers is in a connected state), and an off-level signal is loaded on the first write select control line or the first read select control line connected to the write bit line or the read bit line of the non-target row (so that the first write select sub-circuit connected to the write bit line of the non-target row of different layers is in an off state, or the first read select sub-circuit connected to the read bit line of the non-target row of different layers is in an off state).

[0070] The access control method provided in this embodiment implements bit line control through a common bit line, reduces control signals, and simplifies bit line control.

[0071] In some embodiments, the method may further include loading an off-level signal on a second write select control line or a second read select control line connected to the write bit line or the read bit line of the target row (so that the second write select sub-circuit of the word line of the target row of a different layer is in an off state, or the second read select sub-circuit connected to the read bit line of the target row of a different layer is in an off state), and loading an on-level signal on a second write select control line connected to the write bit line or the read bit line of the non-target row (so that the second write select sub-circuit connected to the write bit line of the non-target row of a different layer is in a connected state, or the second read select sub-circuit connected to the read bit line of the non-target row of a different layer is in a connected state). This embodiment provides a method for accessing a memory, which can realize the control of the read bit line or the write bit line using fewer control signals, thereby reducing the number of control lines.

[0072] The on-level signal is a signal that can put the corresponding gating sub-circuit in a connected state, and the off-level signal is a signal that can put the corresponding gating sub-circuit in a closed state.

[0073] The present disclosure also provides an electronic device comprising the memory device described in any of the preceding embodiments. The electronic device may be a storage device, a smartphone, a computer, a tablet computer, an artificial intelligence device, a wearable device, or a mobile power bank. The storage device may include, but is not limited to, computer memory.

[0074] Although the embodiments disclosed herein are as described above, the contents described herein are merely embodiments for facilitating understanding of the present invention and are not intended to limit the present invention. Any person skilled in the art may make any modifications and variations in the form and details of the embodiments without departing from the spirit and scope of the present invention. However, the scope of patent protection of the present invention shall remain subject to the scope defined by the appended claims.

Claims

1. A memory comprising: At least one layer of memory array, and a plurality of common bit lines corresponding one-to-one to each layer of memory array; Each layer of the memory array includes a plurality of memory cells, a plurality of read bit lines extending along a first direction parallel to the substrate, and a plurality of write bit lines extending along the first direction. The memory cells include at least a read transistor and a write transistor. The read transistor is connected to the read bit line, and the write transistor is connected to the write bit line. The read bit lines and the write bit lines of the same layer are connected to a common bit line corresponding to the memory array layer. Each of the write bit lines is connected to the common bit line via a first write enable sub-circuit, and each of the read bit lines is connected to the common bit line via a first read enable sub-circuit; the first write enable sub-circuit is also connected to a first write enable control line, and the first read enable sub-circuit is also connected to a first read enable control line; the first write enable sub-circuit is configured to: connect or disconnect the write bit line and the common bit line according to the control of the first write enable control line; the first read enable sub-circuit is configured to: connect or disconnect the read bit line and the common bit line according to the control of the first read enable control line.

2. The memory according to claim 1, wherein The memory includes a multi-layer memory array stacked in a direction perpendicular to a substrate, wherein the first write enable sub-circuits connected to the write bit lines in the same row of different layers are connected to the same first write enable control line, and the first write enable sub-circuits connected to the write bit lines in different rows are connected to different first write enable control lines; the first read enable sub-circuits connected to the read bit lines in the same row of different layers are connected to the same first read enable control line, and the first read enable sub-circuits connected to the read bit lines in different rows are connected to different first read enable control lines.

3. The memory according to claim 2, wherein The common bit line extends along a second direction parallel to the substrate, the first write gate control line extends along a direction perpendicular to the substrate, and the first read gate control line extends along a direction perpendicular to the substrate, and the first direction and the second direction intersect.

4. The memory according to claim 2, wherein The first end of each of the write bit lines is connected to the common bit line via a first write gating sub-circuit, the second end of each of the write bit lines is connected to a preset voltage terminal via a second write gating sub-circuit, and the second write gating sub-circuit is further connected to a second write gating control line; the first end of each of the read bit lines is connected to the common bit line via a first read gating sub-circuit, the second end of each of the read bit lines is connected to the preset voltage terminal via a second read gating sub-circuit, and the second read gating sub-circuit is further connected to a second read gating control line; The second write gate subcircuit is configured to: connect or disconnect the write bit line and the preset voltage terminal according to control of the second write gate control line; The second read gate sub-circuit is configured to connect or disconnect the read bit line and the preset voltage terminal according to control of the second read gate control line.

5. The memory according to claim 4, wherein The second write enable sub-circuits connected to the write bit lines of the same row in different layers are connected to the same second write enable control line, and the second write enable sub-circuits connected to the write bit lines of different rows are connected to different second write enable control lines; the second read enable sub-circuits connected to the read bit lines of the same row in different layers are connected to the same second read enable control line, and the second read enable sub-circuits connected to the read bit lines of different rows are connected to different second read enable control lines. The memory according to claim 5 , wherein: The first write gate subcircuit and the second write gate subcircuit connected to the same write bit line are configured in opposite states; the first read gate subcircuit and the second read gate subcircuit connected to the same read bit line are configured in opposite states.

7. The memory according to claim 5, wherein The second write gate control line extends in a direction perpendicular to the substrate, and the second read gate control line extends in a direction perpendicular to the substrate.

8. The memory according to claim 4, wherein The memory includes a plurality of voltage lines extending in a direction perpendicular to the substrate, the plurality of voltage lines being distributed along the second direction, and the voltage lines being connected to the preset voltage terminal; write bit lines in the same row of different layers being connected to the same voltage line extending in a direction perpendicular to the substrate via different second write selection sub-circuits, and write bit lines in different rows being connected to different voltage lines extending in the direction perpendicular to the substrate via different second write selection sub-circuits; read bit lines in the same row of different layers being connected to the same voltage line extending in a direction perpendicular to the substrate via different second read selection sub-circuits, and read bit lines in different rows being connected to different voltage lines extending in the direction perpendicular to the substrate via different second read selection sub-circuits; Alternatively, the memory includes a conductive slot extending along the second direction, the conductive slot is connected to the preset voltage terminal, multiple write bit lines are connected to the conductive slot through different second write enable sub-circuits, and multiple read bit lines are connected to the conductive slot through different second read enable sub-circuits.

9. An electronic device comprising the memory according to any one of claims 1 to 8.

10. A method for accessing a memory according to any one of claims 1 or 8, comprising: In the data writing phase or the data reading phase, according to the target layer and the target row where the storage unit to be operated is located, an on-level signal is loaded on the first write select control line or the first read select control line connected to the write bit line or the read bit line of the target row, and an off-level signal is loaded on the first write select control line or the first read select control line connected to the write bit line or the read bit line of the non-target row.

11. The memory access method according to claim 10, further comprising: A shutoff level signal is loaded on the second write gate control line or the second read gate control line connected to the write bit line or the read bit line of the target row, and an on level signal is loaded on the second write gate control line connected to the write bit line or the read bit line of the non-target row.

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