Display panel and display apparatus

Abstract

A display panel and a display apparatus. The display panel comprises a display region, the display region comprising multiple columns of sub-pixels sequentially distributed at intervals in a row direction (X), and a data signal line being provided at each of a side of a first column of sub-pixels (Pixel-F) distant from the last column of sub-pixels (Pixel-L) and a side of the last column of sub-pixels (Pixel-L) distant from the first column of sub-pixels (Pixel-F). The display panel may provide, by means of a first data signal line (DT1), a data signal for part of a second column of sub-pixels partially shielded by an outer frame (BMO), and provide, by means of a subsequent second data signal line, a data signal for the other sub-pixels in the second column, thereby enabling each sub-pixel in the second column to be pre-charged. Similarly, each sub-pixel of a second-to-last column of sub-pixels which are partially shielded by the outer frame (BMO) is also able to be pre-charged, which can thus solve the problems of uneven brightness and poor display at an edge.

Description

Display panel and display device

[0001] Cross-references

[0002] This disclosure claims priority to Chinese patent application number 202310553950.6 filed on May 15, 2023, entitled “A display panel and display device”, the entire contents of which are incorporated herein by reference. Technical Field

[0003] The present disclosure relates to the field of display technology, and in particular to a display panel and a display device. Background Art

[0004] In order to increase product profits, existing display products reduce costs by reducing the number of COFs (Chip on Film) in the panel.

[0005] In the related art, in order to adapt to the low-cost product architecture, the display product has the problem of uneven brightness at the edges, which is manifested as jagged edges.

[0006] It should be noted that the information disclosed in the above background technology section is only used to enhance the understanding of the background of the present disclosure, and therefore may include information that does not constitute prior art known to ordinary technicians in the field.

[0007] Summary of the Invention

[0008] The purpose of the present disclosure is to overcome the above-mentioned deficiencies of the prior art and to provide a display panel and a display device.

[0009] According to one aspect of the present disclosure, a display panel is provided, comprising a display area, wherein the display area comprises a plurality of columns of sub-pixels spaced apart in a row direction, and data signal lines are provided on a side of the first column of sub-pixels away from a side of the last column of sub-pixels and on a side of the last column of sub-pixels away from the first column of sub-pixels.

[0010] In an exemplary embodiment of the present disclosure, the display panel includes a color film substrate, which includes: a first base substrate; a color resist layer located on one side of the first base substrate and in the display area, the color resist layer including a plurality of sub-pixels distributed in an array; a border area circumferentially arranged around the display area, the border area including a first border and a second border arranged opposite to each other in the row direction; wherein the orthographic projection of the first border on the first base substrate covers the orthographic projection of the first column of sub-pixels on the first base substrate and partially overlaps with the orthographic projection of the second column of sub-pixels on the first base substrate; the orthographic projection of the second border on the first base substrate covers the orthographic projection of the last column of sub-pixels on the first base substrate and partially overlaps with the orthographic projection of the second to last column of sub-pixels on the first base substrate.

[0011] In an exemplary embodiment of the present disclosure, the data signal line on the side of the first column of sub-pixels away from the last column of sub-pixels is the first data signal line, and the data signal line on the side of the last column of sub-pixels away from the first column of sub-pixels is the penultimate data signal line. The first data signal line is electrically connected to part of the sub-pixels in the second pixel column, and the penultimate data signal line is electrically connected to part of the sub-pixels in the second to last column.

[0012] In an exemplary embodiment of the present disclosure, the first data signal line is also electrically connected to some sub-pixels in the first pixel column, and the sub-pixels in the first pixel column connected to the first data signal line and the sub-pixels in the second pixel column connected to the first data signal line are located in the same row; the penultimate data signal line is also electrically connected to some sub-pixels in the Nth pixel column, and the sub-pixels in the Nth pixel column connected to the penultimate data signal line and the sub-pixels in the (N-1)th pixel column connected to the penultimate data signal line are located in the same row.

[0013] In an exemplary embodiment of the present disclosure, among the sub-pixels in the same pixel column, the sub-pixels located in odd rows are connected to the same data signal line, and the sub-pixels located in even rows are connected to another data signal line; among the two adjacent columns of sub-pixels distributed on both sides of the same data signal line, the sub-pixels in the even rows of the previous column and the sub-pixels in the odd rows of the next pixel column are connected to the same data signal line; among the two columns of sub-pixels distributed between two adjacent data signal lines, the sub-pixels in odd rows are connected to the previous data signal line, and the sub-pixels in even rows are connected to the next data signal line.

[0014] In an exemplary embodiment of the present disclosure, the display panel includes a driving substrate and a color filter substrate arranged in a box, the sub-pixels are located on the color filter substrate, and the color resist layer includes a plurality of sub-pixels distributed in an array along the row and column directions; the driving substrate includes: a second base substrate; a common electrode layer, located on one side of the second base substrate, the common electrode layer includes: a plurality of common electrode lines, located in the display area, the orthographic projections of the plurality of common electrode lines on the second base substrate extending along the column direction and distributed in sequence at intervals in the row direction; a source-drain metal layer, located on the side of the common electrode layer away from the second base substrate, the source-drain metal layer including a plurality of data signal lines; wherein the display panel includes a plurality of data signal lines, the orthographic projections of the data signal lines and the common electrode lines on the second base substrate are both located between the orthographic projections of two adjacent columns of sub-pixels on the second base substrate, and the orthographic projections of the plurality of data signal lines and the plurality of common electrode lines on the second base substrate are distributed alternately in sequence in the row direction.

[0015] In an exemplary embodiment of the present disclosure, the display area includes n columns of sub-pixels, m data signal lines and k common electrode lines, where m=n / 2+1, k=n / 2, n is a natural number greater than or equal to 2, and m and k are both natural numbers.

[0016] In an exemplary embodiment of the present disclosure, the display panel includes a plurality of pixel driving circuits, each including a transistor, wherein the gate of each transistor is connected to a gate signal terminal. The display panel includes a driving substrate and a color filter substrate arranged in a cell-to-cell manner. The driving substrate includes: a second base substrate; a gate metal layer located on one side of the second base substrate, the gate metal layer including: a plurality of conductive blocks located in a non-display area of ​​the display panel, the conductive blocks connected to output signal lines of a shift register unit through vias; a plurality of gate signal lines located in a display area, the gate signal lines connected to the conductive blocks, and portions of the gate signal lines forming gates of the transistors. The orthographic projections of some of the conductive blocks on the second base substrate are located within the orthographic projections of the first frame on the second base substrate, and the orthographic projections of some of the conductive blocks on the second base substrate are located within the orthographic projections of the second frame on the second base substrate. Any two adjacent sub-pixels in a row direction have a first spacing in the row direction, and the shortest distance in the row direction between the orthographic projections of the conductive blocks and their adjacent sub-pixels on the second base substrate matches the first spacing.

[0017] In an exemplary embodiment of the present disclosure, a ratio of the shortest distance between the conductive block and its adjacent sub-pixel on the second base substrate in the row direction to the first interval is greater than or equal to 0.8 and less than or equal to 1.2.

[0018] In an exemplary embodiment of the present disclosure, the shortest distance is greater than or equal to 18 μm and less than or equal to 26 μm.

[0019] In an exemplary embodiment of the present disclosure, the border area also includes a third border and a fourth border arranged opposite to each other in the column direction; the display panel also includes: a fan-out area, located on the side of the third border away from the display area, the fan-out area includes: a plurality of data fan-out lines, one data signal line is connected to one data fan-out line, an electrostatic release unit is connected between the first data signal line and the corresponding data fan-out line, and between the penultimate data signal line and the corresponding data fan-out line, and the electrostatic release unit is also connected to the common electrode line.

[0020] In an exemplary embodiment of the present disclosure, the display panel further includes a plurality of chips, and the fan-out area further includes a plurality of virtual data fan-out lines; wherein the number of data channels of the chip is equal to the sum of the number of corresponding data fan-out lines and virtual data fan-out lines.

[0021] In an exemplary embodiment of the present disclosure, the number of virtual data fan-out lines corresponding to at least some chips is different from the number of virtual data fan-out lines corresponding to other chips.

[0022] In an exemplary embodiment of the present disclosure, the plurality of chips include a first chip connected to the first data signal line and a second chip connected to the penultimate data signal line; the number of virtual data fan-out lines corresponding to the first chip and the number of virtual data fan-out lines corresponding to the second chip are both less than the number of virtual data fan-out lines corresponding to other chips.

[0023] In an exemplary embodiment of the present disclosure, each of the first chip and the second chip corresponds to one virtual data fan-out line.

[0024] In an exemplary embodiment of the present disclosure, the border area also includes a third border and a fourth border arranged opposite to each other in the column direction; the first data signal line and the penultimate data signal line are both connected to an electrostatic release unit in the non-display area on one side of the fourth border, and the electrostatic release unit is also connected to a common electrode line.

[0025] According to a second aspect of the present disclosure, a display device is further provided, comprising the display panel described in any embodiment of the present disclosure.

[0026] In the display panel provided by the present disclosure, a data signal line is provided on the side of the first column of sub-pixels away from the last column of sub-pixels and on the side of the last column of sub-pixels away from the first column of sub-pixels. Taking the data signal line on the side of the first column of sub-pixels away from the last column of sub-pixels as the first data signal line and the data signal line on the side of the last column of sub-pixels away from the first column of sub-pixels as the penultimate data signal line as an example, in this way, the first data signal line can be used to provide data signals to some sub-pixels in the second column that are partially blocked by the outer frame, and the second data signal line that follows can be used to provide data signals to other sub-pixels in the second column, so that all sub-pixels in the second column can be pre-charged. Similarly, some sub-pixels in the penultimate column that are partially blocked by the outer frame can be provided with data signals through the last data signal line, and other sub-pixels in the penultimate column can be provided with data signals through the penultimate data signal line. In this way, all sub-pixels in the penultimate column that are partially blocked by the outer frame can be pre-charged. Therefore, the display panel disclosed by the present disclosure can solve the problem of uneven display of edges due to uneven brightness.

[0027] It is to be understood that the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] The accompanying drawings are incorporated into and constitute a part of the specification, illustrate embodiments consistent with the present disclosure, and together with the specification, are used to explain the principles of the present disclosure. Obviously, the drawings described below are only some embodiments of the present disclosure, and those skilled in the art can derive other drawings based on these drawings without inventive effort.

[0029] FIG1 is a schematic structural diagram of a display panel according to an embodiment of the present disclosure;

[0030] FIG2 is a partial enlarged view of the left and right side frames in FIG1 ;

[0031] FIG3 is a schematic cross-sectional view of a display panel according to an embodiment of the present disclosure;

[0032] FIG4 is a schematic diagram showing the distribution of data signal lines in the related art;

[0033] FIG5 is a schematic diagram showing connections between sub-pixels and data signal lines according to an embodiment of the present disclosure;

[0034] FIG6 is a schematic diagram of wiring of a display panel according to an embodiment of the present disclosure;

[0035] FIG7 is a partial enlarged view of point M in FIG6 . DETAILED DESCRIPTION

[0036] Example embodiments will now be described more fully with reference to the accompanying drawings. However, the example embodiments can be implemented in many forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete and will fully convey the concepts of the example embodiments to those skilled in the art. Like reference numerals in the figures represent identical or similar structures, and thus their detailed descriptions will be omitted. Furthermore, the figures are merely schematic illustrations of the present disclosure and are not necessarily drawn to scale.

[0037] Although relative terms such as "upper" and "lower" are used in this specification to describe the relationship of one illustrated component to another, these terms are used for convenience only, such as in accordance with the orientation of the illustrations in the accompanying drawings. It should be understood that if the illustrated device were flipped upside down, the component described as "upper" would become the component "lower." When a structure is referred to as "on" another structure, it may mean that the structure is integrally formed with the other structure, that the structure is "directly" disposed on the other structure, or that the structure is "indirectly" disposed on the other structure through the other structure.

[0038] The terms "a", "an", "the", "said" and "at least one" are used to indicate the presence of one or more elements / components / etc.; the terms "including" and "having" are used to express open-ended inclusion and mean that additional elements / components / etc. may be present in addition to the listed elements / components / etc.; the terms "first", "second" and "third" etc. are used only as labels and are not intended to limit the quantity of their objects.

[0039] Figure 1 is a schematic structural diagram of a display panel according to an embodiment of the present disclosure, and Figure 2 is a partial enlarged view of the left and right side frames in Figure 1. As shown in Figures 1 and 2, the display panel may include a display area, and the display area includes a plurality of columns of sub-pixels spaced in sequence in the row direction X. Data signal lines Data are provided on a side of the first column of sub-pixels Pixel-F away from the last column of sub-pixels Pixel-L, and on a side of the last column of sub-pixels Pixel-L away from the first column of sub-pixels Pixel-F.

[0040] In the display panel provided by the present disclosure, a data signal line Data is provided on both the side of the first column of sub-pixels Pixel-F away from the last column of sub-pixels Pixel-L and the side of the last column of sub-pixels Pixel-L away from the first column of sub-pixels Pixel-F. For example, the data signal line Data on the side of the first column of sub-pixels Pixel-F away from the last column of sub-pixels Pixel-L is the first data signal line DT1, and the data signal line Data on the side of the last column of sub-pixels Pixel-L away from the first column of sub-pixels Pixel-F is the penultimate data signal line DTN. In this manner, data signals can be provided to a portion of the sub-pixels in the second column partially obscured by the outer frame BMO via the first data signal line DT1, and data signals can be provided to another portion of the sub-pixels in the second column via the subsequent second data signal line Data, thereby enabling pre-charging of all sub-pixels in the second column. Similarly, a portion of the sub-pixels in the second-to-last column partially obscured by the outer frame BMO can be provided with data signals via the last data signal line Data, and the remaining sub-pixels in the second-to-last column can be provided with data signals via the penultimate data signal line Data. In this manner, all sub-pixels in the second-to-last column partially obscured by the outer frame BMO can be pre-charged. Therefore, the display panel disclosed in the present invention can solve the problem of uneven display of edges.

[0041] The display panel disclosed herein may be a liquid crystal display panel. FIG3 is a schematic cross-sectional view of a display panel according to one embodiment of the present disclosure. As shown in FIG3 , the liquid crystal display panel may include a color filter substrate and a drive substrate arranged in a cell-to-cell configuration. A frame and a color resist layer CL are provided on the color filter substrate. Data signal lines Data, pixel electrodes Vpixel, and common electrodes Vcon are provided on the drive substrate.

[0042] As shown in FIG1 , the display panel of the present disclosure may include an outer frame BMO and an inner frame BMI. The outer frame BMO may include a first frame GPL and a second frame GPR arranged opposite each other in the row direction X, and a third frame DP and a fourth frame DPO arranged opposite each other in the column direction Y. Both the outer frame BMO and the inner frame BMI may be black matrices. The outer frame BMO is primarily used to prevent light leakage from sub-pixels at the edge of the display area. The inner frame BMI may be in a grid shape, and may be used to isolate adjacent light-emitting areas to prevent light leakage and color mixing. This will not be further described here.

[0043] For ease of description, this disclosure only uses the example of the first column of sub-pixels, Pixel-F, being the leftmost column of sub-pixels in FIG2 , and the last column of sub-pixels, Pixel-L, being the rightmost column of sub-pixels in FIG2 . It is understood that, from left to right in FIG2 , the first column of sub-pixels, Pixel-F, the second column of sub-pixels, ..., the second-to-last column of sub-pixels, and the last column of sub-pixels, Pixel-L, are sequentially shown.

[0044] Data signal lines Data are provided on the side of the first column of sub-pixels Pixel-F away from the last column of sub-pixels Pixel-L, and on the side of the last column of sub-pixels Pixel-L away from the first column of sub-pixels Pixel-F, that is, data signal lines Data are provided on the left side of the first column of sub-pixels Pixel-F and on the right side of the last column of sub-pixels Pixel-L in Figures 1 and 2, that is, data signal lines Data are provided on both the left and right sides of the display area. The purpose of arranging the data signal lines Data in this way in the present disclosure is that by arranging the data signal lines Data on both the left and right sides of the display area, when the outer frame BMO of the display panel blocks the first and last columns of sub-pixels Pixel-L, the light-emitting area of ​​the display panel is equivalent to the second column of sub-pixels to the second to last column of sub-pixels. In this way, the two data signal lines Data on both sides of the display area can be used to provide data signals to part of the sub-pixels in the second column and part of the sub-pixels in the second to last column, respectively, so that these sub-pixels can be pre-charged. In addition, the other sub-pixels in the second column and the second-to-last column can be pre-charged through other connected data signal lines Data, so that the sub-pixels in the first column and the last column of the effective display area of ​​the display panel of the present disclosure can be pre-charged.

[0045] It should be understood that the pre-charging of a sub-pixel using a certain data signal line Data described in the present disclosure means that the gate signal line Gate connected to the sub-pixel is controlled to be turned on in advance so that the data signal line Data connected to the sub-pixel can write a data signal to the sub-pixel in advance.

[0046] The present disclosure will be further described below with reference to the accompanying drawings.

[0047] In conjunction with Figures 2 and 3, the color filter substrate may include a first base substrate BP1, a color resist layer CL located on one side of the first base substrate BP1 and located in the display area, the color resist layer CL including a plurality of sub-pixels distributed in an array; a border area BMA circumferentially arranged around the display area, the border area BMA including the aforementioned first border GPL and second border GPR arranged opposite to each other in the row direction X, and a third border DP and fourth border DPO arranged opposite to each other in the column direction Y. The orthographic projection of the first border GPL on the first base substrate BP1 covers the orthographic projection of the first column of sub-pixels Pixel-F on the first base substrate BP1 and partially overlaps with the orthographic projection of the second column of sub-pixels on the first base substrate BP1. That is, after the color filter substrate and the drive substrate are aligned, the first border GPL completely blocks the first column of sub-pixels Pixel-F, so that the first column of sub-pixels Pixel-F does not emit light. At the same time, the first border GPL also partially blocks the second column of sub-pixels, so that the second column of sub-pixels is the left edge of the actual light-emitting area of ​​the display panel. Similarly, the orthographic projection of the second frame GPR on the first substrate BP1 covers the orthographic projection of the last column of sub-pixels Pixel-L on the first substrate BP1 and partially overlaps with the orthographic projection of the second-to-last column of sub-pixels on the first substrate BP1, that is, after the color filter substrate and the drive substrate are set in a box, the second frame GPR completely blocks the last column of sub-pixels Pixel-L, so that the last column of sub-pixels Pixel-L will not emit light. At the same time, the second frame GPR also partially blocks the second-to-last column of sub-pixels, so that the second-to-last column of sub-pixels is the right edge of the actual light-emitting area of ​​the display panel. In this way, the first column of sub-pixels Pixel-F and the last column of sub-pixels Pixel-L are blocked by the outer frame BMO and cannot emit light, so the actual display area of ​​the display panel is the second column of sub-pixels to the second-to-last column of sub-pixels. The present disclosure is to solve the problem of uneven brightness of the second column of sub-pixels and the second-to-last column of sub-pixels.

[0048] FIG4 is a schematic diagram of the distribution of data signal lines in the related art. As shown in FIG4 , in the related art, the first data signal line Data is located between the first column of sub-pixels Pixel-F and the second column of sub-pixels, and the last data line is located between the last column of sub-pixels Pixel-L and the second-to-last column of sub-pixels. The first data signal line Data connects to some sub-pixels in the second column, while the remaining sub-pixels in the second column are connected to the second data signal line Data. This results in some sub-pixels connected to the first data signal line Data being unable to be precharged, i.e., some sub-pixels in the second column cannot be precharged. While the first data signal line Data is used to charge some sub-pixels in the second column connected to it, the second data signal line Data can be used to precharge the remaining sub-pixels in the second column connected to it, i.e., the sub-pixels in the second column connected to the second data signal line Data can be precharged. This results in some sub-pixels in the second column being able to be precharged while others are not, resulting in uneven brightness of the sub-pixels in the second column during display, i.e., display defects manifested as jagged edges. Similarly, the second-to-last column of sub-pixels will also show uneven brightness and jagged edges when displayed.

[0049] Figure 5 is a connection diagram of sub-pixels and data signal lines according to an embodiment of the present disclosure. As shown in Figure 5, in the display panel of the present disclosure, the data signal line Data on the side of the first column of sub-pixels Pixel-F away from the last column of sub-pixels Pixel-L is the first data signal line DT1, and the data signal line Data on the side of the last column of sub-pixels Pixel-L away from the first column of sub-pixels Pixel-F is the penultimate data signal line DTN. The first data signal line DT1 can be electrically connected to some sub-pixels in the second pixel column, and the penultimate data signal line DTN can be electrically connected to some sub-pixels in the second to last column. In this way, the first data signal line DT1 can be used to provide data signals for some sub-pixels in the second column. In this way, through timing design, the first data signal line DT1 can be used to pre-charge some sub-pixels connected to it in the second column in advance. For example, in the process of the first data signal line DT1 providing data signals to the sub-pixels Pixel-F in the first column, the data signals are synchronously provided to the sub-pixels in the second column, that is, the charging time of the sub-pixels in the second column partially overlaps with the charging time of the sub-pixels Pixel-F in the first column. For example, the conduction level of the gate signal line Gate connected to the sub-pixels Pixel-F in the first column and the conduction level of the gate signal line Gate connected to the sub-pixels in the second column are set to partially overlap, so that the data writing time of the sub-pixels in the second column connected to the first data signal line DT1 can partially overlap with the data writing time of the sub-pixels Pixel-F in the first column, so that the sub-pixels in the second column connected to the first data signal line DT1 can be pre-charged. Since the other sub-pixels in the second column are connected to the second data signal line Data, the second data signal line Data can be used to write data signals to the remaining sub-pixels in the second column during the process of writing data signals on the first data signal line DT1. Therefore, the remaining sub-pixels in the second column can also be pre-charged. In this way, by setting the first data signal line DT1 on the side of the first column sub-pixel Pixel-F away from the last column sub-pixel Pixel-L, each sub-pixel in the second column can be pre-charged, that is, the first column sub-pixel Pixel-F that is actually displayed can be pre-charged. Similarly, by setting the penultimate data signal line DTN on the side of the last column sub-pixel Pixel-L away from the first column sub-pixel Pixel-F, and allowing the penultimate data signal line DTN to connect to some sub-pixels in the second-to-last column, data signals can be provided to some sub-pixels in the second-to-last column through the penultimate data signal line DTN. At the same time, the remaining sub-pixels in the second-to-last column are connected to the second-to-last data signal line Data, that is, the second-to-last data signal line Data can be used to provide data signals for the remaining sub-pixels in the second-to-last column, so that each sub-pixel in the second-to-last column can be pre-charged, that is, the last column of sub-pixels Pixel-L actually displayed can all be pre-charged.Therefore, the display panel disclosed in the present invention can solve the problem of jagged display defects caused by uneven brightness at the edges.

[0050] As shown in Figure 5, in an actual product, the first data signal line DT1 can also be connected to some of the sub-pixels in the first column, and the remaining sub-pixels in the first column can be connected to the second subsequent data signal line Data, so that the connection method between the sub-pixels Pixel-F in the first column and the data signal line Data is the same as the connection method between the sub-pixels in the subsequent pixel columns and the data signal line Data. Similarly, the first-to-last data signal line DTN can also be connected to some of the sub-pixels in the last column, and the remaining sub-pixels in the last column can be connected to the second-to-last data signal line Data. Of course, in other embodiments, the sub-pixels Pixel-F in the first column and the sub-pixels Pixel-L in the last column can also be not connected to the data signal line Data, as long as the data signal lines Data have the above-mentioned arrangement.

[0051] Continuing with FIG. 5 , in the display panel of the present disclosure, among the subpixels in the same pixel column, those in odd-numbered rows are connected to the same data signal line (Data), while those in even-numbered rows are connected to another data signal line (Data). In two adjacent columns of subpixels located on either side of the same data signal line (Data), the even-numbered subpixels in the preceding column and the odd-numbered subpixels in the succeeding column are connected to the same data signal line (Data). In the two columns of subpixels between two adjacent data signal lines (Data), the odd-numbered subpixels are connected to the preceding data signal line (Data), while the even-numbered subpixels are connected to the succeeding data signal line (Data).

[0052] For example, taking the second pixel column as an example, the sub-pixels in the first, third, fifth, and other odd-numbered rows of the second pixel column are all connected to the first data signal line DT1, while the sub-pixels in the second, fourth, sixth, and other even-numbered rows of the second pixel column are all connected to the second data signal line Data. In this way, some of the sub-pixels in the second pixel column can be pre-charged using the first data signal line DT1, while the remaining sub-pixels can be pre-charged using the second data signal line Data.

[0053] The fourth column of sub-pixels and the fifth column of sub-pixels are distributed on both sides of the third data signal line Data, then the second row of sub-pixels, the fourth row of sub-pixels, the sixth row of sub-pixels... and other even-numbered rows of sub-pixels in the fourth pixel column and the first row of sub-pixels, the third row of sub-pixels, the fifth row of sub-pixels... and other odd-numbered rows in the fifth pixel column are all connected to the third data signal line Data.

[0054] The first pixel column and the second pixel column are located between the first data signal line and the second data signal line, then the first row of sub-pixels, the third row of sub-pixels, the fifth row of sub-pixels... and other odd-numbered row sub-pixels of the first pixel column and the second pixel column are all connected to the first data signal line, and the second row of sub-pixels, the fourth row of sub-pixels, the sixth row of sub-pixels... and other even-numbered row sub-pixels of the first pixel column and the second pixel column are all connected to the second data signal line.

[0055] Furthermore, as shown in FIG3 , the drive substrate may include a second base substrate BP2 and a common electrode layer located on one side of the second base substrate BP2. The common electrode layer may include a plurality of common electrode lines COM and a common electrode Vcom. As shown in FIG2 , the orthographic projections of the data signal lines Data and the common electrode lines COM distributed within the display area on the second base substrate BP2 are both located between the orthographic projections of two adjacent columns of sub-pixels on the second base substrate BP2, and the orthographic projections of the plurality of data signal lines Data and the plurality of common electrode lines COM on the second base substrate BP2 are alternately distributed in the row direction X.

[0056] In combination with Figures 2 and 4, the display panel disclosed herein can, based on the display panel described in Figure 1, shift the data signal line Data and the common electrode line COM to the left, and then add a data signal line Data to the right side of the last column of sub-pixels Pixel-L, and add a common electrode line COM between the last column of sub-pixels Pixel-L and the second-to-last column of sub-pixels, so that the data signal line Data has the arrangement structure shown in the present disclosure, and then the data signal line is connected to the corresponding sub-pixel according to the connection method shown in Figure 5.

[0057] Continuing to refer to FIG2 , in the display panel disclosed herein, the display area may include n columns of sub-pixels, m data signal lines Data, and k common electrode lines COM, wherein m=n / 2+1, k=n / 2, n is a natural number greater than or equal to 2, and m and k are both natural numbers. For example, the display area may include 4000 columns of sub-pixels, then the number of data signal lines Data in the present disclosure is 2001, and the number of common electrode lines COM is 2000. By comparing FIG4 , it can be seen that in the related art, the number of data signal lines Data is 2000, and the number of common electrode lines COM is 1999. Obviously, in the display panel disclosed herein, the number of data signal lines Data and common electrode lines COM are different from the number of data signal lines Data and common electrode lines COM in the related art.

[0058] In addition, other structures in the peripheral area of ​​the display panel disclosed in the present invention also have certain differences compared to those in the related art, which will be further explained below with reference to the accompanying drawings.

[0059] Figure 6 is a schematic diagram of the wiring of a display panel according to an embodiment of the present disclosure. The figure only exemplifies the structural schematic diagram of some sub-pixels and some data signal lines Data of the display panel on the second frame GPR side, the third frame DP side and the fourth frame DPO side. It should be understood that in the actual product, there are a large number of pixel rows between the third frame DP and the fourth frame DPO. Here, only three rows and five columns of sub-pixels are used to exemplify the wiring method of the data signal line Data. In an exemplary embodiment, the display panel also includes a fan-out area, which is located on the side of the third frame DP away from the display area. As shown in Figure 6, the fan-out area may include multiple data fan-out lines FIP, and one data signal line Data is connected to one data fan-out line FIP. An electrostatic discharge unit ESD (Electro static Discharge) is connected between the first data signal line DT1 and the corresponding data fan-out line FIP, and between the penultimate data signal line DTN and the corresponding data fan-out line FIP. The electrostatic discharge unit ESD is also connected to the common electrode line COM. One end of the data fan-out line FIP is bound and connected to the chip, and the other end is connected to the data signal line Data via the electrostatic discharge unit ESD. That is, the chip's data signal is transmitted to the corresponding data signal line Data via the data fan-out line FIP. It should be understood that in this exemplary embodiment, the first data signal line DT1 and the penultimate data signal line DTN are both connected to the corresponding data fan-out line FIP via the electrostatic discharge unit ESD. That is, the first data signal line DT1 and the penultimate data signal line DTN have the same structure as other data signal lines Data connected to the data fan-out line FIP. The electrostatic discharge unit ESD is also connected to the common electrode line COM. The electrostatic discharge unit ESD can release large currents through the common electrode line COM to prevent large currents from damaging the data signal line Data.

[0060] As you can see, a chip can have multiple data channels, each of which is connected to a corresponding data fan-out line (FIP). In actual products, the number of channels on a chip can be greater than the number of data fan-out lines (FIPs). In this case, the fan-out area can also include multiple dummy data fan-out lines (Dummy), so that the sum of the number of dummy data fan-out lines and data fan-out lines (FIPs) equals the number of channels on the chip. The provision of dummy data fan-out lines (Dummy) can improve panel uniformity.

[0061] It is worth noting that the data fan-out line FIP corresponding to a chip described in the present disclosure refers to the data fan-out line FIP connected to the chip. The virtual data fan-out line Dummy corresponding to a chip refers to the virtual data fan-out line Dummy located between the data fan-out line FIP connected to the chip and the data fan-out line FIP connected to the adjacent chip.

[0062] Furthermore, in the display panel disclosed herein, the number of virtual data fan-out lines Dummy corresponding to at least some chips is different from the number of virtual data fan-out lines Dummy corresponding to other chips. For example, a plurality of chips may include a first chip connected to the first data signal line DT1, a second chip connected to the last-to-last data signal line DTN, and other chips. The number of virtual data fan-out lines Dummy corresponding to the first chip and the number of virtual data fan-out lines Dummy corresponding to the second chip are both less than the number of virtual data fan-out lines Dummy corresponding to other chips. For example, a display panel may be bound and connected with six chips. The first chip needs to be connected to the first data signal line DT1 through the data fan-out line FIP connected thereto, and the second chip needs to be connected to the last-to-last data signal line DTN through the data fan-out line FIP connected thereto. The number of virtual data fan-out lines Dummy corresponding to the first chip and the second chip is reduced compared to the number of virtual data fan-out lines Dummy of other chips. For example, the number of virtual data fan-out lines Dummy of other chips may be two. The first chip and the second chip each correspond to one virtual data fan-out line Dummy. Of course, the number of virtual data fan-out lines Dummy may be different in different products, and may be determined specifically according to the number of channels of the chip.

[0063] Continuing with FIG6 , in this exemplary embodiment, the connection structure of the first data signal line DT1 and the penultimate data signal line DTN at the fourth border DPO is the same as the connection structure of the other data signal lines Data at the fourth border DPO. For example, the first data signal line DT1 and the penultimate data signal line DTN are each connected to an electrostatic discharge unit ESD at the fourth border DPO. The electrostatic discharge unit ESD is also connected to the common electrode line COM, so that the electrostatic discharge unit ESD protects the other end of the data signal line Data.

[0064] As shown in Figure 6, the penultimate data signal line DTN is located between the last column of sub-pixels Pixel-L and the non-display area. Therefore, in this exemplary embodiment, it is necessary to increase the spacing distance between the penultimate column of sub-pixels Pixel-F and the boundary of the non-display area to ensure the routing space of the penultimate data signal line DTN.

[0065] As described above, the display panel of the present disclosure may include a driving substrate and a color film substrate arranged in a box. In an exemplary embodiment, the driving substrate may include a second base substrate BP2 and a gate metal layer. The gate metal layer is located on one side of the second base substrate BP2. The gate metal layer may include a plurality of conductive blocks 100 located in a non-display area and a plurality of gate signal lines Gate located in a display area. Part of the structure of the gate signal line Gate is used to form the gate of the transistor T. The conductive block 100 is located in the non-display area near the edge of the display area. On the one hand, the conductive block 100 is connected to the output signal line of the shift register unit through a via, and on the other hand, it is also connected to the gate signal line Gate, that is, the output signal line of the shift register unit in the non-display area is connected to the gate signal line Gate in the display area through the conductive block 100, so as to provide a gate control signal to the transistor T through the gate signal line Gate.

[0066] The orthographic projection of part of the conductive block 100 on the second substrate BP2 is located within the orthographic projection of the first frame GPL on the second substrate BP2, and the orthographic projection of part of the conductive block 100 on the second substrate BP2 is located within the orthographic projection of the second frame GPR on the second substrate BP2, that is, a plurality of conductive blocks 100 are distributed at the first frame GPL and the second frame GPR, wherein any two adjacent sub-pixels in the row direction X have a first interval d1 in the row direction X, and the shortest distance d0 between the orthographic projection of the conductive block 100 and the adjacent sub-pixel in the row direction X on the second substrate BP2 matches the first interval d1.

[0067] Specifically, FIG7 is a partial enlarged view of point M in FIG6 . Combining FIG6 and FIG7 , the first interval d1 represents the pixel size of the two sub-pixels in the row direction X. The conductive block 100 is located at the edge of the non-display area. Thus, the shortest distance d0 between the orthographic projection of the conductive block 100 and its adjacent sub-pixels on the second substrate BP2 in the row direction X is the shortest distance d0 between the first column of sub-pixels Pixel-F or the last column of sub-pixels Pixel-L and the boundary of the non-display area. Obviously, this shortest distance d0 represents the spacing between the left sub-pixel and the left boundary of the non-display area, as well as the spacing between the right sub-pixel and the right boundary of the non-display area. The matching of the shortest distance d0 with the first interval d1 can be understood as the same as the first interval d1 or the shortest distance d0 being close to the first interval d1. For example, in an actual product, when the ratio of the shortest distance d0 between the orthographic projection of the conductive block 100 and its adjacent sub-pixels in the row direction X on the second substrate BP2 to the first spacing d1 is greater than or equal to 0.8 and less than or equal to 1.2, the shortest distance d0 can be considered to match the first spacing d1. This ensures that the gap between the first column of sub-pixels Pixel-F or the last column of sub-pixels Pixel-L and the boundary of the non-display area allows for the routing of the first data signal line DT1 and the penultimate data signal line DTN. Furthermore, matching the shortest distance d0 with the row-direction X distance between sub-pixels in the display area ensures that the parasitic effects of the first data signal line DT1 and the penultimate data signal line DTN on the corresponding column of sub-pixels are the same as those on other locations in the display area, thereby ensuring display uniformity. Of course, in actual products, because the first column of sub-pixels Pixel-F and the last column of sub-pixels Pixel-L are both obscured by the outer frame BMO and are not displayed, the shortest distance d0 may differ from the first spacing d1. These differences fall within the scope of protection of this disclosure.

[0068] It is worth noting that the shortest distance d0 between the conductive block 100 described in the present disclosure and the sub-pixels adjacent thereto in the row direction X on the second substrate BP2 can be understood as follows: the orthographic projection of the conductive block 100 on the second substrate BP2 has a first side close to the display area, the orthographic projection of the first column of sub-pixels Pixel-F or the last column of sub-pixels Pixel-L on the second substrate BP2 has a second side close to the non-display area, and the distance from any node on the first side to the second side along the row direction X is the shortest distance d0.

[0069] In an exemplary embodiment, the shortest distance d0 between the conductive block 100 and its adjacent sub-pixel in the row direction X, as projected on the second base substrate BP2, may be greater than or equal to 18 μm and less than or equal to 26 μm, for example, 18 μm, 19 μm, 20 μm, 21 μm, 22 μm, 23 μm, 24 μm, 24.2 μm, 25 μm, 26 μm, etc. In this way, the shortest distance d0 can match the first interval d1 between adjacent sub-pixels in the display area, and the first data signal line DT1 can be arranged outside the first column of sub-pixels Pixel-F, and the last-to-last data signal line DTN can be arranged outside the last-to-last column of sub-pixels Pixel-F.

[0070] It should be understood that the routing structure of the first data signal line DT1 at the first frame GPL is similar to the routing structure of the penultimate data signal line DTN at the second frame GPR shown in FIG6 , and will not be described in detail here.

[0071] The present disclosure further provides a display device, which includes but is not limited to a television, a flat panel, etc. The display device may include the display panel described in any of the above embodiments of the present disclosure.

[0072] Other embodiments of the present disclosure will readily occur to those skilled in the art after considering the specification and practicing the invention disclosed herein. This application is intended to cover any variations, uses, or adaptations of the present disclosure that follow from the generality of the present disclosure and include common knowledge or customary techniques in the art not disclosed herein. The description and examples are to be considered as exemplary only, with the true scope and spirit of the present disclosure being indicated by the claims.

Claims

1. A display panel, wherein: The display area includes a plurality of columns of sub-pixels spaced in sequence in the row direction, and data signal lines are arranged on the side of the first column of sub-pixels away from the last column of sub-pixels and on the side of the last column of sub-pixels away from the first column of sub-pixels.

2. The display panel according to claim 1, wherein: The display panel includes a color film substrate, and the color film substrate includes: a first substrate base plate; A color resist layer, located on one side of the first substrate and in the display area, the color resist layer comprising a plurality of sub-pixels distributed in an array; A frame area, circumferentially arranged around the display area, the frame area comprising a first frame and a second frame arranged opposite to each other in a row direction; The orthographic projection of the first frame on the first substrate covers the orthographic projection of the first column of sub-pixels on the first substrate and partially overlaps with the orthographic projection of the second column of sub-pixels on the first substrate; The orthographic projection of the second frame on the first substrate covers the orthographic projection of the last column of sub-pixels on the first substrate and partially overlaps with the orthographic projection of the second to last column of sub-pixels on the first substrate.

3. The display panel according to claim 2, wherein: The data signal line on the side of the first column of sub-pixels away from the last column of sub-pixels is the first data signal line, and the data signal line on the side of the last column of sub-pixels away from the first column of sub-pixels is the penultimate data signal line. The first data signal line is electrically connected to some sub-pixels in the second pixel column, and the penultimate data signal line is electrically connected to some sub-pixels in the penultimate column.

4. The display panel according to claim 3, wherein: The first data signal line is also electrically connected to some sub-pixels of the first pixel column, and the sub-pixels of the first pixel column connected to the first data signal line and the sub-pixels of the second pixel column connected to the first data signal line are located in the same row; The penultimate data signal line is also electrically connected to some sub-pixels in the Nth pixel column, and the sub-pixels in the Nth pixel column connected to the penultimate data signal line and the sub-pixels in the (N-1)th pixel column connected to the penultimate data signal line are located in the same row.

5. The display panel according to claim 1, wherein: Among the sub-pixels in the same pixel column, the sub-pixels in odd-numbered rows are connected to the same data signal line, and the sub-pixels in even-numbered rows are connected to another data signal line; In two adjacent columns of sub-pixels distributed on both sides of the same data signal line, the even-numbered rows of sub-pixels in the previous column of sub-pixels and the odd-numbered rows of sub-pixels in the next column of sub-pixels are connected to the same data signal line; In the two columns of sub-pixels distributed between two adjacent data signal lines, the sub-pixels located in odd-numbered rows are connected to the previous data signal line, and the sub-pixels located in even-numbered rows are connected to the next data signal line.

6. The display panel according to claim 1, wherein: The display panel comprises a driving substrate and a color filter substrate which are arranged in a box, the sub-pixels are located on the color filter substrate, and the color resistance layer comprises a plurality of sub-pixels distributed in an array along row and column directions; The driving substrate comprises: a second substrate base plate; A common electrode layer is located on one side of the second base substrate, and the common electrode layer includes: A plurality of common electrode lines are located in the display area, wherein the orthographic projections of the plurality of common electrode lines on the second substrate extend along the column direction and are sequentially spaced apart in the row direction; A source-drain metal layer, located at a side of the common electrode layer away from the second substrate, the source-drain metal layer comprising a plurality of data signal lines; Wherein, the display panel includes a plurality of data signal lines, and the orthographic projections of the data signal lines and the common electrode lines on the second substrate are both located between the orthographic projections of two adjacent columns of sub-pixels on the second substrate, and the orthographic projections of the plurality of data signal lines and the plurality of common electrode lines on the second substrate are alternately distributed in the row direction.

7. The display panel according to claim 6, wherein: The display area includes n columns of sub-pixels, m data signal lines and k common electrode lines, wherein m=n / 2+1, k=n / 2, n is a natural number greater than or equal to 2, and m and k are both natural numbers.

8. The display panel according to claim 1, wherein: The display panel comprises a plurality of pixel driving circuits, each of which comprises a transistor, and a gate of each transistor is connected to a gate signal terminal; The display panel includes a driving substrate and a color filter substrate arranged in a cell, and the driving substrate includes: a second substrate base plate; A gate metal layer is located on one side of the second substrate, and the gate metal layer includes: A plurality of conductive blocks are located in a non-display area of ​​the display panel, and the conductive blocks are connected to output signal lines of the shift register unit through via holes; A plurality of gate signal lines, located in the display area, the gate signal lines are connected to the conductive blocks, and a portion of the gate signal lines is used to form a gate of the transistor; Part of the orthographic projections of the conductive blocks on the second substrate are located within the orthographic projections of the first frame on the second substrate, and part of the orthographic projections of the conductive blocks on the second substrate are located within the orthographic projections of the second frame on the second substrate; Any two adjacent sub-pixels in the row direction have a first interval in the row direction, and the shortest distance between the orthographic projection of the conductive block and the adjacent sub-pixel on the second substrate in the row direction matches the first interval.

9. The display panel according to claim 8, wherein: A ratio of the shortest distance between the conductive block and the adjacent sub-pixel on the second substrate in the row direction and the first interval is greater than or equal to 0.8 and less than or equal to 1.

2.

10. The display panel according to claim 8, wherein: The shortest distance is greater than or equal to 18 μm and less than or equal to 26 μm.

11. The display panel according to claim 2, wherein: The border area further includes a third border and a fourth border arranged opposite to each other in the column direction; The display panel further includes: A fan-out area is located on a side of the third frame away from the display area, and the fan-out area includes: There are multiple data fan-out lines, one of the data signal lines is connected to a corresponding data fan-out line, an electrostatic release unit is connected between the first data signal line and the corresponding data fan-out line, and between the penultimate data signal line and the corresponding data fan-out line, and the electrostatic release unit is also connected to a common electrode line.

12. The display panel according to claim 11, wherein: The display panel further includes a plurality of chips, and the fan-out area further includes a plurality of virtual data fan-out lines; The number of data channels of the chip is equal to the sum of the number of corresponding data fan-out lines and virtual data fan-out lines.

13. The display panel according to claim 12, wherein: The number of virtual data fan-out lines corresponding to at least some of the chips is different from the number of virtual data fan-out lines corresponding to other chips.

14. The display panel according to claim 13, wherein: The plurality of chips include a first chip connected to the first data signal line and a second chip connected to the penultimate data signal line; The number of virtual data fan-out lines corresponding to the first chip and the number of virtual data fan-out lines corresponding to the second chip are both less than the number of virtual data fan-out lines corresponding to other chips.

15. The display panel according to claim 14, wherein: The first chip and the second chip each correspond to one virtual data fan-out line.

16. The display panel according to claim 2, wherein: The border area further includes a third border and a fourth border arranged opposite to each other in the column direction; The first data signal line and the penultimate data signal line are both connected to an electrostatic release unit in a non-display area on one side of the fourth frame, and the electrostatic release unit is also connected to a common electrode line.

17. A display device, wherein: A display panel comprising any one of claims 1-16.

Images