Shift register unit, gate drive circuit, display panel, and driving method

Abstract

Provided in the present disclosure are a shift register unit, a gate drive circuit, a display panel, and a driving method. The shift register unit comprises: a first shift register, which is configured to output a cascade signal by means of a cascade output end; a sampling circuit, which is coupled to a first node and is configured to provide a signal at an enabling end to the first node in response to a signal at a sampling control end; and a control circuit, which is coupled to the cascade output end and the first node, and is configured to output, in response to a signal of the first node, a gate scanning signal having the same time sequence as the cascade signal by means of a driving output end, or to output a gate cut-off signal by means of the driving output end.

Description

Shift register unit, gate driving circuit, display panel and driving method

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to the Chinese patent application filed with the State Intellectual Property Office of China on May 26, 2023, with application number 202310609661.3 and application name “Shift register unit, gate drive circuit, display panel and driving method”, the entire contents of which are incorporated by reference into this application. Technical Field

[0003] The present invention relates to the field of display technology, and in particular to a shift register unit, a gate driving circuit, a display panel and a driving method. Background Art

[0004] Display panels, such as organic light-emitting diode (OLED) and quantum dot light-emitting diode (QLED) panels, typically include multiple pixel units. Each pixel unit can include multiple sub-pixels of different colors. By controlling the brightness of these sub-pixels, the desired colors can be mixed, thereby displaying a color image.

[0005] Summary of the Invention

[0006] Some embodiments of the present disclosure provide a shift register unit comprising:

[0007] A first shift register configured to output a cascade signal through a cascade output terminal;

[0008] a sampling circuit coupled to the first node and configured to provide a signal from an enable terminal to the first node in response to a signal from a sampling control terminal;

[0009] A control circuit is coupled to the cascade output terminal and the first node, and is configured to output a gate scan signal with the same timing as the cascade signal through a driving output terminal in response to a signal of the first node, or to output a gate cut-off signal through the driving output terminal.

[0010] In some possible implementations provided by the present disclosure, the sampling circuit is further configured to provide a signal from an enable terminal to the first node in response to a signal from the sampling control terminal in a sampling phase;

[0011] The sampling phase is between the start time of the effective level of the cascade signal of the previous stage shift register unit and the start time of the effective level of the cascade signal of the current stage shift register unit.

[0012] In some possible implementations provided by the present disclosure, the sampling control terminal includes: a first sampling control terminal and a second sampling control terminal;

[0013] The sampling circuit is further configured to provide the signal of the enable terminal to the first node in response to the signal of the first sampling control terminal and the signal of the second sampling control terminal.

[0014] In some possible implementations provided by the present disclosure, the first sampling control terminal of the current stage shift register unit is coupled to the cascade output terminal of the current stage shift register unit, and the second sampling control terminal of the current stage shift register unit is coupled to the cascade output terminal of the previous stage shift register unit;

[0015] The sampling circuit is further configured to provide the signal of the enable terminal to the first node in response to the cascade signal of the current stage shift register unit and the cascade signal of the previous stage shift register unit in the sampling phase.

[0016] In some possible implementations provided by the present disclosure, the first sampling control terminal of the current stage shift register unit is coupled to the pull-down node of the current stage shift register unit, and the second sampling control terminal of the current stage shift register unit is coupled to the pull-up node of the current stage shift register unit;

[0017] The sampling circuit is further configured to provide the signal of the enable terminal to the first node in response to the signal of the pull-down node and the signal of the pull-up node of the current stage shift register unit in the sampling phase.

[0018] In some possible implementations provided by the present disclosure, the sampling circuit includes: a first transistor and a second transistor;

[0019] The gate of the first transistor is coupled to the first sampling control terminal, the first terminal of the first transistor is coupled to the enable terminal, the second terminal of the first transistor is coupled to the first terminal of the second transistor, the gate of the second transistor is coupled to the second sampling control terminal, and the second terminal of the second transistor is coupled to the first node; or

[0020] The gate of the first transistor is coupled to the second sampling control terminal, the first terminal of the first transistor is coupled to the enable terminal, the second terminal of the first transistor is coupled to the first terminal of the second transistor, the gate of the second transistor is coupled to the first sampling control terminal, and the second terminal of the second transistor is coupled to the first node.

[0021] In some possible implementations provided by the present disclosure, the sampling circuit includes: a third transistor;

[0022] A gate of the third transistor is coupled to the sampling control terminal, a first terminal of the third transistor is coupled to the enable terminal, and a second terminal of the third transistor is coupled to the first node.

[0023] In some possible implementations provided by the present disclosure, the shift register unit further includes: a second shift register, which is coupled to the sampling control end and is configured to input a signal to the sampling control end according to a sampling control input end, a first sampling control clock signal end, and a second sampling control clock signal end.

[0024] In some possible implementations provided by the present disclosure, the control circuit includes:

[0025] a first control subcircuit configured to provide a signal from the first reference signal terminal to the third node, or provide a signal from the fourth node to the third node, in response to the cascade signal from the cascade signal terminal;

[0026] The second control subcircuit is configured to provide the signal of the first reference signal terminal to the second node, or provide the signal of the fifth node to the second node in response to the signal of the third node;

[0027] The third control subcircuit is configured to provide the signal of the second reference signal terminal to the fourth node and provide the signal of the second reference signal terminal to the fifth node in response to the signal of the first node;

[0028] The fourth control subcircuit is configured to provide the signal of the first reference signal terminal to the sixth node, or provide the signal of the second reference signal terminal to the sixth node in response to the signal of the second node;

[0029] The fifth control sub-circuit is configured to provide the signal of the first reference signal terminal to the driving output terminal, or provide the signal of the second reference signal terminal to the driving output terminal in response to the signal of the sixth node.

[0030] In some possible implementations provided by the present disclosure, the first control subcircuit includes: a first control transistor and a second control transistor;

[0031] The gate of the first control transistor is coupled to the cascade output terminal, the first electrode of the first control transistor is coupled to the first reference signal terminal, and the second electrode of the first control transistor is coupled to the third node;

[0032] A gate of the second control transistor is coupled to the cascade output terminal, a first electrode of the second control transistor is coupled to the third node, and a second electrode of the second control transistor is coupled to the fourth node.

[0033] In some possible implementations provided by the present disclosure, the second control subcircuit includes: a fourth control transistor, a fifth control transistor, and a first capacitor;

[0034] The gate of the fourth control transistor is coupled to the third node, the first electrode of the fourth control transistor is coupled to the first reference signal terminal, and the second electrode of the fourth control transistor is coupled to the second node;

[0035] The gate of the fifth control transistor is coupled to the third node, the first electrode of the fifth control transistor is coupled to the second node, and the second electrode of the fifth control transistor is coupled to the fifth node;

[0036] A first electrode of the first capacitor is coupled to the first reference signal terminal, and a second electrode of the first capacitor is coupled to the gate of the fourth control transistor.

[0037] In some possible implementations provided by the present disclosure, the third control subcircuit includes: a third control transistor, a sixth control transistor, and a second capacitor;

[0038] The gate of the third control transistor is coupled to the first node, the first electrode of the third control transistor is coupled to the fourth node, and the second electrode of the third control transistor is coupled to the second reference signal terminal;

[0039] The gate of the sixth control transistor is coupled to the first node, the first electrode of the sixth control transistor is coupled to the fifth node, and the second electrode of the sixth control transistor is coupled to the second reference signal terminal;

[0040] A first electrode of the second capacitor is coupled to the first node, and a second electrode of the second capacitor is coupled to the second reference signal terminal.

[0041] In some possible implementations provided by the present disclosure, the fourth control subcircuit includes: a seventh control transistor, an eighth control transistor, and a third capacitor;

[0042] The gate of the seventh control transistor is coupled to the second node, the first electrode of the seventh control transistor is coupled to the first reference signal terminal, and the second electrode of the seventh control transistor is coupled to the sixth node;

[0043] The gate of the eighth control transistor is coupled to the second node, the first electrode of the eighth control transistor is coupled to the sixth node, and the second electrode of the eighth control transistor is coupled to the second reference signal terminal;

[0044] A first electrode of the third capacitor is coupled to the second node, and a second electrode of the third capacitor is coupled to the second reference signal terminal.

[0045] In some possible implementations provided by the present disclosure, the fifth control subcircuit includes: a ninth control transistor and a tenth control transistor;

[0046] The gate of the ninth control transistor is coupled to the sixth node, the first electrode of the ninth control transistor is coupled to the first reference signal terminal, and the second electrode of the ninth control transistor is coupled to the driving output terminal;

[0047] A gate of the tenth control transistor is coupled to the sixth node, a first electrode of the tenth control transistor is coupled to the driving output terminal, and a second electrode of the tenth control transistor is coupled to the second reference signal terminal.

[0048] Some embodiments of the present disclosure provide a gate driving circuit comprising: a plurality of the above-mentioned shift register units; the first shift registers in the plurality of shift register units are sequentially cascaded.

[0049] Some embodiments of the present disclosure provide a display panel comprising: a plurality of gate lines and the above-mentioned gate driving circuit;

[0050] One gate line among the plurality of gate lines is coupled to a driving output terminal of a shift register unit in the gate driving circuit.

[0051] Some embodiments of the present disclosure provide a driving method for a shift register unit, including:

[0052] The first shift register outputs a cascade signal through a cascade output terminal;

[0053] The sampling circuit provides the signal of the enable terminal to the first node in response to the signal of the sampling control terminal;

[0054] The control circuit responds to the signal of the first node and outputs a gate scanning signal having the same timing as the cascade signal through the driving output terminal, or outputs a gate cut-off signal through the driving output terminal. BRIEF DESCRIPTION OF THE DRAWINGS

[0055] FIG1 is a schematic diagram of some structures of a shift register unit in the prior art;

[0056] FIG2 is a timing diagram of some signals in the prior art;

[0057] FIG3 is another signal timing diagram in the prior art;

[0058] FIG4 is a schematic diagram of some structures of a shift register unit provided by an embodiment of the present disclosure;

[0059] FIG5 is a schematic diagram of another structure of a shift register unit provided by an embodiment of the present disclosure;

[0060] FIG6 is a schematic diagram of some further structures of a shift register unit provided by an embodiment of the present disclosure;

[0061] FIG7 is a schematic diagram of some further structures of the shift register unit provided by the embodiment of the present disclosure;

[0062] FIG8 is a schematic diagram of some further structures of the shift register unit provided by an embodiment of the present disclosure;

[0063] FIG9 is a schematic diagram of some further structures of a shift register unit provided by an embodiment of the present disclosure;

[0064] FIG10 is a timing diagram of some signals provided by an embodiment of the present disclosure;

[0065] FIG11 is a flow chart of a driving method provided by an embodiment of the present disclosure;

[0066] FIG12 is another signal timing diagram provided by an embodiment of the present disclosure;

[0067] FIG13 is a timing diagram of some further signals provided by an embodiment of the present disclosure;

[0068] FIG14 is a timing diagram of some further signals provided by an embodiment of the present disclosure;

[0069] FIG15 is a timing diagram of some further signals provided by an embodiment of the present disclosure;

[0070] FIG16 is a schematic diagram of some further structures of a shift register unit provided by an embodiment of the present disclosure;

[0071] FIG17 is a schematic diagram of some further structures of the shift register unit provided by an embodiment of the present disclosure;

[0072] FIG18 is a schematic diagram of some further structures of a shift register unit provided by an embodiment of the present disclosure;

[0073] FIG19 is a schematic diagram of some further structures of the shift register unit provided by an embodiment of the present disclosure;

[0074] FIG20 is a schematic diagram of some further structures of the shift register unit provided by an embodiment of the present disclosure;

[0075] FIG21 is a timing diagram of some further signals provided by an embodiment of the present disclosure;

[0076] FIG22 is a timing diagram of some further signals provided by an embodiment of the present disclosure;

[0077] FIG23 is a timing diagram of some further signals provided by an embodiment of the present disclosure;

[0078] FIG24 is a timing diagram of some further signals provided by an embodiment of the present disclosure;

[0079] FIG25 is a schematic diagram of some further structures of the shift register unit provided by an embodiment of the present disclosure;

[0080] FIG26 is a schematic diagram of some further structures of a shift register unit provided by an embodiment of the present disclosure;

[0081] FIG27 is a schematic diagram of some further structures of the shift register unit provided by an embodiment of the present disclosure;

[0082] FIG28 is a schematic diagram of some further structures of the shift register unit provided by an embodiment of the present disclosure;

[0083] FIG29 is a timing diagram of some further signals provided by an embodiment of the present disclosure;

[0084] FIG30 is a schematic diagram of some further structures of the shift register unit provided by an embodiment of the present disclosure;

[0085] FIG31 is a schematic diagram of some further structures of a shift register unit provided by an embodiment of the present disclosure;

[0086] FIG32 is a schematic diagram of some further structures of the shift register unit provided by an embodiment of the present disclosure;

[0087] FIG33 is a timing diagram of some further signals provided by an embodiment of the present disclosure;

[0088] FIG34 is a timing diagram of some further signals provided by an embodiment of the present disclosure;

[0089] FIG35 is a timing diagram of some further signals provided by an embodiment of the present disclosure;

[0090] FIG36 is a timing diagram of some further signals provided by an embodiment of the present disclosure;

[0091] FIG37 is a schematic diagram of some structures of a display panel provided by an embodiment of the present disclosure;

[0092] FIG38 is a schematic diagram of some other structures of the display panel provided in an embodiment of the present disclosure. DETAILED DESCRIPTION

[0093] In order to make the purpose, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings of the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. And in the absence of conflict, the embodiments of the present invention and the features in the embodiments can be combined with each other. Based on the described embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0094] Unless otherwise defined, the technical or scientific terms used in the present invention shall have the usual meanings understood by persons of ordinary skill in the field to which the present invention belongs. The words "first", "second" and similar terms used in the present invention do not indicate any order, quantity or importance, but are only used to distinguish different components. Words such as "include" or "comprise" mean that the elements or objects preceding the word include the elements or objects listed after the word and their equivalents, without excluding other elements or objects. Words such as "coupled" or "connected" are not limited to physical or mechanical coupling, but may include electrical coupling, whether direct or indirect.

[0095] It should be noted that the sizes and shapes of the figures in the accompanying drawings do not reflect the actual scale and are only for the purpose of illustrating the present invention. The same or similar reference numerals throughout represent the same or similar elements or elements having the same or similar functions.

[0096] In an embodiment of the present disclosure, the display panel includes: a plurality of pixel units arranged in an array, each pixel unit including a plurality of sub-pixels. For example, the pixel unit may include a red sub-pixel, a green sub-pixel, and a blue sub-pixel, so that red, green, and blue can be mixed to achieve a color display. Alternatively, the pixel unit may also include a red sub-pixel, a green sub-pixel, a blue sub-pixel, and a white sub-pixel, so that red, green, blue, and white can be mixed to achieve a color display. Of course, in actual applications, the luminous color of the sub-pixels in the pixel unit can be designed and determined according to the actual application environment, and is not limited here.

[0097] The application scope of Organic Light-Emitting Diode (OLED) display panels has gradually expanded from small and medium-sized watches, mobile phones, tablets and other fields to personal computers (PCs), monitors and other fields. In order to achieve better display effects (such as reducing the ghosting effect and improving the response speed of the screen), the refresh rate of the display panel has gradually increased. However, the gradually increasing refresh rate also increases the power consumption of the graphics processing unit (GPU) and integrated circuit (IC) of the whole machine. However, in specific usage scenarios, usually only some parts of the picture are changing (such as video playback, game windows, etc.), and the pictures in other parts are usually static and do not require a high refresh rate (such as comment area, advertisements, etc.).

[0098] To reduce power consumption, systems have developed partial refresh capabilities, such as Panel Self-Refresh 2 (PSR2), a standard protocol in the digital display field (Embedded DisplayPort, EDP). Display panels need to develop corresponding capabilities to meet this requirement.

[0099] As shown in Figures 1 to 3, the display panel includes multiple shift register units, and the traditional shift register unit structure generally includes a first shift register 10 and a control circuit 30 controlled by the signal of the enable terminal EN. The pulse width is 1H (one line period) and can be directly controlled by the signal of the enable terminal EN. However, with the development of pixels, the signals for controlling pixels have gradually diversified, and the time length has exceeded 1H, resulting in the waveforms of some of the signals at the drive output terminal OUT (such as out2 and out4 in Figure 3) crossing the changing edge (such as the rising edge or the falling edge) of the signal en at the enable terminal EN, resulting in only the waveforms of some of the signals at the drive output terminal OUT (such as out1 and out3 in Figure 3) being output normally, and the waveforms of the signals at the other drive output terminals OUT (such as out2 and out4 in Figure 3) will cause abnormal pixel operation.

[0100] The following describes the operation process of the conventional shift register unit by taking the conventional shift register unit structure shown in FIG. 1 as an example and combining the signal timing diagrams shown in FIG. 2 and FIG. 3 .

[0101] ot1 represents the cascade signal of the cascade output terminal OT in the first-stage shift register unit structure, ot2 represents the cascade signal of the cascade output terminal OT in the second-stage shift register unit structure, ot3 represents the cascade signal of the cascade output terminal OT in the third-stage shift register unit structure, ot4 represents the cascade signal of the cascade output terminal OT in the fourth-stage shift register unit structure, en represents the signal of the enable terminal EN, out1 represents the drive signal of the drive output terminal OUT in the first-stage shift register unit structure, out2 represents the drive signal of the drive output terminal OUT in the second-stage shift register unit structure, out3 represents the drive signal of the drive output terminal OUT in the third-stage shift register unit structure, and out4 represents the drive signal of the drive output terminal OUT in the fourth-stage shift register unit structure.

[0102] As shown in FIG2 , during a full refresh frame, when the signal en at the enable terminal EN is at a high level, the third control transistor M3 and the sixth control transistor M3 are turned on by the high-level signal. At this time, the signal at the second reference signal terminal VGL can be normally output to the second control transistor M2 and the fifth control transistor M5. The first control transistor M1, the second control transistor M2, the fourth control transistor M4, the fifth control transistor M5, the seventh control transistor M7, the eighth control transistor M8, the ninth control transistor M9, and the tenth control transistor M10 can be equivalent to four inverter structures connected in series, thereby ensuring that the waveform of the cascade signal (e.g., ot1, ot2, ot3, ot4 in FIG2 ) can be normally output, that is, the waveform of the drive signal (e.g., out1, out2, out3, out4 in FIG2 ) can be normally output.

[0103] As shown in FIG3 , during a partial refresh frame, at time t1 (which is the rising edge of the signal en at the enable terminal EN), the signal at the enable terminal EN switches from a low level to a high level, and the third control transistor M3 and the sixth control transistor M3 are turned on by the high-level signal. At this time, the signal at the second reference signal terminal VGL can be normally output to the second control transistor M2 and the fifth control transistor M5. The first control transistor M1, the second control transistor M2, the fourth control transistor M4, and the fifth control transistor M5 can be equivalent to a structure of four inverters connected in series. Therefore, after time t1, the waveform of the cascade signal can be output, that is, the waveform of the drive signal (e.g., out2 in FIG3 ) can be output. In other words, the waveform of the drive signal (e.g., out2 in FIG3 ) that crosses the rising edge of the signal en at the enable terminal EN will be partially output.

[0104] At time t2 (which is the falling edge of the signal en at the enable terminal EN), the signal at the enable terminal EN switches from a high level to a low level. Because the signal at the first node N1 before the switch is equivalent to the cascade signal at the cascade signal terminal OT of the same level (i.e., a high level signal), after the switch, the third control transistor M3 and the sixth control transistor M3 are turned off by the low level signal. The first control transistor M1, the second control transistor M2, the fourth control transistor M4, and the fifth control transistor M5 are unable to output the signal at the second reference signal terminal VGL. This means that the inverter cannot function properly. The seventh control transistor M7 and the eighth control transistor M8 can only operate with reference to the high level signal stored in the second capacitor C2 at the first node N1. Consequently, the drive signal (e.g., out4 in FIG3 ) cannot change and continues to output a high level signal. In other words, the waveform of the drive signal (e.g., out4 in FIG3 ) that crosses the falling edge of the signal en at the enable terminal EN cannot generate a falling edge.

[0105] Based on the above problems, the present disclosure provides the following solutions.

[0106] The shift register unit provided by the embodiment of the present disclosure, as shown in FIG4 , includes:

[0107] The first shift register 10 is configured to output a cascade signal through a cascade output terminal OT;

[0108] The sampling circuit 20 is coupled to the first node N1 and is configured to provide a signal from the enable terminal EN to the first node N1 in response to a signal from the sampling control terminal SA;

[0109] The control circuit 30 is coupled to the cascade output terminal OT and the first node N1, and is configured to output a gate scanning signal with the same timing as the cascade signal through the driving output terminal OUT in response to the signal of the first node N1, or to output a gate cut-off signal through the driving output terminal OUT.

[0110] In the disclosed embodiment, the first shift register, sampling circuit, and control circuit cooperate to not only refresh the entire pixel area of ​​the display panel row by row, but also selectively refresh data in a local area of ​​the display panel. Thus, when refreshing data in a local area of ​​the display screen, the display panel only refreshes the selected local area, thereby achieving a high-frequency refresh mode for that local area, while other areas are not refreshed, thereby achieving a low-frequency refresh mode for the remaining areas, thereby minimizing driving power consumption.

[0111] Moreover, when the partial data of the display screen is refreshed, the sampling circuit is provided to ensure that the control circuit can output the correct signal in the next display frame, so that the display panel can work normally and will not output an erroneous signal due to the change of the signal at the enable terminal EN.

[0112] It should be noted that the enable signal is provided by an integrated circuit chip (IC). The chip IC calculates the sub-pixel refresh frequency of each row in the display panel and the waveform requirements of the enable signal in each frame based on the refresh frequency requirements of different areas of the entire machine.

[0113] In some embodiments of the present disclosure, as shown in FIG4 , the sampling circuit 20 is further configured to provide a signal from the enable terminal EN to the first node N1 in response to a signal from the sampling control terminal SA in the sampling phase;

[0114] The sampling phase is between the start time of the effective level of the cascade signal of the previous stage shift register unit and the start time of the effective level of the cascade signal of the current stage shift register unit.

[0115] In some embodiments of the present disclosure, as shown in FIG5 , the sampling control terminal SA includes: a first sampling control terminal SA1 and a second sampling control terminal SA2 ; the sampling circuit 20 is further configured to provide a signal from the enable terminal EN to the first node N1 in response to a signal from the first sampling control terminal SA1 and a signal from the second sampling control terminal SA2 .

[0116] In some embodiments of the present disclosure, as shown in Figure 6, the first sampling control terminal SA1 of the current stage shift register unit is coupled to the cascade output terminal OT of the current stage shift register unit, and the second sampling control terminal SA2 of the current stage shift register unit is coupled to the cascade output terminal OT of the previous stage shift register unit; the sampling circuit 20 is further configured to provide the signal of the enable terminal EN to the first node N1 in response to the cascade signal of the current stage shift register unit and the cascade signal of the previous stage shift register unit in the sampling phase.

[0117] For example, as shown in Figure 6, the first sampling control terminal SA1 of the second-stage shift register unit D2 is coupled to the cascade output terminal OT of the second-stage shift register unit D2, and the second-stage shift register unit D2 is coupled to the cascade output terminal OT of the first-stage shift register unit D1; ... the first sampling control terminal SA1 of the n-th stage shift register unit Dn is coupled to the cascade output terminal OT of the n-th stage shift register unit Dn, and the n-th stage shift register unit Dn is coupled to the cascade output terminal OT of the n-1-th stage shift register unit Dn-1.

[0118] Exemplarily, as shown in FIG6 , the first clock signal terminal CK in the first shift register 10 receives the first clock signal ck, the second clock signal terminal CB receives the second clock signal cb, and the frame start signal terminal STV receives the frame start signal stv.

[0119] Illustratively, the first-stage shift register unit D1 corresponds to a portion of the display area AA, the second-stage shift register unit D2 corresponds to a portion of the display area AA, ... the n-1th-stage shift register unit Dn-1 corresponds to a portion of the display area AA, and the nth-stage shift register unit Dn corresponds to a portion of the display area AA.

[0120] In some embodiments of the present disclosure, as shown in FIG7 , the sampling circuit 20 includes: a first transistor T1 and a second transistor T2; wherein the gate of the first transistor T1 is coupled to the first sampling control terminal SA1, the first terminal of the first transistor T1 is coupled to the enable terminal EN, the second terminal of the first transistor T1 is coupled to the first terminal of the second transistor T2, the gate of the second transistor T2 is coupled to the second sampling control terminal SA2, and the second terminal of the second transistor T2 is coupled to the first node N1.

[0121] In some embodiments of the present disclosure, as shown in FIG8 , the control circuit 30 includes: a first control sub-circuit 310 configured to provide a signal of the first reference signal terminal VGH to the third node N3 or provide a signal of the fourth node N4 to the third node N3 in response to the cascade signal of the cascade signal terminal OT;

[0122] The second control sub-circuit 320 is configured to provide the signal of the first reference signal terminal VGH to the second node N2 or provide the signal of the fifth node N5 to the second node N2 in response to the signal of the third node N3;

[0123] The third control sub-circuit 330 is configured to provide the signal of the second reference signal terminal VGL to the fourth node N4 in response to the signal of the first node N1, and to provide the signal of the second reference signal terminal VGL to the fifth node N5;

[0124] The fourth control sub-circuit 340 is configured to provide the signal of the first reference signal terminal VGH to the sixth node N6 or provide the signal of the second reference signal terminal VGL to the sixth node N6 in response to the signal of the second node N2;

[0125] The fifth control sub-circuit 350 is configured to provide the signal of the first reference signal terminal VGH to the driving output terminal OUT, or provide the signal of the second reference signal terminal VGL to the driving output terminal OUT in response to the signal of the sixth node N6.

[0126] In some embodiments of the present disclosure, as shown in FIG8 , the first control subcircuit 310 includes: a first control transistor M1 and a second control transistor M2;

[0127] The gate of the first control transistor M1 is coupled to the cascade output terminal OT, the first electrode of the first control transistor M1 is coupled to the first reference signal terminal VGH, and the second electrode of the first control transistor M1 is coupled to the third node N3;

[0128] A gate of the second control transistor M2 is coupled to the cascade output terminal OT, a first electrode of the second control transistor M2 is coupled to the third node N3 , and a second electrode of the second control transistor M2 is coupled to the fourth node N4 .

[0129] In some embodiments of the present disclosure, as shown in FIG8 , the second control sub-circuit 320 includes: a fourth control transistor M4 , a fifth control transistor M5 , and a first capacitor C1 ;

[0130] A gate of the fourth control transistor M4 is coupled to the third node N3, a first electrode of the fourth control transistor M4 is coupled to the first reference signal terminal VGH, and a second electrode of the fourth control transistor M4 is coupled to the second node N2;

[0131] A gate of the fifth control transistor M5 is coupled to the third node N3, a first electrode of the fifth control transistor M5 is coupled to the second node N2, and a second electrode of the fifth control transistor M5 is coupled to the fifth node N5;

[0132] A first electrode of the first capacitor C1 is coupled to the first reference signal terminal VGH, and a second electrode of the first capacitor C1 is coupled to the gate of the fourth control transistor M4 .

[0133] In some embodiments of the present disclosure, as shown in FIG8 , the third control sub-circuit 330 includes: a third control transistor M3 , a sixth control transistor M6 , and a second capacitor C2 ;

[0134] A gate of the third control transistor M3 is coupled to the first node N1, a first electrode of the third control transistor M3 is coupled to the fourth node N4, and a second electrode of the third control transistor M3 is coupled to the second reference signal terminal VGL;

[0135] A gate of the sixth control transistor M6 is coupled to the first node N1, a first electrode of the sixth control transistor M6 is coupled to the fifth node N5, and a second electrode of the sixth control transistor M6 is coupled to the second reference signal terminal VGL;

[0136] A first electrode of the second capacitor C2 is coupled to the first node N1 , and a second electrode of the second capacitor C2 is coupled to the second reference signal terminal VGL.

[0137] The second capacitor C2 has a voltage stabilizing effect. When the inverter fails to work normally, the second capacitor C2 can ensure that the voltage of the first node N1 is not affected and remains in a normal state.

[0138] In some embodiments of the present disclosure, as shown in FIG8 , the fourth control sub-circuit 340 includes: a seventh control transistor M7 , an eighth control transistor M8 , and a third capacitor C3 ;

[0139] A gate of the seventh control transistor M7 is coupled to the second node N2, a first electrode of the seventh control transistor M7 is coupled to the first reference signal terminal VGH, and a second electrode of the seventh control transistor M7 is coupled to the sixth node N6;

[0140] A gate of the eighth control transistor M8 is coupled to the second node N2 , a first electrode of the eighth control transistor M8 is coupled to the sixth node N6 , and a second electrode of the eighth control transistor M8 is coupled to the second reference signal terminal VGL;

[0141] A first electrode of the third capacitor C3 is coupled to the second node N2 , and a second electrode of the third capacitor C3 is coupled to the second reference signal terminal VGL.

[0142] In some embodiments of the present disclosure, as shown in FIG8 , the fifth control sub-circuit 350 includes: a ninth control transistor M9 and a tenth control transistor M10 ;

[0143] A gate of the ninth control transistor M9 is coupled to the sixth node N6 , a first electrode of the ninth control transistor M9 is coupled to the first reference signal terminal VGH, and a second electrode of the ninth control transistor M9 is coupled to the driving output terminal OUT;

[0144] A gate of the tenth control transistor M10 is coupled to the sixth node N6 , a first electrode of the tenth control transistor M10 is coupled to the driving output terminal OUT, and a second electrode of the tenth control transistor M10 is coupled to the second reference signal terminal VGL.

[0145] For example, as shown in FIG8 , some transistors may be P-type transistors and some transistors may be N-type transistors. For example, the first transistor T1, the first control transistor M1, the fourth control transistor M4, the seventh control transistor M7, and the ninth control transistor M9 are P-type transistors, and the second transistor T2, the second control transistor M2, the third control transistor M3, the fifth control transistor M5, the sixth control transistor M6, the eighth control transistor M8, and the tenth control transistor M10 are N-type transistors. Furthermore, the N-type transistors are turned on by a high-level signal and turned off by a low-level signal; the P-type transistors are turned off by a high-level signal and turned on by a low-level signal.

[0146] Exemplarily, as shown in FIG9 , the first shift register 10 includes: a first transistor T1-1, a second transistor T2-1, a third transistor T3-1, a fourth transistor T4-1, a fifth transistor T5-1, a sixth transistor T6-1, a seventh transistor T7-1, an eighth transistor T8-1, a ninth transistor T9-1, an eleventh transistor T10-1, an eleventh transistor T11-1, a twelfth transistor T12-1, a first capacitor C1-1, a second capacitor C2-1, and a third capacitor C3-1; wherein the gate of the first transistor T1-1 is coupled to the first clock signal terminal CK, and the first transistor T1-1 is coupled to the first clock signal terminal CK. A first electrode of the first transistor T1-1 is coupled to the frame start signal terminal STV, a second electrode of the first transistor T1-1 is coupled to the gate of the second transistor T2-1; a first electrode of the second transistor T2-1 is coupled to the second electrode of the third transistor T3-1, and the second electrode of the second transistor T2-1 is coupled to the first clock signal terminal CK; a gate of the third transistor T3-1 is coupled to the first clock signal terminal CK, and a first electrode of the third transistor T3-1 is coupled to the second reference signal terminal VGL; a gate of the fourth transistor T4-1 is coupled to the pull-down node A, a first electrode of the fourth transistor T4-1 is coupled to the second electrode of the fifth transistor T5-1, and the fourth transistor T4-1 is coupled to the pull-down node A. The second electrode of the fifth transistor T5-1 is coupled to the second electrode of the third transistor T3-1, and the first electrode of the fifth transistor T5-1 is coupled to the first reference signal terminal VGH; the gate of the sixth transistor T6-1 is coupled to the second electrode of the eleventh transistor T11-1, the first electrode of the sixth transistor T6-1 is coupled to the second clock signal terminal CB, and the second electrode of the sixth transistor T6-1 is coupled to the first electrode of the seventh transistor T7-1; the gate of the seventh transistor T7-1 is coupled to the second clock signal terminal CB, and the second electrode of the seventh transistor T7-1 is coupled to the pull-up node B; the eighth transistor T8-1 is coupled to the second electrode of the eleventh transistor T11-1, the first electrode of the sixth transistor T6-1 is coupled to the second clock signal terminal CB, and the second electrode of the sixth transistor T6-1 is coupled to the first electrode of the seventh transistor T7-1; a gate of the eighth transistor T8-1 coupled to the second electrode of the first transistor T1-1, a first electrode of the eighth transistor T8-1 coupled to the pull-up node B, and a second electrode of the eighth transistor T8-1 coupled to the first reference signal terminal VGH; a gate of the ninth transistor T9-1 coupled to the pull-up node B, a first electrode of the ninth transistor T9-1 coupled to the first reference signal terminal VGH, and a second electrode of the ninth transistor T9-1 coupled to the cascade output terminal OT; a gate of the eleventh transistor T10-1 coupled to the pull-down node A, a first electrode of the eleventh transistor T10-1 coupled to the cascade output terminal OT, and a second electrode of the eleventh transistor T10-1 coupled to the second reference signal terminal VGL;The gate of the eleventh transistor T11-1 is coupled to the second reference signal terminal VGL, the first electrode of the eleventh transistor T11-1 is coupled to the second electrode of the third transistor T3-1, and the second electrode of the eleventh transistor T11-1 is coupled to the gate of the sixth transistor T6-1; the gate of the twelfth transistor T12-1 is coupled to the second reference signal terminal VGL, the first electrode of the twelfth transistor T12-1 is coupled to the second electrode of the first transistor T1-1, and the second electrode of the twelfth transistor T12-1 is coupled to the pull-down Node A is coupled; a first electrode of a first capacitor C1-1 is coupled to the second electrode of the eleventh transistor T11-1, and a second electrode of the first capacitor C1-1 is coupled to the second electrode of the sixth transistor T6-1; a first electrode of a second capacitor C2-1 is coupled to the first reference signal terminal VGH, and a second electrode of the second capacitor C2-1 is coupled to the pull-up node B; a first electrode of a third capacitor C3-1 is coupled to the second electrode of the fifth transistor T5-1, and a second electrode of the third capacitor C3-1 is coupled to the pull-down node A.

[0147] Exemplarily, as shown in FIG10 , stv represents a signal at a frame start signal terminal, ck represents a signal at a first clock signal terminal CK, cb represents a signal at a second clock signal terminal CB, and ot represents a signal at a cascade signal terminal OT.

[0148] For example, in order to reduce the manufacturing process, all transistors may be P-type transistors; or, all transistors may be N-type transistors, which is not limited here.

[0149] For example, the first reference signal terminal VGH can be configured to load a constant first reference voltage vgh, which is generally a high voltage. Furthermore, the second reference signal terminal VGL can be configured to load a constant second reference voltage vgl, which is generally a low voltage. In practical applications, the specific values ​​of the first reference voltage vgh and the second reference voltage vgl can be designed and determined based on the actual application environment and are not limited here.

[0150] It should be noted that the transistors mentioned in the above embodiments of the present disclosure may be thin film transistors (TFTs) or metal oxide semiconductor field effect transistors (MOSs), without limitation. In specific implementations, depending on the transistor type and input signal, the first electrode of the transistor may be used as its source and the second electrode as its drain; or the first electrode may be used as its drain and the second electrode as its source, without making any specific distinction here.

[0151] It should be noted that the structure of the first shift register is merely an example. In practical applications, other structures are possible and are not limited here.

[0152] The driving method of the shift register unit provided in the embodiment of the present disclosure, as shown in FIG11 , includes the following steps:

[0153] S100, the first shift register outputs a cascade signal through the cascade output terminal;

[0154] S200, the sampling circuit provides a signal from the enable terminal to the first node in response to a signal from the sampling control terminal;

[0155] S300 , the control circuit outputs a gate scanning signal having the same timing as the cascade signal through the driving output terminal in response to the signal of the first node, or outputs a gate cut-off signal through the driving output terminal.

[0156] The following describes the working process of the shift register unit provided by the embodiment of the present disclosure by taking the shift register unit structure shown in FIG8 as an example and combining it with the signal timing diagram shown in FIG12 .

[0157] As shown in Figures 12 to 15, sa1(ot) represents the signal of the first sampling control terminal SA1 (cascade signal terminal OT), sa2 represents the signal of the second sampling control terminal SA2, en represents the signal of the enable terminal, n1 represents the signal of the first node N1, n2 represents the signal of the second node N2, and out represents the signal of the driving output terminal OUT; wherein vgh represents the first reference voltage and vgl represents the second reference voltage.

[0158] During a full refresh frame, in sampling phase t, the first transistor T1 is turned on by a low-level signal at the first sampling control terminal SA1, and the second transistor T2 is turned on by a high-level signal at the second sampling control terminal SA2. The first transistor T1 and the second transistor T2 provide a high-level signal at the enable terminal EN to the first node N1. In response to the signal at the first node N1, the control circuit 30 drives the output terminal OUT to output a gate scan signal with the same timing as the cascade signal ot.

[0159] The following describes the working process of the shift register unit provided by the embodiment of the present disclosure by taking the shift register unit structure shown in FIG8 as an example and combining it with the signal timing diagram shown in FIG13 .

[0160] During a partial refresh frame, in a sampling phase t, the first transistor T1 is turned on by a low-level signal at the first sampling control terminal SA1, and the second transistor T2 is turned on by a high-level signal at the second sampling control terminal SA2. The first transistor T1 and the second transistor T2 provide a low-level signal at the enable terminal EN to the first node N1. In response to the signal at the first node N1, the control circuit 30 outputs a gate-off signal via the driver output terminal OUT.

[0161] The following describes the working process of the shift register unit provided by the embodiment of the present disclosure by taking the shift register unit structure shown in FIG8 as an example and combining it with the signal timing diagram shown in FIG14 .

[0162] During a full refresh frame, in sampling phase t, the first transistor T1 is turned on by a low-level signal at the first sampling control terminal SA1, and the second transistor T2 is turned on by a high-level signal at the second sampling control terminal SA2. The first transistor T1 and the second transistor T2 provide a high-level signal at the enable terminal EN to the first node N1. In response to the signal at the first node N1, the control circuit 30 drives the output terminal OUT to output a gate scan signal with the same timing as the cascade signal ot.

[0163] The following describes the working process of the shift register unit provided by the embodiment of the present disclosure by taking the shift register unit structure shown in FIG8 as an example and combining it with the signal timing diagram shown in FIG15 .

[0164] During a partial refresh frame, in sampling phase t, the first transistor T1 is turned on by a low-level signal at the first sampling control terminal SA1, and the second transistor T2 is turned on by a high-level signal at the second sampling control terminal SA2. The first transistor T1 and the second transistor T2 provide a high-level signal at the enable terminal EN to the first node N1. In response to the signal at the first node N1, the control circuit 30 drives the output terminal OUT to output a gate scan signal with the same timing as the cascade signal ot.

[0165] The present disclosure provides some other structural diagrams of the shift register unit, as shown in Figures 16 and 17, which are modifications of the implementation in the above embodiment. The following only describes the differences between this embodiment and the above embodiment, and the similarities are not repeated here.

[0166] In other embodiments of the present disclosure, as shown in Figures 16 and 17, the sampling circuit 20 includes: a first transistor T1 and a second transistor T2; wherein, the gate of the first transistor T1 is coupled to the second sampling control terminal SA2, the first terminal of the first transistor T1 is coupled to the enable terminal EN, the second terminal of the first transistor T1 is coupled to the first terminal of the second transistor T2, the gate of the second transistor T2 is coupled to the first sampling control terminal SA1, and the second terminal of the second transistor T2 is coupled to the first node N1.

[0167] The following describes the working process of the shift register unit provided by the embodiment of the present disclosure by taking the shift register unit structure shown in FIG. 17 as an example and combining it with the signal timing diagram shown in FIG. 12 .

[0168] During a full refresh frame, in sampling phase t, the second transistor T2 is turned on by a low-level signal at the first sampling control terminal SA1, and the first transistor T1 is turned on by a high-level signal at the second sampling control terminal SA2. The first transistor T1 and the second transistor T2 provide a high-level signal at the enable terminal EN to the first node N1. In response to the signal at the first node N1, the control circuit 30 drives the output terminal OUT to output a gate scan signal with the same timing as the cascade signal ot.

[0169] The following describes the working process of the shift register unit provided by the embodiment of the present disclosure by taking the shift register unit structure shown in FIG17 as an example and combining it with the signal timing diagram shown in FIG13 .

[0170] During a partial refresh frame, in sampling phase t, the second transistor T2 is turned on by a low-level signal at the first sampling control terminal SA1, and the first transistor T1 is turned on by a high-level signal at the second sampling control terminal SA2. The first transistor T1 and the second transistor T2 provide a low-level signal at the enable terminal EN to the first node N1. In response to the signal at the first node N1, the control circuit 30 outputs a gate-off signal via the driver output terminal OUT.

[0171] The following describes the working process of the shift register unit provided by the embodiment of the present disclosure by taking the shift register unit structure shown in FIG17 as an example and combining it with the signal timing diagram shown in FIG14 .

[0172] During a full refresh frame, in sampling phase t, the second transistor T2 is turned on by a low-level signal at the first sampling control terminal SA1, and the first transistor T1 is turned on by a high-level signal at the second sampling control terminal SA2. The first transistor T1 and the second transistor T2 provide a high-level signal at the enable terminal EN to the first node N1. In response to the signal at the first node N1, the control circuit 30 drives the output terminal OUT to output a gate scan signal with the same timing as the cascade signal ot.

[0173] The following describes the working process of the shift register unit provided by the embodiment of the present disclosure by taking the shift register unit structure shown in FIG17 as an example and combining it with the signal timing diagram shown in FIG15 .

[0174] During a partial refresh frame, in sampling phase t, the second transistor T2 is turned on by a low-level signal at the first sampling control terminal SA1, and the first transistor T1 is turned on by a high-level signal at the second sampling control terminal SA2. The first transistor T1 and the second transistor T2 provide a high-level signal at the enable terminal EN to the first node N1. In response to the signal at the first node N1, the control circuit 30 drives the output terminal OUT to output a gate scan signal with the same timing as the cascade signal ot.

[0175] The present disclosure provides some structural diagrams of the shift register unit, as shown in Figures 18 to 20, which are modifications of the implementation in the above embodiment. The following only describes the differences between this embodiment and the above embodiment, and the similarities are not repeated here.

[0176] In some further embodiments of the present disclosure, as shown in FIG18 , the first sampling control terminal SA1 of the current-stage shift register unit is coupled to the pull-down node A of the current-stage shift register unit, and the second sampling control terminal SA2 of the current-stage shift register unit is coupled to the pull-up node B of the current-stage shift register unit; the sampling circuit 20 is further configured to provide a signal of the enable terminal EN to the first node N1 in response to signals of the pull-down node A and the pull-up node B of the current-stage shift register unit in the sampling phase.

[0177] For example, as shown in FIG18 , the first sampling control terminal SA1 of the first-stage shift register unit D1 is coupled to the pull-down node A of the first-stage shift register unit D1, and the second sampling control terminal SA2 of the first-stage shift register unit D1 is coupled to the pull-up node B of the first-stage shift register unit D1; the first sampling control terminal SA1 of the second-stage shift register unit D2 is coupled to the pull-down node A of the second-stage shift register unit D2, and the second sampling control terminal SA2 of the second-stage shift register unit D2 is coupled to the pull-up node B of the second-stage shift register unit D2; ... The first sampling control terminal SA1 of the n-1-th stage shift register unit Dn-1 is coupled to the pull-down node A of the n-1-th stage shift register unit Dn-1, and the second sampling control terminal SA2 of the n-1-th stage shift register unit Dn-1 is coupled to the pull-up node B of the n-1-th stage shift register unit Dn-1; the first sampling control terminal SA1 of the n-th stage shift register unit Dn is coupled to the pull-down node A of the n-th stage shift register unit Dn, and the second sampling control terminal SA2 of the n-th stage shift register unit Dn is coupled to the pull-up node B of the n-th stage shift register unit Dn.

[0178] The following describes the working process of the shift register unit provided by the embodiment of the present disclosure by taking the shift register unit structure shown in FIG20 as an example and combining it with the signal timing diagram shown in FIG21 .

[0179] As shown in Figures 21 to 24, a represents the signal of the pull-down node A, b represents the signal of the pull-up node B, ot represents the cascade signal of the cascade signal terminal OT, en represents the signal of the enable terminal, n1 represents the signal of the first node N1, n2 represents the signal of the second node N2, and out represents the signal of the driving output terminal OUT, wherein vgh represents the first reference voltage and vgl represents the second reference voltage.

[0180] During a full refresh frame, in sampling phase t, the first transistor T1 is turned on by a high-level signal at the first sampling control terminal SA1, and the second transistor T2 is turned on by a high-level signal at the second sampling control terminal SA2. The first transistor T1 and the second transistor T2 provide a high-level signal at the enable terminal EN to the first node N1. In response to the signal at the first node N1, the control circuit 30 drives the output terminal OUT to output a gate scan signal with the same timing as the cascade signal ot.

[0181] The following describes the working process of the shift register unit provided by the embodiment of the present disclosure by taking the shift register unit structure shown in FIG20 as an example and combining it with the signal timing diagram shown in FIG22 .

[0182] During a partial refresh frame, in sampling phase t, the first transistor T1 is turned on by a high-level signal at the first sampling control terminal SA1, and the second transistor T2 is turned on by a high-level signal at the second sampling control terminal SA2. The first transistor T1 and the second transistor T2 provide a low-level signal at the enable terminal EN to the first node N1. In response to the signal at the first node N1, the control circuit 30 outputs a gate-off signal via the driver output terminal OUT.

[0183] The following describes the working process of the shift register unit provided by the embodiment of the present disclosure by taking the shift register unit structure shown in FIG20 as an example and combining it with the signal timing diagram shown in FIG23 .

[0184] During a full refresh frame, in sampling phase t, the first transistor T1 is turned on by a high-level signal at the first sampling control terminal SA1, and the second transistor T2 is turned on by a high-level signal at the second sampling control terminal SA2. The first transistor T1 and the second transistor T2 provide a high-level signal at the enable terminal EN to the first node N1. In response to the signal at the first node N1, the control circuit 30 drives the output terminal OUT to output a gate scan signal with the same timing as the cascade signal ot.

[0185] The following describes the working process of the shift register unit provided by the embodiment of the present disclosure by taking the shift register unit structure shown in FIG20 as an example and combining it with the signal timing diagram shown in FIG24 .

[0186] During a partial refresh frame, in sampling phase t, the first transistor T1 is turned on by a high-level signal at the first sampling control terminal SA1, and the second transistor T2 is turned on by a high-level signal at the second sampling control terminal SA2. The first transistor T1 and the second transistor T2 provide a high-level signal at the enable terminal EN to the first node N1. In response to the signal at the first node N1, the control circuit 30 drives the output terminal OUT to output a gate scan signal with the same timing as the cascade signal ot.

[0187] The present disclosure provides some structural diagrams of the shift register unit, as shown in Figures 25 and 26, which are modifications of the implementation in the above embodiment. The following only describes the differences between this embodiment and the above embodiment, and the similarities are not repeated here.

[0188] The following describes the working process of the shift register unit provided by the embodiment of the present disclosure by taking the shift register unit structure shown in FIG26 as an example and combining it with the signal timing diagram shown in FIG21 .

[0189] During a full refresh frame, in sampling phase t, the second transistor T2 is turned on by a high-level signal at the first sampling control terminal SA1, and the first transistor T1 is turned on by a high-level signal at the second sampling control terminal SA2. The first transistor T1 and the second transistor T2 provide a high-level signal at the enable terminal EN to the first node N1. In response to the signal at the first node N1, the control circuit 30 drives the output terminal OUT to output a gate scan signal with the same timing as the cascade signal ot.

[0190] The following describes the working process of the shift register unit provided by the embodiment of the present disclosure by taking the shift register unit structure shown in FIG26 as an example and combining it with the signal timing diagram shown in FIG22 .

[0191] During a partial refresh frame, in sampling phase t, the second transistor T2 is turned on by a high-level signal at the first sampling control terminal SA1, and the first transistor T1 is turned on by a high-level signal at the second sampling control terminal SA2. The first transistor T1 and the second transistor T2 provide a low-level signal at the enable terminal EN to the first node N1. In response to the signal at the first node N1, the control circuit 30 outputs a gate-off signal via the driver output terminal OUT.

[0192] The following describes the working process of the shift register unit provided by the embodiment of the present disclosure by taking the shift register unit structure shown in FIG26 as an example and combining it with the signal timing diagram shown in FIG23 .

[0193] During a full refresh frame, in sampling phase t, the second transistor T2 is turned on by a high-level signal at the first sampling control terminal SA1, and the first transistor T1 is turned on by a high-level signal at the second sampling control terminal SA2. The first transistor T1 and the second transistor T2 provide a high-level signal at the enable terminal EN to the first node N1. In response to the signal at the first node N1, the control circuit 30 drives the output terminal OUT to output a gate scan signal with the same timing as the cascade signal ot.

[0194] The following describes the working process of the shift register unit provided by the embodiment of the present disclosure by taking the shift register unit structure shown in FIG26 as an example and combining it with the signal timing diagram shown in FIG24 .

[0195] During a partial refresh frame, in sampling phase t, the second transistor T2 is turned on by a high-level signal at the first sampling control terminal SA1, and the first transistor T1 is turned on by a high-level signal at the second sampling control terminal SA2. The first transistor T1 and the second transistor T2 provide a high-level signal at the enable terminal EN to the first node N1. In response to the signal at the first node N1, the control circuit 30 drives the output terminal OUT to output a gate scan signal with the same timing as the cascade signal ot.

[0196] The present disclosure provides some structural diagrams of the shift register unit, as shown in Figures 27 to 31, which are modifications of the implementation in the above embodiment. The following only describes the differences between this embodiment and the above embodiment, and the similarities are not repeated here.

[0197] In some other embodiments of the present disclosure, as shown in Figure 27, the shift register unit also includes: a second shift register 40, which is coupled to the sampling control terminal SA and is configured to input a signal to the sampling control terminal SA according to the sampling control input terminal SA-STV, the first sampling control clock signal terminal SA-CK and the second sampling control clock signal terminal SA-CB.

[0198] Exemplarily, as shown in FIG28 , the second shift register 40 includes: a first transistor T1-2, a second transistor T2-2, a third transistor T3-2, a fourth transistor T4-2, a fifth transistor T5-2, a sixth transistor T6-2, a seventh transistor T7-2, an eighth transistor T8-2, a first capacitor C1-2, and a second capacitor C2-2; wherein the gate of the first transistor T1-2 is coupled to the first sampling control clock signal terminal SA-CK, the first electrode of the first transistor T1-2 is coupled to the sampling control input terminal SA-STV, and the second electrode of the first transistor T1-2 is coupled to the sampling control input terminal SA-STV. A first electrode of the eighth transistor T8-2 is coupled; a gate of the eighth transistor T8-2 is coupled to the second reference signal terminal VGL, and a second electrode of the eighth transistor T8-2 is coupled to the gate of the fifth transistor T5-2; a first electrode of the fifth transistor T5-2 is coupled to the sampling control terminal SA, and a second electrode of the fifth transistor T5-2 is coupled to the second sampling control clock signal terminal SA-CB; a gate of the third transistor T3-2 is coupled to the first sampling control clock signal terminal SA-CK, a first electrode of the third transistor T3-2 is coupled to the second reference signal terminal VGL, and a second electrode of the third transistor T3-2 is coupled to the gate of the second transistor The first electrode of the second transistor T2-2 is coupled to the first electrode of the first transistor T1-2; the gate of the second transistor T2-2 is coupled to the second electrode of the first transistor T1-2, and the second electrode of the second transistor T2-2 is coupled to the first sampling control clock signal terminal SA-CK; the gate of the fourth transistor T4-2 is coupled to the second electrode of the third transistor T3-2, the first electrode of the fourth transistor T4-2 is coupled to the first reference signal terminal VGH, and the second electrode of the fourth transistor T4-2 is coupled to the sampling control terminal SA; the gate of the sixth transistor T6-2 is coupled to the second electrode of the third transistor T3-2, and the first electrode of the sixth transistor T6-2 is coupled to the first reference signal terminal VG H is coupled, the second electrode of the sixth transistor T6-2 is coupled to the first electrode of the seventh transistor T7-2; the gate of the seventh transistor T7-2 is coupled to the second sampling control clock signal terminal SA-CB, and the second electrode of the seventh transistor T7-2 is coupled to the second electrode of the first transistor T1-2; the first electrode of the first capacitor C1-2 is coupled to the first reference signal terminal VGH, and the second electrode of the first capacitor C1-2 is coupled to the gate of the fourth transistor T4-2; the first electrode of the second capacitor C2-2 is coupled to the sampling control terminal SA, and the second electrode of the second capacitor C2-2 is coupled to the gate of the fifth transistor T5-2.

[0199] It should be noted that the structure of the second shift register is merely an example. In practical applications, other structures are possible and are not limited here.

[0200] For example, as shown in FIG29 , sa-stv represents the signal of the sampling control input terminal SA-STV, sa-ck represents the signal of the first sampling control clock signal terminal SA-CK, sa-cb represents the signal of the second sampling control clock signal terminal SA-CB, and sa represents the signal of the sampling control terminal SA.

[0201] In some other embodiments of the present disclosure, as shown in Figure 30, the sampling circuit 20 includes: a third transistor T3; wherein the gate of the third transistor T3 is coupled to the sampling control terminal SA, the first terminal of the third transistor T3 is coupled to the enable terminal EN, and the second terminal of the third transistor T3 is coupled to the first node N1.

[0202] The following describes the working process of the shift register unit provided by the embodiment of the present disclosure by taking the shift register unit structure shown in FIG32 as an example and combining it with the signal timing diagram shown in FIG33 .

[0203] As shown in Figures 34 to 37, ot represents the signal of the cascade signal terminal OT, sa represents the signal of the sampling control terminal SA, en represents the signal of the enable terminal, n1 represents the signal of the first node N1, n2 represents the signal of the second node N2, and out represents the signal of the driving output terminal OUT; wherein, vgh represents the first reference voltage, and vgl represents the second reference voltage.

[0204] In the full refresh frame, at time t, the third transistor T3 is turned on under the low-level signal of the sampling control terminal SA, and the third transistor T3 provides the high-level signal of the enable terminal EN to the first node N1. The control circuit 30 responds to the signal of the first node N1 and outputs a gate scan signal with the same timing as the cascade signal ot through the driving output terminal OUT.

[0205] The following describes the working process of the shift register unit provided by the embodiment of the present disclosure by taking the shift register unit structure shown in FIG32 as an example and combining it with the signal timing diagram shown in FIG34 .

[0206] In the local new frame, at time t, the third transistor T3 is turned on under the low level signal of the sampling control terminal SA, and the third transistor T3 provides the low level signal of the enable terminal EN to the first node N1. The control circuit 30 responds to the signal of the first node N1 and outputs the gate cut-off signal through the driving output terminal OUT.

[0207] The following describes the working process of the shift register unit provided by the embodiment of the present disclosure by taking the shift register unit structure shown in FIG32 as an example and combining it with the signal timing diagram shown in FIG35 .

[0208] In the full refresh frame, at time t, the third transistor T3 is turned on under the low-level signal of the sampling control terminal SA, and the third transistor T3 provides the high-level signal of the enable terminal EN to the first node N1. The control circuit 30 responds to the signal of the first node N1 and outputs a gate scan signal with the same timing as the cascade signal ot through the driving output terminal OUT.

[0209] The following describes the working process of the shift register unit provided by the embodiment of the present disclosure by taking the shift register unit structure shown in FIG32 as an example and combining it with the signal timing diagram shown in FIG36 .

[0210] In the local new frame, at time t, the third transistor T3 is turned on under the low-level signal of the sampling control terminal SA, and the third transistor T3 provides the high-level signal of the enable terminal EN to the first node N1. The control circuit 30 responds to the signal of the first node N1 and outputs a gate scan signal with the same timing as the cascade signal ot through the driving output terminal OUT.

[0211] Based on the same inventive concept, the disclosed embodiments provide a gate drive circuit 120, as shown in Figures 6, 18, and 31, comprising: a plurality of the aforementioned shift register units (e.g., D1, D2, Dn-1, and Dn in the figures); and a first shift register 10 in the plurality of shift register units arranged in cascade. The gate drive circuit 120 solves the problem similarly to the aforementioned shift register units. Therefore, the implementation of the gate drive circuit 120 can refer to the implementation of the aforementioned shift register units (e.g., D1, D2, Dn-1, and Dn in the figures), and the repeated parts are not repeated here.

[0212] Based on the same inventive concept, an embodiment of the present disclosure provides a display panel 100, as shown in FIG37 , comprising: a plurality of gate lines GA and the aforementioned gate drive circuit 120; one gate line GA among the plurality of gate lines GA is coupled to a drive output terminal OUT of a shift register unit (e.g., D1, D2, Dn-1, Dn in FIG6 , FIG18 , and FIG31 ) in the gate drive circuit 120. The principle of solving the problem of the display panel 100 is similar to that of the aforementioned gate drive circuit 120. Therefore, the implementation of the display panel 100 can refer to the implementation of the aforementioned gate drive circuit 120, and the repeated parts are not repeated here.

[0213] Exemplarily, as shown in FIG. 38 , the display panel 100 further includes: a plurality of data lines DA and a source driving circuit 130 .

[0214] For example, a plurality of shift register units (e.g., D1, D2, Dn-1, and Dn in FIG. 6 , FIG. 18 , and FIG. 31 ) are respectively coupled to a plurality of gate lines GA, and a source driver circuit 130 is respectively coupled to a plurality of data lines DA. When the display panel 100 is operating, a control signal is input to the gate driver circuit 120, causing the gate driver circuit 120 to output a signal to the coupled gate lines GA, thereby driving the gate lines GA. Furthermore, the source driver circuit 130 inputs a data voltage to the data lines DA based on display data, thereby charging the sub-pixels and causing the sub-pixels to receive the corresponding data voltage, thereby achieving a screen display function.

[0215] For example, two source driver circuits 130 may be provided, wherein one source driver circuit 130 may be connected to half the number of data lines, and the other source driver circuit 130 may be connected to the other half of the number of data lines. Of course, in actual applications, three, four, or more source driver circuits 130 may also be provided, which may be determined according to the requirements of the actual application environment, and this disclosure is not limited thereto.

[0216] In some embodiments of the present disclosure, one column of sub-pixels may correspond to one data line DA, or alternatively, one column of sub-pixels may correspond to multiple data lines DA, which is not limited here.

[0217] In specific implementations, in embodiments of the present invention, the display device may be any product or component with a display function, such as a mobile phone, a tablet computer, a television, a monitor, a laptop computer, a digital photo frame, or a navigation system. Other essential components of the display device are readily understood by those skilled in the art and are not detailed here, nor should they be construed as limitations of the present invention.

[0218] The above is only a specific implementation method of the present application, but the scope of protection of the present application is not limited thereto. Any technician familiar with this technical field can easily think of changes or replacements within the technical scope disclosed in this application, which should be covered by the scope of protection of the present application.

Claims

1. A shift register unit, comprising: A first shift register configured to output a cascade signal through a cascade output terminal; A sampling circuit, coupled to the first node, configured to provide a signal from an enable terminal to the first node in response to a signal from a sampling control terminal; The control circuit is coupled to the cascade output terminal and the first node, and is configured to respond to the signal of the first node and output a gate scan signal with the same timing as the cascade signal through the driving output terminal, or output a gate cut-off signal through the driving output terminal.

2. The shift register unit according to claim 1, wherein: The sampling circuit is further configured to provide a signal from the enable terminal to the first node in response to a signal from the sampling control terminal in a sampling phase; The sampling phase is between the start time of the effective level of the cascade signal of the previous stage shift register unit and the start time of the effective level of the cascade signal of the current stage shift register unit.

3. The shift register unit according to claim 2, wherein: The sampling control end includes: a first sampling control end and a second sampling control end; The sampling circuit is further configured to provide the signal of the enable terminal to the first node in response to the signal of the first sampling control terminal and the signal of the second sampling control terminal.

4. The shift register unit according to claim 3, wherein: The first sampling control terminal of the current stage shift register unit is coupled to the cascade output terminal of the current stage shift register unit, and the second sampling control terminal of the current stage shift register unit is coupled to the cascade output terminal of the previous stage shift register unit; The sampling circuit is further configured to provide the signal of the enable terminal to the first node in response to the cascade signal of the current stage shift register unit and the cascade signal of the previous stage shift register unit in the sampling phase.

5. The shift register unit according to claim 3, wherein: The first sampling control terminal of the current stage shift register unit is coupled to the pull-down node of the current stage shift register unit, and the second sampling control terminal of the current stage shift register unit is coupled to the pull-up node of the current stage shift register unit; The sampling circuit is further configured to provide the signal of the enable terminal to the first node in response to the signal of the pull-down node and the signal of the pull-up node of the current stage shift register unit in the sampling phase.

6. The shift register unit according to any one of claims 3 to 5, wherein: The sampling circuit comprises: a first transistor and a second transistor; The gate of the first transistor is coupled to the first sampling control terminal, the first terminal of the first transistor is coupled to the enable terminal, the second terminal of the first transistor is coupled to the first terminal of the second transistor, the gate of the second transistor is coupled to the second sampling control terminal, and the second terminal of the second transistor is coupled to the first node; or, The gate of the first transistor is coupled to the second sampling control terminal, the first terminal of the first transistor is coupled to the enable terminal, the second terminal of the first transistor is coupled to the first terminal of the second transistor, the gate of the second transistor is coupled to the first sampling control terminal, and the second terminal of the second transistor is coupled to the first node.

7. The shift register unit according to claim 1 or 2, wherein: The sampling circuit comprises: a third transistor; The gate of the third transistor is coupled to the sampling control terminal, the first terminal of the third transistor is coupled to the enable terminal, and the second terminal of the third transistor is coupled to the first node.

8. The shift register unit according to claim 7, wherein: The shift register unit further includes: a second shift register, which is coupled to the sampling control terminal and configured to input a signal to the sampling control terminal according to the sampling control input terminal, the first sampling control clock signal terminal and the second sampling control clock signal terminal.

9. The shift register unit according to any one of claims 1 to 8, wherein: The control circuit comprises: A first control subcircuit is configured to provide a signal from the first reference signal terminal to a third node, or provide a signal from a fourth node to the third node in response to a cascade signal from the cascade signal terminal; The second control subcircuit is configured to respond to the signal of the third node and to providing a signal of the fifth node to the second node, or providing a signal of the fifth node to the second node; The third control subcircuit is configured to provide the signal of the second reference signal terminal to the fourth node in response to the signal of the first node, and to provide the signal of the second reference signal terminal to the fifth node; The fourth control subcircuit is configured to provide the signal of the first reference signal terminal to the sixth node in response to the signal of the second node, or provide the signal of the second reference signal terminal to the sixth node; The fifth control subcircuit is configured to provide the signal of the first reference signal terminal to the driving output terminal, or provide the signal of the second reference signal terminal to the driving output terminal in response to the signal of the sixth node.

10. The shift register unit according to claim 9, wherein: The first control subcircuit includes: a first control transistor and a second control transistor; The gate of the first control transistor is coupled to the cascade output terminal, the first electrode of the first control transistor is coupled to the first reference signal terminal, and the second electrode of the first control transistor is coupled to the third node; A gate of the second control transistor is coupled to the cascade output terminal, a first electrode of the second control transistor is coupled to the third node, and a second electrode of the second control transistor is coupled to the fourth node.

11. The shift register unit according to claim 9, wherein: The second control subcircuit includes: a fourth control transistor, a fifth control transistor and a first capacitor; The gate of the fourth control transistor is coupled to the third node, the first electrode of the fourth control transistor is coupled to the first reference signal terminal, and the second electrode of the fourth control transistor is coupled to the second node; The gate of the fifth control transistor is coupled to the third node, the first electrode of the fifth control transistor is coupled to the second node, and the second electrode of the fifth control transistor is coupled to the fifth node; A first electrode of the first capacitor is coupled to the first reference signal terminal, and a second electrode of the first capacitor is coupled to the gate of the fourth control transistor.

12. The shift register unit according to claim 9, wherein: The third control subcircuit comprises: a third control transistor, a sixth control transistor and a second capacitor; The gate of the third control transistor is coupled to the first node, the first electrode of the third control transistor is coupled to the fourth node, and the second electrode of the third control transistor is coupled to the second reference signal terminal; The gate of the sixth control transistor is coupled to the first node, the first electrode of the sixth control transistor is coupled to the fifth node, and the second electrode of the sixth control transistor is coupled to the second reference signal terminal; A first electrode of the second capacitor is coupled to the first node, and a second electrode of the second capacitor is coupled to the second reference signal terminal.

13. The shift register unit according to claim 9, wherein: The fourth control subcircuit comprises: a seventh control transistor, an eighth control transistor and a third capacitor; The gate of the seventh control transistor is coupled to the second node, the first electrode of the seventh control transistor is coupled to the first reference signal terminal, and the second electrode of the seventh control transistor is coupled to the sixth node; The gate of the eighth control transistor is coupled to the second node, the first electrode of the eighth control transistor is coupled to the sixth node, and the second electrode of the eighth control transistor is coupled to the second reference signal terminal; A first electrode of the third capacitor is coupled to the second node, and a second electrode of the third capacitor is coupled to the second reference signal terminal.

14. The shift register unit according to claim 9, wherein: The fifth control subcircuit comprises: a ninth control transistor and a tenth control transistor; The gate of the ninth control transistor is coupled to the sixth node, the first electrode of the ninth control transistor is coupled to the first reference signal terminal, and the second electrode of the ninth control transistor is coupled to the driving output terminal; A gate of the tenth control transistor is coupled to the sixth node, a first electrode of the tenth control transistor is coupled to the driving output terminal, and a second electrode of the tenth control transistor is coupled to the second reference signal terminal.

15. A gate drive circuit comprising: A plurality of shift register units according to any one of claims 1 to 14; the first shift registers in the plurality of shift register units are arranged in cascade connection in sequence.

16. A display panel, comprising: A plurality of gate lines and a gate driving circuit as claimed in claim 15; A gate line among the plurality of gate lines and a driving input of a shift register unit in the gate driving circuit Output coupling.

17. A method for driving a shift register unit according to any one of claims 1 to 14, comprising: The first shift register outputs a cascade signal through a cascade output terminal; The sampling circuit provides the signal of the enable terminal to the first node in response to the signal of the sampling control terminal; The control circuit responds to the signal of the first node and outputs a gate scanning signal having the same timing as the cascade signal through the driving output terminal, or outputs a gate cut-off signal through the driving output terminal.

Images