Display panel and manufacturing method therefor

Abstract

The embodiments of the present invention disclose a display panel and a manufacturing method therefor. The display panel comprises a substrate, a plurality of anodes located on the substrate, and a plurality of pixel definition parts arranged at intervals and covering the edges of the anodes, each pixel definition part being arranged around one anode. In a direction in parallel with the substrate, each pixel definition part comprises a first side surface away from an anode, the side of the first side surface close to the substrate and the substrate having a first included angle, and the first included angle being greater than or equal to 35 degrees and less than or equal to 45 degrees.

Description

Display panel and manufacturing method thereof Technical Field

[0001] The present invention relates to the field of display, and in particular to a display panel and a manufacturing method thereof. Background Art

[0002] With the development of display technology, OLED (Organic Light-Emitting Diode) display panels have been widely used due to their advantages such as high brightness, low power consumption, fast response, high clarity and high luminous efficiency.

[0003] However, the OLED display panel uses an opening in the pixel definition layer formed as a whole layer, thereby forming a light-emitting element in the opening. The pixel definition layer has a technical problem that stress is difficult to release, resulting in a loss of quality of the display panel.

[0004] Therefore, a display panel and a manufacturing method thereof are urgently needed to solve the above technical problems. SUMMARY OF THE INVENTION

[0005] The present invention provides a display panel and a manufacturing method thereof, which can alleviate the technical problem that stress is difficult to release due to the formation of a pixel definition layer on the entire display panel, thereby affecting the product quality of the display panel.

[0006] To solve the above problems, the technical solutions provided by this application are as follows:

[0007] The present invention provides a display panel, comprising:

[0008] substrate;

[0009] a plurality of anodes located on the substrate;

[0010] a plurality of pixel definition parts, wherein the pixel definition parts cover edges of the anode and expose a portion of the anode;

[0011] Wherein, one of the pixel definition parts is arranged around one of the anodes, and adjacent pixel definition parts are arranged at intervals;

[0012] Along a direction parallel to the substrate, the pixel definition portion includes a first side surface away from the anode, and the first side surface close to the substrate has a first angle with the substrate, the first angle is greater than or equal to 35 degrees, and the first angle is less than or equal to 45 degrees.

[0013] Preferably, the display panel further comprises a first metal layer, wherein the first metal layer is located between the anode and the substrate;

[0014] The display panel also includes a first insulating layer, which is located between the first metal layer and the anode. The first insulating layer includes a first via hole. The anode includes a first connecting portion located in the first via hole. The first connecting portion is connected to the first metal layer. The pixel definition portion covers the first connecting portion.

[0015] Preferably, the display panel further comprises an active layer, the active layer being located between the first metal layer and the substrate, the active layer comprising a channel portion and a first conductor sub-portion and a second conductor sub-portion respectively located on opposite sides of the channel portion;

[0016] The first metal layer includes a source electrode and a drain electrode, the source electrode is located on the first conductor sub-portion, and the drain electrode is located on the second conductor sub-portion;

[0017] At least a portion of the source electrode near the active layer contacts the first conductor sub-portion, and at least a portion of the drain electrode near the active layer contacts the second conductor sub-portion.

[0018] Preferably, the display panel further comprises a gate, the gate being located between the source electrode and the drain electrode, and an orthographic projection of the gate on the active layer covering the channel portion;

[0019] The display panel further includes a gate insulating layer, and the gate insulating layer is at least spaced between the gate and the channel portion.

[0020] Preferably, the gate is located in the first metal layer, and the gate insulating layer includes a first insulating portion, a second insulating portion, and a third insulating portion that are separated from each other, the first insulating portion is spaced between the channel portion and the gate, the second insulating portion is spaced between a portion of the source and the first conductor sub-portion, and the third insulating portion is spaced between a portion of the drain and the second conductor sub-portion;

[0021] One end of the source electrode close to the gate electrode contacts the first conductor sub-portion, and one end of the drain electrode close to the gate electrode contacts the second conductor sub-portion.

[0022] Preferably, the gate is located on a side of the first metal layer away from the substrate, no insulating layer is present between the source and the first conductor sub-section, and no insulating layer is present between the drain and the second conductor sub-section.

[0023] Preferably, in a plane parallel to the substrate, along a direction from the channel portion to the first conductor sub-portion, an edge of the source electrode away from the gate extends beyond an edge of the first conductor sub-portion away from the channel portion;

[0024] In a plane parallel to the substrate, along a direction from the channel portion to the second conductor sub-portion, an edge of the drain away from the gate extends beyond an edge of the second conductor sub-portion away from the channel portion.

[0025] Preferably, the display panel further comprises a second metal layer, the second metal layer is located between the active layer and the substrate, the second metal layer comprises a first light shielding portion, and an orthographic projection of the active layer on the substrate is located within an orthographic projection of the first light shielding portion on the substrate;

[0026] The display panel further includes a buffer layer, which is located on a side of the active layer close to the substrate and covers the second metal layer.

[0027] Preferably, the first insulating layer includes a passivation layer on a side close to the substrate, the buffer layer is spaced between the second metal layer and the active layer, and the side of the buffer layer away from the substrate is in direct contact with the active layer and the passivation layer;

[0028] A side of the buffer layer close to the substrate is in direct contact with the second metal layer and the substrate.

[0029] Preferably, when the gate insulating layer includes a first insulating portion, a second insulating portion and a third insulating portion that are arranged separately, the end of the second insulating portion away from the first insulating portion contacts the buffer layer, and the end of the third insulating portion away from the first insulating portion contacts the buffer layer.

[0030] Preferably, the first insulating layer further includes a second via hole, and the second via hole is located on one side of the active layer;

[0031] The buffer layer includes a third via hole, the third via hole is connected to the second via hole, and the anode is connected to the first light shielding portion through the second via hole and the third via hole;

[0032] The anode includes a second connection portion, and an orthographic projection of the pixel definition portion on the substrate covers an orthographic projection of the second connection portion on the substrate.

[0033] Preferably, the gate insulation layer includes a fourth via hole, the fourth via hole is located on the side of the second insulation portion away from the active layer, the buffer layer includes a fifth via hole, the fourth via hole is connected to the fifth via hole, and the source electrode is connected to the first light shielding portion through the fourth via hole and the fifth via hole.

[0034] Preferably, the gate insulation layer includes a sixth via hole, the sixth via hole is located on the side of the third insulation portion away from the active layer, the buffer layer includes a seventh via hole, the sixth via hole is connected to the seventh via hole, and the drain is connected to the first light shielding portion through the sixth via hole and the seventh via hole.

[0035] Preferably, the display panel includes a display area and a non-display area located on at least one side of the display area, and the display panel further includes a terminal located in the non-display area, and the terminal is located in the first metal layer;

[0036] The terminals include first-type terminals, and the first-type terminals are connected to the second metal layer.

[0037] Preferably, when the gate insulating layer includes the first insulating portion, the second insulating portion, and the third insulating portion that are arranged apart from each other, the gate insulating layer further includes a fourth insulating portion located between the terminal and the buffer layer, the gate insulating layer further includes an eighth via, the eighth via passes through the fourth insulating portion, the buffer layer includes a ninth via, the ninth via passes through the buffer layer between the second metal layer routing and the fourth insulating portion, and the orthographic projection of the eighth via on the substrate covers the orthographic projection of the ninth via on the substrate;

[0038] The first type terminal includes a first type terminal connection portion, which is located in the eighth via and the ninth via. The eighth via and the ninth via expose the second metal layer wiring, and the first type terminal connection portion is in contact with the second metal layer wiring.

[0039] Preferably, the pixel defining portion and the anode have an overlapping portion, and the width of the orthographic projection of the overlapping portion on the substrate is greater than 2 microns.

[0040] Preferably, the display panel further comprises an organic layer located on a side of the anode away from the substrate, and the organic layer comprises a light-emitting layer;

[0041] Along a direction parallel to the substrate, the pixel defining portion includes a second side surface close to the anode, and the orthographic projection of the anode on the substrate and the orthographic projection of the second side surface on the substrate jointly cover the orthographic projection of the light-emitting layer on the substrate.

[0042] Preferably, a side of the second side surface close to the anode has a second angle with the anode, and the second angle is greater than or equal to 35 degrees, and the second angle is less than or equal to 45 degrees.

[0043] The present invention also provides a method for manufacturing a display panel, comprising:

[0044] providing a substrate;

[0045] forming an anode material layer on the substrate;

[0046] forming a pixel definition material layer on the anode material layer;

[0047] The anode material layer and the pixel definition material layer are subjected to a first patterning process to form a plurality of anodes and a plurality of pixel definition portions respectively;

[0048] The pixel definition portion covers the edge of the anode and exposes a portion of the anode. One pixel definition portion is arranged around one anode, and adjacent pixel definition portions are arranged at intervals.

[0049] Preferably, before forming the anode material layer on the substrate, the method further comprises:

[0050] forming a semiconductor material layer on the substrate;

[0051] forming a first metal material layer on the semiconductor material layer, wherein the first metal material layer is in direct contact with the semiconductor material layer;

[0052] The semiconductor material layer and the first metal material layer are subjected to a second patterning process to form a semiconductor layer and a first metal layer respectively;

[0053] The first metal layer includes a source electrode and a drain electrode, and the source electrode and the drain electrode are respectively located on two opposite sides of the semiconductor layer. Beneficial effects

[0054] The present invention reduces the stress on the pixel definition part by arranging the pixel definition part and the anode in a one-to-one correspondence and spacing adjacent pixel definition parts. In addition, the slope of the first side surface of the pixel definition part is gentler, which increases the contact area between the pixel definition part and the adjacent film layer, enhances the firmness of the connection between the pixel definition part and the adjacent film layer, and improves the product quality of the display panel. BRIEF DESCRIPTION OF THE DRAWINGS

[0055] FIG1 is a schematic structural diagram of a first structure of a display panel provided by an embodiment of the present invention;

[0056] FIG2 is a schematic structural diagram of a second structure of a display panel provided by an embodiment of the present invention;

[0057] 3 is a flowchart of the steps of a method for manufacturing a display panel provided by an embodiment of the present invention;

[0058] 4a to 4m are schematic flow charts of a method for manufacturing a display panel according to an embodiment of the present invention. Modes for Carrying Out the Invention

[0059] This application provides a display module. To make the purpose, technical solutions, and effects of this application more clear and explicit, the application is further described in detail below with reference to the accompanying drawings and examples. It should be understood that the specific embodiments described herein are only used to explain this application and are not intended to limit this application.

[0060] Currently, the pixel definition layer in the display panel is integrally formed, and there is a technical problem that the stress of the pixel definition layer is difficult to release, resulting in a decrease in the quality of the display panel.

[0061] 1 and 2 , an embodiment of the present invention provides a display panel 100, including:

[0062] substrate 101;

[0063] A plurality of anodes 102 are located on the substrate 101;

[0064] a plurality of pixel definition portions 103 , each of which covers an edge of the anode 102 and exposes a portion of the anode 102 ;

[0065] Wherein, one of the pixel definition portions 103 is disposed around one of the anodes 102 , and adjacent pixel definition portions 103 are disposed at intervals;

[0066] Along a direction parallel to the substrate 101, the pixel definition portion 103 includes a first side surface 103a away from the anode 102, and the side of the first side surface 103a close to the substrate 101 has a first angle α with the substrate 101, and the first angle α is greater than or equal to 35 degrees, and the first angle α is less than or equal to 45 degrees.

[0067] In the embodiment of the present invention, the pixel definition portions 103 are arranged in a one-to-one correspondence with the anodes 102, and adjacent pixel definition portions 103 are spaced apart, thereby reducing the stress on the pixel definition portions 103. In addition, the first side surface 103a of the pixel definition portion 103 has a gentler slope, thereby increasing the contact area between the pixel definition portion 103 and the adjacent film layer, enhancing the firmness of the connection between the pixel definition portion 103 and the adjacent film layer, and improving the product quality of the display panel 100.

[0068] The technical solution of the present invention will now be described in conjunction with specific embodiments.

[0069] Referring to FIG. 1 and FIG. 2 , in this embodiment, the display panel 100 further includes a first metal layer 104 . The first metal layer 104 is located between the anode 102 and the substrate 101 .

[0070] The display panel 100 also includes a first insulating layer, which is located between the first metal layer 104 and the anode 102. The first insulating layer includes a first via hole H1. The anode 102 includes a first connecting portion located in the first via hole H1. The first connecting portion is connected to the first metal layer 104. The pixel defining portion 103 covers the first connecting portion.

[0071] In some embodiments, the first metal layer 104 can be a plurality of layers or a single layer formed by a low-resistance material such as Al, Ti, Mo, Cu, Ni, or alloys thereof. For example, the first metal layer 104 can be a molybdenum-titanium alloy / copper / molybdenum-titanium alloy (MoTi / Cu / MoTi) three-layer stacked structure formed by molybdenum-titanium alloy and copper.

[0072] When the first metal layer 104 is a MoTi / Cu / MoTi three-layer stacked structure formed by a MoTi layer, a Cu layer, and a MoTi layer, the thickness of the MoTi layer close to the substrate 101 is 250 angstroms to 350 angstroms, the thickness of the Cu layer is 4200 angstroms to 6500 angstroms, and the thickness of the MoTi layer away from the substrate 101 is 400 angstroms to 500 angstroms.

[0073] In some embodiments, the anode 102 includes a material with a high work function. The anode 102 includes one of indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), indium oxide (In2O3), etc., which are conductive materials with relatively high work functions and are transparent. In addition to the conductive materials listed above, the anode 102 may also include reflective materials such as silver (Ag), magnesium (Mg), aluminum (Al), platinum (Pt), palladium (Pb), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), lithium (Li), calcium (Ca), or a combination thereof. The anode 102 may be composed of a single layer or multiple layers of a transparent conductive material and / or a reflective conductive material. For example, the anode 102 may be an IZO / Ag / IZO three-layer stack formed by IZO and Ag. At this time, the thickness of the IZO layer close to the substrate 101 can be 100 angstroms to 200 angstroms, the thickness of the Ag layer can be 1000 angstroms to 1500 angstroms, and the thickness of the IZO layer away from the substrate 101 can be 700 angstroms to 1000 angstroms.

[0074] Referring to FIG. 1 and FIG. 2 , in this embodiment, the pixel definition portion 103 is disposed around the anode 102 and has a pixel definition opening. The pixel definition opening exposes the anode 102 .

[0075] In some embodiments, the material of the pixel definition portion 103 is selected from an organic material, such as a positive photoresist or a negative photoresist, so that the material of the pixel definition portion 103 can be used as a photoresist. The pixel definition portion 103 and the anode 102 are formed through the same patterning process, which saves process steps and reduces process costs. The thickness of the pixel definition portion 103 can be 2.8 microns to 3.7 microns, for example, 3 microns, 3.2 microns, 3.4 microns, 3.5 microns, 3.6 microns, etc., to form a sufficiently deep pixel definition opening.

[0076] In some embodiments, the first insulating layer includes a passivation layer 112 on a side close to the substrate 101 and a planarization layer 113 on a side away from the substrate 101. The passivation layer 112 covers at least the first metal layer 104. The planarization layer 113 provides a flat surface for forming the anode 102. The anode 102 can be directly formed on the side of the planarization layer 113 away from the substrate 101. Furthermore, the first insulating layer can be composed of the passivation layer 112 and the planarization layer 113.

[0077] The material of the passivation layer 112 is selected from inorganic materials, such as silicon nitrogen compounds or silicon oxide compounds. The material of the planarization layer 113 can be selected from organic materials, such as positive photoresist materials or negative photoresist materials, so that the passivation layer 112 and the planarization layer 113 can be formed through a single patterning process, saving process steps and reducing process costs.

[0078] The thickness of the passivation layer 112 is 3500 angstroms to 5000 angstroms, for example, it can be 3600 angstroms, 3800 angstroms, 4000 angstroms, 4200 angstroms, 4500 angstroms, 4800 angstroms, etc., so as to completely cover the first metal layer 104; the thickness of the flattening layer 113 is 3500 angstroms to 5000 angstroms, for example, it can be 3600 angstroms, 3800 angstroms, 4000 angstroms, 4200 angstroms, 4500 angstroms, 4800 angstroms, etc., so as to provide a flat surface.

[0079] The first via hole H1 exposes the first metal layer 104. The anode 102 includes a first connecting portion located within the first via hole H1. The first connecting portion contacts the first metal layer 104 within the first via hole H1, thereby connecting the anode 102 to the first metal layer 104. Since the first connecting portion fills the first via hole H1 to facilitate connection to the first metal layer 104, the pixel defining portion 103 covers the first via hole H1 to prevent an organic layer (such as a light-emitting layer) formed on the anode 102 from falling into the first via hole H1.

[0080] When the first insulating layer is composed of the passivation layer 112 and the planar layer 113 , the first via hole H1 includes a first sub-via hole located in the passivation layer 112 and a second sub-via hole located in the planar layer 113 .

[0081] In some embodiments, the substrate 101 may be a hard substrate or a flexible substrate. When the substrate 101 is a hard substrate, the substrate 101 may be a glass substrate; when the substrate 101 is a flexible substrate, the material of the substrate 101 may be polyimide.

[0082] Please refer to Figures 1 and 2. In this embodiment, the first metal layer 104 includes a source 106 and a drain 107, the first via H1 exposes the source 106, and the first connecting portion is in contact with the source 106; alternatively, the first metal layer 104 exposes the drain 107, and the first connecting portion is in contact with the drain 107.

[0083] 1 and 2 , in this embodiment, the display panel 100 further includes an active layer 105 , which is located between the first metal layer 104 and the substrate 101 . The active layer 105 includes a channel portion 105 a and a first conductor sub-portion 105 b and a second conductor sub-portion 105 c located on opposite sides of the channel portion 105 a .

[0084] The source electrode 106 is located on the first conductor sub-portion 105 b , and the drain electrode 107 is located on the second conductor sub-portion 105 c .

[0085] At least a portion of the source electrode 106 close to the active layer 105 contacts the first conductor sub-portion 105 b , and at least a portion of the drain electrode 107 close to the active layer 105 contacts the second conductor sub-portion 105 c .

[0086] In some embodiments, the material of the active layer 105 can be selected from conductive oxide materials, such as indium gallium zinc oxide (IGZO). During the formation of the active layer 105, the first conductor sub-section 105b and the second conductor sub-section 105c can be made conductive by ion implantation or plasma bombardment. Ion implantation can be used to dope specific elements or particles, including but not limited to H, He, B, Al, N, F, P, Ar, and S. Plasma bombardment is used to bombard the surface of the active layer 105 material with high-energy particles, forming defects (oxygen vacancies). Oxygen vacancies can generate carriers, thereby increasing the conductive properties and achieving the conductive properties of the first conductor sub-section 105b and the second conductor sub-section 105c.

[0087] In some embodiments, the material of the active layer 105 may be selected from polysilicon.

[0088] In this embodiment, the thickness of the active layer 105 may be 200 angstroms to 500 angstroms, for example, 250 angstroms, 300 angstroms, 350 angstroms, 400 angstroms, 450 angstroms, etc.

[0089] 1 and 2 , in this embodiment, the display panel 100 further includes a gate 108 , which is located on a side of the active layer 105 away from the substrate 101 , and between the source 106 and the drain 107 . The orthographic projection of the gate 108 on the active layer 105 covers the channel portion 105 a.

[0090] In this embodiment, the display panel 100 further includes a gate insulating layer 109. The gate insulating layer 109 is located on a side of the gate electrode 108 close to the active layer 105. The gate insulating layer 109 is at least spaced between the gate electrode 108 and the channel portion 105a. The planarizing layer 113 covers the gate insulating layer 109, the first metal layer 104, and / or the gate electrode 108.

[0091] In some embodiments, the material of the gate 108 can be selected from low-resistance materials such as Al, Ti, Mo, Cu, Ni, or alloys thereof. The gate 108 can be a single-layer or multi-layer structure formed by the above metals or alloys.

[0092] Please refer to FIG. 1 . In some embodiments, the gate 108 is located in the first metal layer 104 . The source 106 , the drain 107 , and the gate 108 can be formed using the same material in the same process, which is beneficial for saving process technology and reducing process costs.

[0093] In some embodiments, the gate insulating layer 109 is made of at least one of silicon nitride and silicon oxide. The gate insulating layer 109 may be one or more layers of silicon nitride or silicon oxide, for example, a single layer of silicon oxide.

[0094] The thickness of the gate insulating layer 109 is 1000 angstroms to 2000 angstroms, for example, 1200 angstroms, 1500 angstroms, 1800 angstroms, etc.

[0095] In some embodiments, the gate insulating layer 109 includes a first insulating portion, a second insulating portion, and a third insulating portion that are separately arranged, the first insulating portion is spaced between the channel portion 105a and the gate 108, the second insulating portion is spaced between part of the source 106 and the first conductor sub-portion 105b, and the third insulating portion is spaced between part of the drain 107 and the second conductor sub-portion 105c.

[0096] The first insulating portion, the second insulating portion, and the third insulating portion are separated from each other, i.e., their orthographic projections on the substrate 101 are separated from each other; the first insulating portion is disconnected from the second insulating portion, and the first insulating portion is disconnected from the third insulating portion. The gate insulating layer 109 includes a first opening between the first insulating portion and the second insulating portion, and a second opening between the first insulating portion and the third insulating portion.

[0097] The first insulating portion is spaced between the channel portion 105a and the gate 108. That is, along the direction from the substrate 101 to the first metal layer 104, the channel portion 105a and the gate 108 are located on either side of the first insulating portion. The side of the gate 108 closest to the first insulating portion is in direct contact with the first insulating portion, and the side of the first insulating portion closest to the active layer 105 is in direct contact with the channel portion 105a. The orthographic projection of the gate 108 on the substrate 101 is located within the orthographic projection of the first insulating portion on the substrate 101, and the orthographic projection of the channel portion 105a on the substrate 101 is located within the orthographic projection of the first insulating portion on the substrate 101.

[0098] The second insulating portion is separated between part of the source 106 and the first conductor sub-portion 105b, and the side of the second insulating portion close to the substrate 101 is in direct contact with the end of the first conductor sub-portion 105b away from the channel portion 105a. The second insulating portion covers at least part of the end of the first conductor sub-portion 105b away from the channel portion 105a. The end of the source 106 close to the gate 108 is in contact with the first conductor sub-portion 105b through the first opening, and the end of the source 106 close to the gate 108 covers the end of the second insulating portion close to the first insulating portion.

[0099] The third insulating portion is separated between part of the source 106 and the second conductor sub-portion 105c, and the side of the third insulating portion close to the substrate 101 is in direct contact with the end of the second conductor sub-portion 105c away from the channel portion 105a. The third insulating portion at least covers part of the end of the second conductor sub-portion 105c away from the channel portion 105a. The end of the drain 107 close to the gate 108 is in contact with the second conductor sub-portion 105c through the second opening, and the end of the drain 107 close to the gate 108 covers the end of the third insulating portion close to the first insulating portion.

[0100] Referring to Figure 2 , in some embodiments, no insulating layer is provided between the source electrode 106 and the first conductor sub-segment 105b, and no insulating layer is provided between the drain electrode 107 and the second conductor sub-segment 105c. In other words, the source electrode 106 is directly located on the first conductor sub-segment 105b, and the drain electrode 107 is directly located on the second conductor sub-segment 105c. This facilitates forming the first metal layer 104 and the active layer 105 through a single patterning process, simplifying the manufacturing process and reducing manufacturing costs.

[0101] When there is no insulating layer between the source electrode 106 and the first conductor sub-portion 105b, and no insulating layer between the drain electrode 107 and the second conductor sub-portion 105c, the gate electrode 108 is located on the side of the first metal layer 104 away from the substrate 101, and the gate insulating layer 109 is interposed between the channel portion 105a and the gate electrode 108. The orthographic projection of the gate electrode 108 on the substrate 101 is located within the orthographic projection of the gate insulating layer 109 on the substrate 101, and the orthographic projection of the channel portion 105a on the substrate 101 is located within the orthographic projection of the gate insulating layer 109 on the substrate 101. In this case, the material of the gate electrode 108 can be a double-layer structure consisting of a Cu layer and a MoTi alloy layer, wherein the Cu layer is located on the side of the gate electrode 108 closer to the substrate 101, and the MoTi alloy layer is located on the side of the gate electrode 108 away from the substrate 101. The thickness of the Cu layer is 1800 angstroms to 4200 angstroms, for example, 1900 angstroms, 2500 angstroms, 3000 angstroms, 3500 angstroms, 4000 angstroms, etc. The thickness of the MoTi alloy layer is 250 angstroms to 350 angstroms, for example, 280 angstroms, 300 angstroms, 320 angstroms, 340 angstroms, etc.

[0102] When there is no insulating layer between the source 106 and the first conductor sub-portion 105b, and no insulating layer between the drain 107 and the second conductor sub-portion 105c, in a plane parallel to the substrate 101, along the direction from the channel portion 105a to the first conductor sub-portion 105b, the edge of the source 106 away from the gate 108 exceeds the edge of the first conductor sub-portion 105b away from the channel portion 105a; in a plane parallel to the substrate 101, along the direction from the channel portion 105a to the second conductor sub-portion 105c, the edge of the drain 107 away from the gate 108 exceeds the edge of the second conductor sub-portion 105c away from the channel portion 105a.

[0103] In this embodiment, the gate electrode 108 , the source electrode 106 , the drain electrode 107 , and the active layer 105 constitute a thin film transistor device of the display panel 100 .

[0104] Referring to Figures 1 and 2, in this embodiment, the display panel 100 further includes a second metal layer 110, which is located between the active layer 105 and the substrate 101. The second metal layer 110 includes a first light shielding portion 110a, and the orthographic projection of the active layer 105 on the substrate 101 is located within the orthographic projection of the first light shielding portion 110a on the substrate 101. The provision of the first light shielding portion 110a helps prevent light from the substrate 101 from reaching the active layer 105, thereby affecting the operating performance of the active layer 105.

[0105] In some embodiments, the material of the second metal layer 110 can be selected from metal materials, such as Al, Ti, Mo, Cu, Ni, or alloys including the above metals. The second metal layer 110 can be a single layer or multiple layers formed by the above metal materials or alloys including the above metal materials. For example, the second metal layer 110 can be a double-layer stack of MoTi / Cu formed by a MoTi alloy layer and a Cu layer, wherein the MoTi alloy layer is located on the side close to the substrate 101, and the Cu layer is located on the side away from the substrate 101. Setting the second metal layer 110 to MoTi / Cu, combined with the light-shielding performance of MoTi and the conductive performance of Cu, is conducive to maintaining the conductivity of the traces in the second metal layer 110 while achieving light shielding. Preferably, the thickness of the MoTi alloy layer can be 250 angstroms to 350 angstroms, for example, 280 angstroms, 300 angstroms, 320 angstroms, 340 angstroms, etc.; the thickness of the Cu layer can be 2800 angstroms to 8000 angstroms, for example, 2900 angstroms, 3000 angstroms, 3500 angstroms, 4000 angstroms, 4500 angstroms, 5000 angstroms, 5500 angstroms, 6000 angstroms, 6500 angstroms, 7000 angstroms, 7500 angstroms, etc.

[0106] The display panel 100 further includes a buffer layer 111 . The buffer layer 111 is located on a side of the active layer 105 close to the substrate 101 . The buffer layer 111 covers the second metal layer 110 .

[0107] The buffer layer 111 is spaced between the second metal layer 110 and the active layer 105 . The side of the buffer layer 111 away from the substrate 101 is in direct contact with the active layer 105 . The side of the buffer layer 111 away from the substrate 101 is in direct contact with the passivation layer 112 .

[0108] In some embodiments, a side of the buffer layer 111 close to the substrate 101 is in direct contact with the second metal layer 110 , and a side of the buffer layer 111 close to the substrate 101 is in direct contact with the substrate 101 .

[0109] In some embodiments, the material of the buffer layer 111 is selected from at least one of a silicon nitride compound and a silicon oxide compound. The buffer layer 111 can be a single layer or a stack of silicon nitride compounds or silicon oxide compounds. For example, the buffer layer 111 can include a first buffer sublayer and a second buffer sublayer, the first buffer sublayer being made of a silicon nitride compound and the second buffer sublayer being made of a silicon oxide compound. The first buffer sublayer is located on the side of the buffer layer 111 close to the substrate 101, and the second buffer sublayer is located on the side of the buffer layer 111 away from the substrate 101. The thickness of the first buffer sublayer is 500 angstroms to 2000 angstroms, for example, 800 angstroms, 1000 angstroms, 1200 angstroms, 1500 angstroms, 1800 angstroms, etc.; the thickness of the second buffer sublayer is 2000 angstroms to 3000 angstroms, for example, 2200 angstroms, 2500 angstroms, 2600 angstroms, 2800 angstroms, etc.

[0110] When the gate insulating layer 109 includes the first insulating portion, the second insulating portion and the third insulating portion that are arranged separately, the end of the second insulating portion away from the first insulating portion contacts the buffer layer 111, and the end of the third insulating portion away from the first insulating portion contacts the buffer layer 111.

[0111] In some embodiments, the first light shielding portion 110a is connected to the source 106; alternatively, the first light shielding portion 110a is connected to the drain 107. The connection of the first light shielding portion 110a to the source 106 or the drain 107 prevents electrical drift of the thin film transistor device caused by the first light shielding portion 110a, thereby improving the operating performance of the thin film transistor device.

[0112] Referring to FIG. 2 , when the gate electrode 108 is located on a side of the first metal layer 104 away from the substrate 101, and no insulating layer is present between the source electrode 106 and the first conductor sub-portion 105b, and no insulating layer is present between the drain electrode 107 and the second conductor sub-portion 105c, the source electrode 106 is connected to the first light shielding portion 110a via the anode 102; alternatively, the drain electrode 107 is connected to the first light shielding portion 110a via the anode 102. In this case, the first insulating layer further includes a second via located on a side of the active layer 105, the buffer layer 111 includes a third via connected to the second via, and the anode 102 is connected to the first light shielding portion 110a via the second and third vias. The anode 102 includes a second connecting portion, and the orthographic projection of the pixel defining portion 103 on the substrate 101 overlaps the orthographic projection of the second connecting portion on the substrate 101. Specifically, the buffer layer 111 includes a buffer portion that covers the first light-shielding portion 110a. The second via penetrates the first insulating layer, and the third via penetrates the buffer portion of the buffer layer 111. The orthographic projection of the second via on the substrate 101 covers the orthographic projection of the third via on the substrate 101. The second and third vias expose the first light-shielding portion 110a, and the second connecting portion contacts the first light-shielding portion 110a. When the anode 102 is connected to the source 106, the source 106 is connected to the first light-shielding portion 110a through the anode 102; when the anode 102 is connected to the drain 107, the drain 107 is connected to the first light-shielding portion 110a through the anode 102.

[0113] When the gate insulating layer 109 includes the first insulating portion, the second insulating portion, and the third insulating portion, which are disposed apart from each other, the gate insulating layer 109 includes a fourth via hole, the fourth via hole being located on a side of the second insulating portion away from the active layer 105, the buffer layer 111 includes a fifth via hole, the fifth via hole being located in the buffer layer 111, the fourth via hole being connected to the fifth via hole, and the source electrode 106 being connected to the first light shielding portion 110a through the fourth and fifth via holes. Specifically, the buffer layer 111 includes a buffer portion covering the first light shielding portion 110a, the fourth via hole penetrating a side of the second insulating portion away from the active layer 105, the fifth via hole penetrating the buffer portion, and the orthographic projection of the fourth via hole on the substrate 101 covering the orthographic projection of the fifth via hole on the substrate 101. The source 106 includes a source 106 connecting portion, which is located in the fourth via hole and the fifth via hole. The fourth via hole and the fifth via hole expose the first light shielding portion 110a. The source 106 connecting portion contacts the first light shielding portion 110a to achieve connection between the source 106 and the first light shielding portion 110a.

[0114] Alternatively, referring to FIG1 , when the gate insulating layer 109 includes the first insulating portion, the second insulating portion, and the third insulating portion, which are disposed apart from each other, the gate insulating layer 109 includes a sixth via hole, which passes through the side of the third insulating portion away from the active layer 105. The buffer layer 111 includes a seventh via hole, which passes through the buffer layer 111. The sixth via hole communicates with the seventh via hole, and the drain electrode 107 is connected to the first light shielding portion 110a through the sixth and seventh via holes. Specifically, the sixth via hole passes through the side of the third insulating portion away from the active layer 105, the seventh via hole passes through the buffer portion, and the orthographic projection of the sixth via hole on the substrate 101 overlaps the orthographic projection of the seventh via hole on the substrate 101. The drain 107 includes a drain 107 connecting portion, which is located in the sixth via hole and the seventh via hole. The sixth via hole and the seventh via hole expose the first light shielding portion 110a. The drain 107 connecting portion contacts the first light shielding portion 110a to achieve connection between the drain 107 and the first light shielding portion 110a.

[0115] In this embodiment, the display panel 100 includes a display area and a non-display area located at least on one side of the display area. The display panel 100 further includes a terminal located in the non-display area. The terminal is located in the first metal layer 104 .

[0116] The non-display area has a plurality of terminals, including first-type terminals connected to the second metal layer 110. The second metal layer 110 also includes second metal layer wirings, and the first-type terminals are connected to the second metal layer wirings.

[0117] When the gate insulating layer 109 includes the first insulating portion, the second insulating portion, and the third insulating portion, which are disposed apart from each other, the gate insulating layer 109 further includes a fourth insulating portion located between the terminal and the buffer layer 111. The gate insulating layer 109 further includes an eighth via, which passes through the fourth insulating portion. The buffer layer 111 includes a ninth via, which passes through the buffer layer 111 between the second metal layer trace and the fourth insulating portion. The orthographic projection of the eighth via on the substrate 101 covers the orthographic projection of the ninth via on the substrate 101. The first-type terminal includes a first-type terminal connecting portion, which is located within the eighth and ninth vias. The eighth and ninth vias expose the second metal layer trace, and the first-type terminal connecting portion contacts the second metal layer trace.

[0118] When the gate 108 is located on the side of the first metal layer 104 away from the substrate 101, there is no insulating layer between the source 106 and the first conductor sub-portion 105b, and there is no insulating layer between the drain 107 and the second conductor sub-portion 105c, the buffer layer 111 includes a tenth via, and the tenth via passes through the buffer layer 111 between the second metal layer routing and the first type of terminal, the first type of terminal includes a first type of terminal connecting portion, the first type of terminal connecting portion is located in the tenth via, the tenth via exposes the second metal layer routing, and the first type of terminal connecting portion is in contact with the second metal layer routing.

[0119] In some embodiments, the pixel defining portion 103 and the anode 102 have an overlapping portion, and the width of the orthographic projection of the overlapping portion on the substrate 101 is greater than 2 microns. This is to prevent exposure of the edge of the anode 102 due to process errors and to facilitate covering the first connecting portion and / or the second connecting portion. The anode 102 has a central portion not covered by the pixel defining portion 103 and a peripheral portion covered by the pixel defining portion 103. The orthographic projection of the peripheral portion on the substrate 101 coincides with the orthographic projection of the overlapping portion on the substrate 101. The overlapping portion includes a first side proximal to the central portion and a second side distal to the central portion. The width of the orthographic projection of the overlapping portion on the substrate 101 is greater than 2 microns, that is, the minimum distance between the first side and the second side is greater than 2 microns.

[0120] In some embodiments, the spacing between adjacent anodes 102 is greater than 7 microns, so that the pixel definition parts 103 are spaced apart by a sufficient distance while ensuring sufficient resolution, which helps to relieve the stress on the pixel definition parts 103 and improve the light output rate of the display panel 100.

[0121] Referring to Figures 1 and 2 , in this embodiment, the planar layer 113 is parallel to the substrate 101, and the pixel definition portion 103 is in direct contact with the planar layer 113. The first angle α is equal to the angle formed between the first side surface 103a and the planar layer 113. The first angle α is greater than or equal to 35 degrees, and less than or equal to 45 degrees. For example, the first angle α can be 36 degrees, 37 degrees, 38 degrees, 39 degrees, 40 degrees, 41 degrees, 42 degrees, 43 degrees, 44 degrees, etc. The angle value of the first angle α within the above range makes the slope of the first side surface 103a more gentle. While maintaining the same height, the total surface area of ​​the pixel definition portion 103 is increased, which helps to increase the contact area between the pixel definition portion 103 and the adjacent film layer, thereby strengthening the bond between the pixel definition portion 103 and the adjacent film layer. This prevents the film layer from separating when the display panel 100 is used in a foldable environment, thereby improving the product quality of the display panel 100.

[0122] Referring to Figures 1 and 2 , in this embodiment, the display panel 100 further includes an organic layer 119 located on the side of the anode 102 facing away from the substrate 101. The organic layer 119 includes a light-emitting layer 120. Along a direction parallel to the substrate 101, the pixel defining portion 103 includes a second side surface 103b proximal to the anode 102. The orthographic projection of the anode 102 on the substrate 101 and the orthographic projection of the second side surface 103b on the substrate 101 jointly cover the orthographic projection of the light-emitting layer 120 on the substrate 101. That is, the light-emitting layer 120 is located within the pixel defining opening, and the edge of the light-emitting layer 120 does not extend beyond the second side surface 103b. The orthographic projection of the anode 102 on the substrate 101 and the orthographic projection of the second side surface 103b on the substrate 101 jointly cover the orthographic projection of the light-emitting layer 120 on the substrate 101. This helps prevent light-emitting layers of different colors (e.g., red, green, and blue) from mixing outside the pixel defining portion 103, which could affect the display quality of the display panel 100.

[0123] Referring to Figures 1 and 2, in some embodiments, a side of the second side surface 103b proximal to the anode 102 has a second angle β with the anode 102, wherein the second angle β is greater than or equal to 35 degrees, and the second angle β is less than or equal to 45 degrees. For example, the second angle β may be 36 degrees, 37 degrees, 38 degrees, 39 degrees, 40 degrees, 41 degrees, 42 degrees, 43 degrees, 44 degrees, etc. When the second angle β is within the above range, the second side surface 103b is more gentle, which facilitates the formation of the light-emitting layer 120 within the second side surface 103b.

[0124] In this embodiment, the organic layer 119 includes a hole injection layer, a hole transport layer, an electron transport layer, and an electron injection layer located within the pixel-defining opening. The hole injection layer is located on the side of the anode 102 away from the substrate 101. The hole injection layer, the hole transport layer, the light-emitting layer, the electron transport layer, and the electron injection layer are stacked in this order.

[0125] In this embodiment, the display panel 100 further includes a cathode, which covers at least a side of the organic layer away from the substrate 101 .

[0126] The anode 102 , the cathode, and the organic layer constitute a light-emitting element.

[0127] In the embodiment of the present invention, the pixel definition portion 103 is arranged in a one-to-one correspondence with the anode 102, and adjacent pixel definition portions 103 are spaced apart, thereby reducing the stress on the pixel definition portion 103. In addition, the slope of the first side surface 103a of the pixel definition portion 103 is gentler, thereby increasing the contact area between the pixel definition portion 103 and the adjacent film layer, enhancing the firmness of the connection between the pixel definition portion 103 and the adjacent film layer, and improving the product quality of the display panel 100.

[0128] Referring to FIG. 1 to FIG. 3 and FIG. 4 a to FIG. 4 m , an embodiment of the present invention further provides a method for manufacturing a display panel 100 , including:

[0129] S100 , providing a substrate 101 .

[0130] S200 , forming an anode material layer on the substrate 101 .

[0131] S300 , forming a pixel definition material layer on the anode material layer.

[0132] S400 , the anode material layer and the pixel definition material layer are subjected to a first patterning process to form a plurality of anodes 102 and a plurality of pixel definition portions 103 , respectively.

[0133] The pixel definition portion 103 covers the edge of the anode 102 and exposes a portion of the anode 102 . One pixel definition portion 103 is disposed around one anode 102 , and adjacent pixel definition portions 103 are disposed at intervals.

[0134] Along a direction parallel to the substrate 101, the pixel definition portion 103 includes a first side surface 103a away from the anode 102, and the side of the first side surface 103a close to the substrate 101 has a first angle α with the substrate 101, and the first angle α is greater than or equal to 35 degrees, and the first angle α is less than or equal to 45 degrees.

[0135] In this embodiment, the material of the substrate 101 has been described in detail in the aforementioned display panel 100 and will not be repeated here.

[0136] In this embodiment, the anode material layer includes a material with a high work function. The anode material layer includes one of indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), indium oxide (In2O3), etc., and the above-mentioned material is a conductive material with a relatively high work function and is transparent. In addition to the conductive materials listed above, the anode material layer may also include a reflective material such as silver (Ag), magnesium (Mg), aluminum (Al), platinum (Pt), palladium (Pb), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), lithium (Li), calcium (Ca) or a combination thereof. The anode material layer may be composed of a single layer or multiple layers of a transparent conductive material and / or a reflective conductive material. For example, the anode material layer may be a three-layer stack of IZO material layer / Ag material layer / IZO material layer formed by an IZO material layer and an Ag material layer. The anode material layer may be formed by physical vapor deposition or chemical vapor deposition.

[0137] In this embodiment, the material of the pixel definition material layer is selected from organic materials, such as positive photoresist materials or negative photoresist materials, so that the pixel definition material layer can be used as a photoresist. The pixel definition portion 103 and the anode 102 are formed by the same patterning process, which saves process technology and reduces process costs.

[0138] In some embodiments, step S400 includes:

[0139] S410 , using a first mask to expose the pixel definition material layer.

[0140] The first mask may be a half-tone mask.

[0141] S420 , developing the pixel definition material layer to form a first photoresist region, a second photoresist region, and a first non-photoresist region.

[0142] The thickness of the pixel definition material layer in the first photoresist region is greater than the thickness of the pixel definition material layer in the second photoresist region.

[0143] S430 , using a first etching process to remove the anode material layer corresponding to the first non-photoresistive region to form the anode 102 .

[0144] The first etching process can be a wet etching process. When the anode material layer is a three-layer stack of IZO material layer / Ag material layer / IZO material layer formed by IZO material layer and Ag material layer, a first etchant is used in the first etching process. The first etchant includes phosphoric acid, nitric acid, etc., which is used to etch the Ag material layer and the IZO material layer.

[0145] S440 , removing the pixel definition material layer in the second photoresist region, and retaining the pixel definition material layer in the first photoresist region to form the pixel definition portion 103 .

[0146] The pixel definition material layer in the second photoresist region may be removed by an ashing process.

[0147] In some embodiments, step S400 further includes:

[0148] S450 , cleaning the pixel definition portion 103 and the anode 102 .

[0149] S460 , performing a heating process on the pixel definition portion 103 .

[0150] The material, thickness, and structure of the anode 102 and the pixel defining portion 103 have been described in detail in the aforementioned display panel 100 and will not be repeated here.

[0151] In this embodiment, before step S200, the following steps are included:

[0152] Please refer to FIG. 4 b , S500 , forming a second metal layer 110 on the substrate 101 .

[0153] In this embodiment, the material, thickness, and structure of the second metal layer 110 have been described in detail in the aforementioned display panel 100 and will not be repeated here.

[0154] Please refer to FIG. 4 c , S 600 , forming a buffer material layer 115 on the second metal layer 110 .

[0155] The buffer material layer 115 covers the second metal layer 110 and the substrate 101 .

[0156] S700 , forming a thin film transistor layer on the buffer material layer 115 .

[0157] S800 , forming a passivation layer 112 and a planarization layer 113 on the thin film transistor layer.

[0158] In this embodiment, the material, thickness, and structure of the passivation layer 112 and the planar layer 113 have been described in detail in the aforementioned display panel 100 and will not be repeated here.

[0159] The passivation material layer covers the thin film transistor layer, and the planarization material layer covers the passivation material layer. The planarization material layer is made of a positive photoresist material or a negative photoresist material.

[0160] Referring to FIG. 4 d to FIG. 4 h , in some embodiments, step S700 includes:

[0161] S710 , forming a semiconductor layer 114 and a first metal layer 104 on the buffer layer 111 .

[0162] Step S710 includes:

[0163] S711 , forming a semiconductor material layer 116 on the substrate 101 .

[0164] S712 , forming a first metal material layer 117 on the semiconductor material layer 116 , wherein the first metal material layer 117 is in direct contact with the semiconductor material layer 116 .

[0165] S713 , the semiconductor material layer 116 and the first metal material layer 117 are subjected to a second patterning process to form a semiconductor layer 114 and a first metal layer 104 , respectively.

[0166] The first metal layer 104 includes a source electrode 106 and a drain electrode 107 . The source electrode 106 and the drain electrode 107 are respectively located on two opposite sides of the semiconductor layer 114 .

[0167] There is no insulating layer between the source 106 and the first conductor sub-portion 105 b , and there is no insulating layer between the drain 107 and the second conductor sub-portion 105 c .

[0168] Step S713 includes:

[0169] S713a, forming a first photoresist material layer 118 on the first metal material layer.

[0170] S713b, using a second mask to expose the first photoresist material layer 118.

[0171] The second mask Mask may be a halftone mask.

[0172] S713c: After the first photoresist material layer 118 is developed, a third photoresist region, a fourth photoresist region and a second non-photoresist region are formed.

[0173] The thickness of the first photoresist material layer 118 in the third photoresist region is greater than the thickness of the first photoresist material layer 118 in the fourth photoresist region.

[0174] S713d, using a second etching process to remove the semiconductor material layer 116 and the first metal material layer 117 corresponding to the second non-photoresistive region to form the semiconductor layer 114.

[0175] The second etching process may be a wet etching process.

[0176] S713e, removing the first photoresist material layer 118 in the fourth photoresist region by using an ashing process.

[0177] S713f, using a third etching process to remove the first metal material layer 117 corresponding to the fourth photoresist region to form the first metal layer 104.

[0178] The third etching process can be a wet etching process. When the first metal material layer is a MoTi / Cu / MoTi three-layer stacked structure formed by a MoTi layer, a Cu layer, and a MoTi layer, a second etchant is used in the third etching process. The second etchant does not contain fluorine to avoid damaging the semiconductor layer 114. The second etchant includes components such as hydrogen peroxide and is used for the first metal material layer.

[0179] S713g, remove the first photoresist layer 118.

[0180] S720 , forming a gate insulating layer 109 and a gate 108 between the source 106 and the drain 107 .

[0181] Step S720 includes:

[0182] S721 , forming a gate insulating material layer on the first metal layer 104 .

[0183] S722 , forming a gate material layer on the gate insulating material layer.

[0184] S723 , the gate insulating material layer and the gate material layer are subjected to a third patterning process to form the gate insulating layer 109 and the gate 108 .

[0185] Step S723 includes:

[0186] S723a, forming a second photoresist material layer on the gate material layer.

[0187] S723b, using a third mask to expose the second photoresist layer.

[0188] S723c: The second photoresist material layer is developed to form a fifth photoresist region and a third non-photoresist region.

[0189] S723d, using a fourth etching process to remove the gate material layer corresponding to the third non-photoresistive region to form the gate 108.

[0190] The fourth etching process may be a wet etching process.

[0191] S723e: Use a fifth etching process to remove the gate insulating material layer corresponding to the third non-photoresistive region to form the gate insulating layer 109.

[0192] The fifth etching process may be a dry etching process.

[0193] S723f, remove the second photoresist material layer.

[0194] S730 , performing a conductor treatment on the semiconductor layer 114 to form an active layer 105 .

[0195] The conductorization treatment may be performed by ion implantation or plasma bombardment to form the active layer 105 . The active layer 105 includes a channel portion 105 a and a first conductor sub-portion 105 b and a second conductor sub-portion 105 c located on opposite sides of the channel portion 105 a .

[0196] In this embodiment, the materials, thicknesses, and structures of the gate insulating layer 109 , the first metal layer 104 , and the active layer 105 have been described in detail in the aforementioned display panel 100 and will not be repeated here.

[0197] Referring to FIG. 4i , when the thin film transistor layer is formed through steps S710 to S730 , step S800 includes:

[0198] S810 , forming a passivation layer 112 and a buffer layer 111 .

[0199] Step S810 includes:

[0200] S811 , forming a third photoresist material layer on the passivation material layer.

[0201] S812 , using a fourth mask to expose the third photoresist material layer.

[0202] S813 , developing the third photoresist material layer to form a sixth photoresist region and a fourth non-photoresist region.

[0203] The fourth non-photoresistor region includes a first non-photoresistor sub-region and a second non-photoresistor sub-region.

[0204] S814 , using a sixth etching process to remove the passivation material layer corresponding to the first non-photoresistor sub-region, and to remove the passivation material layer and the buffer material layer 115 corresponding to the second non-photoresistor sub-region, to form the passivation layer 112 and the buffer layer 111 .

[0205] The sixth etching process may be a dry etching process.

[0206] S815 , removing the third photoresist material layer.

[0207] S820 , forming a planarization layer 113 .

[0208] Step S820 includes:

[0209] S821 , using a fifth mask to expose the planar material layer.

[0210] S822 , forming a first planar layer 113 via hole and a second planar layer 113 via hole after developing the planar material layer.

[0211] The planar layer 113 and the passivation layer 112 form a first insulating layer. A via hole is formed in the first planar layer 113 and the passivation material layer corresponding to the first non-light-resistor region is removed to form a first via hole H1 in the first insulating layer. The anode 102 is connected to the source 106 or the drain 107 through the first via hole H1. A via hole is formed in the second planar layer 113 and the passivation material layer corresponding to the second non-light-resistor region is removed to form a second via hole in the first insulating layer. The buffer material layer 115 corresponding to the second non-light-resistor region is removed to form a third via hole. The third via hole is connected to the second via hole. The anode 102 is connected to the first light-shielding portion 110a in the second metal layer 110 through the second via hole and the third via hole.

[0212] The passivation material layer corresponding to the first non-photoresistor region is removed to expose the source 106 or the drain 107. Since the passivation material layer corresponding to the first non-photoresistor region and the passivation material layer and the buffer material layer 115 corresponding to the second non-photoresistor region are removed, the source 106 or the drain 107 is over-etched, and dry etching causes slight damage to the metal material. Therefore, the passivation layer 112 and the buffer layer 111 can be formed by the same etching process, thereby reducing the process cost.

[0213] Referring to FIG. 4j to FIG. 4l , in some embodiments, step S700 includes:

[0214] S740 , forming a semiconductor layer 114 on the buffer layer 111 .

[0215] In some embodiments, step S740 includes:

[0216] S741 , forming a semiconductor material layer on the buffer layer 111 .

[0217] S742 , the semiconductor material layer is subjected to a fourth patterning process to form the semiconductor layer 114 .

[0218] Step S742 includes:

[0219] S742a, forming a fourth photoresist material layer on the semiconductor material layer.

[0220] S742b, using a sixth mask to expose the fourth photoresist material layer.

[0221] S742c: The fourth photoresist material layer is developed to form a seventh photoresist region and a fifth non-photoresist region.

[0222] S742d, using a seventh etching process to remove the semiconductor material layer corresponding to the fifth non-photoresistive region to form the semiconductor layer 114.

[0223] The seventh etching process may be a wet etching process.

[0224] S742e, removing the fourth photoresist material layer.

[0225] S750 , forming a gate insulating layer 109 and a buffer layer 111 .

[0226] Step S750 includes:

[0227] S751 , forming a gate insulating material layer on the semiconductor layer 114 , wherein the gate insulating material layer covers the semiconductor layer 114 and the buffer material layer 115 .

[0228] S752 , the gate insulating material layer is subjected to a fifth patterning process to form the semiconductor layer 114 .

[0229] Step S752 includes:

[0230] S752a, forming a fifth photoresist material layer on the gate insulating material layer.

[0231] S752b, using a seventh mask to expose the fifth photoresist material layer.

[0232] S752c: After the fifth photoresist material layer is developed, an eighth photoresist region and a sixth non-photoresist region are formed.

[0233] The sixth non-photoresistor region includes a third non-photoresistor sub-region, a fourth non-photoresistor sub-region, and a fourth non-photoresistor sub-region.

[0234] S752d, using the eighth etching process to remove the gate insulating material layer corresponding to the third and fourth photoresistor-free regions, the gate insulating material layer corresponding to the fifth photoresistor-free region, and the buffer material layer 115 to form the gate insulating layer 109 and the buffer layer 111.

[0235] The eighth etching process may be a dry etching process.

[0236] The gate insulating layer 109 includes a first insulating portion, a second insulating portion and a third insulating portion. The gate insulating material layer and the buffer layer 111 corresponding to the third non-photoresistor region, the fourth non-photoresistor region and the fifth non-photoresistor region are removed to form the first opening, the second opening and the fourth via hole or the sixth via hole of the gate insulating layer 109, and the fifth via hole or the seventh via hole of the buffer layer 111, respectively.

[0237] The fourth via is located on a side of the second insulating portion away from the active layer 105, the buffer layer 111 includes a fifth via, the fourth via is connected to the fifth via, the source 106 is connected to the first light-shielding portion 110a of the second metal layer 110 through the fourth via and the fifth via; or, the sixth via is located on a side of the third insulating portion away from the active layer 105, the buffer layer 111 includes a seventh via, the sixth via is connected to the seventh via, and the drain 107 is connected to the first light-shielding portion 110a through the sixth via and the seventh via.

[0238] S760 , the semiconductor layer 114 forms an active layer 105 .

[0239] The semiconductor layer 114 is conductively treated by using the first opening and the second opening to form the active layer 105 .

[0240] The conductorization treatment may be performed by ion implantation or plasma bombardment.

[0241] S770 , forming a first metal layer 104 on the gate insulating layer 109 .

[0242] The first metal layer 104 includes the source 106 , the drain 107 , and the gate 108 .

[0243] Step S770 includes:

[0244] S771 , forming a first metal material layer on the gate insulating layer 109 .

[0245] S772 , the first metal material layer is subjected to a sixth patterning process to form the first metal layer 104 .

[0246] Step S772 includes:

[0247] S772a, forming a sixth photoresist material layer on the first metal material layer.

[0248] S772b, using an eighth mask to expose the sixth photoresist material layer.

[0249] S772c: After the sixth photoresist material layer is developed, a ninth photoresist region and a seventh non-photoresist region are formed.

[0250] The ninth photoresistance region includes a first photoresistance sub-region, a second photoresistance sub-region, and a third photoresistance sub-region.

[0251] S772d, using a ninth etching process to remove the first metal material layer corresponding to the seventh non-photoresistive region to form the first metal layer 104.

[0252] The first metal material layer corresponding to the first photoresistor region, the second photoresistor region, and the third photoresistor region respectively forms the source 106 , the drain 107 , and the gate 108 .

[0253] The ninth etching process may be a wet etching process.

[0254] S772e, removing the sixth photoresist material layer.

[0255] In this embodiment, the materials, thicknesses, and structures of the gate insulating layer 109 , the first metal layer 104 , and the active layer 105 have been described in detail in the aforementioned display panel 100 and will not be repeated here.

[0256] Referring to FIG. 4 m , when the thin film transistor layer is formed through steps S740 to S770 , step S800 includes:

[0257] S830 , forming a passivation layer 112 and a planarization layer 113 on the thin film transistor layer.

[0258] Step S830 includes:

[0259] S831 , forming a passivation material layer on the thin film transistor layer.

[0260] S832 , forming a flat material layer on the passivation material layer.

[0261] The material of the flat material layer is selected from positive photoresist material or negative photoresist material.

[0262] S834 , the passivation material layer and the planar material layer are subjected to a seventh patterning process to form the passivation layer 112 and the planar layer 113 .

[0263] Step S834 includes:

[0264] S834a, using an eighth mask to expose the planar material layer.

[0265] S834b: After the planar material layer is developed, a tenth photoresist region and an eighth non-photoresist region are formed to form the planar layer 113.

[0266] S834c, using a tenth etching process to remove the passivation material layer corresponding to the eighth non-photoresistive region to form the passivation layer 112.

[0267] The tenth etching process may be a dry etching process.

[0268] The planar layer 113 and the passivation layer 112 form a first insulating layer. The eighth non-photoresistive region and the passivation material layer corresponding to the eighth non-photoresistive region are removed to form a first via hole H1 in the first insulating layer. The anode 102 is connected to the first metal layer 104 through the first via hole H1.

[0269] In this embodiment, step S500 may include:

[0270] S510 , forming a second metal material layer on the substrate 101 .

[0271] S520 , the second metal material layer is subjected to an eighth patterning process to form the second metal layer 110 .

[0272] Step S520 includes:

[0273] S520a, forming a seventh photoresist material layer on the second metal material layer.

[0274] S520b, using a tenth mask to expose the seventh photoresist material layer.

[0275] S520c: After the seventh photoresist material layer is developed, an eleventh photoresist region and a ninth non-photoresist region are formed.

[0276] S520d, using an eleventh etching process to remove the second metal material layer corresponding to the ninth non-photoresistive region to form the second metal layer 110.

[0277] The eleventh etching process may be a wet etching process.

[0278] S520e, removing the seventh photoresist layer.

[0279] In the method for manufacturing a display panel provided by an embodiment of the present invention, the film layer between the substrate 101 and the pixel definition portion 103 only requires six patterning processes, which reduces process costs and improves process efficiency. At the same time, the pixel definition portion 103 and the anode 102 are arranged in a one-to-one correspondence, and adjacent pixel definition portions 103 are spaced apart, which reduces the stress on the pixel definition portion 103. In addition, the first side surface 103a of the pixel definition portion 103 has a gentler slope, which increases the contact area between the pixel definition portion 103 and the adjacent film layer, enhances the firmness of the bond between the pixel definition portion 103 and the adjacent film layer, and improves the product quality of the manufactured display panel.

[0280] An embodiment of the present invention discloses a display panel and a method for manufacturing the same; the display panel includes a substrate, multiple anodes located on the substrate, and multiple pixel definition parts covering the edges of the anodes and exposing parts of the anodes, wherein a pixel definition part is arranged around an anode, and adjacent pixel definition parts are arranged at intervals. Along a direction parallel to the substrate, the pixel definition part includes a first side surface away from the anode, and a side of the first side surface close to the substrate has a first angle with the substrate, the first angle is greater than or equal to 35 degrees, and the first angle is less than or equal to 45 degrees. The present invention reduces the stress on the pixel definition part by arranging the pixel definition part and the anode in a one-to-one correspondence and spacing the adjacent pixel definition parts, and the slope of the first side surface of the pixel definition part is gentler, thereby increasing the contact area between the pixel definition part and the adjacent film layer, enhancing the firmness of the bonding between the pixel definition part and the adjacent film layer, and improving the product quality of the display panel.

[0281] It is understandable that those skilled in the art can make equivalent substitutions or changes based on the technical solution and inventive concept of this application, and all these changes or substitutions should fall within the scope of protection of the claims attached to this application.

Claims

1. A display panel, wherein: include: substrate; a plurality of anodes disposed on the substrate; A plurality of pixel definition parts, wherein the pixel definition parts cover the edge of the anode and expose a portion of the anode; Wherein, one of the pixel definition parts is arranged around one of the anodes, and adjacent pixel definition parts are arranged at intervals; Along a direction parallel to the substrate, the pixel definition portion includes a first side surface away from the anode, and the first side surface close to the substrate has a first angle with the substrate, the first angle is greater than or equal to 35 degrees, and the first angle is less than or equal to 45 degrees.

2. The display panel according to claim 1, wherein: The display panel further includes a first metal layer, wherein the first metal layer is located between the anode and the substrate; The display panel also includes a first insulating layer, which is located between the first metal layer and the anode. The first insulating layer includes a first via hole. The anode includes a first connecting portion located in the first via hole, the first connecting portion is connected to the first metal layer, and the pixel definition portion covers the first connecting portion.

3. The display panel according to claim 2, wherein: The display panel further comprises an active layer, the active layer is located between the first metal layer and the substrate, the active layer comprises a channel portion and a first conductor sub-portion and a second conductor sub-portion respectively located at opposite sides of the channel portion; The first metal layer includes a source electrode and a drain electrode, the source electrode is located on the first conductor sub-portion, and the drain electrode is located on the second conductor sub-portion; Wherein, at least a part of the source electrode near the active layer contacts the first conductor sub-portion, and at least a part of the drain electrode near the active layer contacts the second conductor sub-portion.

4. The display panel according to claim 3, wherein: The display panel further comprises a gate, the gate being located between the source electrode and the drain electrode, and an orthographic projection of the gate on the active layer covering the channel portion; The display panel further includes a gate insulating layer, and the gate insulating layer is at least spaced between the gate and the channel portion.

5. The display panel according to claim 4, wherein: The gate is located in the first metal layer, the gate insulating layer includes a first insulating portion, a second insulating portion and a third insulating portion which are separated from each other, the first insulating portion is spaced between the channel portion and the gate, the second insulating portion is spaced between a portion of the source and the first conductor sub-portion, and the third insulating portion is spaced between a portion of the drain and the second conductor sub-portion; One end of the source electrode close to the gate electrode contacts the first conductor sub-portion, and one end of the drain electrode close to the gate electrode contacts the second conductor sub-portion.

6. The display panel according to claim 4, wherein: The gate is located at a side of the first metal layer away from the substrate, no insulating layer is between the source and the first conductor sub-portion, and no insulating layer is between the drain and the second conductor sub-portion.

7. The display panel according to claim 6, wherein: In a plane parallel to the substrate, along a direction from the channel portion to the first conductor sub-portion, an edge of a side of the source electrode away from the gate exceeds an edge of a side of the first conductor sub-portion away from the channel portion; In a plane parallel to the substrate, along a direction from the channel portion to the second conductor sub-portion, an edge of a side of the drain away from the gate exceeds an edge of a side of the second conductor sub-portion away from the channel portion.

8. The display panel according to claim 3, wherein: The display panel further includes a second metal layer, the second metal layer is located between the active layer and the substrate, the second metal layer includes a first light shielding portion, and an orthographic projection of the active layer on the substrate is located within an orthographic projection of the first light shielding portion on the substrate; The display panel further includes a buffer layer, which is located on a side of the active layer close to the substrate, and covers the second metal layer.

9. The display panel according to claim 8, wherein: The first insulating layer includes a passivation layer close to the substrate, the buffer layer is spaced between the second metal layer and the active layer, and the buffer layer is in direct contact with the active layer and the passivation layer on a side away from the substrate; A side of the buffer layer close to the substrate is in direct contact with the second metal layer and the substrate.

10. The display panel according to claim 9, wherein: When the gate insulating layer includes a first insulating portion, a second insulating portion and a third insulating portion that are separately arranged, an end of the second insulating portion away from the first insulating portion contacts the buffer layer, and an end of the third insulating portion away from the first insulating portion contacts the buffer layer.

11. The display panel according to claim 8, wherein: The first insulating layer further includes a second via hole, and the second via hole is located at one side of the active layer; The buffer layer includes a third via hole, the third via hole is connected to the second via hole, and the anode is connected to the first light shielding portion through the second via hole and the third via hole; The anode includes a second connection portion, and an orthographic projection of the pixel definition portion on the substrate covers an orthographic projection of the second connection portion on the substrate.

12. The display panel according to claim 8, wherein: The gate insulating layer includes a fourth via hole, which is located on a side of the second insulating portion away from the active layer. The buffer layer includes a fifth via hole, which is connected to the fifth via hole. The source electrode is connected to the first light shielding portion through the fourth via hole and the fifth via hole.

13. The display panel according to claim 8, wherein: The gate insulating layer includes a sixth via hole, which is located on a side of the third insulating portion away from the active layer. The buffer layer includes a seventh via hole, which is connected to the seventh via hole. The drain is connected to the first light shielding portion through the sixth via hole and the seventh via hole.

14. The display panel according to claim 2, wherein: The display panel includes a display area and a non-display area located at least on one side of the display area, the display panel also includes a terminal located in the non-display area, and the terminal is located in the first metal layer; Wherein, the terminals include first-type terminals, and the first-type terminals are connected to the second metal layer.

15. The display panel according to claim 14, wherein: When the gate insulating layer includes the first insulating portion, the second insulating portion, and the third insulating portion that are separated from each other, the gate insulating layer also includes a fourth insulating portion located between the terminal and the buffer layer, the gate insulating layer also includes an eighth via hole, the eighth via hole passes through the fourth insulating portion, the buffer layer includes a ninth via hole, the ninth via hole passes through the buffer layer between the second metal layer routing and the fourth insulating portion, and the orthographic projection of the eighth via hole on the substrate covers the orthographic projection of the ninth via hole on the substrate; The first-type terminal includes a first-type terminal connecting portion, which is located in the eighth via and the ninth via. The eighth via and the ninth via expose the second metal layer routing, and the first-type terminal connecting portion is in contact with the second metal layer routing.

16. The display panel according to any one of claims 1 to 15, wherein: The pixel definition portion and the anode have an overlapping portion, and a width of an orthographic projection of the overlapping portion on the substrate is greater than 2 micrometers.

17. The display panel according to claim 16, wherein: The display panel further comprises an organic layer located on a side of the anode away from the substrate, wherein the organic layer comprises a light-emitting layer; Along a direction parallel to the substrate, the pixel definition portion includes a second side surface close to the anode, and the orthographic projection of the anode on the substrate and the orthographic projection of the second side surface on the substrate jointly cover the orthographic projection of the light-emitting layer on the substrate.

18. The display panel according to claim 17, wherein: A side of the second side surface close to the anode has a second angle with the anode, and the second angle is greater than or equal to 35 degrees and less than or equal to 45 degrees.

19. A method for manufacturing a display panel, wherein: include: providing a substrate; forming an anode material layer on the substrate; forming a pixel definition material layer on the anode material layer; The anode material layer and the pixel definition material layer are subjected to a first patterning process to form a plurality of anodes and a plurality of pixel definition portions respectively; The pixel definition part covers the edge of the anode and exposes part of the anode, one pixel definition part is arranged around one anode, and adjacent pixel definition parts are arranged at intervals; Along a direction parallel to the substrate, the pixel definition portion includes a first side surface away from the anode, and the first side surface close to the substrate has a first angle with the substrate, the first angle is greater than or equal to 35 degrees, and the first angle is less than or equal to 45 degrees.

20. The method for manufacturing a display panel according to claim 19, wherein: Before forming the anode material layer on the substrate, the method further comprises: forming a semiconductor material layer on the substrate; forming a first metal material layer on the semiconductor material layer, wherein the first metal material layer is in direct contact with the semiconductor material layer; The semiconductor material layer and the first metal material layer are subjected to a second patterning process to form a semiconductor layer and a first metal layer respectively; The first metal layer includes a source electrode and a drain electrode, and the source electrode and the drain electrode are respectively located at two opposite sides of the semiconductor layer.

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