Display panel and display device

Abstract

The present application provides a display panel and a display device. A plurality of second pixels are electrically connected to a pixel driving circuit located in a main display area; a pixel driving circuit layer is provided with a plurality of first grooves corresponding to positions between the second pixels of the light-transmissive display area; the first grooves adjacent to different second pixels are communicated with each other; and the distance from a substrate to the surface, away from the substrate, of a first organic insulating sub-layer located at the first grooves is smaller than the distance from the substrate to the surface, away from the substrate, of the first organic insulating sub-layer located in the main display area.

Description

Display panel and display device Technical Field

[0001] The present application relates to the field of display technology, and in particular to a display panel and a display device. Background Art

[0002] To achieve a full-screen design, the imaging component is positioned in the translucent display area of ​​the display panel. However, setting the pixel density of the translucent display area too high will reduce the screen's light transmittance, affecting the imaging effect. Lowering the pixel density of the translucent display area will further affect the screen's display quality. Therefore, when the translucent display area and the main display area use the same pixel density, the low light transmittance of the translucent display area has become a barrier to the development of full-screen technology. SUMMARY OF THE INVENTION

[0003] Embodiments of the present application provide a display panel and a display device, which can improve the problem of low light transmittance in the light-transmitting display area when the light-transmitting display area and the main display area are designed with the same pixel density.

[0004] An embodiment of the present application provides a display panel, which includes a light-transmitting display area and a main display area adjacent to the light-transmitting display area, wherein the transmittance of the light-transmitting display area is greater than the transmittance of the main display area. The display panel includes a substrate, a pixel driving circuit layer, an organic insulating layer, and a light-emitting layer. The pixel driving circuit layer is located on the substrate, and the pixel driving circuit layer includes a plurality of stacked inorganic insulating layers and a plurality of pixel driving circuits arranged in the main display area. The organic insulating layer is located on the pixel driving circuit layer, and the organic insulating layer includes a first organic insulating sublayer and a second organic insulating sublayer located on the first organic insulating sublayer. The light-emitting layer is located on the organic insulating layer, and the light-emitting layer includes a plurality of first pixels located in the main display area and a plurality of second pixels located in the light-transmitting display area, and the first pixels and the second pixels are electrically connected to the corresponding pixel driving circuits. In which, the pixel driving circuit layer includes a plurality of first grooves arranged in the light-transmitting display area and located between the second pixels, the first grooves adjacent to different second pixels are connected to each other, the first organic insulating sublayer fills the first grooves, and the first distance from the surface of the first organic insulating sublayer located at the first groove to the substrate is smaller than the second distance from the surface of the substrate to the substrate of the first organic insulating sublayer located in the main display area.

[0005] Optionally, in some embodiments of the present application, the pixel driving circuit layer further comprises a plurality of raised portions disposed in the light-transmissive display area and corresponding to the second pixels, and the first groove is disposed around the raised portions. A third distance between the first organic insulating sublayer located on the raised portions and the surface of the substrate away from the substrate is greater than the first distance between the first organic insulating sublayer located on the first groove and the surface of the substrate away from the substrate, and is less than the second distance between the first organic insulating sublayer located in the main display area and the surface of the substrate away from the substrate.

[0006] Optionally, in some embodiments of the present application, the pixel driving circuit layer further includes a plurality of second grooves arranged in the light-transmitting display area and corresponding to the second pixels, and the second grooves are connected to the adjacent first grooves.

[0007] Optionally, in some embodiments of the present application, a fourth distance from the first organic insulating sublayer located at the second groove to the surface of the substrate is equal to the first distance from the first organic insulating sublayer located at the first groove to the surface of the substrate.

[0008] Optionally, in some embodiments of the present application, the depth of the first groove is equal to the depth of the second groove.

[0009] Optionally, in some embodiments of the present application, the first organic insulating sublayer includes a third groove disposed in the light-transmitting display area and corresponding to the first groove, wherein a width of the third groove is less than or equal to a width of the first groove.

[0010] Optionally, in some embodiments of the present application, a projection width of a sidewall of the third groove on the substrate is less than or equal to a projection width of a sidewall of the first groove on the substrate.

[0011] Optionally, in some embodiments of the present application, the first groove includes a plurality of stacked and interconnected sub-grooves, wherein the width of the sub-grooves away from the substrate is greater than the width of the sub-grooves close to the substrate.

[0012] Optionally, in some embodiments of the present application, the plurality of sub-grooves include a first sub-groove and a second sub-groove. The pixel driving circuit layer includes a buffer layer, a first gate insulating layer, a second gate insulating layer, and an interlayer dielectric layer. The buffer layer is located on the substrate, the first gate insulating layer is located on the buffer layer, the second gate insulating layer is located on the first gate insulating layer, and the interlayer dielectric layer is located on the second gate insulating layer. The buffer layer and the first gate insulating layer include the first sub-groove, the second gate insulating layer and the interlayer dielectric layer include the second sub-groove, and the width of the first sub-groove is smaller than the width of the second sub-groove.

[0013] Optionally, in some embodiments of the present application, an angle between the bottom surface of the second sub-groove and the sidewall of the second sub-groove is less than or equal to 115°.

[0014] Optionally, in some embodiments of the present application, the display panel further includes a light-shielding layer, which is located under the pixel driving circuit layer. The light-shielding layer is provided with an opening corresponding to the first groove, and the width of the opening is greater than or equal to the width of the first sub-groove.

[0015] Optionally, in some embodiments of the present application, the substrate includes a base and a barrier layer located on the base.

[0016] The present application also provides a display device, comprising any of the above-mentioned display panels. Beneficial effects

[0017] Compared with the prior art, the display panel and display device provided by the present application electrically connect the plurality of second pixels included in the light-transmitting display area to the pixel driving circuit located in the main display area, so that there is no pixel driving circuit design in the entire light-transmitting display area. The pixel driving circuit layer is provided with a plurality of first grooves between the second pixels corresponding to the light-transmitting display area, and the first grooves adjacent to different second pixels are interconnected. The first organic insulating sublayer included in the organic insulating layer fills the first grooves, so that the first distance from the surface of the first organic insulating sublayer located in the first groove to the substrate away from the substrate is less than the second distance from the surface of the first organic insulating sublayer located in the main display area to the substrate away from the substrate, so as to reduce the interface reflection, interference and other effects in the portion of the pixel driving circuit layer corresponding to the light-transmitting display area, which is beneficial to improving the transmittance of the light-transmitting display area and improving the problem of low transmittance of the light-transmitting display area when the light-transmitting display area and the main display area are designed with the same pixel density. By providing a second organic insulating sublayer on the first organic insulating sublayer, a better flatness foundation is provided for the second pixel. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] FIG1 is a schematic structural diagram of a main display area and a light-transmitting display area provided in an embodiment of the present application;

[0019] 2A to 2D are schematic structural diagrams of a display panel provided in an embodiment of the present application;

[0020] FIG3 is a schematic structural diagram of the boundary of the opening and the boundary of the groove provided in an embodiment of the present application. Modes for Carrying Out the Invention

[0021] To make the purpose, technical solutions and effects of this application clearer and more specific, the following further describes this application in detail with reference to the accompanying drawings and examples. It should be understood that the specific examples described herein are only used to explain this application and are not intended to limit this application.

[0022] Specifically, Figure 1 is a structural schematic diagram of the main display area and the translucent display area provided in an embodiment of the present application; an embodiment of the present application provides a display panel, the display panel including a translucent display area 100a and a main display area 100b adjacent to the translucent display area 100a, the transmittance of the translucent display area 100a being greater than the transmittance of the main display area 100b.

[0023] Optionally, the main display area 100b is located outside the light-transmitting display area 100a. Optionally, the main display area 100b is configured to implement the display function of the display panel, and the light-transmitting display area 100a is configured to implement a sensing function while implementing the display function of the display panel. Optionally, the sensing function implemented by the light-transmitting display area 100a includes sensing light to implement imaging, fingerprint recognition, and other functions.

[0024] Optionally, the display panel includes a light sensing device disposed corresponding to the light-transmitting display area 100a. Optionally, the light sensing device includes a camera, a light sensor, etc.

[0025] Optionally, the main display area 100b includes a transition display area 100c, which is located outside the light-transmitting display area 100a. Optionally, the transition display area 100c is configured to implement the display function of the display panel.

[0026] 2A to 2D are schematic structural diagrams of a display panel provided in an embodiment of the present application.

[0027] The display panel includes a substrate 100 , a pixel driving circuit layer 200 , an organic insulating layer 300 and a light emitting layer 400 .

[0028] Optionally, the substrate 100 includes a base 101 and a barrier layer 102 located on the base 101 .

[0029] Optionally, the substrate 101 may be made of a flexible substrate and a rigid substrate. Optionally, the substrate 101 may be formed as a single layer or may be formed into multiple layers by repeated stacking through processes such as coating and curing. Optionally, the flexible substrate may include polyimide or the like. Optionally, the substrate 101 may be formed as a flexible substrate by coating a polymeric material (such as polyimide) on a supporting substrate and curing the polymeric material. Optionally, the supporting substrate may include glass, metal, ceramic, or the like, and the polymeric material may be coated on the supporting substrate through coating processes such as spin coating, slit coating, and inkjet coating. The supporting substrate may be removed in subsequent processes. Optionally, the rigid substrate may include glass, ceramic, or the like.

[0030] Optionally, the barrier layer 102 can be made of various insulating materials (e.g., silicon oxide or silicon nitride). Optionally, the barrier layer 102 can be a single layer or a multilayer structure. The barrier layer 102 can be configured to block or prevent impurities and moisture from penetrating from the substrate 101 into the light-emitting layer 400.

[0031] Optionally, the barrier layer 102 includes a first barrier layer and a second barrier layer, wherein the second barrier layer is located between the first barrier layer and the substrate. The first barrier layer may be formed of SiOx or SiON, and the second barrier layer may be formed of SiNx or SiON.

[0032] The pixel driving circuit layer 200 is located on the substrate 100 and includes a plurality of stacked inorganic insulating layers and a plurality of pixel driving circuits PDE disposed in the main display area 100 b.

[0033] Optionally, the pixel driving circuit PDE that drives the second pixel Pix located in the translucent display area 100a to emit light may be located in the transition display area 100c, and the pixel driving circuit PDE that drives the first pixel located in the main display area 100b to emit light may be located correspondingly in the main display area 100b, so as to reduce the interference of the pixel driving circuit PDE on the transmittance of the translucent display area 100a.

[0034] The pixel driving circuit layer 200 includes a plurality of first grooves H1 disposed in the light-transmitting display area 100 a and located between the second pixels Pix, and the first grooves H1 adjacent to different second pixels Pix are connected to each other.

[0035] Optionally, the first groove H1 exposes the barrier layer 102 , so that the barrier layer 102 blocks or prevents impurities and moisture from penetrating from the substrate 101 into the light-emitting layer 400 .

[0036] Optionally, the pixel driving circuit layer 200 includes a buffer layer 201 , a first gate insulating layer 202 and an interlayer dielectric layer 203 .

[0037] The buffer layer 201 is located on the substrate 100 and can block or prevent impurities and moisture from penetrating from the substrate 100 into the light-emitting layer 400. Optionally, the buffer layer 201 can be a single-layer or multi-layer structure, and the buffer layer 201 can be made of materials such as silicon oxide or silicon nitride.

[0038] The first gate insulating layer 202 is located on the buffer layer 201 . The first gate insulating layer 202 may be a single-layer or multi-layer structure. The material of the first gate insulating layer 202 includes at least one of silicon nitride, silicon oxide, and the like.

[0039] The interlayer dielectric layer 203 is located on the first gate insulating layer 202 . The interlayer dielectric layer 203 may be a single-layer or multi-layer structure. The material of the interlayer dielectric layer 203 includes at least one of silicon nitride, silicon oxide, and the like.

[0040] Optionally, the buffer layer 201 , the first gate insulating layer 202 , and the interlayer dielectric layer 203 are provided with the first grooves H1 that are interconnected at least in portions not corresponding to the second pixels Pix.

[0041] Optionally, the pixel driving circuit layer 200 further includes a second gate insulating layer 204, which is located on the first gate insulating layer 202, and the interlayer dielectric layer 203 is located on the second gate insulating layer 204. The second gate insulating layer 204 can be a single-layer or multi-layer structure, and the material of the second gate insulating layer 204 includes at least one of silicon nitride and silicon oxide.

[0042] Optionally, a plurality of first grooves H1 are formed in the buffer layer 201 , the first gate insulating layer 202 , the second gate insulating layer 204 and the interlayer dielectric layer 203 .

[0043] Optionally, the pixel driving circuit layer 200 further includes an active layer 205 , a first gate layer 206 and a source-drain layer 207 .

[0044] The active layer 205 is located between the buffer layer 201 and the first gate insulating layer 202. Optionally, the active layer 205 includes a silicon semiconductor material, an oxide semiconductor material, etc. Optionally, the silicon semiconductor material includes a polysilicon material.

[0045] The first gate layer 206 is located between the first gate insulating layer 202 and the second gate insulating layer 204. The first gate layer 206 includes a gate electrode provided corresponding to the channel region of the active layer 205. Optionally, the first gate layer 206 may have a single-layer or multi-layer structure. The material of the first gate layer 206 includes Al, Ti, Mo, Cu, Ni, or alloys thereof, or a material with high corrosion resistance.

[0046] The source / drain electrode layer 207 is located on the interlayer dielectric layer 203. The source / drain electrode layer 207 includes a source electrode and a drain electrode electrically connected to the source region and the drain region of the active layer 205, respectively. Optionally, the source / drain electrode layer 207 may have a single-layer or multi-layer structure. The material of the source / drain electrode layer 207 includes at least one of Al, Ti, Mo, Cu, Ni, or alloys thereof, or a material with high corrosion resistance.

[0047] The gate, the source, and the drain respectively form a control electrode, an input electrode, and an output electrode of a transistor. The gate, the source, the drain, and the active layer 205 form a transistor in the pixel driving circuit PDE.

[0048] Optionally, the first gate layer 206 further includes scan lines, etc., and the source / drain layer 207 further includes data lines, etc. The scan lines and the data lines are electrically connected to the pixel driving circuit PDE, so that the pixel driving circuit PDE drives the corresponding light-emitting device to emit light according to the scan signals transmitted by the scan lines and the data signals transmitted by the data lines. The light-emitting device is the first pixel or the second pixel.

[0049] Optionally, the display panel further includes a second gate layer 208 and a signal connection layer 310 .

[0050] The second gate layer 208 is positioned between the second gate insulating layer 204 and the interlayer dielectric layer 203. The second gate layer 208 includes a plate portion corresponding to the gate, so that the gate and the plate portion form two electrodes of a capacitor. Optionally, the second gate layer 208 can have a single-layer or multi-layer structure. The material of the second gate layer 208 includes at least one of Al, Ti, Mo, Cu, Ni, or alloys thereof, or a material with high corrosion resistance.

[0051] The signal connection layer 310 is located on the source-drain layer 207. The signal connection layer 310 includes a plurality of signal connection portions, and the plurality of signal connection portions are electrically connected to corresponding transistors. Optionally, the material for preparing the signal connection layer 310 includes at least one of Al, Ti, Mo, Cu, Ni, or their alloys, or a material with high anti-corrosion performance, etc. Optionally, the material for preparing the signal connection layer 310 includes a transparent conductive material to reduce the influence of the signal connection layer 310 on the light transmittance of the light-transmissive display area 100a.

[0052] Please continue to refer to FIGS. 2A to 2D. The organic insulating layer 300 is located on the pixel driving circuit layer 200. The organic insulating layer 300 includes a first organic insulator layer 301 and a second organic insulator layer 302 located on the first organic insulator layer 301. Among them, the first organic insulator layer 301 fills the first groove H1.

[0053] Optionally, the first distance L1 from the surface of the first organic insulator layer 301 at the first groove H1 away from the substrate 100 to the substrate 100 is less than the second distance L2 from the surface of the first organic insulator layer 301 in the main display area 100b away from the substrate 100 to the substrate 100 (i.e., L1 < L2), so that the top surface of the portion of the first organic insulator layer 301 corresponding to the first groove H1 is lower than the top surface of the portion of the first organic insulator layer 301 corresponding to the main display area 100b. Optionally, the top surface of the portion of the second organic insulator layer 302 corresponding to the first groove H1 is flush with the top surface of the portion of the second organic insulator layer 302 corresponding to the main display area 100b, so as to provide a better flatness basis for the second pixel Pix included in the light-emitting layer 400.

[0054] Continuing with Figures 2A to 2D , the light-emitting layer 400 is located on the organic insulating layer 300. The light-emitting layer 400 includes a plurality of first pixels located within the main display area 100b and a plurality of second pixels Pix located within the light-transmitting display area 100a. The first pixels and the second pixels Pix are electrically connected to the corresponding pixel driving circuits PDE. By electrically connecting the plurality of second pixels Pix to the pixel driving circuits PDE located within the main display area 100b, the entire light-transmitting display area 100a is free of the pixel driving circuits PDE. This improves the transmittance of the light-transmitting display area 100a, and the inorganic insulating layers corresponding to the entire light-transmitting display area 100a (i.e., the buffer layer 201, the first gate insulating layer 202, the second gate insulating layer 204, and the interlayer dielectric layer 203) can be removed to form a first recess H1. By providing an organic insulating layer 300 in the first groove H1, the interface reflection, interference, and other effects that occur in the portion of the buffer layer 201, the gate insulating layer, and the interlayer dielectric layer 203 included in the pixel driving circuit layer 200 corresponding to the transparent display area 100a are reduced. This is beneficial for improving the transmittance of the transparent display area 100a and improving the problem of low transmittance of the transparent display area 100a when the transparent display area 100a and the main display area 100b are designed with the same pixel density.

[0055] Optionally, to ensure that the first organic insulating sublayer 301 has good light transmittance, the refractive index of the first organic insulating sublayer 301 may be less than or equal to 1.6, and the extinction coefficient may be approximately 0. Optionally, the refractive index of the first organic insulating sublayer 301 may be equal to 1.6, 1.5, 1.4, 1.3, 1.2, 1.1, 1, etc.

[0056] Optionally, within a unit area, the density of the second pixels Pix located in the light-transmitting display area 100 a and the density of the first pixels located in the main display area 100 b are the same.

[0057] Optionally, the second pixel Pix and the first pixel include organic light emitting diodes, sub-millimeter light emitting diodes, micro light emitting diodes, etc.

[0058] Optionally, the light emitting layer 400 is electrically connected to the corresponding pixel driving circuit PDE through the signal connection layer 310 .

[0059] Optionally, the signal connection layer 310 includes a first connection layer 311, which is located on the first organic insulating sublayer 301. The first connection layer 311 includes a plurality of first connection parts, and each of the first connection parts is electrically connected to the corresponding pixel driving circuit PDE through a via hole passing through the first organic insulating sublayer 301.

[0060] Optionally, the signal connection layer 310 further includes a second connection layer 312 , and the second connection layer 312 is electrically connected between the second pixel Pix or the first pixel and the first connection layer 311 .

[0061] Optionally, the first connecting layer 311 is located between the first organic insulating sublayer 301 and the second organic insulating sublayer 302, the second connecting layer 312 is located on the second organic insulating sublayer 302, and the second connecting layer 312 includes a plurality of second connecting portions, each of the second connecting portions being electrically connected to the corresponding first connecting portion through a via hole passing through the second organic insulating sublayer 302.

[0062] Optionally, to reduce the step difference on the surface of the second organic insulating sublayer 302 and ensure better surface flatness, the second organic insulating sublayer 302 is prepared using a double coating process. This reduces the probability of breakage or short circuits in the wiring on the second organic insulating sublayer 302 and provides better flatness for the first electrode layer 401 in the light-emitting layer 400. The first electrode layer 401 can be an anode layer or a cathode layer.

[0063] Optionally, the signal connection layer 310 further includes a third connection layer 313 , and the third connection layer 313 is electrically connected between the second pixel Pix or the first pixel and the second connection layer 312 .

[0064] Optionally, the organic insulating layer 300 also includes a third organic insulating sublayer 303, wherein the third organic insulating sublayer 303 is located on the second organic insulating sublayer 302, the second connecting layer 312 is located between the second organic insulating sublayer 302 and the third organic insulating sublayer 303, and the third connecting layer 313 is located on the third organic insulating sublayer 303. The third connecting layer 313 includes a plurality of third connecting portions, and each of the third connecting portions is electrically connected to the corresponding third connecting portion through a via hole passing through the third organic insulating sublayer 303.

[0065] Optionally, the preparation material of the third organic insulating sublayer 303 includes silicon oxide to prevent the gas in the second organic insulating sublayer 302, the first organic insulating sublayer 301, the blocking layer 102 and the substrate 101 located under the third organic insulating sublayer 303 from being released into the light-emitting layer 400.

[0066] Optionally, multiple first connection portions are located within the transition display area 100c to avoid problems such as breakage of multiple first connection portions due to the step difference of the first organic insulating sublayer 301 corresponding to the first groove H1, thereby reducing the probability of electrical connection failure between the second pixel Pix located in the transparent display area 100a and the corresponding pixel driving circuit PDE, which in turn causes display failure of the display panel.

[0067] Optionally, multiple second connection portions are located in the transition display area 100c, or multiple second connection portions extend from the transition display area 100c to the transparent display area 100a, so as to achieve electrical connection between the second pixel Pix located in the transparent display area 100a and the corresponding pixel driving circuit PDE.

[0068] Optionally, multiple third connection portions are located in the transparent display area 100a, or multiple third connection portions extend from the transition display area 100c to the transparent display area 100a, so as to achieve electrical connection between the second pixel Pix located in the transparent display area 100a and the corresponding pixel driving circuit PDE.

[0069] Optionally, the organic insulating layer 300 further includes a fourth organic insulating sublayer 304, which is located on the third organic insulating sublayer 303 and the third connecting layer 313. The first electrode layer 401 of the light-emitting layer 400 includes a plurality of first electrodes, each of which is electrically connected to a corresponding signal connection portion via a via hole penetrating the fourth organic insulating sublayer 304. The first electrode is an anode or cathode of the second pixel Pix or the first pixel.

[0070] Optionally, the first electrode layer 401 is an anode layer, and the first electrode is an anode.

[0071] 2A and 2B , the pixel driving circuit layer 200 further includes a plurality of second grooves H2 disposed in the light-transmitting display area 100 a and corresponding to the second pixels Pix. The second grooves H2 are connected to the adjacent first grooves H1 .

[0072] Optionally, a fourth distance between the first organic insulating sublayer 301 located at the second groove H2 and the surface of the substrate 100 is equal to the first distance L1 between the first organic insulating sublayer 301 located at the first groove H1 and the surface of the substrate 100, so that the portion of the first organic insulating sublayer 301 corresponding to the second pixel Pix is ​​flush with the portion between the corresponding second pixels Pix.

[0073] Optionally, the depth of the first groove H1 is equal to the depth of the second groove H2, so that the first groove H1 and the second groove H2 are prepared synchronously.

[0074] Alternatively, referring to Figures 2C to 2D , the light-transmitting display area 100a includes multiple display sub-areas 1001a and light-transmitting sub-areas 1001b located between the multiple display sub-areas 1001a. The multiple second pixels Pix are located correspondingly in the multiple display sub-areas 1001a, and the first grooves H1 are provided correspondingly to the light-transmitting sub-areas 1001b.

[0075] The pixel driving circuit layer 200 further includes a plurality of protrusions BP disposed in the light-transmitting display area 100a and corresponding to the second pixels Pix, and the first grooves H1 are disposed around the protrusions BP. A third distance L3 between the first organic insulating sublayer 301 located on the protrusions BP and the surface of the substrate 100 is greater than the first distance L1 between the first organic insulating sublayer 301 located on the first grooves H1 and the surface of the substrate 100, and is less than or equal to the second distance L2 (i.e., L1) between the first organic insulating sublayer 301 located in the main display area 100b and the surface of the substrate 100. <L3≤L2)。

[0076] Optionally, the raised portion BP includes a first sub-raised portion and a second sub-raised portion. The buffer layer 201 and the first gate insulating layer 202 are provided with the first sub-raised portion corresponding to the display sub-area 1001a, and the second gate insulating layer 204 and the interlayer dielectric layer 203 are provided with the second sub-raised portion corresponding to the display sub-area 1001a. The orthographic projection of the first sub-raised portion on the substrate 100 has an eighth boundary (e.g., d6 in Figures 2C and 2D is the dimension defined by the eighth boundary), and the orthographic projection of the second sub-raised portion on the substrate 100 has a ninth boundary (e.g., d7 in Figures 2C and 2D is the dimension defined by the ninth boundary). The ninth boundary is located within the eighth boundary, so that the raised portion BP provides better support and flatness for the second pixel Pix.

[0077] Optionally, each of the second pixels Pix includes a first electrode located on the organic insulating layer 300. The orthographic projection of the first electrode on the substrate 100 has a tenth boundary (e.g., d8 in Figures 2C and 2D is the dimension defined by the tenth boundary), and the orthographic projection of the protrusion BP on the substrate 100 is located within the orthographic projection of the first electrode on the substrate 100, thereby reducing the impact of the pixel driving circuit layer 200 on the transmittance of the light-transmitting display area 100a. The orthographic projection of the protrusion BP on the substrate 100 being located within the orthographic projection of the first electrode on the substrate 100 includes the tenth boundary overlapping the eighth boundary, or the tenth boundary being located outside the eighth boundary.

[0078] 2A to 2B , the pixel driving circuit layer 200 is provided with the first groove H1 only in the area corresponding to the light-transmitting sub-area 1001b, so that the size of the first groove H1 is smaller. When the first organic insulating sub-layer 301 fills the first groove H1, the step difference between the top surface of the first organic insulating sub-layer 301 corresponding to the first groove H1 and the top surface of the first organic insulating sub-layer 301 corresponding to the main display area 100b and the transition display area 100c is smaller (as shown by d5 in FIG. 2C to 2D ), which is beneficial to improving the flatness of the surface of the second organic insulating sub-layer 302, thereby minimizing the probability of broken wires in the signal connection layer 310, and is beneficial to improving the flatness of the first electrode located in the light-transmitting display area 100a.

[0079] Continuing with Figures 2A to 2D , since the first distance L1 is less than the second distance L2, the first organic insulating sublayer 301 includes a third groove H3 disposed in the light-transmissive display area 100a and corresponding to the first groove H1. Optionally, the width of the third groove H3 is less than or equal to the width of the first groove H1. This ensures that, after the first organic insulating sublayer 301 fills the first groove H1, the organic insulating sublayer located above the first organic insulating sublayer 301 has better flatness (i.e., by increasing the number of film layers that need to be flattened (e.g., the first flattening layer 201, including the third groove H3, also needs to be flattened), a relatively flat surface is achieved after multiple flattening steps).

[0080] Optionally, Figure 3 is a schematic structural diagram of the boundaries of the first and third grooves provided in an embodiment of the present application. The projected width of the sidewalls of the third groove H3 on the substrate 100 is less than or equal to the projected width of the sidewalls of the first groove H1 on the substrate 100. Optionally, the projected width of the sidewalls of the third groove H3 on the substrate 100 is equal to the projected width of the sidewalls of the first groove H1 on the substrate 100, thereby reducing the probability of light dispersion problems occurring at the intersection of the third groove H3 and the first groove H1.

[0081] Optionally, the orthographic projection of the side wall of the third groove H3 on the substrate 100 has a first boundary B1, and the orthographic projection of the side wall of the first groove H1 on the substrate 100 has a second boundary B2, and the first boundary B1 overlaps with the second boundary B2 to reduce the probability of light dispersion problems occurring at the intersection of the third groove H3 and the first groove H1.

[0082] It is understood that, in existing manufacturing methods, due to limitations such as process precision and process technology, the first boundary B1 and the second boundary B2 may not be completely overlapped during manufacturing. Therefore, the overlap between the first boundary B1 and the second boundary B2 referred to in this application should also include the situation where a spacing error exists between the first boundary B1 and the second boundary B2 due to factors such as process precision and process technology.

[0083] Alternatively, referring to Figures 2A to 2D , the first groove H1 includes a plurality of stacked and interconnected sub-grooves in the thickness direction of the display panel. A greater number of sub-grooves facilitates a flatter surface for the first organic insulating sub-layer 301. However, a greater number of sub-grooves also increases the number of step surfaces formed between the sub-grooves. The greater the number of step surfaces, the greater the probability of light scattering on the step surfaces. Therefore, to achieve a balance between flatness and optical performance, the number of step surfaces Sm between at least two adjacent sub-grooves in the thickness direction of the display panel is set to be less than or equal to 2, so that the display panel achieves both flatness and optical performance.

[0084] Optionally, the number of the step surfaces Sm may be 0, 1 or 2.

[0085] Optionally, when the number of the step surfaces Sm is 0, the sizes of the plurality of sub-grooves may gradually increase or remain unchanged in the direction from the buffer layer 201 to the interlayer dielectric layer 203 .

[0086] Optionally, please continue to refer to Figures 2A to 2D. The buffer layer 201 and the first gate insulating layer 202 are provided with a first sub-groove H11 corresponding to the light-transmitting display area 100a (that is, the side walls of the buffer layer 201 and the side walls of the first gate insulating layer 202 corresponding to the light-transmitting display area 100a are surrounded to form the first sub-groove H11), and the second gate insulating layer 204 and the interlayer dielectric layer 203 are provided with a second sub-groove H12 corresponding to the light-transmitting display area 100a (that is, the side walls of the second gate insulating layer 204 and the side walls of the interlayer dielectric layer 203 corresponding to the light-transmitting display area 100a are surrounded to form the second sub-groove H12). The width of the first sub-groove H11 is smaller than the width of the second sub-groove H12, so that the orthographic projection of the first sub-groove H11 on the substrate 100 is located within the orthographic projection of the second sub-groove H12 on the substrate 100, so that the number of the step surfaces Sm is 1 or 0, thereby taking into account both flatness and optical performance.

[0087] Optionally, in the display panel shown in FIG. 2A to FIG. 2B , when top surfaces of the plurality of first grooves H1 and the plurality of second grooves H2 are flush, the plurality of first grooves H1 and the plurality of second grooves H2 may have a common boundary (as shown by Bc in FIG. 3 ).

[0088] 2C to 2D , when the display panel does not include the second groove H2 , each first groove H1 may have a first boundary B1 . Accordingly, each first groove H1 may include the first sub-groove H11 and the second sub-groove H12 .

[0089] Optionally, referring to FIG3 , the orthographic projection of the second sub-recess H12 on the substrate 100 has a second boundary B2 and a third boundary B3, the orthographic projection of the bottom surface of the third recess H3 on the substrate 100 has a fourth boundary B4, and the orthographic projection of the first sub-recess H11 on the substrate 100 has a fifth boundary B5 and a sixth boundary B6. In the display panel shown in FIG2A and FIG2B , the fourth boundary B4 is located within boundary Bc, the third boundary B3 is located within boundary Bc, the fifth boundary B5 is located within boundary Bc, and the sixth boundary B6 is located within the fifth boundary B5. The fourth boundary B4 and the sixth boundary B6 overlap, thereby reducing the probability of light scattering problems occurring at the intersection of the first sub-recess H11, the second sub-recess H12, and the third recess H3. In the display panel shown in Figures 2C to 2D, the fourth boundary B4 is located within the first boundary B1, the third boundary B3 is located within the second boundary B2, the fifth boundary B5 is located within the second boundary B2, and the sixth boundary B6 is located within the fifth boundary B5. The fourth boundary B4 and the sixth boundary B6 overlap to reduce the probability of light scattering problems occurring at the intersection of the first sub-groove H11, the second sub-groove H12 and the third groove H3.

[0090] Optionally, a first distance d1 is defined between the second boundary B2 or boundary Bc and the third boundary B3, a second distance d2 is defined between the third boundary B3 and the fifth boundary B5, and a third distance d3 is defined between the fifth boundary B5 and the sixth boundary B6. A distance d4 between the first boundary B1 and the fourth boundary B4 is equal to the sum of the first distance d1, the second distance d2, and the third distance d3 (i.e., d4 = d1 + d2 + d3).

[0091] Optionally, the second distance d2 is less than or equal to 0.3 micrometers, and the third distance d3 is less than or equal to 0.8 micrometers, so as to reduce scattering of light at the side surfaces of the first sub-groove H11 and the second sub-groove H12.

[0092] Optionally, the second distance d2 is equal to 0.3 μm, 0.25 μm, 0.21 μm, 0.2 μm, 0.18 μm, 0.15 μm, 0.1 μm, 0.05 μm or 0 μm. Optionally, the third distance d3 is equal to 0.8 μm, 0.75 μm, 0.7 μm, 0.65 μm, 0.6 μm, 0.55 μm, 0.5 μm, 0.45 μm, 0.4 μm, 0.35 μm, 0.3 μm, 0.25 μm, 0.2 μm, 0.15 μm, 0.1 μm or 0 μm.

[0093] It is understood that, in existing manufacturing methods, due to limitations such as process precision and process technology, the fourth boundary B4 and the sixth boundary B6 may not be completely overlapped during manufacturing. Therefore, the overlap of the fourth boundary B4 and the sixth boundary B6 referred to in this application should also include the situation where a spacing error exists between the fourth boundary B4 and the sixth boundary B6 due to factors such as process precision and process technology.

[0094] Alternatively, in the display panel shown in Figures 2A and 2B, the fifth boundary B5 may coincide with the boundary of the light-transmitting display area 100a, or the sixth boundary B6 may coincide with the boundary of the light-transmitting display area 100a, to ensure that the transmittance of the entire light-transmitting display area 100a is improved. Alternatively, the first boundary B1, boundary Bc, and the third boundary B3 are located within the transitional display area 100c to reduce the impact of the first boundary B1, boundary Bc, and the third boundary B3 on the transmittance of the light-transmitting display area 100a.

[0095] Optionally, referring to Figures 2A to 2D , the included angle α between the bottom surface of the second sub-recess H12 and the sidewall of the second sub-recess is less than or equal to 115° (i.e., the step surface Sm is provided between the first sub-recess H11 and the second sub-recess H12, and the step surface Sm and the sidewall of the second sub-first recess H12 have an included angle α, and the supplementary angle of the included angle α is greater than or equal to 65°). This reduces the side length of the second sub-recess H12, thereby reducing light scattering at the side of the second sub-recess H12.

[0096] Optionally, the complementary angle of the angle α is equal to 65°, 66°, 67°, 68°, 69°, 70°, 71°, 72°, 73°, 74°, 75°, 76°, 77°, 78°, 79°, 80°, 81°, 82°, 83°, 84°, 85°, 86°, 87°, 88°, 89°, or 90°.

[0097] Optionally, the angle between the bottom surface of the first sub-groove H11 and the side wall of the first sub-groove H11 is less than or equal to 115°, so that the side length of the first sub-groove H11 is shorter, thereby reducing the scattering of light at the side of the first sub-groove H11.

[0098] Optionally, referring to Figures 2B and 2D , the display panel further includes a light shielding layer 103, which is located below the pixel driving circuit layer 200. The light shielding layer 103 has an opening corresponding to the first groove H1, and the width of the opening is greater than or equal to the width of the first sub-groove H11.

[0099] Optionally, the orthographic projection of the opening on the substrate 100 has a seventh boundary, and the seventh boundary is located between the sixth boundary B6 and the fifth boundary B5, so as to protect the active layer 205 from being exposed to light while ensuring that the transmittance of the light-transmitting display area 100a is not affected by the shading layer.

[0100] Optionally, referring to Figures 2A to 2D , the light-emitting layer 400 further includes a light-emitting material layer 402 and a second electrode layer 403. The display panel includes, among other things, a pixel definition layer 404 and an encapsulation layer 500. The pixel definition layer 404 is located on the first electrode layer 401 and has a pixel definition region corresponding to the first electrode. The light-emitting material layer 402 is located within the pixel definition region. The second electrode layer 403 is located on the light-emitting material layer 402. The encapsulation layer 500 is located on the second electrode layer 403.

[0101] The inventors of this application have provided the pixel drive circuit layer 200 with a first groove H1 corresponding to the translucent display area 100a, and after filling the first groove H1 with a highly transparent organic material, they have verified that the transmittance of the display panel can be increased by approximately 15% (i.e., the transmittance of the display panel has been increased from the original 63% to 78%). This verification was conducted using a camera as a light sensing element, and the results showed that in dark environments, the camera provided corresponding to the translucent display area 100a can produce clearer and more detailed images. Therefore, this application can improve the transmittance of the translucent display area 100a and optimize the imaging effect.

[0102] The present application also provides a display device comprising any of the aforementioned display panels. It is understood that the display device includes a mobile display device (such as a laptop computer, mobile phone, etc.), a fixed terminal (such as a desktop computer, television, etc.), a measuring device (such as a sports bracelet, thermometer, etc.), etc.

[0103] This document uses specific examples to illustrate the principles and implementation methods of this application. The description of the above embodiments is only used to help understand the method and core ideas of this application. At the same time, for technical personnel in this field, based on the ideas of this application, there will be changes in the specific implementation methods and application scope. In summary, the content of this specification should not be understood as limiting this application.

Claims

1. A display panel, wherein: The display panel comprises a light-transmitting display area and a main display area adjacent to the light-transmitting display area, wherein the light transmittance of the light-transmitting display area is greater than the light transmittance of the main display area, and the display panel comprises: substrate; A pixel driving circuit layer, located on the substrate, comprising a plurality of stacked inorganic insulating layers and a plurality of pixel driving circuits arranged in the main display area; an organic insulating layer, located on the pixel driving circuit layer, comprising a first organic insulating sublayer and a second organic insulating sublayer located on the first organic insulating sublayer; and a light-emitting layer, located on the organic insulating layer, comprising: a plurality of first pixels located in the main display area and a plurality of second pixels located in the light-transmitting display area, wherein the first pixels and the second pixels are electrically connected to the corresponding pixel driving circuit; Wherein, the pixel driving circuit layer includes: a plurality of first grooves arranged in the light-transmitting display area and located between the second pixels, the first grooves adjacent to different second pixels are connected to each other, the first organic insulating sublayer fills the first grooves, and a first distance from the surface of the first organic insulating sublayer located at the first groove to the substrate away from the substrate is smaller than a second distance from the surface of the substrate to the substrate of the first organic insulating sublayer located in the main display area away from the substrate.

2. The display panel according to claim 1, wherein: The pixel driving circuit layer further includes: A plurality of raised portions are arranged in the light-transmitting display area and corresponding to the second pixels, the first grooves are arranged around the raised portions, and a third distance from the first organic insulating sublayer located on the raised portions to the substrate away from the surface of the substrate is greater than the first distance from the first organic insulating sublayer located on the first groove to the substrate away from the surface of the substrate, and is less than the second distance from the first organic insulating sublayer located in the main display area to the substrate away from the surface of the substrate.

3. The display panel according to claim 1, wherein: The pixel driving circuit layer further includes: A plurality of second grooves are arranged in the light-transmitting display area and corresponding to the second pixels, and the second grooves are connected to the adjacent first grooves.

4. The display panel according to claim 3, wherein: A fourth distance from the surface of the substrate away from the first organic insulating sublayer located at the second groove to the substrate is equal to the first distance from the surface of the substrate away from the first organic insulating sublayer located at the first groove to the substrate.

5. The display panel according to claim 3, wherein: The depth of the first groove is equal to the depth of the second groove.

6. The display panel according to claim 1, wherein: The first organic insulating sublayer includes a third groove disposed in the light-transmitting display area and corresponding to the first groove; Wherein, the width of the third groove is less than or equal to the width of the first groove.

7. The display panel according to claim 6, wherein: A projection width of a side wall of the third groove on the substrate is smaller than or equal to a projection width of a side wall of the first groove on the substrate.

8. The display panel according to claim 1, wherein: The first groove comprises a plurality of sub-grooves which are stacked and interconnected; The width of the sub-groove far from the substrate is greater than the width of the sub-groove close to the substrate.

9. The display panel according to claim 8, wherein: The plurality of sub-grooves include a first sub-groove and a second sub-groove; the pixel driving circuit layer includes: a buffer layer, located on the substrate; a first gate insulating layer, located on the buffer layer; a second gate insulating layer, located on the first gate insulating layer; and an interlayer dielectric layer, located on the second gate insulating layer; The buffer layer and the first gate insulating layer include the first sub-groove, the second gate insulating layer and the interlayer dielectric layer include the second sub-groove, and the width of the first sub-groove is smaller than the width of the second sub-groove.

10. The display panel according to claim 9, wherein: An angle between a bottom surface of the second sub-groove and a side wall of the second sub-groove is less than or equal to 115°.

11. The display panel according to claim 9, wherein: Also includes: The light shielding layer is located under the pixel driving circuit layer, and the light shielding layer is provided with an opening corresponding to the first groove, and the width of the opening is greater than or equal to the width of the first sub-groove.

12. The display panel according to claim 1, wherein: The substrate includes a base and a barrier layer located on the base.

13. A display device, wherein: A display panel is provided, wherein the display panel comprises a light-transmitting display area and a main display area adjacent to the light-transmitting display area, the light transmittance of the light-transmitting display area is greater than the light transmittance of the main display area, and the display panel comprises: substrate; A pixel driving circuit layer, located on the substrate, comprising a plurality of stacked inorganic insulating layers and a plurality of pixel driving circuits arranged in the main display area; an organic insulating layer, located on the pixel driving circuit layer, comprising a first organic insulating sublayer and a second organic insulating sublayer located on the first organic insulating sublayer; and a light-emitting layer, located on the organic insulating layer, comprising: a plurality of first pixels located in the main display area and a plurality of second pixels located in the light-transmitting display area, wherein the first pixels and the second pixels are electrically connected to the corresponding pixel driving circuit; Wherein, the pixel driving circuit layer includes: a plurality of first grooves arranged in the light-transmitting display area and located between the second pixels, the first grooves adjacent to different second pixels are connected to each other, the first organic insulating sublayer fills the first grooves, and a first distance from the surface of the first organic insulating sublayer located at the first groove to the substrate away from the substrate is smaller than a second distance from the surface of the substrate to the substrate of the first organic insulating sublayer located in the main display area away from the substrate.

14. The display device according to claim 13, characterized in that: The pixel driving circuit layer also includes: A plurality of raised portions are arranged in the light-transmitting display area and corresponding to the second pixels, the first grooves are arranged around the raised portions, and a third distance from the first organic insulating sublayer located on the raised portions to the substrate away from the surface of the substrate is greater than the first distance from the first organic insulating sublayer located on the first groove to the substrate away from the surface of the substrate, and is less than the second distance from the first organic insulating sublayer located in the main display area to the substrate away from the surface of the substrate.

15. The display device according to claim 13, wherein: The pixel driving circuit layer also includes: A plurality of second grooves are arranged in the light-transmitting display area and corresponding to the second pixels, and the second grooves are connected to the adjacent first grooves.

16. The display device according to claim 15, wherein: A fourth distance from the surface of the substrate away from the first organic insulating sublayer located at the second groove to the substrate is equal to the first distance from the surface of the substrate away from the first organic insulating sublayer located at the first groove to the substrate.

17. The display device according to claim 13, wherein: The first organic insulating sublayer includes a third groove disposed in the light-transmitting display area and corresponding to the first groove; Wherein, the width of the third groove is less than or equal to the width of the first groove.

18. The display device according to claim 17, wherein: A projection width of a side wall of the third groove on the substrate is smaller than or equal to a projection width of a side wall of the first groove on the substrate.

19. The display device according to claim 13, wherein: The first groove comprises a plurality of sub-grooves which are stacked and interconnected; The width of the sub-groove far from the substrate is greater than the width of the sub-groove close to the substrate.

20. The display device according to claim 19, wherein: The plurality of sub-grooves include a first sub-groove and a second sub-groove, the width of the first sub-groove is smaller than the width of the second sub-groove, and the angle between the bottom surface of the second sub-groove and the side wall of the second sub-groove is less than or equal to 115°.

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