Interposer and forming method therefor

Abstract

Provided in the embodiments of the present disclosure are an interposer and a forming method therefor. The method comprises: providing a substrate; forming on the substrate a pattern transfer layer comprising a plurality of stitched pattern areas, wherein different pattern areas correspond to different photolithography templates, a stitching area of at least two pattern areas is an overlapping area, and any photolithography template comprises a pattern formed by an exposure area for exposure and a masking area for masking; preprocessing the pattern transfer layer, such that the plurality of pattern areas of the pattern transfer layer have different etching selection ratios in corresponding exposure areas and masking areas on the basis of patterns of the corresponding photolithography templates; etching the preprocessed pattern transfer layer, so as to form the patterns of the corresponding photolithography templates on the pattern transfer layer; and patterning the substrate by taking the pattern transfer layer as a mask. The embodiments of the present disclosure improve the device quality of the interposer.

Description

Adapter plate and forming method thereof

[0001] This application claims priority to Chinese Patent Application No. 202310712857.5 filed on June 15, 2023, and the contents of the above-mentioned Chinese patent application disclosure are hereby incorporated by reference in their entirety as a part of this application. Technical Field

[0002] Embodiments of the present disclosure relate to an adapter plate and a method for forming the same. Background Art

[0003] With the development of semiconductor technology, various packaging technologies have emerged, including 2.5D packaging (CoWoS, RDL, etc.) and 3D packaging (TSV). Furthermore, to achieve multifunctional electronic components, it is necessary to integrate chips with different functions together, and the COW (Chip-on-Wafer) stacking process is widely used. When packaging devices, the interposer, with its high fine-pitch wiring capabilities, can be used to stack chips and wafers.

[0004] However, the quality of the transfer plates formed by the commonly used transfer plate forming methods is not high.

[0005] Summary of the Invention

[0006] In view of this, embodiments of the present disclosure provide an adapter plate and a method for forming the same, which improve the device quality of the adapter plate.

[0007] To solve the above problems, an embodiment of the present disclosure provides a method for forming an adapter plate, comprising:

[0008] providing a substrate;

[0009] forming a pattern transfer layer on the substrate, the pattern transfer layer comprising a plurality of spliced ​​pattern areas, wherein different pattern areas correspond to different photolithography templates, and the spliced ​​area of ​​at least two pattern areas is an overlapping area; wherein any photolithography template comprises a pattern consisting of an exposed area for exposure and a masked area for masking;

[0010] Pre-processing the pattern transfer layer so that the plurality of pattern regions of the pattern transfer layer have different etching selectivities in corresponding exposed regions and masked regions based on the patterns of the corresponding photolithography template;

[0011] Etching the pre-treated pattern transfer layer to form a pattern corresponding to the photolithography template on the pattern transfer layer;

[0012] The substrate is patterned using the pattern transfer layer as a mask.

[0013] Optionally, the number of preprocessing times of the graphic transfer layer corresponds to the number of graphic areas of the graphic transfer layer;

[0014] For any graphic area, the pre-processing of the graphic transfer layer includes:

[0015] forming a patterned photolithography mask layer on the pattern transfer layer, wherein the pattern of the photolithography mask layer corresponds to the pattern of the photolithography template corresponding to the pattern area;

[0016] A pre-processing operation is performed on the pattern transfer layer using the photolithography mask layer as a mask.

[0017] Optionally, the pretreatment operation at least includes: using an ion implantation process to implant ions into the exposed area of ​​the graphic transfer layer.

[0018] Optionally, if the thickness of the pattern transfer layer is 30 nm, the ion implantation dose is E14 to E15.

[0019] Optionally, the material of the pattern transfer layer is amorphous silicon; forming the pattern transfer layer on the substrate comprises depositing an amorphous silicon layer on the substrate and using the amorphous silicon layer as the pattern transfer layer;

[0020] The ion implantation process is specifically to implant boron ions into the exposed amorphous silicon layer.

[0021] Optionally, for any graphic area, the pre-processing of the graphic transfer layer further includes: removing the photolithography mask layer.

[0022] Optionally, the etching of the pre-treated graphic transfer layer is specifically carried out by using a wet etching process to remove the transfer layer material corresponding to the masking area of ​​the graphic transfer layer corresponding to the photolithography template.

[0023] Optionally, the corresponding etching solution in the wet etching process includes a tetramethylammonium hydroxide solution.

[0024] Optionally, providing a substrate includes:

[0025] providing a substrate;

[0026] A hard mask material layer is formed on the substrate.

[0027] Optionally, the forming of the pattern transfer layer on the substrate is specifically forming the pattern transfer layer on the hard mask material layer;

[0028] The method of patterning the substrate by using the pattern transfer layer as a mask specifically involves patterning the hard mask material layer by using the pattern transfer layer as a mask to form a hard mask layer.

[0029] Optionally, after forming the hard mask layer, the method further includes:

[0030] depositing a conductive material on the hard mask layer to form a conductive interconnect layer;

[0031] The conductive interconnect layer is planarized to form a conductive interconnect structure.

[0032] The present disclosure also provides an adapter plate, which is prepared according to the above-mentioned method for forming an adapter plate. The adapter plate includes:

[0033] substrate;

[0034] A conductive interconnect structure located on a substrate comprises a plurality of spliced ​​graphic areas, wherein the spliced ​​areas of at least two graphic areas are overlapping areas.

[0035] Optionally, the conductive interconnect structure patterns corresponding to different pattern areas of the conductive interconnect structure are formed based on different photolithography templates; wherein any photolithography template includes a pattern consisting of an exposure area for exposure and a masking area for masking.

[0036] In the method for forming an adapter plate provided by an embodiment of the present disclosure, a graphic transfer layer is formed on a substrate, wherein the graphic transfer layer includes a plurality of spliced ​​graphic areas, different graphic areas correspond to different photolithography templates, and the spliced ​​area of ​​at least two graphic areas is an overlapping area; wherein any photolithography template includes a graphic composed of an exposed area for exposure and a masked area for masking; furthermore, the graphic transfer layer is pre-processed so that the plurality of graphic areas of the graphic transfer layer have different etching selectivities in the corresponding exposed area and masked area based on the graphic of the corresponding photolithography template; the pre-processed graphic transfer layer is etched to form a graphic corresponding to the photolithography template on the graphic transfer layer; and the substrate is patterned using the graphic transfer layer as a mask.

[0037] By pre-processing the pattern transfer layer on the substrate, the multiple pattern areas of the pattern transfer layer have different etching selectivities between the exposed and masked areas based on the corresponding pattern of the photolithography template. This allows for pattern transfer based on the etching process, ensuring the stability of the pattern on the pattern transfer layer and preventing pattern deformation. Furthermore, using the pattern transfer layer as a mask to pattern the substrate and form the integrated circuit pattern on the substrate, the accuracy of the integrated circuit pattern is improved, thereby increasing the accuracy of critical dimensions and enhancing the device quality of the interposer. BRIEF DESCRIPTION OF THE DRAWINGS

[0038] In order to more clearly illustrate the technical solutions in the embodiments of the present disclosure, the following briefly introduces the drawings required for use in the embodiments. Obviously, the drawings described below are merely embodiments of the present disclosure. For ordinary technicians in this field, other drawings can be obtained based on the provided drawings without any creative work.

[0039] FIG1 is a diagram of an integrated circuit formed by two photomasks;

[0040] Figure 2 is a graphical diagram of Mask-1;

[0041] Figure 3 is a graphical diagram of Mask-2;

[0042] 4 to 6 are schematic structural diagrams corresponding to the steps in a method for forming an adapter plate;

[0043] FIG7 is a top view of the state change of the connection hole pattern after two exposures; and

[0044] 8 to 26 are schematic structural diagrams corresponding to the steps in an embodiment of a method for forming an adapter plate provided in an embodiment of the present disclosure. DETAILED DESCRIPTION

[0045] The following will be combined with the accompanying drawings in the embodiments of the present disclosure to clearly and completely describe the technical solutions in the embodiments of the present disclosure. Obviously, the embodiments described are only part of the embodiments of the present disclosure, not all of the embodiments. Based on the embodiments of the present disclosure, all other embodiments obtained by ordinary technicians in this field without making any creative efforts are within the scope of protection of the present disclosure.

[0046] The quality of the adapter plate formed by the commonly used adapter plate forming method is not high. The reasons for the low quality of the adapter plate are analyzed based on the adapter plate forming method.

[0047] It should be noted that the pattern of the designed integrated circuit can be transferred to the adapter board through steps such as exposing the mask. However, since the size of the mask is fixed, for example, 26mm*33mm, and the adapter board used to integrate chips with different functions has a larger area, it is necessary to use multiple masks for exposure and splicing to photoetch the pattern of the integrated circuit onto the adapter board with a larger area. In addition, in order to ensure the accuracy and completeness of the pattern of the integrated circuit converted on the adapter board, the stitching area on the adapter board corresponding to the patterns of multiple masks can be the overlapping area of ​​the mask (Stitching Zone, ST).

[0048] Among them, Figure 1 exemplarily shows the pattern of an integrated circuit composed of two masks, and the two masks can be Mask-1 and Mask-2. Referring to Figure 1, the area enclosed by the dotted line is the overlapping area of ​​the two masks. In addition, in order to realize the conductive interconnection of the chip, it is necessary to set connection holes of different device structures. In an optional example, the connection hole pattern of the device structure can be set correspondingly in the overlapping area of ​​different masks. The connection hole can be a pattern composed of the exposed area after the mask is exposed, or it can be a pattern composed of the masked area after the mask is exposed. It can be set specifically according to actual needs. For example, in Figure 1, the circular pattern in the overlapping area corresponds to the pattern of the connection hole, and the circular pattern is a pattern composed of the masked area exposed by the mask.

[0049] Corresponding to Figure 1, Figure 2 is a schematic diagram of a mask Mask-1, and Figure 3 is a schematic diagram of another mask Mask-2, where line Aa is a cross-sectional tangent line of the mask. Based on the cross-section of line Aa, Figures 4 to 6 show the structural schematic diagrams corresponding to each step in the method for forming an adapter plate.

[0050] Corresponding to FIG2 , referring to FIG4 , exposure and development of Mask-1 are performed on the substrate 10 , wherein the dotted arrows indicate the illumination direction.

[0051] The substrate 10 is used to arrange electronic components and other components. In an optional example, the substrate 10 may include a substrate 11 and a hard mask material layer 12 located on the substrate. Before the mask is exposed, a photoresist needs to be coated on the substrate 10. The photoresist serves as a photoresist mask layer 13, and the pattern of Mask-1 is transferred to the photoresist mask layer 13. Photoresist is a photosensitive material that undergoes a chemical reaction after exposure, resulting in changes in its own properties and structure. For example, the exposed portion can change from a soluble substance to an insoluble substance. Then, during the etching step, the unexposed portion is removed to achieve the transfer of the mask pattern.

[0052] 3 , referring to FIG5 , exposure and development of Mask-2 are performed on the substrate 10 to transfer the pattern of Mask-2 onto the photolithography mask layer 13 , wherein the dotted arrows indicate the direction of light irradiation.

[0053] 6 , the substrate 10 is patterned using the photolithography mask layer 13 after double exposure and development as a mask.

[0054] In a specific example, an etching process may be performed using the photoresist mask layer 13 as a mask to etch away the hard mask material layer exposed by the photoresist mask layer to form a hard mask layer 12', thereby transferring the patterns of Mask-1 and Mask-2 to the hard mask layer 12', and then, subsequent preparation is performed based on the hard mask layer, such as metal deposition and planarization processes, to form a conductive connection structure and complete the production of the adapter board.

[0055] Among them, since Mask-1 and Mask-2 have overlapping areas, when Mask-1 and Mask-2 are exposed on the substrate 10, the overlapping areas will undergo two exposures. Corresponding to the connection hole pattern of the area circled by the thick circle in the overlapping area of ​​the mask in Figure 1, Figure 7 exemplarily shows a top view of the state change of the connection hole pattern after two exposures. As shown in Figure 7, when not exposed, the photolithography mask layer 13 does not undergo any changes; after the first exposure of the mask (Mask-1), the connection hole pattern (as shown by the dotted line in the figure) can be accurately presented; after the second exposure of the mask (Mask-2), the connection hole pattern changes significantly, and the connection hole pattern is stretched relative to the pattern after the first exposure (in the direction shown by the arrow in the figure). Therefore, in the subsequent step of forming the conductive interconnect structure, the deformed connection hole pattern will cause the critical dimensions of the connection hole to be distorted, reduce the quality of the adapter board device, and thus affect the device performance.

[0056] The reason for the reduced quality of the adapter board components in the above process is that the material of the photolithography mask layer 13 is photoresist, which is soft and undergoes a chemical reaction after exposure. After multiple exposures, the photoresist shrinks significantly, causing the pattern of the first exposure to deform. For example, the size of the connection hole pattern in Figure 7 increases due to the shrinkage of the photoresist. Moreover, because the shrinkage of the photoresist is based on its own changes during exposure, the shrinkage is uncontrollable, which also makes the changes in the connection hole pattern uncontrollable. For example, after multiple exposures, the connection hole pattern deforms from a circle to a square. In the subsequent preparation process, the critical dimensions are severely distorted, thereby reducing the quality of the adapter board components and affecting device performance.

[0057] In addition, after multiple exposures, the photoresist will become charred and hardened, making it difficult to remove and resulting in residue, which in turn reduces the product yield.

[0058] Therefore, it is particularly necessary to provide a method for forming an adapter plate to avoid pattern deformation during multiple masking, improve the accuracy of integrated circuit patterns, and further improve the accuracy of key dimensions and enhance the device quality of the adapter plate.

[0059] The disclosed embodiments provide an improved method for forming an interposer. By pre-processing a pattern transfer layer on a substrate, the pattern transfer layer's multiple pattern areas, based on the corresponding photolithography template pattern, have different etching selectivities between exposed and masked areas. This allows for pattern transfer based on the etching process, ensuring pattern stability on the pattern transfer layer and preventing pattern deformation. Furthermore, the pattern transfer layer is used as a mask to pattern the substrate and form integrated circuit patterns on the substrate, improving the accuracy of the integrated circuit pattern, thereby increasing the accuracy of critical dimensions and enhancing the device quality of the interposer.

[0060] In order to make the above-mentioned purposes, features and advantages of the embodiments of the present disclosure more obvious and easy to understand, the specific embodiments of the present disclosure are described in detail below with reference to the accompanying drawings.

[0061] 8 to 26 are schematic structural diagrams corresponding to the steps in the method for forming the adapter plate according to the embodiment of the present disclosure.

[0062] 8 , a substrate 100 is provided;

[0063] The substrate 100 is used to arrange electronic components and other components. In an optional example, the substrate may include a substrate and a hard mask material layer located on the substrate. Specifically, the steps of providing the substrate 100 may include:

[0064] 9 , a substrate 110 is provided;

[0065] The substrate 110 is used to provide a process foundation for forming the device layer structure. The material of the substrate 110 may be silicon. In other embodiments, the material of the substrate 110 may be, for example, one or more of silicon, germanium, silicon carbide, gallium arsenide, or indium gallium. Alternatively, the substrate may be a silicon-on-insulator substrate or a germanium-on-insulator substrate. Semiconductor devices, such as one or more of a PMOS transistor, a CMOS transistor, an NMOS transistor, a resistor, a capacitor, or an inductor, may also be formed within the substrate 110.

[0066] 10 , a hard mask material layer 120 is formed on the substrate 110 .

[0067] The hard mask material layer 120 is used to isolate and protect the surface of the substrate 110. The material of the hard mask material layer may be, for example, one or more of silicon nitride, silicon oxide, or silicon oxynitride. In a specific embodiment, when the hard mask material layer is multiple, the hard mask material layer may be a stack of multiple materials, for example, a stack of a silicon nitride layer and a silicon oxide layer. The process of forming the hard mask material layer on the substrate may include first forming a first hard mask material layer on the substrate, and then forming a second hard mask material layer on the first hard mask material layer. In a specific example, the material of the first hard mask layer may be silicon nitride, and the material of the second hard mask layer may be silicon oxide.

[0068] It should be noted that the above example is only an optional example, and the layer structure of the substrate can also be set accordingly according to actual needs, and the embodiment of the present disclosure is not limited to this.

[0069] 11 , a pattern transfer layer 130 is formed on the substrate 100 ;

[0070] The pattern transfer layer 130 can be used as a transition layer for forming a complete integrated circuit pattern on a substrate, and can also be referred to as a transition interposer. The material of the pattern transfer layer can be a material whose corresponding etching selectivity can be changed through chemical or physical operations. In one specific example, the material of the pattern transfer layer can be amorphous silicon.

[0071] Since the adapter plate needs to be masked multiple times during the formation process, the graphic transfer layer may include multiple spliced ​​graphic areas, different graphic areas correspond to different photolithography templates, and the splicing area of ​​at least two graphic areas is an overlapping area.

[0072] The photolithography template can be understood as a mask. A pattern may be corresponding to the photolithography template, and different photolithography templates can be combined to form the pattern of an integrated circuit. Specifically, when forming a photolithography pattern based on the photolithography template, any photolithography template may include a pattern consisting of an exposed area for exposure and a masked area for masking. In a specific example, the pattern of the exposed area for exposure of the photolithography template may be a conductive connection line, such as a metal line, corresponding to the formation of a conductive connection structure; and the pattern of the masked area for masking of the photolithography template may be a conductive connection hole, such as a through-hole, corresponding to the formation of a conductive connection structure.

[0073] As an optional implementation, in the example of retaining the substrate 110 and the hard mask material layer 120 , the step of forming a graphic transfer layer 130 on the substrate 100 may be specifically: forming a graphic transfer layer 130 on the hard mask material layer 120 .

[0074] Referring to FIG12 , the graphic transfer layer 130 is pre-processed;

[0075] Based on the pattern transition function of the pattern transfer layer 130, pre-processing the pattern transfer layer 130 can ensure that the multiple pattern regions of the pattern transfer layer have different etching selectivities between the exposed and masked regions based on the corresponding pattern of the photolithography template. For example, as shown in FIG12 , the pattern transfer layer 130 is pre-processed so that the exposed regions correspond to the darker regions of the pattern transfer layer 130, and the etching selectivity of the exposed regions is greater than that of the masked regions.

[0076] It should be noted that the pattern of the photolithography template can be transferred to the pattern transfer layer based on photolithography and etching processes. Specifically, a patterned photolithography mask layer can be first formed on the pattern transfer layer. The pattern of the photolithography mask layer corresponds to the pattern of the photolithography template corresponding to a pattern area. The pattern of the exposed area of ​​the photolithography template can expose the material of the pattern transfer layer, and the pattern of the masked area of ​​the photolithography template can mask the material of the pattern transfer layer. Then, using the photolithography mask layer as a mask, a pre-processing operation is performed on the pattern transfer layer. Then, the pre-processed pattern transfer layer is etched to form the pattern corresponding to the photolithography template on the pattern transfer layer. Since the multiple pattern areas of the pattern transfer layer have different etching selectivities between the exposed and masked areas based on the pattern of the corresponding photolithography template, the etching process can achieve different etching rates in the exposed and masked areas. Based on these different etching rates, the stability of the pattern corresponding to the photolithography template formed on the pattern transfer layer can be ensured, preventing pattern deformation.

[0077] In one optional example, since the pattern transfer layer includes multiple spliced ​​pattern areas, and different pattern areas correspond to different photolithography templates, the number of preprocessing times of the pattern transfer layer 130 can correspond to the number of pattern areas of the pattern transfer layer, thereby converting the patterns of different photolithography templates to the pattern transfer layer 130 to form a complete pattern corresponding to the integrated circuit pattern. In a specific example, for any pattern area, the step of preprocessing the pattern transfer layer may include:

[0078] 13, a patterned photolithography mask layer 140 is formed on the pattern transfer layer 130, and the pattern of the photolithography mask layer 140 corresponds to the pattern of the photolithography template corresponding to the pattern area;

[0079] Specifically, the patterned photolithography mask layer 140 formed on the pattern transfer layer 130 can be formed based on an exposure and development process. Taking Mask-1 as an example, based on the cross section of line Aa, and referring to FIG14 and FIG15 , the formation process of the photolithography mask layer 140 may include:

[0080] A photolithography mask material layer 140' is formed on the graphic transfer layer 130, and the photolithography mask material layer 140' can be a photoresist layer; Mask-1 is exposed and developed to remove the photolithography mask material layer 140' in the exposed area, and a patterned photolithography mask layer 140 is formed on the graphic transfer layer 130; corresponding to the pattern of the photolithography template, the photolithography mask layer 140 can expose part of the graphic transfer layer 130 and cover part of the graphic transfer layer 130.

[0081] Next, referring to FIG. 16 , a pre-processing operation is performed on the pattern transfer layer 130 using the photolithography mask layer 140 as a mask.

[0082] In an optional example, the pretreatment operation may at least include using an ion implantation process to implant ions into the exposed area of ​​the pattern transfer layer 130. By implanting ions into the exposed area of ​​the pattern transfer layer 130, different etching selectivities can be achieved between the exposed area and the masked area of ​​the pattern transfer layer 130.

[0083] The ion implantation dose may correspond to the thickness of the patterned transfer layer 130, so that the ions can penetrate the patterned transfer layer 130 and maintain the material stability of the patterned transfer layer 130. In a specific example, if the thickness of the patterned transfer layer is 30 nm, the ion implantation dose is E14 to E15, where E represents the ion energy in kev; "E14" indicates an ion implantation dose of 10 to the 14th power / square centimeter; and "E15" indicates an ion implantation dose of 10 to the 15th power / square centimeter.

[0084] It should be noted that the above example is only an optional implementation. The graphic transfer layer in the embodiment of the present disclosure may also have other thicknesses. Correspondingly, the ion implantation dose will also change with the thickness of the corresponding graphic transfer layer. The ion implantation dose in the embodiment of the present disclosure corresponds to the thickness of the graphic transfer layer to achieve penetration of the graphic transfer layer. The thickness of the graphic transfer layer and the corresponding ion implantation dose can be set according to actual needs. The implementation methods based on the concept of the present disclosure all fall within the protection scope of the embodiment of the present disclosure.

[0085] Furthermore, in an optional example, the material of the graphic transfer layer may be amorphous silicon, and the step of forming the graphic transfer layer on the substrate may be specifically as follows: depositing an amorphous silicon layer on the substrate and using the amorphous silicon layer as the graphic transfer layer; based on the material properties of amorphous silicon, the ion implantation process may be specifically as follows: implanting boron ions into the exposed amorphous silicon layer to change the etching selectivity of the amorphous silicon layer.

[0086] It should be noted that the above example is only an optional implementation. The graphic transfer layer in the embodiment of the present disclosure may also be other materials, and the method of causing the graphic transfer layer to produce etching selectivity changes may be an ion implantation process, chemical action or physical action, etc. The embodiment of the present disclosure does not limit this and can be set accordingly according to actual needs. The implementation method based on the concept of the method for forming the adapter board disclosed in the present disclosure all fall within the protection scope of the embodiment of the present disclosure.

[0087] As an optional implementation, referring to FIG. 17 , in an example where the photolithography mask layer 140 is retained, for any graphic area, the pre-processing of the graphic transfer layer may further include removing the photolithography mask layer 140 .

[0088] It should be noted that the number of pre-processing times of the graphic transfer layer in the present disclosure corresponds to the number of graphic areas of the graphic transfer layer. For the previous graphic area, after removing the photolithography mask layer 140, when performing operations on the next graphic area, it is necessary to re-form the photolithography mask material layer on the graphic transfer layer 130. Corresponding to Figures 14 to 17, referring to Figures 18 to 21, taking Mask-2 as an example, based on the cross-section of line Aa, a photoresist mask material layer 150' is formed on the graphic transfer layer 130. The photoresist mask material layer can be a photoresist layer. Mask-2 is exposed and developed to remove the photoresist mask material layer in the exposed area to form a patterned photoresist mask layer 150; then, using the photoresist mask layer 150 as a mask, a pretreatment operation is performed on the graphic transfer layer 130, that is, an ion implantation process is used to implant ions into the exposed area of ​​the graphic transfer layer 130, so that the exposed area and the masked area of ​​the graphic transfer layer 130 have different etching selectivities, and the photoresist mask layer 150 is removed.

[0089] It can be understood that in the embodiment of the present disclosure, for any graphic area, the pre-processing of the graphic transfer layer includes removing the photoresist mask layer, so that the photoresist mask layer can only be exposed once. Therefore, there will be no problem of multiple exposures of the photoresist causing the photoresist to be difficult to remove and resulting in residue, thereby further improving the product yield.

[0090] 22 , the pre-treated pattern transfer layer 130 is etched to form a pattern corresponding to the photolithography template on the pattern transfer layer 130 .

[0091] In one optional example, the etching of the pre-treated pattern transfer layer 130 can be performed by using a wet etching process to remove the transfer layer material corresponding to the masked area of ​​the pattern transfer layer 130 corresponding to the photolithography template. Optionally, when the pattern transfer layer is made of amorphous silicon and the ion implantation process involves implanting boron ions into the exposed amorphous silicon layer, the corresponding etching solution in the wet etching process can include a tetramethylammonium hydroxide solution to remove portions of the amorphous silicon layer not implanted with boron ions, while retaining the implanted areas, thereby forming an accurate and complete integrated circuit pattern on the amorphous silicon layer.

[0092] It should be noted that the above example is only an optional implementation. The etching process in the embodiment of the present disclosure can be a wet etching process, a dry etching process, or a process combining wet etching and dry etching. The etching solution in the wet etching process can also be selected according to the pre-treatment operation of the transfer layer in the graphic. The embodiment of the present disclosure does not limit this, and the specific settings can be made according to actual needs.

[0093] 23 , the substrate 100 is patterned using the pattern transfer layer 130 as a mask.

[0094] Based on the multiple graphic areas of the graphic transfer layer, graphics corresponding to different photolithography templates are formed on the graphic transfer layer, so that an accurate graphic corresponding to the integrated circuit can be formed on the graphic transfer layer. Then, using the graphic transfer layer as a mask, the substrate is patterned, and the accurate graphic can be transferred to the next layer structure of the graphic transfer layer corresponding to the substrate, thereby preparing a conductive connection structure corresponding to the designed integrated circuit and obtaining a transfer board.

[0095] In the disclosed embodiments, a pattern transfer layer on a substrate is preprocessed to ensure that the multiple pattern areas of the pattern transfer layer have different etching selectivities between the exposed and masked areas based on the pattern of the corresponding photolithography template. This allows for pattern transfer based on the etching process, ensuring the stability of the pattern on the pattern transfer layer and preventing pattern deformation. Furthermore, the pattern transfer layer is used as a mask to pattern the substrate and form the integrated circuit pattern on the substrate, thereby improving the accuracy of the integrated circuit pattern, thereby increasing the accuracy of critical dimensions and enhancing the device quality of the interposer.

[0096] In some embodiments, in the example of retaining the hard mask material layer 120, the step of patterning the substrate using the graphic transfer layer as a mask can be specifically to pattern the hard mask material layer 120 using the graphic transfer layer 130 as a mask to form a hard mask layer 120'.

[0097] In an optional example, after forming the hard mask layer 120 ′, referring to FIG. 24 , the pattern transfer layer 130 may be further removed;

[0098] 25 , a conductive material is deposited on the hard mask layer 120 ′ to form a conductive interconnect layer 160 ;

[0099] 26 , the conductive interconnect layer 160 is planarized to form a conductive interconnect structure 170 .

[0100] The conductive interconnect layer may be planarized using, for example, a chemical mechanical polishing process. Planarization of the conductive interconnect layer can smooth the surface of the conductive interconnect layer, thereby ensuring uniform thickness and improving the uniformity of subsequently formed conductive interconnect structures. In the example where the hard mask layer 120' is retained, the hard mask layer 120' may be used as a stop layer to planarize the conductive interconnect layer 160.

[0101] Since the accuracy of the pattern formed on the substrate is improved, a complete pattern can be formed on the substrate, thereby forming a conductive interconnection layer to obtain a conductive interconnection structure, avoiding distortion of the characteristic dimensions of the prepared conductive interconnection structure and improving device quality.

[0102] As can be seen, the disclosed embodiments pre-process the pattern transfer layer on the substrate, ensuring that the multiple pattern areas of the pattern transfer layer have different etching selectivities between the exposed and masked areas based on the corresponding pattern of the photolithography template. This allows for pattern transfer based on the etching process, ensuring the stability of the pattern on the pattern transfer layer and preventing pattern deformation. Furthermore, using the pattern transfer layer as a mask to pattern the substrate and form the integrated circuit pattern on the substrate, the accuracy of the integrated circuit pattern is improved, thereby improving the accuracy of critical dimensions and enhancing the device quality of the interposer.

[0103] The present disclosure also provides an adapter plate. The adapter plate may be formed based on the above method. Referring to FIG. 26 , the adapter plate may include:

[0104] substrate 100;

[0105] The conductive interconnect structure 170 is located on the substrate 100. The conductive interconnect structure 170 includes a plurality of spliced ​​graphic areas, and the splicing area of ​​at least two graphic areas is an overlapping area.

[0106] The conductive interconnect structure 170 may be a structure formed based on a designed integrated circuit pattern and used for electrically connecting to a chip and / or wafer.

[0107] The adapter board in the embodiment of the present disclosure improves the accuracy of the pattern of the integrated circuit corresponding to the conductive interconnect structure, thereby improving the accuracy of the key dimensions and enhancing the quality of the device.

[0108] In some embodiments, the integrated circuit pattern on the transfer board can be formed based on steps such as masking and exposure. Therefore, when the conductive interconnect structure includes multiple spliced ​​pattern areas, the conductive interconnect structure patterns corresponding to different pattern areas of the conductive interconnect structure 170 can be formed based on different photolithography templates. Moreover, any photolithography template can include a pattern consisting of an exposed area for exposure and a masked area for masking. The photolithography template can be understood as a mask, and different photolithography templates can be combined to form an integrated circuit pattern.

[0109] The above describes multiple embodiment schemes provided by the embodiments of the present disclosure. The various optional methods introduced in each embodiment scheme can be combined and cross-referenced with each other without conflict, thereby extending a variety of possible embodiment schemes, which can all be considered as embodiment schemes disclosed and disclosed by the embodiments of the present disclosure.

[0110] Although the embodiments of the present disclosure are disclosed above, the present disclosure is not limited thereto. Any person skilled in the art may make various changes and modifications without departing from the spirit and scope of the present disclosure. Therefore, the scope of protection of the present disclosure shall be based on the scope defined by the claims.

Claims

1. A method for forming an adapter plate, comprising: providing a substrate; A graphic transfer layer is formed on the substrate, wherein the graphic transfer layer includes a plurality of spliced ​​graphic areas, different graphic areas correspond to different photolithography templates, and the splicing area of ​​at least two graphic areas is an overlapping area; wherein any of the photolithography templates includes a graphic consisting of an exposure area for exposure and a masking area for masking; Preprocessing the pattern transfer layer so that the plurality of pattern regions of the pattern transfer layer have different etching selectivity ratios in corresponding exposed regions and masked regions based on the patterns of the corresponding photolithography template; Etching the pre-treated pattern transfer layer to form the pattern of the corresponding photolithography template on the pattern transfer layer; The substrate is patterned using the pattern transfer layer as a mask.

2. The method for forming an adapter plate according to claim 1, wherein: The number of times of the preprocessing of the graphic transfer layer corresponds to the number of graphic areas of the graphic transfer layer; For any of the graphic areas, the preprocessing of the graphic transfer layer includes: forming a patterned photolithography mask layer on the pattern transfer layer, wherein the pattern of the photolithography mask layer corresponds to the pattern of the photolithography template corresponding to the pattern area; The preprocessing is performed once on the pattern transfer layer using the photolithography mask layer as a mask.

3. The method for forming an adapter plate according to claim 2, wherein: The pretreatment includes: using an ion implantation process to implant ions into the exposed area of ​​the transfer layer in the pattern.

4. The method for forming an adapter plate according to claim 3, wherein: In response to the thickness of the pattern transfer layer being 30 nm, the ion implantation dose of the ions is E14 to E15.

5. The method for forming an adapter plate according to claim 4, wherein: The material of the graphic transfer layer is amorphous silicon; The forming of the graphic transfer layer on the substrate comprises: depositing an amorphous silicon layer on the substrate, and using the amorphous silicon layer as the graphic transfer layer; The ion implantation process includes: implanting boron ions into the exposed amorphous silicon layer.

6. The method for forming an adapter plate according to any one of claims 2 to 5, wherein: For any of the graphic areas, the pre-processing of the graphic transfer layer further includes: removing the photolithography mask layer.

7. The method for forming an adapter plate according to any one of claims 1 to 6, wherein: The etching of the graphic transfer layer after pre-treatment comprises: using a wet etching process to remove the transfer layer material corresponding to the masking area of ​​the graphic transfer layer corresponding to the photolithography template.

8. The method for forming an adapter plate according to claim 7, wherein: The corresponding etching solution in the wet etching process includes tetramethylammonium hydroxide solution.

9. The method for forming an adapter plate according to any one of claims 1 to 8, wherein: The providing of the substrate comprises: providing a substrate; A hard mask material layer is formed on the substrate.

10. The method for forming an adapter plate according to claim 9, wherein: The forming of the graphic transfer layer on the substrate comprises: forming the graphic transfer layer on the hard mask material layer; The method of patterning the substrate by using the pattern transfer layer as a mask includes: patterning the hard mask material layer by using the pattern transfer layer as a mask to form a hard mask layer.

11. The method for forming an adapter plate according to claim 10, further comprising: depositing a conductive material on the hard mask layer to form a conductive interconnect layer; The conductive interconnect layer is planarized to form a conductive interconnect structure.

12. An adapter plate, the adapter plate being prepared according to the method for forming an adapter plate according to any one of claims 1 to 11, the adapter plate comprising: substrate; A conductive interconnect structure is located on the substrate, wherein the conductive interconnect structure includes a plurality of spliced ​​graphic areas, and the splicing area of ​​at least two graphic areas is an overlapping area.

13. The adapter plate according to claim 12, wherein: The conductive interconnect structure patterns corresponding to different pattern areas of the conductive interconnect structure are formed based on different photolithography templates; wherein any of the photolithography templates includes a pattern consisting of an exposure area for exposure and a masking area for masking.

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