Ferroelectric memory and data reading method and data writing method therefor, and electronic device

Abstract

A ferroelectric memory and a data reading method and data writing method therefor. The ferroelectric memory comprises a memory cell array, a plurality of word lines and a plurality of bit lines. The memory cell array comprises a plurality of memory cells arranged in an array, wherein each memory cell stores n bits of data, each memory cell comprises a transistor and 2n-1 ferroelectric capacitors coupled to the transistor, and n is a positive integer greater than 1. Each word line is coupled to memory cells arranged in a row in the memory cell array. Each bit line is coupled to memory cells arranged in a column in the memory cell array. By means of the present solution, multi-state storage of a ferroelectric memory can be implemented, thereby improving the storage density of the ferroelectric memory.

Description

Ferroelectric memory, data reading method, data writing method, and electronic device

[0001] This application claims priority to the Chinese patent application filed with the China Patent Office on June 13, 2023, with application number 202310707370.8 and application name “Ferroelectric memory and its data reading method and data writing method”, the entire contents of which are incorporated by reference into this application. Technical Field

[0002] The present disclosure relates to the field of semiconductor technology, and in particular to a ferroelectric memory, a data reading method and a data writing method thereof, and an electronic device. Background Art

[0003] With the rapid development of electronic technology, non-volatile transistor memories have seen significant growth, with the ability to be prepared using solution methods and compatible with integrated circuits. These include NAND flash memory, NOR flash memory, resistance random access memory, phase change memory, magnetoresistive random access memory, ferroelectric memory, and spin transfer torque random access memory. Among these, ferroelectric memory holds the greatest commercial value due to its high integration density, good repeatability, and fast response speed. However, ferroelectric memory suffers from relatively low storage density.

[0004] Summary of the Invention

[0005] [Corrected 16.10.2024 according to Rule 91] According to a first aspect of an embodiment of the present disclosure, a ferroelectric memory is provided, comprising: a memory cell array, wherein the memory cell array comprises a plurality of memory cells arranged in an array, each of the memory cells storing n-bit data, wherein each of the memory cells comprises: a transistor and two transistors coupled to the transistor. n -1 ferroelectric capacitor, wherein n is a positive integer greater than 1; a plurality of word lines, each of which is coupled to the memory cells arranged in a row in the memory cell array; and a plurality of bit lines, each of which is coupled to the memory cells arranged in a column in the memory cell array.

[0006] [Corrected 16.10.2024 according to Rule 91] In some embodiments, each of the ferroelectric capacitors includes a first plate and a second plate disposed opposite to each other, and a dielectric layer filled between the first plate and the second plate; n - 1 said ferroelectric capacitors are arranged in sequence along the first direction, 2 n - 1 of the first plates are connected into an integrated structure, 2 n -1 the second electrode plate is connected into an integrated structure, 2 n -1 said dielectric layers are connected into an integral structure, and the dielectric layers have different thicknesses.

[0007] [Corrected 16.10.2024 according to Rule 91] In some embodiments, along the first direction, 2 n -The thickness of the dielectric layer of each of the ferroelectric capacitors increases sequentially.

[0008] [Corrected 16.10.2024 according to Rule 91] In some embodiments, along the first direction, 2 n -1 The coercive voltages of the ferroelectric capacitors are arranged in an arithmetical order.

[0009] [Corrected 16.10.2024 according to Rule 91] In some embodiments, 2 n -1 The second plate has the same potential as 2 n -1 first electrode plate is connected to one of the source and drain of the corresponding transistor (11), the other of the source and drain of the transistor is connected to the corresponding bit line, and the gate of the transistor is connected to the corresponding word line.

[0010] [Corrected 16.10.2024 according to Rule 91] In some embodiments, 2 n -1 second electrode plate connected into an integrated structure and connected to the same power line, 2 n -1 the potential of the second electrode plate is the same.

[0011] [Corrected 16.10.2024 according to Rule 91] In some embodiments, each of the ferroelectric capacitors includes a first plate and a second plate disposed opposite to each other, and a dielectric layer filled between the first plate and the second plate; n - 1 said ferroelectric capacitors are arranged in sequence along the first direction, 2 n - 1 of the first plates are connected into an integrated structure, 2 n -1 said dielectric layers are connected into an integrated structure, 2 n - One of the second electrode plates is arranged at intervals.

[0012] [Corrected 16.10.2024 according to Rule 91] In some embodiments, 2 n -1 The thickness of the dielectric layer is equal to that of 2 n -1 The coercive voltages of the ferroelectric capacitors are the same.

[0013] [Corrected 16.10.2024 according to Rule 91] In some embodiments, 2 n -1 The second electrode plates have the same length.

[0014] [Corrected 16.10.2024 according to Rule 91] In some embodiments, 2 n -1 The second plate potentials are different, 2n -1 first electrode plate is connected to one of the source and drain of the corresponding transistor, the other of the source and drain of the transistor is connected to the corresponding bit line, and the gate of the transistor is connected to the corresponding word line.

[0015] [Corrected 16.10.2024 according to Rule 91] In some embodiments, 2 n -1 second electrode plate connected to different power lines, 2 n -1 The potentials of the second electrodes are different.

[0016] In some embodiments, the second electrode plate, the dielectric layer, and the first electrode plate are stacked in sequence to form a planar capacitor.

[0017] In some embodiments, the transistor is a thin film transistor.

[0018] [Corrected 16.10.2024 according to Rule 91] According to a second aspect of an embodiment of the present disclosure, a data reading method of a ferroelectric memory is provided, which is applied to the above-mentioned ferroelectric memory. The data reading method comprises: using a bit line and a transistor to read the corresponding 2 n -1 The first plates of the ferroelectric capacitors are all charged to a first voltage, and the first voltage causes the polarization direction of each of the ferroelectric capacitors to point to the first plate. When the polarization direction of the ferroelectric capacitor is reversed, the ferroelectric capacitor flows out positive charge to the bit line; according to the change in the charge amount of the bit line, the data in the storage unit is obtained, wherein the storage unit stores n bits of the data.

[0019] [Corrected 16.10.2024 according to Rule 91] In some embodiments, 2 n -1 ferroelectric capacitors are arranged in sequence along the first direction, 2 n -1 first electrode plate forming an integrated structure; 2 n -1 second plate forms an integrated structure and is connected to the same power line, 2 n -1 The potential of the second electrode plate is the same; 2 n -1 dielectric layer forms an integrated structure, and 2 n -1 The thickness of the dielectric layer is different.

[0020] [Corrected 16.10.2024 according to Rule 91] In some embodiments, 2 n -1 ferroelectric capacitors are arranged in sequence along the first direction, 2 n -1 first electrode plate forming an integrated structure; 2 n -1 dielectric layer forms an integrated structure; 2 n -1 second plates are arranged at intervals and connected to different power lines, 2n -1 The potentials of the second electrodes are different.

[0021] [Corrected 16.10.2024 according to Rule 91] According to a third aspect of an embodiment of the present disclosure, a data writing method for a ferroelectric memory is provided, which is applied to the above-mentioned ferroelectric memory. The data writing method comprises: using a bit line and a transistor to write the corresponding 2 n - charging the first plate of a ferroelectric capacitor to a first voltage, wherein the first voltage causes the polarization direction of each storage capacitor to point to the first plate, so as to initialize each ferroelectric capacitor; applying a write voltage to the bit line, and the memory cell stores data; wherein the write voltage has a value of 2 n A voltage value, the storage unit stores n bits of data, each voltage value corresponds to one type of data, some of the voltage values ​​cause the polarization direction of at least some of the ferroelectric capacitors to flip, and different voltage values ​​cause different numbers of the ferroelectric capacitors whose polarization directions are flipped.

[0022] [Corrected 16.10.2024 according to Rule 91] In some embodiments, 2 n -1 ferroelectric capacitors are arranged in sequence along the first direction, 2 n -1 first electrode plate forming an integrated structure; 2 n -1 second plate forms an integrated structure and is connected to the same power line, 2 n -1 The potential of the second electrode plate is the same; 2 n -1 dielectric layer forms an integrated structure, and 2 n -1 The thickness of the dielectric layer is different.

[0023] [Corrected 16.10.2024 according to Rule 91] In some embodiments, 2 n -1 ferroelectric capacitors are arranged in sequence along the first direction, 2 n -1 first electrode plate forming an integrated structure; 2 n -1 dielectric layer forms an integrated structure; 2 n -1 second plates are arranged at intervals and connected to different power lines, 2 n -1 The potentials of the second electrodes are different.

[0024] According to a fourth aspect of the embodiments of the present disclosure, there is provided an electronic device, comprising: a processing device; and a memory device electrically connected to the processing device, wherein the memory device comprises the above-mentioned ferroelectric memory.

[0025] [Corrected 16.10.2024 according to Rule 91] The data writing method of the ferroelectric memory in the embodiment of the present disclosure is applied to a ferroelectric memory of multi-state storage, wherein each memory cell of the ferroelectric memory includes a transistor and a 2 coupled transistor. n -1 ferroelectric capacitor, n is a positive integer greater than 1. By n The first plates of the ferroelectric capacitors are all charged to a first voltage. The first voltage causes the polarization direction of each ferroelectric capacitor to point toward the first plate, thereby initializing each ferroelectric capacitor. Different write voltage values ​​are then used, each voltage value corresponding to a type of data. Some voltage values ​​cause the polarization direction of at least some ferroelectric capacitors to flip, and different voltage values ​​cause different numbers of ferroelectric capacitors to flip their polarization directions, thereby enabling the writing of n-bit data and improving the storage density of the ferroelectric memory. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] FIG1 is a schematic diagram of a storage device 1 of a ferroelectric capacitor in the related art;

[0027] FIG2 is a schematic diagram of a ferroelectric capacitor storing 0 in the related art;

[0028] FIG3 is a schematic structural diagram of a ferroelectric memory in an embodiment of the present disclosure;

[0029] FIG4 is a schematic diagram of a polarization state in an embodiment of the present disclosure;

[0030] FIG5 is a schematic structural diagram of a ferroelectric capacitor in one embodiment of the present disclosure;

[0031] FIG6 is a first storage state of the ferroelectric capacitor in FIG5 ;

[0032] FIG7 is a second storage state of the ferroelectric capacitor in FIG5 ;

[0033] FIG8 is a third storage state of the ferroelectric capacitor in FIG5 ;

[0034] FIG9 is a fourth storage state of the ferroelectric capacitor in FIG5 ;

[0035] FIG10 is another structural diagram of a ferroelectric capacitor in one embodiment of the present disclosure;

[0036] FIG11 is a schematic diagram showing the connection between a transistor and a ferroelectric capacitor in an embodiment of the present disclosure;

[0037] FIG12 is a first storage state of the ferroelectric capacitor in FIG10;

[0038] FIG13 is a second storage state of the ferroelectric capacitor in FIG10;

[0039] FIG14 is a third storage state of the ferroelectric capacitor in FIG10;

[0040] FIG15 is a fourth storage state of the ferroelectric capacitor in FIG10;

[0041] FIG16 is a flow chart of a method for reading data from a ferroelectric capacitor according to an embodiment of the present disclosure;

[0042] FIG17 is a schematic diagram of the bit line pre-charging when the ferroelectric capacitor data is read in FIG5;

[0043] FIG18 is a diagram showing a change in polarization direction of the ferroelectric capacitor in the first storage state in FIG5 ;

[0044] FIG19 is a diagram showing a change in polarization direction of the ferroelectric capacitor in the second storage state in FIG5 ;

[0045] FIG20 is a diagram showing a change in polarization direction of the ferroelectric capacitor in the third storage state in FIG5 ;

[0046] FIG21 is a diagram showing a change in polarization direction of the ferroelectric capacitor in the fourth storage state in FIG5 ;

[0047] FIG22 is a schematic diagram of bit line precharging when reading data from the ferroelectric capacitor in FIG10;

[0048] FIG23 is a diagram showing a change in polarization direction of the ferroelectric capacitor in the first storage state in FIG10 ;

[0049] FIG24 is a diagram showing a change in polarization direction of the ferroelectric capacitor in the second storage state in FIG10 ;

[0050] FIG25 is a diagram showing a change in polarization direction of the ferroelectric capacitor in the third storage state in FIG10;

[0051] FIG26 is a diagram showing a change in polarization direction of the ferroelectric capacitor in the third storage state in FIG10 ;

[0052] FIG27 is a flow chart of a method for writing data into a ferroelectric capacitor according to an embodiment of the present disclosure;

[0053] FIG28 is a schematic diagram of precharging the bit line when writing data into the ferroelectric capacitor in FIG5 ;

[0054] FIG29 is a diagram showing a change in polarization direction of the ferroelectric capacitor in FIG5 when the write voltage is a first preset value;

[0055] FIG30 is a diagram showing a change in polarization direction of the ferroelectric capacitor in FIG5 when the write voltage is a second preset value;

[0056] FIG31 is a diagram showing a change in polarization direction of the ferroelectric capacitor in FIG5 when the write voltage is a third preset value;

[0057] FIG32 is a diagram showing a change in polarization direction of the ferroelectric capacitor in FIG5 when the write voltage is a fourth preset value;

[0058] FIG33 is a schematic diagram of precharging the bit line when writing data into the ferroelectric capacitor in FIG10;

[0059] FIG34 is a diagram showing a change in polarization direction of the ferroelectric capacitor in FIG10 when the write voltage is a first preset value;

[0060] FIG35 is a diagram showing a change in polarization direction of the ferroelectric capacitor in FIG10 when the write voltage is a second preset value;

[0061] FIG36 is a diagram showing a change in polarization direction of the ferroelectric capacitor in FIG10 when the write voltage is a third preset value;

[0062] FIG37 is a diagram showing a change in polarization direction of the ferroelectric capacitor in FIG10 when the write voltage is a fourth preset value;

[0063] FIG38 is a schematic structural diagram of an electronic device according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0064] The technical solutions of the present disclosure will be further described in detail below with reference to the accompanying drawings and examples. Although the accompanying drawings illustrate exemplary implementations of the present disclosure, it should be understood that the present disclosure can be implemented in various forms and should not be limited by the embodiments described herein. Rather, these embodiments are provided to enable a more thorough understanding of the present disclosure and to fully convey the scope of the present disclosure to those skilled in the art.

[0065] The following paragraphs describe the present disclosure in more detail by way of example with reference to the accompanying drawings. The advantages and features of the present disclosure will become more apparent from the following description and claims. It should be noted that the drawings are highly simplified and not to exact scale, and are intended solely to facilitate and clearly illustrate the embodiments of the present disclosure.

[0066] It will be understood that the meanings of “on,” “over,” and “over” throughout this disclosure should be interpreted in the broadest manner, such that “on” not only means being “on” something with no intervening features or layers (i.e., directly on something), but also includes being “on” something with intervening features or layers.

[0067] In the embodiments of the present disclosure, the terms "first," "second," "third," etc. are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence.

[0068] In the embodiments of the present disclosure, the term "layer" refers to a portion of a material including an area having a thickness. A layer may extend over the entirety of a lower or upper structure, or may have an extent that is smaller than the extent of the lower or upper structure. In addition, a layer may be an area of ​​a homogeneous or inhomogeneous continuous structure having a thickness that is smaller than the thickness of the continuous structure. For example, a layer may be located between the top and bottom surfaces of a continuous structure, or a layer may be between any horizontal faces at the top and bottom surfaces of a continuous structure. A layer may extend horizontally, vertically, and / or along an inclined surface. A layer may include multiple sublayers.

[0069] It should be noted that the technical solutions described in the embodiments of the present disclosure can be arbitrarily combined without conflict.

[0070] Ferroelectric memories in the related art have storage density issues. The inventors have discovered that this is due to the fact that ferroelectric memories comprise multiple memory cells, each typically a 1T1C (ferroelectric cell) structure consisting of a transistor and a ferroelectric capacitor. As shown in Figures 1 and 2, ferroelectric capacitors have two polarization directions, meaning they have two stable states, stored as either "0" or "1." Each memory cell can only store one bit of data, resulting in a low storage density.

[0071] [Corrected 16.10.2024 according to Rule 91] To this end, the present disclosure provides a ferroelectric memory comprising a plurality of memory cells, each memory cell comprising a transistor and two coupled transistors. n -1 ferroelectric capacitor, n is a positive integer greater than 1, to store n bits of data. n -1 The polarization direction of a ferroelectric capacitor can determine 2 n storage states, each storage state corresponds to a data, so that 2 n -1 ferroelectric capacitor stores n bits of data, realizing polymorphic storage of ferroelectric memory and improving the storage density of ferroelectric memory.

[0072] In order to make the above-mentioned purposes, features and advantages of the embodiments of the present disclosure more obvious and easy to understand, the technical solutions in the embodiments of the present disclosure will be clearly and completely described below in conjunction with the drawings in the embodiments of the present disclosure. Obviously, the described embodiments are only part of the embodiments of the present disclosure, not all of the embodiments. Based on the embodiments in the present disclosure, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of the present disclosure.

[0073] Referring to FIG3 , an embodiment of the present disclosure provides a semiconductor structure comprising a memory cell array, and a plurality of word lines 30 and a plurality of bit lines 20 electrically connected to the memory cell array. The memory cell array is used to store data and includes a plurality of memory cells 10 arranged in an array and spaced apart. That is, the plurality of memory cells 10 are arranged in multiple rows and columns, with the row direction (the X direction shown in FIG3 ) and the column direction (the Y direction shown in FIG3 ) being perpendicular, to increase the storage density of the memory cell array.

[0074] A plurality of word lines 30 are arranged at intervals, and a plurality of bit lines 20 are arranged at intervals. The word lines 30 extend in a direction that intersects, for example, is perpendicular to, the direction in which the bit lines 20 extend. Each word line 30 is coupled to memory cells 10 arranged in a row in the memory cell array, i.e., each word line 30 is coupled to a row of memory cells 10. Each bit line 20 is coupled to memory cells 10 arranged in a column in the memory cell array, i.e., each bit line 20 is coupled to a column of memory cells 10.

[0075] [Corrected 16.10.2024 according to Rule 91] Continuing to refer to FIG3, each memory cell 10 stores n bits of data. Each memory cell 10 includes a transistor 11 and two transistors coupled to the transistor 11. n -1 ferroelectric capacitor 12, where n is a positive integer greater than 1. When the transistor 11 is turned on, the memory cell 10 performs data writing or data reading.

[0076] Each ferroelectric capacitor 12 includes a first pole plate 121 and a second pole plate 122 that are relatively arranged, and a dielectric layer 123 that is filled between the first pole plate 121 and the second pole plate 122. The first pole plate 121 and the second pole plate 122 are respectively provided on both sides of the dielectric layer 123. The material of the dielectric layer 123 is a ferroelectric material, that is, the second pole plate 122, the dielectric layer 123 and the first pole plate 121 are stacked in sequence to form a planar capacitor. As shown in Figure 3, the second pole plate 122 is the bottom plate of the ferroelectric capacitor 12, and the first pole plate 121 is the top plate of the ferroelectric capacitor 12.

[0077] [Corrected 16.10.2024 according to Article 91] Due to 2 n Each of the ferroelectric capacitors 12 can be polarized according to 2 n -1 The polarization direction of the ferroelectric capacitor 12 can be determined by 2 n storage states, each storage state corresponds to a data, so that 2 n -1 ferroelectric capacitor 12 stores n bits of data. Among them, the storage state is 2 n -The number of ferroelectric capacitors 12 with a polarization direction in a preset direction in one ferroelectric capacitor 12 .

[0078] Exemplary, consult Fig. 4, when n takes value as 2, the transistor 11 correspondences in each storage cell 10 are connected to 3 ferroelectric capacitors 12, and three ferroelectric capacitors 12 can determine 4 kinds of storage states, to store 2 bit data.Wherein, the ferroelectric capacitor 12 that polarization direction points to the third direction can have 3,2,1 or 0, and correspondingly, three ferroelectric capacitors 12 correspond to data 00,10,01,11 respectively.As shown in Figure 4, it is meant that polarization direction points to the third direction, and namely polarization direction points to the upper plate (first plate 121) of ferroelectric capacitor 12.Certainly, when n takes value as 3, the transistor 11 correspondences in each storage cell 10 are connected to 7 ferroelectric capacitors 12, and three ferroelectric capacitors 12 can determine 8 kinds of storage states, to store 3 bit data.

[0079] It can be understood that when there are 3 ferroelectric capacitors 12 with polarization directions pointing to the third direction, that is, all three ferroelectric capacitors 12 are polarized in the third direction (upward), and the three ferroelectric capacitors 12 correspond to 00, that is, the memory cell stores 00. When there are 2 polarization directions pointing to the third direction, that is, any two ferroelectric capacitors 12 of the three ferroelectric capacitors 12 are polarized in the third direction (upward), and the other ferroelectric capacitor 12 is polarized in the opposite direction (downward) of the third direction, and the three ferroelectric capacitors 12 correspond to 10, that is, the memory cell stores 10. When there is 1 polarization direction pointing to the third direction, that is, any one ferroelectric capacitor 12 of the three ferroelectric capacitors 12 is polarized in the third direction (upward), and the other two ferroelectric capacitors 12 are polarized in the opposite direction (downward) of the third direction, and the three ferroelectric capacitors 12 correspond to 01, that is, the memory cell stores 01. When the number of ferroelectric capacitors 12 with polarization pointing in the third direction is zero, that is, all three ferroelectric capacitors 12 are polarized in the opposite direction (downward) of the third direction, the three ferroelectric capacitors 12 correspond to 11, that is, the memory cell stores 11. The three ferroelectric capacitors 12 have four different polarization modes and thus have four storage states to store 2 bits of data.

[0080] [Corrected 16.10.2024 according to Rule 91] Referring to Figures 3 and 5, in some possible embodiments, 2 n -1 ferroelectric capacitors 12 are arranged in sequence along the first direction, wherein 2 n -1 first electrode plate 121 forms an integrated structure, 2 n -1 second electrode plate 122 forms an integrated structure, 2 n -1 dielectric layer 123 forms an integral structure, and 2 n -1 dielectric layer 123 has different thicknesses so that 2 n The coercive voltages of the −1 ferroelectric capacitors 12 are different, and thus the ferroelectric capacitors 12 have n storage states.

[0081] It is understood that, because the thickness of each dielectric layer 123 varies, the second plates 122 are spaced apart along the thickness direction of the dielectric layer 123, and adjacent second plates 122 are connected by a connecting plate to form a single unit. If the dielectric layers 123 are made of the same material, the thicker the dielectric layer 123, the greater the coercive voltage of the ferroelectric capacitor 12, and the greater the applied voltage required to flip its polarization direction.

[0082] [Corrected 16.10.2024 according to Rule 91] In some examples, along the first direction, 2 n -1 The thickness of the dielectric layer 123 of the ferroelectric capacitor 12 increases successively, that is, 2 n -1 second electrode plate 122 is connected in a step shape, the second electrode plate 122 forms a step surface, and the two ends of the connecting electrode plate are respectively connected to the two adjacent second electrode plates 122. n The coercive voltages of the ferroelectric capacitors 12 are sequentially increased, thereby reducing the leakage current between adjacent ferroelectric capacitors 12 .

[0083] [Corrected 16.10.2024 according to Article 91] Wherein, in the first direction, 2 n -1 The coercive voltages of the ferroelectric capacitors 12 are arranged in an arithmetic order, that is, along the first direction 2 n The coercive voltage gradient of each ferroelectric capacitor 12 is increased. This configuration reduces leakage current while also providing a certain degree of differentiation between the coercive voltages of the ferroelectric capacitors 12, thereby preventing erroneous polarization reversal of the ferroelectric capacitors 12. In an example where the memory cell 10 includes three ferroelectric capacitors 12, the coercive voltages of the three ferroelectric capacitors 12 may be 0.5V, 1.5V, and 2.5V, respectively.

[0084] [Corrected 16.10.2024 in accordance with Article 91] Continuing with Figures 3 and 5, 2 n -1 second plates 122 have the same potential, for example, connected to zero potential, that is, the external voltage applied to each ferroelectric capacitor 12 is the same. When the external voltage is greater than the coercive voltage, the polarization direction of the ferroelectric capacitor 12 is reversed. n A first electrode plate 121 is connected to one of the source and drain of the corresponding transistor 11, and the other of the source and drain of the transistor 11 is connected to the corresponding bit line 20, so that data can be written to the ferroelectric capacitor 12 via the bit line 20, or data in the ferroelectric capacitor 12 can be read out to the bit line 20. The gate of the transistor 11 is connected to the corresponding word line 30, which controls whether the transistor 11 is turned on or off.

[0085] [Corrected 16.10.2024 according to Rule 91] As shown in Figures 3 and 5, 2 n - a first electrode plate 121 is formed as a whole and connected to the bit line 20, 2 through the transistor 11 n- 1 second electrode plate 122 is formed into one body and connected to the same power line PL, so that the 2 n -1 second electrode plate 122 has the same potential. The voltage difference between the first electrode plate 121 and the second electrode plate 122 arranged opposite to each other is the external voltage of the ferroelectric capacitor 12. n -1 ferroelectric capacitor 12 has the same applied voltage, while 2 n -1 ferroelectric capacitor 12 has different coercive voltages. According to the relationship between the applied voltage and the coercive voltage, n The polarization direction of a ferroelectric capacitor 12 is reversed or remains unchanged, thereby writing or reading data.

[0086] [Corrected 16.10.2024 in accordance with Article 91] See Figures 6 to 9, 2 n -1 ferroelectric capacitor 12 with 2 n There are 2 storage states n There are four different polarization states, each storage state can correspond to one data, so as to store n bits of data. For example, when n is 2, the three ferroelectric capacitors 12 have four storage states, corresponding to 00, 10, 01, and 11 respectively.

[0087] As shown in FIG6 , the polarization directions of all the ferroelectric capacitors 12 among the three ferroelectric capacitors 12 point to the first pole plate 121, and this polarization state corresponds to 00. As shown in FIG7 , the polarization directions of two of the three ferroelectric capacitors 12 point to the first pole plate 121, and this polarization state corresponds to 10. As shown in FIG8 , the polarization direction of one of the three ferroelectric capacitors 12 points to the first pole plate 121, and this polarization state corresponds to 01. As shown in FIG9 , the polarization directions of all the ferroelectric capacitors 12 among the three ferroelectric capacitors 12 point to the second pole plate 122, and this polarization state corresponds to 11.

[0088] [Corrected 16.10.2024 according to Rule 91] Referring to Figures 10 and 11, in some other possible embodiments, 2 n -1 ferroelectric capacitor 12 is arranged in sequence along the first direction, 2 n - 1 first electrode plate 121 connected into an integrated structure, 2 n -1 dielectric layer 123 connected into an integrated structure, 2 n The second plates 122 are arranged at intervals so that the applied voltages of the ferroelectric capacitors 12 are different (e.g., arranged equidistantly) and the applied voltages of the ferroelectric capacitors 12 remain unchanged, thereby having n storage states. In an example where the memory cell 10 includes three ferroelectric capacitors 12, the applied voltages of the three ferroelectric capacitors 12 can be -1V, 0V, and 1V, respectively.

[0089] [Corrected 16.10.2024 in accordance with Rule 91] Of these, 2n -1 dielectric layer 123 has the same thickness so that 2 n The coercive voltages of the ferroelectric capacitors 12 are the same to facilitate manufacturing. Due to the coercive voltages of the ferroelectric capacitors 12, there is no need to distinguish the ferroelectric capacitors 12. By adjusting the applied voltage of each ferroelectric capacitor 12, data can be written to or read from the memory cell 10. n The lengths of the second plates 122 are the same so that the ferroelectric capacitors 12 are the same.

[0090] It can be understood that in order to achieve connection between the ferroelectric capacitors 12, a connecting plate is connected between two adjacent first plates 121 along the first direction, and a connecting layer is connected between two adjacent dielectric layers 123, so as to achieve that each first plate 121 forms an integral body, each dielectric layer 123 forms an integral body, and each second plate 122 is arranged at intervals.

[0091] [Corrected 16.10.2024 according to Rule 91] In order to realize data writing or data reading, as shown in FIG11, 2 n -1 second electrode plate 122 has different potentials, 2 n A first electrode plate 121 is connected to one of the source and drain of the corresponding transistor 11 , the other of the source and drain of the transistor 11 is connected to the corresponding bit line 20 , and the gate of the transistor 11 is connected to the corresponding word line 30 .

[0092] [Corrected 16.10.2024 according to Rule 91] As shown in Figure 10, 2 n - a first electrode plate 121 is formed as a whole and connected to the bit line 20, 2 through the transistor 11 n -1 second electrode plate 122 is connected to different power lines, so that 2 n The potentials of the two second plates 122 are different. The voltage difference between the first plate 121 and the second plate 122 arranged opposite to each other is the external voltage of the ferroelectric capacitor 12. n -1 ferroelectric capacitor 12 has different applied voltages. According to the relationship between the applied voltage and the coercive voltage, 2 n The polarization direction of a ferroelectric capacitor 12 is reversed or remains unchanged, thereby writing or reading data.

[0093] [Corrected 16.10.2024 in accordance with Article 91] See Figures 10 to 15, 2 n -1 ferroelectric capacitor 12 with 2 n There are 2 storage states nThere are four different polarization states, each storage state can correspond to a data, so as to store n bits of data. For example, when n is 2, the three ferroelectric capacitors 12 have four storage states, corresponding to 00, 10, 01, and 11 respectively.

[0094] As shown in FIG12 , the polarization directions of all the ferroelectric capacitors 12 among the three ferroelectric capacitors 12 point to the first pole plate 121, and this polarization state corresponds to 00. As shown in FIG13 , the polarization directions of two of the three ferroelectric capacitors 12 point to the first pole plate 121, and this polarization state corresponds to 10. As shown in FIG14 , the polarization direction of one of the three ferroelectric capacitors 12 points to the first pole plate 121, and this polarization state corresponds to 01. As shown in FIG15 , the polarization directions of all the ferroelectric capacitors 12 among the three ferroelectric capacitors 12 point to the second pole plate 122, and this polarization state corresponds to 11.

[0095] The type and structure of transistor 11 in the disclosed embodiment are not limited. Transistor 11 may be a thin film transistor (TFT) to facilitate 3D stacking. Transistor 11 may also be a planar transistor, etc., to be compatible with dynamic random access memory (DRAM) processes.

[0096] For example, as shown in FIG11 , transistor 11 includes an active region disposed within substrate 40, a gate dielectric layer 50 located above the active region, and a gate located on gate dielectric layer 50, with word line 30 serving as the gate. A first plate 121 of ferroelectric capacitor 12 is connected to form an integral structure and is connected to the active region via plug 60. Second plates 122 of ferroelectric capacitor 12 are connected to wires 70, respectively, and are connected to peripheral circuits via wires 70 to provide different voltage values ​​to second plates 122 of ferroelectric capacitor 12, thereby placing second plates 122 of ferroelectric capacitor 12 at different potentials.

[0097] [Corrected 16.10.2024 according to Rule 91] In summary, the ferroelectric memory provided by the embodiment of the present disclosure includes a memory cell array, a plurality of word lines 30, and a plurality of bit lines 20. The memory cell array includes a plurality of memory cells 10 arranged in an array. Each word line 30 is coupled to a memory cell 10 arranged in a row in the memory cell array, and each bit line 20 is coupled to a memory cell 10 arranged in a column in the memory cell array. Each memory cell 10 includes a transistor 11 and a 2-bit transistor coupled to the transistor 11. n -1 ferroelectric capacitor 12, n is a positive integer greater than 1, to store n bits of data. n -1 The polarization direction of the ferroelectric capacitor 12 can be determined by 2 n storage states, each storage state corresponds to a data, so that 2n - One ferroelectric capacitor 12 stores n-bit data, realizing polymorphic storage of the ferroelectric memory and improving the storage density of the ferroelectric memory.

[0098] The present disclosure also provides a method for reading data from a ferroelectric memory, which is applied to the above-mentioned ferroelectric memory. Referring to Figures 3, 5, 10, and 11, the specific structure of the ferroelectric memory is described in the above embodiments and will not be described again here. Referring to Figure 16, the data reading method includes the following steps:

[0099] [Corrected 16.10.2024 according to Rule 91] Step S100: Using bit lines and transistors, the corresponding 2 n The first plates of the -1 ferroelectric capacitors are all charged to a first voltage. The first voltage causes the polarization direction of each ferroelectric capacitor to point to the first plate. When the polarization direction of the ferroelectric capacitor is reversed, the ferroelectric capacitor flows positive charge to the bit line.

[0100] [Corrected 16.10.2024 according to Rule 91] The voltage on the bit line 20 is precharged to the first voltage, the word line 30 and the transistor 11 are turned on, so that the corresponding 2 n The first plates 121 of each of the ferroelectric capacitors 12 are charged to a first voltage, that is, the first plates 121 of these ferroelectric capacitors 12 are all at the first voltage. The first voltage is a low voltage, and the absolute value of the potential difference between the first plate 121 and the second plate 122 is greater than the coercive voltage of each ferroelectric capacitor 12, so that the polarization direction of each ferroelectric capacitor 12 points to the first plate 121.

[0101] [Corrected 16.10.2024 in accordance with Article 91] n -1 Before the first plate 121 of the ferroelectric capacitor 12 is charged, 2 n -1 The polarization direction of the ferroelectric capacitor 12 can have multiple situations, so that 2 n -1 ferroelectric capacitor 12 is in different storage states to store data. n After the first plates 121 of -1 ferroelectric capacitors 12 are charged, the polarization directions of these ferroelectric capacitors 12 all point to the first plates 121. If the polarization direction of each ferroelectric capacitor 12 does not change, then no charge flows from the ferroelectric capacitors 12 to the bit line 20. If the polarization direction of any ferroelectric capacitor 12 is reversed, then during the reversal process, charge flows from the ferroelectric capacitor 12 to the bit line 20, and the amount of positive charge is positively correlated with the number of ferroelectric capacitors 12 that are reversed.

[0102] Step S200: acquiring data in a storage unit according to a change in the charge amount of a bit line, wherein the storage unit stores n-bit data.

[0103] [Corrected 16.10.2024 according to Rule 91] According to the change of the charge amount of the bit line 20, the data in the memory cell 10 can be obtained. n -1 The polarization direction of the ferroelectric capacitor 12 can be determined by 2 n There are storage states, each storage state corresponds to one type of data, and the storage unit 10 can store n bits of data.

[0104] [Corrected 16.10.2024 according to Rule 91] In some examples, as shown in Figure 5, 2 n -1 ferroelectric capacitor 12 is arranged in sequence along the first direction, 2 n -1 first electrode plate 121 forms an integrated structure, 2 n -1 second electrode plate 122 forms an integrated structure, 2 n -1 dielectric layer 123 forms an integral structure, and 2 n The thickness of the dielectric layer 123 is different. To facilitate the description of the data reading process of the ferroelectric memory, n is set to 2, that is, each memory cell 10 has three ferroelectric capacitors 12, the coercive voltages of the three ferroelectric capacitors 12 are 0.5V, 1V, and 1.5V, respectively, and the external voltage of the second plates 122 of the three ferroelectric capacitors 12 is 0V.

[0105] Referring to FIG. 17 , the voltage of bit line 20 is precharged to a first voltage. The absolute value of the difference between the first voltage and each external voltage is greater than the coercive voltage. For example, the first voltage can be -3 V. Word line 30 and transistor 11 are turned on, and the potential of first plates 121 of the three ferroelectric capacitors 12 is all at the first voltage, i.e., -3 V. The potential difference between first plate 121 and second plate 122 is greater than the coercive voltage, and the potential of first plate 121 is lower, so that the polarization direction of the three ferroelectric capacitors 12 is all toward first plate 121.

[0106] 18 , before word line 30 and transistor 11 are turned on, if the polarization directions of the three ferroelectric capacitors 12 all point toward first plate 121, the three ferroelectric capacitors 12 store 00. After word line 30 and transistor 11 are turned on, the polarization directions of the three ferroelectric capacitors 12 do not change, and no charge flows.

[0107] Referring to FIG. 19 , before word line 30 and transistor 11 are turned on, if the polarization directions of two ferroelectric capacitors 12 are both directed toward first plate 121, and the polarization direction of one ferroelectric capacitor 12 is directed toward second plate 122, for example, the polarization direction of the first ferroelectric capacitor 12 is directed toward second plate 122, then all three ferroelectric capacitors 12 store 10. After word line 30 and transistor 11 are turned on, the polarization direction of one ferroelectric capacitor 12 flips, and the first plate 121 of the ferroelectric capacitor 12 changes from positive charge to negative charge, equivalent to two positive charges flowing to bit line 20. The polarization directions of the other two ferroelectric capacitors 12 do not change and do not contribute to the charge flow, resulting in a total of two positive charges flowing to bit line 20.

[0108] Referring to FIG. 20 , before word line 30 and transistor 11 are turned on, if the polarization direction of one ferroelectric capacitor 12 points toward first plate 121, and the polarization directions of two ferroelectric capacitors 12 both point toward second plate 122—for example, if the polarization direction of the third ferroelectric capacitor 12 points toward first plate 121—then all three ferroelectric capacitors 12 store 01. After word line 30 and transistor 11 are turned on, the polarization directions of the two ferroelectric capacitors 12 flip, and the first plates 121 of the two ferroelectric capacitors 12 change from positive to negative, resulting in four equivalent positive charges flowing to bit line 20. The polarization direction of the other ferroelectric capacitor 12 remains unchanged and does not contribute to the charge flow, resulting in a total of four equivalent positive charges flowing to bit line 20.

[0109] Referring to Figure 21 , before word line 30 and transistor 11 are turned on, if the polarization directions of the three ferroelectric capacitors 12 all point toward second plate 122, the three ferroelectric capacitors 12 store 11. After word line 30 and transistor 11 are turned on, the polarization directions of the three ferroelectric capacitors 12 flip, and a total of six equivalent positive charges flow to bit line 20.

[0110] The positive charge flowing into the bit line 20 changes the voltage or current on the bit line 20. The corresponding data can be read according to the change in the charge on the bit line 20. A total of four different storage states can be read, that is, 2 bits of data can be read. After the data is read, it needs to be written back to the ferroelectric capacitor 12.

[0111] [Corrected 16.10.2024 according to Rule 91] In other examples, 2 n -1 ferroelectric capacitor 12 is arranged in sequence along the first direction, 2 n - 1 first electrode plate 121 connected into an integrated structure, 2 n -1 dielectric layer 123 connected into an integrated structure, 2 n-1 second plates 122 are arranged at intervals. To facilitate the description of the data reading process of the ferroelectric memory, n is set to 2, that is, each memory cell 10 has three ferroelectric capacitors 12, the coercive voltage of the three ferroelectric capacitors 12 is 1.5V, and the external voltages of the second plates 122 of the three ferroelectric capacitors 12 are respectively -1V, 0V, and 1V.

[0112] Referring to FIG. 22 , the voltage of bit line 20 is precharged to a first voltage. The absolute value of the potential difference between the first voltage and each external voltage is greater than the coercive voltage. For example, the first voltage can be -3 V. Word line 30 and transistor 11 are turned on, and the potential of first plates 121 of the three ferroelectric capacitors 12 is all at the first voltage, i.e., -3 V. The potential difference between first plate 121 and second plate 122 is greater than the coercive voltage, and the potential of first plate 121 is lower, so that the polarization direction of the three ferroelectric capacitors 12 is all toward first plate 121.

[0113] 23 , before word line 30 and transistor 11 are turned on, if the polarization directions of the three ferroelectric capacitors 12 all point toward first plate 121, the three ferroelectric capacitors 12 store 00. After word line 30 and transistor 11 are turned on, the polarization directions of the three ferroelectric capacitors 12 do not change, and no charge flows.

[0114] Referring to FIG. 24 , before word line 30 and transistor 11 are turned on, if the polarization directions of two ferroelectric capacitors 12 are both directed toward first plate 121, and the polarization direction of one ferroelectric capacitor 12 is directed toward second plate 122, for example, the polarization direction of the first ferroelectric capacitor 12 is directed toward second plate 122, then all three ferroelectric capacitors 12 store 10. After word line 30 and transistor 11 are turned on, the polarization direction of one ferroelectric capacitor 12 flips, and the first plate 121 of the ferroelectric capacitor 12 changes from positive charge to negative charge, equivalent to two positive charges flowing to bit line 20. The polarization directions of the other two ferroelectric capacitors 12 do not change and do not contribute to the charge flow, resulting in a total of two positive charges flowing to bit line 20.

[0115] Referring to FIG. 25 , before word line 30 and transistor 11 are turned on, if the polarization direction of one ferroelectric capacitor 12 points toward first plate 121, and the polarization directions of two ferroelectric capacitors 12 both point toward second plate 122, for example, the polarization direction of the third ferroelectric capacitor 12 points toward first plate 121, then the three ferroelectric capacitors 12 store 01. After word line 30 and transistor 11 are turned on, the polarization directions of the two ferroelectric capacitors 12 flip, and the first plates 121 of the two ferroelectric capacitors 12 change from positive to negative, resulting in four equivalent positive charges flowing to bit line 20. The polarization direction of the other ferroelectric capacitor 12 does not change and does not contribute to the charge flow, resulting in a total of four equivalent positive charges flowing to bit line 20.

[0116] Referring to Figure 26 , before word line 30 and transistor 11 are turned on, if the polarization directions of the three ferroelectric capacitors 12 all point toward second plate 122, the three ferroelectric capacitors 12 store 11. After word line 30 and transistor 11 are turned on, the polarization directions of the three ferroelectric capacitors 12 are reversed, and a total of six equivalent positive charges flow to bit line 20.

[0117] The positive charge flowing into the bit line 20 changes the voltage or current on the bit line 20. The corresponding data can be read according to the change in the charge on the bit line 20. A total of four different storage states can be read, that is, 2 bits of data can be read. After the data is read, it needs to be written back to the ferroelectric capacitor 12.

[0118] [Corrected 16.10.2024 according to Rule 91] In summary, the data reading method of the ferroelectric memory in the embodiment of the present disclosure is applied to the ferroelectric memory of polymorphic storage, each memory cell 10 of the ferroelectric memory includes a transistor 11 and a 2 coupled to the transistor 11. n -1 ferroelectric capacitor 12, n is a positive integer greater than 1. By n -1 The first plates 121 of the ferroelectric capacitors 12 are all charged to a first voltage. The first voltage causes the polarization directions of the ferroelectric capacitors 12 to point to the first plates 121. The polarization directions of the ferroelectric capacitors 12 are reversed to flow out positive charges to the bit lines 20. According to the change in the charge amount of the bit lines 20, the data in the storage unit 10 can be obtained, and the reading of n-bit data can be realized, thereby improving the storage density of the ferroelectric memory.

[0119] The present disclosure also provides a method for writing data into a ferroelectric memory, which is applied to the above-mentioned ferroelectric memory. Referring to Figures 3, 5, 30, and 31, the specific structure of the ferroelectric memory is described in the above embodiments and will not be described again here. Referring to Figure 27, the data writing method may include the following steps:

[0120] [Corrected 16.10.2024 according to Rule 91] Step a: Using bit lines and transistors, the corresponding 2 n - The first plates of one ferroelectric capacitor are charged to a first voltage, where the first voltage causes the polarization directions of the storage capacitors to point toward the first plate, so as to initialize the ferroelectric capacitors.

[0121] [Corrected 16.10.2024 according to Rule 91] The voltage on the bit line 20 is precharged to the first voltage, the word line 30 and the transistor 11 are turned on, so that the corresponding 2 n-1 The first plates 121 of the ferroelectric capacitors 12 are all charged to the first voltage, that is, the potential of the first plates 121 of these ferroelectric capacitors 12 is the first voltage. The first voltage is a low voltage, and the absolute value of the potential difference between the first plate 121 and the second plate 122 is greater than the coercive voltage of each ferroelectric capacitor 12, so that the polarization direction of each ferroelectric capacitor 12 points to the first plate 121, completing 2 n - Initialization of 1 ferroelectric capacitor 12.

[0122] [Corrected 16.10.2024 according to Rule 91] Step b: Apply a write voltage to the bit line, and the memory cell stores data; wherein the write voltage has a value of 2 n The storage unit stores n bits of data, each voltage value corresponds to one type of data, and some voltage values ​​cause the polarization directions of at least some ferroelectric capacitors to flip, and different voltage values ​​cause different numbers of ferroelectric capacitors whose polarization directions flip.

[0123] [Corrected 16.10.2024 according to Article 91] A write voltage is applied to the bit line 20 and a write voltage is applied to the corresponding 2 through the transistor 11. n -1 ferroelectric capacitor 12 writes data to make the memory cell 10 store data. Wherein, the write voltage has 2 n voltage values, each voltage value corresponds to 2 n -1 ferroelectric capacitor 12 has a storage state corresponding to a data. The storage state refers to 2 n -1 polarization state of the ferroelectric capacitor 12, specifically 2 n −1 is the number of ferroelectric capacitors 12 whose polarization direction points to the second electrode plate 122 (or the first electrode plate 121 ).

[0124] [Corrected 16.10.2024 according to Article 91] It is understood that the write voltage of 2 n One of the voltage values ​​makes 2 n -1 ferroelectric capacitors 12 have no polarization direction change, that is, the number of ferroelectric capacitors 12 whose polarization direction is reversed is 0, and the other voltage value makes 2 n -1 The polarization directions of all ferroelectric capacitors 12 are reversed, that is, the number of ferroelectric capacitors 12 whose polarization directions are reversed is 2 n -1. The rest of the voltage values ​​are 2 n -1 ferroelectric capacitor 12 has its polarization direction reversed, and each of the remaining voltage values ​​corresponds to a different number of reversed ferroelectric capacitors 12, ranging from 0 to 2. n Different voltage values ​​cause different numbers of ferroelectric capacitors 12 whose polarization directions are reversed, so that each voltage value corresponds to different data.

[0125] For example, when n is 2, the write voltage has four voltage values, which are the first preset value, the second preset value, the third preset value and the fourth preset value. When the voltage value of the write voltage is the first preset value, the polarization direction of 0 ferroelectric capacitors 12 is reversed. When the voltage value of the write voltage is the second preset value, the polarization direction of 1 ferroelectric capacitor 12 is reversed. When the voltage value of the write voltage is the third preset value, the polarization direction of 2 ferroelectric capacitors 12 is reversed. When the voltage value of the write voltage is the fourth preset value, the polarization direction of 3 ferroelectric capacitors 12 is reversed.

[0126] [Corrected 16.10.2024 according to Article 91] In some examples, 2 n -1 ferroelectric capacitor 12 is arranged in sequence along the first direction, 2 n -1 first electrode plate 121 forms an integrated structure, 2 n -1 second electrode plate 122 forms an integrated structure, 2 n -1 dielectric layer 123 forms an integral structure, and 2 n The thickness of the dielectric layer 123 is different. To facilitate the description of the data writing process of the ferroelectric memory, n is set to 2, that is, each memory cell 10 has three ferroelectric capacitors 12, the coercive voltages of the three ferroelectric capacitors 12 are 0.5V, 1V, and 1.5V, respectively, and the external voltage value of the second plate 122 of the three ferroelectric capacitors 12 is 0V.

[0127] Referring to FIG. 28 , the voltage of bit line 20 is precharged to a first voltage. The absolute value of the difference between the first voltage and each external voltage is greater than the coercive voltage. For example, the first voltage can be -3 V. Word line 30 and transistor 11 are turned on, and the potential of first plates 121 of the three ferroelectric capacitors 12 is all at the first voltage, i.e., -3 V. The potential difference between first plate 121 and second plate 122 is greater than the coercive voltage, and the potential of first plate 121 is lower, so that the polarization direction of the three ferroelectric capacitors 12 is all toward the first plate.

[0128] Referring to FIG. 29 , a write voltage is applied to the bit line 20. When the voltage value of the write voltage is a first preset value, the potentials of the first plates 121 of the three ferroelectric capacitors 12 are all the first preset value, and the potentials of the second plates 122 of the three ferroelectric capacitors 12 are all the voltage value of the external voltage. The absolute value of the difference between the first preset value of each ferroelectric voltage and the voltage value of the external voltage is less than the coercive voltage of the ferroelectric capacitor 12. The polarization directions of the three ferroelectric capacitors 12 all point toward the first plate 121, and the polarization direction does not change, storing data 00. For example, the first preset value is 0V, and the difference between it and the voltage value of the external voltage, 0V, is less than the coercive voltage of each ferroelectric capacitor 12.

[0129] Referring to FIG. 30 , a write voltage is applied to the bit line 20. When the write voltage reaches a second preset value, the potentials of the first plates 121 of the three ferroelectric capacitors 12 are all at the second preset value, and the potentials of the second plates 122 of the three ferroelectric capacitors 12 are all at the external voltage. If the absolute value of the difference between the second preset value and the external voltage is greater than the coercive voltage of only one of the three ferroelectric capacitors 12, the polarization direction of that ferroelectric capacitor 12 is reversed. The polarization directions of the remaining two ferroelectric capacitors 12 remain unchanged, and data 10 is stored. For example, if the second preset value is 1V and the coercive voltage is 0.5V, the polarization direction of the ferroelectric capacitor 12 is reversed, while the polarization directions of the remaining two ferroelectric capacitors 12 remain unchanged.

[0130] Referring to FIG. 31 , a write voltage is applied to the bit line 20. When the write voltage reaches a third preset value, the potentials of the first plates 121 of the three ferroelectric capacitors 12 are all at the third preset value, and the potentials of the second plates 122 of the three ferroelectric capacitors 12 are all at the external voltage. If the absolute value of the difference between the third preset value and the external voltage for two of the three ferroelectric capacitors 12 is greater than the coercive voltage of the ferroelectric capacitor 12, the polarization direction of the ferroelectric capacitor 12 flips, while the polarization direction of the remaining ferroelectric capacitor 12 remains unchanged, storing data 01. For example, if the third preset value is 2V and the coercive voltages are 0.5V and 1V, the polarization direction of the ferroelectric capacitors 12 flips, while the polarization direction of the remaining ferroelectric capacitor 12 remains unchanged.

[0131] Referring to FIG. 32 , when a write voltage is applied to bit line 20 and the write voltage reaches a fourth preset value, the potentials of first plates 121 of the three ferroelectric capacitors 12 all reach the fourth preset value, and the potentials of second plates 122 of the three ferroelectric capacitors 12 all reach the external voltage. When the absolute value of the difference between the fourth preset value and the external voltage of the three ferroelectric capacitors 12 is greater than the coercive voltage, the polarization directions of the three ferroelectric capacitors 12 flip, storing data 11. For example, when the third preset value is 3V, the polarization directions of ferroelectric capacitors 12 with coercive voltages of 0.5V, 1V, and 1.5V flip.

[0132] [Corrected 16.10.2024 according to Rule 91] In other examples, 2 n -1 ferroelectric capacitor 12 is arranged in sequence along the first direction, 2 n - 1 first electrode plate 121 connected into an integrated structure, 2 n -1 dielectric layer 123 connected into an integrated structure, 2 n-1 second plates 122 are arranged at intervals. To facilitate the description of the data writing process of the ferroelectric memory, n is set to 2, that is, each memory cell 10 has three ferroelectric capacitors 12, the coercive voltage of the three ferroelectric capacitors 12 is 1.5V, and the external voltages of the second plates 122 of the three ferroelectric capacitors 12 are respectively -1V, 0V, and 1V.

[0133] Referring to FIG. 33 , the voltage of bit line 20 is precharged to a first voltage. The absolute value of the potential difference between the first voltage and each external voltage is greater than the coercive voltage. For example, the first voltage can be -3 V. Word line 30 and transistor 11 are turned on, and the potential of first plates 121 of the three ferroelectric capacitors 12 is all at the first voltage, i.e., -3 V. The potential difference between first plate 121 and second plate 122 is greater than the coercive voltage, and the potential of first plate 121 is lower, so that the polarization direction of the three ferroelectric capacitors 12 is all toward first plate 121.

[0134] Referring to FIG. 34 , a write voltage is applied to the bit line 20. When the write voltage has a first preset value, the potentials of the first plates 121 of the three ferroelectric capacitors 12 are all at the first preset value, and the potentials of the second plates 122 of the three ferroelectric capacitors 12 are all at the voltage value of the external voltage, which has different voltage values. The absolute value of the difference between the first preset value of each ferroelectric voltage and the voltage value of the external voltage is less than 1.5V, that is, less than the coercive voltage of the ferroelectric capacitor 12. The polarization directions of the three ferroelectric capacitors 12 all point toward the first plate 121, and the polarization direction does not change, storing data 00. For example, the first preset value is 0V, and the absolute value of the difference between the first preset value and -1V, 0V, and 1V is less than 1.5V.

[0135] Referring to FIG. 35 , a write voltage is applied to the bit line 20. When the write voltage has a second preset value, the potentials of the first plates 121 of the three ferroelectric capacitors 12 are all at the second preset value, and the potentials of the second plates 122 of the three ferroelectric capacitors 12 are all at the voltage value of the external voltage. If the absolute value of the difference between the second preset value and the voltage value of the external voltage is greater than the coercive voltage of only one of the three ferroelectric capacitors 12, the polarization direction of that ferroelectric capacitor 12 is reversed. The polarization directions of the remaining two ferroelectric capacitors 12 remain unchanged, and data 10 is stored. For example, if the second preset value is 1V and the external voltage has a voltage value of -1V, the polarization direction of the ferroelectric capacitor 12 is reversed, while the polarization directions of the remaining two ferroelectric capacitors 12 remain unchanged.

[0136] Referring to FIG36 , a write voltage is applied to the bit line 20. When the write voltage has a third preset value, the potentials of the first plates 121 of the three ferroelectric capacitors 12 are all at the third preset value, and the potentials of the second plates 122 of the three ferroelectric capacitors 12 are all at the voltage value of the external voltage. If the absolute value of the difference between the third preset value and the voltage value of the external voltage for two of the three ferroelectric capacitors 12 is greater than the coercive voltage of the ferroelectric capacitor 12, the polarization direction of the ferroelectric capacitor 12 is reversed, while the polarization direction of the remaining ferroelectric capacitor 12 remains unchanged, storing data 01. For example, if the third preset value is 2V, the polarization directions of the ferroelectric capacitors 12 with the external voltage values ​​of -1V and 0V are both reversed, while the polarization direction of the ferroelectric capacitor 12 with the external voltage value of 1V remains unchanged.

[0137] Referring to FIG. 37 , when a write voltage is applied to bit line 20 and the write voltage reaches a fourth preset value, the potentials of first plates 121 of the three ferroelectric capacitors 12 all reach the fourth preset value, and the potentials of second plates 122 of the three ferroelectric capacitors 12 all reach the external voltage. When the absolute value of the difference between the fourth preset value and the external voltage of the three ferroelectric capacitors 12 is greater than the coercive voltage, the polarization directions of the three ferroelectric capacitors 12 flip, and data 11 is stored. For example, when the third preset value is 3V, the polarization directions of the ferroelectric capacitors 12 flip when the external voltage reaches -1V, 0V, and 1V.

[0138] [Corrected 16.10.2024 according to Rule 91] In summary, the data writing method of the ferroelectric memory in the embodiment of the present disclosure is applied to the ferroelectric memory of polymorphic storage, each memory cell 10 of the ferroelectric memory includes a transistor 11 and a 2 coupled to the transistor 11. n -1 ferroelectric capacitor 12, n is a positive integer greater than 1. By n The first plates 121 of the ferroelectric capacitors 12 are all charged to a first voltage. The first voltage causes the polarization direction of each ferroelectric capacitor 12 to point toward the first plate 121, thereby initializing each ferroelectric capacitor 12. Different write voltage values ​​are then used, with each voltage value corresponding to a type of data. Some voltage values ​​cause the polarization direction of at least some of the ferroelectric capacitors 12 to flip, and different voltage values ​​cause different numbers of ferroelectric capacitors 12 to flip their polarization directions. This allows writing of n-bit data, thereby improving the storage density of the ferroelectric memory.

[0139] FIG38 is a schematic diagram of the structure of an electronic device according to an embodiment of the present disclosure. Referring to FIG38 , an embodiment of the present disclosure further provides an electronic device 1 comprising a processing device 2 and a storage device 3 electrically connected to the processing device 2, wherein the storage device 3 comprises a ferroelectric memory device as described in any of the above embodiments. The electronic device 1 may be a terminal device such as a mobile phone, a tablet computer, or a smart bracelet, or may be a personal computer (PC), a server, or a workstation. The storage function in the electronic device 1 may be implemented using a ferroelectric random access memory (FRAM) storage device 3.

[0140] In this specification, each embodiment or implementation method is described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same or similar parts between the embodiments can be referenced to each other. The descriptions with reference to the terms "one embodiment", "some embodiments", "illustrative embodiments", "example", "specific example", or "some examples" mean that the specific features, structures, materials or characteristics described in conjunction with the embodiments or examples are included in at least one embodiment or example of the present disclosure. In this specification, the schematic representation of the above terms does not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described can be combined in any one or more embodiments or examples in a suitable manner.

[0141] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present disclosure, rather than to limit them. Although the present disclosure has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or replace some or all of the technical features therein with equivalents. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present disclosure.

Claims

1. [Corrected 16.10.2024 in accordance with Rule 91] A ferroelectric memory, include: A memory cell array, the memory cell array comprising a plurality of memory cells (10) arranged in an array, each of the memory cells (10) storing n-bit data, wherein each of the memory cells (10) comprises: a transistor (11) and 2 n - 1 ferroelectric capacitor (12), wherein n is a positive integer greater than 1; A plurality of word lines (30), each of the word lines (30) being coupled to the memory cells (10) arranged in a row in the memory cell array; A plurality of bit lines (20), each of the bit lines (20) is coupled to the memory cells (10) arranged in columns in the memory cell array.

2. [Corrected 16.10.2024 in accordance with Rule 91] A ferroelectric memory according to claim 1, in, Each of the ferroelectric capacitors (12) comprises a first electrode plate (121), a second electrode plate (122) arranged opposite to each other, and a dielectric layer (123) filled between the first electrode plate (121) and the second electrode plate (122); 2 n - 1 said ferroelectric capacitors are arranged in sequence along a first direction, 2 n - 1 said first electrode plate (121) is connected into an integrated structure, 2 n - 1 said second electrode plate (122) connected into an integrated structure, 2 n -1 said dielectric layers (123) are connected into an integrated structure, and each of said dielectric layers (123) has a different thickness.

3. [Corrected 16.10.2024 in accordance with Rule 91] A ferroelectric memory device according to claim 2, in, Along the first direction, 2 n - The thickness of the dielectric layer (123) of each of the ferroelectric capacitors (12) increases sequentially.

4. [Corrected 16.10.2024 in accordance with Rule 91] A ferroelectric memory according to claim 2 or 3, in, Along the first direction, 2 n - The coercive voltages of the ferroelectric capacitors (12) are arranged in an arithmetic progression.

5. [Corrected 16.10.2024 in accordance with Rule 91] A ferroelectric memory according to any one of claims 2 to 4, in, 2 n -1 the second electrode plate (122) has the same potential, 2 n -1 first electrode plate (121) is connected to one of the source and drain of the corresponding transistor (11), the other of the source and drain of the transistor (11) is connected to the corresponding bit line (20), and the gate of the transistor (11) is connected to the corresponding word line (30).

6. [Corrected 16.10.2024 in accordance with Rule 91] A ferroelectric memory according to any one of claims 2 to 5, in, 2 n - one of the second pole plates (122) is connected to form the integrated structure and connected to the same power line (PL), 2 n -1 the second electrode plates (122) have the same potential.

7. [Corrected 16.10.2024 in accordance with Rule 91] A ferroelectric memory device according to claim 1, in, Each of the ferroelectric capacitors (12) comprises a first electrode plate (121), a second electrode plate (122) arranged opposite to each other, and a dielectric layer (123) filled between the first electrode plate (121) and the second electrode plate (122); 2 n - 1 said ferroelectric capacitors (12) are arranged in sequence along a first direction, 2 n - 1 said first electrode plate (121) is connected into an integrated structure, 2 n - 1 said dielectric layer (123) is connected into an integral structure, 2 n - one of the second electrode plates (122) is arranged at intervals.

8. [Corrected 16.10.2024 in accordance with Rule 91] A ferroelectric memory device according to claim 7, in, 2 n -1 the thickness of the dielectric layer (123) is equal, so that 2 n - The coercive voltages of the ferroelectric capacitors (12) are the same.

9. [Corrected 16.10.2024 in accordance with Rule 91] A ferroelectric memory according to claim 7 or 8, in, 2 n - The lengths of the second electrode plates (122) are the same.

10. [Corrected 16.10.2024 in accordance with Rule 91] A ferroelectric memory according to any one of claims 7 to 9, in, 2 n -1 the second electrode plates (122) have different potentials, 2 n -1 first electrode plate (121) is connected to one of the source and drain of the corresponding transistor (11), the other of the source and drain of the transistor (11) is connected to the corresponding bit line (20), and the gate of the transistor (11) is connected to the corresponding word line (30).

11. [Corrected 16.10.2024 in accordance with Rule 91] A ferroelectric memory according to any one of claims 7 to 10, in, 2 n - 1 of the second electrodes (122) are connected to different power lines respectively, 2 n The potentials of the second electrodes (122) are different.

12. The ferroelectric memory according to any one of claims 2 to 11, in, The second electrode plate (122), the dielectric layer (123), and the first electrode plate (121) are stacked in sequence to form a planar capacitor.

13. The ferroelectric memory according to any one of claims 1 to 12, in, The transistor (11) is a thin film transistor.

14. [Corrected 16.10.2024 according to Rule 91] A method for reading data from a ferroelectric memory, applied to the ferroelectric memory according to any one of claims 1 to 13, wherein the method include: By using the bit line (20) and the transistor (11), the corresponding 2 n - the first plates (121) of a ferroelectric capacitor (12) are all charged to a first voltage, the first voltage causing the polarization direction of each ferroelectric capacitor (12) to point toward the first plate (121), and when the polarization direction of the ferroelectric capacitor (12) is reversed, the ferroelectric capacitor (12) flows positive charge to the bit line (20); Data in the storage unit (10) is obtained according to a change in the amount of charge of the bit line (20), wherein the storage unit stores n bits of the data.

15. [Corrected 16.10.2024 according to Rule 91] A method for reading data from a ferroelectric memory according to claim 14, in, 2 n - a ferroelectric capacitor (12) is arranged in sequence along a first direction, 2 n - a first electrode plate (121) forming an integrated structure; 2 n -1 second electrode plate (122) forms an integral structure and is connected to the same power line (PL), 2 n - one of the second electrodes (122) has the same potential; 2 n -1 dielectric layer (123) forms an integral structure, and 2 n - The thickness of one dielectric layer (123) is different.

16. [Corrected 16.10.2024 according to Rule 91] A method for reading data from a ferroelectric memory according to claim 14, in, 2 n - a ferroelectric capacitor (12) is arranged in sequence along a first direction, 2 n - a first electrode plate (121) forming an integrated structure; 2 n - a dielectric layer (123) forming an integral structure; 2 n - 1 second electrode plates (122) are arranged at intervals and connected to different power lines respectively, 2 n The potentials of the second electrodes (122) are different.

17. [Corrected 16.10.2024 according to Rule 91] A method for writing data into a ferroelectric memory, applied to the ferroelectric memory according to any one of claims 1 to 13, wherein the method for writing data into a ferroelectric memory is: include: By using the bit line (20) and the transistor (11), the corresponding 2 n - charging a first electrode plate (121) of a ferroelectric capacitor (12) to a first voltage, wherein the first voltage causes the polarization direction of each storage capacitor (12) to point toward the first electrode plate (121), so as to initialize each ferroelectric capacitor (12); A write voltage is applied to the bit line (20), and the memory cell (10) stores data; wherein the write voltage has a value of 2 n A voltage value is stored in the storage unit (10) and n bits of data are stored. Each voltage value corresponds to a type of data. Some of the voltage values ​​cause the polarization directions of at least some of the ferroelectric capacitors to flip, and different voltage values ​​cause different numbers of the ferroelectric capacitors to flip their polarization directions.

18. [Corrected 16.10.2024 according to Rule 91] A method for writing data into a ferroelectric memory according to claim 17, in, 2 n - a ferroelectric capacitor (12) is arranged in sequence along a first direction, 2 n - a first electrode plate (121) forming an integrated structure; 2 n -1 second electrode plate (122) forms an integral structure and is connected to the same power line (PL), 2 n - one of the second electrodes (122) has the same potential; 2 n -1 dielectric layer (123) forms an integral structure, and 2 n - One dielectric layer (123) has a different thickness.

19. [Corrected 16.10.2024 according to Rule 91] A method for writing data into a ferroelectric memory according to claim 17, in, 2 n - a ferroelectric capacitor (12) is arranged in sequence along a first direction, 2 n - a first electrode plate (121) forming an integrated structure; 2 n - a dielectric layer (123) forming an integral structure; 2 n - 1 second electrode plates (122) are arranged at intervals and connected to different power lines respectively, 2 n The potentials of the second electrodes (122) are different.

20. An electronic device (1), include: Processing device (2); as well as A memory device (3) electrically connected to the processing device (2), wherein the memory device (3) comprises the ferroelectric memory according to any one of claims 1 to 13.

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