Display substrate and display device

Abstract

A display substrate, comprising: a base, a plurality of first light-emitting units and a plurality of second light-emitting units which are located in a first display region, a plurality of first pixel circuits located in the first display region, and a plurality of second pixel circuits located in a second display region. Each first light-emitting unit comprises at least one first light-emitting element. Each second light-emitting unit comprises at least one second light-emitting element. The at least one first light-emitting unit is adjacent to the at least one second light-emitting unit. At least one first pixel circuit is electrically connected to the at least one first light-emitting element and is configured to drive the at least one first light-emitting element to emit light. At least one second pixel circuit is electrically connected to the at least one second light-emitting element and is configured to drive the at least one second light-emitting element to emit light.

Description

Display substrate and display device

[0001] This application claims priority to the Chinese patent application filed with the China Patent Office on June 16, 2023, with application number 202310722592.7 and invention name “Display Substrate and Display Device”, the contents of which should be understood as incorporated into this application by reference. Technical Field

[0002] This article relates to but is not limited to the field of display technology, and in particular to a display substrate and a display device. Background Art

[0003] Organic light-emitting diodes (OLEDs) and quantum-dot light-emitting diodes (QLEDs) are active light-emitting display devices with the advantages of self-luminescence, wide viewing angle, high contrast, low power consumption, extremely high response speed, light weight, flexibility and low cost.

[0004] Summary of the Invention

[0005] The following is a summary of the subject matter described in detail herein. This summary is not intended to limit the scope of the claims.

[0006] Embodiments of the present disclosure provide a display substrate and a display device.

[0007] On the one hand, this embodiment provides a display substrate, comprising: a substrate, a plurality of first light-emitting units, a plurality of second light-emitting units, a plurality of first pixel circuits, and a plurality of second pixel circuits. The substrate comprises a first display area and a second display area located at least on one side of the first display area. The plurality of first light-emitting units and the plurality of second light-emitting units are located in the first display area; the first light-emitting unit comprises at least one first light-emitting element, and the second light-emitting unit comprises at least one second light-emitting element; the first light-emitting unit is adjacent to the at least one second light-emitting unit. The plurality of first pixel circuits are located in the first display area; at least one first pixel circuit among the plurality of first pixel circuits is electrically connected to the at least one first light-emitting element and is configured to drive the at least one first light-emitting element to emit light. The plurality of second pixel circuits are located in the second display area; at least one second pixel circuit among the plurality of second pixel circuits is electrically connected to the at least one second light-emitting element and is configured to drive the at least one second light-emitting element to emit light.

[0008] In some exemplary embodiments, the plurality of first light emitting units and the plurality of second light emitting units are spaced apart along at least one of a first direction and a second direction; and the first direction intersects the second direction.

[0009] In some exemplary embodiments, in the first direction, one first light emitting unit and one second light emitting unit are arranged at intervals; in the second direction, one first light emitting unit and one second light emitting unit are arranged at intervals.

[0010] In some exemplary embodiments, the plurality of first light-emitting units include: a plurality of columns of first light-emitting units, each column of first light-emitting units including a plurality of first light-emitting units sequentially arranged along the second direction. The plurality of second light-emitting units include: a plurality of columns of second light-emitting units, each column of second light-emitting units including a plurality of second light-emitting units sequentially arranged along the second direction. In the first direction, a column of first light-emitting units and a column of second light-emitting units are alternately arranged.

[0011] In some exemplary embodiments, the plurality of first light-emitting units include multiple rows of first light-emitting units, each row of first light-emitting units including multiple first light-emitting units sequentially arranged along the first direction. The plurality of second light-emitting units include multiple rows of second light-emitting units, each row of second light-emitting units including multiple second light-emitting units sequentially arranged along the first direction. In the second direction, a row of first light-emitting units and a row of second light-emitting units are alternately arranged.

[0012] In some exemplary embodiments, the first light emitting unit and the second light emitting unit adjacent to each other in the first direction are aligned, and the first light emitting unit and the second light emitting unit adjacent to each other in the second direction are aligned; or, the first light emitting unit and the second light emitting unit adjacent to each other in the second direction are misaligned.

[0013] In some exemplary embodiments, a ratio of light emitting areas of the second light emitting element and the first light emitting element emitting light of the same color is less than 1.

[0014] In some exemplary embodiments, the number of first light-emitting elements included in the at least one first light-emitting unit is the same as the number of second light-emitting elements included in the at least one second light-emitting unit.

[0015] In some exemplary embodiments, the at least one first light-emitting unit includes the following four first light-emitting elements: one first light-emitting element that emits light of a first color, one first light-emitting element that emits light of a second color, and two first light-emitting elements that emit light of a third color. The at least one second light-emitting unit includes the following four second light-emitting elements: one second light-emitting element that emits light of the first color, one second light-emitting element that emits light of the second color, and two second light-emitting elements that emit light of the third color.

[0016] In some exemplary embodiments, the plurality of first light-emitting elements and the plurality of second light-emitting elements in the first display area are arranged in multiple rows and columns. In the at least one first light-emitting unit, the two first light-emitting elements emitting third color light are arranged in the same column, the first light-emitting element emitting first color light and the first light-emitting element emitting second color light are arranged in the same column, and the four first light-emitting elements of the first light-emitting unit are arranged in different rows. In the at least one second light-emitting unit, the two second light-emitting elements emitting third color light are arranged in the same column, the second light-emitting element emitting first color light and the second light-emitting element emitting second color light are arranged in the same column, and the four first light-emitting elements of the second light-emitting unit are arranged in different rows.

[0017] In some exemplary embodiments, the plurality of first light-emitting elements and the plurality of second light-emitting elements in the first display area are arranged in multiple rows and columns. In the at least one first light-emitting unit, the two first light-emitting elements emitting third color light are arranged in the same row, the first light-emitting element emitting first color light and the first light-emitting element emitting second color light are arranged in the same row, and the four first light-emitting elements of the first light-emitting unit are arranged in different columns. In the at least one second light-emitting unit, the two second light-emitting elements emitting third color light are arranged in the same row, the first light-emitting element emitting first color light and the second light-emitting element emitting second color light are arranged in the same row, and the four second light-emitting elements of the second light-emitting unit are arranged in different columns.

[0018] In some exemplary embodiments, the four first light-emitting elements in the first light-emitting unit are electrically connected to four first pixel circuits in a one-to-one correspondence, and the four first pixel circuits are arranged sequentially along the first direction, and the orthographic projection of each first pixel circuit on the substrate at least partially overlaps with the orthographic projection of the connected first light-emitting element on the substrate.

[0019] In some exemplary embodiments, the four first pixel circuits are symmetrically arranged about a first center line of the four first pixel circuits along the first direction, the first first pixel circuit and the second first pixel circuit among the four first pixel circuits are symmetrically arranged about a second center line of the two first pixel circuits along the first direction, and the third first pixel circuit and the fourth first pixel circuit are symmetrically arranged about a third center line of the two first pixel circuits along the first direction.

[0020] In some exemplary embodiments, the four first pixel circuits are electrically connected to first power lines, and the first power lines are arranged in a grid shape in the first display area.

[0021] In some exemplary embodiments, in a direction perpendicular to a display substrate, the display substrate includes: a circuit structure layer located on the substrate; the circuit structure layer includes the plurality of first pixel circuits and the plurality of second pixel circuits; each of the plurality of first pixel circuits and the plurality of second pixel circuits includes at least one first-type transistor, at least one second-type transistor, and a storage capacitor. The circuit structure layer includes: a first semiconductor layer, a first conductive layer, a second conductive layer, a second semiconductor layer, a third conductive layer, a fourth conductive layer, a fifth conductive layer, and a sixth conductive layer disposed on the substrate. The first semiconductor layer includes at least an active layer of the first-type transistor of the pixel circuit; the first conductive layer includes at least a gate electrode of the first-type transistor of the pixel circuit and a first electrode of the storage capacitor; the second conductive layer includes at least a second electrode of the storage capacitor of the pixel circuit; the second semiconductor layer includes at least an active layer of the second-type transistor of the pixel circuit; the third conductive layer includes at least a gate electrode of the second-type transistor of the pixel circuit; the fourth conductive layer includes at least a plurality of connection electrodes; the fifth conductive layer includes at least a plurality of data lines; and the sixth conductive layer includes at least a first power line.

[0022] In some exemplary embodiments, the first display area includes: a plurality of first sub-regions and a plurality of second sub-regions; at least one of the plurality of first sub-regions is provided with at least one first light-emitting unit, and at least one of the plurality of second sub-regions is provided with at least one second light-emitting unit. The second conductive layer further includes: a first scan line, a light emission control line, a first reset control line, and a second reset control line electrically connected to the first pixel circuit; the first scan line, the light emission control line, the first reset control line, and the second reset control line extend along a first direction. In a second direction, the first scan line and the first reset control line bypass one side of the second sub-region, while the light emission control line and the second reset control line bypass the other side of the second sub-region; the second direction intersects the first direction.

[0023] In some exemplary embodiments, the first display area includes: a plurality of first sub-regions and a plurality of second sub-regions; at least one first sub-region of the plurality of first sub-regions is provided with at least one first light-emitting unit, and at least one second sub-region of the plurality of second sub-regions is provided with at least one second light-emitting unit. The third conductive layer further includes: a first initial signal line, a second initial signal line, a third initial signal line, and a second scan line electrically connected to the first pixel circuit; the first initial signal line, the second initial signal line, the third initial signal line, and the second scan line extend along a first direction. In a second direction, the first initial signal line and the second scan line bypass one side of the second sub-region, while the second initial signal line and the third initial signal line bypass the other side of the second sub-region; the second direction intersects the first direction.

[0024] In some example embodiments, the ratio of the number of the first light emitting units to the number of the second light emitting units in the first display area is 0.8 to 1.2.

[0025] In some exemplary embodiments, the light transmittance of the first display area is greater than the light transmittance of the second display area. The display substrate further includes: a plurality of third light-emitting elements and a plurality of third pixel circuits located in the second display area, at least one of the plurality of third pixel circuits being electrically connected to at least one of the plurality of third light-emitting elements and configured to drive the at least one third light-emitting element to emit light. The plurality of second pixel circuits are spaced apart between the plurality of third pixel circuits.

[0026] In some exemplary embodiments, the orthographic projection of the at least one first pixel circuit on the substrate overlaps with the orthographic projection of the at least one first light-emitting element on the substrate. The at least one second pixel circuit is electrically connected to the at least one second light-emitting element via at least one conductive connecting line; and the orthographic projection of the at least one second pixel circuit on the substrate does not overlap with the orthographic projection of the at least one second light-emitting element on the substrate.

[0027] In some exemplary embodiments, an orthographic projection of the at least one conductive connection line on the substrate overlaps with an orthographic projection of the at least one first pixel circuit on the substrate.

[0028] On the other hand, this embodiment provides a display device, comprising the display substrate as described above, and a sensor located on a non-display surface side of the display substrate, wherein the orthographic projection of the sensor on the display substrate at least partially overlaps with the first display area of ​​the display substrate.

[0029] Still other aspects will become apparent upon reading and understanding the accompanying drawings and detailed description.

[0030] Summary of the Figures

[0031] The accompanying drawings are used to provide an understanding of the technical solution of the present application and constitute a part of the specification. Together with the embodiments of the present application, they are used to explain the technical solution of the present application and do not constitute a limitation on the technical solution of the present application.

[0032] FIG1 is a schematic diagram of a display substrate according to at least one embodiment of the present disclosure;

[0033] FIG2 is an equivalent circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0034] FIG3 is a timing diagram of the operation of the pixel circuit provided in FIG2 ;

[0035] 4A and 4B are partial schematic diagrams of a first display area according to at least one embodiment of the present disclosure;

[0036] FIG5 is a schematic diagram showing the connection relationship between a light-emitting element and a pixel circuit according to at least one embodiment of the present disclosure;

[0037] FIG6 is a partial top view of the first display area according to at least one embodiment of the present disclosure;

[0038] FIG7A is a schematic diagram of the first display area after the first semiconductor layer is formed in FIG6 ;

[0039] FIG7B is a schematic diagram of a first sub-region in FIG7A ;

[0040] FIG8A is a schematic diagram of the first display area after the first conductive layer is formed in FIG6 ;

[0041] FIG8B is a schematic diagram of the first conductive layer in FIG8A ;

[0042] FIG8C is a schematic diagram of a first sub-region in FIG8A ;

[0043] FIG9A is a schematic diagram of the first display area after the second conductive layer is formed in FIG6 ;

[0044] FIG9B is a schematic diagram of the second conductive layer in FIG9A ;

[0045] FIG9C is a schematic diagram of a first sub-region in FIG9A ;

[0046] FIG10A is a schematic diagram of the first display region after the second semiconductor layer is formed in FIG6 ;

[0047] FIG10B is a schematic diagram of the second semiconductor layer in FIG10A ;

[0048] FIG10C is a schematic diagram of a first sub-region in FIG10A ;

[0049] FIG11A is a schematic diagram of the first display area after the third conductive layer is formed in FIG6 ;

[0050] FIG11B is a schematic diagram of the third conductive layer in FIG11A ;

[0051] FIG11C is a schematic diagram of a first sub-region in FIG11A ;

[0052] FIG12 is a schematic diagram of a first sub-region after forming a fifth insulating layer in FIG6 ;

[0053] FIG13A is a schematic diagram of the first display area after the fourth conductive layer is formed in FIG6;

[0054] FIG13B is a schematic diagram of the fourth conductive layer in FIG13A;

[0055] FIG13C is a schematic diagram of a first sub-region in FIG13A ;

[0056] FIG14 is a schematic diagram of a first sub-region after forming a seventh insulating layer in FIG6 ;

[0057] FIG15A is a schematic diagram of the first display area after the fifth conductive layer is formed in FIG6 ;

[0058] FIG15B is a schematic diagram of the fifth conductive layer in FIG15A;

[0059] FIG15C is a schematic diagram of a first sub-region in FIG15A;

[0060] FIG16 is a schematic diagram of a first sub-region after the eighth insulating layer is formed in FIG6 ;

[0061] FIG17A is a schematic diagram of the first display area after the sixth conductive layer is formed in FIG6 ;

[0062] FIG17B is a schematic diagram of the sixth conductive layer in FIG17A;

[0063] FIG17C is a schematic diagram of a first sub-region in FIG17A ;

[0064] FIG18 is a schematic diagram of the first display area after the ninth insulating layer is formed in FIG6 ;

[0065] FIG19A is a schematic diagram of the first display area after the conductive connection layer is formed in FIG6 ;

[0066] FIG19B is a schematic diagram of the conductive connection layer in FIG19A;

[0067] FIG20 is a schematic diagram of the first display area after the anode layer is formed in FIG6;

[0068] FIG21 is another exemplary diagram of the first display area according to at least one embodiment of the present disclosure;

[0069] FIG22 is another exemplary diagram of the first display area according to at least one embodiment of the present disclosure;

[0070] FIG23 is another exemplary diagram of the first display area according to at least one embodiment of the present disclosure;

[0071] FIG24 is another exemplary diagram of the first display area according to at least one embodiment of the present disclosure;

[0072] FIG25 is another exemplary diagram of the first display area according to at least one embodiment of the present disclosure;

[0073] FIG26 is another exemplary diagram of the first display area according to at least one embodiment of the present disclosure;

[0074] FIG27 is another exemplary diagram of the first display area according to at least one embodiment of the present disclosure;

[0075] FIG28 is another exemplary diagram of the first display area according to at least one embodiment of the present disclosure;

[0076] FIG29 is another exemplary diagram of the first display area according to at least one embodiment of the present disclosure;

[0077] FIG30 is another exemplary diagram of the first display area according to at least one embodiment of the present disclosure;

[0078] FIG31 is another exemplary diagram of the first display area according to at least one embodiment of the present disclosure;

[0079] FIG32 is another exemplary diagram of the first display area according to at least one embodiment of the present disclosure;

[0080] FIG33 is another exemplary diagram of the first display area according to at least one embodiment of the present disclosure;

[0081] FIG34 is another exemplary diagram of the first display area according to at least one embodiment of the present disclosure;

[0082] FIG35 is another exemplary diagram of the first display area according to at least one embodiment of the present disclosure;

[0083] FIG36 is a schematic diagram of a display device according to at least one embodiment of the present disclosure.

[0084] Details

[0085] The embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings. The embodiments can be implemented in a variety of different forms. A person skilled in the art can easily understand that the method and content can be transformed into other forms without departing from the purpose and scope of the present disclosure. Therefore, the present disclosure should not be interpreted as being limited to the contents described in the following embodiments. In the absence of conflict, the embodiments and features in the embodiments of the present disclosure can be combined with each other in any manner.

[0086] In the drawings, the size of one or more components, layer thicknesses, or regions may be exaggerated for clarity. Therefore, one embodiment of the present disclosure is not necessarily limited to these dimensions, and the shapes and sizes of one or more components in the drawings do not reflect true proportions. Furthermore, the drawings schematically illustrate idealized examples, and one embodiment of the present disclosure is not limited to the shapes or values ​​shown in the drawings.

[0087] In this specification, ordinal numbers such as "first," "second," and "third" are provided to avoid confusion among constituent elements, and are not intended to limit the number. "Multiple" in this disclosure means two or more.

[0088] In this specification, for convenience, words and phrases indicating orientation or positional relationships, such as "middle," "upper," "lower," "front," "back," "vertical," "horizontal," "top," "bottom," "inside," and "outside," are used to illustrate the positional relationships of constituent elements with reference to the accompanying drawings. This is merely for the purpose of facilitating the description of this specification and simplifying the description, and is not intended to indicate or imply that the device or element referred to must have a specific orientation, be constructed, or operate in a specific orientation. Therefore, they should not be construed as limitations on the present disclosure. The positional relationships of constituent elements may be appropriately changed depending on the orientation of the constituent elements being described. Therefore, the present disclosure is not limited to the words and phrases described in the specification and may be appropriately replaced depending on the circumstances.

[0089] In this specification, unless otherwise specified or limited, the terms "mounted," "connected," and "connected" should be understood broadly. For example, they can refer to fixed connections, removable connections, or integral connections; they can refer to mechanical connections or connections; they can refer to direct connections, indirect connections through intermediaries, or internal communication between two components. Those skilled in the art will understand the meaning of these terms in this disclosure based on the circumstances.

[0090] In this specification, "electrically connected" includes components connected together via an element having some electrical function. There are no particular limitations on the "element having some electrical function" as long as it enables transmission of electrical signals between the connected components. Examples of "element having some electrical function" include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other components with multiple functions.

[0091] In this specification, a transistor refers to a device that includes at least three terminals: a gate, a drain, and a source. A transistor has a channel region between the drain (drain electrode terminal, drain region, or drain electrode) and the source (source electrode terminal, source region, or source electrode), and current can flow through the drain, channel region, and source. In this specification, the channel region refers to the region through which current primarily flows.

[0092] In this specification, the first electrode can be referred to as the drain and the second electrode as the source, or vice versa. The functions of "source" and "drain" are sometimes interchanged when using transistors with opposite polarity or when the direction of current changes during circuit operation. Therefore, in this specification, the terms "source" and "drain" can be interchanged. Furthermore, the gate electrode can also be referred to as the control electrode.

[0093] In this specification, "parallel" refers to a state where the angle formed by two straight lines is greater than -10° and less than 10°, and thus also includes a state where the angle is greater than -5° and less than 5°. Furthermore, "perpendicular" refers to a state where the angle formed by two straight lines is greater than 80° and less than 100°, and thus also includes a state where the angle is greater than 85° and less than 95°.

[0094] In this specification, circles, ellipses, triangles, rectangles, trapezoids, pentagons or hexagons are not in the strict sense, but may be approximate circles, approximate ellipses, approximate triangles, approximate rectangles, approximate trapezoids, approximate pentagons or approximate hexagons, etc. There may be some small deformations caused by tolerances, such as chamfers, arc edges and deformations.

[0095] The term "light transmittance" in this disclosure refers to the ability of light to pass through a medium, and is the percentage of the luminous flux passing through a transparent or translucent body to the incident luminous flux.

[0096] In the present disclosure, "about" and "substantially" are used without strict limits and allow for process and measurement errors. In the present disclosure, "substantially the same" means that the numerical values ​​differ by less than 10%.

[0097] In this disclosure, "A extends along direction B" means that A may include a main portion and a secondary portion connected to the main portion, the main portion being a line, line segment, or strip, extending along direction B, and the length of the main portion extending along direction B being greater than the length of the secondary portion extending along other directions. In this disclosure, "A extends along direction B" means "the main portion of A extends along direction B."

[0098] With the continuous development of display technology, cameras are usually installed on display devices to meet the needs of shooting or face recognition. In order to maximize the screen-to-body ratio, technologies such as bangs screen, water drop screen, and hollowing out in the screen have appeared one after another. These technologies are achieved by making holes in part of the display area and placing a camera below the hole area to reduce the area occupied by the camera, thereby increasing the screen-to-body ratio. However, the above technologies require digging out part of the display area, which will cause part of the display image to be unable to be displayed, and the screen-to-body ratio cannot be further increased. In order to avoid punching holes in the display area and to make a true full screen possible while ensuring the practicality of the display substrate, the pixel circuit external method or the pixel circuit internal method is usually adopted in the camera area under the screen.

[0099] The external pixel circuit method involves placing the pixel circuits connected to the light-emitting elements in the under-screen camera area within the normal display area. By separating the light-emitting elements and pixel circuits, the light transmittance of the under-screen camera area is improved. Since the under-screen camera area lacks pixel circuits, it lacks any other light-shielding layers besides the anodes of the light-emitting elements, resulting in higher light transmittance. However, with this method, the pixel circuits and light-emitting elements must be electrically connected via conductive wires. Limited by the space available for these wires, the size (e.g., aperture) of the under-screen camera area of ​​the display substrate using the external pixel circuit method is limited. Increasing the aperture of the under-screen camera area typically requires additional masking processes for the conductive wires, increasing costs. Furthermore, the conductive wires are typically made of transparent conductive materials, such as indium tin oxide (ITO). Due to the high sheet resistance of ITO, the conductive wires are subject to heavy load, which can easily affect the brightness of the light-emitting elements in the under-screen camera area, reducing the brightness and causing display artifacts in the under-screen camera area, such as vertical mura.

[0100] The built-in pixel circuit method involves placing a light-emitting element and the pixel circuit connected to it in the under-screen camera area. Compared to the external pixel circuit method, the built-in method eliminates the need for long conductive wires to connect the pixel circuit and light-emitting element in the under-screen camera area, thus avoiding display issues in the under-screen camera area caused by these wires. Furthermore, the built-in method places no restrictions on the size of the under-screen camera area and can support under-screen camera areas with large apertures. However, in display substrates using the built-in pixel circuit method, the anode of the light-emitting element in the under-screen camera area cannot completely block the pixel circuit, thus affecting the light transmittance of the under-screen camera area.

[0101] This embodiment provides a display substrate and a display device, which can support increasing the size of the under-screen camera area while ensuring the light transmittance of the under-screen camera area.

[0102] This embodiment provides a display substrate, comprising: a substrate, a plurality of first light-emitting units, a plurality of second light-emitting units, a plurality of first pixel circuits, and a plurality of second pixel circuits. The substrate comprises a first display area and a second display area located at least on one side of the first display area. The plurality of first light-emitting units and the plurality of second light-emitting units are located in the first display area; the first light-emitting unit comprises at least one first light-emitting element, and the second light-emitting unit comprises at least one second light-emitting element. The first light-emitting unit is adjacent to the at least one second light-emitting unit. The plurality of first pixel circuits are located in the first display area; at least one of the plurality of first pixel circuits is electrically connected to the at least one first light-emitting element and is configured to drive the at least one first light-emitting element to emit light. The plurality of second pixel circuits are located in the second display area; at least one of the plurality of second pixel circuits is electrically connected to the at least one second light-emitting element and is configured to drive the at least one second light-emitting element to emit light.

[0103] The display substrate provided in this embodiment adopts a combination of external and internal pixel circuits, which can ensure the light transmittance of the first display area and support increasing the size of the first display area.

[0104] In some exemplary embodiments, the plurality of first light-emitting units and the plurality of second light-emitting units may be spaced apart along at least one of a first direction and a second direction. The first direction intersects the second direction. For example, the first direction may be perpendicular to the second direction. In some examples, the plurality of first light-emitting units and the plurality of second light-emitting units may be spaced apart in both the first and second directions. For example, in the first direction, one first light-emitting unit and one second light-emitting unit may be spaced apart; in the second direction, one first light-emitting unit and one second light-emitting unit may be spaced apart. In other examples, the plurality of first light-emitting units and the plurality of second light-emitting units may be spaced apart only along the first or second direction. By spacing the first and second light-emitting units, this example allows for a rational layout of the light-emitting elements external to the pixel circuit and the light-emitting elements internal to the pixel circuit to achieve an optimal combination of light transmittance and size in the first display area, thereby improving the performance of the display substrate and the user experience. Furthermore, spacing the first and second light-emitting units facilitates brightness compensation between the first and second light-emitting elements, thereby improving brightness uniformity in the first display area.

[0105] In some exemplary embodiments, the ratio of the light-emitting areas of the second light-emitting element emitting light of the same color to the first light-emitting element may be less than 1. In some examples, the ratio of the light-emitting areas of the second light-emitting element emitting light of the same color to the first light-emitting element may be 0.4 to 0.8, for example, approximately 0.5. This example reduces the light-emitting area of ​​the second light-emitting element, thereby improving the dimming caused by the external placement of the pixel circuit of the second light-emitting element.

[0106] In some exemplary embodiments, the number of first light-emitting elements included in at least one first light-emitting unit may be the same as the number of second light-emitting elements included in at least one second light-emitting unit. In some examples, at least one first light-emitting unit may include the following four first light-emitting elements: a first light-emitting element that emits light of a first color, a first light-emitting element that emits light of a second color, and two first light-emitting elements that emit light of a third color. At least one second light-emitting unit may include the following four second light-emitting elements: a second light-emitting element that emits light of a first color, a second light-emitting element that emits light of a second color, and two second light-emitting elements that emit light of a third color. However, this embodiment is not limited to this. For example, the first light-emitting unit and the second light-emitting unit may each include three light-emitting elements. In this example, the number of light-emitting elements included in the first light-emitting unit and the second light-emitting unit is set to be the same, which can facilitate brightness compensation between adjacent light-emitting elements emitting light of the same color, thereby contributing to brightness uniformity in the first display area.

[0107] In some exemplary embodiments, the ratio of the number of the first light-emitting units to the second light-emitting units in the first display area may be 0.8 to 1.2, for example, approximately 1. The ratio of the number of the first light-emitting units to the second light-emitting units in this example can effectively reduce the number of conductive connection lines connected to the external pixel circuit and the wiring space, thereby supporting an increase in the size of the first display area.

[0108] In some exemplary embodiments, the light transmittance of the first display area may be greater than the light transmittance of the second display area. The display substrate may further include: a plurality of third light-emitting elements and a plurality of third pixel circuits located in the second display area. At least one third pixel circuit is electrically connected to at least one third light-emitting element and configured to drive the at least one third light-emitting element to emit light. The plurality of second pixel circuits may be spaced apart between the plurality of third pixel circuits. In this example, by setting the second display area to have a lower light transmittance than the first display area, the display effect of the display substrate can be ensured.

[0109] In some examples, the sum of the number of first and second light-emitting elements per unit area can be less than or equal to the number of third light-emitting elements per unit area. Alternatively, the density of first and second light-emitting elements in the first display area can be less than or equal to the density of third light-emitting elements in the second display area. Alternatively, the pixel density (PPI) of the first display area can be less than or equal to the pixel density of the second display area.

[0110] The solution of this embodiment is illustrated below through some examples.

[0111] Figure 1 is a schematic diagram of a display substrate according to at least one embodiment of the present disclosure. In some examples, as shown in Figure 1 , the display substrate may include a display area AA and a peripheral area BB located outside the display area AA. The display area AA of the display substrate may include at least a first display area A1 and a second display area A2. The second display area A2 may at least partially surround the first display area A1. For example, the second display area A2 may surround the first display area A1. The peripheral area BB may surround the second display area A2. However, this embodiment is not limited to this.

[0112] In some examples, as shown in Figure 1, the first display area A1 may be a light-transmitting display area, and may also be referred to as an under-screen camera (FDC, Full Display With Camera) area. The second display area A2 may be referred to as a normal display area. For example, the orthographic projection of a sensor (such as a camera or other hardware) on the display substrate may be located within the first display area A1 of the display substrate. In some examples, as shown in Figure 1, the first display area A1 may be circular, and the size of the orthographic projection of the sensor on the display substrate may be less than or equal to the size of the first display area A1. However, this embodiment is not limited to this. In other examples, the first display area A1 may be rectangular, and the size of the orthographic projection of the sensor on the display substrate may be less than or equal to the size of the inscribed circle of the first display area A1.

[0113] In some examples, as shown in FIG1 , the first display area A1 can be located at the top center of the display area AA. The second display area A2 can surround the first display area A1. However, this embodiment is not limited to this. For example, the first display area A1 can be located at other locations, such as the upper left corner, lower left corner, lower right corner, or upper right corner of the display area AA. For example, the second display area A2 can surround at least one side of the first display area A1.

[0114] In some examples, as shown in FIG1 , the display area AA may be a rectangle, such as a rounded rectangle. The first display area A1 may be circular or elliptical. However, this embodiment is not limited thereto. For example, the first display area A1 may be a rectangle, a semicircle, a pentagon, or other shapes.

[0115] In some examples, the display area AA may be provided with a plurality of sub-pixels. At least one sub-pixel may include a pixel circuit and a light-emitting element. The pixel circuit may be configured to drive the connected light-emitting element. For example, the pixel circuit may be configured to provide a driving current to drive the light-emitting element to emit light. The pixel circuit may include a plurality of transistors and at least one capacitor. For example, the pixel circuit may be a 3T1C, 4T1C, 5T1C, 5T2C, 6T1C, 7T1C, or 8T1C structure. In the above circuit structure, T refers to a thin film transistor, C refers to a capacitor, the number before T represents the number of thin film transistors in the circuit, and the number before C represents the number of capacitors in the circuit.

[0116] In some examples, the light-emitting element may be any one of a light-emitting diode (LED), an organic light-emitting diode (OLED), a quantum dot light-emitting diode (QLED), a micro-LED (including mini-LED or micro-LED), etc. For example, the light-emitting element may be an OLED, which may emit red light, green light, blue light, or white light, etc. when driven by its corresponding pixel circuit. The light-emitting color of the light-emitting element may be determined as needed. In some examples, the light-emitting element may include: an anode, a cathode, and an organic light-emitting layer located between the anode and the cathode. The anode of the light-emitting element may be electrically connected to the corresponding pixel circuit. However, this embodiment is not limited to this.

[0117] Figure 2 is an equivalent circuit diagram of a pixel circuit of at least one embodiment of the present disclosure. The pixel circuit of this example is illustrated using an 8T1C structure as an example. In some examples, as shown in Figure 2, the pixel circuit of this example may include eight transistors (i.e., a first transistor T1 to an eighth transistor T8) and a storage capacitor Cst. The first transistor T1 may also be referred to as a first reset transistor, the second transistor T2 may also be referred to as a threshold compensation transistor, the third transistor T3 may also be referred to as a drive transistor, the fourth transistor T4 may also be referred to as a data write transistor, the fifth transistor T5 may also be referred to as a first light-emitting control transistor, the sixth transistor T6 may also be referred to as a second light-emitting control transistor, the seventh transistor T7 may also be referred to as a second reset transistor, and the eighth transistor T8 may also be referred to as a third reset transistor. The light-emitting element EL may include an anode, a cathode, and an organic light-emitting layer disposed between the anode and the cathode.

[0118] In some examples, the first transistor T1 and the third transistor T3 to the eighth transistor T8 may be first-type transistors, such as P-type transistors, and the second transistor T2 may be a second-type transistor, such as N-type transistors. However, this embodiment is not limited to this. For example, the plurality of transistors in the pixel circuit may all be P-type transistors, or may all be N-type transistors.

[0119] In some examples, the first type of transistor of the pixel circuit (for example, including the first transistor T1, the third transistor T3 to the eighth transistor T8) can be a low-temperature polysilicon thin film transistor, and the second type of transistor of the pixel circuit (for example, including the second transistor T2) can be an oxide thin film transistor. The active layer of the low-temperature polysilicon thin film transistor is made of low-temperature polysilicon (LTPS), and the active layer of the oxide thin film transistor is made of oxide semiconductor (Oxide). Low-temperature polysilicon thin film transistors have the advantages of high mobility and fast charging, while oxide thin film transistors have the advantages of low leakage current. Integrating low-temperature polysilicon thin film transistors and oxide thin film transistors on a display substrate to form a low-temperature polycrystalline oxide (LTPS+Oxide) display substrate can take advantage of the advantages of both, achieve low-frequency driving, reduce power consumption, and improve display quality.

[0120] In some examples, as shown in FIG2 , the pixel circuit can be electrically connected to a first scan line GL1, a second scan line GL2, a data line DL, a first power line PL1, a second power line PL2, an emission control line EML, a first initial signal line INIT1, a second initial signal line INIT2, a third initial signal line INIT3, a first reset control line RST1, and a second reset control line RST2. The first power line PL1 can be configured to provide a constant first voltage signal VDD to the pixel circuit, and the second power line PL2 can be configured to provide a constant second voltage signal VSS to the pixel circuit, with the first voltage signal VDD being greater than the second voltage signal VSS. The first scan line GL1 can be configured to provide a first scan signal SCAN1 to the pixel circuit. The second scan line GL2 can be configured to provide a second scan signal SCAN2 to the pixel circuit. The data line DL can be configured to provide a data signal to the pixel circuit. The emission control line EML can be configured to provide an emission control signal EM to the pixel circuit. The first reset control line RST1 can be configured to provide a first reset control signal RESET1 to the pixel circuit. The second reset control line may be configured to provide a second reset control signal RESET2 to the pixel circuit.

[0121] In some examples, as shown in FIG2 , the gate of the third transistor T3 is electrically connected to the first node N1, the first electrode of the third transistor T3 is electrically connected to the second node N2, and the second electrode of the third transistor T3 is electrically connected to the third node N3. The gate of the fourth transistor T4 is electrically connected to the first scan line GL1, the first electrode of the fourth transistor T4 is electrically connected to the data line DL, and the second electrode of the fourth transistor T4 is electrically connected to the second node N2. The gate of the second transistor T2 is electrically connected to the second scan line GL2, the first electrode of the second transistor T2 is electrically connected to the first node N1, and the second electrode of the second transistor T2 is electrically connected to the third node N3. The gate of the fifth transistor T5 is electrically connected to the emission control line EML, the first electrode of the fifth transistor T5 is electrically connected to the first power line PL1, and the second electrode of the fifth transistor T5 is electrically connected to the second node N2. The gate of the sixth transistor T6 is electrically connected to the emission control line EML, the first electrode of the sixth transistor T6 is electrically connected to the third node N3, and the second electrode of the sixth transistor T6 is electrically connected to the fourth node N4. The gate of the first transistor T1 is electrically connected to the first reset control line RST1, the first electrode of the first transistor T1 is electrically connected to the first initial signal line INIT1, and the second electrode of the first transistor T1 is electrically connected to the third node N3. The gate of the seventh transistor T7 is electrically connected to the second reset control line RST2, the first electrode of the seventh transistor T7 is electrically connected to the second initial signal line INIT2, and the second electrode of the seventh transistor T7 is electrically connected to the fourth node N4. The gate of the eighth transistor T8 is electrically connected to the second reset control line RST2, the first electrode of the eighth transistor T8 is electrically connected to the third initial signal line INIT3, and the second electrode of the eighth transistor T8 is electrically connected to the second node N2. The first electrode of the storage capacitor Cst is electrically connected to the first node N1, and the second electrode of the storage capacitor Cst is electrically connected to the first power line PL1.

[0122] In this example, the first node N1 is the connection point of the storage capacitor Cst, the second transistor T2 and the third transistor T3, the second node N2 is the connection point of the fifth transistor T5, the fourth transistor T4, the eighth transistor T8 and the third transistor T3, the third node N3 is the connection point of the first transistor T1, the third transistor T3, the second transistor T2 and the sixth transistor T6, and the fourth node N4 is the connection point of the sixth transistor T6, the seventh transistor T7 and the light emitting element EL.

[0123] FIG3 is an operating timing diagram of the pixel circuit shown in FIG2. The operating process of the pixel circuit shown in FIG2 will be described below with reference to FIG3. In the pixel circuit, the first transistor T1, the third transistor T3 to the eighth transistor T8 are P-type transistors, and the second transistor T2 is an N-type transistor.

[0124] In some examples, as shown in FIG. 2 and FIG. 3 , during a frame display period, the operation process of the pixel circuit may include at least: a first stage S1 , a second stage S2 , a third stage S3 , and a fourth stage S4 .

[0125] The first stage S1 is called the first reset stage. The second reset control signal RESET2 provided by the second reset control line RST2 is a low-level signal, turning on the seventh transistor T7 and the eighth transistor T8. The second scan signal SCAN2 provided by the second scan line GL2 is a high-level signal, turning on the second transistor T2. The eighth transistor T8 is turned on, allowing the third initial signal provided by the third initial signal line INIT3 to be supplied to the second node N2. The seventh transistor T7 is turned on, allowing the second initial signal provided by the second initial signal line INIT2 to be supplied to the fourth node N4, initializing the fourth node N4. The first scan signal SCAN1 provided by the first scan line GL1 is a high-level signal, the first reset control signal RESET1 provided by the first reset control line RST1 is a high-level signal, and the emission control signal EM provided by the emission control line EML is a high-level signal, turning off the fourth transistor T4, the first transistor T1, the fifth transistor T5, and the sixth transistor T6. During this stage, the light-emitting element EL does not emit light.

[0126] The second stage S2 is called the second reset stage. The first reset control signal RESET1 provided by the first reset control line RST1 is a low-level signal, turning on the first transistor T1; the second scan signal SCAN2 provided by the second scan line GL2 is a high-level signal, turning on the second transistor T2. The first transistor T1 and the second transistor T2 are turned on, causing the first initial signal line provided by the first initial signal line INIT1 to be supplied to the first node N1, initializing the first node N1. The second reset control signal RESET2 provided by the second reset control line RST2 is a high-level signal, the first scan signal SCAN1 provided by the first scan line GL1 is a high-level signal, and the emission control signal EM provided by the emission control line EML is a high-level signal, turning off the seventh transistor T7, the eighth transistor T8, the fourth transistor T4, the fifth transistor T5, and the sixth transistor T6. During this stage, the light-emitting element EL does not emit light.

[0127] The third stage S3 is called the data writing stage or the threshold compensation stage. The first scan signal SCAN1 provided by the first scan line GL1 is a low-level signal, and the fourth transistor T4 is turned on. The second scan signal SCAN2 provided by the second scan line GL2 is a high-level signal, and the second transistor T2 is turned on. During this stage, the first electrode of the storage capacitor Cst is at a low level, and the third transistor T3 is turned on. The second transistor T2, the fourth transistor T4, and the third transistor T3 are turned on, so that the data voltage Vdata output by the data line DL is provided to the first node N1 through the second node N2, the turned-on third transistor T3, the third node N3, and the turned-on second transistor T2. The difference between the data voltage Vdata output by the data line DL and the threshold voltage of the third transistor T3 is charged into the storage capacitor Cst. The voltage at the first electrode of the storage capacitor Cst (i.e., the first node N1) is Vdata-|Vth|, where Vdata is the data voltage output by the data line DL and Vth is the threshold voltage of the third transistor T3. The first reset control signal RESET1 provided by the first reset control line RST1 is a high level signal, the second reset control signal RESET2 provided by the second reset control line RST2 is a high level signal, and the light-emitting control signal EM provided by the light-emitting control line EML is a high level signal, so that the first transistor T1, the seventh transistor T7, the eighth transistor T8, the fifth transistor T5 and the sixth transistor T6 are disconnected.

[0128] In the fourth stage S4, the emission control signal EM provided by the emission control line EML can be switched from a high-level signal to a low-level signal, turning on the fifth transistor T5 and the sixth transistor T6. The second scan signal SCAN2 provided by the second scan line GL2 is a low-level signal, turning off the second transistor T2. The first scan signal SCAN1 provided by the first scan line GL1, the first reset control signal RESET1 provided by the first reset control line RST1, and the second reset control signal RESET2 provided by the second reset control line RST2 are high-level signals, turning off the fourth transistor T4, the first transistor T1, the seventh transistor T7, and the eighth transistor T8. The first voltage signal VDD output by the first power line PL1 can provide a driving voltage to the anode of the light-emitting element EL through the turned-on fifth transistor T5, the third transistor T3, and the sixth transistor T6, thereby driving the light-emitting element EL to emit light.

[0129] During the driving process of the pixel circuit, the driving current flowing through the third transistor T3 is determined by the voltage difference between its gate and the first electrode. Since the voltage of the first node N1 is Vdata-|Vth|, the driving current of the third transistor T3 is: I=K×(Vgs-Vth) 2 =K×[(VDD-Vdata+|Vth|)-Vth] 2 =K×[VDD-Vdata]2 ;

[0130] Wherein, I is the driving current flowing through the third transistor T3, that is, the driving current driving the light-emitting element, K is a constant, Vgs is the voltage difference between the gate and the first electrode of the third transistor T3, Vth is the threshold voltage of the third transistor T3, Vdata is the data voltage output by the data line DL, and VDD is the first voltage signal output by the first power line PL1.

[0131] From the above equation, it can be seen that the current flowing through the light-emitting element is independent of the threshold voltage of the third transistor T3. Therefore, the pixel circuit of this embodiment can effectively compensate for the threshold voltage of the third transistor T3. Moreover, the pixel circuit provided by this embodiment can improve the display quality caused by low frequency and enhance the display effect of the light-emitting element.

[0132] In some examples, as shown in FIG1 , the first display area A1 of the display substrate may be provided with a plurality of first light-emitting elements 21, a plurality of second light-emitting elements 22, and a plurality of first pixel circuits 11. At least one first pixel circuit 11 is electrically connected to at least one first light-emitting element 21 and is configured to drive at least one first light-emitting element 21 to emit light. The second display area A2 may be provided with a plurality of second pixel circuits 12, a plurality of third pixel circuits 13, and a plurality of third light-emitting elements 23. The circuit structures of the first pixel circuits 11, second pixel circuits 12, and third pixel circuits 13 in this example may be the same, for example, the 8T1C structure described above. At least one second pixel circuit 12 may be electrically connected to at least one second light-emitting element 22 via at least one conductive connecting line 15 and is configured to drive at least one second light-emitting element 22 to emit light. The conductive connecting line 15 may extend from the first display area A1 to the second display area A2. At least one third pixel circuit 13 is electrically connected to at least one third light-emitting element 23 and is configured to drive at least one third light-emitting element 23 to emit light.

[0133] For example, multiple first pixel circuits 11 are electrically connected to multiple first light-emitting elements 21 in a one-to-one correspondence, and one first pixel circuit 11 can be configured to drive one first light-emitting element 21. The orthographic projection of the first light-emitting element 21 on the substrate at least partially overlaps with the orthographic projection of the first pixel circuit 11 to which it is connected. Multiple second pixel circuits 12 are electrically connected to multiple second light-emitting elements 22 in a one-to-one correspondence, and one second pixel circuit 12 can be configured to drive one second light-emitting element 22. The orthographic projection of the second light-emitting element 22 on the substrate may not overlap with the orthographic projection of the second pixel circuit 12 to which it is connected. Multiple third pixel circuits 13 are electrically connected to multiple third light-emitting elements 23 in a one-to-one correspondence, and one third pixel circuit 13 can be configured to drive one third light-emitting element 23. The orthographic projection of the third light-emitting element 23 on the substrate at least partially overlaps with the orthographic projection of the third pixel circuit 13 to which it is connected. However, this embodiment is not limited to this. In other examples, multiple first pixel circuits can be configured to drive one first light-emitting element; or one first pixel circuit can be configured to drive multiple first light-emitting elements. For another example, multiple second pixel circuits can be configured to drive one second light-emitting element; or one second pixel circuit can be configured to drive multiple second light-emitting elements. For another example, multiple third pixel circuits can be configured to drive one third light-emitting element; or one third pixel circuit can be configured to drive multiple third light-emitting elements.

[0134] Figures 4A and 4B are partial schematic diagrams of the first display area of ​​at least one embodiment of the present disclosure. In some examples, as shown in Figure 4A, the first display area may include: multiple first sub-areas A11 and multiple second sub-areas A12. At least one first sub-area A11 is adjacent to at least one second sub-area A12. For example, the first sub-area A11 is adjacent to two second sub-areas A12 in a first direction X and is located between the two second sub-areas A12; the first sub-area A11 is adjacent to two second sub-areas A12 in a second direction Y and is located between the two second sub-areas A12. The first direction X intersects the second direction Y. For example, the first direction X can be perpendicular to the second direction Y.

[0135] In some examples, as shown in FIG4A , a first light-emitting unit 2a may be provided in the first sub-area A11, and a second light-emitting unit 2b may be provided in the second sub-area A12. The multiple first light-emitting units 2a and multiple second light-emitting units 2b in the first display area may be arranged in an array into multiple rows and columns. A row of light-emitting units may include multiple first light-emitting units 2a and multiple second light-emitting units 2b spaced apart along a first direction X, and a column of light-emitting units may include multiple first light-emitting units 2a and multiple second light-emitting units 2b spaced apart along a second direction Y. In the first direction X, the first light-emitting units 2a and the second light-emitting units 2b are spaced apart one by one; in the second direction Y, the first light-emitting units 2a and the second light-emitting units 2b are spaced apart one by one. For example, one first light-emitting unit 2a may be adjacent to four second light-emitting units 2b. In this example, "A and B are adjacent" means that A and B are close to each other, and there are no other objects of the same type between A and B. In this example, the first light-emitting unit and the second light-emitting unit are arranged at intervals in the first direction and the second direction, which not only ensures the light transmittance of the first display area, but also facilitates the realization of a larger first display area and facilitates brightness compensation to improve the brightness uniformity of the first display area.

[0136] In some examples, as shown in Figures 4A and 4B, adjacent first light-emitting units 2a and second light-emitting units 2b are aligned in a first direction X, and adjacent first light-emitting units 2a and second light-emitting units 2b are aligned in a second direction Y. In this example, "A and B are aligned in direction C" means that a line connecting the centers of A and B in direction C is substantially parallel to direction C.

[0137] In some examples, as shown in FIG4A , the first light-emitting unit 2a may include at least one first light-emitting element, for example, four first light-emitting elements; and the second light-emitting unit 2b may include at least one second light-emitting element, for example, four second light-emitting elements. The number of first light-emitting elements included in the first light-emitting unit 2a and the number of second light-emitting elements included in the second light-emitting unit 2b may be the same. However, this embodiment is not limited to this. In other examples, the number of first light-emitting elements included in the first light-emitting unit may be greater than the number of second light-emitting elements included in the second light-emitting unit, or the number of first light-emitting elements included in the first light-emitting unit may be less than the number of second light-emitting elements included in the second light-emitting unit. In this example, by setting the number of first light-emitting elements included in the first light-emitting unit to be the same as the number of second light-emitting elements included in the second light-emitting unit, it is convenient to control the ratio of the first light-emitting elements to the second light-emitting elements, thereby facilitating the design of brightness compensation between the first light-emitting element and the second light-emitting element.

[0138] In some examples, as shown in Figures 4A and 4B, the plurality of light-emitting elements (including a plurality of first light-emitting elements and a plurality of second light-emitting elements) in the first display area can be arranged in an array into multiple rows and columns. A row of light-emitting elements may include a plurality of first light-emitting elements and a plurality of second light-emitting elements arranged along a first direction X, and a column of light-emitting elements may include a plurality of first light-emitting elements and a plurality of second light-emitting elements arranged along a second direction Y. A column of light-emitting units may include four columns of light-emitting elements, and a row of light-emitting units may include two rows of light-emitting elements. For example, the light-emitting units in the a-th column may include the d-th column, the d+1-th column, the d+2-th column, and the d+3-th column of light-emitting elements, and the light-emitting units in the b-th row may include the c-th row and the c+1-th row of light-emitting elements, where a, b, c, and d are all integers greater than 0.

[0139] In some examples, as shown in Figures 4A and 4B, a first light-emitting unit 2a may include the following four first light-emitting elements: a first light-emitting element 21a that emits light of a first color, a first light-emitting element 21b that emits light of a second color, and two first light-emitting elements 21c and 21d that emit light of a third color. The four first light-emitting elements included in the first light-emitting unit 2a may be arranged in two rows of light-emitting elements, with the first light-emitting element 21a that emits light of the first color and the first light-emitting element 21b that emits light of the second color being arranged in the same row of light-emitting elements, and the two first light-emitting elements 21c and 21d that emit light of the third color being arranged in the same row of light-emitting elements. The four first light-emitting elements may be arranged in different columns of light-emitting elements.

[0140] In some examples, as shown in Figures 4A and 4B, a second light-emitting unit 2b may include the following four second light-emitting elements: a second light-emitting element 22a that emits light of the first color, a second light-emitting element 22b that emits light of the second color, and two second light-emitting elements 22c and 22d that emit light of the third color. The four second light-emitting elements included in a second light-emitting unit 2b may be arranged in two rows of light-emitting elements, the second light-emitting element 22a that emits light of the first color and the second light-emitting element 22b that emits light of the second color may be arranged in the same row of light-emitting elements, the two second light-emitting elements 22c and 22d that emit light of the third color may be arranged in the same row of light-emitting elements, and the four second light-emitting elements may be arranged in different columns of light-emitting elements. The arrangement of the four second light-emitting elements in the second light-emitting unit of this example is roughly the same as the arrangement of the four first light-emitting elements in the first light-emitting unit. The arrangement of the light-emitting elements of this example can be beneficial for designing brightness compensation between the first light-emitting element and the second light-emitting element.

[0141] In some examples, as shown in FIG4B , in the c-th row of light-emitting elements, two second light-emitting elements 22c and 22d emitting third color light and two first light-emitting elements 21c and 21d emitting third color light can be periodically arranged along the first direction X; in the c+1-th row of light-emitting elements, the second light-emitting element 22a emitting first color light, the second light-emitting element 22b emitting second color light, the first light-emitting element 21a emitting first color light and the first light-emitting element 21b emitting second color light can be periodically arranged along the first direction X. In the d-th column of light-emitting elements, the second light-emitting element 22a emitting the first color light and the first light-emitting element 21b emitting the second color light can be arranged at intervals along the second direction X; in the d+1-th column of light-emitting elements, the second light-emitting element 22c (or 22d) emitting the second color light and the first light-emitting element 21c (or 21d) emitting the third color light can be arranged at intervals along the second direction Y; in the d+2-th column of light-emitting elements, the second light-emitting element 22b emitting the second color light and the first light-emitting element 21a emitting the first color light can be arranged at intervals along the second direction Y; in the d+3-th column of light-emitting elements, the second light-emitting element 22d emitting the second color light and the first light-emitting element 21d emitting the third color light can be arranged at intervals along the second direction Y.

[0142] In some examples, as shown in FIG4A , in different first light-emitting units located in adjacent rows of light-emitting units, the arrangement order of the first light-emitting elements 21 a emitting the first color light and the first light-emitting elements 21 b emitting the second color light is reversed. For example, in the first light-emitting units located in the bth row, the first light-emitting elements 21 a emitting the first color light and the first light-emitting elements 21 b emitting the second color light can be arranged sequentially along the first direction X. In the first light-emitting units located in the b+1th row, the first light-emitting elements 21 b emitting the second color light and the first light-emitting elements 21 a emitting the first color light can be arranged sequentially along the first direction X.

[0143] In some examples, as shown in FIG4A , in different first light-emitting units located in adjacent light-emitting unit columns, the arrangement order of the first light-emitting elements 21 a emitting the first color light and the first light-emitting elements 21 b emitting the second color light is reversed. For example, in the first light-emitting unit located in the ath column, the first light-emitting element 21 b emitting the second color light and the first light-emitting element 21 a emitting the first color light can be arranged sequentially along the first direction X. In the first light-emitting unit located in the a+1th column, the first light-emitting element 21 a emitting the first color light and the first light-emitting element 21 b emitting the second color light can be arranged sequentially along the first direction X.

[0144] In some examples, as shown in FIG4A , in different second light-emitting units located in adjacent light-emitting unit rows, the arrangement order of the second light-emitting elements 22 a emitting the first color light and the second light-emitting elements 22 b emitting the second color light is reversed; in different second light-emitting units located in adjacent light-emitting unit columns, the arrangement order of the second light-emitting elements 22 a emitting the first color light and the second light-emitting elements 22 b emitting the second color light is reversed. The arrangement of the second light-emitting elements in the second light-emitting units is similar to the arrangement of the first light-emitting elements in the first light-emitting units, and therefore will not be further described here.

[0145] In some examples, the first color light may be red light (R), the second color light may be blue light (B), and the third color light may be green light (G). However, this embodiment is not limited thereto.

[0146] In some examples, the first light-emitting element of the first light-emitting unit 2a in the first display area can be configured to perform brightness compensation for the second light-emitting element of the adjacent second light-emitting unit 2b emitting light of the same color. For example, the first light-emitting element 21b emitting blue light in the first light-emitting unit 2a in column a, row b+1 and column a, row b+3 can perform brightness compensation for the second light-emitting element 22b emitting blue light in the second light-emitting unit 2b in column a, row b+2. The first light-emitting element 21a emitting red light in the first light-emitting unit 2a in column a, row b+1 and column a, row b+3 can perform brightness compensation for the second light-emitting element 22a emitting red light in the second light-emitting unit 2b in column a, row b+2. The first light-emitting element 21c emitting green light in the first light-emitting unit 2a in the a+1th column and the bth row, the first light-emitting element 21d emitting green light in the first light-emitting unit 2a in the a+1th column and the b+1th row, and the first light-emitting element 21c emitting green light in the first light-emitting unit 2a in the a+1th column and the b+2th row, can compensate for the brightness of the second light-emitting element 22c emitting green light in the second light-emitting unit 2b in the a+1th column and the b+1th row. This example uses the first light-emitting elements in a first light-emitting unit to compensate for the brightness of the second light-emitting elements in the adjacent second light-emitting unit that emit the same color light, effectively improving the dim brightness of the second light-emitting elements.

[0147] Figure 5 is a schematic diagram of the connection relationship between the light-emitting elements and the pixel circuits of at least one embodiment of the present disclosure. In some examples, as shown in Figure 5, the first display area A1 may include: a plurality of first pixel circuits (for example, including first pixel circuits 11a, 11b, 11c and 11d), a plurality of first light-emitting elements and a plurality of second light-emitting elements, and the second display area A2 may include a plurality of second pixel circuits 12, a plurality of third pixel circuits 13 and a plurality of third light-emitting elements (not shown). The first pixel circuit and the first light-emitting element may be located in the first sub-area A11, and the second light-emitting element may be located in the second sub-area A12. The light transmittance of the second sub-area A12 may be greater than the light transmittance of the first sub-area A11. For example, the first sub-area A11 may be a non-light-transmitting area, and the second sub-area A12 may include a non-light-transmitting area and a light-transmitting area. The position of the anode and the wiring of the second light-emitting element in the second sub-area A12 may be a non-light-transmitting area, and the area where the metal wiring is not provided between the anodes of adjacent second light-emitting elements may be a light-transmitting area.

[0148] In some examples, as shown in FIG5 , the four first pixel circuits of each first sub-region A11 can be arranged in sequence along the first direction X. For example, the first pixel circuits 11a, 11b, 11c, and 11d can be arranged in sequence along the first direction X. The four first light-emitting elements of the first light-emitting unit can be electrically connected to the four first pixel circuits in a one-to-one correspondence. For example, a first light-emitting element emitting a first color light (e.g., a red first light-emitting element) can be electrically connected to the first pixel circuit 11a, a first light-emitting element emitting a third color light (e.g., a green first light-emitting element) can be electrically connected to the first pixel circuit 11b, a first light-emitting element emitting a second color light (e.g., a blue first light-emitting element) can be electrically connected to the first pixel circuit 11c, and another first light-emitting element emitting a third color light (e.g., a green first light-emitting element) can be electrically connected to the first pixel circuit 11d.

[0149] In some examples, as shown in FIG5 , the second sub-region A12 is not provided with a pixel circuit, and the four second light-emitting elements in the second sub-region A12 can be electrically connected to the second pixel circuit 12 in the second display area A2 via a conductive connection line 15. In the second sub-region A12, the light-transmitting areas between adjacent second light-emitting elements can be connected to each other to form a continuous light-transmitting area, thereby improving the light transmittance of the first display area.

[0150] In some examples, as shown in FIG5 , within the second display area A2, a plurality of second pixel circuits 12 may be spaced apart and distributed between a plurality of third pixel circuits 13. Within the second display area A2, the area for arranging the second pixel circuits 12 may be obtained by reducing the size of the third pixel circuits 13 in the first direction X. For example, the size of the third pixel circuits 13 in the first direction X may be smaller than the size of the third light-emitting element in the first direction X.

[0151] In some examples, the original f columns of third pixel circuits can be compressed along the first direction X to create space for one or two columns of second pixel circuits, and the space occupied by the f columns of pixel circuits before compression and the f+1 or f+2 columns of pixel circuits after compression can be the same. Wherein, f can be an integer greater than 1. In this example, f can be 4, and space for two columns of second pixel circuits can be created by compressing four columns of third pixel circuits. However, this embodiment is not limited to this.

[0152] In some examples, as shown in FIG5 , a second pixel circuit 12 may be provided in a second display area A2 on both sides (e.g., left and right) of the first display area A1 along the first direction X, and a second pixel circuit may not be provided in a second display area on both sides (e.g., top and bottom) of the first display area A1 along the second direction Y, or an inactive pixel circuit may be provided to maintain uniformity of the components of the multiple film layers in the second display area during the etching process. The structure of the inactive pixel circuit may be substantially the same as that of the second pixel circuit in the same row or column, except that the inactive pixel circuit is not electrically connected to any light-emitting element. This embodiment is not limited to this.

[0153] In some examples, as shown in FIG5 , a second light-emitting element in the first display area A1 near the center of the first display area A1 can be electrically connected to a second pixel circuit 12 in the second display area A2 near the first display area A1, and a second light-emitting element near the edge of the first display area A1 can be electrically connected to a second pixel circuit away from the first display area A1. This embodiment does not limit the connection relationship between the second pixel circuit and the second light-emitting element.

[0154] Figure 6 is a partial top view of the first display area of ​​at least one embodiment of the present disclosure. Figure 6 illustrates the first light-emitting units and the second light-emitting units in columns a to a+2 and rows b to b+3. In some examples, as shown in Figure 6, on a plane parallel to the display substrate, the first display area of ​​the display substrate includes a plurality of first sub-areas and a plurality of second sub-areas spaced apart along a first direction X and a second direction Y. The first sub-area may include a first light-emitting unit (including four first light-emitting elements 21a, 21b, 21c, and 21d) and four first pixel circuits, and the second sub-area may include a second light-emitting unit (including four second light-emitting elements 22a, 22b, 22c, and 22d). The second sub-area where the second light-emitting unit in the a+1 column and the b+1 row is located may be surrounded by the first sub-area where the first light-emitting unit in the a+1 column and the b+1 row is located, the first sub-area where the first light-emitting unit in the a+2 column and the b+1 row is located, and the first sub-area where the first light-emitting unit in the a+1 column and the b+2 row is located. The first sub-region where the first light-emitting unit in the a+1th column and the bth row is located, the first sub-region where the first light-emitting unit in the a+1th column and the b+1th row is located, the first sub-region where the first light-emitting unit in the a+2th column and the b+1th row is located, and the first sub-region where the first light-emitting unit in the a+1th column and the b+2th row is located can be connected to each other.

[0155] In some examples, in a direction perpendicular to the display substrate, the display substrate may include: a substrate, and a circuit structure layer, a conductive connection layer, and a light-emitting structure layer disposed on the substrate. The light-emitting structure layer may be located on a side of the circuit structure layer away from the substrate, and the conductive connection layer may be located between the circuit structure layer and the light-emitting structure layer. The circuit structure layer of the first display area may include: a plurality of first pixel circuits, and the light-emitting structure layer of the first display area may include: a plurality of first light-emitting elements and a plurality of second light-emitting elements.

[0156] In some examples, the circuit structure layer may include: a first semiconductor layer, a first conductive layer, a second conductive layer, a second semiconductor layer, a third conductive layer, a fourth conductive layer, a fifth conductive layer, and a sixth conductive layer disposed on a substrate. A first insulating layer may be disposed between the first semiconductor layer and the first conductive layer, a second insulating layer may be disposed between the first conductive layer and the second conductive layer, a third insulating layer may be disposed between the second conductive layer and the second semiconductor layer, a fourth insulating layer may be disposed between the second semiconductor layer and the third conductive layer, a fifth insulating layer may be disposed between the third conductive layer and the fourth conductive layer, a sixth insulating layer and a seventh insulating layer may be disposed between the fourth conductive layer and the fifth conductive layer, an eighth insulating layer may be disposed between the fifth conductive layer and the sixth conductive layer, and a ninth insulating layer may be disposed on the side of the sixth conductive layer away from the substrate. In some examples, the first to sixth insulating layers may be inorganic insulating layers, and the seventh to ninth insulating layers may be organic insulating layers. This embodiment is not limited to this.

[0157] In some examples, the conductive connection layer may include a plurality of conductive connection lines, and the conductive connection lines may extend from the first display area to the second display area to achieve electrical connection between the second light-emitting element and the second pixel circuit.

[0158] In some examples, the light-emitting structure layer may include: an anode layer, a pixel definition layer, an organic light-emitting layer, and a cathode layer, which are sequentially arranged on the circuit structure layer. The anode layer may be electrically connected to the pixel circuit of the circuit structure layer, the organic light-emitting layer may be connected to the anode layer, and the cathode layer may be connected to the organic light-emitting layer. The organic light-emitting layer may emit light of a corresponding color when driven by the anode layer and the cathode layer.

[0159] In some examples, the encapsulation structure layer may include a stacked first encapsulation layer, a second encapsulation layer, and a third encapsulation layer. The first and third encapsulation layers may be made of inorganic materials, and the second encapsulation layer may be made of organic materials. The second encapsulation layer may be disposed between the first and third encapsulation layers, forming an inorganic material / organic material / inorganic material stacked structure, thereby preventing external moisture from entering the light-emitting structure layer. In some possible implementations, the display substrate may further include other film layers, such as a touch structure layer and a color filter layer, which are not limited in this embodiment.

[0160] The structure of the display substrate is explained below by taking the example of the preparation process of the display substrate as an example. The "patterning process" mentioned in the present disclosure includes processes such as coating photoresist, mask exposure, development, etching, and stripping photoresist for metal materials, inorganic materials or transparent conductive materials, and includes processes such as coating organic materials, mask exposure and development for organic materials. Deposition can be carried out by any one or more of sputtering, evaporation, and chemical vapor deposition, coating can be carried out by any one or more of spraying, spin coating and inkjet printing, and etching can be carried out by any one or more of dry etching and wet etching, which are not limited in the present disclosure. "Thin film" refers to a thin film made by deposition, coating or other processes on a substrate of a certain material. If the "thin film" does not require a patterning process during the entire production process, the "thin film" can also be called a "layer". If the "thin film" requires a patterning process during the entire production process, it is called a "thin film" before the patterning process and a "layer" after the patterning process. The "layer" after the patterning process contains at least one "pattern".

[0161] The “A and B are arranged in the same layer” mentioned in the present disclosure means that A and B are formed simultaneously through the same patterning process, or the surfaces of A and B close to the substrate are at substantially the same distance from the substrate, or the surfaces of A and B close to the substrate are in direct contact with the same film layer. The “thickness” of the film layer is the dimension of the film layer in the direction perpendicular to the display substrate. In the exemplary embodiments of the present disclosure, “the orthographic projection of B is within the range of the orthographic projection of A” or “the orthographic projection of A includes the orthographic projection of B” means that the boundary of the orthographic projection of B falls within the boundary of the orthographic projection of A, or the boundary of the orthographic projection of A overlaps with the boundary of the orthographic projection of B. The “shape of A” mentioned in the present disclosure refers to the shape of the orthographic projection of A on the substrate.

[0162] In some examples, the preparation process of the display substrate may include the following operations. The circuit structure layer is described below using the two first pixel circuits in the first sub-region of the first display area as an example. This example is described using the first pixel circuit as the aforementioned 8T1C structure. Among them, the first first pixel circuit (i.e., the first pixel circuit 11a) may include: a first transistor 31a, a second transistor 32a, a third transistor 33a, a fourth transistor 34a, a fifth transistor 35a, a sixth transistor 36a, a seventh transistor 37a, an eighth transistor 38a and a storage capacitor; the second first pixel circuit (i.e., the first pixel circuit 11b) may include: a first transistor 31b, a second transistor 32b, a third transistor 33b, a fourth transistor 34b, a fifth transistor 35b, a sixth transistor 36b, a seventh transistor 37b, an eighth transistor 38b and a storage capacitor. The connection relationship between the eight transistors and the storage capacitor in each first pixel circuit can be referred to the equivalent circuit diagram shown in Figure 2.

[0163] (1) Provide a substrate. In some examples, the substrate can be a rigid substrate or a flexible substrate. For example, the rigid substrate can be, but is not limited to, one or more of glass and quartz; the flexible substrate can be, but is not limited to, one or more of polyethylene terephthalate, polyethylene terephthalate, polyetheretherketone, polystyrene, polycarbonate, polyarylate, polyarylate, polyimide, polyvinyl chloride, polyethylene, and textile fiber. In some examples, the flexible substrate can include a first flexible material layer, a first inorganic material layer, a second flexible material layer, and a second inorganic material layer stacked together. The material of the first flexible material layer and the second flexible material layer can be polyimide (PI), polyethylene terephthalate (PET), or a surface-treated polymer soft film. The material of the first inorganic material layer and the second inorganic material layer can be silicon nitride (SiNx, x>0) or silicon oxide (SiOy, y>0), etc., to improve the substrate's resistance to water and oxygen.

[0164] (2) Forming a first semiconductor layer. In some examples, a first semiconductor thin film is deposited on a substrate, and the first semiconductor thin film is patterned by a patterning process to form a first semiconductor layer disposed on the substrate. In some examples, the first semiconductor layer can be made of amorphous silicon (a-Si), polycrystalline silicon (p-Si), sexithiophene, or polythiophene.

[0165] Fig. 7A is a schematic diagram of the first display region after the first semiconductor layer is formed in Fig. 6. Fig. 7B is a schematic diagram of a first sub-region in Fig. 7A.

[0166] In some examples, as shown in Figures 7A and 7B, the first semiconductor layer of the first display area may include at least: active layers of multiple first-type transistors of multiple first pixel circuits (for example, including: the first active layer 310a of the first transistor of the first pixel circuit 11a in the first sub-area, the third active layer 330a of the third transistor, the fourth active layer 340a of the fourth transistor, the fifth active layer 350a of the fifth transistor, the sixth active layer 360a of the sixth transistor, the seventh active layer 370a of the seventh transistor, and the eighth active layer 380a of the eighth transistor, as well as the first active layer 310b of the first transistor of the first pixel circuit 11b, the third active layer 330b of the third transistor, the fourth active layer 340b of the fourth transistor, the fifth active layer 350b of the fifth transistor, the sixth active layer 360b of the sixth transistor, the seventh active layer 370b of the seventh transistor, and the eighth active layer 380b of the eighth transistor).

[0167] In some examples, within the first sub-region, the first semiconductor layer patterns of the four first pixel circuits can be substantially symmetrical about the first center line O1, the first semiconductor layer patterns of the first pixel circuits 11a and 11b can be substantially symmetrical about the second center line O2, and the first semiconductor layer patterns of the first pixel circuits 11c and 11d can be substantially symmetrical about the third center line O3. The first semiconductor layer patterns within different first sub-regions can be independent of each other.

[0168] In some examples, within the first sub-region, the first active layer, third active layer, fourth active layer, fifth active layer, sixth active layer, and seventh active layer of the four first pixel circuits can be interconnected as an integrated structure. The seventh active layer 370a of the first pixel circuit 11a and the seventh active layer 370b of the first pixel circuit 11b can be interconnected. The fifth active layer 350b of the first pixel circuit 11b and the fifth active layer of the first pixel circuit 11c can be interconnected. The seventh active layer of the first pixel circuit 11c and the seventh active layer of the first pixel circuit 11d can be interconnected. The first active layer of each first pixel circuit can be located on one side of the third active layer along the second direction Y, and the eighth active layer can be located on the side of the third active layer opposite to the second direction Y.

[0169] In some examples, the third active layers 330a and 330b may be approximately U-shaped, the fourth active layers 340a and 340b and the fifth active layers 350a and 350b may be approximately I-shaped, and the first active layers 310a and 310b, the sixth active layers 360a and 360b, the seventh active layers 370a and 370b, and the eighth active layers 380a and 380b may be approximately L-shaped. However, this embodiment is not limited thereto.

[0170] In some examples, the active layer of each transistor may include: a first region, a second region, and a channel region located between the first region and the second region. The material of the first semiconductor layer may include, for example, polysilicon. The channel region may not be doped with impurities and have semiconductor properties. The first region and the second region may be doped regions on both sides of the channel region, and are doped with impurities and therefore have conductivity. The impurities may vary depending on the type of transistor. In some examples, the doped region of the active layer may be interpreted as a source electrode or a drain electrode of the transistor. The portion of the active layer between the transistors may be interpreted as wiring doped with impurities, which can be used to electrically connect the transistors. This embodiment is not limited to this.

[0171] (2) Forming a first conductive layer. In some examples, a first insulating film and a first conductive film are sequentially deposited on the substrate forming the aforementioned structure. The first conductive film is patterned through a patterning process to form a first insulating layer and a first conductive layer disposed on the first insulating layer. In some examples, the first conductive layer may also be referred to as a first gate metal layer.

[0172] Figure 8A is a schematic diagram of the first display area after the first conductive layer is formed in Figure 6. Figure 8B is a schematic diagram of the first conductive layer in Figure 8A. Figure 8C is a schematic diagram of a first sub-area in Figure 8A.

[0173] In some examples, as shown in Figures 8A to 8C, the first conductive layer of the first display area may include at least: multiple first scan lines (for example, first scan lines GL1(i), GL1(i+1), GL1(i+2), GL1(i+3)), multiple light-emitting control lines (for example, light-emitting control lines EML(i), EML(i+1), EML(i+2), EML(i+3)), multiple first reset control lines (for example, first reset control lines RST1(i), RST1(i+1), RST1(i+2), RST1(i+3)), multiple second reset control lines (for example, second reset control lines RST2(i), RST2(i+1), RST2(i+2), RST2(i+3)), and multiple first electrodes of storage capacitors of first pixel circuits (for example, first electrodes 391a, 391b).

[0174] In some examples, within the first sub-region, the first scan line GL1(i) may be located on one side of the first electrode (e.g., 391a and 391b) of the storage capacitor of the first pixel circuit in the second direction Y, and the first reset control line RST1(i) may be located on one side of the first scan line GL1(i) in the second direction Y. The emission control line EML(i) may be located on a side of the first electrode (e.g., 391a and 391b) of the storage capacitor of the first pixel circuit in the opposite direction of the second direction Y, and the second reset control line RST2(i) may be located on a side of the emission control line EML(i) in the opposite direction of the second direction Y.

[0175] In some examples, the first reset control line RST1(i), the first scan line GL1(i), the second reset control line RST2(i), and the emission control line EML(i) can bend around a second sub-region adjacent to the first sub-region along the first direction X. For example, the first reset control line RST1(i) and the first scan line GL1(i) can bend around one side of the second sub-region along the second direction Y, and the second reset control line RST2(i) and the emission control line EML(i) can bend around the side of the second sub-region opposite to the second direction Y. In this example, by arranging the routing of the first conductive layer to bend around the second sub-region, light transmittance in the second sub-region is improved.

[0176] In some examples, the shape of the first reset control line RST1(i) can be substantially a zigzag line extending along the first direction X. In the first sub-region, the overlapping region of the first reset control line RST1(i) and the first active layer of the four first pixel circuits can serve as the gates of the first transistors of the four first pixel circuits (e.g., including the gate of the first transistor 31a and the gate of the first transistor 31b).

[0177] In some examples, the shape of the first scan line GL1(i) can be substantially a zigzag line extending along the first direction X. In the first sub-region, the overlapping region of the first scan line GL1(i) and the fourth active layer of the four first pixel circuits can serve as the gates of the fourth transistors of the four first pixel circuits (e.g., including the gate of the fourth transistor 34a and the gate of the fourth transistor 34b).

[0178] In some examples, the shape of the light emission control line EML(i) can be substantially a zigzag line extending along the first direction X. In the first sub-region, the overlapping region of the light emission control line EML(i) and the fifth active layer of the four first pixel circuits can serve as the gates of the fifth transistors of the four first pixel circuits (for example, including the gates of the fifth transistors 35 a and 35 b ), and the overlapping region of the light emission control line EML(i) and the sixth active layer of the four first pixel circuits can serve as the gates of the sixth transistors of the four first pixel circuits (for example, including the gates of the sixth transistors 36 a and 36 b ).

[0179] In some examples, the shape of the second reset control line RST2(i) can be substantially a zigzag line extending along the first direction X. In the first sub-region, the overlapping region of the second reset control line RST2(i) and the seventh active layer of the four first pixel circuits can serve as the gates of the seventh transistors of the four first pixel circuits (e.g., including the gates of the seventh transistors 37a and 37b), and the overlapping region of the second reset control line RST2(i) and the eighth active layer of the four first pixel circuits can serve as the gates of the eighth transistors of the four first pixel circuits (e.g., including the gates of the eighth transistors 38a and 38b).

[0180] In some examples, the first electrode 391a of the storage capacitor of the first pixel circuit 11a can also serve as the gate of the third transistor 33a, and the first electrode 391b of the storage capacitor of the first pixel circuit 11b can also serve as the gate of the third transistor 33b. The orthographic projections of the first electrodes 391a and 391b on the substrate can be approximately rectangular. This embodiment is not limited to this.

[0181] (3) Forming a second conductive layer. In some examples, a second insulating film and a second conductive film are sequentially deposited on the substrate forming the aforementioned structure. The second conductive film is patterned through a patterning process to form a second insulating layer and a second conductive layer disposed on the second insulating layer. In some examples, the second conductive layer may also be referred to as a second gate metal layer.

[0182] Figure 9A is a schematic diagram of the first display area after the second conductive layer is formed in Figure 6. Figure 9B is a schematic diagram of the second conductive layer in Figure 9A. Figure 9C is a schematic diagram of a first sub-area in Figure 9A.

[0183] In some examples, as shown in Figures 9A to 9C, the second conductive layer of the first display area may include at least: a plurality of second scanning auxiliary lines (for example, second scanning auxiliary lines GL2b(i), GL2b(i+1), GL2b(i+2), GL2b(i+3)), and a plurality of second electrodes of the storage capacitors of the first pixel circuits (for example, second electrodes 392a, 392b).

[0184] In some examples, the second scanning auxiliary line GL2b(i) can be shaped substantially like a zigzag line extending along the first direction X. Within the first sub-region, the second scanning auxiliary line GL2b(i) can be located on one side of the second electrode (e.g., 392a and 392b) of the storage capacitor of the first pixel circuit in the second direction Y. The second scanning auxiliary line GL2b(i) can bypass the second sub-region from one side in the second direction Y and be located on a side opposite to the first scanning line GL1(i) in the second direction Y.

[0185] In some examples, within the first sub-region, the orthographic projection of the second electrode of the storage capacitor of each first pixel circuit on the substrate can be approximately a rectangular structure with a hollowed-out area. The orthographic projection of the hollowed-out area on the substrate can be approximately rectangular, and the rectangle can have rounded or chamfered corners. The second electrode 392a of the storage capacitor of the first pixel circuit 11a and the second electrode 392b of the storage capacitor of the first pixel circuit 11b can be electrically connected via a first plate connection block 392-1, the second electrode 392b of the storage capacitor of the first pixel circuit 11b and the second electrode of the storage capacitor of the first pixel circuit 11c can be electrically connected via a second plate connection block 392-2, and the second electrode of the storage capacitor of the first pixel circuit 11c and the second electrode of the storage capacitor of the first pixel circuit 11d can be electrically connected via another first plate connection block 392-1. The second electrodes of the storage capacitors of the first pixel circuits 11a and 11d can be electrically connected to a second plate connection block 392-2 on the side away from the remaining first pixel circuits. The length L1 of the first plate connecting block 392-1 along the second direction Y can be less than the length L2 of the second plate connecting block 392-2 along the second direction Y. The second electrode of the storage capacitor can subsequently be electrically connected to the first power line via the second plate connecting block. In this example, the second electrodes of the storage capacitors of the four first pixel circuits in the first sub-region can be interconnected and integrated, which helps ensure uniform transmission of the first voltage signal along the first direction X.

[0186] (4) Forming a second semiconductor layer. In some examples, a third insulating film and a second semiconductor film are sequentially deposited on the substrate having the aforementioned pattern formed thereon. The second semiconductor film is patterned by a patterning process to form a third insulating layer and a second semiconductor layer disposed on the third insulating layer. In some examples, the material of the second semiconductor layer may include indium gallium zinc oxide (IGZO).

[0187] Figure 10A is a schematic diagram of the first display area after the second semiconductor layer is formed in Figure 6. Figure 10B is a schematic diagram of the second semiconductor layer in Figure 10A. Figure 10C is a schematic diagram of a first sub-area in Figure 10A.

[0188] In some examples, as shown in Figures 10A to 10C, the second semiconductor layer of the first display area may include at least: an active layer of a second type transistor of a plurality of first pixel circuits (for example, including: a second active layer 320a of the second transistor 32a of the first pixel circuit 11a within the first sub-area, a second active layer 320b of the second transistor 32b of the first pixel circuit 11b).

[0189] In some examples, within the first sub-region, the second semiconductor layer patterns of the four first pixel circuits can be roughly symmetrical about the first center line O1, the second semiconductor layer patterns of the first pixel circuits 11a and 11b can be roughly symmetrical about the second center line O2, and the second semiconductor layer patterns of the first pixel circuits 11c and 11d can be roughly symmetrical about the third center line O3.

[0190] In some examples, the second active layers 320a and 320b can be substantially L-shaped. The overlapping region between the second scanning auxiliary line GL2b(i) and the second active layer 320a can serve as the bottom gate of the second transistor 32a, and the overlapping region between the second scanning auxiliary line GL2b(i) and the second active layer 320b can serve as the bottom gate of the second transistor 32b.

[0191] (5) Forming a third conductive layer. In some examples, a fourth insulating film and a third conductive film are sequentially deposited on the substrate having the aforementioned pattern formed thereon. The third conductive film is patterned by a patterning process to form a fourth insulating layer and a third conductive layer disposed on the fourth insulating layer. In some examples, the third conductive layer may also be referred to as a third gate metal layer.

[0192] Figure 11A is a schematic diagram of the first display area after the third conductive layer is formed in Figure 6. Figure 11B is a schematic diagram of the third conductive layer in Figure 11A. Figure 11C is a schematic diagram of a first sub-area in Figure 11A.

[0193] In some examples, as shown in Figures 11A to 11C, the third conductive layer of the first display area may include at least: a plurality of second scan lines (e.g., second scan lines GL2(i), GL2(i+1), GL2(i+2), GL2(i+3)), a plurality of first initial signal lines (e.g., first initial signal lines INIT1(i), INIT1(i+1), INIT1(i+2), INIT1(i+3)), a plurality of second initial signal lines (e.g., second initial signal lines INIT2(i), INIT2(i+1), INIT2(i+2), INIT2(i+3)), and a plurality of third initial signal lines (e.g., third initial signal lines INIT3(i), INIT3(i+1), INIT3(i+2), INIT3(i+3)). The first initial signal lines, the second scan lines, the second initial signal lines, and the third initial signal lines may each be substantially in the shape of a zigzag line extending along the first direction X.

[0194] In some examples, within the first sub-region, the first initial signal line INIT1(i) and the second scan line GL2(i) may be located on one side of the storage capacitor along the second direction Y, and the second initial signal line INIT2(i) and the third initial signal line INIT3(i) may be located on a side of the storage capacitor in a direction opposite to the second direction Y. The first initial signal line INIT1(i) may be located on one side of the second scan line GL2(i) along the second direction Y. The second initial signal line INIT2(i) may be located on a side of the third initial signal line INIT3(i) in a direction opposite to the second direction Y.

[0195] In some examples, the first initial signal line INIT1(i), the second scan line GL2(i), the second initial signal line INIT2(i), and the third initial signal line INIT3(i) can bend around a second sub-region adjacent to the first sub-region along the first direction X. For example, the first initial signal line INIT1(i) and the second scan line GL2(i) can bend around one side of the second sub-region along the second direction Y, and the second initial signal line INIT2(i) and the third initial signal line INIT3(i) can bend around the second sub-region in the opposite direction of the second direction Y. In this example, by setting the routing of the third conductive layer to bend around the second sub-region, light transmittance of the second sub-region is improved.

[0196] In some examples, the orthographic projection of the first initial signal line INIT1(i) on the substrate may at least partially overlap with the orthographic projection of the first reset control line RST1(i) on the substrate, the orthographic projection of the second scan line GL2(i) on the substrate may at least partially overlap with the orthographic projection of the second scan auxiliary line GL2b(i) on the substrate, the orthographic projection of the third initial signal line INIT3(i) on the substrate may at least partially overlap with the orthographic projection of the light emitting control line EML(i) on the substrate, and the orthographic projection of the second initial signal line INIT2(i) on the substrate may at least partially overlap with the orthographic projection of the second reset control line RST2(i) on the substrate. This example avoids occupying excessive routing space by stacking the routing of different conductive layers, which helps save wiring space and thereby improves the light transmittance of the first display area.

[0197] (6) Forming a fifth insulating layer. In some examples, a fifth insulating film is deposited on the substrate having the aforementioned pattern formed thereon, and the fifth insulating film is patterned by a patterning process to form a fifth insulating layer.

[0198] FIG12 is a schematic diagram of a first sub-region after the fifth insulating layer is formed in FIG6. In some examples, as shown in FIG12, the fifth insulating layer of the first display area may have a plurality of via holes, such as first to nineteenth via holes V1 to V19, twenty-first to twenty-second via holes V21 to V22, twenty-third to twenty-fourth via holes V23 to V24, twenty-fifth to twenty-ninth via holes V25 to V29, and thirty-first to thirty-fourth via holes V31 to V34.

[0199] In some examples, the fifth insulating layer, the fourth insulating layer, the third insulating layer, the second insulating layer, and the first insulating layer in the first via hole V1 to the nineteenth via hole V19 can be removed to expose a portion of the surface of the first semiconductor layer. The fifth insulating layer, the fourth insulating layer, the third insulating layer, and the second insulating layer in the twenty-first via hole V21 and the twenty-second via hole V22 can be removed to expose a portion of the surface of the first conductive layer. The fifth insulating layer, the fourth insulating layer, and the third insulating layer in the twenty-third via hole V23 and the twenty-fourth via hole V24 can be removed to expose a portion of the surface of the second conductive layer. The fifth insulating layer in the twenty-fifth via hole V25 to the twenty-ninth via hole V29 can be removed to expose a portion of the surface of the third conductive layer. The fifth insulating layer and the fourth insulating layer in the thirty-first via hole V31 to the thirty-fourth via hole V34 can be removed to expose the surface of the second semiconductor layer.

[0200] (7) Forming a fourth conductive layer. In some examples, a fourth conductive film is deposited on the substrate having the aforementioned pattern, and the fourth conductive film is patterned by a patterning process to form a fourth conductive layer on the fifth insulating layer. In some examples, the fourth conductive layer may also be referred to as a first source / drain metal layer.

[0201] Figure 13A is a schematic diagram of the first display area after the fourth conductive layer is formed in Figure 6. Figure 13B is a schematic diagram of the fourth conductive layer in Figure 13A. Figure 13C is a schematic diagram of a first sub-area in Figure 13A.

[0202] In some examples, as shown in FIG. 13A to FIG. 13C , the fourth conductive layer of the first display area may include at least: a plurality of connection electrodes (eg, including first to ninth connection electrodes 401 to 409 , and eleventh to seventeenth connection electrodes 411 to 417 ).

[0203] In some examples, the shape of the first connection electrode 401 may be substantially rectangular.The first connection electrode 401 may be electrically connected to the fourth active layer of the fourth transistor 34a of the first pixel circuit 11a through the third via hole V3.

[0204] In some examples, the second connection electrode 402 can be shaped substantially like a strip extending along the second direction Y. One end of the second connection electrode 402 can be electrically connected to the second active layer of the second transistor 32a of the first pixel circuit 11a through a thirty-first via hole V31, and the other end can be electrically connected to the first electrode 391a of the storage capacitor through a twenty-first via hole V21. The second connection electrode 402 is electrically connected to the gate of the third transistor 33a, the first electrode 391a of the storage capacitor, and the first electrode of the second transistor 32a. The second connection electrode 402 can serve as the first node of the first pixel circuit 11a.

[0205] In some examples, the third connection electrode 403 may be shaped substantially like a strip extending along the second direction Y. One end of the third connection electrode 403 may be electrically connected to the first active layer of the first transistor 31 a of the first pixel circuit 11 a through the second via hole V2, and the other end may be electrically connected to the second active layer of the second transistor 32 a through the thirty-second via hole V32, and may also be electrically connected to the third active layer of the third transistor 33 a through the sixth via hole V6.

[0206] In some examples, the fourth connection electrode 404 may be shaped substantially like a zigzag line extending along the second direction Y. The fourth connection electrode 404 may be electrically connected to the fourth active layer of the fourth transistor 34 a of the first pixel circuit 11 a through a fourth via hole V4, and may also be electrically connected to the eighth active layer of the eighth transistor 38 a through an eighth via hole V8.

[0207] In some examples, the fifth connection electrode 405 may be shaped substantially like a strip extending along the second direction Y. The fifth connection electrode 405 may be electrically connected to the fifth active layer of the fifth transistor 35a of the first pixel circuit 11a through a fifth via hole V5, and may also be electrically connected to the second plate connection block 392-2 through a twenty-third via hole V23, thereby achieving electrical connection to the second electrode 392a of the storage capacitor.

[0208] In some examples, the shape of the sixth connection electrode 406 may be substantially rectangular.The sixth connection electrode 406 may be electrically connected to the sixth active layer of the sixth transistor 36a of the first pixel circuit 11a through a seventh via hole V7.

[0209] In some examples, the shape of the seventh connection electrode 407 can be substantially L-shaped. The seventh connection electrode 407 can be electrically connected to the eighth active layer of the eighth transistor 38a of the first pixel circuit 11a through the ninth via hole V9, and can also be electrically connected to the third initial signal line INIT3(i) through the twenty-sixth via hole V26.

[0210] In some examples, the eighth connection electrode 408 may be shaped substantially like a strip extending along the second direction Y. The eighth connection electrode 408 may be electrically connected to the seventh active layer of the seventh transistor 37 a of the first pixel circuit 11 a through a tenth via hole V10, and may also be electrically connected to the second initial signal line INIT2(i) through a twenty-seventh via hole V27.

[0211] In some examples, the shape of the ninth connection electrode 409 can be substantially an arch extending along the second direction Y. One end of the ninth connection electrode 409 can be electrically connected to the first active layer of the first transistor 31 a of the first pixel circuit 11 a through the first via hole V1, and can also be electrically connected to the first initial signal line INIT1(i) through the twenty-fifth via hole V25, and the other end can be electrically connected to the first active layer of the first transistor 31 b of the first pixel circuit 11 b through the eleventh via hole V11, and can also be electrically connected to the first initial signal line INIT1(i) through the twenty-eighth via hole V28.

[0212] In some examples, the eleventh connection electrode 411 may be substantially rectangular in shape. The eleventh connection electrode 411 may be electrically connected to the fourth active layer of the fourth transistor 34b of the first pixel circuit 11b through the thirteenth via hole V13.

[0213] In some examples, the twelfth connection electrode 412 can be shaped substantially like a strip extending along the second direction Y. One end of the twelfth connection electrode 412 can be electrically connected to the second active layer of the second transistor 32b of the first pixel circuit 11b via a thirty-third via hole V31, and the other end can be electrically connected to the first electrode 391b of the storage capacitor via a twenty-second via hole V22. The twelfth connection electrode 412 is electrically connected to the gate of the third transistor 33b, the first electrode 391b of the storage capacitor, and the first electrode of the second transistor 32b. The twelfth connection electrode 412 can serve as the first node of the first pixel circuit 11b.

[0214] In some examples, the thirteenth connection electrode 413 may be shaped substantially like a strip extending along the second direction Y. One end of the thirteenth connection electrode 413 may be electrically connected to the first active layer of the first transistor 31 b of the first pixel circuit 11 b through a twelfth via hole V12, and the other end may be electrically connected to the second active layer of the second transistor 32 b through a thirty-fourth via hole V34, and may also be electrically connected to the third active layer of the third transistor 33 b through a sixteenth via hole V16.

[0215] In some examples, the shape of the fourteenth connection electrode 414 can be substantially a zigzag shape extending along the second direction Y. The fourteenth connection electrode 414 can be electrically connected to the fourth active layer of the fourth transistor 34 b of the first pixel circuit 11 b through the fourteenth via hole V14, and can also be electrically connected to the eighth active layer of the eighth transistor 38 b through the eighteenth via hole V18.

[0216] In some examples, the shape of the fifteenth connection electrode 415 can be substantially a strip extending along the second direction Y. The fifteenth connection electrode 415 can be electrically connected to the fifth active layer of the fifth transistor 35b of the first pixel circuit 11b through the fifteenth via hole V15, and can also be electrically connected to another second plate connection block 392-2 through the twenty-fourth via hole V24, thereby achieving electrical connection with the second electrode 392b of the storage capacitor.

[0217] In some examples, the shape of the sixteenth connection electrode 416 may be substantially rectangular. The sixteenth connection electrode 416 may be electrically connected to the sixth active layer of the sixth transistor 36b of the first pixel circuit 11b through the seventeenth via hole V17.

[0218] In some examples, the shape of the seventeenth connection electrode 417 can be substantially L-shaped. The seventeenth connection electrode 417 can be electrically connected to the eighth active layer of the eighth transistor 38b of the first pixel circuit 11b through a nineteenth via hole V19, and can also be electrically connected to the third initial signal line INIT3(i) through a twenty-ninth via hole V29.

[0219] In some examples, within the first sub-region, the first pixel circuits 11a and 11b may be roughly symmetrical about the second center line O2, the first pixel circuits 11c and 11d may be roughly symmetrical about the third center line O3, and the first pixel circuits 11a and 11b, the first pixel circuits 11c and 11d may be roughly symmetrical about the first center line O1.

[0220] In some examples, the first pixel circuits within the plurality of first sub-regions arranged along the first direction X may be aligned in the first direction X, and the first pixel circuits within the plurality of first sub-regions arranged along the second direction Y may be aligned in the second direction Y. For example, four columns of first pixel circuits may be arranged within one column of first sub-regions.

[0221] (8) Forming a sixth insulating layer and a seventh insulating layer. In some examples, a sixth insulating film is deposited on the substrate on which the aforementioned pattern is formed, and then a seventh insulating film is coated. The seventh insulating film and the sixth insulating film are patterned by a patterning process to form the sixth insulating layer and the seventh insulating layer. In some examples, the sixth insulating layer may also be referred to as a passivation layer, and the seventh insulating layer may also be referred to as a first planarization layer.

[0222] Figure 14 is a schematic diagram of a first sub-region after the seventh insulating layer is formed in Figure 6. In some examples, as shown in Figure 14, the seventh insulating layer of the first display area can be provided with a plurality of vias, such as vias 41 to 46 (V41 to V46). The seventh and sixth insulating layers within vias 41 to 46 (V41 to V46) can be removed to expose a portion of the surface of the fourth conductive layer.

[0223] (9) Forming a fifth conductive layer. In some examples, a fifth conductive film is deposited on the substrate having the aforementioned pattern, and the fifth conductive film is patterned by a patterning process to form a fifth conductive layer on the seventh insulating layer. In some examples, the fifth conductive layer may also be referred to as a second source / drain metal layer.

[0224] Figure 15A is a schematic diagram of the first display area after the fifth conductive layer is formed in Figure 6. Figure 15B is a schematic diagram of the fifth conductive layer in Figure 15A. Figure 15C is a schematic diagram of a first sub-area in Figure 15A.

[0225] In some examples, as shown in Figures 15A to 15C, the fifth conductive layer of the first display area may include at least: multiple data lines (for example, data lines DL(j-4), DL(j-3), DL(j-2), DL(j-1), DL(j), DL(j+1), DL(j+2), DL(j+3), DL(j+4), DL(j+5), DL(j+6), DL(j+7)), multiple first anode connecting electrodes (for example, first anode connecting electrodes 422a, 422b, 422c and 422d), multiple first power connecting electrodes (for example, first power connecting electrodes 423a, 423b and 423c), and multiple first shielding electrodes (for example, first shielding electrodes 421a and 421b).

[0226] In some examples, the plurality of data lines may be roughly in the shape of a zigzag extending along the second direction Y. The four first sub-pixels in each first sub-region are electrically connected to the four data lines in a one-to-one correspondence. The data line DL(j) may be electrically connected to the first connection electrode 401 through the forty-first via V41, thereby being electrically connected to the fourth transistor of the first pixel circuit 11a. The data line DL(j+1) may be electrically connected to the eleventh connection electrode 411 through the forty-fifth via V45, thereby being electrically connected to the fourth transistor of the first pixel circuit 11b. The data line DL(j+2) may be electrically connected to the fourth transistor of the first pixel circuit 11c. The data line DL(j+3) may be electrically connected to the fourth transistor of the first pixel circuit 11d.

[0227] In some examples, the four data lines electrically connected to the four first pixel circuits in the first sub-region can be divided into two groups to bypass the second sub-region adjacent to the first sub-region in the second direction Y. For example, the data line DL(j) connected to the first pixel circuit 11a and the data line DL(j+1) connected to the first pixel circuit 11b can bypass the adjacent second sub-region in the second direction Y from the side opposite to the first direction X, and the data line DL(j+2) connected to the first pixel circuit 11c and the data line DL(j+2) connected to the first pixel circuit 11d can bypass the adjacent second sub-region in the second direction Y from the side of the first direction X. In this example, by setting the data lines to bend and bypass the second sub-region, the space occupied by the wiring is reduced, thereby improving the light transmittance of the first display area.

[0228] In some examples, the shape of the first anode connection electrodes 422a, 422b, 422c, and 422d can be substantially rectangular. The first anode connection electrodes 422a and 422b can be located between the data lines DL(j) and DL(j+1), and the first anode connection electrodes 422c and 422d can be located between the data lines DL(j+2) and DL(j+3).

[0229] In some examples, the first anode connection electrode 422a can be electrically connected to the sixth connection electrode 406 through the forty-third via hole V43, thereby achieving electrical connection with the sixth transistor of the first pixel circuit 11a. The first anode connection electrode 422b can be electrically connected to the sixteenth connection electrode 416 through the forty-sixth via hole V46, thereby achieving electrical connection with the sixth transistor of the first pixel circuit 11b. The first anode connection electrode 422c can be electrically connected to the sixth transistor of the first pixel circuit 11c. The first anode connection electrode 422d can be electrically connected to the sixth transistor of the first pixel circuit 11d.

[0230] In some examples, the shapes of the first power connection electrodes 423a, 423b, and 423c can be substantially rectangular. The first power connection electrode 423a can be located on one side of the data line DL(j) in the opposite direction of the first direction X, the first power connection electrode 423b can be located between the data lines DL(j+1) and DL(j+2), and the first power connection electrode 423c can be located on one side of the data line DL(j+3) in the first direction X.

[0231] In some examples, the first power connection electrode 423a can be electrically connected to the fifth connection electrode 405 through the forty-second via hole V42, thereby achieving electrical connection with the fifth transistor and storage capacitor of the first pixel circuit 11a. The second power connection electrode 423b can be electrically connected to the fifteenth connection electrode 415 through the forty-fourth via hole V44, thereby achieving electrical connection with the fifth transistor and storage capacitor of the first pixel circuits 11b and 11c. The third power connection electrode 423c can be electrically connected to the fifth transistor and storage capacitor of the first pixel circuit 11d.

[0232] In some examples, the shape of the first shielding electrodes 421a and 421b can be roughly n-shaped. The first shielding electrode 421a can be located between the data lines DL(j) and DL(j+1), and the first shielding electrode 421b can be located between the data lines DL(j+2) and DL(j+3). The orthographic projection of the first shielding electrode 421a on the substrate can cover the orthographic projection of the second connecting electrode 402 and the twelfth connecting electrode 412 on the substrate, which can block the first node of the first pixel circuit 11a and the first node of the first pixel circuit 11b, thereby shielding the influence of other signals on the first nodes of the first pixel circuits 11a and 11b. The second shielding electrode 421b can block the first node of the first pixel circuit 11c and the first node of the first pixel circuit 11d, thereby shielding the influence of other signals on the first nodes of the first pixel circuits 11c and 11d.

[0233] (10) Forming an eighth insulating layer. In some examples, an eighth insulating film is coated on the substrate having the aforementioned pattern, and the eighth insulating film is patterned by a patterning process to form the eighth insulating layer. In some examples, the eighth insulating layer may also be referred to as a second planar layer.

[0234] FIG16 is a schematic diagram of a first sub-region after the eighth insulating layer is formed in FIG6 . In some examples, as shown in FIG16 , the eighth insulating layer in the first display region may be provided with a plurality of vias, such as vias V51 through V59. The eighth insulating layer within vias V51 through V59 may be removed, exposing a portion of the surface of the fifth conductive layer.

[0235] (11) Forming a sixth conductive layer. In some examples, a sixth conductive film is deposited on the substrate having the aforementioned pattern, and the sixth conductive film is patterned by a patterning process to form a sixth conductive layer on the eighth insulating layer. In some examples, the sixth conductive layer may also be referred to as a third source / drain metal layer.

[0236] Figure 17A is a schematic diagram of the first display area after the sixth conductive layer is formed in Figure 6. Figure 17B is a schematic diagram of the sixth conductive layer in Figure 17A. Figure 17C is a schematic diagram of a first sub-area in Figure 17A.

[0237] In some examples, as shown in Figures 17A to 17C, the sixth conductive layer of the first display area may include at least: a plurality of second anode connecting electrodes (for example, second anode connecting electrodes 431a, 431b, 431c and 431d), a plurality of third anode connecting electrodes (for example, third anode connecting electrodes 432a, 432b, 432c and 432d), and a first power line 44.

[0238] In some examples, the first power lines 44 of the first display area can have a mesh structure. The first power lines 44 of the first sub-area can be substantially symmetrical about the first centerline O1. The first power lines 44 of the first sub-area can include: first extension segments 441a and 441b, second extension segments 442a and 442b, third extension segments 443a, 443b, and 443c, and fourth extension segments 444a and 444b. The first extension segments 441a and 441b, the second extension segments 442a and 442b, the third extension segments 443a, 443b, and 443c, and the fourth extension segments 444a and 444b can be interconnected and integral. The second sub-area can be surrounded by the first extension segments 441a and 441b within adjacent first sub-areas in the second direction Y and the fourth extension segments 444a and 44b within adjacent first sub-areas in the first direction X. The first extension segments, the third extension segments, and the fourth extension segments of the first power lines 44 in different first sub-areas may be electrically connected correspondingly to form a grid-like design within the entire first display.

[0239] In some examples, the first extension segments 441a and 441b may be shaped substantially like strips extending along the first direction X. The first extension segment 441a may be located on a side opposite to the first shielding electrodes 421a and 421b along the second direction Y, and the first extension segment 441b may be located on a side of the first shielding electrodes 421a and 421b along the second direction Y.

[0240] In some examples, the second extension segments 442a and 442b can be shaped substantially like strips extending along the second direction Y. The second extension segment 442a can be electrically connected to the first shielding electrode 421a via a fifty-first via V51, and the second extension segment 442b can be electrically connected to the first shielding electrode 421b via a fifty-second via V52. Both ends of the second extension segment 442a are electrically connected to the first extension segments 441a and 441b, respectively, and both ends of the second extension segment 442b can be electrically connected to the first extension segments 441a and 441b, respectively.

[0241] In some examples, the third extension segments 443a, 443b, and 443c can be shaped substantially like strips extending along the second direction Y. The third extension segment 443a can be electrically connected to the first power connection electrode 423a via a fifty-third via hole V53, the third extension segment 443b can be electrically connected to the first power connection electrode 423b via a fifty-fourth via hole V54, and the third extension segment 443c can be electrically connected to the first power connection electrode 423c via a fifty-fifth via hole V55. The ends of the third extension segment 443a can be electrically connected to the first extension segments 441a and 441b, respectively. The ends of the third extension segment 443b can be electrically connected to the first extension segments 441a and 441b, respectively. The ends of the third extension segment 443c can be electrically connected to the first extension segments 441a and 441b, respectively. The three third extension segments and the two second extension segments can be spaced apart along the first direction X.

[0242] In some examples, the fourth extension segments 444a and 444b can be shaped substantially like strips extending along the second direction Y. Both ends of the fourth extension segment 444a can be electrically connected to the first extension segments 441a and 441b, respectively, and both ends of the fourth extension segment 444b can be electrically connected to the first extension segments 441a and 441b, respectively. The fourth extension segment 444a is located on a side of the third extension segment 443a opposite to the first direction X, and the fourth extension segment 444b is located on a side of the third extension segment 443c in the first direction X.

[0243] In some examples, in the first sub-region, the two first extensions 441a and 441b, the two second extensions 442a and 442b, and the three third extensions 443a, 443b, and 443c of the first power line 44 can be connected to form four accommodating areas. The four accommodating areas correspond to the four first pixel circuits, and a second anode connection electrode can be disposed in each accommodating area.

[0244] The mesh design of the first power line in the first sub-area of ​​this example can ensure the symmetrical design of the circuit structure layer, thereby avoiding display differences under different viewing angles (such as left and right viewing angle differences) caused by the circuit structure layer.

[0245] In some examples, the second anode connection electrode 431a can be located in the accommodation area between the third extension section 443a and the second extension section 442a. The second anode connection electrode 431a can be shaped substantially like a dumbbell extending along the second direction Y. The second anode connection electrode 431a can be electrically connected to the first anode connection electrode 422a through the fifty-sixth via hole V56 to achieve electrical connection with the sixth transistor of the first pixel circuit 11a.

[0246] In some examples, the second anode connection electrode 431b can be located in the accommodation area between the third extension section 443b and the second extension section 442a. The second anode connection electrode 432b can be shaped substantially like a dumbbell extending along the second direction Y. The second anode connection electrode 431b can be electrically connected to the first anode connection electrode 422b through the fifty-seventh via hole V57, thereby achieving electrical connection with the sixth transistor of the first pixel circuit 11b.

[0247] In some examples, the second anode connection electrode 431c can be located in the accommodation area between the third extension section 443b and the second extension section 442b. The second anode connection electrode 432c can be shaped substantially like a dumbbell extending along the second direction Y. The second anode connection electrode 431c can be electrically connected to the first anode connection electrode 422c through the fifty-eighth via hole V58, thereby achieving electrical connection with the sixth transistor of the first pixel circuit 11c.

[0248] In some examples, the second anode connection electrode 431d can be located in the accommodation area between the third extension section 443c and the second extension section 442b. The second anode connection electrode 432d can be shaped substantially like a dumbbell extending in a direction intersecting both the first direction and the second direction. The second anode connection electrode 432d can be electrically connected to the first anode connection electrode 422d through the fifty-ninth via V59, thereby electrically connecting to the sixth transistor of the first pixel circuit 11d.

[0249] In some examples, the third anode connection electrodes 432a, 432b, 432c, and 432d are substantially rectangular in shape, with chamfered and rounded corners. The third anode connection electrodes 432a, 432b, 432c, and 432d can be located within an area surrounded by first extensions 441a and 441b adjacent in the second direction Y and fourth extensions 444a and 44b adjacent in the first direction X. The third anode connection electrodes 432a and 432b are aligned along the first direction X and are adjacent to the first extension 441a within one first sub-area in the second direction Y. The third anode connection electrodes 423c and 423d can be aligned along the first direction X and are adjacent to the first extension 441b within another first sub-area in the second direction Y.

[0250] (12) Forming a ninth insulating layer. In some examples, a ninth insulating film is coated on the substrate having the aforementioned pattern, and the ninth insulating film is patterned by a patterning process to form a ninth insulating layer. In some examples, the ninth insulating layer may also be referred to as a third planar layer.

[0251] FIG18 is a schematic diagram of the first display area after the ninth insulating layer is formed in FIG6 . In some examples, as shown in FIG18 , the ninth insulating layer in the first display area may have multiple vias, such as vias V61 through V68. The ninth insulating layer within vias V61 through V68 may be removed to expose a portion of the surface of the sixth conductive layer.

[0252] At this point, the circuit structure layer can be prepared. The film structure of the circuit structure layer in the second display area is similar to that of the first display area, so it will not be described in detail here.

[0253] (13) Forming a conductive connection layer. In some examples, a transparent conductive film is deposited on the substrate on which the aforementioned pattern is formed, and the transparent conductive film is patterned by a patterning process to form a conductive connection layer. In this example, a single conductive connection layer is used as an example for description. However, this embodiment is not limited to this. In other examples, multiple conductive connection layers may be provided, and a flat layer may be provided between adjacent conductive connection layers.

[0254] Fig. 19A is a schematic diagram of the first display area after the conductive connection layer is formed in Fig. 6. Fig. 19B is a schematic diagram of the conductive connection layer in Fig. 19A.

[0255] In some examples, as shown in Figures 19A and 19B, the conductive connection layer of the first display area can include: multiple conductive connection lines (e.g., conductive connection lines 15a, 15b, 15c and 15d), multiple fourth anode connection electrodes (e.g., fourth anode connection electrodes 461a, 461b, 461c and 461d).

[0256] In some examples, the shape of the fourth anode connection electrodes 461a, 461b, 461c, and 461d can be substantially rectangular, and the rectangle can have rounded or chamfered corners. The fourth anode connection electrode 461a can be electrically connected to the second anode connection electrode 431a through the sixty-first via hole V61. The fourth anode connection electrode 461b can be electrically connected to the second anode connection electrode 431b through the sixty-second via hole V62. The fourth anode connection electrode 461c can be electrically connected to the second anode connection electrode 431c through the sixty-third via hole V63. The fourth anode connection electrode 461d can be electrically connected to the second anode connection electrode 431d through the sixty-fourth via hole V64.

[0257] In some examples, the plurality of conductive connection lines can extend at least along a first direction X, can extend from the first display area to the second display area, and be electrically connected to the second pixel circuit in the second display area. Conductive connection line 15a can be electrically connected to the third anode connection electrode 432a through the sixty-fifth via V65, conductive connection line 15b can be electrically connected to the third anode connection electrode 432c through the sixty-sixth via V66, conductive connection line 15c can be electrically connected to the third anode connection electrode 432b through the sixty-seventh via V67, and conductive connection line 15d can be electrically connected to the third anode connection electrode 432d through the sixty-eighth via V68. The orthographic projection of the conductive connection line on the substrate can overlap with the orthographic projection of at least one first pixel circuit on the substrate. For example, the orthographic projections of the conductive connection lines 15a, 15b, 15c, and 15d on the substrate can all overlap with the orthographic projections of the four first pixel circuits connected to the four first light-emitting elements of the first light-emitting unit in the ath column and the b+1th row on the substrate.

[0258] In some examples, the conductive connection layer may be made of a transparent conductive material, such as ITO. Although the conductive connection line passes through the second sub-region, it can avoid affecting the light transmittance of the second sub-region.

[0259] (14) Forming a light-emitting structure layer. In some examples, a tenth insulating film is coated on the substrate on which the aforementioned pattern is formed, and the tenth insulating film is patterned by a patterning process to form a tenth insulating layer. The tenth insulating layer may have a plurality of vias, and the plurality of vias may expose a portion of the surface of the conductive connection layer. Subsequently, an anode film is deposited on the substrate on which the aforementioned pattern is formed, and the anode film is patterned by a patterning process to form an anode layer.

[0260] FIG20 is a schematic diagram of the first display area after the anode layer is formed in FIG6. In some examples, as shown in FIG20, the first display area may include: anodes of a plurality of first light-emitting elements (e.g., anode 211a of first light-emitting element 21a, anode 211b of first light-emitting element 21b, anode 211c of first light-emitting element 21c, and anode 211d of first light-emitting element 21d), and anodes of a plurality of second light-emitting elements (e.g., anode 221a of second light-emitting element 22a, anode 221b of second light-emitting element 22b, anode 221c of second light-emitting element 22c, and anode 221d of second light-emitting element 22d).

[0261] In some examples, the anode 211a of the first light-emitting element 21a emitting the first color light can be electrically connected to the fourth anode connection electrode 461a through a via hole provided in the tenth insulating layer. The anode 211b of the first light-emitting element 21b emitting the second color light can be electrically connected to the fourth anode connection electrode 461c through a via hole provided in the tenth insulating layer. The anode 211c of the first light-emitting element 21c emitting the third color light can be electrically connected to the fourth anode connection electrode 461b through a via hole provided in the tenth insulating layer. The anode 211d of the first light-emitting element 21d emitting the third color light can be electrically connected to the fourth anode connection electrode 461d through a via hole provided in the tenth insulating layer.

[0262] In some examples, the anode 221a of the second light-emitting element 22a emitting the first color light can be electrically connected to the conductive connection line 15c through a via hole provided in the tenth insulating layer. The anode 221b of the second light-emitting element 22b emitting the second color light can be electrically connected to the conductive connection line 15a through a via hole provided in the tenth insulating layer. The anode 221c of the second light-emitting element 22c emitting the third color light can be electrically connected to the conductive connection line 15b through a via hole provided in the tenth insulating layer. The anode 221d of the second light-emitting element 22d emitting the third color light can be electrically connected to the conductive connection line 15d through a via hole provided in the tenth insulating layer.

[0263] In some examples, a pixel definition film is applied to the substrate on which the aforementioned pattern is formed, and a mask, exposure, and development process are performed to form a pixel definition layer. The pixel definition layer may be formed with multiple pixel openings that expose the anode layer. An organic light-emitting layer is formed within the aforementioned pixel openings, and the organic light-emitting layer is connected to the anode layer. Subsequently, a cathode film is deposited and patterned using a patterning process to form a cathode pattern, and the cathode is connected to the organic light-emitting layer.

[0264] In some examples, as shown in FIG6 , the pixel definition layer of the first display area can form a plurality of first pixel openings (e.g., first pixel openings 210 a, 210 b, 210 c, and 210 d) and a plurality of second pixel openings (e.g., second pixel circuits 220 a, 220 b, 220 c, and 220 d). The shapes of the plurality of first pixel openings and the plurality of second pixel openings can be substantially circular.

[0265] In some examples, the first pixel opening 210a may expose a portion of the surface of the anode 211a, the first pixel opening 210b may expose a portion of the surface of the anode 211b, the first pixel opening 210c may expose a portion of the surface of the anode 211c, and the first pixel opening 210d may expose a portion of the surface of the anode 211d. The second pixel opening 220a may expose a portion of the surface of the anode 221a, the second pixel opening 220b may expose a portion of the surface of the anode 221b, the second pixel opening 220c may expose a portion of the surface of the anode 221c, and the second pixel opening 220d may expose a portion of the surface of the anode 221d.

[0266] In some examples, the light-emitting area of ​​first light-emitting element 21b emitting the second color light can be larger than the light-emitting area of ​​first light-emitting element 21a emitting the first color light. The light-emitting area of ​​first light-emitting element 21a emitting the first color light can be larger than the light-emitting area of ​​first light-emitting element 21c or 21d emitting the third color light. The light-emitting areas of first light-emitting elements 21c and 21d emitting the third color light can be the same. The light-emitting area of ​​a light-emitting element in this example can refer to the area of ​​the overlapping region of the anode, the organic light-emitting layer, and the cathode, exposed by the pixel opening of the pixel definition layer.

[0267] In some examples, the light-emitting area of ​​second light-emitting element 22b emitting the second color light can be larger than the light-emitting area of ​​second light-emitting element 22a emitting the first color light. The light-emitting area of ​​second light-emitting element 22a emitting the first color light can be larger than the light-emitting area of ​​second light-emitting element 22c or 22d emitting the third color light. The light-emitting areas of second light-emitting elements 22c and 22d emitting the third color light can be the same.

[0268] In some examples, the light-emitting area of ​​the first light-emitting element can be larger than the light-emitting area of ​​the second light-emitting element that emits light of the same color. For example, the ratio of the light-emitting areas of the second light-emitting element and the first light-emitting element that emit light of the same color can be 0.4 to 0.8, such as approximately 0.5. For example, the light-emitting area of ​​the second light-emitting element 22a that emits light of the first color can be approximately half the light-emitting area of ​​the first light-emitting element 21a that emits light of the first color. The light-emitting area of ​​the second light-emitting element 22b that emits light of the second color can be approximately half the light-emitting area of ​​the first light-emitting element 21b that emits light of the second color. The light-emitting area of ​​the second light-emitting element 22c (or 22d) that emits light of a third color can be approximately half the light-emitting area of ​​the first light-emitting element 21c (or 21d) that emits light of the third color.

[0269] This example reduces the light-emitting area of ​​the second light-emitting element, thereby reducing the dim brightness of the second light-emitting element caused by low current density due to a large load on the conductive connecting line, which is beneficial to improving the brightness of the second light-emitting element.

[0270] In some examples, the pixel definition layer of the first sub-region may be made of black material to shield the first pixel circuit and wiring of the first sub-region, and the pixel definition layer of the second sub-region may be made of transparent material to improve the light transmittance of the second sub-region. This embodiment is not limited to this.

[0271] In some examples, after the light emitting structure layer is prepared, an encapsulation layer may be formed on the cathode. The encapsulation layer may include a stacked structure of inorganic material / organic material / inorganic material.

[0272] In some examples, the first conductive layer, the second conductive layer, the third conductive layer, the fourth conductive layer, the fifth conductive layer, and the sixth conductive layer can be made of metal materials, such as any one or more of silver (Ag), copper (Cu), aluminum (Al), and molybdenum (Mo), or alloy materials of the above metals, such as aluminum neodymium alloy (AlNd) or molybdenum niobium alloy (MoNb), and can be a single layer structure or a multi-layer composite structure, such as Mo / Cu / Mo. The first insulating layer, the second insulating layer, the third insulating layer, the fourth insulating layer, the fifth insulating layer, and the sixth insulating layer can be made of any one or more of silicon oxide (SiOx, x>0), silicon nitride (SiNy, y>0), and silicon oxynitride (SiON), and can be a single layer, a multi-layer, or a composite layer. The seventh insulating layer, the eighth insulating layer, and the ninth insulating layer can be made of organic materials such as polyimide, acrylic, or polyethylene terephthalate. The pixel definition layer can be made of organic materials such as polyimide, acrylic, or polyethylene terephthalate. The anode layer may be made of a reflective material such as metal, and the cathode layer may be made of a transparent conductive material. However, this embodiment is not limited thereto.

[0273] The structure of the display substrate and its preparation process in this embodiment are merely illustrative. In some exemplary embodiments, the corresponding structure can be modified and patterning processes can be added or removed as needed. The preparation process of this exemplary embodiment can be implemented using currently available manufacturing equipment and is well compatible with existing manufacturing processes. The process is simple to implement, easy to implement, and has high production efficiency, low production costs, and a high yield rate.

[0274] In some examples, the structures of the second pixel circuit and the third pixel circuit in the second display area can be roughly the same as the structure of the first pixel circuit, the light-emitting areas of the third light-emitting element and the first light-emitting element that emit light of the same color can be roughly the same, and the structure of the third light-emitting element in the second display area can be roughly the same as the structure of the first light-emitting element, so they will not be repeated here.

[0275] The display substrate provided in this example has a built-in first pixel circuit connected to the first light-emitting element in the first display area, and an external second pixel circuit connected to the second light-emitting element. The light-emitting elements external to the pixel circuit and the light-emitting elements built into the pixel circuit can be reasonably arranged to achieve an optimal combination of light transmittance and size in the first display area, thereby improving the performance of the display substrate and user experience.

[0276] Figure 21 is another example diagram of the first display area of ​​at least one embodiment of the present disclosure. In some examples, as shown in Figure 21, the first sub-area A11 and the second sub-area A12 of the first display area can be spaced apart along the second direction Y. The first sub-area A11 can include a row of first light-emitting units 2a (including a plurality of first light-emitting units 2a arranged sequentially along the first direction X), and the second sub-area A12 can include a row of second light-emitting units 2b (including a plurality of second light-emitting units 2b arranged sequentially along the first direction X). In the second direction Y, the first light-emitting units 2a and the second light-emitting units 2b can be aligned and spaced apart.

[0277] In some examples, as shown in FIG21 , a first light-emitting unit 2a may include a first light-emitting element 21a that emits a first color of light, a first light-emitting element 21b that emits a second color of light, and two first light-emitting elements 21c and 21d that emit a third color of light. A second light-emitting unit 2b may include a second light-emitting element 22a that emits a first color of light, a second light-emitting element 22b that emits a second color of light, and two second light-emitting elements 22c and 22d that emit a third color of light. The arrangement of the light-emitting elements in this example can be referred to the description of the previous embodiment and will not be repeated here.

[0278] The display substrate of this example, by providing a row of first light-emitting units and a row of second light-emitting units spaced apart in the second direction, can rationally arrange the light-emitting elements external to the pixel circuit and the light-emitting elements internal to the pixel circuit, thereby achieving an optimal combination of light transmittance and size in the first display area, thereby improving the performance of the display substrate and user experience. The remaining description of the display substrate of this example can be referred to the description of the previous embodiment, and is therefore not repeated here.

[0279] Figure 22 is another example diagram of the first display area of ​​at least one embodiment of the present disclosure. In some examples, as shown in Figure 22, the first sub-area A11 and the second sub-area A12 of the first display area can be spaced apart along the first direction X. The first sub-area A11 can include a column of first light-emitting units 2a (including a plurality of first light-emitting units 2a arranged sequentially along the second direction Y), and the second sub-area A12 can include a column of second light-emitting units 2b (including a plurality of second light-emitting units 2b arranged sequentially along the second direction Y). In the first direction X, the first light-emitting units 2a and the second light-emitting units 2b can be aligned and spaced apart.

[0280] The display substrate of this example, by providing a row of first light-emitting units and a row of second light-emitting units spaced apart in the first direction, can rationally arrange the light-emitting elements external to the pixel circuit and the light-emitting elements internal to the pixel circuit, thereby achieving an optimal combination of light transmittance and size in the first display area, thereby improving the performance of the display substrate and user experience. The remaining description of the display substrate of this example can be referred to the description of the previous embodiment, and will not be repeated here.

[0281] Figure 23 is another example diagram of the first display area of ​​at least one embodiment of the present disclosure. In some examples, as shown in Figure 23, the first sub-area A11 and the second sub-area A12 of the first display area can be spaced apart in both the first direction X and the second direction Y. The first sub-area A11 may include two first light-emitting units 2a arranged sequentially along the first direction X, and the second sub-area A12 may include two second light-emitting units 2b arranged sequentially along the first direction X. In the first direction X, the two first light-emitting units 2a and the two second light-emitting units 2b can be aligned and spaced apart. In the second direction Y, one first light-emitting unit 2a and one second light-emitting unit 2b can be aligned and spaced apart. However, this embodiment is not limited to this. In other examples, the two first light-emitting units and the second light-emitting unit can be spaced apart in the first direction, or the two first light-emitting units and the second light-emitting unit can be spaced apart in the second direction.

[0282] The display substrate of this example, by providing two first light-emitting units and two second light-emitting units spaced apart in the first and second directions, can rationally arrange the light-emitting elements external to the pixel circuit and the light-emitting elements internal to the pixel circuit, thereby achieving an optimal combination of light transmittance and size in the first display area, thereby improving the performance of the display substrate and user experience. The remaining description of the display substrate of this example can be referred to the description of the previous embodiment, and is therefore not repeated here.

[0283] Figure 24 is another example diagram of the first display area of ​​at least one embodiment of the present disclosure. In some examples, as shown in Figure 24, the first sub-area A11 and the second sub-area A12 of the first display area can be spaced apart along the first direction X and the second direction Y. The first sub-area A11 can include a first light-emitting unit 2a, and the second sub-area A12 can include a second light-emitting unit 2b. In the second direction Y, the first light-emitting unit 2a and the second light-emitting unit 2b can be aligned and spaced apart. In the first direction X, the first light-emitting unit 2a and the second light-emitting unit 2b can be aligned and spaced apart.

[0284] In some examples, as shown in FIG24 , the first light-emitting unit 2a may include: a first light-emitting element 21a that emits a first color light; a first light-emitting element 21b that emits a second color light; and two first light-emitting elements 21c and 21d that emit a third color light. The first light-emitting elements 21a and 21b may be arranged alternately in the same column of light-emitting elements, the first light-emitting elements 21c and 21d may be arranged alternately in the same column of light-emitting elements, or the first light-emitting elements 21a, 21b, 21c, and 21d may be arranged in different rows of light-emitting elements.

[0285] In some examples, as shown in FIG24 , the second light-emitting unit 2b may include: a second light-emitting element 22a that emits a first color light; a second light-emitting element 22b that emits a second color light; and two second light-emitting elements 22c and 22d that emit a third color light. The second light-emitting elements 22a and 22b may be arranged alternately in the same column of light-emitting elements, the second light-emitting elements 22c and 22d may be arranged alternately in the same column of light-emitting elements, or the second light-emitting elements 22a, 22b, 22c, and 22d may be arranged in different rows of light-emitting elements.

[0286] The display substrate of this example, by arranging first light-emitting units (including four first light-emitting elements arranged in two columns vertically) and second light-emitting units (including four second light-emitting elements arranged in two columns vertically) spaced apart in both the first and second directions, can rationally arrange the light-emitting elements external to the pixel circuit and the light-emitting elements internal to the pixel circuit to achieve an optimal combination of light transmittance and size in the first display area, thereby improving the performance of the display substrate and user experience. The remaining description of the display substrate of this example can be referred to the description of the aforementioned embodiment, and therefore will not be repeated here.

[0287] Figure 25 is another example diagram of the first display area of ​​at least one embodiment of the present disclosure. In some examples, as shown in Figure 25, the first sub-area A11 and the second sub-area A12 of the first display area can be spaced apart along the first direction X. The first sub-area A11 can include a column of first light-emitting units 2a (including a plurality of first light-emitting units 2a arranged sequentially along the second direction Y), and the second sub-area A12 can include a column of second light-emitting units 2b (including a plurality of second light-emitting units 2b arranged sequentially along the second direction Y). In the first direction X, the first light-emitting units 2a and the second light-emitting units 2b can be aligned and spaced apart.

[0288] The display substrate of this example, by arranging first light-emitting units (including four first light-emitting elements arranged in two columns vertically) and second light-emitting units (including four second light-emitting elements arranged in two columns vertically) spaced apart in the first direction, can rationally arrange the light-emitting elements external to the pixel circuit and the light-emitting elements internal to the pixel circuit to achieve an optimal combination of light transmittance and size in the first display area, thereby improving the performance of the display substrate and user experience. The remaining description of the display substrate of this example can be referred to the description of the aforementioned embodiment, and therefore will not be repeated here.

[0289] Figure 26 is another example diagram of the first display area of ​​at least one embodiment of the present disclosure. In some examples, as shown in Figure 26, the first sub-area A11 and the second sub-area A12 of the first display area can be spaced apart along the second direction Y. The first sub-area A11 can include a row of first light-emitting units 2a (including a plurality of first light-emitting units 2a arranged sequentially along the first direction X), and the second sub-area A12 can include a row of second light-emitting units 2b (including a plurality of second light-emitting units 2b arranged sequentially along the first direction X). In the second direction Y, the first light-emitting units 2a and the second light-emitting units 2b can be aligned and spaced apart.

[0290] The display substrate of this example, by arranging first light-emitting units (including four first light-emitting elements arranged in two columns vertically) and second light-emitting units (including four second light-emitting elements arranged in two columns vertically) spaced apart in the second direction, can rationally arrange the light-emitting elements external to the pixel circuit and the light-emitting elements internal to the pixel circuit to achieve an optimal combination of light transmittance and size in the first display area, thereby improving the performance of the display substrate and user experience. The remaining description of the display substrate of this example can be referred to the description of the aforementioned embodiment, and therefore will not be repeated here.

[0291] Figure 27 is another example diagram of the first display area of ​​at least one embodiment of the present disclosure. In some examples, as shown in Figure 27, the first sub-area A11 and the second sub-area A12 of the first display area can be spaced apart along the first direction X and the second direction Y. The first sub-area A11 can include a first light-emitting unit 2a, and the second sub-area A12 can include a second light-emitting unit 2b. In the second direction Y, the first light-emitting unit 2a and the second light-emitting unit 2b can be aligned and spaced apart. In the first direction X, the first light-emitting unit 2a and the second light-emitting unit 2b can be aligned and spaced apart.

[0292] In some examples, as shown in FIG27 , the first light-emitting unit 2a may include: a first light-emitting element 21a that emits a first color light; a first light-emitting element 21b that emits a second color light; and a first light-emitting element 21c that emits a third color light. The first light-emitting elements 21a and 21b may be arranged alternately in the same column of light-emitting elements, the first light-emitting element 21c may be arranged in the same column of light-emitting elements, or the first light-emitting elements 21a, 21b, and 21c may be arranged in different rows of light-emitting elements. The three first light-emitting elements of the first light-emitting unit 2a are arranged in a roughly triangular shape.

[0293] In some examples, as shown in FIG27 , the second light-emitting unit 2b may include: a second light-emitting element 22a emitting a first color light; a second light-emitting element 22b emitting a second color light; and second light-emitting elements 22c and 22d emitting a third color light. Second light-emitting elements 22a and 22b may be arranged alternately in the same column of light-emitting elements, second light-emitting element 22c may be arranged in the same column of light-emitting elements, and second light-emitting elements 22a, 22b, and 22d may be arranged in different rows of light-emitting elements. The three first light-emitting elements of the second light-emitting unit 2b are arranged in a roughly triangular shape.

[0294] The display substrate of this example, by arranging the first light-emitting unit (including three first light-emitting elements arranged in a triangular pattern) and the second light-emitting unit (including three second light-emitting elements arranged in a triangular pattern) spaced apart in both the first and second directions, can rationally arrange the light-emitting elements external to the pixel circuit and the light-emitting elements internal to the pixel circuit to achieve an optimal combination of light transmittance and size in the first display area, thereby improving the performance of the display substrate and user experience. The remaining description of the display substrate of this example can be referred to the description of the aforementioned embodiment, and therefore will not be repeated here.

[0295] Figure 28 is another example diagram of the first display area of ​​at least one embodiment of the present disclosure. In some examples, as shown in Figure 28, the first sub-area A11 and the second sub-area A12 of the first display area can be spaced apart along the second direction Y. The first sub-area A11 can include a row of first light-emitting units 2a, and the second sub-area A12 can include a row of second light-emitting units 2b. In the second direction Y, the first light-emitting units 2a and the second light-emitting units 2b can be aligned and spaced apart.

[0296] The display substrate of this example, by arranging first light-emitting units (including three first light-emitting elements arranged in a triangular pattern) and second light-emitting units (including three second light-emitting elements arranged in a triangular pattern) spaced apart in the second direction, can rationally arrange the light-emitting elements external to the pixel circuit and the light-emitting elements internal to the pixel circuit to achieve an optimal combination of light transmittance and size, thereby improving the performance of the display substrate and user experience. The remaining description of the display substrate of this example can be referred to the description of the aforementioned embodiment, and therefore will not be repeated here.

[0297] Figure 29 is another example diagram of the first display area of ​​at least one embodiment of the present disclosure. In some examples, as shown in Figure 29, the first sub-area A11 and the second sub-area A12 of the first display area can be spaced apart along the first direction X. The first sub-area A11 can include a column of first light-emitting units 2a, and the second sub-area A12 can include a column of second light-emitting units 2b. In the first direction X, the first light-emitting units 2a and the second light-emitting units 2b can be aligned and spaced apart.

[0298] The display substrate of this example, by arranging first light-emitting units (including three first light-emitting elements arranged in a triangular pattern) and second light-emitting units (including three second light-emitting elements arranged in a triangular pattern) spaced apart in a first direction, can rationally arrange the light-emitting elements external to the pixel circuit and the light-emitting elements internal to the pixel circuit to achieve an optimal combination of light transmittance and size in the first display area, thereby improving the performance of the display substrate and user experience. The remaining description of the display substrate of this example can be referred to the description of the aforementioned embodiment, and therefore will not be repeated here.

[0299] Figure 30 is another example diagram of the first display area of ​​at least one embodiment of the present disclosure. In some examples, as shown in Figure 30 , the first sub-area A11 and the second sub-area A12 of the first display area can be spaced apart along both the first direction X and the second direction Y. The first sub-area A11 can include a first light-emitting unit 2a, and the second sub-area A12 can include a second light-emitting unit 2b. In the first direction X and the second direction Y, the first light-emitting unit 2a and the second light-emitting unit 2b can be aligned and spaced apart.

[0300] In some examples, as shown in FIG30 , the first light-emitting unit 2a may include: a first light-emitting element 21a that emits light of a first color, a first light-emitting element 21b that emits light of a second color, and a first light-emitting element 21c that emits light of a third color. The first light-emitting elements 21a, 21c, and 21b may be arranged sequentially along the first direction X. The second light-emitting unit 2b may include: a second light-emitting element 22a that emits light of the first color, a second light-emitting element 22b that emits light of the second color, and second light-emitting elements 22c and 22d that emit light of a third color. The second light-emitting elements 22a, 22c, and 22b may be arranged sequentially along the first direction X. The light-emitting elements in this example may be periodically arranged along the first direction X, with the light-emitting element emitting the first color, the light-emitting element emitting the third color, and the light-emitting element emitting the second color serving as a repeating unit. In the second direction Y, light-emitting elements emitting light of the same color may be aligned.

[0301] The display substrate of this example, by arranging the first light-emitting unit (including three first light-emitting elements arranged along the first direction) and the second light-emitting unit (including three second light-emitting elements arranged along the first direction) spaced apart in both the first and second directions, can rationally arrange the light-emitting elements external to the pixel circuit and the light-emitting elements internal to the pixel circuit to achieve an optimal combination of light transmittance and size in the first display area, thereby improving the performance of the display substrate and user experience. The remaining description of the display substrate of this example can be referred to the description of the aforementioned embodiment, and therefore will not be repeated here.

[0302] Figure 31 is another example diagram of the first display area of ​​at least one embodiment of the present disclosure. In some examples, as shown in Figure 31, the first sub-area A11 and the second sub-area A12 of the first display area can be spaced apart along the second direction Y. The first sub-area A11 can include a row of first light-emitting units 2a, and the second sub-area A12 can include a row of second light-emitting units 2b. In the second direction Y, the first light-emitting units 2a and the second light-emitting units 2b can be aligned and spaced apart. However, this embodiment is not limited to this. In other examples, the first sub-area and the second sub-area can be spaced apart along the first direction X. The first sub-area can include a column of first light-emitting units, and the second sub-area can include a column of second light-emitting units.

[0303] The display substrate of this example, by providing a first light-emitting unit (including three first light-emitting elements arranged along a first direction) and a second light-emitting unit (including three second light-emitting elements arranged along the first direction) spaced apart in a second direction, can rationally arrange the light-emitting elements external to the pixel circuit and the light-emitting elements internal to the pixel circuit to achieve an optimal combination of light transmittance and size in the first display area, thereby improving the performance of the display substrate and user experience. The remaining description of the display substrate of this example can be referred to the description of the aforementioned embodiment, and therefore will not be repeated here.

[0304] Figure 32 is another example diagram of the first display area of ​​at least one embodiment of the present disclosure. In some examples, as shown in Figure 32, the light-emitting elements of the first display area can be arranged periodically along the first direction X according to the light-emitting elements emitting the second color light (e.g., blue light B), the light-emitting elements emitting the first color light (e.g., red light R), and the light-emitting elements emitting the third color light (e.g., green light G) as a repeating unit. In the second direction Y, the light-emitting elements emitting the same color light can be staggered. Among them, the light-emitting elements emitting the second color light in a row of repeating units can be aligned in the second direction Y with the light-emitting elements emitting the first color light in the previous row of repeating units. Adjacent rows of light-emitting elements can be arranged in a manner that staggers one light-emitting element in the second direction Y.

[0305] In some examples, as shown in FIG32 , the first sub-area A11 and the second sub-area A12 of the first display area may be spaced apart in a fourth direction D4 that intersects both the first direction X and the second direction Y. The first sub-area A11 may include a plurality of first light-emitting units 2a sequentially arranged along a third direction D3, and the second sub-area A12 may include a plurality of second light-emitting units 2b sequentially arranged along the third direction D3. The third direction D3 and the fourth direction D4 may intersect, for example, may be perpendicular to each other. The first light-emitting unit 2a may include three first light-emitting elements, and the second light-emitting unit 2b may include three second light-emitting elements.

[0306] The display substrate of this example, by arranging the first light-emitting unit (including three first light-emitting elements arranged along the first direction) and the second light-emitting unit (including three second light-emitting elements arranged along the first direction) to be spaced apart in a fourth direction intersecting both the first and second directions, can rationally arrange the light-emitting elements external to the pixel circuit and the light-emitting elements internal to the pixel circuit to achieve an optimal combination of light transmittance and size in the first display area, thereby improving the performance of the display substrate and user experience. The remaining description of the display substrate of this example can be referred to the description of the aforementioned embodiment, and therefore will not be repeated here.

[0307] Figure 33 is another example diagram of the first display area of ​​at least one embodiment of the present disclosure. In some examples, as shown in Figure 33, the light-emitting elements in the first display area can be arranged periodically along the first direction X according to the light-emitting elements emitting the first color light (e.g., blue light R), the light-emitting elements emitting the second color light (e.g., blue light B), and the light-emitting elements emitting the third color light (e.g., green light G) as a repeating unit, and in the second direction Y, the light-emitting elements emitting the same color light can be staggered. Among them, the light-emitting elements emitting the first color light in a row of repeating units can be aligned in the second direction with the center lines of the light-emitting elements emitting the second color light and the light-emitting elements emitting the third color light in the previous row of repeating units. Adjacent rows of light-emitting elements can be arranged in a manner that staggers 1.5 light-emitting elements in the second direction Y.

[0308] In some examples, as shown in FIG33 , the first sub-region A11 and the second sub-region A12 of the first display area may be spaced apart in the first direction X. The first sub-region A11 may include a plurality of first light-emitting units 2a sequentially arranged along the second direction Y, and adjacent first light-emitting units 2a may be staggered. The second sub-region A12 may include a plurality of second light-emitting units 2b sequentially arranged along the second direction Y, and adjacent second light-emitting units 2b may be staggered. The first light-emitting unit 2a may include three first light-emitting elements, and the second light-emitting unit 2b may include three second light-emitting elements.

[0309] The display substrate of this example, by providing a first light-emitting unit (including three first light-emitting elements arranged along a first direction) and a second light-emitting unit (including three second light-emitting elements arranged along the first direction) spaced apart in the first direction, can rationally arrange the light-emitting elements external to the pixel circuit and the light-emitting elements internal to the pixel circuit to achieve an optimal combination of light transmittance and size in the first display area, thereby improving the performance of the display substrate and user experience. The remaining description of the display substrate of this example can be referred to the description of the aforementioned embodiment, and therefore will not be repeated here.

[0310] Figure 34 is another example diagram of the first display area of ​​at least one embodiment of the present disclosure. In some examples, as shown in Figure 34, multiple first light-emitting units 2a and multiple second light-emitting units 2b in the first display area can be arranged at intervals in multiple circumferential areas with the center of the first display area as the center of the circle. The first sub-area A11 and the second sub-area A12 can be arranged at intervals along the direction from the center of the circle to the edge. The first sub-area A11 may include at least one first light-emitting unit 2a, and the second sub-area A12 may include multiple second light-emitting units 2b. Along the direction from the center of the circle to the edge, the number of first light-emitting units 2a in different first sub-areas A11 may gradually increase, and the number of first light-emitting units 2b in different second sub-areas A12 may gradually increase. The first light-emitting unit 2a may include three or four first light-emitting elements, and the second light-emitting unit 2b may include three or four second light-emitting elements. This embodiment is not limited to this.

[0311] The display substrate of this example utilizes a first light-emitting unit and a second light-emitting unit spaced from the center to the edge of the circle, and rationally arranges the light-emitting elements external to the pixel circuit and the light-emitting elements internal to the pixel circuit to achieve an optimal combination of light transmittance and size in the first display area, thereby improving the performance of the display substrate and user experience. The remaining description of the display substrate of this example can be referred to the description of the previous embodiment, and will not be repeated here.

[0312] FIG35 is another example diagram of the first display area of ​​at least one embodiment of the present disclosure. In some examples, as shown in FIG35 , the light-emitting elements in the first display area can be arranged in the following manner: multiple light-emitting elements emitting third color light (e.g., green light G) are arranged in multiple rows and columns, light-emitting elements emitting first color light (e.g., red light R) and second color light (e.g., blue light B) are arranged alternately in the row and column directions, and light-emitting elements emitting first color light and light-emitting elements emitting third color light are arranged in different rows and columns.

[0313] In some examples, as shown in FIG35 , the first light-emitting unit may include a first light-emitting element, and the second light-emitting unit may include a first second light-emitting element. In the first direction X, a first light-emitting unit and a second light-emitting unit are arranged at intervals. Among them, in a row of light-emitting elements, the first light-emitting element and the second light-emitting element are arranged at intervals. For example, the first light-emitting element that emits the third color light (G) is arranged at intervals; the first light-emitting element that emits the first color light (R) and the second light-emitting element that emits the second color light (B) are arranged at intervals, or the first light-emitting element that emits the second color light (B) and the second light-emitting element that emits the first color light (R) are arranged at intervals.

[0314] In some examples, in the second direction Y, one first light-emitting unit and one second light-emitting unit are alternately arranged, or two first light-emitting units and two second light-emitting units are alternately arranged. In one column of light-emitting elements, the first light-emitting element emitting the third color light (G) and the second light-emitting element emitting the third color light (G) are alternately arranged one by one; in another column of light-emitting elements, two first light-emitting elements (including the first light-emitting element emitting the first color light (R) and the first light-emitting element emitting the first color light (B)) and two second light-emitting elements (including the second light-emitting element emitting the first color light (R) and the first light-emitting element emitting the second color light (B)) are alternately arranged.

[0315] The display substrate of this example is configured such that a single first light-emitting element and a single second light-emitting element are spaced apart in the first direction, and a single first light-emitting element and a single first light-emitting element, or two first light-emitting elements and two second light-emitting elements, are spaced apart in the second direction. The light-emitting elements external to the pixel circuit and the light-emitting elements internal to the pixel circuit are rationally arranged to achieve an optimal combination of light transmittance and size in the first display area, thereby improving the performance of the display substrate and user experience. The remaining description of the display substrate of this example can be referred to the description of the aforementioned embodiment, and therefore will not be repeated here.

[0316] Figure 36 is a schematic diagram of a display device according to at least one embodiment of the present disclosure. As shown in Figure 36 , this embodiment provides a display device comprising: a display substrate 91; and a sensor 92 located on the light-emitting side of the light-emitting structure layer, away from the display substrate 91. Sensor 92 may be located on the non-display surface of the display substrate 91. The orthographic projection of sensor 92 on the display substrate 91 may overlap with the first display area A1.

[0317] In some examples, the display substrate 91 may be a flexible OLED display substrate, a QLED display substrate, a Micro-LED display substrate, or a Mini-LED display substrate. The display device may be a product having an image (including a static image or a dynamic image, wherein the dynamic image may be a video) display function. For example, the display device may be: a display, a television, a billboard, a digital photo frame, a laser printer with a display function, a telephone, a mobile phone, a painting screen, a personal digital assistant (PDA), a digital camera, a portable camcorder, a viewfinder, a navigator, a vehicle, a large-area wall, an information query device (such as business query equipment for e-government, banks, hospitals, power departments, etc.), a monitor, and the like. For another example, the display device may also be a microdisplay, a VR device or an AR device containing a microdisplay, and the like.

[0318] The drawings in this disclosure only relate to the structures involved in this disclosure, and other structures can refer to the general design. In the absence of conflict, the embodiments of the present disclosure, that is, the features in the embodiments, can be combined with each other to obtain new embodiments. It should be noted that the above-mentioned embodiments or implementation methods are merely exemplary and not restrictive. Therefore, the present disclosure is not limited to the contents shown and described in detail herein. Various modifications, replacements or omissions can be made to the form and details of the implementation without departing from the scope of this disclosure.

Claims

1. A display substrate, include: A substrate, comprising a first display area and a second display area located at at least one side of the first display area; A plurality of first light-emitting units and a plurality of second light-emitting units are located in the first display area; the first light-emitting unit includes at least one first light-emitting element, and the second light-emitting unit includes at least one second light-emitting element; the first light-emitting unit is adjacent to at least one second light-emitting unit; A plurality of first pixel circuits are located in the first display area; at least one first pixel circuit among the plurality of first pixel circuits is electrically connected to the at least one first light-emitting element and is configured to drive the at least one first light-emitting element to emit light; A plurality of second pixel circuits, located in the second display area; At least one second pixel circuit among the plurality of second pixel circuits is electrically connected to the at least one second light emitting element and is configured to drive the at least one second light emitting element to emit light.

2. The display substrate according to claim 1, in, The plurality of first light emitting units and the plurality of second light emitting units are arranged at intervals along at least one of a first direction and a second direction; the first direction intersects the second direction.

3. The display substrate according to claim 2, in, In the first direction, a first light emitting unit and a second light emitting unit are arranged at intervals; in the second direction, a first light emitting unit and a second light emitting unit are arranged at intervals.

4. The display substrate according to claim 2, in, The plurality of first light emitting units include: a plurality of columns of first light emitting units; each column of first light emitting units includes a plurality of first light emitting units sequentially arranged along the second direction; The plurality of second light emitting units include: a plurality of columns of second light emitting units, each column of second light emitting units includes a plurality of second light emitting units sequentially arranged along the second direction; In the first direction, a column of first light emitting units and a column of second light emitting units are arranged at intervals.

5. The display substrate according to claim 2, in, The plurality of first light emitting units include a plurality of rows of first light emitting units, and each row of first light emitting units includes a plurality of first light emitting units sequentially arranged along the first direction; The plurality of second light emitting units include a plurality of rows of second light emitting units, and each row of second light emitting units includes a plurality of second light emitting units sequentially arranged along the first direction; In the second direction, a row of first light emitting units and a row of second light emitting units are arranged at intervals.

6. The display substrate according to claim 2, in, The first light emitting unit and the second light emitting unit adjacent to each other in the first direction are aligned and arranged, and the first light emitting unit and the second light emitting unit adjacent to each other in the second direction are aligned and arranged; Alternatively, the first light emitting unit and the second light emitting unit adjacent to each other in the second direction are misaligned.

7. The display substrate according to any one of claims 1 to 6, in, The ratio of the light emitting areas of the second light emitting element and the first light emitting element that emit light of the same color is less than 1.

8. The display substrate according to any one of claims 1 to 7, in, The number of first light-emitting elements included in the at least one first light-emitting unit is the same as the number of second light-emitting elements included in the at least one second light-emitting unit.

9. The display substrate according to claim 8, in, The at least one first light-emitting unit includes the following four first light-emitting elements: a first light-emitting element emitting a first color light, a first light-emitting element emitting a second color light, and two first light-emitting elements emitting a third color light; The at least one second light emitting unit includes the following four second light emitting elements: one second light emitting element emitting first color light, one second light emitting element emitting second color light, and two second light emitting elements emitting third color light.

10. The display substrate according to claim 9, in, The plurality of first light emitting elements and the plurality of second light emitting elements in the first display area are arranged in a plurality of rows and columns; In the at least one first light-emitting unit, the two first light-emitting elements emitting the third color light are arranged in the same column, the first light-emitting element emitting the first color light and the first light-emitting element emitting the second color light are arranged in the same column, and the four first light-emitting elements of the first light-emitting unit are arranged in different rows; In the at least one second light-emitting unit, the two second light-emitting elements emitting third color light are arranged in the same column, the second light-emitting element emitting first color light and the second light-emitting element emitting second color light are arranged in the same column, and the four first light-emitting elements of the second light-emitting unit are arranged in different rows.

11. The display substrate according to claim 9, in, The plurality of first light emitting elements and the plurality of second light emitting elements in the first display area are arranged in a plurality of rows and columns; In the at least one first light-emitting unit, the two first light-emitting elements emitting the third color light are arranged in the same row, the first light-emitting element emitting the first color light and the first light-emitting element emitting the second color light are arranged in the same row, and the four first light-emitting elements of the first light-emitting unit are arranged in different columns; In the at least one second light-emitting unit, the two second light-emitting elements emitting the third color light are arranged in the same row, the first light-emitting element emitting the first color light and the second light-emitting element emitting the second color light are arranged in the same row, and the four second light-emitting elements of the second light-emitting unit are arranged in different columns.

12. The display substrate according to claim 11, in, The four first light-emitting elements in the first light-emitting unit are electrically connected to the four first pixel circuits in a one-to-one correspondence. The four first pixel circuits are arranged in sequence along the first direction, and the orthographic projection of each first pixel circuit on the substrate at least partially overlaps with the orthographic projection of the connected first light-emitting element on the substrate.

13. The display substrate according to claim 12, in, The four first pixel circuits are symmetrically arranged about the first center line of the four first pixel circuits along the first direction, the first first pixel circuit and the second first pixel circuit among the four first pixel circuits are symmetrically arranged about the second center line of the two first pixel circuits along the first direction, and the third first pixel circuit and the fourth first pixel circuit are symmetrically arranged about the third center line of the two first pixel circuits along the first direction.

14. The display substrate according to claim 12, in, The four first pixel circuits are electrically connected to first power lines, and the first power lines are in a grid shape in the first display area.

15. The display substrate according to claim 12 or 13, in, In a direction perpendicular to the display substrate, the display substrate comprises: a circuit structure layer located on the substrate; the circuit structure layer comprises the plurality of first pixel circuits and the plurality of second pixel circuits; each of the plurality of first pixel circuits and the plurality of second pixel circuits comprises: at least one first type transistor, at least one second type transistor and a storage capacitor; The circuit structure layer includes: a first semiconductor layer, a first conductive layer, a second conductive layer, a second semiconductor layer, a third conductive layer, a fourth conductive layer, a fifth conductive layer and a sixth conductive layer arranged on the substrate; The first semiconductor layer includes at least: an active layer of a first type transistor of the pixel circuit; The first conductive layer at least includes: a gate of a first type transistor of the pixel circuit and a first electrode of a storage capacitor; The second conductive layer at least includes: a second electrode of the storage capacitor of the pixel circuit; The second semiconductor layer at least includes: an active layer of a second type transistor of the pixel circuit; The third conductive layer at least includes: a gate of the second type transistor of the pixel circuit; The fourth conductive layer at least includes: a plurality of connecting electrodes; The fifth conductive layer at least includes: a plurality of data lines; The sixth conductive layer at least includes: a first power line.

16. The display substrate according to claim 15, in, The first display area includes: a plurality of first sub-areas and a plurality of second sub-areas; at least one first sub-area of ​​the plurality of first sub-areas is provided with at least one first light-emitting unit, and at least one second sub-area of ​​the plurality of second sub-areas is provided with at least one second light-emitting unit; The second conductive layer further includes: a first scan line, a light emitting control line, a first reset control line and a second reset control line electrically connected to the first pixel circuit; the first scan line, the light emitting control line, the first reset control line and the second reset control line extend along a first direction; In the second direction, the first scan line and the first reset control line bypass one side of the second sub-region, and the light emitting control line and the second reset control line bypass the other side of the second sub-region; the second direction intersects the first direction.

17. The display substrate according to claim 15 or 16, in, The first display area includes: a plurality of first sub-areas and a plurality of second sub-areas; at least one first sub-area of ​​the plurality of first sub-areas is provided with at least one first light-emitting unit, and at least one second sub-area of ​​the plurality of second sub-areas is provided with at least one second light-emitting unit; The third conductive layer further includes: a first initial signal line, a second initial signal line, a third initial signal line and a second scan line electrically connected to the first pixel circuit; the first initial signal line, the second initial signal line, the third initial signal line and the second scan line extend along a first direction; In the second direction, the first initial signal line and the second scan line bypass one side of the second sub-region, and the second initial signal line and the third initial signal line bypass the other side of the second sub-region; the second direction intersects the first direction.

18. The display substrate according to any one of claims 1 to 17, in, The ratio of the number of the first light emitting units to the number of the second light emitting units in the first display area is 0.8 to 1.

2.

19. The display substrate according to any one of claims 1 to 18, in, The light transmittance of the first display area is greater than the light transmittance of the second display area; The display substrate further comprises: a plurality of third light emitting elements and a plurality of third pixel circuits located in the second display area, at least one third pixel circuit of the plurality of third pixel circuits being electrically connected to at least one third light emitting element of the plurality of third light emitting elements and configured to drive the at least one third light emitting element to emit light; The plurality of second pixel circuits are arranged at intervals between the plurality of third pixel circuits.

20. The display substrate according to any one of claims 1 to 19, in, The orthographic projection of the at least one first pixel circuit on the substrate overlaps with the orthographic projection of the at least one first light-emitting element on the substrate; The at least one second pixel circuit is electrically connected to the at least one second light emitting element via at least one conductive connecting line; The orthographic projection of the at least one second pixel circuit on the substrate has no overlap with the orthographic projection of the at least one second light-emitting element on the substrate.

21. The display substrate according to claim 20, in, An orthographic projection of the at least one conductive connection line on the substrate overlaps with an orthographic projection of the at least one first pixel circuit on the substrate.

22. A display device, comprising a display substrate as claimed in any one of claims 1 to 21, and a sensor located on a non-display surface side of the display substrate, wherein an orthographic projection of the sensor on the display substrate at least partially overlaps with a first display area of ​​the display substrate.

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