Chip select signal control circuit, processing circuit, and memory

Abstract

Disclosed is a chip select signal control circuit (80), comprising: a first control signal generation circuit (10), a second control signal generation circuit (20), a chip select signal sampling circuit (30) and a logic control circuit (40), wherein the first control signal generation circuit (10) outputs a first control signal (CS_EVEN_PP_T) according to a first chip select sampling signal (EVEN_CS_OT) and a first command address sampling signal (EVEN_CA1_OB), which are obtained by means of performing sampling in the previous two system sampling periods; the second control signal generation circuit (20) outputs a second control signal (CS_EVEN_P_T) according to a second chip select sampling signal (ODD_CS_OT) and a second command address sampling signal (ODD_CA1_OB), which are obtained by means of performing sampling in the previous system sampling period; and the logic control circuit (30) controls the output of the current chip select sampling signal (CS) according to the first control signal (CS_EVEN_PP_T) and the second control signal (CS_EVEN_P_T).

Description

Chip select signal control circuit, processing circuit and memory

[0001] This application claims priority to the Chinese patent application filed with the China Patent Office on June 16, 2023, with application number 202310725638.0 and application name “A chip select signal control circuit, processing circuit and memory”, the entire contents of which are incorporated by reference into this application. Technical Field

[0002] The present disclosure relates to, but is not limited to, a chip select signal control circuit, a processing circuit, and a memory. Background Art

[0003] In memory, command address signals are transmitted via the command address bus, and the chip select signal indicates whether the command address signal is valid. Because the command address bus aggregates various command address signals, various decoding errors may occur in some special cases.

[0004] Summary of the Invention

[0005] In view of this, embodiments of the present disclosure provide a chip select signal control circuit, a processing circuit, and a memory, which can avoid decoding errors of command address signals.

[0006] The technical solution of the embodiment of the present disclosure is implemented as follows:

[0007] An embodiment of the present disclosure provides a chip select signal control circuit, the chip select signal control circuit comprising:

[0008] a first control signal generating circuit configured to receive a first chip select sampling signal and a first command address sampling signal, and output a first control signal at a first level when the levels of the first chip select sampling signal and the first command address sampling signal meet a first preset rule; otherwise, output a first control signal at a second level; wherein the first chip select sampling signal is obtained by sampling the initial chip select signal during the first two system sampling cycles, and the first command address sampling signal is obtained by sampling the initial command address signal during the first two system sampling cycles;

[0009] a second control signal generating circuit configured to receive a second chip select sampling signal and a second command address sampling signal, and output a second control signal of a first level when the levels of the second chip select sampling signal and the second command address sampling signal meet a second preset rule; otherwise, output a second control signal of a second level; wherein the second chip select sampling signal is obtained by sampling the initial chip select signal during a previous system sampling cycle, and the second command address sampling signal is obtained by sampling the initial command address signal during the previous system sampling cycle;

[0010] a chip select signal sampling circuit, configured to receive the initial chip select signal and a first frequency-divided clock signal, sample the initial chip select signal according to the first frequency-divided clock signal, and output a current chip select sampling signal;

[0011] A logic control circuit is connected to the first control signal generating circuit, the second control signal generating circuit and the chip select signal sampling circuit, and is configured to receive the first control signal, the second control signal and the current chip select sampling signal, and output the current chip select sampling signal when the first control signal and the second control signal meet a third preset rule.

[0012] In some embodiments, the second control signal generating circuit is further configured to receive the first control signal after the first delay and a second divided clock signal, sample the first control signal after the first delay according to the second divided clock signal, and output it as the second control signal.

[0013] In some embodiments, the first control signal generating circuit is further configured to, in the first operating mode, apply a second delay to the first control signal and then output it; or, in the second operating mode, output the first control signal.

[0014] In some embodiments, the chip select signal control circuit also includes: a command address signal sampling circuit, configured to receive an initial command address signal, the first frequency-divided clock signal and the second frequency-divided clock signal, and sample the initial command address signal into the first command address sampling signal according to the first frequency-divided clock signal; and sample the initial command address signal into the second command address sampling signal according to the second frequency-divided clock signal.

[0015] In some embodiments, the first control signal generating circuit includes: a first NAND gate, a first inverter, and a second inverter; the input ends of the first NAND gate receive the first chip select sampling signal and the first command address sampling signal respectively; the output end of the first NAND gate is connected to the input end of the first inverter; the output end of the first inverter is connected to the input end of the second inverter; the first NAND gate outputs the first control signal; the first inverter outputs the first control signal after the first delay; and the second inverter outputs the first control signal after the second delay.

[0016] In some embodiments, the first control signal generating circuit further includes: a first data selector; a first input end of the first data selector receives the first control signal after the second delay; a second input end of the first data selector receives the first control signal; and a control end of the first data selector receives an operating mode enable signal.

[0017] In some embodiments, the first control signal generating circuit also includes: a first level trigger; the data input end of the first level trigger is connected to the output end of the first data selector; the clock input end of the first level trigger receives the first divided clock signal; the output end of the first level trigger serves as the output end of the first control signal generating circuit.

[0018] In some embodiments, the second control signal generating circuit includes: a second NAND gate, a first D flip-flop and a second data selector; the input ends of the second NAND gate receive the second chip select sampling signal and the second command address sampling signal respectively; the output end of the second NAND gate is connected to the first input end of the second data selector; the data input end of the first D flip-flop receives the first control signal after the first delay, and the clock input end of the first D flip-flop receives the second divided clock signal; the in-phase output end of the first D flip-flop is connected to the second input end of the second data selector; and the control end of the second data selector receives the working mode enable signal.

[0019] In some embodiments, the second control signal generating circuit further includes: a second level trigger; the data input end of the second level trigger is connected to the output end of the second data selector; the clock input end of the second level trigger receives the first divided clock signal; the output end of the second level trigger serves as the output end of the second control signal generating circuit.

[0020] In some embodiments, the chip select signal sampling circuit includes: a second D flip-flop, a third inverter and a fourth inverter; the data input end of the second D flip-flop receives the initial chip select signal, and the clock input end of the second D flip-flop receives the first divided clock signal; the in-phase output end of the second D flip-flop is connected to the input end of the third inverter; the output end of the third inverter is connected to the input end of the fourth inverter; and the fourth inverter outputs the current chip select sampling signal.

[0021] In some embodiments, the logic control circuit includes: an OR gate and a third NAND gate; the first input end of the OR gate is connected to the output end of the first control signal generating circuit; the second input end of the OR gate is connected to the output end of the second control signal generating circuit; the output end of the OR gate is connected to the first input end of the third NAND gate; the second input end of the third NAND gate receives the current chip select sampling signal; the output end of the third NAND gate serves as the output end of the logic control circuit.

[0022] In some embodiments, the command address signal sampling circuit includes: a third D flip-flop and a fourth D flip-flop; the data input terminal of the third D flip-flop receives the initial command address signal, the clock input terminal of the third D flip-flop receives the first divided clock signal, and the third D flip-flop outputs the first command address sampling signal; the data input terminal of the fourth D flip-flop receives the initial command address signal, the clock input terminal of the fourth D flip-flop receives the second divided clock signal, and the fourth D flip-flop outputs the second command address sampling signal.

[0023] An embodiment of the present disclosure also provides a chip select signal processing circuit, characterized in that it includes: a chip select signal control circuit as described in the above scheme, and a decoding circuit; the decoding circuit is connected to the chip select signal control circuit, and is configured to receive a current chip select sampling signal, decode the current chip select sampling signal and output it.

[0024] An embodiment of the present disclosure further provides a memory, which includes the chip select signal processing circuit as described in the above solution.

[0025] In some embodiments, the memory is DDR5 DRAM.

[0026] It can be seen that the embodiment of the present disclosure provides a chip select signal control circuit, including: a first control signal generating circuit, a second control signal generating circuit, a chip select signal sampling circuit and a logic control circuit. Among them, the first control signal generating circuit outputs a first control signal based on the first chip select sampling signal and the first command address sampling signal obtained by sampling in the previous two system sampling cycles; the second control signal generating circuit outputs a second control signal based on the second chip select sampling signal and the second command address sampling signal obtained by sampling in the previous system sampling cycle; and the logic control circuit controls the output of the current chip select sampling signal based on the first control signal and the second control signal. In this way, by using the signals in the previous and previous two system sampling cycles to perform logic checks, it is possible to ensure that the command address signal in the current system sampling cycle is decoded normally, thereby avoiding decoding errors. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] FIG1 is a signal schematic diagram 1 provided by an embodiment of the present disclosure;

[0028] FIG2 is a second signal diagram provided by an embodiment of the present disclosure;

[0029] FIG3 is a first structural diagram of a chip select signal control circuit provided by an embodiment of the present disclosure;

[0030] FIG4 is a third signal diagram provided by an embodiment of the present disclosure;

[0031] FIG5 is a fourth signal diagram provided by an embodiment of the present disclosure;

[0032] FIG6 is a second structural diagram of a chip select signal control circuit provided in an embodiment of the present disclosure;

[0033] FIG7 is a third structural diagram of a chip select signal control circuit provided in an embodiment of the present disclosure;

[0034] FIG8 is a fourth structural diagram of a chip select signal control circuit provided in an embodiment of the present disclosure;

[0035] FIG9 is a first structural diagram of a command address sampling circuit provided by an embodiment of the present disclosure;

[0036] FIG10 is a fifth structural diagram of a chip select signal control circuit provided in an embodiment of the present disclosure;

[0037] FIG11 is a fifth signal diagram provided by an embodiment of the present disclosure;

[0038] FIG12 is a sixth signal diagram provided by an embodiment of the present disclosure;

[0039] FIG13 is a second structural diagram of a command address sampling circuit provided in an embodiment of the present disclosure;

[0040] FIG14 is a schematic structural diagram of a chip select signal processing circuit provided in an embodiment of the present disclosure;

[0041] FIG15 is a schematic diagram of the structure of the memory provided in an embodiment of the present disclosure. DETAILED DESCRIPTION

[0042] In order to make the purpose, technical solutions and advantages of the present disclosure clearer, the technical solutions of the present disclosure are further elaborated in detail below with reference to the accompanying drawings and embodiments. The described embodiments should not be regarded as limiting the present disclosure. All other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of the present disclosure.

[0043] In the following description, reference is made to “some embodiments”, which describes a subset of all possible embodiments, but it will be understood that “some embodiments” may be the same subset or different subsets of all possible embodiments and may be combined with each other without conflict.

[0044] If similar descriptions of "first / second" appear in the invention document, the following explanation is added. In the following description, the terms "first\second\third" involved are only used to distinguish similar objects and do not represent a specific order for the objects. It can be understood that "first\second\third" can be interchanged with a specific order or sequence where permitted, so that the embodiments of the present disclosure described herein can be implemented in an order other than that illustrated or described herein.

[0045] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by those skilled in the art in the art of the present disclosure. The terms used herein are only for the purpose of describing the embodiments of the present disclosure and are not intended to limit the present disclosure.

[0046] It should be noted that the chip select signal is used to select the corresponding chip. When multiple chips are connected to the same bus, the chip select signal is used to distinguish which chip processes the data and address on the bus. In other words, the chip select signal triggers the corresponding chip to enter the working state. For example, in a memory, multiple memory chips are included; if the CPU (processor) wants to access a memory unit, it must first select the memory chip through the chip select signal, that is, perform chip selection; then, it can select the corresponding memory unit from the selected memory chip according to the address code, that is, perform word selection, to read / write data. The chip select signal is usually valid at a low level; in the embodiment of the present disclosure, the chip select signal is described as valid at a low level.

[0047] On the other hand, the command address signal includes the command signal and the address signal, which are transmitted through the bus. For example, in DRAM (dynamic random access memory), the command address signal may include: row address strobe (RAS), column address strobe (CAS), write command (WE), activate command (ACT), and other command signals, as well as address signals (such as A13 to A0).

[0048] Furthermore, the command address signal needs to be indicated as valid by the chip select signal. Referring to Figure 1, taking the design of DDR5 DRAM (fifth-generation double-bit rate synchronous dynamic random access memory) as an example, the command address signal CA<12:0> input can be sampled as an address and can be sampled and decoded as an instruction. That is, the command address signal CA<12:0> includes the command signal CMD and the address signal ADD. After the chip select signal CS_n indicates valid (that is, the chip select signal CS_n is low), the command address signal CA<12:0> is sampled by the even clock signal CLK_ET for decoding. Among them, the odd clock signal CLK_OT and the even clock signal CLK_ET are obtained by dividing the clock signal CK_t and are used to sample the command address signal CA<12:0>.

[0049] It should be noted that DDR5 DRAM has two command modes: 1T CMD and 2T CMD. 1T CMD requires only one system sampling cycle to output the command and address signals as instructions and addresses; 2T CMD, on the other hand, requires two system sampling cycles to transmit the command and address signals.

[0050] It should also be noted that the clock signal CK_t is the basic reference clock in the chip system; the system sampling period described in the embodiments of the present disclosure refers to the period of the clock signal CK_t, which will not be repeated below.

[0051] Figure 1 shows the signal waveform diagram of the command address signal CA<12:0> in 2T CMD mode. Referring to Figure 1, the command address signal CA<12:0> requires two system sampling cycles to transmit the instruction and address. Specifically, the command address signal CA<12:0> transmits the instruction and a portion of the address (i.e., CMD+ADD) during the 0th cycle of the clock signal CK_t; the command address signal CA<12:0> transmits the remaining portion of the address (i.e., ADD) during the 2nd cycle of the clock signal CK_t.

[0052] The chip select signal CS_n shown in Figure 1 is active (i.e., low) for only one system sampling cycle. However, there are cases where the chip select signal CS_n remains active for multiple system sampling cycles. For example, in a two-rank chip structure, the chip select signal corresponding to the on-chip termination command NT_ODT_CMD of a non-target chip remains active for two system sampling cycles.

[0053] Figure 2 illustrates a portion of the waveforms of the command address signal and chip select signal for a non-target chip. As shown in Figure 2, the command address signal CA includes the non-target chip's read command NT_RD (a type of on-chip termination command). Accordingly, the chip select signal CS_n remains active for two cycles of the clock signal CK_t. Therefore, during the second system sampling cycle in which the chip select signal CS_n remains active, the address signal CA (marked by the dashed line) may be mistaken for a command, potentially leading to incorrect sampling and decoding.

[0054] FIG3 is a schematic diagram of an optional structure of a chip select signal control circuit provided in an embodiment of the present disclosure. As shown in FIG3 , the chip select signal control circuit 80 includes: a first control signal generating circuit 10 , a second control signal generating circuit 20 , a chip select signal sampling circuit 30 , and a logic control circuit 40 .

[0055] The first control signal generating circuit 10 is configured to receive a first chip select sampling signal EVEN_CS_OT and a first command address sampling signal EVEN_CA1_OB, and output a first control signal CS_EVEN_PP_T of a first level when the levels of the first chip select sampling signal EVEN_CS_OT and the first command address sampling signal EVEN_CA1_OB meet a first preset rule; otherwise, output the first control signal CS_EVEN_PP_T of a second level; wherein the first chip select sampling signal EVEN_CS_OT is obtained by sampling the initial chip select signal CS_n during the first two system sampling cycles, and the first command address sampling signal EVEN_CA1_OB is obtained by sampling the initial command address signal during the first two system sampling cycles.

[0056] The second control signal generating circuit 20 is configured to receive the second chip select sampling signal ODD_CS_OT and the second command address sampling signal ODD_CA1_OB, and output the second control signal CS_EVEN_P_T of the first level when the levels of the second chip select sampling signal ODD_CS_OT and the second command address sampling signal ODD_CA1_OB meet a second preset rule; otherwise, output the second control signal CS_EVEN_P_T of the second level; wherein the second chip select sampling signal ODD_CS_OT is obtained by sampling the initial chip select signal CS_n in the previous system sampling cycle, and the second command address sampling signal ODD_CA1_OB is obtained by sampling the initial command address signal in the previous system sampling cycle.

[0057] The chip select signal sampling circuit 30 is configured to receive the initial chip select signal CS_n and the first frequency-divided clock signal CLK_ET (ie, an even clock signal), sample the initial chip select signal CS_n according to the first frequency-divided clock signal CLK_ET, and output a current chip select sampling signal CS.

[0058] The logic control circuit 40 is connected to the first control signal generation circuit 10, the second control signal generation circuit 20 and the chip select signal sampling circuit 30, and is configured to receive the first control signal CS_EVEN_PP_T, the second control signal CS_EVEN_P_T and the current chip select sampling signal CS, and output the current chip select sampling signal CS when the first control signal CS_EVEN_PP_T and the second control signal CS_EVEN_P_T meet the third preset rule.

[0059] It should be noted that in Figure 3, the first chip select sampling signal EVEN_CS_OT and the first command address sampling signal EVEN_CA1_OB are obtained by sampling the even clock signal CLK_ET; the second chip select sampling signal ODD_CS_OT and the second command address sampling signal ODD_CA1_OB are obtained by sampling the odd clock signal CLK_OT (not shown in Figure 3).

[0060] As can be seen from Figure 1, the odd clock signal CLK_OT and the even clock signal CLK_ET are obtained by dividing the clock signal CK_t; that is, the frequency of the odd clock signal CLK_OT and the even clock signal CLK_ET is half the frequency of the clock signal CK_t; the period of the odd clock signal CLK_OT and the even clock signal CLK_ET is twice the period of the clock signal CK_t.

[0061] Continuing with Figure 1, since the odd clock signal CLK_OT and the even clock signal CLK_ET are in antiphase, if any sampling edge (rising edge) of the even clock signal CLK_ET is used as the current sampling edge, then the sampling edge (rising edge) of the odd clock signal CLK_OT is preceded by one system sampling cycle (i.e., half the cycle of the even clock signal CLK_ET); further, the previous sampling edge (rising edge) of the even clock signal CLK_ET is preceded by two system sampling cycles (i.e., one cycle of the even clock signal CLK_ET).

[0062] 1 and 3 , because the chip select signal sampling circuit 30 receives and samples the initial chip select signal CS_n based on the even clock signal CLK_ET to obtain the current chip select sampling signal CS, the current chip select sampling signal CS is sampled two system sampling cycles in advance, on the sampling edge of the even clock signal CLK_ET. In other words, the first chip select sampling signal EVEN_CS_OT is obtained by sampling the initial chip select signal CS_n using the even clock signal CLK_ET during the first two system sampling cycles. Correspondingly, the first command address sampling signal EVEN_CA1_OB is obtained by sampling the initial command address signal using the even clock signal CLK_ET during the first two system sampling cycles. Similarly, the moment when the current chip select sampling signal CS is sampled is one system sampling cycle in advance, which is the sampling edge of the odd clock signal CLK_OT; that is, the second chip select sampling signal ODD_CS_OT is obtained by sampling the initial chip select signal CS_n by the odd clock signal CLK_OT during the previous system sampling cycle; correspondingly, the second command address sampling signal ODD_CA1_OB is obtained by sampling the initial command address signal by the odd clock signal CLK_OT during the previous system sampling cycle.

[0063] FIG4 and FIG5 respectively show waveforms of different command address signals CA when the active level of the chip select signal CS_n lasts for multiple system sampling cycles.

[0064] Referring to Figure 4, the command address signal CA includes two consecutive 1T CMD mode commands (i.e., PRE and PDE), and the chip select signal CS_n remains active for two system sampling cycles. Therefore, sampling based on the chip select signal CS_n may cause the second command PDE to be canceled.

[0065] Referring to FIG3 , the second control signal generation circuit 20 in the disclosed embodiment outputs the second control signal CS_EVEN_P_T based on the second chip select sampling signal ODD_CS_OT and the second command address sampling signal ODD_CA1_OB obtained during the previous system sampling cycle. In other words, in conjunction with FIG4 , the second control signal generation circuit 20 can make a comprehensive determination based on the levels of the chip select signal CS_n and the command address signal CA during the previous system sampling cycle. For example, if the chip select signal CS_n is low and the identification signal in the command address signal CA is high during the previous system sampling cycle, the current command PDE can be determined to be a complete command, and the current command PDE can be sampled and decoded normally when the chip select signal CS_n is low.

[0066] Referring to Figure 5, the read command NT_RD (a type of on-chip termination command) of the non-target chip lasts for two system sampling cycles and is immediately followed by a command PRE. Therefore, when sampling based on the chip select signal CS_n, the PRE command may be mistakenly interpreted as the second system sampling cycle of the 2T CMD mode.

[0067] Referring to FIG3 , the first control signal generation circuit 10 in the disclosed embodiment outputs the first control signal CS_EVEN_PP_T based on the first chip select sampling signal EVEN_CS_OT and the first command address sampling signal EVEN_CA1_OB obtained during the first two system sampling cycles. That is, in conjunction with FIG5 , the first control signal generation circuit 10 can make a comprehensive determination based on the levels of the chip select signal CS_n and the command address signal CA during the first two system sampling cycles. For example, if the chip select signal CS_n is low during the first two system sampling cycles, and the command address signal CA indicates a read command NT_RD for a non-target chip, then the current command PDE can be determined to be a complete command. The current command PDE can then be sampled and decoded normally when the chip select signal CS_n is low, thus preventing the read command NT_RD from being incorrectly decoded during the second system sampling cycle.

[0068] It is understandable that the aggregation of various command address signals on the command address bus may result in various decoding errors. In the disclosed embodiment, the first control signal generation circuit generates a first control signal based on the levels of the chip select signal and the command address signal in the first two system sampling cycles; the second control signal generation circuit generates a second control signal based on the levels of the chip select signal and the command address signal in the previous system sampling cycle; and the logic control circuit controls the output of the current chip select sampling signal based on the first control signal and the second control signal, that is, controls whether the chip select signal has an effect on the current command address signal. In this way, using the signals in the previous and first two system sampling cycles to perform logic checks can ensure that the command address signal in the current system sampling cycle is decoded normally, avoiding decoding errors.

[0069] FIG6 is a schematic diagram of another optional structure of a chip select signal control circuit provided in an embodiment of the present disclosure. FIG6 illustrates how the chip select signal sampling circuit 30 receives and samples the initial chip select signal CS_n based on the odd clock signal CLK_OT to obtain the current chip select sampling signal CS. In other words, FIG6 illustrates a circuit structure corresponding to FIG3 , and the various signals illustrated in FIG6 can be deduced with reference to FIG3 .

[0070] Specifically, referring to Figure 6, the first control signal generating circuit 10 is configured to receive the first chip select sampling signal ODD_CS_OT and the first command address sampling signal ODD_CA1_OB, and output the first control signal CS_ODD_PP_T of the first level when the levels of the first chip select sampling signal ODD_CS_OT and the first command address sampling signal ODD_CA1_OB meet the first preset rule; otherwise, it outputs the first control signal CS_ODD_PP_T of the second level; wherein, the first chip select sampling signal ODD_CS_OT is obtained by sampling the initial chip select signal CS_n during the first two system sampling cycles, and the first command address sampling signal ODD_CA1_OB is obtained by sampling the initial command address signal during the first two system sampling cycles.

[0071] The second control signal generating circuit 20 is configured to receive the second chip select sampling signal EVEN_CS_OT and the second command address sampling signal EVEN_CA1_OB, and output the second control signal CS_ODD_P_T of the first level when the levels of the second chip select sampling signal EVEN_CS_OT and the second command address sampling signal EVEN_CA1_OB meet a second preset rule; otherwise, output the second control signal CS_ODD_P_T of the second level; wherein the second chip select sampling signal EVEN_CS_OT is obtained by sampling the initial chip select signal CS_n in the previous system sampling cycle, and the second command address sampling signal EVEN_CA1_OB is obtained by sampling the initial command address signal in the previous system sampling cycle.

[0072] The chip select signal sampling circuit 30 is configured to receive an initial chip select signal CS_n and an odd clock signal CLK_OT, sample the initial chip select signal CS_n according to the odd clock signal CLK_OT, and output a current chip select sampling signal CS.

[0073] The logic control circuit 40 is connected to the first control signal generation circuit 10, the second control signal generation circuit 20 and the chip select signal sampling circuit 30, and is configured to receive the first control signal CS_ODD_PP_T, the second control signal CS_ODD_P_T and the current chip select sampling signal CS, and output the current chip select sampling signal CS when the first control signal CS_ODD_PP_T and the second control signal CS_ODD_P_T meet the third preset rule.

[0074] It will be appreciated that Figures 3 and 6 illustrate circuit structures corresponding to different sampling clocks. If the initial chip select signal CS_n is sampled using the even clock signal CLK_ET, the circuit shown in Figure 3 operates; if the initial chip select signal CS_n is sampled using the odd clock signal CLK_OT, the circuit shown in Figure 6 operates. Specific configurations can be made based on the actual situation in the chip system.

[0075] Correspondingly, in the circuit shown in Figure 6, the first chip select sampling signal ODD_CS_OT is obtained by sampling the initial chip select signal CS_n by the odd clock signal CLK_OT during the first two system sampling cycles; the first command address sampling signal ODD_CA1_OB is obtained by sampling the initial command address signal by the odd clock signal CLK_OT during the first two system sampling cycles; the second chip select sampling signal EVEN_CS_OT is obtained by sampling the initial chip select signal CS_n by the even clock signal CLK_ET during the previous system sampling cycle; the second command address sampling signal EVEN_CA1_OB is obtained by sampling the initial command address signal by the even clock signal CLK_ET during the previous system sampling cycle.

[0076] In some embodiments of the present disclosure, referring to FIG7 , the second control signal generating circuit 20 is further configured to receive the first control signal EVEN_CHK1 after the first delay and the second divided clock signal CLK_OT (i.e., the odd clock signal), sample the first control signal EVEN_CHK1 after the first delay according to the second divided clock signal CLK_OT, and output the sample as the second control signal CS_EVEN_P_T.

[0077] 7 , the first control signal generating circuit 10 is further configured to, in the first operating mode, add a second delay to the first control signal and then output it; or, in the second operating mode, output the first control signal.

[0078] It should be noted that in memory (such as DRAM), there are two operating modes, namely 1N mode and 2N mode. In 1N mode, both the odd clock signal CLK_OT and the even clock signal CLK_ET are sampled; while in 2N mode, only one of the odd clock signal CLK_OT and the even clock signal CLK_ET is sampled.

[0079] In Figure 7 , the level of the operating mode enable signal EN indicates the operating mode of the memory. For example, when the operating mode enable signal EN is high, the memory is in 1N mode (i.e., the first operating mode); when the operating mode enable signal EN is low, the memory is in 2N mode (i.e., the second operating mode). In other words, the chip select signal control circuit 80 provided in the embodiments of the present disclosure will also make corresponding adjustments based on the different operating modes of the memory.

[0080] Referring to Figure 7 , for the first control signal generating circuit 10, in 1N mode, a second delay is applied to the first control signal CS_EVEN_PP_T output by the first control signal generating circuit 10. In 2N mode, the second delay is not applied to the first control signal CS_EVEN_PP_T output by the first control signal generating circuit 10. Applying the second delay allows the output first control signal CS_EVEN_PP_T to match the timing of other signals in the 1N mode.

[0081] Continuing to refer to Figure 7, for the second control signal generating circuit 20, in the 1N mode, the second control signal generating circuit 20 outputs the second control signal CS_EVEN_P_T according to the second chip select sampling signal ODD_CS_OT and the second command address sampling signal ODD_CA1_OB; in the 2N mode, the second control signal generating circuit 20 samples the first control signal EVEN_CHK1 after the first delay and outputs it.

[0082] It should be noted that in the circuit illustrated in FIG7 , in 2N mode, the even clock signal CLK_ET samples the initial chip select signal CS_n. That is, the odd clock signal CLK_OT is not sampled at this time. Thus, the second chip select sampling signal ODD_CS_OT and the second command address sampling signal ODD_CA1_OB, obtained by sampling the odd clock signal CLK_OT, cannot be used in 2N mode. Consequently, in 2N mode, the second control signal generation circuit 20 can sample the first control signal EVEN_CHK1, which has undergone the first delay, based on the odd clock signal CLK_OT. This replaces the logic check of the signal in the previous system sampling cycle and outputs the second control signal CS_EVEN_P_T.

[0083] Accordingly, in the circuit shown in FIG8 , in 2N mode, the initial chip select signal CS_n is sampled by the odd clock signal CLK_OT. Referring to FIG8 , the second control signal generating circuit 20 is further configured to receive the first control signal ODD_CHK1 after the first delay and the second frequency-divided clock signal CLK_ET (i.e., the even clock signal), sample the first control signal ODD_CHK1 after the first delay according to the second frequency-divided clock signal CLK_ET, and output the sample as the second control signal CS_EVEN_P_T.

[0084] It is understandable that the chip select signal control circuit provided by the embodiment of the present disclosure can make corresponding adjustments according to different operating modes of the memory, thereby better adapting to different operating modes of the memory and expanding the application range of the circuit.

[0085] In some embodiments of the present disclosure, the chip select signal control circuit further includes a command address signal sampling circuit. The command address signal sampling circuit is configured to receive an initial command address signal, a first frequency-divided clock signal, and a second frequency-divided clock signal, sample the initial command address signal into a first command address sampling signal according to the first frequency-divided clock signal, and sample the initial command address signal into a second command address sampling signal according to the second frequency-divided clock signal.

[0086] That is, referring to FIG9 , the command address signal sampling circuit 50 can sample the initial command address signal CA based on the odd clock signal CLK_OT and output the command address sampling signal ODD_CA1_OB. The command address signal sampling circuit 50 can also sample the initial command address signal CA based on the even clock signal CLK_ET and output the command address sampling signal EVEN_CA1_OB. The command address sampling signals ODD_CA1_OB and EVEN_CA1_OB serve as input signals in FIG3 , FIG6 , FIG7 , and FIG8 .

[0087] FIG10 is a schematic diagram of an optional structure of a chip select signal control circuit provided in an embodiment of the present disclosure. FIG11 and FIG12 are schematic diagrams of waveforms of some of the signals in FIG10 . FIG11 illustrates the waveforms of some of the signals in the memory in 1N mode; that is, both the odd clock signal CLK_OT and the even clock signal CLK_ET in FIG11 are sampled. FIG12 illustrates the waveforms of some of the signals in the memory in 2N mode; in FIG12 , only the even clock signal CLK_ET is sampled.

[0088] In some embodiments of the present disclosure, referring to FIG10 , a first control signal generating circuit 10 includes: a first NAND gate Nand1, a first inverter Inv1, and a second inverter Inv2. The inputs of the first NAND gate Nand1 receive the first chip select sampling signal EVEN_CS_OT and the first command address sampling signal EVEN_CA1_OB, respectively. The output of the first NAND gate Nand1 is connected to the input of the first inverter Inv1. The output of the first inverter Inv1 is connected to the input of the second inverter Inv2. The first NAND gate Nand1 outputs the first control signal EVEN_CHK, the first inverter Inv1 outputs the first control signal EVEN_CHK1 after a first delay, and the second inverter Inv2 outputs the first control signal EVEN_CHK2 after a second delay.

[0089] Continuing with FIG10 , the first control signal generating circuit 10 further includes a first data selector Mux1. A first input terminal (i.e., a "1" input terminal) of the first data selector Mux1 receives the first control signal EVEN_CHK2 after the second delay, a second input terminal (i.e., a "0" input terminal) of the first data selector Mux1 receives the first control signal EVEN_CHK, and a control terminal of the first data selector Mux1 receives the operating mode enable signal EN.

[0090] In the disclosed embodiment, the level of the operating mode enable signal EN represents the operating mode of the memory. When the memory is in 1N mode (i.e., the first operating mode), the operating mode enable signal EN is at a high level; thus, the first data selector Mux1 selects to output the first control signal EVEN_CHK2 (i.e., the signal received at the "1" input terminal) after the second delay. When the memory is in 2N mode (i.e., the second operating mode), the operating mode enable signal EN is at a low level; thus, the first data selector Mux1 selects to output the first control signal EVEN_CHK (i.e., the signal received at the "0" input terminal).

[0091] In some embodiments of the present disclosure, referring to FIG10 , the first control signal generating circuit 10 further includes a first level flip-flop T1. A data input terminal D of the first level flip-flop T1 is connected to an output terminal of the first data selector Mux1, a clock input terminal of the first level flip-flop T1 receives a first frequency-divided clock signal CLK_ET, and an output terminal of the first level flip-flop T1 serves as an output terminal of the first control signal generating circuit 10.

[0092] In the disclosed embodiment, referring to Figures 10 and 12 , the initial command address signal CA includes a PRE signal and a PDE signal. The PDE signal is the signal currently being sampled and decoded, while the PRE signal precedes the PDE signal by two system sampling cycles. The PRE signal is initially sampled by the even clock signal CLK_ET as a high-level pre-sampled command address CA1 (PRE), and is further sampled as a low-level first command address sampling signal EVEN_CA1_OB.

[0093] In addition, the initial chip select signal CS_n is at an active level (low level) two system sampling cycles prior to the initial chip select signal CS_n. That is, the initial chip select signal CS_n corresponds to the low level of the PRE signal. Thus, two system sampling cycles prior to the initial chip select signal CS_n, the initial chip select signal CS_n is sampled by the even clock signal CLK_ET as the first chip select sampling signal EVEN_CS_OT at a high level.

[0094] Furthermore, the first command address sampling signal EVEN_CA1_OB is low, and the first chip select sampling signal EVEN_CS_OT is high. After a NAND operation through the first NAND gate Nand1, a high-level first control signal EVEN_CHK is generated. Thus, the PRE signals of the first two system sampling cycles represent commands in 1T CMD mode. Therefore, the PDE signal of the current system sampling cycle represents a new command and can be decoded normally.

[0095] In the disclosed embodiment, referring to FIG10 and FIG12 , if the initial chip select signal CS_n and the pre-sampling command address CA1 (PRE) are both low in the first two system sampling cycles, then it is recognized that the first two system sampling cycles are in 2T CMD mode. In this case, if the on-chip termination command NT_ODT_CMD (not shown) is included, the current system sampling cycle can be decoded normally, thereby eliminating the situation where the command after the on-chip termination command NT_ODT_CMD is canceled.

[0096] In some embodiments of the present disclosure, referring to FIG10 , the second control signal generating circuit 20 includes: a second NAND gate Nand2, a first D flip-flop DFF1, and a second data selector Mux2. The input terminals of the second NAND gate Nand2 receive the second chip select sampling signal ODD_CS_OT and the second command address sampling signal ODD_CA1_OB, respectively. The output terminal of the second NAND gate Nand2 is connected to the first input terminal (i.e., the "1" input terminal) of the second data selector Mux2. The data input terminal D of the first D flip-flop DFF1 receives the first control signal EVEN_CHK1 after the first delay, the clock input terminal of the first D flip-flop DFF1 receives the second divided clock signal CLK_OT, and the non-inverting output terminal Q of the first D flip-flop DFF1 is connected to the second input terminal (i.e., the "0" input terminal) of the second data selector Mux2. The control terminal of the second data selector Mux2 receives the operating mode enable signal EN.

[0097] In the disclosed embodiment, the level of the operating mode enable signal EN indicates the operating mode of the memory. When the memory is in 1N mode (i.e., the first operating mode), the operating mode enable signal EN is high; thus, the second data selector Mux2 selects to output the signal received at its "1" input. When the memory is in 2N mode (i.e., the second operating mode), the operating mode enable signal EN is low; thus, the first data selector Mux1 selects to output the signal received at its "0" input.

[0098] In some embodiments of the present disclosure, referring to FIG10 , the second control signal generating circuit 20 further includes a second level flip-flop T2. A data input terminal D of the second level flip-flop T2 is connected to the output terminal of the second data selector Mux2. A clock input terminal of the second level flip-flop T2 receives the first frequency-divided clock signal CLK_ET. An output terminal Q of the second level flip-flop T2 serves as an output terminal of the second control signal generating circuit 20.

[0099] In the disclosed embodiment, referring to Figures 10 and 11 , the initial command address signal CA includes a PRE signal and a PDE signal. The PDE signal is the signal currently being sampled and decoded, while the PRE signal precedes the PDE signal by one system sampling cycle. The PRE signal is initially sampled as a high-level pre-sampled command address CA1 (PRE), and is further sampled by the odd-clock signal CLK_OT as a low-level second command address sampling signal ODD_CA1_OB.

[0100] In addition, the initial chip select signal CS_n is at an active level (low level) before one system sampling cycle. That is, the initial chip select signal CS_n corresponds to the low level of the PRE signal. Thus, before one system sampling cycle, the initial chip select signal CS_n is sampled by the odd clock signal CLK_OT to become the second chip select sampling signal ODD_CS_OT at a high level.

[0101] Furthermore, the second command address sampling signal ODD_CA1_OB is low, and the second chip select sampling signal ODD_CS_OT is high. After a NAND operation by the second NAND gate Nand2, a high-level second control signal is obtained (i.e., point A is high). Thus, the PRE signal of the previous system sampling cycle indicates a command in 1T CMD mode. Therefore, the PDE signal of the current system sampling cycle is a new command and can be decoded normally.

[0102] In the disclosed embodiment, referring to FIG10 and FIG11 , if the initial chip select signal CS_n is high in the previous system sampling cycle, or if the initial chip select signal CS_n is low and the initial command address signal CA is high in the previous system sampling cycle, it will be recognized that no instruction operation was performed in the previous system sampling cycle, or that a 1T CMD mode command was being performed. In this way, the current system sampling cycle can be decoded normally, thereby preventing two consecutive 1T CMD mode commands from being mistakenly recognized as the second cycle of the on-chip termination command NT_ODT_CMD.

[0103] In some embodiments of the present disclosure, referring to FIG. 10 , the chip select signal sampling circuit 30 includes a second D-type flip-flop DFF2, a third inverter Inv3, and a fourth inverter Inv4. The data input D of the second D-type flip-flop DFF2 receives the initial chip select signal CS_n, and the clock input of the second D-type flip-flop DFF2 receives the first divided clock signal CLK_ET. The non-inverting output Q of the second D-type flip-flop DFF2 is connected to the input of the third inverter Inv3. The output of the third inverter Inv3 is connected to the input of the fourth inverter Inv4. The fourth inverter Inv4 outputs the current chip select sampling signal CS.

[0104] In the embodiment of the present disclosure, referring to Figure 10, the second D flip-flop DFF2 samples the initial chip select signal CS_n under the triggering of the first divided clock signal CLK_ET (i.e., an even clock signal), and obtains the current chip select sampling signal CS after passing through two stages of inverters Inv3 and Inv4.

[0105] In some embodiments of the present disclosure, referring to FIG. 10 , the logic control circuit 40 includes an OR gate Or1 and a third NAND gate Nand3. A first input of the OR gate Or1 is connected to the output of the first control signal generating circuit 10, and a second input of the OR gate Or1 is connected to the output of the second control signal generating circuit 20. The output of the OR gate Or1 is connected to a first input of a third NAND gate Nand3, a second input of which receives a current chip select sampling signal CS. The output of the third NAND gate Nand3 serves as the output of the logic control circuit 40.

[0106] In the disclosed embodiment, referring to FIG10 , the two input terminals of OR gate Or1 receive the first control signal CS_EVEN_PP_T and the second control signal CS_EVEN_P_T, respectively, and perform a comprehensive logical check. The result of this check is represented by the level at point B. Because the first control signal CS_EVEN_PP_T is obtained from the first two system sampling cycles, and the second control signal CS_EVEN_P_T is obtained from the previous system sampling cycle, the result output by OR gate Or1 is a logical check that combines the signals from the previous and two system sampling cycles.

[0107] Furthermore, the third NAND gate Nand3 outputs or blocks the current chip select sampling signal CS (i.e., the level at point C) based on the determination result output by the OR gate Or1 (i.e., the level at point B). Referring to Figures 11 and 12 , when the level at point B is high, the level at point C determines the output at point D. In other words, when the level at point B is high, the low level at point C (i.e., the current chip select sampling signal CS, which has been sampled as a valid level) is output as a high level at point D. This ensures that the current chip select sampling signal CS is at a valid level, allowing normal decoding of the current system sampling cycle.

[0108] It is understandable that the aggregation of various command address signals on the command address bus may result in various decoding errors. In the disclosed embodiment, the first control signal generation circuit generates a first control signal based on the levels of the chip select signal and the command address signal in the first two system sampling cycles; the second control signal generation circuit generates a second control signal based on the levels of the chip select signal and the command address signal in the previous system sampling cycle; and the logic control circuit controls the output of the current chip select sampling signal based on the first control signal and the second control signal, that is, controls whether the chip select signal has an effect on the current command address signal. In this way, using the signals in the previous and first two system sampling cycles to perform logic checks can ensure that the command address signal in the current system sampling cycle is decoded normally, avoiding decoding errors.

[0109] In some embodiments of the present disclosure, referring to FIG. 13 , the command address signal sampling circuit 50 includes a third D flip-flop DFF3 and a fourth D flip-flop DFF4. The data input terminal D of the third D flip-flop DFF3 receives the initial command address signal CA, the clock input terminal of the third D flip-flop DFF3 receives the first divided clock signal CLK_ET, and the third D flip-flop DFF3 outputs the first command address sampling signal EVEN_CA1_OB. The data input terminal D of the fourth D flip-flop DFF4 receives the initial command address signal CA, the clock input terminal of the fourth D flip-flop DFF4 receives the second divided clock signal CLK_OT, and the fourth D flip-flop DFF4 outputs the second command address sampling signal ODD_CA1_OB.

[0110] In the disclosed embodiment, referring to Figures 12 and 13 , the third D-type flip-flop DFF3, triggered by the first frequency-divided clock signal CLK_ET (i.e., an even clock signal), samples the PRE signal of the first two system sampling cycles of the initial command address signal CA and outputs a first command address sampling signal EVEN_CA1_OB. The first command address sampling signal EVEN_CA1_OB is output to the inverting output terminal (i.e., the non-Q terminal) of the third D-type flip-flop DFF3. Therefore, the first command address sampling signal EVEN_CA1_OB shown in Figure 12 is sampled as a low level.

[0111] Accordingly, referring to Figures 11 and 13 , the fourth D-type flip-flop DFF4, triggered by the second frequency-divided clock signal CLK_OT (i.e., the odd clock signal), samples the PRE signal of the previous system sampling cycle in the initial command address signal CA and outputs a second command address sampling signal ODD_CA1_OB. The second command address sampling signal ODD_CA1_OB is output to the inverting output terminal (i.e., the non-Q terminal) of the fourth D-type flip-flop DFF4. Therefore, the second command address sampling signal ODD_CA1_OB shown in Figure 11 is sampled as a low level.

[0112] The embodiment of the present disclosure also provides a chip select signal processing circuit. As shown in FIG14 , the chip select signal processing circuit 70 includes: a chip select signal control circuit 80 and a decoding circuit 60 , wherein the chip select signal control circuit 80 includes the technical features described in the aforementioned embodiment.

[0113] 14 , the decoding circuit 60 is connected to the chip select signal control circuit 80. The decoding circuit 60 is configured to receive the current chip select sampling signal CS, decode the current chip select sampling signal CS and output it, that is, output the decoded chip select sampling signal CS1.

[0114] The embodiment of the present disclosure further provides a memory, as shown in FIG15 , the memory 90 includes: a chip select signal processing circuit 70 , wherein the chip select signal processing circuit 70 includes the technical features described in the aforementioned embodiment.

[0115] In some embodiments of the present disclosure, referring to FIG. 15 , the memory 90 is a fifth-generation double data rate synchronous dynamic random access memory (DDR5 DRAM).

[0116] It should be noted that, in this document, the terms "comprises," "includes," or any other variations thereof are intended to encompass non-exclusive inclusion, such that a process, method, article, or apparatus comprising a series of elements includes not only those elements but also other elements not explicitly listed, or elements inherent to such process, method, article, or apparatus. In the absence of further limitations, an element defined by the phrase "comprising a ..." does not exclude the presence of other identical elements in the process, method, article, or apparatus comprising the element.

[0117] The serial numbers of the embodiments of the present disclosure are for descriptive purposes only and do not represent the merits of the embodiments. The methods disclosed in the several method embodiments provided in the present disclosure can be arbitrarily combined to obtain new method embodiments when there is no conflict. The features disclosed in the several product embodiments provided in the present disclosure can be arbitrarily combined to obtain new product embodiments when there is no conflict. The features disclosed in the several method or device embodiments provided in the present disclosure can be arbitrarily combined to obtain new method embodiments or device embodiments when there is no conflict.

[0118] The above description is only a specific embodiment of the present disclosure, but the protection scope of the present disclosure is not limited thereto. Any technician familiar with the technical field can easily think of changes or replacements within the technical scope disclosed in the present disclosure, and they should all be covered by the protection scope of the present disclosure.

Claims

1. A chip select signal control circuit (80), characterized in that: The chip select signal control circuit (80) comprises: The first control signal generating circuit (10) is configured to receive a first chip select sampling signal (EVEN_CS_OT) and a first command address sampling signal (EVEN_CA1_OB), and output a first control signal (CS_EVEN_PP_T) of a first level when the levels of the first chip select sampling signal (EVEN_CS_OT) and the first command address sampling signal (EVEN_CA1_OB) meet a first preset rule, and otherwise output a first control signal (CS_EVEN_PP_T) of a second level; wherein the first chip select sampling signal (EVEN_CS_OT) is obtained by sampling an initial chip select signal (CS_n) during the first two system sampling cycles, and the first command address sampling signal (EVEN_CA1_OB) is obtained by sampling an initial command address signal during the first two system sampling cycles; The second control signal generating circuit (20) is configured to receive a second chip select sampling signal (ODD_CS_OT) and a second command address sampling signal (ODD_CA1_OB), and output a second control signal (CS_EVEN_P_T) of a first level when the levels of the second chip select sampling signal (ODD_CS_OT) and the second command address sampling signal (ODD_CA1_OB) meet a second preset rule, and otherwise output a second control signal (CS_EVEN_P_T) of a second level; wherein the second chip select sampling signal (ODD_CS_OT) is obtained by sampling the initial chip select signal (CS_n) in a previous system sampling cycle, and the second command address sampling signal (ODD_CA1_OB) is obtained by sampling the initial command address signal in a previous system sampling cycle; A chip select signal sampling circuit (30) is configured to receive the initial chip select signal (CS_n) and a first frequency-divided clock signal (CLK_ET), sample the initial chip select signal (CS_n) according to the first frequency-divided clock signal (CLK_ET), and output a current chip select sampling signal (CS); A logic control circuit (40) is connected to the first control signal generating circuit (10), the second control signal generating circuit (20) and the chip select signal sampling circuit (30), and is configured to receive the first control signal (CS_EVEN_PP_T), the second control signal (CS_EVEN_P_T) and the current chip select sampling signal (CS), and output the current chip select sampling signal (CS) when the first control signal and the second control signal meet a third preset rule.

2. The chip select signal control circuit according to claim 1, characterized in that: The second control signal generating circuit (20) is further configured to receive the first control signal (EVEN_CHK1) after the first delay and a second frequency-divided clock signal (CLK_OT), sample the first control signal (EVEN_CHK1) after the first delay according to the second frequency-divided clock signal (CLK_OT), and output the sample as the second control signal (CS_EVEN_P_T).

3. The chip select signal control circuit according to claim 2, characterized in that: The first control signal generating circuit (10) is further configured to, in the first working mode, add a second delay to the first control signal and then output it; Alternatively, in the second working mode, the first control signal is output.

4. The chip select signal control circuit according to claim 3, characterized in that: The first control signal generating circuit (10) comprises: a first NAND gate (Nand1), a first inverter (Inv1) and a second inverter (Inv2); The input end of the first NAND gate receives the first chip selection sampling signal and the first command address sampling signal respectively; the output end of the first NAND gate is connected to the input end of the first inverter; the output end of the first inverter is connected to the input end of the second inverter; The first NAND gate outputs the first control signal; the first inverter outputs the first control signal after the first delay; and the second inverter outputs the first control signal after the second delay.

5. The chip select signal control circuit according to claim 3 or 4, characterized in that: The first control signal generating circuit (10) further includes: a first data selector (Mux1); The first input terminal of the first data selector receives the first control signal after the second delay; the second input terminal of the first data selector receives the first control signal; and the control terminal of the first data selector receives an operation mode enable signal (EN).

6. The chip select signal control circuit according to claim 5, characterized in that: The first control signal generating circuit (10) further includes: a first level trigger (T1); The data input end of the first level trigger is connected to the output end of the first data selector; the clock input end of the first level trigger receives the first frequency-divided clock signal; and the output end of the first level trigger serves as the output end of the first control signal generating circuit.

7. The chip select signal control circuit according to any one of claims 2 to 6, characterized in that: The second control signal generating circuit (20) comprises: a second NAND gate (Nand2), a first D flip-flop (DFF1) and a second data selector (Mux2); The input end of the second NAND gate receives the second chip selection sampling signal and the second command address sampling signal respectively; the output end of the second NAND gate is connected to the first input end of the second data selector; The data input terminal of the first D flip-flop receives the first control signal after the first delay, and the clock input terminal of the first D flip-flop receives the second frequency-divided clock signal; the in-phase output terminal of the first D flip-flop is connected to the second input terminal of the second data selector; The control terminal of the second data selector receives an operation mode enable signal (EN).

8. The chip select signal control circuit according to claim 7, characterized in that: The second control signal generating circuit further includes: a second level trigger (T2); The data input end of the second level trigger is connected to the output end of the second data selector; the clock input end of the second level trigger receives the first frequency-divided clock signal; and the output end of the second level trigger serves as the output end of the second control signal generating circuit.

9. The chip select signal control circuit according to any one of claims 1 to 8, characterized in that: The chip selection signal sampling circuit comprises: a second D flip-flop (DFF2), a third inverter (Inv3) and a fourth inverter (Inv4); The data input terminal of the second D flip-flop receives the initial chip select signal, and the clock input terminal of the second D flip-flop receives the first frequency-divided clock signal; The in-phase output terminal of the second D flip-flop is connected to the input terminal of the third inverter; the output terminal of the third inverter is connected to the input terminal of the fourth inverter; The fourth inverter outputs the current chip selection sampling signal.

10. The chip select signal control circuit according to any one of claims 1 to 9, characterized in that: The logic control circuit (40) comprises: an OR gate (Or1) and a third NAND gate (Nand3); The first input end of the OR gate is connected to the output end of the first control signal generating circuit; the second input end of the OR gate is connected to the output end of the second control signal generating circuit; The output end of the OR gate is connected to the first input end of the third NAND gate; the second input end of the third NAND gate receives the current chip selection sampling signal; the output end of the third NAND gate serves as the output end of the logic control circuit.

11. The chip select signal control circuit according to any one of claims 1 to 10, characterized in that: The chip select signal control circuit also includes: The command address signal sampling circuit (50) is configured to receive an initial command address signal (CA), the first frequency-divided clock signal (CLK_ET) and a second frequency-divided clock signal (CLK_OT), sample the initial command address signal into the first command address sampling signal according to the first frequency-divided clock signal; and sample the initial command address signal into the second command address sampling signal according to the second frequency-divided clock signal.

12. The chip select signal control circuit according to claim 11, characterized in that: The command address signal sampling circuit (50) comprises: a third D flip-flop (DFF3) and a fourth D flip-flop (DFF4); The data input terminal of the third D flip-flop receives the initial command address signal, the clock input terminal of the third D flip-flop receives the first frequency-divided clock signal, and the third D flip-flop outputs the first command address sampling signal; The data input terminal of the fourth D flip-flop receives the initial command address signal, the clock input terminal of the fourth D flip-flop receives the second frequency-divided clock signal, and the fourth D flip-flop outputs the second command address sampling signal.

13. A chip select signal processing circuit (70), characterized in that: include: The chip select signal control circuit (80) as claimed in any one of claims 1 to 12, and a decoding circuit (60); The decoding circuit is connected to the chip selection signal control circuit, and is configured to receive a current chip selection sampling signal (CS), decode the current chip selection sampling signal and output it.

14. A memory (90), characterized in that: The memory comprises the chip select signal processing circuit (70) as claimed in claim 13.

15. The memory according to claim 14, characterized in that: The memory is the fifth generation double data rate synchronous dynamic random access memory (DDR5 DRAM).

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