Display pixel comprising light-emitting diodes for a display screen

Abstract

The present disclosure relates to a display pixel for a display screen, comprising at least one light-emitting device, a driver circuit for driving the light-emitting device, the display pixel receiving a first voltage (Vcc) and a first binary signal, the light-emitting device being powered with the first voltage. The display pixel further comprises a supply circuit (60) providing a power supply voltage (Vdd), inferior to the first voltage, for the powering of the driver circuit. The supply circuit comprises a first capacitor (C1) charged with a reference power supply voltage (Vdd_Ref) from the first binary signal. The supply circuit further comprises a voltage follower circuit (OAmp) providing the power supply voltage at its output, the voltage follower circuit being supplied by the first voltage, being coupled to the first capacitor, and maintaining the power supply voltage equal to the reference power supply voltage.

Description

B22967PCT – IR00251    DESCRIPTION Display pixel comprising light-emitting diodes for a display screen This application claims the priority benefit of French patent application number 23 / 06015, filed on 13 / 06 / 2023, entitled "Display pixel comprising light-emitting diodes for a display screen", which is hereby incorporated by reference to the maximum extent allowable by law. Technical field

[0001] The present disclosure generally concerns display pixels comprising light-emitting diodes for a display screen. Background art

[0002] A pixel of an image corresponds to the unit element of the image displayed by a display screen. For the display of color images, a display screen generally comprises, for the display of each pixel of the image, at least three components, also called display sub-pixels, which each emit a light radiation substantially in a single color (for example, red, green, and blue). The superposition of the radiations emitted by the three display sub-pixels provides the observer with the colored sensation corresponding to the pixel of the displayed image. In this case, the assembly formed by the three display sub-pixels used for the display of a pixel of an image is called display pixel of the display screen. Each display sub-pixel may comprise a light source, particularly a light-emitting diode.

[0003] The display pixels may be distributed in an array, each display pixel being located at the intersection of a row (or line) and of a column of the array. Generally, each row of display pixels is successively selected, and the display pixels of the selected row are programmed to display the desired image pixels.B22967PCT – IR00251

[0004] An active array is a screen drive architecture enabling to maintain all the pixel rows active for the entire duration of an image, conversely to arrays called passive, where each row is only active for a time T = Tframe / N (where Tframe is the duration of the image and N is the number of rows of the screen). This enables to increase the luminosity of the display screen. Further, it is possible to send low voltage or current levels onto the array control lines, which enables to display more significant data flows.

[0005] In the context of a screen based on light-emitting diodes of micrometer-range dimensions formed on electronic circuits, the size of the light-emitting diode circuit is generally smaller than the size of the image pixel due to the high intrinsic luminosity of light-emitting diodes. One of the solutions used thus is to deposit these unit light- emitting diodes on a support (also called slab) containing the drive electronics. Another solution comprises using display pixels comprising light-emitting diodes and a circuit for controlling the light-emitting diodes. It is then spoken of smart pixels. This particularly enables to simplify the forming of an active array, since the control electronics of the light-emitting diodes of the display pixel is for the most part embedded on the display pixel. Document WO 2018 / 185433 describes an example of a smart pixel.

[0006] For a smart pixel, the number of bonding conductive pads of the smart pixel, used for the electric connection of the smart pixel to the support, imposes the dimensions of the smart pixel, particularly due to the minimum size of these pads and to the minimum space to be provided between these pads. To limit the number of bonding conductive pads, it is known to deliver a single power supply voltage to the display pixels, and each display pixel internally generates one or aB22967PCT – IR00251    plurality of decreased power supply voltages, particularly for the biasing of components of the control electronics.

[0007] The static power consumption of a display pixel corresponds to the electric power consumed by the display pixel when the latter emits no light. It may be formed of the leakage currents of components or currents necessary to the internal operation of the display pixel control circuit. In the context of smart pixels, a significant part of the static power consumption originates from the generation of power supply voltages internally to the smart pixel.

[0008] It may be envisaged to provide an additional conductive pad, on each smart pixel, to supply the smart pixel with the decreased power supply voltage so that it is not generated within the smart pixel. However, this may cause an increase in the dimensions of the smart pixel, which is not desirable.

[0009] The tendency is to the increase of the number of display pixels of the display screen. The static power consumption of the display pixels may then become a critical factor. Indeed, for a so-called 4K display screen having a resolution of 2,160 by 3,840 display pixels, the static power consumption of the display screen may be greater than 150 W.

[0010] There is a need to decrease the static power consumption of the display screen. Summary of Invention

[0011] An object of an embodiment is to provide a display screen comprising light-emitting diodes overcoming all or part of the disadvantages of existing display screens comprising light-emitting diodes.

[0012] Another object of an embodiment is to provide another way of providing the decreased power supply voltage for theB22967PCT – IR00251    powering of the driver circuit of the display pixel. Another object of an embodiment is for the display pixels to have dimensions smaller than 200 µm, which limits the number of bonding conductive pads between the display pixel and the support of the display pixels.

[0013] One embodiment provides a display pixel for a display screen, comprising at least one light-emitting device, for example a light-emitting diode, a driver circuit for driving the light-emitting device, the display pixel being configured to receive a first voltage and a first binary signal, the light-emitting device being powered with the first voltage, the display pixel further comprising a supply circuit configured to provide a power supply voltage, inferior to the first voltage, for the powering of the driver circuit, the supply circuit comprising a first capacitor configured to be charged with a reference power supply voltage from the first binary signal, said supply circuit further comprising a voltage follower circuit providing the power supply voltage at its output, the voltage follower circuit being supplied by the first voltage, being coupled to the first capacitor, and being configured to maintain the power supply voltage equal to the reference power supply voltage.

[0014] A charge of the first capacitor occurs when the first binary signal is at logical state "1". Therefore, the reference decreased voltage is generated when the first binary signal is equal to the high state "1". Therefore, the reference decreased voltage can be obtained with precision since it is generated from the first binary signal that is provided with precision. The operational amplifier provides the decreased voltage and supplies the electronic components of the driver circuit coupled to the output of the operational amplifier with a current that is advantageously drawn from the source of the high reference potential and not from theB22967PCT – IR00251    pad receiving the first binary signal. The reference decreased voltage is used only as a comparison voltage for the generation of the decreased voltage. Therefore, the discharge of the first capacitor occurs mainly by tiny leakage currents but not by the power consumption of components of the driver circuit.

[0015] According to an embodiment, the display pixel comprises at least first, second, and third bonding electrically-conductive pads, the first voltage being received between the first and second bonding electrically- conductive pads, the first binary signal being received on the third bonding electrically-conductive pad, the first binary signals alternating between a second voltage, lower than the first voltage, and a third voltage, lower than the second voltage, the driver circuit being configured to drive the light-emitting device from the first binary signal received on the third bonding electrically-conductive pad. The charge of the first capacitor is only performed by currents drawn from the third bonding electrically-conductive pad.

[0016] According to an embodiment, the supply circuit comprises a first branch coupling the third bonding electrically-conductive pad and the first capacitor, the first branch comprising only one or more Schottky diodes, diodes, and / or transistors. The component on the first branch advantageously prevents a discharge of the first capacitor through the third bonding electrically-conductive pad when the first binary signal is at logical state "0".

[0017] According to an embodiment, the supply circuit further comprises a second capacitor, the voltage follower circuit being configured to charge the second capacitor with the power supply voltage. Second capacitor allows a betterB22967PCT – IR00251    stabilization of the power supply voltage to be obtained, in particular when a high current is drawn by the components of the driver circuit supplied with the power supply voltage.

[0018] According to an embodiment, the voltage follower circuit is supplied by the first voltage through a switch and the supply circuit further comprises a trigger circuit configured to command the switch, preferably based on the first binary signal. The voltage follower circuit can be activated, by closing the switch, only when strong current in-rushes occur. This advantageously allows the power consumption of the voltage follower circuit to be reduced.

[0019] According to an embodiment, the trigger circuit is configured to close the switch, during a given duration, after each falling edge and / or each rising edge of the first binary signal.

[0020] According to an embodiment, the second capacitor is configured also to be charged by the first binary signal. A charge of the second capacitor occurs when the first binary signal is at logical state "1". The charge of the second capacitor is advantageously also performed by means of the first binary signal.

[0021] According to an embodiment, the supply circuit comprises a second branch coupling the third bonding electrically-conductive pad and the second capacitor, the second branch comprising only one or more Schottky diodes, diodes, and / or transistors. The component on the second branch advantageously prevents a discharge of the second capacitor through the third bonding electrically-conductive pad when the first binary signal is at logical state "0".

[0022] According to an embodiment, the display pixel is intended to receive a second binary signal, and the first capacitor is configured to be charged with the reference powerB22967PCT – IR00251    supply voltage from the first binary signal and the second binary signal. The charge of the first capacitor is advantageously improved since it is performed by both first binary signal and second binary signal.

[0023] According to an embodiment, the display pixel comprises at least one fourth bonding electrically-conductive pads, the second binary signal being received on the fourth bonding electrically-conductive pad, the driver circuit being configured to drive the light-emitting device from the first binary signal received on the third bonding electrically- conductive pad and the second binary signal received on the fourth bonding electrically-conductive pad, the second binary signal alternating between the second voltage and the third voltage.

[0024] According to an embodiment, the supply circuit comprises a third branch coupling the fourth bonding electrically-conductive pad and the first capacitor, the third branch comprising only one or more Schottky diodes, diodes, and / or transistors. The component on the third branch advantageously prevents a discharge of the first capacitor through the fourth bonding electrically-conductive pad when the second binary signal is at logical state "0".

[0025] According to an embodiment, the second capacitor is configured also to be charged by the second binary signal. The charge of the second capacitor is advantageously improved since it is also performed by the second binary signal.

[0026] According to an embodiment, the supply circuit comprises a fourth branch coupling the fourth bonding electrically-conductive pad and the second capacitor, the fourth branch comprising only one or more Schottky diodes, diodes, and / or transistors. The component on the fourth branch advantageously prevents a discharge of the second capacitorB22967PCT – IR00251    through the fourth bonding electrically-conductive pad when the second binary signal is at logical state "0".

[0027] According to an embodiment, the voltage follower circuit comprises an operational amplifier having a non- inverting input, an inverting input, and an output, the non- inverting input of the operational amplifier being coupled to the first capacitor, the output of the operational amplifier providing the power supply voltage, and the inverting input of the operational amplifier being connected to the output of the operational amplifier.

[0028] According to an embodiment, each of the first capacitor and the second capacitor comprises an electrode connected to the second bonding electrically-conductive pad.

[0029] According to an embodiment, the driver circuit is configured to determine a digital signal from values of the second binary signal received relatively to first pulses of the first binary signal and to command the light-emitting device based on the digital signal.

[0030] According to an embodiment, the driver circuit is configured to control the light-emitting device by pulse- width modulation based on the digital signal.

[0031] According to an embodiment, the driver circuit is configured to turn on or turn off the light-emitting device at the rate of second pulses of the first binary signal at the second voltage or at the third voltage.

[0032] According to an embodiment, the display pixel only comprises the first, second, third, and fourth bonding electrically-conductive pads. This embodiment is advantageous since the number of bonding electrically-conductive pads is reduced and there is not a bonding electrically-conductive pad dedicated to receive a decreased supply voltage. However,B22967PCT – IR00251    the display pixel can comprise more four bonding electrically- conductive pads even though no bonding electrically- conductive pad is dedicated to receive a decreased supply voltage.

[0033] According to an embodiment, the first binary signal is a first binary voltage and the second binary signal is a second binary voltage.

[0034] One embodiment also provides a display screen comprising an array of display pixels as previously defined, the display screen further comprising circuits for delivering, for each display pixel, the first voltage between the first and second bonding electrically-conductive pads, the first binary signal on the third bonding electrically-conductive pads, and the second binary signal on the fourth bonding electrically-conductive pad.

[0035] One embodiment also provides a method of controlling a display screen comprising an array of display pixels as previously defined, the method comprising the delivery, for each display pixel, of the first voltage between the first and second bonding electrically-conductive pads, the delivery of the first binary signal on the third bonding electrically- conductive pad, and the delivery of the second binary signal on the fourth bonding electrically-conductive pad.

[0036] According to an embodiment, the method comprises the delivery of the first binary signal and of the second binary signal such that, in operation, the ratio of the average duration for which at least one of the first binary signal and of the second binary signal is at the second voltage to the sum of the average duration for which the first binary signal and the second binary signal are at the third voltage and of the average duration for which at least one of theB22967PCT – IR00251    first binary signal and of the second binary signal is at the second voltage is greater than 75%.

[0037] According to an embodiment, the method comprises the delivery of the first binary signal and of the second binary signal such that, at any time in operation, at least one of the first binary signal and of the second binary signal is at the second voltage.

[0038] According to an embodiment, the reference power supply voltage is inferior to the second voltage by less than 10% and the power supply voltage is inferior to the second voltage by less than 10%. Brief description of drawings

[0039] The foregoing features and advantages, as well as others, will be described in detail in the following description of specific embodiments given by way of illustration and not limitation with reference to the accompanying drawings, in which:

[0040] Figure 1 partially and schematically shows an example of a display screen;

[0041] Figure 2 is a very simplified cross-section view of an example of a display pixel;

[0042] Figure 3 is a bottom view of the display pixel of Figure 2;

[0043] Figure 4 shows a block diagram of an embodiment according to the invention of a display pixel of the display screen of Figure 1;

[0044] Figure 5 shows a block diagram of an embodiment of a circuit for charging a capacitor of the display pixel of Figure 4;B22967PCT – IR00251

[0045] Figure 6 shows a block diagram of another embodiment of a circuit for charging a capacitor of the display pixel of Figure 4;

[0046] Figure 7 shows a block diagram of another embodiment of a circuit for charging a capacitor of the display pixel of Figure 4;

[0047] Figure 8 shows examples of timing diagrams of signals of the display pixel of Figure 7 according to an embodiment of an operating method of the display screen;

[0048] Figure 9 shows a block diagram of another embodiment of a circuit for charging a capacitor of the display pixel of Figure 4;

[0049] Figure 10 shows a block diagram of another embodiment of a circuit for charging a capacitor of the display pixel of Figure 4;

[0050] Figure 11 shows a block diagram of another embodiment of a circuit for charging a capacitor of the display pixel of Figure 4;

[0051] Figure 12 shows a block diagram of another embodiment of a circuit for charging a capacitor of the display pixel of Figure 4;

[0052] Figure 13 shows an electric diagram of an embodiment of a part of the circuit for charging the capacitor of Figure 7, 9, 11, or 12;

[0053] Figure 14 shows an electric diagram of an embodiment of another part of the circuit for charging the capacitor of Figure 7, 9, 11, or 12;

[0054] Figure 15 shows a more detailed block diagram of an embodiment according to the invention of the display pixel of Figure 4;B22967PCT – IR00251

[0055] Figure 16 shows examples of timing diagrams of signals of the display pixel of Figure 15 according to an embodiment of an operating method of the display screen;

[0056] Figure 17 shows timing diagrams of signals of the display pixel of Figure 15 according to another embodiment of an operating method of the display screen;

[0057] Figure 18 shows an electric diagram of an embodiment of the current source of the display pixel of Figure 15; and

[0058] Figure 19 shows an electric diagram of another embodiment of the current source of the display pixel of Figure 15. Description of embodiments

[0059] Like features have been designated by like references in the various figures. In particular, the structural and / or functional features that are common among the various embodiments may have the same references and may dispose identical structural, dimensional and material properties. For the sake of clarity, only the steps and elements that are useful for an understanding of the embodiments described herein have been illustrated and described in detail.

[0060] Unless indicated otherwise, when reference is made to two elements connected together, this signifies a direct connection without any intermediate elements other than conductors, and when reference is made to two elements coupled together, this signifies that these two elements can be connected or they can be coupled via one or more other elements.

[0061] Further, a signal which alternates between a first constant state, for example, a low logical state, noted "0", and a second constant state, for example, a high logical state, noted "1", is called a "binary signal". The high and lowB22967PCT – IR00251    states of different binary signals of a same electronic circuit may be different. In practice, the binary signals may correspond to voltages or to currents which may not be perfectly constant in the high or low state.

[0062] Further, in the following description, there are called "power terminals" of an insulated gate field-effect transistor, or MOS transistor, the source and the drain of the MOS transistor.

[0063] Further, unless indicated otherwise, when it is spoken of a voltage at a conductive pad, the difference between the potential at said conductive pad and a reference potential, for example, the ground, taken as equal to 0 V, is considered.

[0064] Unless specified otherwise, the expressions "around", "approximately", "substantially" and "in the order of" signify within 10%, and preferably within 5%. Further the expression "substantially constant" means which varies by less than 10% over time with respect to a reference value.

[0065] In the following specification, embodiments are disclosed for a color display screen comprising color display pixels, each display pixel comprising light-emitting diodes adapted to emit radiations of different colors. However, these embodiments also apply for a monochromatic display screen comprising monochromatic display pixels, each monochromatic display pixel comprising one light-emitting diode or only light-emitting diodes adapted to emit a radiation of a single color.

[0066] Figure 1 partially and schematically shows a known example of a display screen 10. Display screen 10 comprises display pixels 12i,j, for example, arranged in M rows and in N columns, M being an integer varying from 1 to 8,000 and N being an integer varying from 1 to 16,000, i being an integer varying from 1 to M, and j being an integer varying from 1 toB22967PCT – IR00251    N. As an example, in Figure 1, M and N are equal to 6. Each display pixel 12i,jis coupled to a source of a low reference potential Gnd, for example, the ground, via an electrode 14iand to a source of a high reference potential Vcc via an electrode 16j. As an example, electrodes 14iare shown as being aligned along the rows in Figure 1 and electrodes 16jare shown as being aligned along the columns in Figure 1, the reverse layout being possible. The power supply voltage of the display screen 10 corresponds to the voltage between high reference potential Vcc and low reference potential Gnd, and is noted Vcc like the high reference potential. Power supply voltage Vcc particularly depends on the arrangement of the light-emitting diodes and on the technology according to which the light-emitting diodes are manufactured. As an example, power supply voltage Vcc may be in the order of from 3.5 V to 5.5 V.

[0067] For each row, the display pixels 12i,jin the row are coupled to a row electrode 18i. For each column, the display pixels 12i,jin the column are coupled to a column electrode 20j. Display screen 10 comprises a selection circuit 22 coupled to row electrodes 18iand adapted to delivering a selection and timing signal Comion each row electrode 18i. Display screen 10 comprises a data delivery circuit 24 coupled to column electrodes 20jand adapted to delivering a data signal Datajon each column electrode 20j. Selection circuit 22 and data delivery circuit 24 are controlled by a circuit 26, for example comprising a processor.

[0068] Figure 2 is a very simplified cross-section view of a known example of display pixel 12i,jand Figure 3 is a bottom view of display pixel 12i,j. Each display pixel 12i,jcomprises a control circuit 30 covered with a display circuit 32. Display circuit 32 comprises at least one light-emitting diode LED, preferably at least three light-emitting diodes LED. TheB22967PCT – IR00251    display pixel comprises a lower surface 34 and an upper surface 35 opposite to lower surface 34, surfaces 34 and 35 being preferably planar and parallel. Control circuit 30 further comprises bonding conductive pads P_Gnd, P_Vcc, P_Col, P_Row on lower surface 34. Control circuit 30 may correspond to an integrated circuit comprising electronic components, particularly insulated gate field effect transistors, also called MOS transistors, or thin film transistors, also called TFTs. Preferably, display circuit 32 only comprises light- emitting diodes LED and the conductive elements of these light-emitting diodes LED and control circuit 30 comprises all the electronic components necessary for the control of the light-emitting diodes LED of display circuit 32. As a variant, display circuit 32 may also comprise other electronic components in addition to light-emitting diodes LED. Light- emitting diodes LED may be 2D light-emitting diodes, also called planar light-emitting diodes, comprising a stack of planar layers, or 3D light-emitting diodes, each comprising a three-dimensional semiconductor element covered with an active area. In Figure 2, light-emitting diodes LED are shown as being connected with a common anode. It may however be desirable to arrange light-emitting diodes LED according to another configuration. As an example, light-emitting diodes LED may be connected with a common cathode, or be connected independently from one another.

[0069] According to an embodiment, display pixel 12i,jcomprises three light sources emitting light at first, second, and third wavelengths. According to an embodiment, the first wavelength corresponds to blue light and is within the range from 430 nm to 490 nm. According to an embodiment, the second wavelength corresponds to green light and is within the range from 510 nm to 570 nm. According to an embodiment, the thirdB22967PCT – IR00251    wavelength corresponds to red light and is within the range from 600 nm to 720 nm.

[0070] Each conductive pad P_Gnd, P_Vcc, P_Col, P_Row is intended to be connected to one of the electrodes 14i, 16j, 18i, 20jschematically shown in Figure 2. The first conductive pad P_Vcc is coupled to electrodes 14iand receives high reference potential Vcc. The second conductive pad P_Gnd is coupled to electrodes 16jand receives low reference potential Gnd. The third conductive pad P_Col is coupled to column electrode 20jand receives data signal Dataj. The fourth conductive pad P_Row is coupled to row electrode 18iand receives selection and timing signal Comi. The dimensions of conductive pads P_Gnd, P_Vcc, P_Col, P_Row and the layout of conductive pads P_Gnd, P_Vcc, P_Col, P_Row on surface 34 are particularly imposed by the rules of design of display pixel 12i,jand by the method of assembly of display pixels 12i,jin display screen 10. According to an embodiment, in bottom view, display pixel 12i,jhas dimensions smaller than 200 µm.

[0071] Figure 4 shows an example of a block diagram of a display pixel 12i,jof display screen 10.

[0072] According to an example, display pixel 12i,jcomprises at least three light-emitting diodes, a single light-emitting diode LED being shown in Figure 4. Each light-emitting diode LED is coupled in series with a controllable current source CS. In the present example, for each light-emitting diode LED, the anode of light-emitting diode LED is for example coupled to the conductive pad P_Vcc receiving high reference potential Vcc and the cathode of light-emitting diode LED is for example coupled to a terminal of controllable current source CS, the other terminal of controllable current source CS being coupled to the conductive pad P_Gnd receiving low reference potential Gnd. As a variation, for each light-emitting diode LED, theB22967PCT – IR00251    cathode of light-emitting diode LED is for example coupled to the conductive pad P_Gnd receiving low reference potential Gnd and the anode of light-emitting diode LED is coupled to a terminal of controllable current source CS, the other terminal of controllable current source CS being coupled to the conductive pad P_Vcc receiving high reference potential Vcc.

[0073] Display pixel 12i,jfurther comprises a circuit 40 for driving controllable current source CS. Driver circuit 40 may particularly comprise electronic components such as MOS transistors or TFTs. Driver circuit 40 may be formed, in whole or in part, in control circuit 30. Driver circuit 40 may essentially correspond to a logic circuit.

[0074] It may be desirable to use a decreased power supply voltage Vdd, inferior to supply voltage Vcc, for example lower than 4 V, in particular in the order of 1 V or of 1.8 V, to power the electronic components of driver circuit 40, this decreased power supply voltage for example corresponding to the voltage likely to be applied between the power terminals of the MOS transistors. For this purpose, display pixel 12i,jcomprises a supply circuit 60 that supplies the decreased supply voltage Vdd. Supply circuit 60 receives high reference potential Vcc, and at least one of selection signal Comiand data signal Datajand provides the decreased supply voltage Vdd. .As an example, in Figure 4, supply circuit 60 is shown receiving high reference potential Vcc, selection signal Comiand data signal Dataj.

[0075] According to an embodiment, detection and timing signal Comi, received at conductive pad P_Row of each display pixel 12i,j, is a binary signal alternating between a low state "0" and a high state "1", the low state corresponding to low reference potential Gnd and the high state "1" correspondingB22967PCT – IR00251    to a low voltage, substantially equal to decreased power supply voltage Vdd. Data signal Datajis a binary signal alternating between a low state "0" and high state "1", the low state corresponding to low reference potential Gnd and the high state "1" corresponding to a low voltage, substantially equal to decreased power supply voltage Vdd.

[0076] Figure 5 shows a block diagram of an embodiment of supply circuit 60. Supply circuit 60 comprises a first capacitor C1 and a first diode D1 coupling, to a first electrode of capacitor C1, a conductive pad of display pixel 12i,jreceiving a signal that does not correspond to a constant voltage. In the present embodiment, diode D1 couples conductive pad P_Row receiving binary signal Comito the first electrode of capacitor C1. As a variation, diode D1 can couple conductive pad P_Col receiving binary signal Datajto the first electrode of capacitor C1. In the present embodiment, the anode of diode D1 is connected to conductive pad P_Row and the cathode of diode D1 is connected to the first electrode of capacitor C1. Capacitor C1 has a second electrode receiving low reference potential Gnd. The voltage across capacitor C1 corresponds to a reference decreased supply voltage Vdd_Ref. Diode D1 can correspond to a Schottky diode, a common diode, or a diode-mounted MOS transistor. The function of diode D1 is to prevent the circulation of a current fromm capacitor C1 to conductive pad P_Row. Diode D1 could be replaced by any electronic component or electronic components that would provide the same function.

[0077] Supply circuit 60 further comprises an operational amplifier OAmp having an non-inverting input (+), an inverting input (-), and an output. Operational amplifier OAmp is connected as voltage follower circuit. Non-inverting input (+) is coupled, preferably connected, to the first electrode of capacitor C1. Inverting input (-) of operational amplifierB22967PCT – IR00251    OAmp is coupled, preferably connected, to the output of operational amplifier OAmp. The output of operational amplifier OAmp provides decreased voltage Vdd. The electrical supply of operational amplifier OAmp is obtained by coupling operational amplifier OAmp to the high reference voltage Vcc and the low reference voltage Gnd. Decreased voltage Vdd is used for the electrical supply of the electrical components of driver circuit 40, in particular MOS transistors.

[0078] A charge of capacitor C1 occurs when selection and timing signal Comiis at logical state "1". Diode D1 prevents a discharge of capacitor C1 through pad P_Row when selection and timing signal Comiis at logical state "0". The charge of capacitor C1 is only performed by currents drawn from pad P_Row through diode D1. Therefore, reference decreased voltage Vdd_Ref is generated when timing signal Comiis equal to the high state "1". Therefore, reference decreased voltage Vdd_Ref can be obtained with precision since it is generated from selection and timing signal Comithat is provided with precision by selection circuit 22.

[0079] Operational amplifier OAmp maintains equal the voltage at its non-inverting input (+) and the voltage at its inverting input (-), that is to say voltages Vdd_Ref and Vdd. Therefore, operational amplifier OAmp provides decreased voltage Vdd and supplies the electronic components of driver circuit 40 coupled to the output of operational amplifier OAmp with a current drawn from pad P_Vcc receiving high reference potential Vcc and not from pad P_Row receiving selection and timing signal Comi. Reference decreased voltage Vdd_Ref is used only as a comparison voltage for the generation of decreased voltage Vdd. Therefore, the discharge of capacitor C1 occurs mainly by tiny leakage currents but not by the power consumption of components of driver circuit 40.B22967PCT – IR00251

[0080] Figure 6 shows a block diagram of another embodiment of supply circuit 60. Supply circuit 60 shown in Figure 6 comprises all the elements of supply circuit 60 shown in Figure 5 and further comprises a capacitor C2 having a first electrode coupled, preferable connected, to the output of rational amplifier OAmp. Capacitor C2 can have a second electrode receiving low reference potential Gnd. The voltage across capacitor C2 corresponds to decreased supply voltage Vdd. Capacitor C2 allows a better stabilization of power supply voltage Vdd to be obtained, in particular when a high current is drawn by the components of driver circuit 40 supplied with power supply voltage Vdd.

[0081] Figure 7 shows a block diagram of another embodiment of supply circuit 60. Supply circuit 60 shown in Figure 7 comprises all the elements of supply circuit 60 shown in Figure 6 and further comprises a controllable switch SW. Operational amplifier OAmp is coupled, preferably connected, to conductive pad P_Vcc receiving high reference voltage Vcc by means of controllable switch SW. Supply circuit 60 further comprises a trigger circuit 62 configured for providing a binary signal Ctrl controlling switch SW.

[0082] When switch SW is closed, operational amplifier OAmp is supplied by supply voltage Vcc. Operational amplifier OAmp then maintains equal the voltage at its non-inverting input (+) and the voltage at its inverting input (-), that is to say voltages Vdd_Ref and Vdd. Therefore, a charge of capacitor C2 can occur by means of operational amplifier OAmp, that is to say by a current drawn from pad P_Vcc receiving high reference potential Vcc. When switch SW is open, operational amplifier OAmp is not supplied by supply voltage Vcc and does not charge capacitor C2. The charge of capacitor C2 is performed through a current drawn from pad P_Row or through a current drawn from pad P_Vcc.B22967PCT – IR00251

[0083] The inventors have noted that the strongest current in-rushes drawn by the components of driver circuit 40 occur just after an rising and / or falling edge of the signal that clocks the operation of driver circuit 40, in particular the toggling between on and off states of the transistors of driver circuit 40. According to an embodiment, the operation of driver circuit 40 is clocked by selection and timing signal Comi. The inventors have noted that the strongest current in- rushes drawn by the components of driver circuit 40 occur just after an edge of binary selection and timing signal Comi. In that embodiment, trigger circuit 62 is coupled, preferably connected, to pad P_Row receiving binary selection and timing signal Comiand provides trigger signal Ctrl based on selection and timing signal Comiso that switch SW is close during each current in-rushes of driver circuit 40. Therefore, the current, during each current in-rushes of driver circuit 40, is drawn from pad P_Vcc receiving high reference voltage Vcc and not from pad P_Row receiving selection and timing signal Comiand pad P_Col receiving data signal Dataj. This is advantageous since, especially for display screen 10 comprising a high number of display pixels 12i,j, for example more than 100 display pixels 12i,jper row, it can be necessary to provide a damping resistor on each row electrode 18iand / or on each column electrode 20jin order to prevent oscillations of voltages on these electrodes. If the current during a current in-rushes of driver circuit 40 was drawn from pad P_Row receiving selection and timing signal Comiand / or pad P_Col receiving data signal Dataj, it could lead to a high voltage drop across the damping resistor so that the voltage level of selection and timing signal Comiand / or data signal Datajreaching some display pixels 12i,jcould be too low.

[0084] Figure 8 shows examples, for display pixel 12i,jof Figure 4 and supply circuit 60 of Figure 7, of timing diagramsB22967PCT – IR00251    of selection and timing signal Comireceived by display pixel 12i,j, current IL drawn by driver circuit 40 due to the power consumption of driver circuit 40, and signal Ctrl provided by trigger circuit 62 according to an embodiment of an operating method of display screen 10. According to an embodiment, the strongest current in-rushes drawn by the components of driver circuit 40 occur just after each rising edge of binary selection and timing signal Comi. Current IL comprises a peak Pk after just after each rising edge of binary selection and timing signal Comi. According to an embodiment, when binary trigger signal Ctrl is at logical state "0", switch SW is open and when binary trigger signal Ctrl is at logical state "1", switch SW is closed. Trigger circuit 62 sets trigger signal Ctrl at logical value "1" for a duration D when detecting a rising edge of selection and timing signal Comi. According to an embodiment, duration D is in the range from 10 ns and 30 ns. According to an embodiment, trigger circuit 62 comprises logic gates.

[0085] Figure 9 shows a block diagram of another embodiment of supply circuit 60. Supply circuit 60 shown in Figure 9 comprises all the elements of supply circuit 60 shown in Figure 7 and further comprises a second diode D2 coupling conductive pad P_Row to the first electrode of capacitor C2. The anode of diode D2 is connected to conductive pad P_Row and the cathode of diode D2 is connected to the first electrode of capacitor C2. Diode D2 can correspond to a Schottky diode, a common diode, or a diode-mounted MOS transistor.

[0086] A charge of capacitor C1 and of capacitor C2 occurs when timing signal Comiis at logical state "1". Diode D1 prevents a discharge of capacitor C1 through pad P_Row when selection and timing signal Comiis at logical state "0" andB22967PCT – IR00251    diode D2 prevents a discharge of capacitor C2 through pad P_Row when selection and timing signal Comi is at state "0".

[0087] When switch SW is closed, operational amplifier OAmp is supplied by supply voltage Vcc. Operational amplifier OAmp then maintains equal the voltage at its non-inverting input (+) and the voltage at its inverting input (-), that is to say voltages Vdd_Ref and Vdd. Therefore, a charge of capacitor C2 can occur by means of operational amplifier OAmp, that is to say by a current drawn from pad P_Vcc receiving high reference potential Vcc. When switch SW is open, operational amplifier OAmp is not supplied by supply voltage Vcc and does not participate to the charge of capacitor C2. The charge of capacitor C2 is then performed through a current drawn from pad P_Row.

[0088] Figure 10 shows a block diagram of another embodiment of supply circuit 60. Supply circuit 60 shown in Figure 10 comprises all the elements of supply circuit 60 shown in Figure 5 and further comprises a third diode D3 coupling conductive pad P_Col to the first electrode of capacitor C1. The anode of diode D3 is connected to conductive pad P_Col and the cathode of diode D3 is connected to the first electrode of capacitor C1. Diode D3 can correspond to a Schottky diode, a common diode, or a diode-mounted MOS transistor. The function of diode D3 is to prevent the circulation of a current from capacitor C1 to conductive pad P_Col. Diode D3 could be replaced by any electronic component or electronic components that would provide the same function.

[0089] A charge of capacitor C1 occurs when at least one of selection and timing signal Comiand data signal Datajis at logical state "1". Diode D1 prevents a discharge of capacitor C1 through pad P_Row when selection and timing signal Comiis at logical state "0" and diode D3 prevents a discharge ofB22967PCT – IR00251    capacitor C1 through pad P_Col when data signal Datajis at state "0". The charge of capacitor C1 is only performed by currents drawn from pad P_Row through diode D1 and / or from pad P_Col through diode D3. Therefore, reference decreased voltage Vdd_Ref is generated when timing signal Comiand / or data signal Datajare equal to the high state "1". Therefore, reference decreased voltage Vdd_Ref can be obtained with precision since it is generated from selection and timing signal Comiand data signal Datajthat are provided with precision by selection circuit 22 and data delivery circuit 24.

[0090] Figure 11 shows a block diagram of another embodiment of supply circuit 60. Supply circuit 60 shown in Figure 11 comprises all the elements of supply circuit 60 shown in Figure 7 and further comprises diode D3 coupling conductive pad P_Col to the first electrode of capacitor C1, as shown in Figure 10.

[0091] Figure 12 shows a block diagram of another embodiment of supply circuit 60. Supply circuit 60 shown in Figure 12 comprises all the elements of supply circuit 60 shown in Figure 11 and further comprises diode D2 coupling conductive pad P_Row to the first electrode of capacitor C1, as shown in Figure 10, and a fourth diode D4 coupling conductive pad P_Col to the first electrode of capacitor C2. The anode of diode D4 is connected to conductive pad P_Col and the cathode of diode D4 is connected to the first electrode of capacitor C2. Diode D4 can correspond to a Schottky diode, a common diode, or a diode-mounted MOS transistor.

[0092] A charge of capacitor C1 and of capacitor C2 occurs when at least one of selection and timing signal Comiand data signal Datajis at logical state "1". Diode D1 prevents a discharge of capacitor C1 through pad P_Row when selectionB22967PCT – IR00251    and timing signal Comiis at logical state "0" and diode D2 prevents a discharge of capacitor C2 through pad P_Row when selection and timing signal Comi is at state "0". Diode D3 prevents a discharge of capacitor C1 through pad P_Col when data signal Datajis at state "0" and diode D4 prevents a discharge of capacitor C2 through pad P_Col when data signal Datajis at state "0".

[0093] Figure 13 shows an electric diagram of an embodiment of operational amplifier OAmp of Figures 5 to 7 and 9 to 12 and switch SW of supply circuit 60 of Figure 7, 9, 11, or 12.

[0094] Operational amplifier OAmp comprises a differential pair comprising a MOS transistor T1, for example an N-MOS transistor, and a MOS transistor T2, for example an N-MOS transistor. The gate of transistor T1 corresponds to the non- inverting input of operational amplifier OAmp and receives voltage Vdd_Ref. The gate of transistor T2 corresponds to the inverting input of operational amplifier OAmp and receives voltage Vdd. Operational amplifier OAmp further comprises a current mirror comprising a MOS transistor T3, for example an P-MOS transistor, and a MOS transistor T4, for example an P- MOS transistor. The gate of transistor T3 is coupled, preferably connected, to the gate of transistor T4 and to the drain of transistor T3. The source of transistor T3 and the source of transistor T4 are coupled, preferably connected, to a node N. The drain of transistor T3 is coupled, preferably connected, to the drain of transistor T1. The drain of transistor T4 is coupled, preferably connected, to the drain of transistor T2. Operational amplifier OAmp further comprises a MOS transistor T5, for example an N-MOS transistor. The gate of transistor T5 is coupled, preferably connected, to node N. The drain of transistor T5 is coupled, preferably connected, to the sources of transistors T1 and T2. The source of transistor T5 receives low reference voltage Gnd.B22967PCT – IR00251    Operational amplifier OAmp further comprises a MOS transistor T6, for example an N-MOS transistor, and a MOS transistor T7, for example an N-MOS transistor. The drain of transistor T6 is coupled, preferably connected, to node N. The gate of transistor T6 is coupled, preferably connected, to the drain of transistor T2. The source of transistor T7 receives low reference voltage Gnd. The source of transistor T6 is coupled, preferably connected, to the drain of transistor T7. The gate of transistor T7 is coupled, preferably connected, to the gate of transistor T5. The source of transistor T6 corresponds to the output of operational amplifier OAmp.

[0095] Switch SW of supply circuit 60 comprises a transistor MOS T8, for example a P-MOS transistor, a transistor MOS T9, for example an N-MOS transistor, and a transistor MOS T10, for example an N-MOS transistor. The gate of each transistor T8, T9, and T10 receives a signal / Ctrl that is the opposite of signal Ctrl provided by trigger circuit 62. The source of transistor T8 receives high reference potential Vcc. The source of transistor T9 receives low reference potential Gnd. The drain of transistor T8 and the drain of transistor T9 are coupled, preferably connected, to node N. The source of transistor T10 receives low reference potential Gnd. The drain of transistor T10 is coupled, preferably connected, to the drain of transistor T2. When signal Ctrl is a logical value "0", transistors T9 and T10 are in an on state and transistor T8 is in an off state. Node N is substantially at low reference voltage Gnd and the drain of transistor T2 is substantially at low reference voltage Gnd. Operational amplifier OAmp is not electrically supplied and does not work. When signal Ctrl is a logical value "1", transistors T9 and T10 are in an off state and transistor T8 is in an on state. Node N is substantially at high reference voltage Vcc and the drain of transistor T2 can rise from low reference voltage Gnd.B22967PCT – IR00251    Operational amplifier OAmp is electrically supplied by supply voltage Vcc and can operate.

[0096] Figure 14 shows an electric diagram of an embodiment of trigger circuit 62 of supply circuit 60 of Figure 7, 9, 11, or 12. Trigger circuit 62 comprises a delay circuit DEL receiving selection and timing signal Comiand providing a signal DCom corresponding to signal selection and timing signal Comishifted in time of duration D. Trigger circuit 62 further comprises an inverter INV and an AND logic gate AND. The input of inverter INV is coupled, preferably connected, to the output of delay circuit DEL. Inverter INV receives signal DCom and provides a signal / DCom, that is the opposite of signal DCom. A first input of logic gate AND is coupled, preferably connected, to the output of inverter INV. The first input of logic gate AND receives signal / DCom and a second input of logic gate AND receives selection and timing signal Comi. The output of logic gate AND provides trigger signal Ctrl. When selection and timing signal Comiremains at logical value "0" or "1", signal / DCom has the opposite value to selection and timing signal Comiso that signal Ctrl is at logical value "0". When selection and timing signal Comigoes from logical value "0" to logical value "1", that is to say for a rising edge of selection and timing signal Comi, signal / DCom remains for a duration D at the preceding value of signal Comi, that is "0". Therefore, both inputs of logic gate AND are at logical value "1" and signal Ctrl is at logical value "1". When selection and timing signal Comigoes from logical value "1" to logical value "0, that is to say for a falling edge of selection and timing signal Comi, signal / DCom remains for a duration D at the preceding value of signal Comi, that is "1". Therefore, both inputs of logic gate AND are at logical value "0" and signal Ctrl is at logical value "0".B22967PCT – IR00251

[0097] Figure 15 shows a more detailed block diagram of an embodiment of driver circuit 40 of display pixel 12i,jof Figure 4 configured to drive the light emitting diodes LED by pulse width modulation (PWM).

[0098] Driver circuit 40 comprises a circuit 46 (Mode selection) coupled to conductive pad P_Col receiving data signal Datajand coupled to conductive pad P_Row receiving selection and timing signal Comi, and configured to deliver a clock signal Clk and data Data to a storage circuit 48 (Color Data registers) or to deliver a signal PWM to implement a pulse width modulation to a circuit 50 (LED driver) for controlling the controllable current source CS associated with each light-emitting diode LED. Storage circuit 48 is configured to store color signals R, G, B representative of the image pixel to be displayed. Circuit 50 is configured to control the controllable current sources CS coupled to light- emitting diodes LED with signals I_red, I_green, and I_blue, obtained from the R, G, B color signals, and from signal PWM. In the present embodiment, data Data can correspond to data signal Datajand clock signal Clk is obtained from selection and timing signal Comi.

[0099] As a variant, data signals Datajallow both the determination, by each display pixel 12i,j, of a clock signal and of the R, G, B color signals representative of the light intensities desired for the radiations at the first, second, and third wavelengths. In this case, driver circuit 40 further comprises a circuit coupled to conductive pad P_Col receiving data signal Datajand delivering, based on data signal Dataj, clock signal Clk and data Data. Circuit 46 (Mode selection) receives signals Clk and Data, and is coupled to conductive pad P_Row receiving selection and timing signal Comi, and is configured to deliver signals Clk and Data to storage circuit 48 or to deliver signal PWM to circuit 50.B22967PCT – IR00251

[0100] Figure 16 shows a timing diagram of signals received by display pixels 12i,jhaving the structure shown in Figure 15 for an embodiment of a method of displaying an image on display screen 10.

[0101] Potentials Vcc and Gnd are substantially constant. The image pixels of a new image to be displayed are successively displayed from the row of rank 1 to the row of rank M. Call frame duration T the duration separating two successive selections of the same row of display screen 10. Timing diagrams of signals Com1and Data1will be detailed for the row of rank 1, knowing that the timing diagrams of signals Comiare similar to the timing diagram of signal Com1, although shifted in time. Data signal Data1contains a succession of bits having the same duration and at state "1" or "0", shown by crossed rectangles in Figure 16. The display of a new image pixel by a display pixel 121,j, with j varying from 1 to N, of the row of rank 1 comprises a first phase P1 followed by a second phase P2. During phase P1, data signals Datajare transmitted to each display pixel 121,jof the row of rank 1, only signal Data1being shown in Figure 16. During second phase P2, the light-emitting diodes of each display pixel 121,jare controlled from the R, G, B color signals, determined based on data signals Dataj.

[0102] During first phase P1, selection and timing signal Com1comprises successive regularly spaced pulses at state "1". The succession of pulses at state "1" of signal Com1is detected by the circuit 46 of each display pixel 121,jof the row of rank 1 and thus enables to select the display pixels 121,jof this row, while the display pixels of the other rows are not selected. During first phase P1, data signals Datajare transmitted onto column electrodes 20j. For each display pixel 121,j, circuit 44 determines clock signal Clk based on the pulses of selection and timing signal Comiand data DataB22967PCT – IR00251    based data signal Dataj. Circuit 46, of each display pixel 121,j of selected row, delivers, at the rate of clock signal Clk, the data Data which are stored in circuit 50 in the form of R, G, B digital signals having their bits provided by the successive values of signal Data. The end of first period P1 for a row corresponds to the beginning of first period P1 for the next row.

[0103] As a variant, during first phase P1, selection and timing signal Com1is set at state "0" and clock signal Clk and data Data are determined based data signal Dataj. As an example, each pulse of data signal Datajmay have a first duration or a second duration, longer than the first duration. Signal Clk may correspond to a sequence of pulses of same durations having their rising edges coinciding, to within a possible constant offset, with the rising edges of the pulses of data signal Dataj. Data Data may correspond to a binary signal at state "0" when the pulse of signal Datajhas the first duration, and at state "1" when the pulse of signal Datajhas the second duration. Circuit 46, selected by signal Com1 at state "0", delivers, at the rate of clock signal Clk, the data Data which are stored in circuit 50 in the form of R, G, B digital signals having their bits provided by the successive values of signal Data. The end of first period P1 for a row corresponds to the beginning of first period P1 for the next row.

[0104] According to an embodiment, the light-emitting diodes of display pixel 121,jare controlled by pulse-width modulation or PWM control. For this purpose, during second phase P2, selection and timing signal Com1exhibits the repetition of a succession of pulses at state "1" which are transmitted by the circuit 46 of each display pixel 121,jof the row of rank 1 to circuit 50 (PWM signal) to clock the operation of circuit 50 for the control of light-emitting diodes LED by pulse-B22967PCT – IR00251    width modulation. The number of pulses in the succession corresponds to the number of bits of each R, G, and B digital signal. As an example, when controllable current source CS comprises a MOS transistor in series with a current source, this transistor is turned on or is turned off, at the rate of the PWM pulses, according to the value "0" or "1" of each bit of R, G, or B color signal, starting by the most significant bit, this transistor being maintained on or off until the next pulse of signal Com1. The duration between two successive pulses of signal Com1is divided each time by two, so that the total duration for which the light-emitting diode is on depends on the value of the R, G, or B color signal. The succession of pulses of signal Com1is repeated until the next first phase P1 of the row of rank 1, a single repetition being illustrated as an example in Figure 16. As a variation, the transistor of controllable current source CS is turned on or is turned off, at the rate of the PWM pulses, according to the value "0" or "1" of each bit of R, G, or B color signal, starting by the most significant bit, this transistor being maintained on or off until the next pulse of signal Com1. The duration between two successive pulses of signal Com1is then multiplied each time by two, so that the total duration for which the light-emitting diode is on depends on the value of the R, G, or B color signal.

[0105] In the present embodiment, selection and timing signal Comiis most of the time at state "1". This advantageously enables to obtain a more frequent recharging of the capacitors C1 or C2 of circuit 60 for delivering decreased voltage Vdd, and thus to further decrease the capacitance of capacitors C1 and C2. As a variation, selection and timing signal Comican be inverted with respect what is shown in Figure 16.

[0106] Generally, according to an embodiment, the ratio of the average duration for which at least one of signal ComiB22967PCT – IR00251    and of signal Datajis at decreased voltage Vdd to the sum of the average duration for which signal Comiand signal Datajare at low reference potential Gnd and of the average duration for which at least one of signal Comiand of second signal Datajis at voltage Vdd is greater than 75%, preferably greater than 85%, more preferably greater than 95%.

[0107] Figure 17 shows a timing diagram of signals received by display pixels 12i,jhaving the structure shown in Figure 15 for another embodiment of a method of displaying an image on display screen 10.

[0108] In Figure 17, timing diagrams of signals Com1, Com2, Com3and Data1for the rows of rank 1, 2, and 3 and the column of rank 1 have been shown, knowing that the timing diagram of the other signals Comiare similar to the timing diagram of signal Com1although shifted in time. The timing diagrams of signals Vcc, Gnd, not shown, and of the signals Comiof the embodiment illustrated in Figure 17 may be identical to those shown in Figure 16. The timing diagrams of signals Comiand data signals Datajof the embodiment illustrated in Figure 17 are identical to those shown in Figure 16 with the difference that each phase P1 comprises two successive phases P1.1 and P1.2. During phase P1.1, each data signal Dataj, j varying from 1 to N, is held at state "1" when one of signals Comi, i varying from 1 to N, is at state "0" for a long duration for the selection of the row of rank i. During the phase P1.2 which follows phase P1.1, data signals Datajare transmitted onto the column electrodes 20jand are acquired by the display pixels 12i,jof the row of rank i. This embodiment is advantageous since, at any time, for each display pixel 12i,j, at least one of the signals Comiand Datajreceived by display pixel 12i,jis at state "1".B22967PCT – IR00251

[0109] In the previously-described embodiments, the light- emitting diodes LED of display pixel 121,jare controlled by pulse-width modulation. However, the control of the light- emitting diodes LED of display pixel 121,jmay be different from a control by pulse-width modulation. According to an embodiment, the control of light-emitting diodes LED is a current level control.

[0110] Figure 18 shows an embodiment of current source CS where current source CS comprises N elementary controllable current sources CS1to CSN, where N is an integer greater than or equal to 2. Preferably, N is equal to the number of bits of the R, G, or B digital color signal. In the present embodiment, elementary current sources CSj, j varying from 1 to N, are assembled in parallel between a node A1and a node A2. When the light-emitting diodes LED are assembled with a common anode, as shown in Figure 4, for each color, node A1is coupled, preferably connected, to the cathode of the light- emitting diode LED corresponding to the considered color, and node A2is coupled, preferably connected, to conductive pad P_Gnd coupled to the source of low reference potential Gnd. When the light-emitting diodes LED are assembled with a common cathode, node A1is coupled, preferably connected, to conductive pad P_Vcc coupled to the source of high reference potential Vcc and, for each color, node A2is coupled, preferably connected, to the anode of the light-emitting diode LED corresponding to the considered color.

[0111] Each elementary current source CSjis activated or deactivated by circuit 50 by means of a control signal Cj. As an example, control signal Cjis a binary signal corresponding to the bit of rank j of the R, G, or B digital color signal. Elementary current source CSjis off when signal Cjis in a first state, for example, the low state, and current sourceB22967PCT – IR00251    CSjis activated when signal Cjis in a second state, for example, the high state.

[0112] The larger the number of current sources CSjwhich are activated, the higher the intensity of current ICS. According to an embodiment, current source CS is capable of supplying a current ICS having an intensity at a level from among a plurality of constant levels and having its level depending on the number of general light-emitting diodes which are conductive. The currents supplied by the elementary current sources CSjof current source CS may be identical or different. According to an embodiment, each elementary current source CSjis capable of supplying a current of intensity I*2j-1. Current source CS is then adapted to supplying a current having an intensity ICS which may, according to control signals Cj, take any value k*I, with k varying from 0 to 2M- 1.

[0113] According to an embodiment, the control of light- emitting diodes LED is an analog control.

[0114] Figure 19 shows an embodiment of current source CS where the current source comprises a MOS transistor T assembled in series with a resistor Rs between nodes A1and A2, nodes A1and A2being defined as previously in relation with Figure 18. Current source CS further comprises a digital- to-analog converter DAC receiving the R, G, or B digital color signal and an operational amplifier OA having its inverting input (-) coupled, preferably connected, to the midpoint between resistor Rs and the MOS transistor and having its non-inverting input (+) receiving the analog signal delivered by digital-to-analog converter DAC. Transistor T is made more or less conductive according to the R, G, or B digital color signal transmitted to digital-to-analog converter DAC.B22967PCT – IR00251

[0115] Various embodiments and variants have been described. Those skilled in the art will understand that certain features of these various embodiments and variants may be combined, and other variants will occur to those skilled in the art. In particular, the PWM modulation may be internally generated in the control circuit 30 of display pixel 12i,jto avoid using signal Comito generate it. Other embodiments may also not use a PWM modulation but a linear driving of light-emitting diode LED. Other embodiments may also use other electro- optical components such as organic light-emitting diodes.

[0116] Finally, the practical implementation of the described embodiments and variations is within the abilities of those skilled in the art based on the functional indications given hereabove.

Claims

B22967PCT – IR00251    CLAIMS 1. Display pixel (12i,j) for a display screen (10), comprising at least one light-emitting device (LED), a driver circuit (40) for driving the light-emitting device (LED), the display pixel (12i,j) being configured to receive a first voltage (Vcc) and a first binary signal (Comi), the light-emitting device being powered with the first voltage (Vcc), the display pixel further comprising a supply circuit (60) configured to provide a power supply voltage (Vdd), inferior to the first voltage (Vcc), for the powering of the driver circuit (40), the supply circuit (60) comprising a first capacitor (C1) configured to be charged with a reference power supply voltage (Vdd_Ref) from the first binary signal (Comi), said supply circuit (60) further comprising a voltage follower circuit (OAmp) providing the power supply voltage (Vdd) at its output, the voltage follower circuit (OAmp) being supplied by the first voltage (Vcc), being coupled to the first capacitor (C1), and being configured to maintain the power supply voltage (Vdd) equal to the reference power supply voltage (Vdd_Ref).

2. Display pixel (12i,j) according to claim 1, comprising at least first, second, and third bonding electrically- conductive pads (P_Vcc, P_Gnd, P_Row), the first voltage (Vcc) being received between the first and second bonding electrically-conductive pads (P_Vcc, P_Gnd), the first binary signal (Comi) being received on the third bonding electrically-conductive pad (P_Row), the first binary signals alternating between a second voltage, lower than the first voltage (Vcc), and a third voltage (Gnd), lower than the second voltage, the driver circuit (40) being configured to drive the light-emitting device (LED) fromB22967PCT – IR00251    the first binary signal (Comi) received on the third bonding electrically-conductive pad (P_Row).

3. Display pixel (12i,j) according to claim 2, wherein the supply circuit (60) comprises a first branch coupling the third bonding electrically-conductive pad (P_Row) and the first capacitor (C1), the first branch comprising only one or more Schottky diodes, diodes, and / or transistors.

4. Display pixel (12i,j) according to any of claims 1 to 3, wherein the supply circuit (60) further comprises a second capacitor (C2), the voltage follower circuit (OAmp) being configured to charge the second capacitor (C2) with the power supply voltage (Vdd).

5. Display pixel (12i,j) according to claim 4, wherein the voltage follower circuit (OAmp) is supplied by the first voltage (Vcc) through a switch (SW) and wherein the supply circuit (60) further comprises a trigger circuit (62) configured to command the switch (SW).

6. Display pixel (12i,j) according to claim 5, wherein the trigger circuit (62) is configured to command the switch (SW) based on the first binary signal (Comi).

7. Display pixel (12i,j) according to claim 6, wherein the trigger circuit (62) is configured to close the switch (SW), during a given duration (D), after each falling edge and / or each rising edge of the first binary signal (Comi).

8. Display pixel (12i,j) according to claim 4 or 5, wherein the second capacitor (C2) is configured also to be charged by the first binary signal (Comi).

9. Display pixel (12i,j) according to claims 2 and 8, wherein the supply circuit (60) comprises a second branch coupling the third bonding electrically-conductive padB22967PCT – IR00251    (P_Row) and the second capacitor (C2), the second branch comprising only one or more Schottky diodes, diodes, and / or transistors.

10. Display pixel (12i,j) according to any of claims 4 to 9, wherein each of the first capacitor (C1) and the second capacitor (C2) comprises an electrode connected to the second bonding electrically-conductive pad (P_Gnd).

11. Display pixel (12i,j) according to any of claims 1 to 10, wherein the display pixel (12i,j) is intended to receive a second binary signal (Dataj), and wherein the first capacitor (C1) is configured to be charged with the reference power supply voltage (Vdd_Ref) from the first binary signal (Comi) and the second binary signal (Dataj).

12. Display pixel (12i,j) according to claims 2 and 11, comprising at least one fourth bonding electrically- conductive pads (P_Col), the second binary signal (Dataj) being received on the fourth bonding electrically- conductive pad (P_Col), the driver circuit (40) being configured to drive the light-emitting device (LED) from the first binary signal (Comi) received on the third bonding electrically-conductive pad (P_Row) and the second binary signal (Dataj) received on the fourth bonding electrically- conductive pad (P_Col), the second binary signal (Dataj) alternating between the second voltage and the third voltage (Gnd).

13. Display pixel (12i,j) according to claim 12, wherein the supply circuit (60) comprises a third branch coupling the fourth bonding electrically-conductive pad (P_Col) and the first capacitor (C1), the third branch comprising only one or more Schottky diodes, diodes, and / or transistors.B22967PCT – IR00251    14. Display pixel (12i,j) according to claims 4 and 11, wherein the second capacitor (C2) is configured also to be charged by the second binary signal (Dataj).

15. Display pixel (12i,j) according to claims 12 and 14, wherein the supply circuit (60) comprises a fourth branch coupling the fourth bonding electrically-conductive pad (P_Col) and the second capacitor (C2), the fourth branch comprising only one or more Schottky diodes, diodes, and / or transistors.

16. Display pixel (12i,j) according to any of claims 11 to 15, wherein the driver circuit (40) is configured to determine a digital signal (R, G, B) from values of the second binary signal (Dataj) received relatively to first pulses of the first binary signal (Comi) and to command the light-emitting device (LED) based on the digital signal.

17. Display pixel (12i,j) according to claim 16, wherein the driver circuit (40) is configured to control the light- emitting device (LED) by pulse-width modulation based on the digital signal (R, G, B).

18. Display pixel (12i,j) according to claim 17, wherein the driver circuit (40) is configured to turn on or turn off the light-emitting device (LED) at the rate of second pulses of the first binary signal (Comi) at the second voltage (Vdd) or at the third voltage (Gnd).

19. Display pixel (12i,j) according to claim 12 or 13, only comprising the first, second, third, and fourth bonding electrically-conductive pads (36).

20. Display pixel (12i,j) according to any of claims 11 to 19, wherein the first binary signal (Comi) is a first binaryB22967PCT – IR00251    voltage and wherein the second binary signal (Dataj) is a second binary voltage.

21. Display pixel (12i,j) according to any of claims 1 to 20, wherein the voltage follower circuit (OAmp) comprises an operational amplifier (OAmp) having a non-inverting input (+), an inverting input (-), and an output, the non- inverting input (+) of the operational amplifier (OAmp) being coupled to the first capacitor (C1), the output of the operational amplifier (OAmp) providing the power supply voltage (Vdd), and the inverting input (-) of the operational amplifier (OAmp) being connected to the output of the operational amplifier (OAmp).

22. Display screen (10) comprising an array of display pixels (12i,j) according to claim 12 or 13, the display screen further comprising circuits (22, 24) for delivering, for each display pixel, the first voltage (Vcc) between the first and second bonding electrically-conductive pads (P_Vcc, P_Gnd), the first binary signal (Comi) on the third bonding electrically-conductive pads (P_Row), and the second binary signal (Dataj) on the fourth bonding electrically-conductive pad (P_Col).

23. Method of controlling a display screen (10) comprising an array of display pixels (12i,j) according to claim 12 or 13, the method comprising the delivery, for each display pixel (12i,j), of the first voltage (Vcc) between the first and second bonding electrically-conductive pads (P_Vcc, P_Gnd), the delivery of the first binary signal (Comi) on the third bonding electrically-conductive pad (P_Row), and the delivery of the second binary signal (Dataj) on the fourth bonding electrically-conductive pad (P_Col).B22967PCT – IR00251    24. Method according to claim 23, comprising the delivery of the first binary signal (Comi) and of the second binary signal (Dataj) such that, in operation, the ratio of the average duration for which at least one of the first binary signal (Comi) and of the second binary signal (Dataj) is at the second voltage (Vdd) to the sum of the average duration for which the first binary signal (Comi) and the second binary signal (Dataj) are at the third voltage (Gnd) and of the average duration for which at least one of the first binary signal (Comi) and of the second binary signal (Dataj) is at the second voltage (Vdd) is greater than 75%.

25. Method according to claim 24, comprising the delivery of the first binary signal (Comi) and of the second binary signal (Dataj) such that, at any time in operation, at least one of the first binary signal (Comi) and of the second binary signal (Dataj) is at the second voltage (Vdd).

26. Method according to any of claims 23 to 24, wherein the reference power supply voltage (Vdd_Ref) is inferior to the second voltage (Gnd) by less than 10% and wherein the power supply voltage (Vdd) is inferior to the second voltage (Gnd) by less than 10%.

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