Memory system and operation method therefor, host-end apparatus and operation method therefor, and computer readable storage medium

Abstract

A memory system and an operation method therefor, a host-end apparatus and an operation method therefor, and a computer readable storage medium. The memory system comprises a memory device and a memory controller coupled to the memory device. The memory controller is configured to: receive a read command, wherein the read command instructs to read event log information generated during running by firmware, and the event log information comprises an index number and a parameter value of an event log; when firmware runs different functional modules, different event log elements are correspondingly generated, and the different event log elements correspond to different index numbers (S1001).

Description

Memory system and operation method thereof, host-side device and operation method thereof, and computer-readable storage medium Technical Field

[0001] The present disclosure relates to, but is not limited to, a memory system and an operating method thereof, a host-side device and an operating method thereof, and a computer-readable storage medium. Background Art

[0002] With the rapid development of data storage technology, more and more data storage systems, such as solid-state drives (SSDs), are appearing in electronic devices. SSDs, due to their fast read and write speeds, vibration resistance, low power consumption, quiet operation, low heat generation, and lightweight design, have found widespread application in military, automotive, industrial, medical, and aviation applications.

[0003] However, there are still many problems that need to be solved in the memory system in the related art.

[0004] Summary of the Invention

[0005] According to a first aspect of an embodiment of the present disclosure, a memory system is provided, the memory system including a memory device and a memory controller coupled to the memory device;

[0006] The memory controller is configured to:

[0007] A read command is received, wherein the read command instructs to read event log information generated during the operation of the firmware, wherein the event log information includes an index number and a parameter value of the event log; different event log elements are generated corresponding to different functional modules of the firmware operation, and different event log elements correspond to different index numbers.

[0008] In some embodiments, the firmware includes an event log information output program configured to record an index number and parameter value of an event log; and the memory controller is configured to:

[0009] When the firmware runs to the functional module, the output program of the event log information in the firmware is run, thereby generating event log information including an index number and a parameter value.

[0010] In some embodiments, the event log element corresponding to the index number in the event log information and the parameter name corresponding to the parameter value can be obtained based on the event log information and the code file; the code file includes a correspondence table of event log elements and index numbers, and a list of parameter names corresponding to each event log element.

[0011] In some implementations, the parameter name list includes a plurality of parameter names; the code file further includes: placeholder information corresponding to the parameter names;

[0012] The interval between two adjacent parameter values ​​can be obtained according to the placeholder information.

[0013] In some embodiments, the memory controller is configured to:

[0014] The event log information is temporarily stored in a buffer before receiving the read command.

[0015] In some embodiments, the memory controller is configured to:

[0016] The event log information temporarily stored in the buffer is transferred to the memory device.

[0017] In some implementations, the functional modules include: a garbage collection module, a normal power on / off module, an abnormal power on / off module, a wear leveling module, and a bad block management module.

[0018] In some embodiments, the memory system includes a memory card or a solid-state drive.

[0019] According to a second aspect of an embodiment of the present disclosure, a host-end device is provided, the host-end device including a compilation system; the compilation system including a compilation controller, the compilation controller being configured to:

[0020] receiving a scan command instructing to scan a project file, and generating an event log set by extracting keywords related to event logs from the project file, wherein the event log set includes a plurality of event log elements; different event log elements are generated corresponding to different function modules executed by the firmware;

[0021] Generate a code file, which includes a correspondence table between event log elements and index numbers, and a parameter name list corresponding to each event log element.

[0022] In some embodiments, the host device further includes a parsing system, the parsing system includes a parsing controller, and the parsing controller is configured to:

[0023] Receive event log information and the code file; the event log information includes an event log index number and a parameter value; different event log elements are generated corresponding to different function modules running in the firmware, and different event log elements correspond to different index numbers;

[0024] According to the event log information and the code file, an event log element corresponding to an index number in the event log information and a parameter name corresponding to a parameter value are obtained.

[0025] In some implementations, the parameter name list includes a plurality of parameter names; the code file further includes: placeholder information corresponding to the parameter names; and the parsing controller is configured to:

[0026] The interval between two adjacent parameter values ​​is obtained according to the placeholder information.

[0027] According to a third aspect of an embodiment of the present disclosure, a method for operating a memory system is provided, the method comprising:

[0028] A read command is received, wherein the read command instructs to read event log information generated during the operation of the firmware, wherein the event log information includes an index number and a parameter value of the event log; different event log elements are generated corresponding to different functional modules of the firmware operation, and different event log elements correspond to different index numbers.

[0029] In some embodiments, the firmware includes an event log information output program configured to record an event log index number and a parameter value; the method further includes:

[0030] When the firmware runs to the functional module, the output program of the event log information in the firmware is run, thereby generating event log information including an index number and a parameter value.

[0031] In some embodiments, the event log element corresponding to the index number in the event log information and the parameter name corresponding to the parameter value can be obtained based on the event log information and the code file; the code file includes a correspondence table of event log elements and index numbers, and a list of parameter names corresponding to each event log element.

[0032] In some implementations, the parameter name list includes a plurality of parameter names; the code file further includes: placeholder information corresponding to the parameter names;

[0033] The interval between two adjacent parameter values ​​can be obtained according to the placeholder information.

[0034] In some embodiments, the method further comprises:

[0035] Before receiving the read command, the event log information is temporarily stored in a buffer.

[0036] In some embodiments, the method further comprises:

[0037] The event log information temporarily stored in the buffer is transferred to the memory device.

[0038] According to a fourth aspect of an embodiment of the present disclosure, a method for operating a host-side device is provided, the method comprising:

[0039] receiving a scan command instructing to scan a project file, and generating an event log set by extracting keywords related to event logs from the project file, wherein the event log set includes a plurality of event log elements; different event log elements are generated corresponding to different function modules executed by the firmware;

[0040] A code file is generated, wherein the code file includes a correspondence table between event log elements and index numbers, and a parameter name list corresponding to each event log element.

[0041] In some embodiments, the method further comprises:

[0042] Receive event log information and the code file; the event log information includes an event log index number and a parameter value; different event log elements are generated corresponding to different function modules running in the firmware, and different event log elements correspond to different index numbers;

[0043] According to the event log information and the code file, an event log element corresponding to an index number in the event log information and a parameter name corresponding to a parameter value are obtained.

[0044] In some implementations, the parameter name list includes a plurality of parameter names; the code file further includes: placeholder information corresponding to the parameter names; the method further includes:

[0045] The interval between two adjacent parameter values ​​is obtained according to the placeholder information.

[0046] According to a fifth aspect of an embodiment of the present disclosure, a computer-readable storage medium is provided, on which a computer program is stored. When the computer program is executed by a processor, the operating method described in any one of the schemes in some implementation methods is performed. BRIEF DESCRIPTION OF THE DRAWINGS

[0047] FIG1 is a schematic diagram of an exemplary system having a memory system according to an embodiment of the present disclosure;

[0048] FIG2 a is a schematic diagram of an exemplary memory card having a memory system according to an embodiment of the present disclosure;

[0049] FIG2 b is a schematic diagram of an exemplary solid-state drive having a memory system according to an embodiment of the present disclosure;

[0050] FIG3 a is a schematic diagram showing the distribution of storage cells of a three-dimensional NAND memory according to an embodiment of the present disclosure;

[0051] FIG3 b is a schematic diagram of an exemplary memory device including peripheral circuits according to an embodiment of the present disclosure;

[0052] FIG4 is a cross-sectional schematic diagram of a memory array including memory strings according to an embodiment of the present disclosure;

[0053] FIG5 is a schematic diagram of an exemplary memory including a memory array and peripheral circuits according to an embodiment of the present disclosure;

[0054] FIG6 is a schematic diagram of the framework structure of a memory system according to an embodiment of the present disclosure;

[0055] FIG7 is a schematic diagram of an implementation flow of an operating method of a memory system according to an embodiment of the present disclosure;

[0056] FIG8 is a schematic diagram of a flowchart of an operating method of a host-side device according to an embodiment of the present disclosure;

[0057] FIG9 is a schematic diagram of a framework flow for obtaining the complete content of event log information according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0058] Exemplary embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. Although exemplary embodiments of the present disclosure are shown in the accompanying drawings, it should be understood that the present disclosure can be implemented in various forms and should not be limited by the specific embodiments described herein. Instead, these embodiments are provided to enable a more thorough understanding of the present disclosure and to fully convey the scope of the present disclosure to those skilled in the art.

[0059] In the following description, numerous specific details are provided to provide a more thorough understanding of the present disclosure. However, it will be apparent to those skilled in the art that the present disclosure can be practiced without one or more of these details. In other instances, certain technical features known in the art are not described to avoid confusion with the present disclosure; that is, all features of actual embodiments are not described herein, nor are well-known functions and structures described in detail.

[0060] In the drawings, the sizes of layers, regions, elements and their relative sizes may be exaggerated for clarity. Like reference numerals denote like elements throughout.

[0061] It should be understood that when an element or layer is referred to as being "on, adjacent to, connected to, or coupled to" another element or layer, it may be directly on, adjacent to, connected to, or coupled to the other element or layer, or there may be intervening elements or layers. In contrast, when an element is referred to as being "directly on, directly adjacent to, directly connected to, or directly coupled to" another element or layer, there may be no intervening elements or layers. It should be understood that although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers, and / or parts, these elements, components, regions, layers, and / or parts should not be limited by these terms. These terms are merely used to distinguish one element, component, region, layer, or part from another element, component, region, layer, or part. Therefore, without departing from the teachings of the present disclosure, the first element, component, region, layer, or part discussed below may be represented as a second element, component, region, layer, or part. However, when the second element, component, region, layer, or part is discussed, it does not necessarily mean that the first element, component, region, layer, or part exists in the present disclosure.

[0062] Spatially relative terms such as "under," "beneath," "below," "under," "above," "above," etc., may be used herein for convenience of description to describe the relationship of an element or feature shown in the figures to other elements or features. It should be understood that in addition to the orientations shown in the figures, the spatially relative terms are intended to include different orientations of the device in use and operation. For example, if the device in the drawings is turned over, then the elements or features described as "under the other elements" or "under it" or "under it" will be oriented as "on" the other elements or features. Therefore, the exemplary terms "under" and "under" can include both the upper and lower orientations. The device can be oriented otherwise (rotated 90 degrees or other orientations) and the spatial descriptors used herein are interpreted accordingly.

[0063] The purpose of the terms used herein is only to describe specific embodiments and is not intended to limit the present disclosure. When used herein, the singular forms "a", "an", and "the" are intended to include the plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "comprising" and / or "comprising", when used in this specification, determine the presence of the features, integers, steps, operations, elements and / or parts, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, parts and / or groups. When used herein, the term "and / or" includes any and all combinations of the relevant listed items.

[0064] In order to enable a more detailed understanding of the features and technical contents of the embodiments of the present disclosure, the implementation of the embodiments of the present disclosure is described in detail below with reference to the accompanying drawings. The accompanying drawings are for reference only and are not intended to limit the embodiments of the present disclosure.

[0065] FIG1 shows a block diagram of an exemplary system 100 with memory according to some aspects of the present disclosure. System 100 can be a mobile phone, a desktop computer, a laptop computer, a tablet computer, a vehicle computer, a game console, a printer, a positioning device, a wearable electronic device, a smart sensor, a virtual reality (VR) device, an augmented reality device, or any other suitable electronic device having storage therein. As shown in FIG1 , system 100 can include a host-side device 108 and a memory system 102, and memory system 102 has one or more memory devices 104 and a memory controller 106. Host-side device 108 can be a processor (e.g., a central processing unit) or a system on chip (e.g., an application processor) of an electronic device. Host-side device 108 can be configured to send data to or receive data from memory device 104.

[0066] According to some embodiments, the memory controller 106 is coupled to the memory device 104 and the host-side device 108 and is configured to control the memory device 104. The memory controller 106 can manage data stored in the memory device 104 and communicate with the host-side device 108. In some embodiments, the memory controller 106 is designed to operate in a low duty cycle environment, such as a secure digital card, a compact flash card, a universal serial bus flash drive, or other media used in electronic devices such as personal computers, digital cameras, mobile phones, etc. In some embodiments, the memory controller 106 is designed to operate in a high duty cycle environment, such as an SSD or an embedded multimedia card used as data storage for mobile devices such as smartphones, tablet computers, laptop computers, etc., as well as enterprise storage arrays.

[0067] The memory controller 106 can be configured to control operations of the memory device 104, such as read, erase, and program operations. The memory controller 106 can also be configured to manage various functions related to data stored or to be stored in the memory device 104, including, but not limited to, bad block management, garbage collection, logical-to-physical address translation, wear leveling, and the like. In some embodiments, the memory controller 106 is also configured to process error correction codes for data read from or written to the memory device 104. The memory controller 106 can also perform any other suitable functions, such as formatting the memory device 104. The memory controller 106 can communicate with an external device (e.g., the host device 108) according to a specific communication protocol. For example, the memory controller 106 can communicate with the external device using at least one of various interface protocols, such as the USB protocol, the MMC protocol, the Peripheral Component Interconnect protocol, the Peripheral Component Interconnect High Speed ​​protocol, the Advanced Technology Attachment protocol, the Serial Advanced Technology Attachment protocol, the Parallel Advanced Technology Attachment protocol, the Minicomputer Mini Interface protocol, the Enhanced MiniDisk Interface protocol, the Integrated Drive Electronics protocol, a firmware protocol, and the like.

[0068] The memory controller 106 and one or more memory devices 104 can be integrated into various types of storage devices, for example, included in the same package (e.g., a Universal Flash Storage (UFS) package or an embedded multimedia card package). That is, the memory system 102 can be implemented and packaged into different types of terminal electronic products. In one example, as shown in FIG2a, the memory controller 106 and a single memory device 104 can be integrated into a memory card 202. The memory card 202 can include a compact flash card, a smart media card, a memory stick, a multimedia card, a secure digital card, a UFS, etc. The memory card 202 can also include a memory card connector 204 that couples the memory card 202 to a host-side device (e.g., the host-side device 108 in FIG1 ). In another example, as shown in FIG2b, the memory controller 106 and multiple memory devices 104 can be integrated into an SSD 206. The SSD 206 can also include an SSD connector 208 that couples the SSD 206 to a host-side device (e.g., the host-side device 108 in FIG1 ). In some implementations, the storage capacity and / or operating speed of SSD 206 is greater than the storage capacity and / or operating speed of memory card 202 .

[0069] Figure 3a illustrates a schematic structural diagram of a memory array of a three-dimensional NAND memory. As shown in Figure 3a, the memory array of the three-dimensional NAND memory comprises several parallel, staggered rows of memory cells parallel to gate isolation structures. Every four rows of memory cells are separated by gate isolation structures and upper select gate isolation structures, and each memory cell row includes multiple memory cells. The gate isolation structures may include a first gate isolation structure and a second gate isolation structure. The first gate isolation structure divides the memory array into multiple memory blocks (blocks). The multiple second gate isolation structures may divide the memory blocks into multiple finger storage areas (finger). An upper select gate isolation structure disposed between each finger storage area may divide the finger storage area into two parts, thereby dividing the finger storage area into two memory slices. The memory block shown in Figure 3a includes six memory slices. In practical applications, the number of memory slices in a memory block is not limited to this number. The memory cells in a memory slice coupled to a word line may be associated with a memory page (page), where a memory page is a physical page.

[0070] It should be noted that the number of memory cell rows between the gate isolation structure and the upper select gate isolation structure shown in FIG3a is merely illustrative and does not limit the number of memory cell rows contained in a finger storage area of ​​the 3D NAND memory disclosed herein. In actual applications, the number of memory cell rows contained in a finger storage area can be adjusted based on actual conditions, such as 2, 4, 8, or 16.

[0071] FIG3 b shows a schematic circuit diagram of an exemplary memory device 300 including peripheral circuitry according to aspects of the present disclosure. Memory device 300 may be an example of memory device 104 in FIG1 . Memory device 300 may include a memory array 301 and peripheral circuitry 302 coupled to memory array 301. For illustration, memory array 301 is described as a three-dimensional NAND-type memory array, wherein memory cells 306 are NAND memory cells, and memory cells 306 are provided in the form of an array of memory strings 308, each memory string 308 extending vertically above a substrate (not shown). In some embodiments, each memory string 308 includes a plurality of memory cells 306 coupled in series and stacked vertically. Each memory cell 306 may hold a continuous analog value, such as a voltage or charge, that depends on the number of electrons trapped within the region of the memory cell 306. Each memory cell 306 may be a floating-gate type memory cell including a floating-gate transistor, or a charge-trapping type memory cell including a charge-trapping transistor.

[0072] In some embodiments, each memory cell 306 is a single-level cell (SLC) that has two possible memory states and can therefore store one bit of data. For example, the first memory state "0" can correspond to a first voltage range, and the second memory state "1" can correspond to a second voltage range. In some embodiments, each memory cell 306 is a multi-level cell (MLC) capable of storing more than a single bit of data in more than four memory states. For example, an MLC can store two bits per cell, three bits per cell (also known as a triple-level cell (TLC)), or four bits per cell (also known as a quad-level cell (QLC)). Each MLC can be programmed to assume a range of possible nominal storage values. In one example, if each MLC stores two bits of data, the MLC can be programmed to assume one of three possible programming levels from an erased state by writing one of the three possible nominal storage values ​​to the cell. A fourth nominal storage value can be used for the erased state.

[0073] As shown in FIG3b , each memory string 308 may include a bottom selected transistor (BST) 310 at its source terminal and a top selected transistor (TST) 312 at its drain terminal. BST 310 and TST 312 may be configured to activate the selected memory string 308 during read and program operations. In some embodiments, the sources of the memory strings 308 in the same memory block 304 are coupled via the same source line (SL) 314 (e.g., a common SL). In other words, according to some embodiments, all memory strings 308 in the same memory block 304 have an array common source (ACS). According to some embodiments, the TST 312 of each memory string 308 is coupled to a corresponding bit line (BL) 316, and data can be read from or written to the bit line 316 via an output bus (not shown). In some embodiments, each memory string 308 is configured to be selected or deselected by applying a select voltage (e.g., higher than the threshold voltage of the transistor having TST 312) or a deselect voltage (e.g., 0 V) ​​to the corresponding TST 312 via one or more TSLs (Top selected lines) 313 and / or by applying a select voltage (e.g., higher than the threshold voltage of the transistor having BST 310) or a deselect voltage (e.g., 0 V) ​​to the corresponding BST 310 via one or more BSLs (Bottom Selected lines) 315.

[0074] As shown in FIG3 b , a memory string 308 can be organized into a plurality of memory blocks 304, each of which can have a common source line 314 (e.g., coupled to ground). In some embodiments, each memory block 304 is a basic data unit for erase operations, i.e., all memory cells 306 on the same memory block 304 are erased simultaneously. To erase the memory cells 306 in a selected memory block, the source lines 314 coupled to the selected memory block and unselected memory blocks in the same plane as the selected memory block can be biased with an erase voltage (Vers) (e.g., a high positive voltage (e.g., 20V or higher)). It should be understood that in some examples, erase operations can be performed at the half-block level, at the quarter-block level, or at any suitable number of memory blocks or any suitable fraction of memory blocks. Memory cells 306 of adjacent memory strings 308 can be coupled by word lines 318, which select which row of memory cells 306 is affected by read and program operations. In some embodiments, each word line 318 is coupled to a memory page 320 of memory cells 306. The size of a memory page 320 in bits can be related to the number of memory strings 308 coupled by the word line 318 in a memory block 304. Each word line 318 can include multiple control gates (gate electrodes) at each memory cell 306 in the corresponding memory page 320 and a gate line coupled to the control gates. Referring to FIG. 3 a above, a memory page 320 includes multiple memory cells 306, each of which is isolated by an upper select gate isolation structure and a gate isolation structure. The multiple memory cells between the upper select gate isolation structure and the gate isolation structure are arranged into multiple memory cell rows, each of which is parallel to the gate isolation structure and the upper select gate isolation structure. The memory cells in a memory slice that share the same word line form a programmable (read / write) page.

[0075] FIG4 illustrates a cross-sectional schematic diagram of an exemplary memory array 301 including memory strings 308 according to aspects of the present disclosure. As shown in FIG4 , memory strings 308 may include a stacked structure 410 comprising a plurality of gate layers 411 and a plurality of insulating layers 412 alternately stacked in sequence, and a memory string 308 vertically extending through the gate layers 411 and insulating layers 412. The gate layers 411 and insulating layers 412 may be alternately stacked, with adjacent gate layers 411 separated by an insulating layer 412. The number of memory cells included in the memory array 301 is primarily related to the number of pairs of gate layers 411 and insulating layers 412 in the stacked structure 410.

[0076] The constituent material of the gate layer 411 may include a conductive material. Conductive materials include, but are not limited to, tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), polysilicon, doped silicon, silicide, or any combination thereof. In some embodiments, each gate layer 411 includes a metal layer, for example, a tungsten layer. In some embodiments, each gate layer 411 includes a doped polysilicon layer. Each gate layer 411 may include a control gate surrounding a memory cell. The gate layer 411 at the top of the stacked structure 410 may extend laterally as an upper selection gate line, the gate layer 411 at the bottom of the stacked structure 410 may extend laterally as a lower selection gate line, and the gate layer 411 extending laterally between the upper selection gate line and the lower selection gate line may serve as a word line layer.

[0077] In some embodiments, the stacked structure 410 may be disposed on a substrate 401. The substrate 401 may include silicon (e.g., single crystal silicon), silicon germanium (SiGe), gallium arsenide (GaAs), germanium (Ge), silicon on insulator (SOI), germanium on insulator (GOI), or any other suitable material.

[0078] In some embodiments, memory string 308 includes a channel structure extending vertically through stacked structure 410. In some embodiments, the channel structure includes a channel hole filled with one or more semiconductor materials (e.g., serving as a semiconductor channel) and one or more dielectric materials (e.g., serving as a memory film). In some embodiments, the semiconductor channel comprises silicon, such as polycrystalline silicon. In some embodiments, the memory film is a composite dielectric layer comprising a tunneling layer, a storage layer (also referred to as a "charge trapping / storage layer"), and a barrier layer. The channel structure may have a cylindrical shape (e.g., a pillar). In some embodiments, the semiconductor channel, tunneling layer, storage layer, and barrier layer are arranged radially in this order from the center of the pillar toward the outer surface of the pillar. The tunneling layer may comprise silicon oxide, silicon oxynitride, or any combination thereof. The storage layer may comprise silicon nitride, silicon oxynitride, or any combination thereof. The barrier layer may comprise silicon oxide, silicon oxynitride, a high dielectric constant (high-k) dielectric, or any combination thereof. In one example, the memory film may comprise a composite layer of silicon oxide / silicon oxynitride / silicon oxide (ONO).

[0079] Referring back to FIG3 b , the peripheral circuitry 302 can be coupled to the memory array 301 via the bit lines 316 , word lines 318 , source lines 314 , BSLs 315 , and TSLs 313 . The peripheral circuitry 302 can include any suitable analog, digital, and mixed-signal circuitry for facilitating the operation of the memory array 301 by applying and sensing voltage and / or current signals to and from each target memory cell 306 via the bit lines 316 , word lines 318 , source lines 314 , BSLs 315 , and TSLs 313 . The peripheral circuitry 302 can include various types of peripheral circuitry formed using metal-oxide-semiconductor technology. For example, FIG5 illustrates some exemplary peripheral circuitry, where the peripheral circuitry 302 includes a page buffer / sense amplifier 504 , a column decoder / bit line driver 506 , a row decoder / word line driver 508 , a voltage generator 510 , a control logic unit 512 , a register 514 , an interface 516 , and a data bus 518 . It should be understood that in some examples, additional peripheral circuits not shown in FIG. 5 may also be included.

[0080] The page buffer / sense amplifier 504 can be configured to read data from the memory array 301 and program (write) data to the memory array 301 according to control signals from the control logic unit 512. In one example, the page buffer / sense amplifier 504 can store a page of program data (write data) to be programmed into one page 320 of the memory array 301. In another example, the page buffer / sense amplifier 504 can perform a program verification operation to ensure that the data has been correctly programmed into the memory cell 306 coupled to the selected word line 318. In yet another example, the page buffer / sense amplifier 504 can also sense a low-power signal from the bit line 316 representing a data bit stored in the memory cell 306 and amplify the small voltage swing to a recognizable logic level during a read operation. The column decoder / bit line driver 506 can be configured to be controlled by the control logic unit 512 and select one or more memory strings 308 by applying a bit line voltage generated by the voltage generator 510.

[0081] The row decoder / wordline driver 508 can be configured to be controlled by the control logic unit 512 and select / deselect memory blocks 304 of the memory array 301 and select / deselect word lines 318 of the memory blocks 304. The row decoder / wordline driver 508 can also be configured to drive the word lines 318 using word line voltages generated from the voltage generator 510. In some embodiments, the row decoder / wordline driver 508 can also select / deselect and drive the BSL 315 and TSL 313. As described in detail below, the row decoder / wordline driver 508 is configured to perform a programming operation on the memory cells 306 coupled to the selected word line(s) 318. The voltage generator 510 can be configured to be controlled by the control logic unit 512 and generate word line voltages (e.g., read voltage, program voltage, pass voltage, local voltage, verify voltage, etc.), bit line voltages, and source line voltages to be supplied to the memory array 301.

[0082] The control logic unit 512 can be coupled to each peripheral circuit described above and is configured to control the operation of each peripheral circuit. The register 514 can be coupled to the control logic unit 512 and include a status register, a command register, and an address register for storing status information, command operation code (OP code), and command address for controlling the operation of each peripheral circuit. The interface 516 can be coupled to the control logic unit 512 and act as a control buffer to buffer control commands received from a host-side device (not shown) and relay them to the control logic unit 512, as well as buffer status information received from the control logic unit 512 and relay them to the host-side device. The interface 516 can also be coupled to the column decoder / bit line driver 506 via the data bus 518 and act as a data I / O interface and data buffer to buffer data and relay it to the memory array 301 or relay or buffer data from the memory array 301.

[0083] Figure 6 shows a block diagram of a memory system 601. Memory system 601 includes a memory controller 602 and a memory device 603. Memory controller 602 is used to control memory device 603 to perform read and write operations. Memory controller 602 and memory device 603 can be coupled in any suitable manner. Memory controller 602 includes a control unit (CPU) 608, a buffer 609, an error correction module 606, a host I / F 605, a memory I / F 607, a wear leveling module 611, and a garbage collection module 612. In the disclosed embodiment, memory device 603 may be a semiconductor memory for storing non-volatile data, such as a NAND memory. Memory system 601 is connected to a host 604. Host I / F 605 outputs commands and valid data (write data) received from host 604 to an internal bus 610 and sends valid data (read data) read from memory device 603 and responses from control unit 608 to host 604.

[0084] The memory I / F 607 controls the writing of data to the memory device 603 and the reading of data from the memory device 603 based on instructions from the control unit 608. The control unit 608, for example, is a central processing unit (CPU) or a microprocessor (MPU), which controls the memory system 601 as a whole. The control unit 608 receives commands from the host 604 via the host I / F 605, and performs control based on these commands. For example, the control unit 608 instructs the memory I / F 607 to write data to the memory device 603 based on a command from the host 604. Furthermore, the control unit 608 instructs the memory I / F 607 to read data from the memory device 603 based on a command from the host 604.

[0085] The buffer 609 temporarily stores data received from the host 604 before storing it in the memory device 603 , and temporarily stores data read from the storage device 603 before sending it to the host 604 .

[0086] Error correction module 606 is the data encoding and decoding unit. Because flash memory storage inherently has a bit error rate, error checking and correction (ECC) is added to the original data during data write operations to ensure data accuracy. This is an encoding process. When reading data, error detection and correction are also required through decoding. If the number of erroneous bits exceeds the ECC error correction capability, the data will be uploaded to the host as "uncorrectable." The ECC encoding and decoding process is performed by error correction module 606.

[0087] Since flash memory must be erased before writing and cannot be overwritten, when users update data, they can only find another space to write new data. As a result, the data in the original space becomes outdated and becomes garbage. Garbage collection is required to free up new write space. The garbage collection module 612 can be used to move valid data from several flash memory blocks, write them to a new flash memory block, and then erase these previous flash memory blocks to obtain available flash memory blocks.

[0088] Flash memory has a lifespan, meaning its blocks have a limited number of erase and write cycles. If a block exceeds a certain number of erase and write cycles, it becomes less reliable and may even become unusable. Wear leveling module 611 prevents some blocks from being frequently erased, maintaining a relatively balanced erase and write cycle across each block, thereby extending the overall lifespan of the memory chip.

[0089] Operations of the memory system (eg, a write data operation, a read data operation, an erase data operation, etc.) may be implemented by running firmware stored in the memory system.

[0090] The memory device in the embodiments of the present disclosure includes but is not limited to a three-dimensional NAND memory. For ease of understanding, the three-dimensional NAND memory is used as an example for description.

[0091] During the operation of the firmware, it is inevitable that firmware faults (called bugs in English) will occur. Generally, the faults can be located through the event log information generated during the operation of the firmware. The event log information is generally stored in a memory device in the memory system. When fault location is required, the event log information stored in the memory device will be read out. The storage space used to store event log information in the memory device is generally limited. The commonly used method is to directly store the American Standard Code for Information Interchange (ASCII) corresponding to the event log information generated during the operation of the firmware, or to compress and store the event log information using a suitable compression algorithm. However, these two methods still require a large storage space in the memory device when storing the event log information. With the continuous improvement of the requirements for three-dimensional NAND memory, how to store more effective event log information in a limited storage space and save the capacity of the memory device has become an urgent problem to be solved.

[0092] In view of one or more of the above problems, an embodiment of the present disclosure provides an operating method of a memory system, as shown in FIG7 , the method including:

[0093] Step S1001: Receive a read command, wherein the read command indicates to read the event log information generated during the firmware operation, wherein the event log information includes the index number and parameter value of the event log; different function modules of the firmware operation generate different event log elements, and different event log elements correspond to different index numbers.

[0094] Here, firmware is a program written into an erasable programmable read-only memory or an electrically erasable programmable read-only memory. It refers to the device "driver" stored inside the memory system. Through firmware, the operating system can implement specific operating actions according to standard device drivers. Firmware is the software that performs the most basic and lowest-level work of a system.

[0095] In some specific examples, the firmware is stored in a read-only memory in a memory controller of the memory system or in a memory device.

[0096] Firmware inevitably encounters bugs during operation, generating various event logs. These logs record key information about the firmware's operation, allowing for efficient bug location and supporting system recovery. The types of event logs generated by the firmware vary depending on the functional module of the program.

[0097] In some specific examples, the functional modules include but are not limited to a garbage collection (GC) module, a normal power on / off module, an abnormal power on / off module, a wear leveling (WL) module, and a bad block management module.

[0098] In some specific examples, different event log elements are generated when the firmware runs into different functional modules, and different event log elements need to record different parameters. For example, when the firmware runs into the garbage collection module, the corresponding event log element will record information such as the identification number of the current source storage block, the type of the current source storage block, the identification number of the target storage block, and the type of the target storage block.

[0099] Here, different event log elements correspond to different index numbers, that is, each index number corresponds to a unique event log element, each event log element also corresponds to only one unique index number, and different parameters need to be recorded in different event log elements. It is understandable that in the embodiment of the present disclosure, different event log elements are numbered, and different event log elements correspond to different index numbers. When recording event log information in the memory system, only the index number and parameter value are recorded. This greatly reduces the storage space occupied by each event log information, thereby saving space for storing event log information in the memory device, so that more effective event log information can be stored in the limited storage space.

[0100] The following will specifically introduce how to implement event log information stored in the memory system, including index numbers and parameter values.

[0101] In some embodiments, the firmware includes an event log information output program, and the event log information output program is configured to record an index number and a parameter value of an event log.

[0102] In some embodiments, the method further comprises:

[0103] When the firmware runs to the functional module, the output program of the event log information in the firmware is run, thereby generating event log information including an index number and a parameter value.

[0104] It can be understood that the recording of event log information is achieved by running the program in the firmware. In the embodiment of the present disclosure, the output program of the event log information in the firmware is set accordingly, so that when the firmware runs to the functional module, it can output event log information including the index number and parameter value according to the setting.

[0105] In the embodiment of the present disclosure, the event log information stored in the memory system only includes an index number and a parameter value, but the specific content of the event log information cannot be obtained only through the index number and the parameter value. The following will specifically introduce how to obtain the complete content of the event log information.

[0106] In some embodiments, the event log element corresponding to the index number in the event log information and the parameter name corresponding to the parameter value can be obtained based on the event log information and the code file; the code file includes a correspondence table between the event log element and the index number, and a parameter name list corresponding to each event log element. Here, the code file includes but is not limited to a dat file, and the code file stores the correspondence between the index number and the event log element, and also a parameter name list corresponding to each event log element. By combining the index number in the event log information in the memory system with the code file, the event log element corresponding to the index number in the memory system can be obtained, and then the parameter name list corresponding to a certain index number in the memory system can be obtained through the parameter name list corresponding to each event log element in the code file, thereby obtaining the parameter name corresponding to each parameter value in an event log information recorded in the memory system, and then obtaining the complete content of the event log information in the memory system.

[0107] It can be understood that in the embodiment of the present disclosure, the event log information in the memory system only includes the index number and parameter value. The event log information in the memory system needs to be combined with the content in the code file and parsed to obtain the complete content of the event log information. This makes it possible to encrypt the event log information, thereby improving the security of the information.

[0108] In some embodiments, the method further comprises:

[0109] Before receiving the read command, the event log information is temporarily stored in a buffer.

[0110] In some embodiments, the method further comprises:

[0111] The event log information temporarily stored in the buffer is transferred to the memory device.

[0112] Here, the buffer may be a buffer in a memory controller. Event log information generated during firmware execution is temporarily stored in the buffer in the memory controller. When the amount of event log information stored in the buffer exceeds a preset value, the event log information in the buffer is transferred to the memory device. The preset value may be set based on the size of the buffer's storage space.

[0113] Here, a read command is received, and the read command instructs to read the event log information generated during the operation of the firmware. It can be understood that what is generally read here is the event log information in the memory device, but when the read command is received, the data size of the event log information in the cache may not have reached the preset value, that is, some event log information may still exist in the cache. Therefore, the read command here can also be to read the event log information in the cache in the memory controller.

[0114] It can be understood that the size of the storage space occupied by each event log information in the embodiment of the present disclosure is reduced, and the event log information temporarily stored in the cache in the memory controller is only transferred to the memory device when the data size is greater than a preset value. In this way, more event log information can be stored in the cache and then transferred to the memory device. When recording the same event log information, the solution provided in the embodiment of the present disclosure can greatly reduce the number of times the event log information is written to the memory device, thereby saving the read and write resources of the CPU and the memory device.

[0115] In some embodiments, the parameter name list includes a plurality of parameter names; the code file further includes: placeholder information corresponding to the parameter names;

[0116] The interval between two adjacent parameter values ​​can be obtained according to the placeholder information.

[0117] It can be understood that no other symbols need to be set between two adjacent parameter values ​​in the event log information stored in the memory system for division. In the embodiment of the present disclosure, the code file may also include placeholder information corresponding to the parameter name. The purpose of dividing the two adjacent parameter values ​​is achieved by using the placeholder information corresponding to each parameter name. This further reduces the storage space occupied by each event log information in the memory system.

[0118] The following is an exemplary description of the specific forms of the code file, the event log information in the memory system, and the parsed event log information.

[0119] For example, one of the information in the code file is: (00cf0212 "(%d) cpu%d adm cq, sq len: %x, cp len: %x"), where 00cf0212 is the index number, and "(%d) cpu%d adm cq, sq len: %x, cp len: %x" is an event log element; cpu, sq len, and cp len are parameter names, respectively, and together constitute a parameter list. If the parameter name is not set before the first %d, the system defaults to the first parameter value corresponding to the system time; the first %d can correspond to the system time placeholder, the second %d can correspond to the CPU ID placeholder, the first %x corresponds to the first parameter sq len placeholder, and the second %x corresponds to the second parameter cp len placeholder.

[0120] One of the event log information stored in the memory system is: 00cf0212005912f300000e000e000c000c, where 00cf0212 is the index number. The index number is followed by four parameter values, namely 005912f3, 00, 000e000e, and 000c000c, which correspond to the system timestamp, CPU ID, first parameter, and second parameter, respectively. Here, the placeholder of each parameter value can be used to distinguish the interval between two adjacent parameter values.

[0121] By combining the coded file with the event log information in the memory system, the complete content of the event log information obtained after parsing is: CPU0adm cp, sq len: e00e, cp len: c00c.

[0122] An embodiment of the present disclosure provides a method for operating a memory system, the method comprising: receiving a read command, the read command instructing to read event log information generated during firmware execution, the event log information including an event log index number and parameter values; and generating different event log elements corresponding to different functional modules executed by the firmware, each event log element corresponding to a different index number. In the embodiment of the present disclosure, the event log information read from the memory system only includes the event log index number and parameter value, thereby significantly reducing the amount of data in each event log message, thereby reducing the storage resources required to store the event log information and enabling more valid event log messages to be stored in the available storage space.

[0123] The present disclosure provides an operating method for a host-side device, as shown in FIG8 , wherein the method includes:

[0124] Step S2001: receiving a scan command, the scan command instructing to scan a project file, and generating an event log set by extracting keywords related to event logs from the project file, the event log set including a plurality of event log elements; different event log elements are generated corresponding to different function modules running in the firmware;

[0125] Step S2002: Generate a code file, which includes a correspondence table between event log elements and index numbers, and a parameter name list corresponding to each event log element.

[0126] In some specific examples, the host device includes a compilation system; the compilation system includes a compilation controller, and the execution subject in the above embodiment can be the compilation controller, that is, the compilation controller receives a scan command, generates an event log set, and generates a code file.

[0127] It is understandable that a project file includes a large amount of information. By extracting keywords related to event log information, an event log set including multiple event log elements can be obtained more efficiently.

[0128] In some embodiments, the method further comprises:

[0129] Receive event log information and the code file; the event log information includes an event log index number and a parameter value; different event log elements are generated corresponding to different function modules running in the firmware, and different event log elements correspond to different index numbers;

[0130] According to the event log information and the code file, an event log element corresponding to an index number in the event log information and a parameter name corresponding to a parameter value are obtained.

[0131] In some specific examples, the host-end device also includes a parsing system, and the parsing system includes a parsing controller. The execution subject in the above embodiment can be the parsing controller, that is, the parsing controller receives event log information and code files, and obtains the event log element corresponding to the index number in the event log information and the parameter name corresponding to the parameter value.

[0132] In some embodiments, the parameter name list includes a plurality of parameter names; the code file further includes: placeholder information corresponding to the parameter names; the method further includes:

[0133] The interval between two adjacent parameter values ​​is obtained according to the placeholder information.

[0134] The present disclosure provides an operating method for a host-side device, the method comprising: receiving a scan command, the scan command instructing to scan a project file, and generating an event log set by extracting keywords related to event logs from the project file, the event log set including multiple event log elements; executing different function modules of the firmware to generate different event log elements; and generating a code file, the code file including a correspondence table between event log elements and index numbers, and a parameter name list corresponding to each event log element. In the present disclosure, the event log set is generated by scanning the project file, and then the code file is generated. Since the code file includes the correspondence table between event log elements and index numbers and the parameter name list corresponding to each event log element, it can be combined with event log information in a memory system to obtain the complete content of the event log information through parsing. The code file itself occupies less memory, thereby saving memory occupied by the event log information while being able to obtain the complete event log information. In addition, the event log information in the memory system needs to be combined with the code file in the host-side device to obtain the complete content of the event log information, so that the event log information can be encrypted, thereby improving the security of the information.

[0135] Figure 9 is a schematic diagram of a framework process for obtaining the complete content of event log information according to an embodiment of the present disclosure. As shown in Figure 9, the process for obtaining the complete content of event log information provided by the embodiment of the present disclosure includes three stages: a compilation stage, an event log information acquisition stage, and a parsing stage. During the compilation stage, the compilation controller of the compilation system first receives a scan command and scans the project file, thereby generating a code file in DAT format, which includes an index number and a parameter list. During the event log information acquisition stage, the host sends a command to read the event log information to the memory system. The memory controller in the memory system receives the command and transmits it to the memory device via firmware. The firmware obtains the event log information from the memory device, and the host obtains the event log information via the firmware. The event log information obtained by the host includes an index number and parameter values. During the parsing stage, the parsing controller of the parsing system obtains the code file and the event log information read from the memory device. The parsing tool parses the code file and the event log information read from the memory device, thereby obtaining the complete content of the event log information in the parsing tool.

[0136] Based on the above-mentioned operating method of the memory system, an embodiment of the present disclosure further provides a memory system, the memory system including a memory device and a memory controller coupled to the memory device;

[0137] The memory controller is configured to:

[0138] A read command is received, wherein the read command instructs to read event log information generated during the operation of the firmware, wherein the event log information includes an index number and a parameter value of the event log; different event log elements are generated corresponding to different functional modules of the firmware operation, and different event log elements correspond to different index numbers.

[0139] In some embodiments, the firmware includes an event log information output program configured to record an index number and a parameter value of an event log; and the memory controller is configured to:

[0140] When the firmware runs to the functional module, the output program of the event log information in the firmware is run, thereby generating event log information including an index number and a parameter value.

[0141] In some embodiments, the event log element corresponding to the index number in the event log information and the parameter name corresponding to the parameter value can be obtained based on the event log information and the code file; the code file includes a correspondence table of event log elements and index numbers, and a list of parameter names corresponding to each event log element.

[0142] In some embodiments, the parameter name list includes a plurality of parameter names; the code file further includes: placeholder information corresponding to the parameter names;

[0143] The interval between two adjacent parameter values ​​can be obtained according to the placeholder information.

[0144] In some embodiments, the memory controller is configured to:

[0145] The event log information is temporarily stored in a buffer before receiving the read command.

[0146] In some embodiments, the memory controller is configured to:

[0147] The event log information temporarily stored in the buffer is transferred to the memory device.

[0148] In some embodiments, the functional modules include: a garbage collection module, a normal power on and off module, an abnormal power on and off module, a wear leveling module, and a bad block management module.

[0149] In some embodiments, the memory system includes a memory card or a solid-state drive.

[0150] Here, the specific structure and composition of the memory system can refer to the detailed introduction of Figures 1, 2a, 2b, 3a, 3b, 4, 5, and 6, and other details about the memory system are similar to those in the operating method of the aforementioned memory system. For the sake of brevity, they will not be repeated here.

[0151] Based on the above-mentioned operating method of the host-side device, an embodiment of the present disclosure further provides a host-side device, wherein the host-side device includes a compilation system; the compilation system includes a compilation controller, and the compilation controller is configured to:

[0152] receiving a scan command instructing to scan a project file, and generating an event log set by extracting keywords related to event logs from the project file, wherein the event log set includes a plurality of event log elements; different event log elements are generated corresponding to different function modules executed by the firmware;

[0153] A code file is generated, wherein the code file includes a correspondence table between event log elements and index numbers, and a parameter name list corresponding to each event log element.

[0154] In some embodiments, the host device further includes a parsing system, the parsing system includes a parsing controller, and the parsing controller is configured to:

[0155] Receive event log information and the code file; the event log information includes an event log index number and a parameter value; different event log elements are generated corresponding to different function modules running in the firmware, and different event log elements correspond to different index numbers;

[0156] According to the event log information and the code file, an event log element corresponding to an index number in the event log information and a parameter name corresponding to a parameter value are obtained.

[0157] In some embodiments, the parameter name list includes multiple parameter names; the code file further includes: placeholder information corresponding to the parameter names; the parsing controller is configured to:

[0158] The interval between two adjacent parameter values ​​is obtained according to the placeholder information.

[0159] Here, the specific structure and composition of the host-side device can refer to the detailed introduction of Figure 1 above, and other details about the host-side device are similar to those in the aforementioned operating method of the host-side device. For the sake of brevity, they will not be repeated here.

[0160] Based on the operating method of the above-mentioned memory system and the operating method of the host-side device, an embodiment of the present disclosure also provides a computer-readable storage medium, on which a computer program is stored. When the computer program is executed by a processor, the operating method described in any of the above-mentioned embodiments is executed.

[0161] Here, all or part of the processes in the above-mentioned embodiments can be implemented by instructing relevant hardware through a computer program. The program can be stored in a computer-readable storage medium. When the program is executed, it can include the processes of the embodiments of the above-mentioned methods. The storage medium can be a magnetic disk, an optical disk, a read-only memory (ROM), a random access memory (RAM), a flash memory, a hard disk (HDD), or a solid-state drive; the storage medium can also include a combination of the above-mentioned types of memory.

[0162] It should be understood that “one embodiment” or “an embodiment” mentioned throughout the specification means that specific features, structures or characteristics related to the embodiment are included in at least one embodiment of the present disclosure. Therefore, “in one embodiment” or “in an embodiment” appearing throughout the specification does not necessarily refer to the same embodiment. In addition, these specific features, structures or characteristics can be combined in one or more embodiments in any suitable manner. It should be understood that in the various embodiments of the present disclosure, the size of the serial numbers of the above-mentioned processes does not mean the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of the present disclosure. The serial numbers of the embodiments of the present disclosure are for description only and do not represent the advantages and disadvantages of the embodiments.

[0163] The methods disclosed in the several method embodiments provided in this disclosure can be arbitrarily combined without conflict to obtain new method embodiments.

[0164] The above description is merely a specific embodiment of the present disclosure, but the scope of protection of the present disclosure is not limited thereto. Any changes or substitutions that can be easily conceived by a person skilled in the art within the technical scope disclosed in this disclosure should be included in the scope of protection of the present disclosure. Therefore, the scope of protection of the present disclosure should be based on the scope of protection of the claims.

Claims

1. A memory system, comprising a memory device and a memory controller coupled to the memory device; The memory controller is configured to: A read command is received, wherein the read command indicates reading event log information generated during the operation of the firmware, wherein the event log information includes an index number and a parameter value of the event log; different event log elements are generated corresponding to different functional modules of the firmware operation, and different event log elements correspond to different index numbers.

2. The memory system according to claim 1, wherein: The firmware includes an output program for event log information, and the output program for event log information is configured to record an index number and a parameter value of an event log; the memory controller is configured to: When the firmware runs to the functional module, the output program of the event log information in the firmware is run, thereby generating event log information including an index number and a parameter value.

3. The memory system according to claim 1, wherein: According to the event log information and the code file, the event log element corresponding to the index number in the event log information and the parameter name corresponding to the parameter value can be obtained; The code file includes a correspondence table between event log elements and index numbers, and a parameter name list corresponding to each event log element.

4. The memory system according to claim 3, wherein: The parameter name list includes a plurality of parameter names; the code file further includes: placeholder information corresponding to the parameter names; The interval between two adjacent parameter values ​​can be obtained according to the placeholder information.

5. The memory system according to claim 1, wherein: The memory controller is configured to: The event log information is temporarily stored in a buffer before receiving the read command.

6. The memory system according to claim 5, wherein: The memory controller is configured to: The event log information temporarily stored in the buffer is transferred to the memory device.

7. The memory system according to claim 1, wherein: The functional modules include: a garbage collection module, a normal power on and off module, an abnormal power on and off module, a wear leveling module, and a bad block management module.

8. The memory system according to claim 1, wherein: The memory system includes a memory card or a solid state drive.

9. A host-end device, the host-end device comprising a compilation system; the compilation system comprising a compilation controller, the compilation controller being configured to: receiving a scan command, the scan command instructing to scan a project file, and generating an event log set by extracting keywords related to event logs in the project file, the event log set including a plurality of event log elements; The firmware runs different functional modules and generates different event log elements. A code file is generated, wherein the code file includes a correspondence table between event log elements and index numbers, and a parameter name list corresponding to each event log element.

10. The host-side device according to claim 9, wherein: The host-end device further includes a parsing system, the parsing system includes a parsing controller, and the parsing controller is configured to: Receive event log information and the code file; the event log information includes an index number and a parameter value of the event log; The firmware runs different function modules and generates different event log elements. Different event log elements correspond to different index numbers. The event log element corresponding to the index number in the event log information and the parameter name corresponding to the parameter value are obtained according to the event log information and the code file.

11. The host-side device according to claim 10, wherein: The parameter name list includes a plurality of parameter names; the code file further includes: placeholder information corresponding to the parameter names; the parsing controller is configured to: The interval between two adjacent parameter values ​​is obtained according to the placeholder information.

12. A method for operating a memory system, the method comprising: Receive a read command, wherein the read command indicates to read event log information generated during the operation of the firmware, wherein the event log information includes an index number and a parameter value of the event log; Different function modules running in the firmware generate different event log elements, and different event log elements correspond to different index numbers.

13. The operating method according to claim 12, wherein: The firmware includes an output program for event log information, and the output program for event log information is configured to record an index number and a parameter value of an event log; The method further comprises: When the firmware runs to the functional module, the output program of the event log information in the firmware is run, thereby generating event log information including an index number and a parameter value.

14. The operating method according to claim 12, wherein: According to the event log information and the code file, the event log element corresponding to the index number in the event log information and the parameter name corresponding to the parameter value can be obtained; The code file includes a correspondence table between event log elements and index numbers, and a parameter name list corresponding to each event log element.

15. The operating method according to claim 14, wherein: The parameter name list includes a plurality of parameter names; the code file further includes: placeholder information corresponding to the parameter names; The interval between two adjacent parameter values ​​can be obtained according to the placeholder information.

16. The operating method according to claim 12, wherein: The method further comprises: Before receiving the read command, the event log information is temporarily stored in a buffer.

17. The operating method according to claim 16, wherein: The method further comprises: The event log information temporarily stored in the buffer is transferred to the memory device.

18. A method for operating a host-side device, the method comprising: receiving a scan command, the scan command instructing to scan a project file, and generating an event log set by extracting keywords related to event logs in the project file, the event log set including a plurality of event log elements; The firmware runs different functional modules and generates different event log elements. A code file is generated, wherein the code file includes a correspondence table between event log elements and index numbers, and a parameter name list corresponding to each event log element.

19. The operating method according to claim 18, wherein: The method further comprises: Receive event log information and the code file; the event log information includes an index number and a parameter value of the event log; different event log elements are generated corresponding to different function modules running in the firmware, and different event log elements correspond to different index numbers; The event log element corresponding to the index number in the event log information and the parameter name corresponding to the parameter value are obtained according to the event log information and the code file.

20. The operating method according to claim 19, wherein: The parameter name list includes multiple parameter names; The code file further includes: placeholder information corresponding to the parameter name; the method further includes: The interval between two adjacent parameter values ​​is obtained according to the placeholder information.

21. A computer-readable storage medium having a computer program stored thereon, wherein the computer program, when executed by a processor, performs the operating method according to any one of claims 12 to 20.

Images