Gate driving circuit and display panel

Abstract

A gate driving circuit and a display panel. The gate driving circuit comprises: a plurality of gate driving units and a plurality of dummy driving units; the gate driving units and the dummy driving units each comprise a first pull-down maintaining module (101); the first pull-down maintaining module (101) comprises a first transistor (T1); the channel length of the first transistor (T1) in the corresponding gate driving unit is less than the channel length of the first transistor (T1) in the corresponding dummy driving unit; and a channel width-to-length ratio of the first transistor (T1) in the gate driving unit is equal to a channel width-to-length ratio of the first transistor (T1) in the dummy driving unit.

Description

Gate drive circuit and display panel Technical Field

[0001] The present application relates to the field of display technology, and in particular to a gate drive circuit and a display panel. Background Art

[0002] Existing high-resolution display panels are typically driven by a gate-driver on array (GOA) circuit integrated on an array substrate. The redundant drive units near the end of the gate drive circuit are activated by a start signal. Due to the prolonged loading of the start signal, the threshold voltage of the corresponding pull-down transistor shifts to the right, reducing its pull-down capability. Consequently, the redundant drive units near the end of the gate drive circuit have poor output signal capabilities, resulting in dark lines in the corresponding display area. SUMMARY OF THE INVENTION

[0003] The present application provides a gate driving circuit and a display panel, which can improve the level transmission signal output capability of a redundant driving unit near the end of the gate driving circuit and improve the appearance of dark lines in the display area.

[0004] On the one hand, an embodiment of the present application provides a gate drive circuit, comprising: a plurality of gate drive units; and a plurality of redundant drive units; wherein the gate drive unit and the virtual drive unit are cascaded, and both the gate drive unit and the virtual drive unit are used to output a current-stage transmission signal, and the gate drive unit is also used to output a current-stage scan signal; the gate drive unit and the virtual drive unit each include a first pull-down maintenance module, the first pull-down maintenance module is electrically connected to a pull-up node, a first reference low-level signal terminal, and a current-stage transmission signal output terminal, and the first pull-down maintenance module is used to control the potential of the pull-up node and the current-stage transmission signal output terminal; the first pull-down maintenance module includes a first transistor, the gate of the first transistor is electrically connected to the pull-up node, the first electrode of the first transistor is electrically connected to the first pull-down node, and the second electrode of the first transistor is electrically connected to the first reference low-level signal terminal; wherein the channel length of the first transistor in the gate drive unit is less than the channel length of the first transistor in the virtual drive unit, and the channel width-to-length ratio of the first transistor in the gate drive unit is equal to the channel width-to-length ratio of the first transistor in the virtual drive unit.

[0005] Optionally, in some embodiments of the present application, the gate driving unit and the virtual driving unit both include an output module, the output module is used to output the current-level stage transmission signal, and the output module of the gate driving unit is also used to output the current-level scanning signal; the output module includes a second transistor, the gate of the second transistor is electrically connected to the pull-up node, the first electrode of the second transistor is electrically connected to the clock signal end, and the second electrode of the second transistor is electrically connected to the stage transmission signal end; the channel length of the second transistor in the gate driving unit is smaller than the channel length of the second transistor in the virtual driving unit, and the channel width-to-length ratio of the second transistor in the gate driving unit is equal to the channel width-to-length ratio of the second transistor in the virtual driving unit.

[0006] Optionally, in some embodiments of the present application, the output module further includes a third transistor and a bootstrap capacitor, the gate of the third transistor is electrically connected to the pull-up node, the first electrode of the third transistor is electrically connected to the clock signal end, the second electrode of the third transistor is electrically connected to the current level scan signal output end, one end of the bootstrap capacitor is electrically connected to the pull-up node, and the other end of the bootstrap capacitor is electrically connected to the current level scan signal output end; the channel length of the third transistor in the gate driving unit is greater than the channel length of the third transistor in the virtual driving unit, and the channel width-to-length ratio of the third transistor in the gate driving unit is equal to the channel width-to-length ratio of the third transistor in the virtual driving unit.

[0007] Optionally, in some embodiments of the present application, the first pull-down maintaining module further includes a fourth transistor, a fifth transistor and a sixth transistor, the gate of the fourth transistor and the first electrode of the fourth transistor are electrically connected to the first control signal terminal, the second electrode of the fourth transistor is electrically connected to the first pull-down node, the gate of the fifth transistor is electrically connected to the first pull-down node, the first electrode of the fifth transistor is electrically connected to the first control signal terminal, the second electrode of the fifth transistor is electrically connected to the second pull-down node, the gate of the sixth transistor is electrically connected to the pull-up node, the first electrode of the sixth transistor is electrically connected to the second pull-down node, and the second electrode of the sixth transistor is electrically connected to the pull-up node. the first reference low-level signal terminal is electrically connected to the gate driving unit; the channel length of the fourth transistor in the gate driving unit is smaller than the channel length of the fourth transistor in the virtual driving unit, and / or the channel length of the fifth transistor in the gate driving unit is smaller than the channel length of the fifth transistor in the virtual driving unit, and / or the channel length of the sixth transistor in the gate driving unit is smaller than the channel length of the sixth transistor in the virtual driving unit; and the channel width-to-length ratio of the fourth transistor, the fifth transistor and the sixth transistor in the gate driving unit is equal to the channel width-to-length ratio of the fourth transistor, the fifth transistor and the sixth transistor in the virtual driving unit.

[0008] Optionally, in some embodiments of the present application, the first pull-down maintaining module further includes a seventh transistor, an eighth transistor, and a ninth transistor, the gate of the seventh transistor being electrically connected to the second pull-down node, the first electrode of the seventh transistor being electrically connected to the current-stage scan signal output terminal, the second electrode of the seventh transistor being electrically connected to the second reference low-level signal terminal, the gate of the eighth transistor being electrically connected to the second pull-down node, the first electrode of the eighth transistor being electrically connected to the pull-up node, the second electrode of the eighth transistor being electrically connected to the first reference low-level signal terminal, the gate of the ninth transistor being electrically connected to the second pull-down node, the first electrode of the ninth transistor being electrically connected to the current-stage scan signal output terminal, and the second electrode of the ninth transistor being electrically connected to the first reference low-level signal terminal; the channel lengths of the seventh and eighth transistors in the gate driving unit are both greater than the channel lengths of the seventh and eighth transistors in the virtual driving unit, and the channel width-to-length ratios of the seventh and eighth transistors in the gate driving unit are equal to the channel width-to-length ratios of the seventh and eighth transistors in the virtual driving unit.

[0009] Optionally, in some embodiments of the present application, the channel length of the ninth transistor in the gate driving unit is greater than or equal to the channel length of the ninth transistor in the virtual driving unit, and the channel width-to-length ratio of the ninth transistor in the gate driving unit is equal to the channel width-to-length ratio of the ninth transistor in the virtual driving unit.

[0010] Optionally, in some embodiments of the present application, the gate driving unit and the virtual driving unit both include a second pull-down maintaining module, the second pull-down maintaining module is electrically connected to the pull-up node, the first reference low-level signal end and the current-level signal output end, and the second pull-down maintaining module is used to control the potential of the pull-up node and the current-level signal output end; the second pull-down maintaining module includes a tenth transistor, the gate of the tenth transistor is electrically connected to the pull-up node, the first electrode of the tenth transistor is electrically connected to the third pull-down node, and the second electrode of the tenth transistor is electrically connected to the first reference low-level signal end; the channel length of the tenth transistor in the gate driving unit is smaller than the channel length of the tenth transistor in the virtual driving unit, and the channel width-to-length ratio of the tenth transistor in the gate driving unit is equal to the channel width-to-length ratio of the tenth transistor in the virtual driving unit.

[0011] Optionally, in some embodiments of the present application, the second pull-down maintaining module further includes an eleventh transistor, a twelfth transistor and a thirteenth transistor, the gate of the eleventh transistor and the first electrode of the eleventh transistor are electrically connected to the second control signal terminal, the second electrode of the eleventh transistor is electrically connected to the third pull-down node, the gate of the twelfth transistor is electrically connected to the third pull-down node, the first electrode of the twelfth transistor is electrically connected to the second control signal terminal, the second electrode of the twelfth transistor is electrically connected to the fourth pull-down node, the gate of the thirteenth transistor is electrically connected to the pull-up node, the first electrode of the thirteenth transistor is electrically connected to the fourth pull-down node, and the second electrode of the thirteenth transistor is electrically connected to the pull-up node. the eleventh transistor in the gate driving unit is electrically connected to the first reference low-level signal terminal; the channel length of the eleventh transistor in the gate driving unit is smaller than the channel length of the eleventh transistor in the virtual driving unit, and / or the channel length of the twelfth transistor in the gate driving unit is smaller than the channel length of the twelfth transistor in the virtual driving unit, and / or the channel length of the thirteenth transistor in the gate driving unit is smaller than the channel length of the thirteenth transistor in the virtual driving unit; and the channel width-to-length ratio of the eleventh transistor, the twelfth transistor, and the thirteenth transistor in the gate driving unit is equal to the channel width-to-length ratio of the eleventh transistor, the twelfth transistor, and the thirteenth transistor in the virtual driving unit.

[0012] Optionally, in some embodiments of the present application, the second pull-down maintaining module further includes a fourteenth transistor, a fifteenth transistor, and a sixteenth transistor, the gate of the fourteenth transistor being electrically connected to the fourth pull-down node, the first electrode of the fourteenth transistor being electrically connected to the current-stage scan signal output terminal, the second electrode of the fourteenth transistor being electrically connected to the second reference low-level signal terminal, the gate of the fifteenth transistor being electrically connected to the fourth pull-down node, the first electrode of the fifteenth transistor being electrically connected to the pull-up node, the second electrode of the fifteenth transistor being electrically connected to the first reference low-level signal terminal, and the sixteenth transistor being electrically connected to the fourth pull-down node. The gate of the transistor is electrically connected to the fourth pull-down node, the first electrode of the sixteenth transistor is electrically connected to the current-stage signal output terminal, and the second electrode of the sixteenth transistor is electrically connected to the first reference low-level signal terminal; the channel lengths of the fourteenth transistor and the fifteenth transistor in the gate driving unit are both greater than the channel lengths of the fourteenth transistor and the fifteenth transistor in the virtual driving unit, and the channel width-to-length ratio of the fourteenth transistor and the fifteenth transistor in the gate driving unit is equal to the channel width-to-length ratio of the fourteenth transistor and the fifteenth transistor in the virtual driving unit.

[0013] Optionally, in some embodiments of the present application, the channel length of the sixteenth transistor in the gate driving unit is greater than or equal to the channel length of the sixteenth transistor in the virtual driving unit, and the channel width-to-length ratio of the sixteenth transistor in the gate driving unit is equal to the channel width-to-length ratio of the sixteenth transistor in the virtual driving unit.

[0014] On the other hand, the present application also provides a display panel, the display panel includes a display area and a non-display area arranged around the display area, wherein the non-display area is provided with a gate drive circuit, the gate drive circuit includes: a plurality of gate drive units and a plurality of virtual drive units, the gate drive unit and the virtual drive unit are cascaded, the gate drive unit and the virtual drive unit are both used to output the current level transmission signal, the gate drive unit is also used to output the current level scanning signal; the gate drive unit and the virtual drive unit both include a first pull-down maintenance module, the first pull-down maintenance module is connected to the pull-up node, the first reference low-level signal terminal and the current level transmission signal The output end is electrically connected, and the first pull-down maintaining module is used to control the potential of the pull-up node and the current-stage signal output end; the first pull-down maintaining module includes a first transistor, the gate of the first transistor is electrically connected to the pull-up node, the first electrode of the first transistor is electrically connected to the first pull-down node, and the second electrode of the first transistor is electrically connected to the first reference low-level signal end; wherein, the channel length of the first transistor in the gate driving unit is less than the channel length of the first transistor in the virtual driving unit, and the channel width-to-length ratio of the first transistor in the gate driving unit is equal to the channel width-to-length ratio of the first transistor in the virtual driving unit.

[0015] Optionally, in some embodiments of the present application, the gate driving unit and the virtual driving unit both include an output module, the output module is used to output the current-level stage transmission signal, and the output module of the gate driving unit is also used to output the current-level scanning signal; the output module includes a second transistor, the gate of the second transistor is electrically connected to the pull-up node, the first electrode of the second transistor is electrically connected to the clock signal end, and the second electrode of the second transistor is electrically connected to the stage transmission signal end; the channel length of the second transistor in the gate driving unit is smaller than the channel length of the second transistor in the virtual driving unit, and the channel width-to-length ratio of the second transistor in the gate driving unit is equal to the channel width-to-length ratio of the second transistor in the virtual driving unit.

[0016] Optionally, in some embodiments of the present application, the output module further includes a third transistor and a bootstrap capacitor, the gate of the third transistor is electrically connected to the pull-up node, the first electrode of the third transistor is electrically connected to the clock signal end, the second electrode of the third transistor is electrically connected to the current level scan signal output end, one end of the bootstrap capacitor is electrically connected to the pull-up node, and the other end of the bootstrap capacitor is electrically connected to the current level scan signal output end; the channel length of the third transistor in the gate driving unit is greater than the channel length of the third transistor in the virtual driving unit, and the channel width-to-length ratio of the third transistor in the gate driving unit is equal to the channel width-to-length ratio of the third transistor in the virtual driving unit.

[0017] Optionally, in some embodiments of the present application, the first pull-down maintaining module further includes a fourth transistor, a fifth transistor and a sixth transistor, the gate of the fourth transistor and the first electrode of the fourth transistor are electrically connected to the first control signal terminal, the second electrode of the fourth transistor is electrically connected to the first pull-down node, the gate of the fifth transistor is electrically connected to the first pull-down node, the first electrode of the fifth transistor is electrically connected to the first control signal terminal, the second electrode of the fifth transistor is electrically connected to the second pull-down node, the gate of the sixth transistor is electrically connected to the pull-up node, the first electrode of the sixth transistor is electrically connected to the second pull-down node, and the second electrode of the sixth transistor is electrically connected to the pull-up node. the first reference low-level signal terminal is electrically connected to the gate driving unit; the channel length of the fourth transistor in the gate driving unit is smaller than the channel length of the fourth transistor in the virtual driving unit, and / or the channel length of the fifth transistor in the gate driving unit is smaller than the channel length of the fifth transistor in the virtual driving unit, and / or the channel length of the sixth transistor in the gate driving unit is smaller than the channel length of the sixth transistor in the virtual driving unit; and the channel width-to-length ratio of the fourth transistor, the fifth transistor and the sixth transistor in the gate driving unit is equal to the channel width-to-length ratio of the fourth transistor, the fifth transistor and the sixth transistor in the virtual driving unit.

[0018] Optionally, in some embodiments of the present application, the first pull-down maintaining module further includes a seventh transistor, an eighth transistor, and a ninth transistor, the gate of the seventh transistor being electrically connected to the second pull-down node, the first electrode of the seventh transistor being electrically connected to the current-stage scan signal output terminal, the second electrode of the seventh transistor being electrically connected to the second reference low-level signal terminal, the gate of the eighth transistor being electrically connected to the second pull-down node, the first electrode of the eighth transistor being electrically connected to the pull-up node, the second electrode of the eighth transistor being electrically connected to the first reference low-level signal terminal, the gate of the ninth transistor being electrically connected to the second pull-down node, the first electrode of the ninth transistor being electrically connected to the current-stage scan signal output terminal, and the second electrode of the ninth transistor being electrically connected to the first reference low-level signal terminal; the channel lengths of the seventh and eighth transistors in the gate driving unit are both greater than the channel lengths of the seventh and eighth transistors in the virtual driving unit, and the channel width-to-length ratios of the seventh and eighth transistors in the gate driving unit are equal to the channel width-to-length ratios of the seventh and eighth transistors in the virtual driving unit.

[0019] Optionally, in some embodiments of the present application, the channel length of the ninth transistor in the gate driving unit is greater than or equal to the channel length of the ninth transistor in the virtual driving unit, and the channel width-to-length ratio of the ninth transistor in the gate driving unit is equal to the channel width-to-length ratio of the ninth transistor in the virtual driving unit.

[0020] Optionally, in some embodiments of the present application, the gate driving unit and the virtual driving unit both include a second pull-down maintaining module, the second pull-down maintaining module is electrically connected to the pull-up node, the first reference low-level signal end and the current-level signal output end, and the second pull-down maintaining module is used to control the potential of the pull-up node and the current-level signal output end; the second pull-down maintaining module includes a tenth transistor, the gate of the tenth transistor is electrically connected to the pull-up node, the first electrode of the tenth transistor is electrically connected to the third pull-down node, and the second electrode of the tenth transistor is electrically connected to the first reference low-level signal end; the channel length of the tenth transistor in the gate driving unit is smaller than the channel length of the tenth transistor in the virtual driving unit, and the channel width-to-length ratio of the tenth transistor in the gate driving unit is equal to the channel width-to-length ratio of the tenth transistor in the virtual driving unit.

[0021] Optionally, in some embodiments of the present application, the second pull-down maintaining module further includes an eleventh transistor, a twelfth transistor and a thirteenth transistor, the gate of the eleventh transistor and the first electrode of the eleventh transistor are electrically connected to the second control signal terminal, the second electrode of the eleventh transistor is electrically connected to the third pull-down node, the gate of the twelfth transistor is electrically connected to the third pull-down node, the first electrode of the twelfth transistor is electrically connected to the second control signal terminal, the second electrode of the twelfth transistor is electrically connected to the fourth pull-down node, the gate of the thirteenth transistor is electrically connected to the pull-up node, the first electrode of the thirteenth transistor is electrically connected to the fourth pull-down node, and the second electrode of the thirteenth transistor is electrically connected to the pull-up node. the eleventh transistor in the gate driving unit is electrically connected to the first reference low-level signal terminal; the channel length of the eleventh transistor in the gate driving unit is smaller than the channel length of the eleventh transistor in the virtual driving unit, and / or the channel length of the twelfth transistor in the gate driving unit is smaller than the channel length of the twelfth transistor in the virtual driving unit, and / or the channel length of the thirteenth transistor in the gate driving unit is smaller than the channel length of the thirteenth transistor in the virtual driving unit; and the channel width-to-length ratio of the eleventh transistor, the twelfth transistor, and the thirteenth transistor in the gate driving unit is equal to the channel width-to-length ratio of the eleventh transistor, the twelfth transistor, and the thirteenth transistor in the virtual driving unit.

[0022] Optionally, in some embodiments of the present application, the second pull-down maintaining module further includes a fourteenth transistor, a fifteenth transistor, and a sixteenth transistor, the gate of the fourteenth transistor being electrically connected to the fourth pull-down node, the first electrode of the fourteenth transistor being electrically connected to the current-stage scan signal output terminal, the second electrode of the fourteenth transistor being electrically connected to the second reference low-level signal terminal, the gate of the fifteenth transistor being electrically connected to the fourth pull-down node, the first electrode of the fifteenth transistor being electrically connected to the pull-up node, the second electrode of the fifteenth transistor being electrically connected to the first reference low-level signal terminal, and the sixteenth transistor being electrically connected to the fourth pull-down node. The gate of the transistor is electrically connected to the fourth pull-down node, the first electrode of the sixteenth transistor is electrically connected to the current-stage signal output terminal, and the second electrode of the sixteenth transistor is electrically connected to the first reference low-level signal terminal; the channel lengths of the fourteenth transistor and the fifteenth transistor in the gate driving unit are both greater than the channel lengths of the fourteenth transistor and the fifteenth transistor in the virtual driving unit, and the channel width-to-length ratio of the fourteenth transistor and the fifteenth transistor in the gate driving unit is equal to the channel width-to-length ratio of the fourteenth transistor and the fifteenth transistor in the virtual driving unit.

[0023] Optionally, in some embodiments of the present application, the channel length of the sixteenth transistor in the gate driving unit is greater than or equal to the channel length of the sixteenth transistor in the virtual driving unit, and the channel width-to-length ratio of the sixteenth transistor in the gate driving unit is equal to the channel width-to-length ratio of the sixteenth transistor in the virtual driving unit. Beneficial effects

[0024] The gate drive circuit provided in an embodiment of the present application solves the problem of dark lines appearing in the display area by increasing the channel length of the first transistor in the gate drive unit and adjusting the channel width of the first transistor in the virtual drive unit accordingly. This improves the level transmission signal output capability of the virtual drive unit near the end of the gate drive circuit, thereby solving the problem of dark lines appearing in the display area. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] FIG1 is a schematic structural diagram of a gate drive circuit provided in an embodiment of the present application;

[0026] FIG2 a is a schematic diagram of a first structure of a gate driving unit in the gate driving circuit provided in FIG1 ;

[0027] FIG2 b is a comparison diagram of the channel of the first transistor in the virtual driving unit provided in FIG1 before and after adjustment;

[0028] FIG3a is a waveform of a current-stage scanning signal output by a gate driving unit when the virtual driving unit is not adjusted; FIG3b is a waveform of a current-stage scanning signal output by a gate driving unit after the virtual driving unit is adjusted;

[0029] FIG4 a is a waveform of a current-stage transmission signal output by the virtual driving unit after the virtual driving unit is adjusted;

[0030] FIG4 b is a waveform of the current-stage scanning signal output by the gate driving unit after adjustment by the virtual driving unit;

[0031] FIG5 is a schematic diagram of a second structure of a gate driving unit in the gate driving circuit provided in FIG1 ;

[0032] FIG6 is a schematic diagram of a third structure of the gate driving unit in the gate driving circuit provided in FIG1 ;

[0033] FIG7 is a schematic diagram of a fourth structure of the gate driving unit in the gate driving circuit provided in FIG1 ;

[0034] FIG8 is a schematic diagram of a fifth structure of the gate driving unit in the gate driving circuit provided in FIG1 ;

[0035] FIG9 is a sixth structural diagram of the gate driving unit in the gate driving circuit provided in FIG1 . Modes for Carrying Out the Invention

[0036] The following will describe the technical solutions in the embodiments of the present application in conjunction with the drawings in the embodiments of the present application. The described embodiments are only used to explain and illustrate the ideas of the present application and should not be regarded as limiting the scope of protection of the present application.

[0037] The transistors used in all embodiments of the present application may be thin film transistors or other devices with similar characteristics. In the embodiments of the present application, in order to distinguish the two poles of the transistor other than the gate, one of the source and the drain is referred to as the first electrode, and the other of the source and the drain is referred to as the second electrode. According to the form in the accompanying drawings, the signal control end of the switching transistor is defined as the gate, the signal input end is defined as the first electrode, and the signal output end is defined as the second electrode. In addition, the transistors used in the embodiments of the present application are N-type transistors or P-type transistors, wherein the N-type transistor is turned on when the gate is at a high potential and is cut off when the gate is at a low potential; the P-type transistor is turned on when the gate is at a low potential and is cut off when the gate is at a high potential.

[0038] As shown in Figure 1, the gate drive circuit provided in an embodiment of the present application includes: multiple gate drive units Normal and multiple redundant drive units Dummies. The gate drive units Normal and Dummies are cascaded, and both the gate drive units Normal and Dummies are used to output the current-stage transmission signal ST (N-1, N, N+1...). The gate drive unit Normal is also used to output the current-stage scan signal G (N-1, N, N+1...). Figure 1 takes the cascaded N-1th, Nth, and N+1th gate drive units Normal as an example.

[0039] When the N-th gate drive unit is operating in Normal mode, the scan signal output by the N-th gate drive unit is high, which is used to turn on the transistor switch of each pixel in a row of the display panel and charge the pixel electrode in each pixel through the data signal. The N-th level transmission signal is used to control the operation of the N+1-th gate drive unit. When the N+1-th gate drive unit is operating in Normal mode, the scan signal output by the N+1-th gate drive unit is high, and the scan signal output by the N-th gate drive unit is low.

[0040] As shown in FIG2a , both the gate driver unit and the redundant driver unit include a first pull-down maintenance module 101. The first pull-down maintenance module 101 is electrically connected to a pull-up node Q, a first reference low-level signal terminal VSSQ, and the current-stage signal output terminals ST(N−1, N, N+1, ...). The first pull-down maintenance module 101 is configured to control the potentials of the pull-up node Q and the current-stage signal output terminals ST(N−1, N, N+1, ...). The first pull-down maintenance module 101 includes a first transistor T1, a gate of the first transistor T1 being electrically connected to the pull-up node Q, a first electrode of the first transistor T1 being electrically connected to a first pull-down node K1, and a second electrode of the first transistor T1 being electrically connected to the first reference low-level signal terminal VSSQ. The channel length of the first transistor T1 in the gate driver unit is shorter than the channel length of the first transistor T1 in the redundant driver unit, and the channel width-to-length ratio of the first transistor T1 in the gate driver unit is equal to the channel width-to-length ratio of the first transistor T1 in the redundant driver unit. Specifically, the first pull-down maintaining module 101 is also electrically connected to the second reference low-level signal terminal VSSG.

[0041] Experimental verification shows that after the gate drive circuit provided by this application undergoes high-temperature and high-humidity aging, if the channel length of the first transistor T1 is reduced, horizontal dark lines will appear in the corresponding display area. That is, the channel length of the first transistor T1 has a significant impact on the output waveform of the current-stage scan signal G(N-1, N, N+1...) of the gate drive unit. Therefore, as shown in Figure 2b, the first transistor T1' before adjustment includes a first active layer 10, a first source electrode 11, and a first drain electrode 12, and the first transistor T1 after adjustment includes a second active layer 20, a second source electrode 21, and a second drain electrode 22. The channel length H2 of the adjusted first transistor T1 is greater than the channel length H1 of the first transistor T1' before adjustment, and the channel width W2 of the adjusted first transistor T1 is greater than the channel width W1 of the first transistor T1' before adjustment, so that the channel width-to-length ratio of the adjusted first transistor T1 is equal to the channel width-to-length ratio of the first transistor T1 before adjustment. That is, in the embodiment of the present application, by increasing the channel length of the first transistor T1 in the redundant driving unit and adjusting the channel width accordingly to maintain the channel width-to-length ratio of the first transistor T1 in the redundant driving unit unchanged, the stability of the first transistor T1 in the redundant driving unit can be improved, and leakage of the first pull-down maintenance module 101 can be avoided, which may cause the output capability of the current-stage transmission signal ST (N-1, N, N+1...) to deteriorate, thereby preventing the pull-down capability of the pull-down transistor of the gate driving unit from also deteriorating, resulting in the occurrence of horizontal dark lines in the display area corresponding to the end of the gate driving circuit (especially the pixel unit electrically connected to the last-stage gate driving unit).

[0042] In the embodiment of the present application, both the gate drive unit and the redundant drive unit include an output module 102. The output module 102 is electrically connected to the clock signal terminal CK, the pull-up node Q, the current-stage transmission signal output terminal ST (N-1, N, N+1...), and the current-stage scan signal output terminal G (N-1, N, N+1...). The output module 102 is used to output the current-stage transmission signal ST (N-1, N, N+1...). The output module 102 of the gate drive unit is also used to output the current-stage scan signal G (N-1, N, N+1...). Specifically, the current-stage scan signal output terminal G (N-1, N, N+1...) of the gate drive unit is electrically connected to the corresponding scan line.

[0043] In an embodiment of the present application, the gate driving unit and the redundant driving unit both include a second pull-down maintaining module 103, which is electrically connected to the pull-up node Q, the first reference low-level signal terminal VSSQ, and the current-stage signal output terminal ST (N-1, N, N+1...). The second pull-down maintaining module 103 is used to control the potential of the pull-up node Q and the current-stage signal output terminal ST (N-1, N, N+1...). The second pull-down maintaining module 103 works alternately with the first pull-down maintaining module 101, which is beneficial to improving the performance and life of the device by sharing the workload.

[0044] In the embodiment of the present application, both the gate drive unit and the redundant drive unit include a pull-up control module 104, a reset module 105, and a pull-down module 106. The pull-up control module 104 is electrically connected to the current-stage scan signal output terminal G(N-8) corresponding to the eight previous stages and the current-stage transmission signal output terminal ST(N-8) corresponding to the eight previous stages. The reset module 105 is electrically connected to the reset signal terminal Reset, the pull-up node Q, and the first reference low-level signal terminal VSSQ. The pull-down module 106 is electrically connected to the pull-up node Q, the current-stage scan signal output terminals G(N-1, N, N+1...), the first reference low-level signal terminal VSSQ, and the second reference low-level signal terminal VSSG. The pull-up control module 104 is configured to control the potential of the pull-up node Q. Specifically, the pull-up control module 104 is configured to pull the potential of the pull-up node Q high. The reset module 105 is configured to reset the potential of the pull-up node Q. The pull-down module 106 is used to control the potential of the pull-up node Q and the current-stage scan signal output terminal G (N-1, N, N+1...). Specifically, the pull-down module 106 is used to pull down the potential of the pull-up node Q and the current-stage scan signal output terminal G (N-1, N, N+1...).

[0045] It should be noted that the circuit structure of the gate driving unit is the same as the circuit structure of the redundant driving unit. The channel length of the first transistor in the redundant driving unit is adjusted, and the channel width of the first transistor is adjusted accordingly according to the adjusted channel length, so that the channel width-to-length ratio of the first transistor remains unchanged.

[0046] Although adjustment of the channel length can affect the stability and performance of the circuit, as shown in Figures 3a and 3b, when the channel length of the first transistor T1 in the redundant driving unit is appropriately adjusted, the waveform of the current-stage scanning signal G(N-1, N, N+1...) output by the gate driving unit does not differ significantly. In other words, adjusting the channel length of the first transistor T1 in the redundant driving unit does not affect the waveform of the current-stage scanning signal G(N-1, N, N+1...) output by the gate driving unit.

[0047] It should be noted that the test parameters of the first transistor T1 in the redundant driving unit remain unchanged before and after the channel length adjustment, including temperature, transistor threshold voltage, reference high level, etc. Specifically, in a low-temperature environment, the temperature is less than or equal to -40 degrees Celsius, preferably -50 degrees Celsius. In a high-temperature environment, the temperature is greater than or equal to 200 degrees Celsius, preferably 250 degrees Celsius. The threshold voltage of the P-type transistor is greater than or equal to 6 volts, and the threshold voltage of the N-type transistor is less than or equal to -5 volts. The reference high level is less than or equal to 12V.

[0048] In addition, as shown in Figures 4a and 4b, after the channel length of the first transistor T1 in the redundant driving unit is adjusted, the waveform of the current-stage transmission signal ST (N-1, N, N+1...) output by the redundant driving unit has no obvious difference from the waveform of the current-stage scanning signal G (N-1, N, N+1...) output by the gate driving unit. That is, after the channel length of the first transistor T1 in the redundant driving unit is adjusted, the waveform of the current-stage transmission signal ST (N-1, N, N+1...) output by the redundant driving unit can be maintained within the range of the predetermined waveform specification, and such adjustment does not affect the waveform of the current-stage scanning signal G (N-1, N, N+1...) output by the gate driving unit.

[0049] The gate driving circuit provided in the embodiment of the present application increases the channel length of the first transistor T1 in the gate driving unit to be shorter than the channel length of the first transistor T1 in the redundant driving unit, and the channel width-to-length ratio of the first transistor T1 in the gate driving unit is equal to the channel width-to-length ratio of the first transistor T1 in the redundant driving unit. That is, by increasing the channel length of the first transistor T1 in the redundant driving unit and correspondingly adjusting the channel width of the first transistor T1 in the redundant driving unit, the channel width-to-length ratio of the first transistor T1 in the redundant driving unit remains unchanged, thereby improving the level transmission signal output capability of the redundant driving unit, and facilitating solving the problem of dark lines appearing in the display area.

[0050] As a specific embodiment of the present application, as shown in FIG5 , the output module 102 includes a second transistor T2. The gate of the second transistor T2 is electrically connected to the pull-up node Q. The first electrode of the second transistor T2 is electrically connected to the clock signal terminal CK. The second electrode of the second transistor T2 is electrically connected to the current-stage signal transmission terminal ST (N-1, N, N+1, ...). The channel length of the second transistor T2 in the gate driving unit is shorter than the channel length of the second transistor T2 in the redundant driving unit, and the channel width-to-length ratio of the second transistor T2 in the gate driving unit is equal to the channel width-to-length ratio of the second transistor T2 in the redundant driving unit.

[0051] In the embodiment of the present application, the output module 102 further includes a third transistor T3 and a bootstrap capacitor. The gate of the third transistor T3 is electrically connected to the pull-up node Q, the first electrode of the third transistor T3 is electrically connected to the clock signal terminal CK, the second electrode of the third transistor T3 is electrically connected to the current-stage scan signal output terminal G(N-1, N, N+1...), one end of the bootstrap capacitor is electrically connected to the pull-up node Q, and the other end of the bootstrap capacitor is electrically connected to the current-stage scan signal output terminal G(N-1, N, N+1...). The channel length of the third transistor T3 in the gate driving unit is greater than the channel length of the third transistor T3 in the redundant driving unit, and the channel width-to-length ratio of the third transistor T3 in the gate driving unit is equal to the channel width-to-length ratio of the third transistor T3 in the redundant driving unit.

[0052] In the gate drive circuit provided in the embodiments of the present application, the channel length of the second transistor T2 in the redundant drive unit is further increased, while the channel width-to-length ratio of the second transistor T2 in the redundant drive unit remains unchanged. Simultaneously, the channel length of the third transistor T3 in the redundant drive unit is correspondingly reduced, while the channel width-to-length ratio of the third transistor T3 in the redundant drive unit remains unchanged. The size parameters of the second transistor T2 are adjusted, and the size of the bootstrap capacitor remains unchanged, thereby further improving the output capability of the current-stage transmission signal ST(N-1, N, N+1...), thereby more effectively improving the problem of horizontal dark lines in the display area.

[0053] As a specific embodiment of the present application, as shown in Figure 6, the first pull-down maintaining module 101 also includes a fourth transistor T4, a fifth transistor T5 and a sixth transistor T6, the gate of the fourth transistor T4 and the first electrode of the fourth transistor T4 are electrically connected to the first control signal terminal, the second electrode of the fourth transistor T4 is electrically connected to the first pull-down node K1, the gate of the fifth transistor T5 is electrically connected to the first pull-down node K1, the first electrode of the fifth transistor T5 is electrically connected to the first control signal terminal, the second electrode of the fifth transistor T5 is electrically connected to the second pull-down node P1, the gate of the sixth transistor T6 is electrically connected to the pull-up node Q, the first electrode of the sixth transistor T6 is electrically connected to the second pull-down node P1, and the second electrode of the sixth transistor T6 is electrically connected to the first reference low-level signal terminal VSSQ. The channel length of the fourth transistor T4 in the gate driving unit is smaller than the channel length of the fourth transistor T4 in the redundant driving unit, and / or the channel length of the fifth transistor T5 in the gate driving unit is smaller than the channel length of the fifth transistor T5 in the redundant driving unit, and / or the channel length of the sixth transistor T6 in the gate driving unit is smaller than the channel length of the sixth transistor T6 in the redundant driving unit. Furthermore, the channel width-to-length ratios of the fourth transistor T4, the fifth transistor T5, and the sixth transistor T6 in the gate driving unit are equal to the channel width-to-length ratios of the fourth transistor T4, the fifth transistor T5, and the sixth transistor T6 in the redundant driving unit.

[0054] Specifically, the channel lengths of the fourth transistor T4, the fifth transistor T5, and the sixth transistor T6 in the redundant driving unit may be appropriately increased simultaneously, or the channel length of only at least one of the fourth transistor T4, the fifth transistor T5, and the sixth transistor T6 may be appropriately increased while maintaining the channel width-to-length ratio of the fourth transistor T4, the fifth transistor T5, and the sixth transistor T6 unchanged, thereby improving the performance of the transistors and further improving the ability of the redundant driving unit to output the current-stage transmission signal ST (N-1, N, N+1, . . . ), thereby improving the problem of dark lines in the display area.

[0055] In the embodiment of the present application, the first pull-down maintaining module 101 further includes a seventh transistor T7, an eighth transistor T8 and a ninth transistor T9, the gate of the seventh transistor T7 is electrically connected to the second pull-down node P1, the first electrode of the seventh transistor T7 is electrically connected to the current-stage scan signal output terminal G (N-1, N, N+1...), the second electrode of the seventh transistor T7 is electrically connected to the second reference low-level signal terminal VSSG, the gate of the eighth transistor T8 is electrically connected to the second pull-down node P1, the first electrode of the eighth transistor T8 is electrically connected to the pull-up node Q, the second electrode of the eighth transistor T8 is electrically connected to the first reference low-level signal terminal VSSQ, the gate of the ninth transistor T9 is electrically connected to the second pull-down node P1, the first electrode of the ninth transistor T9 is electrically connected to the current-stage scan signal output terminal ST (N-1, N, N+1...), and the second electrode of the ninth transistor T9 is electrically connected to the first reference low-level signal terminal VSSQ. The channel lengths of the seventh transistor T7 and the eighth transistor T8 in the gate driving unit are both greater than the channel lengths of the seventh transistor T7 and the eighth transistor T8 in the redundant driving unit, and the channel width-to-length ratio of the seventh transistor T7 and the eighth transistor T8 in the gate driving unit is equal to the channel width-to-length ratio of the seventh transistor T7 and the eighth transistor T8 in the redundant driving unit.

[0056] The cause of horizontal dark lines in the gate drive circuit provided in the embodiment of the present application is that the threshold voltages of the first transistor T1 and the fourth transistor T4 shift to the right under long-term stress, resulting in the failure of the potentials of the first pull-down node K1 and the second pull-down node P1 to be promptly pulled down to the first reference low level. The high potential of the second pull-down node P1 causes leakage in the seventh transistor T7, the eighth transistor T8, and the ninth transistor T9, thereby deteriorating the output capability of the current-stage transmission signal ST (N-1, N, N+1...). Therefore, in the present application, the channel lengths of the first transistor T1, the fourth transistor T4, the fifth transistor T5, and the sixth transistor T6 in the redundant drive unit are appropriately increased while maintaining their channel width-to-length ratios unchanged to improve their performance, ensure that the potentials of the first pull-down node K1 and the second pull-down node P1 are promptly pulled down, thereby avoiding the deterioration of the output capability of the current-stage transmission signal ST (N-1, N, N+1...) caused by leakage, and improving the horizontal dark line problem. Furthermore, the channel lengths of the seventh transistor T7 and the eighth transistor T8 in the redundant driving unit are appropriately reduced to ensure layout space for the first transistor T1 , the fourth transistor T4 , the fifth transistor T5 and the sixth transistor T6 in the redundant driving unit.

[0057] In the embodiment of the present application, the channel length of the ninth transistor T9 in the gate driving unit is greater than or equal to the channel length of the ninth transistor T9 in the redundant driving unit, and the channel width-to-length ratio of the ninth transistor T9 in the gate driving unit is equal to the channel width-to-length ratio of the ninth transistor T9 in the redundant driving unit. In other words, the channel length of the ninth transistor T9 in the redundant driving unit can be reduced or maintained unchanged. Those skilled in the art can adjust this according to actual needs, and this application does not impose any specific restrictions here.

[0058] As a specific embodiment of the present application, as shown in FIG7 , the second pull-down maintaining module 103 includes a tenth transistor T10, wherein the gate of the tenth transistor T10 is electrically connected to the pull-up node Q, the first electrode of the tenth transistor T10 is electrically connected to the third pull-down node K2, and the second electrode of the tenth transistor T10 is electrically connected to the first reference low-level signal terminal VSSQ. The channel length of the tenth transistor T10 in the gate driving unit is less than the channel length of the tenth transistor T10 in the redundant driving unit, and the channel width-to-length ratio of the tenth transistor T10 in the gate driving unit is equal to the channel width-to-length ratio of the tenth transistor T10 in the redundant driving unit.

[0059] In an embodiment of the present application, the second pull-down maintaining module 103 also includes an eleventh transistor T11, a twelfth transistor T12 and a thirteenth transistor T13, the gate of the eleventh transistor T11 and the first electrode of the eleventh transistor T11 are electrically connected to the second control signal terminal, the second electrode of the eleventh transistor T11 is electrically connected to the third pull-down node K2, the gate of the twelfth transistor T12 is electrically connected to the third pull-down node K2, the first electrode of the twelfth transistor T12 is electrically connected to the second control signal terminal, the second electrode of the twelfth transistor T12 is electrically connected to the fourth pull-down node P2, the gate of the thirteenth transistor T13 is electrically connected to the pull-up node Q, the first electrode of the thirteenth transistor T13 is electrically connected to the fourth pull-down node P2, and the second electrode of the thirteenth transistor T13 is electrically connected to the first reference low-level signal terminal VSSQ. The channel length of the eleventh transistor T11 in the gate driving unit is smaller than the channel length of the eleventh transistor T11 in the redundant driving unit, and / or the channel length of the twelfth transistor T12 in the gate driving unit is smaller than the channel length of the twelfth transistor T12 in the redundant driving unit, and / or the channel length of the thirteenth transistor T13 in the gate driving unit is smaller than the channel length of the thirteenth transistor T13 in the redundant driving unit. Furthermore, the channel width-to-length ratios of the eleventh transistor T11, the twelfth transistor T12, and the thirteenth transistor T13 in the gate driving unit are equal to the channel width-to-length ratios of the eleventh transistor T11, the twelfth transistor T12, and the thirteenth transistor T13 in the redundant driving unit.

[0060] In the embodiment of the present application, the second pull-down maintaining module 103 further includes a fourteenth transistor T14, a fifteenth transistor T15 and a sixteenth transistor T16, the gate of the fourteenth transistor T14 is electrically connected to the fourth pull-down node P2, the first electrode of the fourteenth transistor T14 is electrically connected to the current-stage scan signal output terminal G (N-1, N, N+1...), the second electrode of the fourteenth transistor T14 is electrically connected to the second reference low-level signal terminal VSSG, the gate of the fifteenth transistor T15 is electrically connected to the fourth pull-down node P2, the first electrode of the fifteenth transistor T15 is electrically connected to the pull-up node Q, the second electrode of the fifteenth transistor T15 is electrically connected to the first reference low-level signal terminal VSSQ, the gate of the sixteenth transistor T16 is electrically connected to the fourth pull-down node P2, the first electrode of the sixteenth transistor T16 is electrically connected to the current-stage scan signal output terminal ST (N-1, N, N+1...), and the second electrode of the sixteenth transistor T16 is electrically connected to the first reference low-level signal terminal VSSQ. The channel lengths of the fourteenth transistor T14 and the fifteenth transistor T15 in the gate driving unit are both greater than the channel lengths of the fourteenth transistor T14 and the fifteenth transistor T15 in the redundant driving unit, and the channel width-to-length ratio of the fourteenth transistor T14 and the fifteenth transistor T15 in the gate driving unit is equal to the channel width-to-length ratio of the fourteenth transistor T14 and the fifteenth transistor T15 in the redundant driving unit.

[0061] In the embodiment of the present application, the channel length of the sixteenth transistor T16 in the gate driving unit is greater than or equal to the channel length of the sixteenth transistor T16 in the redundant driving unit, and the channel width-to-length ratio of the sixteenth transistor T16 in the gate driving unit is equal to the channel width-to-length ratio of the sixteenth transistor T16 in the redundant driving unit.

[0062] The working principle of the second pull-down maintaining module 103 of the virtual driving module in the gate driving circuit provided in the embodiment of the present application is the same as that of the first pull-down maintaining module 101, and the two work alternately, so the channel adjustment principle of the corresponding transistor in the second pull-down maintaining module 103 is not repeated.

[0063] As shown in FIG8 , the pull-up control module 104 includes a seventeenth transistor T17, the gate of which is electrically connected to the stage transmission signal terminal corresponding to the upper eight stages, a first electrode of which is electrically connected to the current-stage scan signal output terminal G(N−1, N, N+1, . . . ) corresponding to the upper eight stages, and a second electrode of which is electrically connected to the pull-up node Q. The reset module 105 includes an eighteenth transistor T18, the gate of which is electrically connected to the reset signal terminal Reset, the first electrode of which is electrically connected to the pull-up node Q, and the second electrode of which is electrically connected to the first reference low-level signal terminal VSSQ. The pull-down module 106 includes a nineteenth transistor T19 and a twentieth transistor T20, the gate of which is electrically connected to the stage transmission signal terminal corresponding to the lower eight stages, the first electrode of which is electrically connected to the pull-up node Q, and the second electrode of which is electrically connected to the first reference low-level signal terminal VSSQ. A gate of the twentieth transistor T20 is electrically connected to the stage transmission signal terminals corresponding to the eight lower stages, a first electrode of the twentieth transistor T20 is electrically connected to the scan signal output terminal G(N-1, N, N+1 . . . ) of the current stage, and a second electrode of the twentieth transistor T20 is electrically connected to the second reference low-level signal terminal VSSG.

[0064] The number of clock signals in the gate driving circuit provided in the embodiment of the present application is preferably 16CK, that is, it includes 8 levels of redundant driving units. As shown in Figure 8, the control end of the pull-down module 106 of the N-th level gate driving unit / redundant driving unit in the present application, that is, the gate of the nineteenth transistor T19 and the twentieth transistor T20, is connected to the level transmission signal ST (N+8).

[0065] As a specific embodiment of the present application, as shown in FIG9 , the gate driving unit includes a first pull-down maintaining module 101 , an output module 102 , a second pull-down maintaining module 103 , a pull-up control module 104 , a reset module 105 and a pull-down module 106 .

[0066] The first pull-down maintaining module 101 includes a first transistor T1, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a seventh transistor T7, an eighth transistor T8, and a ninth transistor T9. The gate of the first transistor T1 is electrically connected to the pull-up node Q, the first electrode of the first transistor T1 is electrically connected to the first pull-down node K1, and the second electrode of the first transistor T1 is electrically connected to the first reference low-level signal terminal VSSQ. The gate of the fourth transistor T4 and the first electrode of the fourth transistor T4 are electrically connected to the first control signal terminal, the second electrode of the fourth transistor T4 is electrically connected to the first pull-down node K1, the gate of the fifth transistor T5 is electrically connected to the first pull-down node K1, the first electrode of the fifth transistor T5 is electrically connected to the first control signal terminal, the second electrode of the fifth transistor T5 is electrically connected to the second pull-down node P1, the gate of the sixth transistor T6 is electrically connected to the pull-up node Q, the first electrode of the sixth transistor T6 is electrically connected to the second pull-down node P1, and the second electrode of the sixth transistor T6 is electrically connected to the first reference low-level signal terminal VSSQ. A gate of the seventh transistor T7 is electrically connected to the second pull-down node P1, a first electrode of the seventh transistor T7 is electrically connected to the scan signal output terminal G (N-1, N, N+1 . . . ) of the current stage, a second electrode of the seventh transistor T7 is electrically connected to the second reference low-level signal terminal VSSG, a gate of the eighth transistor T8 is electrically connected to the second pull-down node P1, a first electrode of the eighth transistor T8 is electrically connected to the pull-up node Q, a second electrode of the eighth transistor T8 is electrically connected to the first reference low-level signal terminal VSSQ, a gate of the ninth transistor T9 is electrically connected to the second pull-down node P1, a first electrode of the ninth transistor T9 is electrically connected to the scan signal output terminal ST (N-1, N, N+1 . . . ) of the current stage, and a second electrode of the ninth transistor T9 is electrically connected to the first reference low-level signal terminal VSSQ.

[0067] The output module 102 includes a second transistor T2, a third transistor T3, and a bootstrap capacitor. The gate of the second transistor T2 is electrically connected to a pull-up node Q, the first electrode of the second transistor T2 is electrically connected to the clock signal terminal CK, and the second electrode of the second transistor T2 is electrically connected to the current stage signal terminal ST(N-1, N, N+1...). The gate of the third transistor T3 is electrically connected to the pull-up node Q, the first electrode of the third transistor T3 is electrically connected to the clock signal terminal CK, and the second electrode of the third transistor T3 is electrically connected to the current stage scan signal output terminal G(N-1, N, N+1...). One end of the bootstrap capacitor is electrically connected to the pull-up node Q, and the other end of the bootstrap capacitor is electrically connected to the current stage scan signal output terminal G(N-1, N, N+1...).

[0068] The second pull-down maintaining module 103 includes a tenth transistor T10, an eleventh transistor T11, a twelfth transistor T12, a thirteenth transistor T13, a fourteenth transistor T14, a fifteenth transistor T15 and a sixteenth transistor T16, the gate of the tenth transistor T10 is electrically connected to the pull-up node Q, the first electrode of the tenth transistor T10 is electrically connected to the third pull-down node K2, and the second electrode of the tenth transistor T10 is electrically connected to the first reference low-level signal terminal VSSQ. A gate of the eleventh transistor T11 and a first electrode of the eleventh transistor T11 are electrically connected to the second control signal terminal, a second electrode of the eleventh transistor T11 is electrically connected to the third pull-down node K2, a gate of the twelfth transistor T12 is electrically connected to the third pull-down node K2, a first electrode of the twelfth transistor T12 is electrically connected to the second control signal terminal, a second electrode of the twelfth transistor T12 is electrically connected to the fourth pull-down node P2, a gate of the thirteenth transistor T13 is electrically connected to the pull-up node Q, a first electrode of the thirteenth transistor T13 is electrically connected to the fourth pull-down node P2, and a second electrode of the thirteenth transistor T13 is electrically connected to the first reference low-level signal terminal VSSQ. A gate of the fourteenth transistor T14 is electrically connected to the fourth pull-down node P2, a first electrode of the fourteenth transistor T14 is electrically connected to the scan signal output terminal G(N−1, N, N+1 . . . ) of the current stage, a second electrode of the fourteenth transistor T14 is electrically connected to the second reference low-level signal terminal VSSG, a gate of the fifteenth transistor T15 is electrically connected to the fourth pull-down node P2, a first electrode of the fifteenth transistor T15 is electrically connected to the pull-up node Q, a second electrode of the fifteenth transistor T15 is electrically connected to the first reference low-level signal terminal VSSQ, a gate of the sixteenth transistor T16 is electrically connected to the fourth pull-down node P2, a first electrode of the sixteenth transistor T16 is electrically connected to the scan signal output terminal ST(N−1, N, N+1 . . . ) of the current stage, and a second electrode of the sixteenth transistor T16 is electrically connected to the first reference low-level signal terminal VSSQ.

[0069] The pull-up control module 104 includes a seventeenth transistor T17, a gate of the seventeenth transistor T17 is electrically connected to the stage transmission signal terminal corresponding to the upper eight stages, a first electrode of the seventeenth transistor T17 is electrically connected to the current stage scan signal output terminal G (N-8) corresponding to the upper eight stages, and a second electrode of the seventeenth transistor T17 is electrically connected to the pull-up node Q.

[0070] The reset module 105 includes an eighteenth transistor T18, a gate of the eighteenth transistor T18 is electrically connected to the reset signal terminal Reset, a first electrode of the eighteenth transistor T18 is electrically connected to the pull-up node Q, and a second electrode of the eighteenth transistor T18 is electrically connected to the first reference low-level signal terminal VSSQ.

[0071] The pull-down module 106 includes a nineteenth transistor T19 and a twentieth transistor T20. The gate of the nineteenth transistor T19 is electrically connected to the stage transmission signal terminal corresponding to the next eight stages, the first electrode of the nineteenth transistor T19 is electrically connected to the pull-up node Q, and the second electrode of the nineteenth transistor T19 is electrically connected to the first reference low-level signal terminal VSSQ. The gate of the twentieth transistor T20 is electrically connected to the stage transmission signal terminal corresponding to the next eight stages, the first electrode of the twentieth transistor T20 is electrically connected to the scan signal output terminal G(N+8) of the current stage, and the second electrode of the twentieth transistor T20 is electrically connected to the second reference low-level signal terminal VSSG.

[0072] The channel lengths of the first transistor T1, the second transistor T2, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, the tenth transistor T10, the eleventh transistor T11, the twelfth transistor T12, and the thirteenth transistor T13 in the gate driving unit are all smaller than the channel lengths of the first transistor T1, the second transistor T2, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, the tenth transistor T10, the eleventh transistor T11, the twelfth transistor T12, and the thirteenth transistor T13 in the redundant driving unit. Moreover, the channel width-to-length ratios of the first transistor T1, the second transistor T2, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, the tenth transistor T10, the eleventh transistor T11, the twelfth transistor T12, and the thirteenth transistor T13 in the gate driving unit are equal to the channel width-to-length ratios of the first transistor T1, the second transistor T2, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, the tenth transistor T10, the eleventh transistor T11, the twelfth transistor T12, and the thirteenth transistor T13 in the redundant driving unit.

[0073] The channel lengths of the third transistor T3, the seventh transistor T7, the eighth transistor T8, the fourteenth transistor T14, and the fifteenth transistor T15 in the gate driving unit are all greater than the channel lengths of the third transistor T3, the seventh transistor T7, the eighth transistor T8, the fourteenth transistor T14, and the fifteenth transistor T15 in the redundant driving unit, and the channel width-to-length ratios of the third transistor T3, the seventh transistor T7, the eighth transistor T8, the fourteenth transistor T14, and the fifteenth transistor T15 in the gate driving unit are equal to the channel width-to-length ratios of the third transistor T3, the seventh transistor T7, the eighth transistor T8, the fourteenth transistor T14, and the fifteenth transistor T15 in the redundant driving unit.

[0074] It should be noted that the circuit structure of the gate driving unit is the same as the circuit structure of the redundant driving unit. The channel length of some transistors in the redundant driving unit is adjusted, and the channel width of the transistor is adjusted accordingly according to the adjusted channel length, so that the channel width-to-length ratio of the transistor remains unchanged.

[0075] Among them, the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, the seventh transistor T7, the eighth transistor T8, the ninth transistor T9, the tenth transistor T10, the eleventh transistor T11, the twelfth transistor T12, the thirteenth transistor T13, the fourteenth transistor T14, the fifteenth transistor T15, the sixteenth transistor T16, the seventeenth transistor T17, the eighteenth transistor T18, the nineteenth transistor T19, and the twentieth transistor T20 are all transistors of the same type, preferably, all P-type transistors.

[0076] On the other hand, the present application also provides a display panel, comprising a display area and a non-display area disposed around the display area, wherein the non-display area is provided with the aforementioned gate drive circuit, and the display area is provided with a plurality of pixel units, the gate drive circuit being electrically connected to the pixel units. It should be noted that a vertical alignment (VA) type liquid crystal display has advantages such as a wide viewing angle and high contrast, and the display panel in the present application is preferably a VA type display panel.

[0077] The above is a detailed introduction to a display panel and a preparation method thereof provided in an embodiment of the present application. The description of the above embodiment is only used to help understand the core idea of ​​the present application, and the content of this specification should not be understood as limiting the scope of protection of the present application.

Claims

1. A gate drive circuit, comprising: Multiple gate drive units; as well as Multiple virtual drive units; The gate driving unit and the virtual driving unit are cascaded, and both the gate driving unit and the virtual driving unit are used to output the current stage transmission signal, and the gate driving unit is also used to output the current stage scanning signal; The gate driving unit and the virtual driving unit both include a first pull-down maintaining module, the first pull-down maintaining module is electrically connected to the pull-up node, the first reference low-level signal terminal and the current-stage signal output terminal, and the first pull-down maintaining module is used to control the potential of the pull-up node and the current-stage signal output terminal; The first pull-down maintaining module includes a first transistor, a gate of the first transistor is electrically connected to the pull-up node, a first electrode of the first transistor is electrically connected to the first pull-down node, and a second electrode of the first transistor is electrically connected to the first reference low-level signal terminal; wherein, A channel length of the first transistor in the gate driving unit is smaller than a channel length of the first transistor in the dummy driving unit, and a channel width-to-length ratio of the first transistor in the gate driving unit is equal to a channel width-to-length ratio of the first transistor in the dummy driving unit.

2. The gate drive circuit according to claim 1, wherein: The gate driving unit and the virtual driving unit both include an output module, the output module is used to output the current level transmission signal, and the output module of the gate driving unit is also used to output the current level scanning signal; The output module includes a second transistor, a gate of the second transistor is electrically connected to the pull-up node, a first electrode of the second transistor is electrically connected to the clock signal terminal, and a second electrode of the second transistor is electrically connected to the stage transmission signal terminal; The channel length of the second transistor in the gate driving unit is smaller than the channel length of the second transistor in the dummy driving unit, and the channel width-to-length ratio of the second transistor in the gate driving unit is equal to the channel width-to-length ratio of the second transistor in the dummy driving unit.

3. The gate driving circuit according to claim 2, wherein: The output module further includes a third transistor and a bootstrap capacitor, wherein a gate of the third transistor is electrically connected to the pull-up node, a first electrode of the third transistor is electrically connected to the clock signal terminal, a second electrode of the third transistor is electrically connected to the current-stage scan signal output terminal, one end of the bootstrap capacitor is electrically connected to the pull-up node, and the other end of the bootstrap capacitor is electrically connected to the current-stage scan signal output terminal; The channel length of the third transistor in the gate driving unit is greater than the channel length of the third transistor in the dummy driving unit, and the channel width-to-length ratio of the third transistor in the gate driving unit is equal to the channel width-to-length ratio of the third transistor in the dummy driving unit.

4. The gate driving circuit according to claim 1, wherein: The first pull-down maintaining module further includes a fourth transistor, a fifth transistor and a sixth transistor, the gate of the fourth transistor and the first electrode of the fourth transistor are electrically connected to the first control signal terminal, the second electrode of the fourth transistor is electrically connected to the first pull-down node, the gate of the fifth transistor is electrically connected to the first pull-down node, the first electrode of the fifth transistor is electrically connected to the first control signal terminal, the second electrode of the fifth transistor is electrically connected to the second pull-down node, the gate of the sixth transistor is electrically connected to the pull-up node, the first electrode of the sixth transistor is electrically connected to the second pull-down node, and the second electrode of the sixth transistor is electrically connected to the first reference low-level signal terminal; The channel length of the fourth transistor in the gate driving unit is smaller than the channel length of the fourth transistor in the virtual driving unit, and / or the channel length of the fifth transistor in the gate driving unit is smaller than the channel length of the fifth transistor in the virtual driving unit, and / or the channel length of the sixth transistor in the gate driving unit is smaller than the channel length of the sixth transistor in the virtual driving unit; And the channel width-to-length ratio of the fourth transistor, the fifth transistor and the sixth transistor in the gate driving unit is equal to the channel width-to-length ratio of the fourth transistor, the fifth transistor and the sixth transistor in the dummy driving unit.

5. The gate driving circuit according to claim 4, wherein: The first pull-down maintaining module also includes a seventh transistor, an eighth transistor and a ninth transistor, the gate of the seventh transistor is electrically connected to the second pull-down node, the first electrode of the seventh transistor is electrically connected to the current scan signal output terminal, the second electrode of the seventh transistor is electrically connected to the second reference low level signal terminal, the gate of the eighth transistor is electrically connected to the second pull-down node, the first electrode of the eighth transistor is electrically connected to the pull-up node, the second electrode of the eighth transistor is electrically connected to the first reference low level signal terminal, the gate of the ninth transistor is electrically connected to the second pull-down node, the first electrode of the ninth transistor is electrically connected to the current scan signal output terminal, and the second electrode of the ninth transistor is electrically connected to the first reference low level signal terminal; The channel lengths of the seventh transistor and the eighth transistor in the gate driving unit are both greater than the channel lengths of the seventh transistor and the eighth transistor in the virtual driving unit, and the channel width-to-length ratio of the seventh transistor and the eighth transistor in the gate driving unit is equal to the channel width-to-length ratio of the seventh transistor and the eighth transistor in the virtual driving unit.

6. The gate driving circuit according to claim 5, wherein: The channel length of the ninth transistor in the gate driving unit is greater than or equal to the channel length of the ninth transistor in the virtual driving unit, and the channel width-to-length ratio of the ninth transistor in the gate driving unit is equal to the channel width-to-length ratio of the ninth transistor in the virtual driving unit.

7. The gate driving circuit according to claim 1, wherein: The gate driving unit and the virtual driving unit both include a second pull-down maintaining module, the second pull-down maintaining module is electrically connected to the pull-up node, the first reference low-level signal terminal and the current-stage signal output terminal, and the second pull-down maintaining module is used to control the potential of the pull-up node and the current-stage signal output terminal; The second pull-down maintaining module includes a tenth transistor, a gate of the tenth transistor is electrically connected to the pull-up node, a first electrode of the tenth transistor is electrically connected to the third pull-down node, and a second electrode of the tenth transistor is electrically connected to the first reference low-level signal terminal; The channel length of the tenth transistor in the gate driving unit is less than the channel length of the tenth transistor in the dummy driving unit, and the channel width-to-length ratio of the tenth transistor in the gate driving unit is equal to the channel width-to-length ratio of the tenth transistor in the dummy driving unit.

8. The gate driving circuit according to claim 7, wherein: The second pull-down maintaining module further includes an eleventh transistor, a twelfth transistor and a thirteenth transistor, the gate of the eleventh transistor and the first electrode of the eleventh transistor are electrically connected to the second control signal terminal, the second electrode of the eleventh transistor is electrically connected to the third pull-down node, the gate of the twelfth transistor is electrically connected to the third pull-down node, the first electrode of the twelfth transistor is electrically connected to the second control signal terminal, the second electrode of the twelfth transistor is electrically connected to the fourth pull-down node, the gate of the thirteenth transistor is electrically connected to the pull-up node, the first electrode of the thirteenth transistor is electrically connected to the fourth pull-down node, and the second electrode of the thirteenth transistor is electrically connected to the first reference low-level signal terminal; The channel length of the eleventh transistor in the gate driving unit is smaller than the channel length of the eleventh transistor in the virtual driving unit, and / or the channel length of the twelfth transistor in the gate driving unit is smaller than the channel length of the twelfth transistor in the virtual driving unit, and / or the channel length of the thirteenth transistor in the gate driving unit is smaller than the channel length of the thirteenth transistor in the virtual driving unit; And the channel width-to-length ratio of the eleventh transistor, the twelfth transistor and the thirteenth transistor in the gate driving unit is equal to the channel width-to-length ratio of the eleventh transistor, the twelfth transistor and the thirteenth transistor in the dummy driving unit.

9. The gate driving circuit according to claim 8, wherein: The second pull-down maintaining module also includes a fourteenth transistor, a fifteenth transistor and a sixteenth transistor, the gate of the fourteenth transistor is electrically connected to the fourth pull-down node, the first electrode of the fourteenth transistor is electrically connected to the current-stage scan signal output terminal, the second electrode of the fourteenth transistor is electrically connected to the second reference low-level signal terminal, the gate of the fifteenth transistor is electrically connected to the fourth pull-down node, the first electrode of the fifteenth transistor is electrically connected to the pull-up node, the second electrode of the fifteenth transistor is electrically connected to the first reference low-level signal terminal, the gate of the sixteenth transistor is electrically connected to the fourth pull-down node, the first electrode of the sixteenth transistor is electrically connected to the current-stage scan signal output terminal, and the second electrode of the sixteenth transistor is electrically connected to the first reference low-level signal terminal; The channel lengths of the fourteenth transistor and the fifteenth transistor in the gate driving unit are both greater than the channel lengths of the fourteenth transistor and the fifteenth transistor in the virtual driving unit, and the channel width-to-length ratio of the fourteenth transistor and the fifteenth transistor in the gate driving unit is equal to the channel width-to-length ratio of the fourteenth transistor and the fifteenth transistor in the virtual driving unit.

10. The gate driving circuit according to claim 9, wherein: A channel length of the sixteenth transistor in the gate driving unit is greater than or equal to a channel length of the sixteenth transistor in the virtual driving unit, and a channel width-to-length ratio of the sixteenth transistor in the gate driving unit is equal to the channel width-to-length ratio of the sixteenth transistor in the virtual driving unit.

11. A display panel comprising a display area and a non-display area arranged around the display area, wherein: The non-display area is provided with a gate driving circuit, and the gate driving circuit includes: a plurality of gate driving units; and Multiple virtual drive units; The gate driving unit and the virtual driving unit are cascaded, and both the gate driving unit and the virtual driving unit are used to output the current stage transmission signal, and the gate driving unit is also used to output the current stage scanning signal; The gate driving unit and the virtual driving unit both include a first pull-down maintaining module, the first pull-down maintaining module is electrically connected to the pull-up node, the first reference low-level signal terminal and the current-stage signal output terminal, and the first pull-down maintaining module is used to control the potential of the pull-up node and the current-stage signal output terminal; The first pull-down maintaining module includes a first transistor, a gate of the first transistor is electrically connected to the pull-up node, a first electrode of the first transistor is electrically connected to the first pull-down node, and a second electrode of the first transistor is electrically connected to the first reference low-level signal terminal; wherein, A channel length of the first transistor in the gate driving unit is smaller than a channel length of the first transistor in the dummy driving unit, and a channel width-to-length ratio of the first transistor in the gate driving unit is equal to a channel width-to-length ratio of the first transistor in the dummy driving unit.

12. The display panel according to claim 11, wherein: The gate driving unit and the virtual driving unit both include an output module, the output module is used to output the current level transmission signal, and the output module of the gate driving unit is also used to output the current level scanning signal; The output module includes a second transistor, a gate of the second transistor is electrically connected to the pull-up node, a first electrode of the second transistor is electrically connected to the clock signal terminal, and a second electrode of the second transistor is electrically connected to the stage transmission signal terminal; The channel length of the second transistor in the gate driving unit is smaller than the channel length of the second transistor in the dummy driving unit, and the channel width-to-length ratio of the second transistor in the gate driving unit is equal to the channel width-to-length ratio of the second transistor in the dummy driving unit.

13. The display panel according to claim 12, wherein: The output module further includes a third transistor and a bootstrap capacitor, wherein a gate of the third transistor is electrically connected to the pull-up node, a first electrode of the third transistor is electrically connected to the clock signal terminal, a second electrode of the third transistor is electrically connected to the current-stage scan signal output terminal, one end of the bootstrap capacitor is electrically connected to the pull-up node, and the other end of the bootstrap capacitor is electrically connected to the current-stage scan signal output terminal; The channel length of the third transistor in the gate driving unit is greater than the channel length of the third transistor in the dummy driving unit, and the channel width-to-length ratio of the third transistor in the gate driving unit is equal to the channel width-to-length ratio of the third transistor in the dummy driving unit.

14. The display panel according to claim 11, wherein: The first pull-down maintaining module further includes a fourth transistor, a fifth transistor and a sixth transistor, the gate of the fourth transistor and the first electrode of the fourth transistor are electrically connected to the first control signal terminal, the second electrode of the fourth transistor is electrically connected to the first pull-down node, the gate of the fifth transistor is electrically connected to the first pull-down node, the first electrode of the fifth transistor is electrically connected to the first control signal terminal, the second electrode of the fifth transistor is electrically connected to the second pull-down node, the gate of the sixth transistor is electrically connected to the pull-up node, the first electrode of the sixth transistor is electrically connected to the second pull-down node, and the second electrode of the sixth transistor is electrically connected to the first reference low-level signal terminal; The channel length of the fourth transistor in the gate driving unit is smaller than the channel length of the fourth transistor in the virtual driving unit, and / or the channel length of the fifth transistor in the gate driving unit is smaller than the channel length of the fifth transistor in the virtual driving unit, and / or the channel length of the sixth transistor in the gate driving unit is smaller than the channel length of the sixth transistor in the virtual driving unit; And the channel width-to-length ratio of the fourth transistor, the fifth transistor and the sixth transistor in the gate driving unit is equal to the channel width-to-length ratio of the fourth transistor, the fifth transistor and the sixth transistor in the dummy driving unit.

15. The display panel according to claim 14, wherein: The first pull-down maintaining module also includes a seventh transistor, an eighth transistor and a ninth transistor, the gate of the seventh transistor is electrically connected to the second pull-down node, the first electrode of the seventh transistor is electrically connected to the current scan signal output terminal, the second electrode of the seventh transistor is electrically connected to the second reference low level signal terminal, the gate of the eighth transistor is electrically connected to the second pull-down node, the first electrode of the eighth transistor is electrically connected to the pull-up node, the second electrode of the eighth transistor is electrically connected to the first reference low level signal terminal, the gate of the ninth transistor is electrically connected to the second pull-down node, the first electrode of the ninth transistor is electrically connected to the current scan signal output terminal, and the second electrode of the ninth transistor is electrically connected to the first reference low level signal terminal; The channel lengths of the seventh transistor and the eighth transistor in the gate driving unit are both greater than the channel lengths of the seventh transistor and the eighth transistor in the virtual driving unit, and the channel width-to-length ratio of the seventh transistor and the eighth transistor in the gate driving unit is equal to the channel width-to-length ratio of the seventh transistor and the eighth transistor in the virtual driving unit.

16. The display panel according to claim 15, wherein: The channel length of the ninth transistor in the gate driving unit is greater than or equal to the channel length of the ninth transistor in the virtual driving unit, and the channel width-to-length ratio of the ninth transistor in the gate driving unit is equal to the channel width-to-length ratio of the ninth transistor in the virtual driving unit.

17. The display panel according to claim 11, wherein: The gate driving unit and the virtual driving unit both include a second pull-down maintaining module, the second pull-down maintaining module is electrically connected to the pull-up node, the first reference low-level signal terminal and the current-stage signal output terminal, and the second pull-down maintaining module is used to control the potential of the pull-up node and the current-stage signal output terminal; The second pull-down maintaining module includes a tenth transistor, a gate of the tenth transistor is electrically connected to the pull-up node, a first electrode of the tenth transistor is electrically connected to the third pull-down node, and a second electrode of the tenth transistor is electrically connected to the first reference low-level signal terminal; The channel length of the tenth transistor in the gate driving unit is less than the channel length of the tenth transistor in the dummy driving unit, and the channel width-to-length ratio of the tenth transistor in the gate driving unit is equal to the channel width-to-length ratio of the tenth transistor in the dummy driving unit.

18. The display panel according to claim 17, wherein: The second pull-down maintaining module further includes an eleventh transistor, a twelfth transistor and a thirteenth transistor, the gate of the eleventh transistor and the first electrode of the eleventh transistor are electrically connected to the second control signal terminal, the second electrode of the eleventh transistor is electrically connected to the third pull-down node, the gate of the twelfth transistor is electrically connected to the third pull-down node, the first electrode of the twelfth transistor is electrically connected to the second control signal terminal, the second electrode of the twelfth transistor is electrically connected to the fourth pull-down node, the gate of the thirteenth transistor is electrically connected to the pull-up node, the first electrode of the thirteenth transistor is electrically connected to the fourth pull-down node, and the second electrode of the thirteenth transistor is electrically connected to the first reference low-level signal terminal; The channel length of the eleventh transistor in the gate driving unit is smaller than the channel length of the eleventh transistor in the virtual driving unit, and / or the channel length of the twelfth transistor in the gate driving unit is smaller than the channel length of the twelfth transistor in the virtual driving unit, and / or the channel length of the thirteenth transistor in the gate driving unit is smaller than the channel length of the thirteenth transistor in the virtual driving unit; And the channel width-to-length ratio of the eleventh transistor, the twelfth transistor and the thirteenth transistor in the gate driving unit is equal to the channel width-to-length ratio of the eleventh transistor, the twelfth transistor and the thirteenth transistor in the dummy driving unit.

19. The display panel according to claim 18, wherein: The second pull-down maintaining module also includes a fourteenth transistor, a fifteenth transistor and a sixteenth transistor, the gate of the fourteenth transistor is electrically connected to the fourth pull-down node, the first electrode of the fourteenth transistor is electrically connected to the current-stage scan signal output terminal, the second electrode of the fourteenth transistor is electrically connected to the second reference low-level signal terminal, the gate of the fifteenth transistor is electrically connected to the fourth pull-down node, the first electrode of the fifteenth transistor is electrically connected to the pull-up node, the second electrode of the fifteenth transistor is electrically connected to the first reference low-level signal terminal, the gate of the sixteenth transistor is electrically connected to the fourth pull-down node, the first electrode of the sixteenth transistor is electrically connected to the current-stage scan signal output terminal, and the second electrode of the sixteenth transistor is electrically connected to the first reference low-level signal terminal; The channel lengths of the fourteenth transistor and the fifteenth transistor in the gate driving unit are both greater than the channel lengths of the fourteenth transistor and the fifteenth transistor in the virtual driving unit, and the channel width-to-length ratio of the fourteenth transistor and the fifteenth transistor in the gate driving unit is equal to the channel width-to-length ratio of the fourteenth transistor and the fifteenth transistor in the virtual driving unit.

20. The display panel according to claim 19, wherein: A channel length of the sixteenth transistor in the gate driving unit is greater than or equal to a channel length of the sixteenth transistor in the virtual driving unit, and a channel width-to-length ratio of the sixteenth transistor in the gate driving unit is equal to the channel width-to-length ratio of the sixteenth transistor in the virtual driving unit.

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