Gate driving module and display panel

Abstract

A gate driving module (10) and a display panel (100). The gate driving module (10) comprises a plurality of cascaded gate driving circuits (20). Each gate driving circuit (20) comprises a stage-transmission unit (201), an output unit (202), a stage-transmission frequency division control unit (203), and an output frequency division control unit (204), wherein the stage-transmission frequency division control unit (203) controls, according to a signal of one of a first node (P) and a second node (Q) and a signal of a third node (S), a stage-transmission output unit (2012) to output the stage transmission signal of the present stage, and the output frequency division control unit (204) controls the signal of the third node (S) according to a frequency division control signal (FD), so as to control the output unit (202) to output the gate control signal of the present stage.

Description

Gate driver module and display panel Technical Field

[0001] The present application relates to the field of display technology, and in particular to a gate driving module and a display panel. Background Art

[0002] OLED (Organic Light-Emitting Diode) display panels are widely used due to their flexibility and other characteristics.

[0003] Among them, the gate drive circuit in the OLED display panel generally outputs effective pulses step by step to turn on multiple rows of sub-pixels in sequence. The refresh rate of the entire display area is the same, and it is impossible to use different refresh rates to drive different areas, resulting in limited usage scenarios.

[0004] Therefore, existing OLED display panels have the defect that different areas cannot achieve different refresh rates, which urgently needs to be improved. SUMMARY OF THE INVENTION

[0005] The present application provides a gate driving module and a display panel to achieve driving with different refresh rates for different areas.

[0006] An embodiment of the present application provides a gate driving module, comprising a frequency division signal line and a plurality of cascaded gate driving circuits, wherein the frequency division signal line is used to transmit a frequency division control signal to the plurality of gate driving circuits, and the gate driving circuits include:

[0007] a stage transmission unit, comprising a stage transmission receiving unit and a stage transmission output unit, wherein the stage transmission receiving unit is used to receive a stage transmission signal generated by the upper-stage gate driving circuit, and the stage transmission output unit is electrically connected to the stage transmission receiving unit through a first node and a second node, and is used to output the stage transmission signal of the current stage to the lower-stage gate driving circuit according to the signal of the first node and the signal of the second node;

[0008] an output unit electrically connected to the stage transmission output unit through the first node, one of the second node, and a third node, and configured to output a gate control signal according to a signal of the first node, one of the second node, and a signal of the third node; and

[0009] a stage transmission frequency division control unit, electrically connected to the stage transmission receiving unit via the first node or the second node, and electrically connected to the stage transmission output unit via a fourth node, configured to control a signal of one of the first node and the second node according to the frequency division control signal, so as to control the stage transmission output unit to output the stage transmission signal of the current stage;

[0010] An output frequency division control unit is connected between the first node, one of the second node and the third node, and is used to control the signal of the third node according to the frequency division control signal to control the output unit to output the gate control signal of this level. Beneficial effects

[0011] The present application provides a gate driver module and a display panel, comprising the above-mentioned frequency-dividing signal line and a plurality of cascaded gate driver circuits, wherein the gate driver circuit comprises the above-mentioned stage transmission unit and output unit. Furthermore, a stage transmission frequency-dividing control unit is provided, which is electrically connected to the stage transmission receiving unit via the first node or the second node (and is also electrically connected to the stage transmission output unit via the fourth node), and an output frequency-dividing control unit is provided, which is connected between one of the first node and the second node and the third node. The two control units are respectively configured to control the signal of one of the first node and the second node according to the frequency-dividing control signal to control the stage transmission output unit to output the stage transmission signal of the current stage, and to control the signal of the third node according to the frequency-dividing control signal to control the output unit to output the gate control signal of the current stage, so that the invalidation of the gate control signal does not affect the invalidation of the stage transmission signal. A sequential frequency reduction mode for multiple regions of the display panel can be achieved by setting whether the stage transmission signal has a stage transmission valid pulse, and an arbitrary frequency conversion mode for multiple regions of the display panel can be achieved by setting whether the gate control signal has a gate valid pulse (because the stage transmission valid pulse can always exist). BRIEF DESCRIPTION OF THE DRAWINGS

[0012] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present application. For those skilled in the art, other drawings can be obtained based on these drawings without creative work.

[0013] FIG1 is a schematic structural diagram of a gate drive module provided in an embodiment of the present application.

[0014] FIG2 and FIG3 are circuit diagrams of two gate drive circuits provided in embodiments of the present application, respectively.

[0015] 4 and 5 are schematic structural diagrams of display panels provided in embodiments of the present application.

[0016] 6 and 7 are circuit diagrams of pixel driving circuits provided in embodiments of the present application.

[0017] FIG8 and FIG9 are waveform diagrams of some signals in FIG6 and FIG7 respectively.

[0018] FIG10 is a waveform diagram of some signals in a single-stage gate drive circuit provided in an embodiment of the present application.

[0019] 11 to 16 are waveform diagrams of some signals in the multi-stage gate drive circuit provided in an embodiment of the present application.

[0020] FIG17 is a waveform diagram of a data signal transmitted on the same data line and two frequency-dividing control signals corresponding to two gate driving circuits. Modes for Carrying Out the Invention

[0021] The following will be combined with the accompanying drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the embodiments described are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without making creative efforts are within the scope of protection of this application.

[0022] In the description of this application, the terms "first", "second", etc. are used for descriptive purposes only and cannot be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Therefore, the features defined as "first" and "second" may explicitly or implicitly include one or more of the said features. In this article, no distinction is made between the source and drain of the transistor, and the two can be set interchangeably. The terms "low voltage" and "high voltage" represent two voltages with a relatively smaller voltage value and a relatively larger voltage value, and can represent two voltage values ​​of the same signal at different times, or two voltage values ​​of different signals at the same time or different times. In addition, it should be noted that the drawings only provide structures that are closely related to this application, and some details that are not closely related to the application are omitted. The purpose is to simplify the drawings so that the application points are clear at a glance, rather than to indicate that the actual device is exactly the same as the drawings, and it is not a limitation of the actual device.

[0023] References to "embodiments" herein mean that a particular feature, structure, or characteristic described in connection with the embodiments may be included in at least one embodiment of the present application. The appearance of the phrase at various times in the specification does not necessarily refer to the same embodiment, nor does it constitute an independent or alternative embodiment that is mutually exclusive of other embodiments. It is understood, both explicitly and implicitly, by those skilled in the art that the embodiments described herein may be combined with other embodiments.

[0024] The present application provides a gate driving module, which includes but is not limited to the following embodiments and combinations of the following embodiments.

[0025] In one embodiment, as shown in FIG1 , the gate driving module 10 includes a frequency division signal line FDL and a plurality of cascaded gate driving circuits 20, wherein the frequency division signal line FDL is used to transmit the frequency division control signal FD to the plurality of gate driving circuits 20. As shown in FIG2 and FIG3 , the gate driving circuit 20 includes: a level transmission unit 201, including a level transmission receiving unit 2011 and a level transmission output unit 2012, wherein the level transmission receiving unit 2011 is used to receive the level transmission signal generated by the upper-level gate driving circuit 20, and the level transmission output unit 2012 is electrically connected to the level transmission receiving unit 2011 through a first node P and a second node Q, and is used to output the level transmission signal of the current level to the lower-level gate driving circuit 20 according to the signal of the first node P and the signal of the second node Q; an output unit 202 is electrically connected to the first node P, the second node Q, and a third node S. connected to the stage transmission output unit 2012, and used to output the gate control signal of the current stage according to the signal of one of the first node P and the second node Q and the signal of the third node S; and a stage transmission frequency division control unit 203, electrically connected to the stage transmission receiving unit 2011 through the first node P or the second node Q, and electrically connected to the stage transmission output unit 2012 through a fourth node R, used to control the signal of one of the first node P and the second node Q according to the frequency division control signal FD, so as to control the stage transmission output unit 2012 to output the stage transmission signal of the current stage; an output frequency division control unit 204, connected between the first node P and the second node Q and the third node S, used to control the signal of the third node S according to the frequency division control signal FD, so as to control the output unit 202 to output the gate control signal of the current stage.

[0026] Specifically, FIG1 illustrates a cascade of n (n≥2) gate drive circuits 20 as an example. The first-stage gate drive circuit 2010 can use the first start signal STV1 or the second start signal STV2 (the two have opposite phases) as its corresponding "upper-stage gate control signal." The gate control signal Scan(1) outputted thereby is transmitted to the lower-stage (second-stage) gate drive circuit 20. Similarly, the n-stage gate drive circuit 20 can generate and output the gate control signal Scan(n) of the current stage (n-stage) based on the gate control signal Scan(n-1) of the (n-1)-stage. FIG2 and FIG3 illustrate an i-stage gate drive circuit 20 as an example. The i-stage gate drive circuit 20 can generate and output the gate control signal Scan(i) of the current stage (i-stage) based on the gate control signal Scan(i-1) of the (i-1)-stage.

[0027] It can be understood that, on the basis that the signal of one of the first node P and the second node Q electrically connected to the stage transmission output unit 2012 remains unchanged, on the one hand, in this embodiment, a stage transmission frequency division control unit 203 connected between the stage transmission receiving unit 2011 and the stage transmission output unit 2012 is provided, so that the signal of the other of the first node P and the second node Q can be controlled according to the frequency division control signal FD (whether it can be acted upon by the fourth node R), thereby controlling the signal transmitted to the stage transmission output unit 2012, and then determining the specific situation of the stage transmission signal output by the stage transmission output unit 2012 of the current stage (whether it has a stage transmission valid pulse) to determine whether to drive the next stage gate driving circuit 20. If the stage transmission signal has a stage transmission valid pulse, it can be considered that the stage transmission receiving unit 20 in the next stage gate driving circuit 20 is in a state of being driven by the stage transmission receiving unit 2011. 011 can work normally. Similarly, the specific situation of the level transmission signal output by the level transmission output unit 2012 of the level is determined in combination with the level transmission frequency division control unit 203 of the level. On the other hand, the present embodiment also provides an output frequency division control unit 204 connected between the first node P, one of the second node Q and the third node S to control the signal of the third node S according to the frequency division control signal FD, so as to control the specific situation (whether there is a gate effective pulse) of the gate control signal of the current level output by the output unit 202 (that is, the signal transmitted to the corresponding multiple sub-pixels Pi in the display panel to control whether the sub-pixels Pi are turned on) to decide whether to turn on the corresponding multiple sub-pixels Pi. If the gate control signal has a gate effective pulse, it can be considered that the corresponding multiple sub-pixels Pi can be refreshed for later light emission.

[0028] It should be understood that for multiple gate drive circuits 20 cascaded in sequence, if the multiple gate control signals output by the multiple gate drive circuits 20 of the first part all output a gate effective pulse once in one frame in every n1 frames, the multiple gate control signals output by the multiple gate drive circuits 20 of the second part all output a gate effective pulse once in one frame in every n2 frames, and the multiple gate control signals output by the multiple gate drive circuits 20 of the third part all output a gate effective pulse once in one frame in every n3 frames, then it can be considered that the three display areas respectively constituted by the three parts of sub-pixels Pi corresponding to these three parts of gate drive circuits 20 have three corresponding refresh rates of (1 / n1)*m, (1 / n2)*m, and (1 / n3)*m, where m is the least common multiple of n1, n1, and n1.

[0029] To sum up, in this embodiment, the gate control signal for determining the refresh rate of any display area of ​​the display panel is directly determined by the corresponding output frequency division unit and the frequency division control signal FD at this time. One input end of the output frequency division unit is connected to one of the first node P and the second node Q, and the other input end is connected to the third node S, wherein the third node S is connected to the first node P or the second node Q through the stage transmission frequency division unit, that is, it can be considered that the signal of the third node S is jointly determined by the stage transmission frequency division unit and the frequency division control signal FD loaded to the stage transmission frequency division unit, so the gate control signal is jointly determined by the stage transmission frequency division unit, the output frequency division unit, and the frequency division control signal FD loaded to the stage transmission frequency division unit and the output frequency division unit. The refresh rate of the corresponding display area can be determined by reasonably setting these three elements. Furthermore, the above three elements in the different multiple gate drive circuits 20 corresponding to different display areas of the display panel can be reasonably set to achieve different refresh rates respectively.

[0030] Among them, this embodiment does not limit whether the stage transmission frequency division units in different gate drive circuits 20 are set differently, whether the output frequency division units are set differently, and whether the time periods during which the frequency division control signals FD are respectively effective are set differently. To facilitate circuit design, the stage transmission frequency division units and the output frequency division units in the multi-stage gate drive circuit 20 can be set to be the same. Correspondingly, the time periods during which the frequency division control signals FD are respectively effective on different gate drive circuits 20 can be set differently to achieve differentiated settings of refresh rates in different display areas.

[0031] In one embodiment, as shown in Figures 1 to 3, the frequency division control signal FD includes a first frequency division control signal FD1 and a second frequency division control signal FD2, and the frequency division signal line FDL includes a first frequency division signal line FDL1 for transmitting the first frequency division control signal FD1 and a second frequency division signal line FDL2 for transmitting the second frequency division control signal FD2; wherein, the first frequency division signal line FDL is electrically connected to the output frequency division control unit 204 to control the signal of the third node S; wherein, the second frequency division signal line FDL is electrically connected to the stage transmission frequency division control unit 203 to control the signal of one of the first node P and the second node Q.

[0032] It can be understood that in this embodiment, by specifically setting the frequency division signal line FDL as an independent first frequency division signal line FDL and a first frequency division signal line FDL, independent first frequency division control signals FD1 and second frequency division control signals FD2 (which do not necessarily have to be the same) can be transmitted respectively to independently control the working states of the output frequency division control unit 204 and the stage transmission frequency division control unit 203, thereby respectively controlling the specific conditions of the stage transmission signal and the gate signal generated by the gate drive circuit 20 of this stage.

[0033] Specifically, the effective action period of the first frequency-dividing control signal FD1 corresponding to each stage of the gate driving circuit 20 and the effective action period of the second frequency-dividing control signal FD2 corresponding to each stage of the gate driving circuit 20 can be reasonably set to meet different situations. For each stage of the gate driving circuit 20, the following situations may be included but not limited to:

[0034] In case 1, the second frequency division control signal FD2 is properly set so that the signal of the fourth node R can act on the signal of the first node P or the signal of the second node Q, so that the level transmission signal generated and output by the level transmission frequency division control unit 203 has a level transmission effective pulse, thereby controlling the level transmission receiving unit 2011 in the next-stage gate driving circuit 20 to work normally;

[0035] Based on situation 1, the specific situations may include but are not limited to the following:

[0036] In case 1.1, the first frequency division control signal FD1 is properly set so that the gate control signal generated and output by the output frequency division unit has a gate effective pulse, thereby controlling the corresponding multiple sub-pixels Pi to turn on, that is, refreshing the corresponding multiple sub-pixels Pi for subsequent light emission;

[0037] Case 1.2: The first frequency division control signal FD1 is reasonably set so that the gate control signal generated and output by the output frequency division unit does not have a gate effective pulse, thereby controlling the corresponding multiple sub-pixels Pi not to turn on, that is, not refreshing the corresponding multiple sub-pixels Pi for later luminescence.

[0038] Furthermore, in case 1, if the time period of the effective action of the second frequency-division control signal FD2 corresponding to each level of the gate drive circuit 20 is set so that each level of the transmission signal has a level-transmission effective pulse, that is, each level of the transmission signal is uninterrupted, then at this time, the first frequency-division control signal FD1 can be set to control whether each level of the gate control signal has a gate effective pulse. Combined with the above discussion, arbitrary frequency division of multiple display areas can be achieved (the refresh rate of the latter display area can be increased or decreased compared with the former display area), that is, by controlling the relatively first and last levels of the gate control signals in one frame to have or not have gate effective pulses, or to have or not have gate effective pulses.

[0039] In case 2, the second frequency-division control signal FD2 is reasonably set so that the signal of the fourth node R cannot act on the signal of the first node P or the signal of the second node Q, so that the level transmission signal generated and output by the level transmission frequency-division control unit 203 does not have a level transmission valid pulse (determined by the signal of the first node P or the signal of the second node Q), thereby controlling the level transmission receiving unit 2011 in the next-level gate driving circuit 20 to not work normally. At the same time, since the signal of the third node S connected to the source of the output unit 202 is also determined by the signal of the first node P or the signal of the second node Q, it can also be considered here that the signal of the third node S at this time will also cause the gate control signal of this level to have no gate valid pulse. Therefore, it can be considered that the gate control signal from the current level to the last level does not have a gate valid pulse, and the corresponding multiple sub-pixels Pi cannot be refreshed for later light emission. Combined with the above discussion, only frequency reduction of multiple display areas can be achieved.

[0040] Case 3: The first frequency division control signal FD1 is properly set so that the output frequency division control unit 204 can control the third node S to be acted upon by the first node P or the second node Q, thereby enabling the output unit 202 to be acted upon by the first node P or the second node Q.

[0041] Based on situation 3, it may include but is not limited to the following situations:

[0042] In case 3.1, the second frequency-division control signal FD2 is reasonably set so that the signal at the fourth node R can act on the signal at the first node P or the signal at the second node Q, so that the level transmission signal generated and output by the level transmission frequency-division control unit 203 has a level transmission effective pulse, thereby controlling the level transmission receiving unit 2011 in the next-stage gate driving circuit 20 to operate normally. Since the signal at the first node P or the signal at the second node Q can also act on the third node S to act on the output unit 202, the gate control signal generated and output by the output frequency-division unit also has a gate effective pulse, thereby controlling the corresponding multiple sub-pixels Pi to turn on, that is, refreshing the corresponding multiple sub-pixels Pi for subsequent light emission.

[0043] In case 3.2, the second frequency-division control signal FD2 is properly set so that the signal at the fourth node R can act on the signal at the first node P or the signal at the second node Q, so that the stage-transmission signal generated and output by the stage-transmission frequency-division control unit 203 does not have a stage-transmission valid pulse. Similarly, as can be seen in "case 2", the signal at the first node P or the signal at the second node Q cannot invalidate the signal at the third node S, which also causes the gate control signal of the current stage to have no gate-valid pulse. Therefore, it can be considered that the gate control signal from the current stage to the last stage has no gate-valid pulse, and the corresponding multiple sub-pixels Pi cannot be refreshed for subsequent light emission.

[0044] Furthermore, in Case 3, if the first frequency-division control signal FD1 is set to the effective action period corresponding to each level of the gate drive circuit 20 so that the third node S of each level is acted upon by the first node P or the second node Q, then at this time, the second frequency-division control signal FD2 can be set to control whether the signal of the fourth node R acts on the signal of the first node P or the signal of the second node Q, so as to control whether the level transfer signal generated and output by each level transfer frequency-division control unit 203 has a level transfer effective pulse. Combined with the above discussion, frequency reduction of multiple display areas can be achieved.

[0045] Case 4: The first frequency division control signal FD1 is reasonably set so that the output frequency division control unit 204 cannot control the third node S to be affected by the first node P or the second node Q, and thus the output unit 202 cannot be affected by the first node P or the second node Q. That is, no matter what the signal of the first node P and the signal of the second node Q are, the first frequency division control signal FD1 will act on the output frequency division control unit 204, so that the signal of the third node S will cause the gate control signal of this stage to have no gate effective pulse. Therefore, it can be considered that the gate control signal from the current stage to the last stage has no gate effective pulse, and the corresponding multiple sub-pixels Pi cannot be refreshed for later light emission. Combined with the above discussion, only frequency reduction of multiple display areas can be achieved.

[0046] In one embodiment, as shown in Figures 1 to 3, the output frequency division control unit 204 includes: a first frequency division transistor T18, the gate of the first frequency division transistor T18 is connected to the first frequency division signal line FDL, the source of the first frequency division transistor T18 is electrically connected to the first node P or the second node Q, and the drain of the control transistor is electrically connected to the third node S; wherein, the first frequency division control signal FD1 is used to control the third node S to be electrically connected or disconnected with the first node P or the second node Q.

[0047] In combination with the above discussion, it can be seen that the first frequency division control signal FD1 can act on the output frequency division control unit 204 to control whether the third node S is affected by the first node P or the second node Q. Furthermore, this embodiment illustrates that the first frequency division control signal FD1 can act on the gate of the first frequency division transistor T18 in the output frequency division control unit 204 to control whether the third node S is electrically connected or disconnected with the first node P or the second node Q.

[0048] Specifically, if electrically connected, it can be considered that the third node S can be affected by the first node P or the second node Q, which is equivalent to the signal of the first node P or the signal of the second node Q can control whether the gate control signal generated and output by the output unit 202 has a gate effective pulse (that is, the above-mentioned situation 3); if disconnected, it can be considered that the third node S cannot be affected by the first node P or the second node Q. Since the first node P or the second node Q used to control the generation of the level transfer signal cannot act on the output unit 202, it can be considered that the gate control signal generated and output by the output unit 202 does not have a gate effective pulse (that is, the above-mentioned situation 4).

[0049] In one embodiment, as shown in Figures 1 to 3, the output frequency division control unit 204 further includes: a second frequency division transistor T20, the gate of the second frequency division transistor T20 is electrically connected to the fifth node of the stage transmission unit 201, the source of the second frequency division transistor T20 is electrically connected to the first frequency division signal line FDL, and the drain of the second frequency division transistor T20 is electrically connected to the gate of the first frequency division transistor T18; wherein, the first frequency division control signal FD1 and the signal of the fifth node are used to control the electrical connection or disconnection of the third node S with the first node P or the second node Q; wherein, the signal of the fifth node is also used to control the stage transmission signal and the gate control signal output by the gate drive circuit 20 of this stage.

[0050] It can be understood that in this embodiment, a second frequency-dividing transistor T20 is further provided which is electrically connected to the gate of the first frequency-dividing transistor T18, and the turning-on condition of the second frequency-dividing transistor T20 is determined by the signal of the fifth node, and the signal of the fifth node is also used to control the stage transmission signal and the gate control signal output by this stage, that is, it can be considered that the state of the signal of the fifth node can feedback the states of both the stage transmission signal and the gate control signal of this stage, so as to ensure that the turning-on of the second frequency-dividing transistor T20 is controlled only when the states of both the stage transmission signal and the gate control signal generated by this stage are appropriate, thereby allowing the first frequency-dividing control signal FD1 to be transmitted to the gate of the first frequency-dividing transistor T18 of this stage to control the turning-on condition of the first frequency-dividing transistor T18, and taking into account the premise that the stage transmission signal and the gate control signal output of each stage are correct waveforms, so as to achieve differentiated settings of the refresh rates of different display areas.

[0051] It should be noted that, in this embodiment, the specific connection relationship between the fifth node and the above-mentioned module is not limited. It is only necessary to meet the above-mentioned limitation that "the signal of the fifth node is also used to control the stage transmission signal and the gate control signal output by the gate drive circuit 20 of this stage". For example, the fifth node can be electrically connected to the first node P or the second node Q, or even the fifth node can be the first node P or the second node Q. In this application, the fifth node is taken as the node D as an example for explanation (based on the fact that the second frequency dividing transistor T20 in Figures 2 and 3 are P-type transistors and N-type transistors respectively, both of which can refer to the analysis of Figure 10 later).

[0052] Specifically, in combination with the analysis of Figures 2 and 10 below, it can be seen that based on the fact that the stage-transmitting signal generated by this stage has a stage-transmitting valid pulse (that is, the signal of the first node P and the signal of the second node Q are both valid signals), if the gate control signal of this stage needs to output a gate-valid pulse, it can be considered that the voltage in the signal of the fifth node that can ensure that the gate-valid pulse of this stage is completely output (for example, the end point of the fifth stage t5 in Figure 10) can be used to control the first frequency-dividing control signal FD1 to be transmitted to the gate of the first frequency-dividing transistor T18 of this stage. For example, if the second frequency-dividing transistor T20 is a P-type transistor, it can be considered that the voltage of the fifth node is a higher voltage and a lower voltage before and after the time node when the gate-valid pulse of this stage is completely output, respectively, to ensure that the second frequency-dividing transistor T20 is turned on only after the gate-valid pulse of this stage is completely output.

[0053] In particular, if the gate control signal of this stage does not need to output a gate effective pulse, combined with the above discussion, it can be seen that the starting point (voltage jump) of the effective action period of the first frequency-divided control signal FD1 corresponding to this stage can be set before the moment when the voltage corresponding to the start of output of the gate effective pulse of this stage appears in the signal of the fifth node (for example, the starting point t3 of the third stage in Figure 10), so as to ensure that the electrical connection between the third node S and the first node P or the second node Q is cut off before the gate effective pulse of this stage is output.

[0054] In one embodiment, as shown in Figures 1 to 3, the stage transmission frequency division control unit 203 includes: a third frequency division transistor T17, the gate of the third frequency division transistor T17 is electrically connected to the second frequency division signal line FDL, the source of the first frequency division transistor T18 is electrically connected to the stage transmission receiving unit 2011 through the fourth node R, and the drain of the third frequency division transistor T17 is electrically connected to the first node P or the second node Q; wherein the second frequency division control signal FD2 is used to control the fourth node R to be electrically connected or disconnected with the first node P or the second node Q.

[0055] Among them, combined with the above discussion, it can be seen that the second frequency division control signal FD2 can act on the stage transmission frequency division control unit 203 to control whether the first node P or the second node Q is affected by the fourth node R. Furthermore, this embodiment describes that the second frequency division control signal FD2 can act on the gate of the third frequency division transistor T17 in the stage transmission frequency division control unit 203 to control the fourth node R to be electrically connected or disconnected with the first node P or the second node Q.

[0056] Specifically, if they are electrically connected, it can be considered that the first node P or the second node Q can be affected by the fourth node R, which is equivalent to the signal of the fourth node R being able to control whether the level transmission signal generated and output by the level transmission output unit 2012 has a level transmission valid pulse (i.e., the above-mentioned situation 1); if they are disconnected, it can be considered that the first node P or the second node Q cannot be affected by the fourth node R. Since the fourth node R used to control the level transmission signal generated by this level cannot act on the level transmission output unit 2012, it can be considered that the level transmission signal generated and output by the level transmission output unit 2012 does not have a level transmission valid pulse (i.e., the above-mentioned situation 2).

[0057] In one embodiment, as shown in Figures 2 and 3, the stage transfer-out unit 2012 includes: a first-stage transfer-out transistor T10, wherein the gate of the first-stage transfer-out transistor T10 is electrically connected to the first node P, the source of the first-stage transfer-out transistor T10 is electrically connected to a first voltage line to apply a first voltage VGH, and the drain of the first-stage transfer-out transistor T10 is electrically connected to a stage transfer-out terminal OUT in the gate driving circuit 20 for outputting the stage transfer signal; and a second-stage transfer-out transistor T9, wherein the gate of the second-stage transfer-out transistor T9 is electrically connected to the second node Q, the source of the second-stage transfer-out transistor T9 is electrically connected to a second voltage line to apply a second voltage VGL, and the drain of the second-stage transfer-out transistor T9 is electrically connected to the stage transfer-out terminal OUT.

[0058] Specifically, the first node P can control the activation of the first-stage transmission output transistor T10 to control whether the first voltage can be transmitted to the stage transmission output terminal OUT, and the second node Q can control the activation of the second-stage transmission output transistor T9 to control whether the second voltage can be transmitted to the stage transmission output terminal OUT. In combination with the above discussion, it can be seen that in the present application, by providing a third frequency-dividing transistor T17 connected between the fourth node R and the first node P or the second node Q to control whether the first node P or the second node Q can receive the signal of the fourth node R, the activation of the first output transistor T22 or the activation of the second output transistor T21 is controlled, thereby controlling the specific situation of the stage transmission signal generated and output by the stage transmission output terminal OUT.

[0059] For example, when the first-stage transmission output transistor T10 is turned on and the second-stage transmission output transistor T9 is turned off, the gate control signal can be equal to the first voltage; for another example, when the first-stage transmission output transistor T10 is turned off and the second-stage transmission output transistor T9 is turned on, the generated stage transmission signal can be equal to the second voltage; for another example, when both are turned off, the generated stage transmission signal can be equal to the previous voltage; for another example, when both are turned on, the generated stage transmission signal can be between the first voltage and the second voltage.

[0060] In one embodiment, as shown in Figures 2 and 3, the output unit 202 includes: a first output transistor T22, wherein the gate of the first output transistor T22 is electrically connected to the third node S, the source of the first output transistor T22 is electrically connected to the first voltage line, and the drain of the first output transistor T22 is electrically connected to the gate output terminal OUTA in the gate driving circuit 20 for outputting the gate control signal; and a second output transistor T21, wherein the gate of the second output transistor T21 is electrically connected to the first node P or the second node Q, the source of the second output transistor T21 is electrically connected to the second voltage line, and the drain of the second output transistor T21 is electrically connected to the gate output terminal OUTA.

[0061] Similarly, as discussed above, the third node S can control the activation of the first output transistor T22 to control whether the first voltage can be transmitted to the gate output terminal OUTA, and the first node P or the second node Q can control the activation of the second output transistor T21 to control whether the second voltage can be transmitted to the gate output terminal OUTA. In combination with the above discussion, it can be seen that in the present application, a first frequency-dividing transistor T18 connected between the third node S and the first node P or the second node Q is provided to control whether the third node S can receive the signal from the first node P or the second node Q, thereby controlling the activation of the first output transistor T22 or the activation of the second output transistor T21, thereby controlling the specific conditions of the gate control signal generated and output by the gate output terminal OUTA.

[0062] In one embodiment, the gate driving circuit 20 is electrically connected to at least one corresponding pixel driving circuit 302, the gate output terminal OUTA is electrically connected to the corresponding pixel transistor in each of the pixel driving circuits 302, and the first voltage is greater than the second voltage; wherein, as shown in FIG2 , the pixel transistor is an N-type transistor, the drain of the third frequency-dividing transistor T17 and the source of the first frequency-dividing control transistor are both electrically connected to the first node P (in this case, the gate driving circuit 20 can be considered as an i-th stage NScan circuit, and the gate control signal generated is NSca no(i) signal, the level transmission signal is NScan(i) signal, and the level transmission signal of the previous level is NScan(i-1) signal); or, as shown in Figure 3, the pixel transistor is a P-type transistor, the drain of the third frequency-dividing transistor T17 and the source of the first frequency-dividing control transistor are both electrically connected to the second node Q (in this case, the gate drive circuit 20 can be considered to be the i-th level PScan circuit, the gate control signal generated is the PScano(i) signal, the level transmission signal is the PScan(i) signal, and the level transmission signal of the previous level is the PScan(i-1) signal).

[0063] In this embodiment, the structure of the pixel driving circuit 302 is not limited. It can be considered that the pixel transistor K can control the opening state of the corresponding sub-pixel Pi under the control of the gate control signal output by the gate driving circuit 20. Specifically, in this embodiment, based on the fact that the first voltage is greater than the second voltage, when the pixel transistor is an N-type transistor, the drain of the third frequency-dividing transistor T17 and the source of the first frequency-dividing control transistor are both electrically connected to the first node P, so that the turn-on status of both the first-stage transmission transistor T10 and the first output transistor T22 can be controlled to control whether the larger first voltage (which can be the effective voltage of the N-type transistor) can be transmitted to the gate of the N-type pixel transistor, thereby controlling whether the corresponding sub-pixel Pi is turned on; when the pixel transistor is a P-type transistor, the drain of the third frequency-dividing transistor T17 and the source of the first frequency-dividing control transistor are both electrically connected to the second node Q, thereby controlling the turn-on status of the second-stage transmission transistor T9 and the second output transistor T21 to control whether the smaller second voltage (which can be the effective voltage of the P-type transistor) can be transmitted to the gate of the P-type pixel transistor, thereby controlling whether the corresponding sub-pixel Pi is turned on.

[0064] According to the above discussion, if the duration of the effective voltage required to turn on the N-type or P-type pixel transistor is equal, it can be considered that in the NScano signal and PScan signal output by the NScan circuit and the PScan circuit respectively, the voltage value of the gate effective pulse of the former (for example, but not limited to being equal to the first voltage) is greater than the voltage value of the gate effective pulse of the latter (for example, but not limited to being equal to the second voltage), and the pulse width of the gate effective pulses of the two can be equal.

[0065] Furthermore, since the level transmission receiving unit 2011 can receive the level transmission signal generated by the upper level, according to the level transmission function of the level transmission signal, the first start signal STV1 and the second start signal STV2 respectively loaded to the NScan circuit of the first level and the PScan circuit of the first level can also be obtained by shifting the level transmission signals (NScan(1), PScan(1)) generated by the respective first-level gate driving circuits 20 by the same distance along the negative direction of the time axis, that is, the voltage values ​​of the effective level transmission pulses of the two can be equal to the first voltage and the second voltage, respectively. Among them, the first start signal STV1, the second start signal STV2, the NScano signal, the PScano signal, the NScan signal, and the PScan signal can all be periodic signals.

[0066] In one embodiment, as shown in Figures 2 and 3, the stage transmission receiving unit 2011 includes: a fourth node control unit 20111, which is electrically connected to the clock signal line (including but not limited to the first clock signal line CKL1 and the second clock signal line CKL2, the first clock signal XCK and the second clock signal line CKL2CK respectively loaded on the two can be symmetrical about the time axis, and the voltage value of the intersection of the time axis and the voltage axis is not limited here, and both can include two different voltage values) and the fourth node R, and is used to control the signal of the fourth node R according to the clock signal transmitted by the clock signal line; a second node control unit 20112 (as shown in Figure 2) or a first node control unit 20113 (as shown in Figure 3), and the second node control unit 2011 2 is electrically connected to the clock signal line and the second node Q, and is used to control the signal of the second node Q according to the clock signal. The first node control unit 20113 is electrically connected to the clock signal line and the first node P, and is used to control the signal of the one node according to the clock signal; an input unit 20114, the input end of the input unit 20114 is electrically connected to the gate drive circuit 20 of the upper level to load the stage transmission signal generated by the gate drive circuit 20 of the upper level, and the output end of the input unit 20114 is electrically connected to the fourth node control unit 20111 and the second node control unit 20112, or is electrically connected to the fourth node control unit 20111 and the first node control unit 20113.

[0067] It should be noted that, for the sake of ease of description, in the present application, the schematic diagram only takes the second-stage transmission transistor T9 as an example, that is, the second node Q is located below the first node P (that is, the second output transistor T21 is located below the first output transistor T22). In fact, the present application protects the connection relationship of multiple electronic devices and is not limited to the positional relationship. Based on the input unit 20114 loading the level transmission signal generated by the upper gate drive circuit 20, as shown in FIG2 , for the NScan circuit, since the level transmission frequency division control unit 203 is connected to the first node P located above, it can be considered that the fourth node R is also set above. At this time, it can be considered that the fourth node control unit 203 also needs to be set close to the top. The control unit 20111 is used to control the voltage of the fourth node R (further combined with the stage transmission and frequency division control unit 203 to control the voltage of the first node P), and the voltage of the second node Q needs to be controlled by the second node control unit 20112 set near the bottom; as shown in Figure 3, for the PScan circuit, since the stage transmission and frequency division control unit 203 is connected to the second node Q located at the bottom, it can be considered that the fourth node R is also set at the bottom. At this time, it can be considered that the fourth node control unit 20111 also needs to be set near the bottom to control the voltage of the fourth node R (further combined with the stage transmission and frequency division control unit 203 to control the voltage of the second node Q), and the voltage of the first node P needs to be controlled by the first node control unit 20113 set near the top.

[0068] In one embodiment, as shown in FIG2 , the stage frequency division control unit 203 and the output frequency division control unit 204 are both electrically connected to the first node P (i.e., the gate drive circuit 20 is an NScan circuit for example); the input unit 20114 includes an input transistor T3, the gate of the input transistor T3 is loaded with the clock signal (for example, connected to the first clock signal line CKL1 to load the first clock signal), the source of the input transistor T3 is configured as the input end of the input unit 20114, and the drain of the input transistor T3 is configured as the input end of the input unit 20 114 output terminal; the fourth node control unit 20111 includes a first transistor T4, a seventh transistor T5, a second transistor T6 and a third transistor T7 arranged in series, the gate of the seventh transistor T5 is electrically connected to the drain of the input transistor T3, the source of the seventh transistor T5 is loaded with the clock signal (for example, the first clock signal), the gate of the first transistor T4 is loaded with the clock signal (for example, the first clock signal), the source of the first transistor T4 is loaded with the second voltage, and the drain of the first transistor T4 is electrically connected to the gate of the second transistor T6 and the drain of the seventh transistor T5, the drain of the second transistor T6 is electrically connected to the source of the third transistor T7, the source of the second transistor T6 and the gate of the third transistor T7 are both loaded with the clock signal, and the drain of the third transistor T7 is electrically connected to the fourth node R; the second node control unit 20112 includes a fourth transistor T13, a first capacitor C1, a fifth transistor T1 and a sixth transistor T2 arranged in series, the gate of the fourth transistor T13 (electrically connected to the control line CL) is loaded with a control signal, and the source of the fourth transistor T13 is loaded with the clock signal. The fourth transistor T13 is electrically connected to the second node Q, the gate of the fifth transistor T1 is electrically connected to the drain of the first transistor T4, the source of the fifth transistor T1 is loaded with the first voltage, the drain of the fifth transistor T1 is electrically connected to the source of the sixth transistor T2, the drain of the sixth transistor T2 is loaded with the clock signal, and the gate of the sixth transistor T2 is also loaded with the stage transmission signal generated by the upper gate driving circuit 20, and the first capacitor C1 is electrically connected between the gate and drain of the sixth transistor T2.

[0069] In this application, the transistors in the gate drive circuit 20 are all P-type transistors as an example, and the operation of some signals in some states is explained: at startup, the control signal transmitted by CL can control the fourth transistor T13 to turn on to transmit the first voltage to the second node Q; later, when the voltage in the first clock signal is low and the voltage in the (i-1)-th stage gate control signal NScano(i-1) is low, the gate control signal NScano(i-1) controls both the seventh transistor T5 and the second output transistor T21 to turn on, and the second voltage is transmitted to the stage transmission output terminal OUT through the second output transistor T21, and the first clock signal controls the first transistor T4 to turn on, and the second voltage is transmitted to the gate of the second transistor T6 to control it to turn on. At this time, the high voltage in the second clock signal controls the third transistor T7 to turn off; later, when the voltage in the first clock signal is high, the input transistor T3, the second transistor T6 and the first transistor T4 are turned off. At this time, it can be considered that the second output transistor T21 remains on, the low voltage in the second clock signal controls the third transistor T7 to turn on, the fourth node R is still not loaded with voltage, and the stage transmission output terminal OUT still outputs the second voltage.

[0070] It should be noted that the present application does not limit the type of each transistor in the gate drive circuit 20. For example, they may all be P-type transistors, or some may be N-type transistors and the other part may be P-type transistors. The corresponding signals may also be matched and set according to the type of transistor. For details, please refer to the full text for the principle explanation of "all transistors in the gate drive circuit 20 are P-type transistors".

[0071] Furthermore, the fourth node control unit 20111 may further include an eighth transistor T11 and a second capacitor C2, the second node control unit 20112 may further include a ninth transistor T12, the stage transmission output unit 2012 may further include a third capacitor C3 electrically connected between the gate and source of the first output transistor T22, the gate of the eighth transistor T11 and the gate of the ninth transistor T12 may both be loaded with a second voltage to maintain opening, the source and drain of the eighth transistor T11 are respectively electrically connected to the drain of the first transistor T4 and the gate of the second transistor T6, the second capacitor C2 is electrically connected between the gate and the drain of the second transistor T6, and the source and drain of the ninth transistor T12 are respectively electrically connected to the drain of the input transistor T3 and the second node Q.

[0072] Among them, the first capacitor C1, the second capacitor C2 and the third capacitor C3 can be used to maintain the voltage of the corresponding nodes and play a coupling role. The eighth transistor T11 and the ninth transistor T12 can respectively ensure that they are turned on only when the source voltage of both is low enough to maintain a low voltage at their drains, which is beneficial to the turning on of the first output transistor T22 and the second output transistor T21.

[0073] In one embodiment, as shown in FIG2 , the second node control unit 20112 further includes: a tenth transistor T14, wherein a source of the tenth transistor T14 is loaded with the stage transmission signal generated by the upper-stage gate driving circuit 20, a gate of the tenth transistor T14 is loaded with the clock signal (first clock signal), and a drain of the tenth transistor T14 is electrically connected to the gate of the sixth transistor T2; an eleventh transistor T16, wherein both a gate and a source of the eleventh transistor T16 are electrically connected to the gate of the sixth transistor T2, and a drain of the eleventh transistor T16 is electrically connected to the second node Q. Similarly, a twelfth transistor T15 may be provided for maintaining a low voltage on the gate of the sixth transistor T2; a gate of the twelfth transistor T15 may be loaded with a second voltage, and a source and a drain of the twelfth transistor T15 may be electrically connected to the drain of the tenth transistor T14 and the gate of the sixth transistor T2, respectively.

[0074] It can be understood that in this embodiment, the second node control unit 20112 is further provided with the above-mentioned tenth transistor T14 and eleventh transistor T16. The tenth transistor T14 can be used to control the voltage of the gate of the sixth transistor T2. Further, by providing the eleventh transistor T16 connected between the second node Q and the gate of the sixth transistor T2, the second node Q is not directly electrically connected to the first capacitor C1 to avoid being coupled by the first capacitor C1, and the second node Q can be maintained at a lower voltage.

[0075] It should be noted that, as can be seen from a comparison of FIG. 3 and FIG. 2 , the PScan circuit differs from the NScan circuit in one respect, namely, the difference between the second start signal STV2 and the first start signal STV1 discussed above. The specific structures of the input unit 20114 and the output unit 202 of the two circuits can be the same. Another difference is that the NScan circuit requires a fourth node control unit 20111 and a second node control unit 20112, while the PScan circuit requires a fourth node control unit 20111 and a first node control unit 20113. The specific structure of the fourth node control unit 20111 in the NScan circuit can be the same as that of the first node control unit 20113 in the PScan circuit, except that the output of the former is connected to the first node P via the stage transmission and frequency division control unit 203, while the output of the latter is directly connected to the first node P. Similarly, the specific structure of the second node control unit 20112 in the NScan circuit can be the same as that of the third node S control unit in the PScan circuit, except that the output of the former is directly connected to the second node Q, while the output of the latter is connected to the second node Q via the stage transmission and frequency division control unit 203.

[0076] Furthermore, the gate drive circuit 20 in the present application can also be but not limited to an EM circuit. The difference between the EM circuit and the NScan circuit is that the first start signal STV1 is replaced by the third start signal STV3. The third start signal STV3 can be understood as the first start signal STV1 being shifted a certain distance along the negative or positive direction of the time axis, and the waveforms of the two do not overlap. Similarly, the third start signal STV3 can also be a periodic signal.

[0077] The present application provides a display panel, which includes but is not limited to the following embodiments and combinations of the following embodiments.

[0078] In one embodiment, in combination with Figures 4 to 7, the display panel 100 includes: a gate driving module 10 as described in any one of the above; a panel body 30, including a plurality of sub-pixels Pi and a plurality of scanning lines SL, the plurality of sub-pixels Pi including a light-emitting device 301 and a pixel driving circuit 302 for driving the light-emitting device 301 to emit light, the pixel driving circuit 302 including at least one transistor (i.e., the pixel transistor discussed above); wherein the gate control signal output by the gate driving circuit 20 is transmitted to the gates of the plurality of transistors in the corresponding plurality of pixel driving circuits 302 via the corresponding scanning lines.

[0079] 4 illustrates a display panel 100 including six gate driver modules 10 (GOA1, GOA2, two GOA3s, GOA4, and GOA5, electrically connected to corresponding sub-pixels Pi through a first scan line EML1, a second scan line NSL1, a third scan line PSL, a fourth scan line NSL2, and a fifth scan line EML2, respectively). For example, the two GOA3s may be, but are not limited to, the same PScan circuit, i.e., the signals loaded by the two GOA3s (the second start signal STV2) and the signals output by the two GOA3s may be the same, so as to improve the reliability of the PScan signals output by the two GOA3s. For example, GOA1 and GOA5 may be two different EM circuits, for example, the two third start signals STV3 corresponding to the two GOA3s may be different (for example, but not limited to, the values ​​of at least one of the two parameters, the pulse width and the starting time of the effective pulses of the two GOA3s may be different). For example, GOA2 and GOA4 may be two different NScan circuits, for example, the two first start signals STV1 corresponding to the two GOA3s may be different (for example, but not limited to, the values ​​of at least one of the two parameters, the pulse width and the starting time of the effective pulses of the two GOA3s may be different).

[0080] The difference between Figure 5 and Figure 4 is that the six gate driving modules 10 include two GOA1', GOA2', two GOA3', and GOA4', which are electrically connected to the corresponding sub-pixels Pi through the sixth scan line EML', the seventh scan line NSL1', the eighth scan line PSL1', and the ninth scan line NSL2', respectively. Similarly, the two GOA1's can be but are not limited to the same EM circuit, GOA2' and GOA4' can be two different NScan circuits, for example, the two first start signals STV1 corresponding to the two can be different, and the two GOA3s can be but are not limited to the same PScan circuit.

[0081] It should be noted that Figures 4 and 5 only illustrate the connection relationship between multiple gate driving circuits 20 in the same gate module, as well as the connection relationship between each of them and multiple sub-pixels Pi. As for the signal lines connected to each gate driving circuit 20, please refer to Figures 1 to 3 and the relevant text description above.

[0082] Specifically, in combination with Figures 4 and 6, Figure 6 includes a pixel driving circuit 302 corresponding to the setting method of the gate driving module 10 in Figure 4, and the pixel driving circuit 302 may include a data transistor M2, the source of the data transistor M2 is loaded with the data signal Vdata, the drain of the data transistor is electrically connected to the source of the driving transistor M1, and the gate of the data transistor M2 (for example, a P-type transistor) can be electrically connected to the third scan line PSL to load the PScan signal.

[0083] In which, the pixel driving circuit 302 may further include a reset transistor M4 and a compensation transistor M3, the gate of the reset transistor M4 (for example, an N-type transistor) may be electrically connected to the scan line NSL1 to load the NScan1 signal, the reset transistor M4 is configured to transmit the reset signal VI1 to the gate of the driving transistor M1 for resetting, the gate of the compensation transistor M3 (for example, an N-type transistor) may be electrically connected to the fourth scan line NSL2 to load the NScan2 signal, and the source and drain of the compensation transistor M3 are electrically connected to the drain and gate of the driving transistor M1, respectively.

[0084] The pixel driving circuit 302 may further include an initialization transistor M7. The gate of the initialization transistor M7 (for example, a P-type transistor) is electrically connected to the fifth scan line EML2 to load the EM2 signal. The drain of the initialization transistor M7 is electrically connected to one end of the light-emitting device 301 (the other end of the light-emitting device 301 may be loaded with the low voltage signal VSS). The initialization transistor M7 is configured to transmit the initialization signal VI2 to one end of the light-emitting device 301 for initialization.

[0085] The pixel driving circuit 302 further includes a reset transistor M8. The gate of the reset transistor M8 (for example, a P-type transistor) can be electrically connected to the fifth scan line EML2 to load the EM2 signal. The drain of the reset transistor M8 is electrically connected to the source of the driving transistor M1. The reset transistor M8 is configured to transmit the reset signal VI3 to the source of the driving transistor M1 to reset its voltage.

[0086] The pixel driving circuit 302 may further include a first light-emitting control transistor M5 and a second light-emitting control transistor M6. The source of the first light-emitting control transistor M5 is loaded with a first high voltage VDD, the drain of the first light-emitting control transistor M5 is electrically connected to the source of the driving transistor M1, the source and drain of the second light-emitting control transistor M6 are electrically connected to the drain of the driving transistor M1 and one end of the light-emitting device 301, respectively. The gates of the first light-emitting control transistor M5 and the second light-emitting control transistor M6 (for example, both are P-type transistors) are electrically connected to the first scan line EML1 to load the EM1 signal, and are both configured to control the light-emitting timing of the light-emitting device 301 according to the EM1 signal.

[0087] The pixel driving circuit 302 further includes a storage capacitor Cst, which is connected in series between the source of the first light emitting control transistor M5 and the gate of the driving transistor M1.

[0088] The pixel driving circuit 302 further includes a boost capacitor Cboost, which is connected in series between the gate of the driving transistor M1 and the gate of the data transistor M2.

[0089] Based on the above discussion, as shown in FIG8 , FIG8 is a timing diagram corresponding to the pixel driving circuit 302 in FIG7 . The writing frame WF of the display panel may include a first reset phase tim1 , a second reset phase tim2 , a data writing phase tim3 , and a light emitting phase tim4 . The specific working process is as follows:

[0090] In the first reset phase tim1, the initial transistor M7 and the reset transistor M8 are turned on according to the corresponding EMo2 signal, and the compensation transistor M3 is turned on according to the corresponding NScano2 signal, so that the anode of the light-emitting device 301 is reset according to the initialization signal VI2, and the input end, output end, and control end source, drain, and gate of the driving transistor M1 are reset according to the reset signal VI3;

[0091] In the second reset phase tim2, the reset transistor M4 is turned on according to the corresponding NScano1 signal, and the compensation transistor M3 is turned on according to the corresponding NScano2 signal, so that the gate and drain of the driving transistor M1 are reset according to the initialization signal VI2;

[0092] In the data writing phase tim3, the data transistor M2 is turned on according to the corresponding PScano signal, and the compensation transistor M3 is turned on according to the corresponding NScano2 signal, so that the gate of the driving transistor M1 can be written with the data signal Vdata;

[0093] In the light emitting stage tim4, the first light emitting control transistor M5 and the second light emitting control transistor M6 are turned on according to the EMo1 signal, so that the driving transistor M1 generates a driving current to drive the corresponding light emitting device 301 to emit light;

[0094] Furthermore, a third reset stage tin may be included between the light-emitting stage tim4 and the data writing stage tim3. In the third reset stage tin, the initial transistor M7 and the reset transistor M8 are turned on according to the corresponding EMo2 signal, so that the anode of the light-emitting device 301 can be reset according to the initialization signal VI2, and the source and drain of the driving transistor M1 can be reset according to the reset signal VI3.

[0095] It should be noted that, as can be seen from the differences in the configurations of the gate driver modules 10 in FIG. 5 and FIG. 4 , in conjunction with FIG. 5 and FIG. 7 , FIG. 7 includes a pixel driver circuit 302 corresponding to the configuration of the gate driver module 10 in FIG. 5 , i.e., the pixel driver circuit 302 in FIG. 7 can only be driven by the same EM circuit, and therefore can only be electrically connected to the same sixth scan line EML′ and loaded with the same signal (and cannot be electrically connected to the first scan line EML1 and the fifth scan line EML2 to be loaded with two different signals as in FIG. 6 ).

[0096] Specifically, as shown in Figure 7, compared with Figure 6, the difference is that the reset transistor M8 is removed, the first scan line EML1 is replaced by the sixth scan line EML', the second scan line NSL1 is replaced by the seventh scan line NSL1', the third scan line PSL is replaced by the eighth scan line PSL1', the fourth scan line NSL2 is replaced by the ninth scan line NSL2', and the fifth scan line EML2 is also replaced by the eighth scan line PSL1' of the previous level.

[0097] Based on the above discussion, as shown in FIG9 , FIG9 is a timing diagram corresponding to the pixel driving circuit 302 in FIG7 . The writing frame WF of the display panel may include a first reset phase tim1 ′, a second reset phase tim2 ′, a data writing phase tim3 ′, and a light-emitting phase tim4 ′. Taking the i-th stage gate driving circuit 20 as an example, the specific working process is as follows:

[0098] In the first reset phase tim1′, the reset transistor M4 is turned on according to the corresponding NScano1′(i) signal, so that the gate of the driving transistor M1 is reset according to the initialization signal VI1;

[0099] In the second reset phase tim2', the initial transistor M7 is turned on according to the corresponding PScano1'(i-1) signal, so that the anode of the light-emitting device 301 is reset according to the initialization signal VI2, and the compensation transistor M3 is turned on according to the corresponding NScano1'(2) signal;

[0100] In the data writing phase tim3', the data transistor M2 is turned on according to the corresponding PScano1'(i) signal, and the compensation transistor M3 is turned on according to the corresponding NScano2'(i) signal, so that the gate of the driving transistor M1 can be written with the data signal Vdata;

[0101] In the third reset phase tim4', the initial transistor M7 is turned on according to the corresponding PScano1'(i-1) signal, so that the anode of the light emitting device 301 is reset again according to the initialization signal VI2;

[0102] In the coupling phase tim5', the data transistor M2 is turned on according to the corresponding PScano1'(i) signal. At this time, regardless of the data signal Vdata, since the compensation transistor M3 is turned off, it will not affect the gate voltage of the driving transistor M1. However, since the gate voltage of the data transistor M2 is reduced, the gate voltage of the driving transistor M1 will also increase.

[0103] In the light-emitting stage tim6', the first light-emitting control transistor M5 and the second light-emitting control transistor M6 are turned on according to the EMo'(i) signal, so that the driving transistor M1 generates a driving current to drive the corresponding light-emitting device 301 to emit light. Since the gate voltage of the driving transistor M1 in the coupling stage tim5' rises to a value greater than the data voltage given by the data signal Vdata in the data writing stage tim3', the light-emitting device 301 will have a greater brightness. It can also be considered that the upper limit of the data voltage can be effectively reduced, saving power consumption.

[0104] According to the above analysis, in order to achieve normal light emission of each row of sub-pixels Pi, each level of gate driving circuit 20 (each of GOA1 to GOA5, each of GOA1' to GOA4') needs to output a corresponding gate-effective pulse in a corresponding time period to control the corresponding transistor in the pixel driving circuit 302 to turn on, thereby realizing the corresponding function to turn on the sub-pixels Pi. It can also be considered that if the gate driving circuit 20 cannot output the corresponding gate-effective pulse in the corresponding time period, the sub-pixels Pi in the corresponding row will not be able to emit light.

[0105] As shown in Figures 6 and 7, if the PScano signal and the PScano1'(i) signal do not have a gate-valid (low voltage) pulse, the data transistor M2 cannot be turned on, resulting in the data signal being unable to be written to the source of the drive transistor M1 and the sub-pixel Pi being unable to be turned on. If the EM1 signal and the EMo'(i) signal do not have a gate-valid (low voltage) pulse, the first emission control transistor M5 and the second emission control transistor M6 cannot be turned on, resulting in the drive current being unable to be formed and the sub-pixel Pi being unable to be turned on. If the NScano2 signal and the NScano2'(i) signal do not have a gate-valid (high voltage) pulse, the compensation transistor M3 cannot be turned on, resulting in the data signal being unable to be written to the gate of the drive transistor M1 and the sub-pixel Pi being unable to be turned on. Of course, if the EMo2 signal, the NScano1 signal, and the NScano1'(i) signal do not have a valid pulse, the light emission of the sub-pixel Pi will also be affected to a certain extent.

[0106] Specifically, based on the pixel driving circuit 302 shown in FIG6, at least one of the three gate driving circuits 20 used in the present application to generate the PScano signal, the EMo1 signal, and the NScano2 signal can be provided with the stage transmission frequency division control unit 203 and the output frequency division control unit 204 discussed above. Based on the pixel driving circuit 302 shown in FIG7, at least one of the three gate driving circuits 20 used in the present application to generate the PScano1'(i) signal, the EMo'(i) signal, and the NScano2'(i) signal can be provided with the stage transmission frequency division control unit 203 and the output frequency division control unit 204 discussed above. In this way, based on the first stage On the premise that the start signals (for example, the first start signal STV1, the second start signal STV2, and the third start signal STV3) in the gate drive circuit 20 have been set, in each frame, and in combination with the setting of the frequency division control signal FD (refer to the discussion of Cases 1 to 4 above), it is possible to control whether the first node P (for Figure 2) or the second node Q (for Figure 3) is electrically connected to the fourth node R, and control whether the third node S is electrically connected to the first node P (for Figure 2) or the second node Q (for Figure 3), so that the output gate control signal has or does not have a gate effective pulse, so as to control whether the sub-pixel Pi of the corresponding row is turned on (refreshed).

[0107] In one embodiment, as shown in Figures 4 and 5, the display panel is in a frequency reduction mode and a frequency increase mode in a time-sharing manner, and the multiple gate driving circuits 20 include a plurality of cascaded first gate driving circuits 2001 and a plurality of cascaded second gate driving circuits 2002 cascaded after the plurality of first gate driving circuits 2001; wherein, the multiple sub-pixels Pi include a plurality of first sub-pixels Pi1 electrically connected to the plurality of first gate driving circuits 2001 and a plurality of second sub-pixels Pi2 electrically connected to the plurality of second gate driving circuits 2002, the plurality of first sub-pixels Pi constitute a first display area, and the plurality of second sub-pixels Pi constitute a second display area; in the frequency reduction mode, the refresh rate of the first display area is greater than the refresh rate of the second display area; in the frequency increase mode, the refresh rate of the first display area is less than the refresh rate of the second display area.

[0108] In combination with the above discussion, it can be seen that the present application can control whether the level transmission signal generated by this stage has a level transmission valid pulse and whether the gate control signal has a gate valid pulse by setting the above-mentioned level transmission frequency division control unit 203 and output frequency division control unit 204 in the gate driving unit.

[0109] Specifically, here we take the i-th level NScan circuit shown in Figure 2 as an example. Here, based on the fact that the transistors in Figure 2 are all P-type transistors (i.e., low voltage is valid), the third frequency-division transistor T17 is turned on (i.e., the second frequency-division control signal FD2 is at its lower voltage), the first clock signal line CKL1 and the second clock signal line CKL2 transmit the first clock signal and the second clock signal respectively, combined with the working timing of the NScan circuit shown in Figure 9 for explanation, it can include but is not limited to the following 6 working stages t1 to t6.

[0110] In the first stage t1, the first clock signal XCK is set low, the second clock signal line CK is set high, and the stage transfer signal NScan(i-1) generated in the previous stage is set low: the third transistor T7 is in a closed state according to the second clock signal line CK; the first transistor T4, the input transistor T3 and the tenth transistor T14 are turned on according to the first clock signal XCK, and the low stage transfer signal NScan(i-1) is transmitted to the node D, the second node Q and the node F, so that the seventh transistor T5, the thirteenth transistor T8, the second-stage transmission transistor T9, the sixth transistor T2 and the eleventh transistor T16 are turned on according to NScan(i-1), the second voltage VGL is transmitted to the node C and the node B, and the high second clock signal line CK is transmitted to the node E. The first voltage VGH is transmitted to the node P (the fourth node R), so that the second transistor T6 and the fifth transistor T1 are turned on according to the second voltage VGL. The high second clock signal line CK is transmitted to the node A to charge the second capacitor C2 to a voltage equal to the voltage difference between the nodes A and B. The first voltage VGH is transmitted to the node E (the voltage of the node E can be between the first voltage VGH and the high voltage of the second clock signal line CK) to charge the first capacitor C1 to a voltage equal to the voltage difference between the nodes E and F. The first capacitor C1 is charged, so that the voltage of the node F is coupled and increased. Since the first-stage transmission output transistor T10 is turned off and the second-stage transmission output transistor T9 is turned on, the generated gate control signal NScano(i) is a low voltage.

[0111] In the second stage t2, the first clock signal XCK is set high, the second clock signal line CK is set low, and the stage transfer signal NScan(i-1) generated by the previous stage is set low: the first transistor T4, the input transistor T3 and the tenth transistor T14 are in the closed state according to the first clock signal XCK, and the gate of the seventh transistor T5, the node D, the second node Q, and the node F are maintained at the previous voltage; the sixth transistor T2 is maintained on, and the low-set second clock signal line CK is transmitted to the node E. The voltage of the node F is further pulled down by the first capacitor C1 due to the falling of the second clock signal CK, so that the eleventh transistor T16 is maintained on, and the voltage of the node F is transmitted to the node D, but the voltage of the node D is also increased by the coupling effect of the rising first clock signal XCK transmitted by the first clock signal line CKL1 in the circuit layout; the eleventh transistor T16 is turned off, due to The ninth transistor T12 prevents the voltage at the second node Q from following the voltage at the node D. The second-stage output transistor T9 remains on. The seventh transistor T5 remains on, and the high first clock signal XCK is transmitted to the nodes C and B. The fifth transistor T1 and the second transistor T6 are turned off. The thirteenth transistor T8 is turned on in response to the voltage at the node D. The first voltage VGH is transmitted to the first node P (the fourth node R), turning off the first-stage output transistor T10. Simultaneously, the low second clock signal line CK turns on the third transistor T7. The first voltage VGH is further transmitted to the node A, charging the second capacitor C2 to a voltage equal to the voltage difference between nodes A and B. Since the first-stage output transistor T10 is turned off and the second-stage output transistor T9 is turned on, the generated gate control signal NScano(i) is a low voltage.

[0112] In the third stage t3, the first clock signal XCK is set low, the second clock signal line CK is set high, and the level transfer signal NScan(i-1) generated by the previous stage is set high: the third transistor T7 is in a closed state according to the second clock signal line CK; the first transistor T4, the input transistor T3 and the tenth transistor T14 are turned on according to the first clock signal XCK, the high level transfer signal NScan(i-1) is transmitted to the node D, the node Q, the node F, and the gate of the seventh transistor T5, and the second voltage VGL is transmitted to the node C and the node B; the second-stage transmission transistor T9 is turned off, and the seventh transistor T5 is turned off according to the high level transfer signal NScan(i-1); the fifth transistor T1 and the second transistor T6 are turned on according to The first-stage output transistor T10 is turned on by the second voltage VGL, and the first voltage VGH is transmitted to the node E to charge the first capacitor C1 to a voltage equal to the voltage difference between the nodes E and F. The second clock signal line CK, which is set high, is transmitted to the node A to charge the second capacitor C2 to a voltage equal to the voltage difference between the nodes A and B. The thirteenth transistor T8 is turned off in response to the high-stage transfer signal NScan(i-1). The first node P (the fourth node R) is maintained at the previous (high) voltage via the third capacitor C3, turning off the first-stage output transistor T10. Since the first-stage output transistor T10 and the second-stage output transistor T9 are turned off, that is, the stage output terminal OUT is floating, the generated gate control signal NScano(i) is maintained at a low voltage.

[0113] In the fourth stage t4, the first clock signal XCK is set high, the second clock signal line CK is set low, and the stage transfer signal NScan(i-1) generated by the previous stage is set high: the input transistor T3, the first transistor T4 and the tenth transistor T14 are in the off state according to the first clock signal XCK, and the gate of the seventh transistor T5, the node D, the second node Q, and the node C are maintained at the previous voltage; the seventh transistor T5 is turned off according to the previous high voltage, the second-stage transmission transistor T9 is turned off according to the previous high voltage of the second node Q, the thirteenth transistor T8 is turned off according to the high voltage of the node D, the fifth transistor T1 and the second transistor T6 are turned on according to the previous low voltage of the node C, and the sixth transistor T2 is turned on according to the previous high voltage of the node F. The first voltage VGH is transmitted to the node E through the fifth transistor T1, that is, the voltage of the node E remains substantially unchanged. Combined with the coupling effect of the first capacitor C1, the voltage of the node F can also remain substantially unchanged. The low second clock signal CK is transmitted to the node A through the second transistor T6. Combined with the coupling effect of the second capacitor C2, the voltage of the node B is also reduced. The third transistor T7 is turned on according to the second clock signal CK. The low voltage at point A is transmitted to the node P (the fourth node R) through the third transistor T7, thereby turning on the first-stage transmission output transistor T10. Since the first-stage transmission output transistor T10 is turned on and the second-stage transmission output transistor T9 is turned off, the generated gate control signal NScano(i) is a high voltage.

[0114] In the fifth stage t5, the first clock signal XCK is set low, the second clock signal line CK is set high, and the stage transfer signal NScan(i-1) generated by the previous stage is set low: the third transistor T7 is in a closed state according to the second clock signal line CK; the first transistor T4, the input transistor T3 and the tenth transistor T14 are turned on according to the first clock signal XCK, and the low stage transfer signal NScan(i-1) is transmitted to the node D, the second node Q, and the gate of the seventh transistor T5 through the input transistor T3; the second-stage transmission transistor T9 is turned on according to the low voltage of the second node Q, and the sixth transistor T2 is turned on according to the voltage of the node F to transmit the high second clock signal line CK to the node E, so as to charge the first capacitor C1 to a voltage equal to the voltage difference between the nodes E and F; the seventh transistor T5 is turned on to transmit the low first clock signal XCK to the nodes C and B, and the fifth transistor T1 is turned on according to the low first clock signal XCK and the second voltage VGL. The voltage VGH is transmitted to the node E through the fifth transistor T1 (the voltage of the node E may be between the first voltage VGH and the high voltage of the second clock signal line CK). Since the first voltage VGH and the high voltage of the second clock signal line CK are equal, the voltage of the node E is substantially constant, and the voltage of the node F is substantially constant. The eleventh transistor T16 is turned off, thereby preventing the first capacitor C1 from affecting the falling speed of the voltage of the second node Q. The second transistor T6 is turned on in response to the low voltage at the node B, so that the high second clock signal line CK is transmitted to the node A, thereby charging the second capacitor C2 to a voltage equal to the voltage difference between the nodes A and B. The thirteenth transistor T8 is turned on in response to the low voltage at the node D, so that the first voltage VGH is transmitted to the first node P (the fourth node R), thereby turning off the first-stage transmission output transistor T10. Since the first-stage transmission output transistor T10 is turned off and the second-stage transmission output transistor T9 is turned on, the generated gate control signal NScano(i) is a low voltage.

[0115] In the sixth stage t6, the stage transfer signal NScan(i-1) generated by the previous stage is set low, and the first clock signal XCK and the second clock signal line CK are alternately set low and high, driving the voltage of the node F to couple downward. Each time the voltage of the node F is coupled downward, the voltage will gradually decrease, approaching -16V, and the voltage of the corresponding second node Q will gradually decrease, approaching -20V. In the first few cycles after the seventh transistor T5 of the fifth stage, the voltage of the node F is more obviously coupled downward, and the voltage of the second node Q is greatly affected by the voltage of the node F. Later, the eleventh transistor T16 is turned off, and the voltage of the second node Q tends to be stable and will not be affected by the voltage of the node F.

[0116] It should be noted that the gate drive circuit provided in the present application may be, but is not limited to, a 16T3C structure or a 13T3C structure (only the former is used as an example in Figures 2 and 3). Compared to the 13T3C structure, the 16T3C structure further includes the above-mentioned tenth transistor T14, twelfth transistor T15, and eleventh transistor T16. On the one hand, when the stage transfer signal NScan(i-1) of the previous stage writes a low voltage to the second node Q and the node F, the voltage of the second node Q can flow out from the eleventh transistor T16 and the ninth transistor T12 at the same time, and the second node Q is not directly connected to the first capacitor C1 (blocked by the eleventh transistor T16) to maintain the voltage. Therefore, the voltage of the second node Q can drop faster, which is conducive to turning on the second-stage transmission transistor T9. On the other hand, the second node Q is not directly connected to the first capacitor C1 (blocked by the eleventh transistor T16). Therefore, the fluctuation of the node E voltage will not drive the change of the second node Q voltage. In addition, the eleventh transistor T16 acts like a diode, and the second node Q voltage will not be pulled up by the node F.

[0117] In combination with the above discussion, it can be seen from Figures 2 and 10 that if the level transfer signal NScan(i-1) generated by the upper stage is always low (excluding valid high voltage pulses), it can be considered that the second node and the node D are always maintained at a low voltage, so as to always turn on the second-stage transmission output transistor T9 and the thirteenth transistor T8, and always turn off the first-stage transmission output transistor T10, so that the level transfer signal NScan(i) output by this stage is always a low voltage (excluding valid high voltage pulses).

[0118] In combination with the above discussion, it can be seen with reference to Figures 2 and 10 that during a period in which the third frequency-dividing transistor T17 is turned off (i.e., the second frequency-dividing control signal FD2 is at its higher voltage), that is, the first node P and the fourth node R are disconnected, the voltage of the first node P at this time can only be determined by the on-state of the thirteenth transistor T8 and the coupling effect of the third capacitor C3.

[0119] Specifically, in the first stage t1, the thirteenth transistor T8 is turned on, the first voltage VGH is transmitted to the first node P, and the first-stage transmission output transistor T10 is turned off; in the second stage t2, the thirteenth transistor T8 is turned on, the first voltage VGH is transmitted to the first node P, and the first-stage transmission output transistor T10 is turned off; in the third stage t3, the thirteenth transistor T8 is turned off, the first node P is maintained at the first voltage VGH, and the first-stage transmission output transistor T10 is turned off; in the fourth stage t4, the thirteenth transistor T8 is turned off, the first node P is maintained at the first voltage VGH, and the first-stage transmission output transistor T10 is turned off; in the fifth stage t5, the thirteenth transistor T8 is turned on, the first voltage VGH is transmitted to the first node P, and the first-stage transmission output transistor T10 is turned off; in the sixth stage t6, the thirteenth transistor T8 is turned on, the first voltage VGH is transmitted to the first node P, and the first-stage transmission output transistor T10 is turned off. Therefore, it can be considered that the first-stage transmission output transistor T10 is turned off in each stage, and the gate control signal is related to the turn-on state of the second-stage transmission output transistor T9, as follows:

[0120] In the first phase t1, the second-stage transmission output transistor T9 is turned on, so the stage transmission signal NScan(i) generated by this stage is a low voltage;

[0121] In the second phase t2, the second-stage transmission output transistor T9 is turned on, so the stage transmission signal NScan(i) generated by this stage is a low voltage;

[0122] In the third phase t3, the second-stage transmission output transistor T9 is turned off, that is, the stage transmission output terminal OUT is suspended, so the stage transmission signal NScano(i) generated by this stage is maintained at a low voltage;

[0123] In the fourth phase t4, the second-stage transmission output transistor T9 is turned off, that is, the stage transmission output terminal OUT is suspended, so the stage transmission signal NScano(i) generated by this stage is maintained at a low voltage;

[0124] In the fifth phase t5, the second-stage transmission output transistor T9 is turned on, so the stage transmission signal NScano(i) generated by this stage is a low voltage;

[0125] In the sixth phase t6 , the second-stage transmission output transistor T9 is turned on, so the stage transmission signal NScano(i) generated by this stage is a low voltage.

[0126] To summarize, if the third frequency-dividing transistor T17 is turned off (i.e., the second frequency-dividing control signal FD2 is at its higher voltage), the level-transmitting signal NScan(i) generated by this stage is all at a low voltage; if the third frequency-dividing transistor T17 is turned on (i.e., the second frequency-dividing control signal FD2 is at its lower voltage), under the alternating high and low voltages of the level-transmitting signal NScan(i-1), the first clock signal XCK, and the second clock signal CK generated by the previous stage, the level-transmitting signal NScan(i) generated by this stage can form a level-transmitting effective pulse (e.g., a high voltage pulse) in a corresponding time period (e.g., between the starting point of the fourth stage t4 and the end point of the fifth stage in FIG. 10 ), thereby acting on the corresponding transistor (e.g., the compensation transistor M3 in FIG. 6 and FIG. 7 ) in the pixel driving circuit 302 of the corresponding row, to turn on (refresh) the light-emitting device 301 of the corresponding row.

[0127] It can be understood that in the present application, the level transmission signal generated by the gate driving circuit 20 of this level is only transmitted to the gate driving circuit 20 of the next level, and the generated gate control signal is only loaded to the sub-pixel Pi of the corresponding row of this level; combined with the above analysis, it can be seen that in one frame, if the first node P (for Figure 2) or the second node Q (for Figure 3) in the gate driving circuit 20 of this level is not electrically connected to the fourth node R, no matter whether the third node S is electrically connected to the first node P or the second node Q, the gate control signal of this level does not have a valid pulse, which causes the sub-pixel Pi of the corresponding row of this level to be unable to turn on, and at the same time, the level transmission signal of this level does not have Therefore, the operation of the gate driving circuit 20 of the lower level cannot be controlled, resulting in that the level transmission signal and the gate control signal of the lower level also do not have the level transmission effective pulse and the gate effective pulse respectively (that is, the sub-pixels Pi of the corresponding row of the lower level cannot be turned on), and so on, the sub-pixels Pi of the subsequent rows cannot be turned on; that is, only when the first node P (for Figure 2) or the second node Q (for Figure 3) in the gate driving circuit 20 of each level is electrically connected to the fourth node R, can it be further controlled by controlling whether the third node S is electrically connected to the first node P or the second node Q to control whether the sub-pixels Pi of each row are turned on.

[0128] It should be understood that if the first sub-pixels Pi are turned on for more frames in a plurality of consecutive frames than the second sub-pixels Pi, it means that the first display area has a higher refresh rate than the second display area, and vice versa.

[0129] If a frequency reduction mode is to be implemented (the refresh rate decreases from the first display area to the second display area), the following method can be adopted: in a plurality of consecutive frames, in at least one frame at the front (e.g., Frame 1 in FIG11 ), the level transmission signals and gate control signals (e.g., NScano(1) to NScano(6) in FIG11 ) generated by all levels can be controlled to have level transmission valid pulses and gate valid pulses pl, respectively; in at least one frame at the back (e.g., Frame 4 in FIG11 ), the level transmission signals and gate control signals (e.g., NScano(1) to NScano(2) in FIG11 ) generated by each first gate driving circuit 2001 can be controlled to have level transmission valid pulses and gate valid pulses pl, respectively, and the level transmission signals generated by each second gate driving circuit 2002 can be controlled not to have level transmission valid pulses so that the corresponding gate control signals (e.g., NScano(3) to NScano(6) in FIG11 ) also do not have gate valid pulses, or only the generated gate control signals (e.g., NScano(3) to NScano(6) in FIG11 ) do not have gate valid pulses.

[0130] Specifically, referring to FIG. 2 and FIG. 3 and related discussions, in the frequency reduction mode, taking the first frequency dividing transistor T18 as a P-type transistor as an example, there are two implementation methods:

[0131] Mode 1, please refer to but not limited to Figure 11, the first frequency-division control signal FD1 (i.e., its voltage is equal to the low voltage) is used to control the third node S in each level of the gate drive circuit 20 to be electrically connected to the first node P (for Figure 2) or the second node Q (for Figure 3); within a frame, the second frequency-division control signal FD2 is used to control the first node P or the second node Q in the first gate drive circuit 2001 to be electrically connected to the fourth node R, so as to control the output gate control signal to have a gate effective pulse pl, so as to turn on the corresponding light-emitting device 301; within the frame, the second frequency-division control signal FD2 is also used to control the first node P or the second node Q in the second gate drive circuit 2002 to be disconnected from the fourth node R, so as to control the output gate control signal to not have the gate effective pulse pl, so as not to turn on the corresponding light-emitting device 301.

[0132] Mode 2 differs from Mode 1 in that the second frequency-division control signal FD2 (i.e., its voltage is equal to the low voltage) is used to control the fourth node R in each level of the gate drive circuit 20 to be electrically connected to the first node P (for Figure 2) or the second node Q (for Figure 3); within a frame, the first frequency-division control signal FD1 is used to control the third node S in the first gate drive circuit 2001 to be electrically connected to the first node P or the second node Q, so as to control the output gate control signal to have a gate effective pulse pl, so as to turn on the corresponding light-emitting device 301; within the frame, the first frequency-division control signal FD1 is also used to control the third node S in the second gate drive circuit 2002 to be disconnected from the first node P or the second node Q, so as to control the output gate control signal to not have the gate effective pulse pl, so as not to turn on the corresponding light-emitting device 301.

[0133] Regardless of whether method 1 or 2 is adopted, for the first-level gate driving circuit 20 to the sixth-level gate driving circuit 20, assuming that the refresh rates of the first two-level (first-level to second-level) gate driving circuit 20, the middle two-level (third-level to fourth-level) gate driving circuit 20, and the last two-level (fifth-level to sixth-level) gate driving circuit 20 are 120HZ, 60HZ, and 30HZ respectively, then according to the above content, within the four consecutive frames (Frame 1 to Frame 4), it can be set as follows: NScano(1) to NScano(2) have gate effective pulses pl in Frame 1 to Frame 4, the gate control signals NScano(3) to NScano(4) have gate effective pulses pl in Frame 1 and Frame 3, and the gate control signals NScano(5) to NScano(6) have gate effective pulses pl only in Frame 1;

[0134] That is, the frequency division control signal FD needs to be set as follows (the following is an example of method 1):

[0135] The first frequency-dividing control signal FD1 is at a low voltage in Frames 1 to 4, turning on the six first frequency-dividing transistors T18 corresponding to the gate driving circuits 20 of stages 1 to 6, so that the gate control signal generated by each can be the same as the corresponding stage transmission signal;

[0136] The second frequency division control signal FD2 is at a low voltage corresponding to each stage in Frame 1, so that the six third frequency division transistors T17 corresponding to the gate driving circuits 20 of the first to sixth stages are turned on, so that the six stage transmission signals NScan(1) to NScan(6) and the six gate control signals NScano(1) to NScano(6) all have gate valid pulses pl in Frame 1;

[0137] The second frequency division control signal FD2 is a low voltage before tf1 in Frame 2 to turn on the two third frequency division transistors T17 corresponding to the gate driving circuits 20 of the first to second stages, so that NScano(1) to NScano(2) all have gate effective pulses pl in Frame 2. The second frequency division control signal FD2 is a high voltage after tf1 to turn off the four third frequency division transistors T17 corresponding to the gate driving circuits 20 of the third to sixth stages, so that NScano(3) to NScano(6) do not have gate effective pulses pl in Frame 2.

[0138] The second frequency division control signal FD2 is a low voltage before tf2 in Frame 3 to turn on the four third frequency division transistors T17 corresponding to the gate driving circuits 20 of the first to fourth stages, so that NScan(1) to NScan(4) all have gate effective pulses pl in Frame 3. The second frequency division control signal FD2 is a high voltage after tf2 to turn off the two third frequency division transistors T17 corresponding to the gate driving circuits 20 of the fifth to sixth stages, so that NScan(5) to NScan(6) do not have gate effective pulses pl in Frame 3.

[0139] The analysis of the second frequency-division control signal FD2 in Frame 4 may refer to the analysis in Frame 2 .

[0140] Of course, as analyzed above and compared with FIG. 11 , the second frequency-dividing control signal FD2 can also be set to a low voltage in Frames 1 to 4 to turn on the six third frequency-dividing transistors T17 corresponding to the gate driving circuits 20 of the first to sixth stages, so that the stage-transmitting signals generated by each stage have stage-transmitting valid pulses.

[0141] Furthermore, the corresponding frequency division setting is achieved by controlling the first frequency division control signal FD1 in each frame to have or not have a gate effective pulse during the period when the first frequency division control signal FD1 effectively acts on the gate driving circuit of the corresponding stage.

[0142] In summary, the display panel can be divided into at least a first area, a second area, and a third area. The first area (corresponding to the action of the first to second-level gate driving circuits 20) is loaded with a valid pulse pl in Frame 1 to Frame 4 to perform data writing (i.e., data refresh is performed 4 times). The second area (corresponding to the action of the third to fourth-level gate driving circuits 20) is loaded with a gate valid pulse pl in Frame 1 and Frame 3 to perform data writing (i.e., data refresh is performed 2 times), that is, its refresh rate is half of that of the first area. Similarly, the second area (corresponding to the action of the fifth to sixth-level gate driving circuits 20) is loaded with a valid pulse pl only in Frame 1 to perform data writing (i.e., data refresh is performed 1 time), and its refresh rate is 1 / 4 of the first area. In the above example, the refresh rates of the first area, the second area and the third area can be a, (1 / 2)*a, (1 / 4)*a respectively. If a is an integer multiple of 4, it needs to be divided into 4 frames, for example, 120HZ, 60HZ, and 30HZ respectively.

[0143] For the sake of convenience, the display panel is divided into three areas, and each area is affected by a two-level gate control signal, and the refresh rates of the three areas can be a, (1 / 2)*a, and (1 / 4)*a, respectively. For the sake of convenience, the display panel is divided into three areas. The refresh rates of the three areas can be changed, and the corresponding refresh rates can also be adjusted. The only difference here is the degree of refresh rate difference of the multiple areas shown, and the frame number setting requirements. If the refresh rate of each of the three areas is 1 / 3 of the refresh rate of the former, 9 frames need to be shown so that the refresh times of the three areas are 3 times, that is, the three areas are refreshed 9 times, 3 times and 1 time respectively in 9 frames.

[0144] Specifically, if you want to achieve the frequency increase mode (the frequency increases from the first display area to the second display area), you can use the following method: in the continuous multiple frames, in at least one frame in the front (for example, Frame 1 in Figures 12 to 16), the level transmission signals and gate control signals generated by all stages can be controlled to have level transmission valid pulses and gate valid pulses respectively; in at least one frame in the back (for example, Frame 4 in Figures 12 to 13, Frame 3 in Figures 14 to 15, Frame 1 in Figure 16), the level transmission signals and gate control signals generated by all stages can be controlled to have level transmission valid pulses and gate valid pulses respectively. 4), the level transmission signal generated by each first gate driving circuit 2001 is controlled to have a level transmission effective pulse (the level transmission is continuously applied to the second gate driving circuit 2002), and the gate control signal generated does not have a gate effective pulse (for example, NScan (1) to NScan (2) in Figures 12 to 13, NScan (3) to NScan (4) in Figures 14 to 15, and NScan (1) to NScan (4) in Figure 16), and the level transmission signal and gate control signal generated by each second gate driving circuit 2002 respectively have a level transmission effective pulse and a gate effective pulse (for example, NScan (3) to NScan (4) in Figures 12 to 13, NScan (5) to NScan (6) in Figures 14 to 15, and NScan (5) to NScan (6) in Figure 16).

[0145] Specifically, referring to FIG. 2 and FIG. 3 and the related discussion, in the frequency-up mode, please refer to but not be limited to FIG. 12 to FIG. 16. Here, the third frequency-dividing transistor T17 is taken as a P-type transistor as an example, that is, the second frequency-dividing control signal FD2 (for example, its voltage is equal to the low voltage) is used to control the fourth node R in each stage of the gate driving circuit 20 to be electrically connected to the first node P (for FIG. 2) or the second node Q (for FIG. 3); within one frame, the first frequency-dividing control signal FD1 is used to control the third node S in the first gate driving circuit 2001 to be electrically connected to the first node P (for FIG. 2) or the second node Q (for FIG. 3). The first node P (for Figure 2) or the second node Q (for Figure 3) is disconnected to control the output gate control signal to have no gate effective pulse, so as not to turn on the corresponding light-emitting device 301; within the frame, the first frequency-dividing control signal FD1 is used to control the first node P (for Figure 2) or the second node Q (for Figure 3) in the second gate drive circuit 2002 to be electrically connected to the fourth node R, so as to control the output gate control signal to have the gate effective pulse, so as to turn on the corresponding light-emitting device 301.

[0146] For example, as shown in FIG12 , the refresh rates of the front two-stage gate driving circuit 20, the middle two-stage gate driving circuit 20, and the rear two-stage gate driving circuit 20 are 30 Hz, 120 Hz, and 60 Hz, respectively. Based on the above content, within Frame 1 to Frame 4, it can be set as follows: NScano(1) to NScano(2) have gate effective pulses pl in Frame 1, NScano(3) to NScano(4) have gate effective pulses pl in Frame 1 to Frame 4, and gate control signals NScano(5) to NScano(6) have gate effective pulses pl in Frame 1 and Frame 3;

[0147] That is, the frequency division control signal FD needs to be set as follows:

[0148] The second frequency-dividing control signal FD2 is at a low voltage in Frames 1 to 4, so that the six third frequency-dividing transistors T17 corresponding to the gate driving circuits 20 of stages 1 to 6 are all turned on, so that the stage-transmitting signals generated by each of them have stage-transmitting valid pulses.

[0149] The first frequency division control signal FD1 is at a low voltage corresponding to each stage in Frame 1, so that the six first frequency division transistors T18 corresponding to the gate driving circuits 20 of stages 1 to 6 are turned on, so that the third node S can be electrically connected to the first node P or the second node Q, so that the six gate control signals NScano(1) to NScano(6) also have gate valid pulses pl in Frame 1;

[0150] The first frequency division control signal FD1 is a high voltage before tf1 and after ft2 in Frame 2, so that the two first frequency division transistors T18 corresponding to the gate driving circuits 20 of the first, second, fifth, and sixth stages are turned off, so that NScano(1) to NScano(2) and NScano(5) to NScano(6) do not have the gate effective pulse pl in Frame 2. The first frequency division control signal FD1 is a low voltage between tf1 and ft2, so that the two first frequency division transistors T18 corresponding to the gate driving circuits 20 of the first and third stages are turned on, so that NScano(1) to NScano(3) do not have the gate effective pulse pl in Frame 2.

[0151] The first frequency division control signal FD1 is a high voltage before tf3 in Frame 3 so that the two first frequency division transistors T18 corresponding to the gate driving circuits 20 of the first and second stages are turned off, so that NScano(1) to NScano(2) do not have the gate effective pulse pl in Frame 3. The first frequency division control signal FD1 is a low voltage after tf3 so that the four first frequency division transistors T18 corresponding to the gate driving circuits 20 of the third to sixth stages are turned on, so that NScano(3) to NScano(6) have the gate effective pulse pl in Frame 3.

[0152] The analysis of the first frequency-division control signal FD1 in Frame 4 may refer to the analysis in Frame 2 .

[0153] Similarly, for example, as shown in FIG13 , the refresh rates of the front two-stage gate drive circuit 20, the middle two-stage gate drive circuit 20, and the rear two-stage gate drive circuit 20 are 60 Hz, 120 Hz, and 30 Hz, respectively. Based on the above content, it can be seen that within Frame 1 to Frame 4, it can be set as follows: NScano(1) to NScano(2) have gate effective pulses pl in Frame 1 and Frame 3, NScano(3) to NScano(4) have gate effective pulses pl in Frame 1 to Frame 4, and gate control signals NScano(5) to NScano(6) have gate effective pulses pl only in Frame 1;

[0154] That is, the frequency division control signal FD needs to be set as follows:

[0155] The second frequency division control signal FD2 is set the same as that in FIG12 so that the level transfer signal generated by each level gate driving circuit 20 has a level transfer effective pulse;

[0156] The first frequency division control signal FD1 is low voltage corresponding to each level in Frame 1. Similarly, the six gate control signals NScano(1) to NScano(6) also have gate valid pulses pl in Frame 1.

[0157] The first frequency division control signal FD1 is a high voltage before tf1 and after ft2 in Frame 2. Similarly, NScano(1) to NScano(2) and NScano(5) to NScano(6) do not have a gate valid pulse pl in Frame 2. The first frequency division control signal FD1 is a low voltage between tf1 and ft2. Similarly, NScano(3) to NScano(4) have a gate valid pulse pl in Frame 2.

[0158] The first frequency division control signal FD1 is at a low voltage before tf3 in Frame 3, so that NScano(1) to NScano(4) all have gate valid pulses pl in Frame 3, and is at a high voltage after tf3, so that NScano(5) to NScano(6) do not have gate valid pulses pl in Frame 3.

[0159] The analysis of the first frequency-division control signal FD1 in Frame 4 may refer to the analysis in Frame 2 .

[0160] Similarly, for example, as shown in FIG14 , the refresh rates of the front two-stage gate drive circuit 20, the middle two-stage gate drive circuit 20, and the rear two-stage gate drive circuit 20 are 120 Hz, 30 Hz, and 60 Hz, respectively. Based on the above content, within Frame 1 to Frame 4, it can be set as follows: NScano(1) to NScano(2) have gate effective pulses pl in Frame 1 to Frame 4, NScano(3) to NScano(4) have gate effective pulses pl only in Frame 1, and gate control signals NScano(5) to NScano(6) have gate effective pulses pl in Frame 1 and Frame 3;

[0161] That is, the frequency division control signal FD needs to be set as follows:

[0162] The second frequency division control signal FD2 is set the same as that in FIG12 so that the level transfer signal generated by each level gate driving circuit 20 has a level transfer effective pulse;

[0163] The first frequency division control signal FD1 is low voltage corresponding to each level in Frame 1. Similarly, the six gate control signals NScano(1) to NScano(6) also have gate valid pulses pl in Frame 1.

[0164] The first frequency division control signal FD1 is at a low voltage before tf1 in Frame 2, so that NScano(1) to NScano(2) all have gate valid pulses pl in Frame 2, and is at a high voltage after tf1, so that NScano(3) to NScano(6) do not have gate valid pulses pl in Frame 2.

[0165] The first frequency division control signal FD1 is low voltage before tf2 and after ft3 in Frame 3, so that NScano(1) to NScano(2) and NScano(5) to NScano(6) all have gate valid pulses pl in Frame 3, and is high voltage between tf2 and ft3, so that NScano(3) to NScano(4) do not have gate valid pulses pl in Frame 3.

[0166] The analysis of the first frequency-division control signal FD1 in Frame 4 may refer to the analysis in Frame 2 .

[0167] Similarly, for example, as shown in FIG15 , the refresh rates of the front two-stage gate drive circuit 20, the middle two-stage gate drive circuit 20, and the rear two-stage gate drive circuit 20 are 60 Hz, 30 Hz, and 120 Hz, respectively. Based on the above content, it can be seen that within Frame 1 to Frame 4, it can be set as follows: NScano(1) to NScano(2) have gate effective pulses pl in Frame 1 and Frame 3, NScano(3) to NScano(4) have gate effective pulses pl only in Frame 1, and gate control signals NScano(5) to NScano(6) have gate effective pulses pl in Frame 1 to Frame 4.

[0168] That is, the frequency division control signal FD needs to be set as follows:

[0169] The second frequency division control signal FD2 is set the same as that in FIG12 so that the level transfer signal generated by each level gate driving circuit 20 has a level transfer effective pulse;

[0170] The first frequency division control signal FD1 is low voltage corresponding to each level in Frame 1. Similarly, the six gate control signals NScano(1) to NScano(6) also have gate valid pulses pl in Frame 1.

[0171] The first frequency division control signal FD1 is a high voltage before tf1 in Frame 2, so that NScano(1) to NScano(4) do not have a gate valid pulse pl in Frame 2, and is a low voltage after tf1, so that NScano(5) to NScano(6) have a gate valid pulse pl in Frame 2.

[0172] The first frequency division control signal FD1 is low voltage before tf2 and after ft3 in Frame 3, so that NScano(1) to NScano(2) and NScano(5) to NScano(6) all have gate valid pulses pl in Frame 3, and is high voltage between tf2 and ft3, so that NScano(3) to NScano(4) do not have gate valid pulses pl in Frame 3.

[0173] The analysis of the first frequency-division control signal FD1 in Frame 4 may refer to the analysis in Frame 2 .

[0174] Similarly, for example, as shown in FIG16 , the refresh rates of the front two-stage gate drive circuit 20, the middle two-stage gate drive circuit 20, and the rear two-stage gate drive circuit 20 are 30 Hz, 60 Hz, and 120 Hz, respectively. Based on the above content, it can be seen that within Frame 1 to Frame 4, it can be set as follows: NScano(1) to NScano(2) have gate effective pulses pl only in Frame 1, NScano(3) to NScano(4) have gate effective pulses pl in Frame 1 and Frame 3, and gate control signals NScano(5) to NScano(6) have gate effective pulses pl in Frame 1 to Frame 4.

[0175] That is, the frequency division control signal FD needs to be set as follows:

[0176] The second frequency division control signal FD2 is set the same as that in FIG12 so that the level transfer signal generated by each level gate driving circuit 20 has a level transfer effective pulse;

[0177] The first frequency division control signal FD1 is low voltage corresponding to each level in Frame 1. Similarly, the six gate control signals NScano(1) to NScano(6) also have gate valid pulses pl in Frame 1.

[0178] The first frequency division control signal FD1 is a high voltage before tf1 in Frame 2, so that NScano(1) to NScano(4) do not have a gate valid pulse pl in Frame 2, and is a low voltage after tf1, so that NScano(5) to NScano(6) have a gate valid pulse pl in Frame 2.

[0179] The first frequency division control signal FD1 is a high voltage before tf2 in Frame 3, so that NScano(1) to NScano(2) do not have a gate valid pulse pl in Frame 3, and is a low voltage after tf2, so that NScano(3) to NScano(6) have a gate valid pulse pl in Frame 3.

[0180] The analysis of the first frequency-division control signal FD1 in Frame 4 may refer to the analysis in Frame 2 .

[0181] In conjunction with the relevant discussion of Figures 11 to 16, the display panel can be further divided into m regions corresponding to the m gate drive circuits 20 cascaded in sequence. The corresponding m refresh rates can be expressed as a / (j1), a / (j2), and finally a / (jm). j1 to jm are all positive integers, and the m refresh rates are all positive integers. The number of frames should be set to the lowest common multiple of the m numbers j1 to jm. For example, if the two refresh rates are 120Hz and 1Hz, there should be 120 frames in one cycle. Similarly, reference can be made to the above description of "m is the lowest common multiple of n1, n1, and n1."

[0182] In summary, the first frequency division control signal FD1 and the second frequency division control signal FD2 can be reasonably controlled according to the refresh rate relationship among the first area, the second area A2 and the third area. For example, the first area A1, the second area A2 and the third area A3 are respectively used for video playback, the comment area screen (which can be scrolled according to needs), and the keyboard screen, that is, the refresh rates of the three are reduced in sequence. At this time, the first frequency division control signal FD1 can be kept at a low voltage in multiple frames, and the second frequency division control signal FD2 can be relied on to jump from a valid (low) voltage to an invalid (high) voltage to achieve this. Alternatively, the second frequency division control signal FD2 can be kept at a low voltage in multiple frames. The low voltage is continuously maintained, and this is achieved by relying on the jump of the first frequency-dividing control signal FD1 from the valid (low) voltage to the invalid (high) voltage; for example, the first area A1, the second area A2 and the third area A3 are respectively used for date display, video playback, and comment area screen (which can be scrolled according to needs), that is, the refresh rates of the three tend to first increase and then decrease. At this time, the second frequency-dividing control signal FD2 can only be maintained at a low voltage in multiple frames to maintain that each stage can output a valid stage transfer pulse, and rely on the first frequency-dividing control signal FD1 to jump from the invalid (high) voltage to the valid (low) voltage, and then from the valid (low) voltage to the invalid (high) voltage to achieve this.

[0183] Among them, the frame in which the gate of the multi-level gate control signal corresponding to any area has a gate effect pulse can be called the write frame of the area, which is used to turn on the sub-pixel Pi so that the corresponding at least one data string can be loaded onto the corresponding at least one row of sub-pixels Pi respectively, and the frame without a gate effect pulse is called the hold frame of the area, so that the corresponding at least one row of sub-pixels Pi can be maintained as the corresponding at least one data string. For example, Frame 1 in Figures 11 to 16 is simultaneously a write frame for three areas corresponding to the front two levels, middle two levels, and rear two levels of gate driving circuits 20; Frame 2 and Frame 4 in Figures 12 to 13 are simultaneously a write frame for an area corresponding to the middle two levels of gate driving circuits 20, and are also simultaneously a hold frame for an area corresponding to the front two levels and rear two levels of gate driving circuits 20; Frame 3 in Figures 14 to 15 is simultaneously a hold frame for an area corresponding to the middle two levels of gate driving circuits 20, and is also simultaneously a write frame for an area corresponding to the front two levels and rear two levels of gate driving circuits 20; Frame 2 and Frame 4 in Figures 15 to 16 are simultaneously a hold frame for an area corresponding to the front two levels and middle two levels of gate driving circuits 20, and are also simultaneously a write frame for an area corresponding to the rear two levels of gate driving circuits 20.

[0184] Based on the above discussion, it can be considered that in a write frame, the gate-active pulse in the gate control signal turns on the corresponding row of sub-pixels Pi, causing the multiple sub-data in the corresponding data string to be transmitted to the corresponding multiple sub-pixels Pi. Therefore, it is possible to determine whether the frame is a write frame for the next row of sub-pixels Pi or a hold frame for the previous row of sub-pixels Pi based on whether the two data strings corresponding to the two adjacent rows of sub-pixels Pi have changed (that is, whether the two voltage values ​​corresponding to the two adjacent sub-data transmitted by the data line electrically connected to any column of sub-pixels Pi are the same, that is, whether the data signal transmitted by the data line has jumped).

[0185] As shown in Figure 17, if the data signal source transmitted by the data line jumps, due to the row-by-row scanning, the data signal transmitted by each data line will simultaneously undergo an effective jump hop1 (that is, the gate control signal of the corresponding level needs to have a gate effective pulse to turn on the sub-pixel Pi of the corresponding row to load the multiple sub-data after the jump). The frequency division control signal FD can be set to control the corresponding gate effective pulse to be generated before the corresponding data string appears to ensure that the sub-pixel Pi of the corresponding row is turned on. Based on the fact that the first frequency division transistor T18 and the second frequency division transistor T20 are both P-row transistors, the first frequency division control signal FD1 and the first frequency division control signal FD1 are both set to a low voltage to turn on the above two.

[0186] Specifically, taking Figure 6 as an example, the NScano2 signal and the NScano1 signal in Figure 8 respectively represent the signals loaded on the gates of M3 and M4 (both are P-type transistors) in Figure 6, and the con(M3) signal and the con(M4) signal in Figure 17 can respectively represent the total frequency division control signal FD in the two NScan circuits used to generate the NScano2 signal and the NScano1 signal. The "total frequency division control signal FD" can be understood as the signal after the first frequency division control signal FD1 and the second frequency division control signal FD2 in the NScan circuit are summed, that is, only when both are at a valid (low) voltage, the "total frequency division control signal FD" will be at a valid (low) voltage, otherwise they are both at an invalid (high) voltage.

[0187] 6 and 8 , the NScano2 signal needs to be a valid (high) voltage in advance of the NScano1 signal, so as to realize turning on the compensation transistor M3 in the first reset phase tim1 so that the anode of the light-emitting device 301 is reset according to the initialization signal VI2, and then turning on the reset transistor M4 in the second reset phase tim2 so that the gate of the driving transistor M1 is reset according to the initialization signal VI2. Therefore, as shown in FIG17 , for example, the con(M3) signal and the con(M4) signal corresponding to the two NScan circuits can be respectively changed from an invalid (high) voltage to a valid (low) voltage 32 row cycles and 16 row cycles before the “sub-data valid jump hop1”, so as to sequentially turn on the compensation transistor and the reset transistor. In combination with the relevant discussions in FIG2 and FIG3 , it can be seen that the first reset phase tim1 and the second reset phase tim2 of the corresponding row sub-pixel Pi are sequentially completed;

[0188] Furthermore, still based on FIG6 , the frequency division control signal FD (also referred to as the con(M2) signal) in the PScan circuit for generating the PScano signal can be controlled to jump from the invalid (high) voltage to the valid (low) voltage before the “sub-data valid transition hop1” (less than 16 row cycles), or when it is equal to the “sub-data valid transition hop1” (not shown in FIG17 ), so as to turn on the data transistor and continue the period from the valid transition hop1 to the invalid transition hop2 of the data signal transmitted by the data line, so as to perform the data writing phase tim3;

[0189] Furthermore, still based on FIG6 , after the “sub-data invalid transition hop2”, the frequency division control signal FD (also referred to as the con(M5 / 6) signal) in the EM circuit used to generate the EMo1 signal can be controlled to transition from an invalid (high) voltage to a valid (low) voltage (not shown in FIG17 ), thereby turning on the first and second light-emitting control transistors. This continues for the period from the valid transition hop1 to the invalid transition hop2 of the data signal transmitted on the data line, thereby performing the light-emitting stage tim4.

[0190] 6 , between the light-emitting stage tim4 and the data writing stage tim3 , the frequency-division control signal FD (also referred to as the con(M7 / 8) signal) in the EM circuit for generating the EMo2 signal can be controlled to jump from an invalid (high) voltage to a valid (low) voltage (not shown in FIG17 ) to turn on the initial transistor and reset the transistor to proceed to the third reset stage tin.

[0191] Among them, the above-mentioned "row cycle" can be understood as the sum of the on-time and row blanking time of each row of sub-pixels Pi. In Figure 17, only one frame is used, and the first 878 rows of sub-pixels Pi are in the holding frame (that is, the corresponding con(M3) signal and con(M4) signal are in the invalid (high) voltage for a period of time maintained at 878 row cycles), and the con(M3) signal and con(M4) signal jump from the valid (low) voltage to the invalid (high) voltage 30 row cycles and 14 row cycles before the "sub-data invalid jump hop2", respectively. The subsequent 878 rows of sub-pixels Pi are also in the holding frame (that is, the corresponding con(M3) signal and con(M4) signal are in the invalid (high) voltage for a period of time also maintained at 878 row cycles).

[0192] In summary, in this embodiment, the waveform of the "total frequency division control signal FD" in at least one corresponding gate driver circuit 20 can be set based on the "sub-data valid transition hop1" and "sub-data valid transition hop1" of the data signal transmitted by the data line. For example, in the low-frequency region, the Source signal is in a constant voltage signal during the maintenance frame. At this time, the "total frequency division control signal FD" can be equal to an invalid (high) voltage, so that the effective gate pulse cannot be output. For another example, in the high-frequency region, when the Source signal undergoes the "sub-data valid transition hop1", the "total frequency division control signal FD" can be triggered to jump to a valid (low) voltage, so that the effective gate pulse can be output normally. In addition, combined with the above analysis, it can be seen that the transition moment of the "total frequency division control signal FD" in different gate driver circuits 20 for different transistors in the pixel driver circuit 302 can be at the "sub-data valid transition hop1" or before or after it, so as to respectively achieve different working stages.

[0193] It should be noted that, in combination with the above discussion on Figures 2, 3 and 10, in any level of the gate drive circuit 20, if at least one of the first clock signal and the second clock signal is equal to the constant voltage, the corresponding level transfer signal and gate control signal will not have a level transfer valid pulse and a gate valid pulse respectively, and thus the sub-pixel Pi of the corresponding row cannot be refreshed (i.e., cannot be turned on).

[0194] Furthermore, the gate drive module 10 includes n-stage gate drive circuits 20 cascaded in sequence, where n is a positive integer greater than or equal to 2, and the n-stage gate drive circuits 20 are all loaded with the same clock signal (for example, the 6-stage gate drive circuits 20 in Figures 11 to 16 are all loaded with the first clock signal and the second clock signal, and it can be considered that the positions where the first clock signal and the second clock signal are loaded in two adjacent stages are opposite); within one frame, the clock signal is alternately equal to the first clock voltage and the second clock voltage (which can be respectively) during the period of time when it is effectively applied to the gate drive circuits 20 of the i-th stage to the (i+k)-th stage. The high voltage and low voltage in the first clock signal and the second clock signal can control the opening of multiple rows of sub-pixels Pi corresponding to the gate control signals of the i-th to (i+k)-th levels), i and k are both positive integers greater than or equal to 1; wherein, when the gate control signals output by the gate drive circuit 20 of the (i+k+1)-th to n-th levels do not include the gate effective pulse, the clock signal is always equal to the first clock voltage or the second clock voltage during the period when it effectively acts on the gate drive circuit 20 of the (i+k+1)-th to n-th levels (which also just satisfies the situation that the corresponding multiple sub-pixels Pi are not turned on).

[0195] It can be understood that since the gate control signals from the i-th to the (i+k)-th levels all have gate effective pulses, and the gate control signals from the (i+k+1)-th to the n-th levels all do not have gate effective pulses, based on this, in this embodiment, the clock signal is set to be equal to a constant voltage during the period when it effectively acts on the (i+k+1)-th to the n-th level gate drive circuits 20, which not only meets the requirement of "the gate control signals from the (i+k+1)-th to the n-th levels all do not have gate effective pulses", but also saves power consumption.

[0196] Furthermore, to ensure that the gate effective pulse of the (i+k)th level gate control signal is completely generated (to avoid interruption due to the clock signal becoming a constant voltage signal), the clock signal can be set to be equal to the constant voltage signal after the gate effective pulse is completely generated.

[0197] It should be noted that it must be satisfied that the last few levels of gate control signals do not have gate effective pulses. If there is at least one last level of gate control signal with a gate effective pulse, the voltage of the gate drive circuit 20 corresponding to the previous few levels of gate control signals that do not have gate effective pulses cannot be set to a constant voltage, because this will also make it impossible to generate a level transfer signal acting on the next level, and it will be impossible to achieve at least one subsequent level of gate control signal with a gate effective pulse.

[0198] Specifically, for example, as shown in FIG11 , in Frame 2 and Frame 4, at least one of the first clock signal and the second clock signal (the two may be equal or unequal) may be set to be equal to at least one of a high voltage and a low voltage after the end time of the gate valid pulse in NScano(2); and in Frame 3, at least one of the first clock signal and the second clock signal may be set to be equal to at least one of a high voltage and a low voltage after the end time of the gate valid pulse in NScano(4).

[0199] Similarly, as shown in FIG12 , in Frame 2 and Frame 4, at least one of the first clock signal and the second clock signal can be set to be equal to at least one of a high voltage and a low voltage after the end time of the gate valid pulse in NScano(4).

[0200] Similarly, as shown in FIG13 , in Frame 2 to Frame 4, at least one of the first clock signal and the second clock signal can be set to be equal to at least one of a high voltage and a low voltage after the end time of the gate valid pulse in NScano(4).

[0201] Similarly, as shown in FIG14 , in Frame 2 and Frame 4, at least one of the first clock signal and the second clock signal can be set to be equal to at least one of a high voltage and a low voltage after the end time of the gate valid pulse in NScano(2).

[0202] As discussed above, for example, as shown in FIG15 and FIG16 , in Frame 1 and Frame 4, since NScano(5) and NScano(6) (i.e., corresponding to the last two stages of the gate driving circuit 20) both have gate valid pulses, the first clock signal and the second clock signal need to be maintained alternately set to the first clock voltage and the second clock voltage in each frame to ensure that the stage transmission signal of each stage can be generated until the generation of the sixth stage, i.e., the gate control signal, is controlled.

[0203] The present application provides a gate driver module and a display panel, comprising the above-mentioned frequency-dividing signal line and a plurality of cascaded gate driver circuits, wherein the gate driver circuit comprises the above-mentioned stage transmission unit and output unit. Furthermore, a stage transmission frequency-dividing control unit is provided, which is electrically connected to the stage transmission receiving unit via the first node or the second node (and is also electrically connected to the stage transmission output unit via the fourth node), and an output frequency-dividing control unit is provided, which is connected between one of the first node and the second node and the third node. The two control units are respectively configured to control the signal of one of the first node and the second node according to the frequency-dividing control signal to control the stage transmission output unit to output the stage transmission signal of the current stage, and to control the signal of the third node according to the frequency-dividing control signal to control the output unit to output the gate control signal of the current stage, so that the invalidation of the gate control signal does not affect the invalidation of the stage transmission signal. A sequential frequency reduction mode for multiple regions of the display panel can be achieved by setting whether the stage transmission signal has a stage transmission valid pulse, and an arbitrary frequency conversion mode for multiple regions of the display panel can be achieved by setting whether the gate control signal has a gate valid pulse (because the stage transmission valid pulse can always exist).

[0204] This document uses specific examples to illustrate the principles and implementation methods of this application. The description of the above embodiments is only used to help understand the method and core ideas of this application. At the same time, for technical personnel in this field, based on the ideas of this application, there will be changes in the specific implementation methods and application scope. In summary, the content of this specification should not be understood as limiting this application.

Claims

1. A gate drive module, wherein: It includes a frequency division signal line and a plurality of cascaded gate drive circuits, wherein the frequency division signal line is used to transmit a frequency division control signal to the plurality of gate drive circuits, and the gate drive circuit includes: A level transmission unit, comprising a level transmission receiving unit and a level transmission output unit, wherein the level transmission receiving unit is used to receive a level transmission signal generated by the upper-level gate driving circuit, and the level transmission output unit is electrically connected to the level transmission receiving unit through a first node and a second node, and is used to output the level transmission signal of the current level to the lower-level gate driving circuit according to the signal of the first node and the signal of the second node; an output unit, electrically connected to the stage transmission output unit through the first node, one of the second nodes, and a third node, and configured to output a gate control signal according to a signal of the first node, one of the second nodes, and a signal of the third node; and a stage transmission frequency division control unit, electrically connected to the stage transmission receiving unit through the first node or the second node, and electrically connected to the stage transmission output unit through a fourth node, and configured to control a signal of one of the first node and the second node according to the frequency division control signal, so as to control the stage transmission output unit to output the stage transmission signal of the current stage; An output frequency division control unit is connected between the first node, one of the second nodes and the third node, and is used to control the signal of the third node according to the frequency division control signal to control the output unit to output the gate control signal of this stage.

2. The gate driving module according to claim 1, wherein: The frequency division control signal includes a first frequency division control signal and a second frequency division control signal, and the frequency division signal line includes a first frequency division signal line for transmitting the first frequency division control signal and a second frequency division control signal line for transmitting the second frequency division control signal; Wherein, the first frequency division signal line is electrically connected to the output frequency division control unit to control the signal of the third node; The second frequency division signal line is electrically connected to the stage transmission frequency division control unit to control a signal of one of the first node and the second node.

3. The gate driving module according to claim 2, wherein: The output frequency division control unit comprises: a first frequency-dividing transistor, wherein a gate of the first frequency-dividing transistor is connected to the first frequency-dividing signal line, a source of the first frequency-dividing transistor is electrically connected to the first node or the second node, and a drain of the control transistor is electrically connected to the third node; The first frequency division control signal is used to control whether the third node is electrically connected to or disconnected from the first node or the second node.

4. The gate driving module according to claim 3, wherein: The output frequency division control unit also includes: a second frequency-dividing transistor, wherein a gate of the second frequency-dividing transistor is electrically connected to the fifth node of the stage transmission unit, a source of the second frequency-dividing transistor is electrically connected to the first frequency-dividing signal line, and a drain of the second frequency-dividing transistor is electrically connected to the gate of the first frequency-dividing transistor; The first frequency division control signal and the signal of the fifth node are used to control the third node to be electrically connected or disconnected with the first node or the second node; The signal of the fifth node is also used to control the stage transmission signal and the gate control signal output by the gate driving circuit of this stage.

5. The gate driving module according to claim 2, wherein: The level transmission and frequency division control unit comprises: a third frequency-dividing transistor, wherein the gate of the third frequency-dividing transistor is electrically connected to the second frequency-dividing signal line, the source of the first frequency-dividing transistor is electrically connected to the stage transmission receiving unit through the fourth node, and the drain of the third frequency-dividing transistor is electrically connected to the first node or the second node; The second frequency division control signal is used to control whether the fourth node is electrically connected to or disconnected from the first node or the second node.

6. The gate driving module according to claim 3, wherein: The level transmission and frequency division control unit comprises: a third frequency-dividing transistor, wherein the gate of the third frequency-dividing transistor is electrically connected to the second frequency-dividing signal line, the source of the first frequency-dividing transistor is electrically connected to the stage transmission receiving unit through the fourth node, and the drain of the third frequency-dividing transistor is electrically connected to the first node or the second node; The second frequency division control signal is used to control whether the fourth node is electrically connected to or disconnected from the first node or the second node.

7. The gate driving module according to claim 6, wherein: The level transmission output unit comprises: a first-stage transmission output transistor, wherein a gate of the first-stage transmission output transistor is electrically connected to the first node, a source of the first-stage transmission output transistor is electrically connected to the first voltage line to load a first voltage, and a drain of the first-stage transmission output transistor is electrically connected to a stage transmission output terminal in the gate driving circuit for outputting the stage transmission signal; A second-stage transmission output transistor, wherein the gate of the second-stage transmission output transistor is electrically connected to the second node, the source of the second-stage transmission output transistor is electrically connected to the second voltage line to load a second voltage, and the drain of the second-stage transmission output transistor is electrically connected to the stage transmission output end.

8. The gate driving module according to claim 7, wherein: The output unit comprises: a first output transistor, wherein a gate of the first output transistor is electrically connected to the third node, a source of the first output transistor is electrically connected to the first voltage line, and a drain of the first output transistor is electrically connected to a gate output terminal of the gate driving circuit for outputting the gate control signal; A second output transistor, wherein the gate of the second output transistor is electrically connected to the first node or the second node, the source of the second output transistor is electrically connected to the second voltage line, and the drain of the second output transistor is electrically connected to the gate output terminal.

9. The gate driving module according to claim 8, wherein: The gate driving circuit is electrically connected to at least one corresponding pixel driving circuit, the gate output terminal is electrically connected to a corresponding pixel transistor in each of the pixel driving circuits, and the first voltage is greater than the second voltage; The pixel transistor is an N-type transistor, and the drain of the third frequency-dividing transistor and the source of the first frequency-dividing control transistor are both electrically connected to the first node; Alternatively, the pixel transistor is a P-type transistor, and the drain of the third frequency-dividing transistor and the source of the first frequency-dividing control transistor are both electrically connected to the second node.

10. The gate driving module according to claim 6, wherein: The level transmission receiving unit comprises: a fourth node control unit, electrically connected to the clock signal line and the fourth node, and configured to control a signal of the fourth node according to a clock signal transmitted by the clock signal line; a second node control unit, electrically connected to the clock signal line and the second node, and configured to control a signal of the second node according to the clock signal; An input unit, wherein the input end of the input unit is electrically connected to the gate driving circuit of the upper level to load the level transmission signal generated by the gate driving circuit of the upper level, and the input end of the input unit is electrically connected to the fourth node control unit and the second node control unit, or is electrically connected to the fourth node control unit and the first node control unit.

11. The gate driving module according to claim 10, wherein: The stage transmission frequency division control unit and the output frequency division control unit are both electrically connected to the first node; The input unit comprises an input transistor, a gate of the input transistor is loaded with the clock signal, a source of the input transistor is configured as an input terminal of the input unit, and a drain of the input transistor is configured as an output terminal of the input unit; The fourth node control unit includes a first transistor, a seventh transistor, a second transistor and a third transistor connected in series, the gate of the seventh transistor is electrically connected to the drain of the input transistor, the source of the seventh transistor is loaded with the clock signal, the gate of the first transistor is loaded with the clock signal, the source of the first transistor is loaded with the second voltage, the drain of the first transistor is electrically connected to the gate of the second transistor and the drain of the seventh transistor, the drain of the second transistor is electrically connected to the source of the third transistor, the source of the second transistor and the gate of the third transistor are both loaded with the clock signal, and the drain of the third transistor is electrically connected to the fourth node; The second node control unit includes a fourth transistor, a first capacitor, a fifth transistor and a sixth transistor arranged in series, the gate of the fourth transistor is loaded with a control signal, the source of the fourth transistor is loaded with the first voltage, the drain of the fourth transistor is electrically connected to the second node, the gate of the fifth transistor is electrically connected to the drain of the first transistor, the source of the fifth transistor is loaded with the first voltage, the drain of the fifth transistor is electrically connected to the source of the sixth transistor, the drain of the sixth transistor is loaded with the clock signal, the gate of the sixth transistor is also loaded with the level transmission signal generated by the upper gate drive circuit, and the first capacitor is electrically connected between the gate and the drain of the sixth transistor.

12. The gate driving module according to claim 11, wherein: The second node control unit also includes: a tenth transistor, wherein a source of the tenth transistor is loaded with the level transmission signal generated by the upper gate driving circuit, a gate of the tenth transistor is loaded with the clock signal, and a drain of the tenth transistor is electrically connected to the gate of the sixth transistor; an eleventh transistor, wherein a gate and a source of the eleventh transistor are both electrically connected to the gate of the sixth transistor, and a drain of the eleventh transistor is electrically connected to the second node.

13. A display panel, wherein: include: The gate drive module as claimed in claim 2; A panel body, comprising a plurality of sub-pixels and a plurality of scanning lines, wherein the plurality of sub-pixels comprise light-emitting devices and a pixel driving circuit for driving the light-emitting devices to emit light, wherein the pixel driving circuit comprises at least one transistor; The gate control signal output by the gate driving circuit is transmitted to the gates of the plurality of transistors in the corresponding plurality of pixel driving circuits via the corresponding scanning lines.

14. The display panel according to claim 13, wherein: The output frequency division control unit comprises: a first frequency-dividing transistor, wherein a gate of the first frequency-dividing transistor is connected to the first frequency-dividing signal line, a source of the first frequency-dividing transistor is electrically connected to the first node or the second node, and a drain of the control transistor is electrically connected to the third node; The first frequency division control signal is used to control whether the third node is electrically connected to or disconnected from the first node or the second node.

15. The display panel according to claim 13, wherein: The display panel is in a frequency reduction mode and a frequency increase mode in a time-sharing manner, and the plurality of gate driving circuits include a plurality of first gate driving circuits cascaded together and a plurality of second gate driving circuits cascaded together after the plurality of first gate driving circuits; The plurality of sub-pixels include a plurality of first sub-pixels electrically connected to a plurality of the first gate driving circuits, and a plurality of second sub-pixels electrically connected to a plurality of the second gate driving circuits, the plurality of the first sub-pixels constitute a first display area, and the plurality of the second sub-pixels constitute a second display area; In the frequency reduction mode, the refresh rate of the first display area is greater than the refresh rate of the second display area; In the frequency-upgrading mode, the refresh rate of the first display area is lower than the refresh rate of the second display area.

16. The display panel according to claim 15, wherein: In the frequency reduction mode, the first frequency division control signal is used to control the third node in each stage of the gate driving circuit to be electrically connected to the first node or the second node; In the first type of frame, the second frequency-divided control signal is used to control the first node or the second node in the first gate driving circuit to be electrically connected to the fourth node, so as to control the output gate control signal to have a gate effective pulse, so as to turn on the corresponding light-emitting device; In the first type of frame, the second frequency division control signal is also used to control the first node or the second node and the fourth node in the second gate drive circuit to open the circuit, so as to control the output gate control signal to not have the gate effective pulse, so as not to turn on the corresponding light-emitting device.

17. The display panel according to claim 15, wherein: In the frequency reduction mode, the second frequency division control signal is used to control the fourth node in each stage of the gate driving circuit to be electrically connected to the first node or the second node; In the second type of frame, the first frequency division control signal is used to control the third node in the first gate driving circuit to be electrically connected to the first node or the second node, so as to control the output gate control signal to have a gate effective pulse, so as to turn on the corresponding light emitting device; In the second type of frame, the first frequency division control signal is also used to control the circuit between the third node and the first node or the second node in the second gate drive circuit to be disconnected, so as to control the output gate control signal to not have the gate effective pulse, so as not to turn on the corresponding light-emitting device.

18. The display panel according to claim 15, wherein: In the frequency-up mode, the second frequency-division control signal is used to control the fourth node in each stage of the gate driving circuit to be electrically connected to the first node or the second node; In the third type of frame, the first frequency division control signal is used to control the circuit between the third node and the first node or the second node in the first gate driving circuit to be disconnected, so as to control the output gate control signal to have no gate effective pulse, so as not to turn on the corresponding light emitting device; In the third type of frame, the first frequency-division control signal is used to control the first node or the second node in the second gate drive circuit to be electrically connected to the fourth node, so as to control the output gate control signal to have the gate effective pulse to turn on the corresponding light-emitting device.

19. The display panel according to claim 16, wherein: In the frequency-up mode, the second frequency-division control signal is used to control the fourth node in each stage of the gate driving circuit to be electrically connected to the first node or the second node; In the third type of frame, the first frequency division control signal is used to control the circuit between the third node and the first node or the second node in the first gate driving circuit to be disconnected, so as to control the output gate control signal to have no gate effective pulse, so as not to turn on the corresponding light emitting device; In the third type of frame, the first frequency-division control signal is used to control the first node or the second node in the second gate drive circuit to be electrically connected to the fourth node, so as to control the output gate control signal to have the gate effective pulse to turn on the corresponding light-emitting device.

20. The display panel according to claim 13, wherein: The gate driving module comprises n-stage gate driving circuits cascaded in sequence, where n is a positive integer greater than or equal to 2, and the n-stage gate driving circuits are all loaded with the same clock signal; In one frame, the clock signal is alternately equal to the first clock voltage and the second clock voltage during the period of time when it effectively acts on the gate driving circuit of the i-th level to the (i+k)-th level, and i and k are both positive integers greater than or equal to 1; Among them, when the gate control signals output by the gate driving circuits of the (i+k+1)th to nth levels do not include the gate effective pulse, the clock signal is always equal to the first clock voltage or the second clock voltage during the period when it effectively acts on the gate driving circuits of the (i+k+1)th to nth levels.

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