CXL data transmission board and data transmission control method

Abstract

A compute express link (CXL) data transmission board and a data transmission control method. The CXL data transmission board comprises: a control chip, wherein the control chip is a chip supporting a CXL protocol, and uplink ports and downlink ports are deployed on the control chip; the uplink ports connected to hosts, wherein the hosts are devices supporting a peripheral component interconnect express (PCIe) protocol or devices supporting a CXL protocol; and the downlink ports connected to processors and / or memory modules, wherein the downlink ports are correspondingly connected to the uplink ports, and the hosts are configured to transmit data to the corresponding downlink ports by means of the uplink ports, so as to transmit the data to the processors and / or the memory modules by means of the downlink ports. By means of the present application, the problem in the related art that resources cannot be re-allocated on the basis of different workloads is solved, achieving the effect of flexibly allocating resources.

Description

CXL data transmission board and method for controlling data transmission

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to a Chinese patent application filed with the Patent Office of China on June 28, 2023, with application number 202310776401.5 and application name “CXL data transmission board and method for controlling data transmission”, the entire contents of which are incorporated herein by reference. Technical Field

[0003] The embodiments of the present application relate to the field of computers, and more particularly to a CXL data transmission board and a method for controlling data transmission. Background Art

[0004] With the development of cloud computing applications, information technology has gradually permeated all areas of society. People's daily work increasingly involves communicating online, and the amount of network data is also growing explosively. As the core equipment for processing and storing data, servers are facing increasingly higher performance and configuration requirements. The development of current server technology is facing a bottleneck in memory architecture: the growth in the number of memory channels has not kept pace with the increase in the number of CPU (Central Processing Unit) cores, resulting in a decrease in the memory bandwidth that each core can handle, limiting processor performance.

[0005] Currently, memory and processors are tightly coupled, with memory deployed within server nodes. Memory costs account for a significant portion of the overall server cost, but in practice, memory usage is inefficient. Some memory spaces are never accessed, while others store relatively cold data that is rarely accessed. This portion of memory fails to fully realize its value. The related technology, Compute Express Link (CXL), an open interconnect standard, cannot reallocate resources based on different workloads.

[0006] This shows that the related art has the problem of being unable to reallocate resources according to different workloads.

[0007] Summary of the Invention

[0008] The embodiments of the present application provide a CXL data transmission board and a method for controlling data transmission, so as to at least solve the problem in the related art of being unable to reallocate resources according to different workloads.

[0009] According to a first aspect, a CXL data transmission board is provided, comprising: a control chip, the control chip being a chip supporting the open interconnection standard CXL protocol, and having an upstream port and a downstream port deployed on the control chip; the upstream port being connected to a host, wherein the host is a device supporting the high-speed serial computer expansion bus standard PCIe protocol or a device supporting the CXL protocol; the downstream port being connected to a processor and / or a memory module, the downstream port being correspondingly connected to the upstream port, the host being configured to transmit data via the upstream port to the corresponding downstream port, so as to transmit the data via the downstream port to the processor and / or the memory module, wherein both the processor and the memory module are devices supporting the PCIe protocol or the CXL protocol.

[0010] According to a second aspect, a method for controlling data transmission is provided, comprising: receiving a data request sent by a host through an upstream port, wherein the data request includes data to be transmitted, and the host is a device supporting the PCIe protocol or a device supporting the CXL protocol; in response to the data request, searching for routing information of the host from a routing table; and transmitting the data to a processor and / or a memory module connected to a downstream port corresponding to the upstream port according to the routing information, wherein the downstream port is correspondingly connected to the upstream port, and the processor and the memory module are both devices supporting the PCIe protocol or devices supporting the CXL protocol.

[0011] According to a third aspect, a link switching control system is provided. The link switching control system includes the above-mentioned CXL data transmission board.

[0012] According to a fourth aspect, a non-volatile readable storage medium is further provided, in which a computer program is stored, wherein the computer program is configured to execute the steps of any of the above method embodiments when running.

[0013] According to a fifth aspect, an electronic device is also provided, comprising a memory and a processor, wherein a computer program is stored in the memory, and the processor is configured to run the computer program to execute the steps in any one of the above method embodiments.

[0014] Through this application, the control chip in the CXL data transmission board is a chip that supports the CXL protocol and is equipped with an uplink port and a downlink port. The uplink port is connected to the host, where the host is a device that supports the PCIe protocol or a device that supports the CXL protocol. The downlink port is connected to the processor and / or memory module, and the downlink port is connected to the uplink port accordingly. This allows the host to connect to both the processor and the memory module, allowing the number of processors and memory modules to be flexibly configured according to actual needs. Therefore, it can solve the problem of the related art that resources cannot be reallocated according to different workloads, and achieve the effect of flexible resource allocation. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] FIG1 is a schematic structural diagram of a CXL data transmission board according to an embodiment of the present application;

[0016] FIG2 is a schematic diagram of a CXL data transmission board according to an embodiment of the present application;

[0017] FIG3 is a connection diagram at the switch level according to an embodiment of the present application;

[0018] FIG4 is a second flowchart of a method for controlling signal transmission according to an embodiment of the present application;

[0019] FIG5 is a schematic diagram of an external manager managing a control chip according to an embodiment of the present application;

[0020] FIG6 is a flowchart of a method for controlling data transmission according to an embodiment of the present application;

[0021] FIG7 is a schematic diagram of an electronic device according to an embodiment of the present application. DETAILED DESCRIPTION

[0022] The embodiments of the present application will be described in detail below with reference to the accompanying drawings and in combination with the embodiments.

[0023] It should be noted that the terms "first", "second", etc. in the description and claims of this application and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence.

[0024] The following is an explanation of the relevant technologies in this embodiment:

[0025] CXL (Compute Express Link) is an open industry standard for high-bandwidth, low-latency device interconnection. It can be used to connect CPUs and GPUs, memory, and smart network cards.

[0026] GPU, Graphics Processing Unit;

[0027] CXL SW, Compute Express Link switch;

[0028] CPU, Central Processing Unit.

[0029] In this embodiment, a CXL data transmission board is provided. FIG1 is a schematic structural diagram of a CXL data transmission board according to an embodiment of the present application. As shown in FIG1 , the CXL data transmission board includes:

[0030] The control chip supports the open interconnection standard CXL protocol and has both uplink and downlink ports.

[0031] The uplink port is connected to a host, wherein the host is a device that supports the high-speed serial computer expansion bus standard PCIe (Peripheral Component Interconnect express) protocol or a device that supports the CXL protocol;

[0032] The downstream port is connected to the processor and / or memory module, and the downstream port is correspondingly connected to the upstream port. The host is configured to transmit data to the corresponding downstream port through the upstream port, so as to transmit data to the processor and / or memory module through the downstream port, wherein the processor and memory module are both devices that support the PCIe protocol or devices that support the CXL protocol.

[0033] The CXL data transmission board in this embodiment can be applied to scenarios requiring high-speed data transmission and large-scale data processing, such as data centers, high-performance computing, artificial intelligence cloud computing, and the like.

[0034] In this embodiment, the control chip supports the CXL protocol and includes a high-speed interconnect architecture, the CXL Switch Fabric. The CXL Switch Fabric can connect multiple CXL devices to form a shared computing platform. The CXL Switch Fabric provides a scalable and flexible infrastructure for CXL devices, enabling communication and data transmission between them by providing high-speed point-to-point connections. CXL devices can be hosts, processors, memory modules, and other devices.

[0035] The CXL Switch Fabric architecture is optionally divided into three layers: the transaction layer, the link layer, and the physical layer. To ensure compatibility with both PCIe and CXL protocols, the CXL Switch Fabric provides a Flex Bus port, allowing devices to select between PCIe and CXL devices. The CXL.cache and CXL.mem protocols are combined to share a common transaction layer and link layer, while CXL.io has its own transaction layer and link layer. The CXL link layer interacts with the CXL ARB or MUX to interleave traffic from the two logical flows. The physical layer also contains two sublayers: the logical sublayer and the electrical sublayer. The logical sublayer can switch between PCIe and CXL modes, while the electrical sublayer complies with the PCIe specification. In the transaction layer, CXL.io provides a non-coherent load or store interface for I / O devices.

[0036] Optionally, the processor can be a CPU or a GPU. The CPU and GPU can bypass the PCIe protocol and use the CXL protocol to share and access each other's memory resources. Through the CXL protocol, the CPU and GPU are connected to form a single, massive stack memory pool. In this embodiment, the GPU box can support both the PCIe protocol and the CXL protocol. As shown in Figure 2, the CXL data transmission board can be a CXL switch board, the control chip can be a CXL switch chip, and the processor can be a GPU. The upstream device can be connected to multiple hosts, and the downstream device can be connected to the GPU box or a memory module, providing flexible configuration. Each host can also be connected to different downstream devices, and the connection relationship between the host host and downstream devices can be changed by changing the burned information of the CXL switch chip. The number of connected upstream and downstream devices can be determined by the function of the CXL switch chip.

[0037] Optionally, when the downstream device is a GPU BOX, the GPU BOX supports 16 GPU slots internally and is interconnected with the CXL Switch chip through a CDFP cable. The onboard CPLD (Complex Programmable Logic Device) is set to control the power-on sequence of the BOX, and the onboard bus master controller BMC (Bus Master Controller) is set to manage the working status of the GPU.

[0038] Optionally, the memory module is a device based on the CXL bus protocol, which can realize remote memory expansion and multi-host memory sharing. The CDFP interface of the memory board is interconnected with the CXL Switch board through a CDFP cable. The onboard BMC and CPLD are responsible for the management of the CXL Switch board, including heat dissipation control, power on and off, and status indication.

[0039] Through this application, the control chip in the CXL data transmission board is a chip that supports the CXL protocol and is equipped with an uplink port and a downlink port. The uplink port is connected to the host, where the host is a device that supports the PCIe protocol or a device that supports the CXL protocol. The downlink port is connected to the processor and / or memory module, and the downlink port is connected to the uplink port accordingly. This allows the host to connect to both the processor and the memory module, allowing the number of processors and memory modules to be flexibly configured according to actual needs. Therefore, it can solve the problem of the related art that resources cannot be reallocated according to different workloads, and achieve the effect of flexible resource allocation.

[0040] In an exemplary embodiment, there are N upstream ports and N downstream ports, where N is a natural number greater than 1. The value of N is determined by the function of the control chip. For example, N can be 16 or 4. As shown in Figure 2, the CXL Switch chip has six upstream and downstream ports. By flexibly setting the value of N, this embodiment allows for flexible configuration of connected upstream and downstream devices, enabling flexible resource allocation.

[0041] In an exemplary embodiment, the control chip includes at least one of the following:

[0042] The control unit is configured to control the topology of the CXL link between the upstream port and the downstream port, wherein the CXL link is configured to connect the corresponding upstream port and downstream port.

[0043] The management unit is configured to manage routing information between the host and the processor and / or memory module.

[0044] The identification unit is connected to the processor and / or memory module, and is configured to identify the protocol type supported by the processor and / or memory module when the host establishes a connection with the processor and / or memory module.

[0045] In this embodiment, when the control chip is a CXL Switch Fabric architecture chip, the control unit may be composed of multiple CXL Switch Fanouts. CXL switch fanout refers to the process of replicating a CXL link to multiple additional links within a CXL Switch Fabric. This process allows multiple devices to simultaneously access and share devices on the same CXL link, thereby improving system performance and scalability. The control chip can implement CXL switch fanout because CXL supports a point-to-point topology, allowing multiple devices to communicate with each other over a CXL link and forward data packets within the link. The primary purpose of CXL switch fanout is to improve connection efficiency and data throughput between multiple devices in a system.

[0046] The management unit can consist of multiple CXL Switch Roots. CXL devices connect to the CXL Switch Fabric through CXL ports. The CXL Switch Root maintains a routing table to store and manage routing information between nodes in the network. When a CXL device sends a data request, the routing table selects the optimal path and forwards the data to the destination CXL device. For example, data from HOST1 is transferred to the memory module for storage. The traffic manager of the CXL port on the CXL data transmission board stores the data sequentially in a buffer for fast processing and transmission. Based on the input port and routing table information, the CXL Switch Fabric selects the optimal path in the buffer and forwards the data to the port of the destination CXL device. While forwarding data, the CXL Switch Fabric also ensures stable communication speed and consistent performance within the control chip. When a CXL device needs to return data, the CXL Switch Fabric also uses routing information and the status of the buffer to find the optimal path and transmit the data to the destination device.

[0047] The identification unit can use BIOS commands to identify whether the port is connected to a PCLE device or a CXL device. For example, taking the CPU of the Intel Eagle Stream series as an example, the CXL interconnection is completely dependent on the PCIe 5.0 electrical layer, and all topologies rely on PCIe. The Eagle Stream CPU can support CXL 4X16 channels. CXL and PCI Express devices can work simultaneously under a given port, with 8 lanes for each device. Any x16 PCI Express port can be connected to a PCI Express device or a CXL device. The identification unit can automatically detect whether the other end is a PCI Express card or a CXL device, and dynamically configure the link. When connecting a CXL device, the CXL mode should be set in advance in the BIOS, and the BIOS command can also be used to identify whether the port is connected to a PCLE device or a CXL device. This embodiment can control the link topology and routing information, as well as identify the type of device, through the control chip, so that resources can be quickly allocated.

[0048] In an exemplary embodiment, the number of hosts is M, the number of processors is P, and the number of memory modules is K, wherein M, P, and K are all natural numbers greater than or equal to 1.

[0049] In this embodiment, when M is greater than 1, M hosts share K memory modules. When N is 16, M is greater than or equal to 2 and less than or equal to 7. When N is 16, M is 7, and P is 7, there is a one-to-one correspondence between processors and hosts, or one host corresponds to multiple processors, with data transmitted between the hosts and processors using the PCIe protocol. When K is greater than 1, one host corresponds to multiple memory modules, which form a host's memory resource pool. Data is transmitted between the hosts and memory modules using the CXL protocol. The number of hosts is directly proportional to the number of memory modules. For example, if the control chip uses a CXL 2.0 switch chip, the control chip is compatible with PCIe 5.0 and supports switching between different firmware (programs written to EPROM (Erasable Programmable Read-Only Memory) or EEPROM (Electrically Erasable Programmable Read-Only Memory)). The control chip has a total of 16 ports, each of which can be configured as PCIe or CXL, supporting mixed PCIe and CXL scenarios. It can connect up to 7 hosts and a minimum of 2. In high-speed computing scenarios, the upstream device can connect to seven hosts, and the downstream device can connect to seven GPUs, with each host connected to one GPU, enabling multi-channel parallel data processing. Alternatively, it can connect to two hosts, each providing four X16 signals. Host 1 connects to four GPUs for accelerated data processing, while host 2 connects to four X16 memory modules for data read and storage. Alternatively, it can connect to four hosts upstream and eight X16 memory modules downstream, using the CXL protocol. Each host has two X16 ports, each connected to two X16 memory modules.

[0050] Optionally, as shown in Figure 3, the controller chip's switch layer can consist of multiple VCXLs, which can be mapped to specific physical ports based on host instructions, supporting the allocation of up to 16 logical storage spaces. Each VCXL has its own ID, which is used to bind or unbind the VCXL to a physical port under host control, enabling configuration between different ports.

[0051] The ports in this embodiment can be flexibly configured based on actual application requirements, and the number of hosts and the port resource information of the hosts can also be flexibly configured, thereby achieving the purpose of flexible resource allocation.

[0052] In an exemplary embodiment, the CXL data transmission board further includes a connector connecting the control chip and a manager. The manager is configured to manage the operation of the control chip via the connector. In this embodiment, the connector can be a cable assembly connector MCIO. As shown in Figure 2, the CXL Switch chip connects to an external manager CPU via the MCIO connector. As shown in Figure 4, the manager CPU manages the I2C, RESET, and status indicators of the CXL Switch chip. This embodiment manages the control chip through an external manager, enabling accurate control of the operating status of the control chip.

[0053] In one exemplary embodiment, the CXL data transmission board further includes a clock generator connected to the control chip and configured to generate a first initialization clock signal for activating the control chip and, after the control chip is activated, to generate a first clock signal that coordinates the clock frequency of the control chip. In this embodiment, the clock generator is connected to the control chip, processor, and memory module via a preset interface and is configured to generate a second initialization clock signal for activating the control chip, processor, and memory module, respectively, and, after the control chip, processor, and memory module are activated, to generate a second clock signal that coordinates the clock frequencies of the control chip, processor, and memory module. As shown in Figure 4, the CXL data transmission board supports an RJ45 interface, which serves as a BMC management network port. Each CDFP interface is equipped with a set of red and green bi-color lights. Based on the clock signal generated by the clock generator, the red light is off when data transmission is normal and remains on after a fault occurs. The green light remains on when no data is being transmitted and flashes at a frequency of 1 Hz during normal data transmission. This embodiment uses the clock generator to accurately monitor data transmission.

[0054] In an exemplary embodiment, the CXL data transmission board also includes: a debugging device, which is connected to the control chip and is configured to debug the CXL performance of the control chip. In this embodiment, the scope of debugging of the debugging device includes: CXL margin testing, which is the same as PCIe debugging; CXL link speed, width, and compliance testing; enabling or disabling interleaving mode to perform system stress or performance or bandwidth testing. In addition, it also includes CXL compliance testing, CXL stress testing, CXL delay testing, etc. In addition, it also includes link and protocol error handling, using PCIe ERR messages through CXL.io, CXL.io protocol errors are recorded and displayed. This embodiment can ensure the correctness of data transmission through debugging of the debugging device.

[0055] The method embodiments provided in the embodiments of the present application can be executed in a mobile terminal, a computer terminal or a similar computing device. Taking operation on a mobile terminal as an example, Figure 5 is a hardware structure block diagram of a mobile terminal of a method for controlling data transmission in an embodiment of the present application. As shown in Figure 5, the mobile terminal may include one or more (only one is shown in Figure 5) processors 502 (the processor 502 may include but is not limited to a processing device such as a microprocessor MCU or a programmable logic device FPGA) and a memory 504 configured to store data, wherein the above-mentioned mobile terminal may also include a transmission device 506 and an input and output device 508 configured to have a communication function. It can be understood by those skilled in the art that the structure shown in Figure 5 is only for illustration and does not limit the structure of the above-mentioned mobile terminal. For example, the mobile terminal may also include more or fewer components than those shown in Figure 1, or have a configuration different from that shown in Figure 5.

[0056] The memory 504 can be configured to store computer programs, for example, software programs and modules of application software, such as the computer program corresponding to the method for controlling data transmission in the embodiment of the present application. The processor 502 executes various functional applications and data processing by running the computer program stored in the memory 504, that is, implementing the above-mentioned method. The memory 504 may include a high-speed random access memory, and may also include a non-volatile memory, such as one or more magnetic storage devices, flash memory, or other non-volatile solid-state memory. In some instances, the memory 504 may include a memory remotely located relative to the processor 502, and these remote memories may be connected to the mobile terminal via a network. Examples of the above-mentioned network include, but are not limited to, the Internet, an intranet, a local area network, a mobile communication network, and combinations thereof.

[0057] The transmission device 506 is configured to receive or transmit data via a network. Examples of such networks may include wireless networks provided by the mobile terminal's communications provider. In one embodiment, the transmission device 506 includes a network interface controller (NIC), which can be connected to other network devices via a base station to enable communication with the Internet. In another embodiment, the transmission device 506 may be a radio frequency (RF) module configured to communicate with the Internet wirelessly.

[0058] In this embodiment, a method for controlling data transmission is provided. FIG6 is a flow chart of the method for controlling data transmission according to an embodiment of the present application. As shown in FIG6 , the flow chart includes the following steps:

[0059] Step S602: receiving a data request sent by a host through an uplink port, wherein the data request includes data to be transmitted, and the host is a device supporting the PCIe protocol or a device supporting the CXL protocol;

[0060] Step S604, in response to the data request, searching the routing information of the host from the routing table;

[0061] In step S606, the data is transmitted to the processor and / or memory module connected to the downlink port corresponding to the uplink port according to the routing information, wherein the downlink port is connected to the uplink port correspondingly, and the processor and memory module are both devices supporting the PCIe protocol or devices supporting the CXL protocol.

[0062] The execution subject of the above steps may be a processor provided in a control chip, or a processor or processing device provided relatively independently from a terminal or a server, etc., but is not limited thereto.

[0063] This embodiment can be applied to scenarios that require high-speed data transmission and large-scale data processing, such as data centers, high-performance computing, artificial intelligence cloud computing, and the like.

[0064] In this embodiment, the control chip supports the CXL protocol and includes a high-speed interconnect architecture, the CXL Switch Fabric. The CXL Switch Fabric can connect multiple CXL devices to form a shared computing platform. The CXL Switch Fabric provides a scalable and flexible infrastructure for CXL devices, enabling communication and data transmission between them by providing high-speed point-to-point connections. CXL devices can be hosts, processors, memory modules, and other devices.

[0065] The CXL Switch Fabric architecture is optionally divided into three layers: the transaction layer, the link layer, and the physical layer. To ensure compatibility with both PCIe and CXL protocols, the CXL Switch Fabric provides a Flex Bus port, allowing devices to select between PCIe and CXL devices. The CXL.cache and CXL.mem protocols are combined to share a common transaction layer and link layer, while CXL.io has its own transaction layer and link layer. The CXL link layer interacts with the CXL ARB or MUX to interleave traffic from the two logical flows. The physical layer also contains two sublayers: the logical sublayer and the electrical sublayer. The logical sublayer can switch between PCIe and CXL modes, while the electrical sublayer complies with the PCIe specification. In the transaction layer, CXL.io provides a non-coherent load or store interface for I / O devices.

[0066] Optionally, the processor can be either a CPU or a GPU. The CPU and GPU can bypass the PCIe protocol and use the CXL protocol to share and access each other's memory resources. Through the CXL protocol, the CPU and GPU are effectively connected into a single, massive stacked memory pool. In this embodiment, the GPU BOX supports both the PCIe protocol and the CXL protocol. As shown in Figure 2, the CXL data transmission board can be a CXL Switch board, the control chip can be a CXL Switch chip, and the processor can be a GPU. Uplink devices can connect to multiple hosts, and downlink devices can connect to the GPU BOX or memory modules, providing flexible configuration. Furthermore, each host can connect to different downlink devices, and the connection relationship between the host and downlink devices can be changed by changing the information programmed into the CXL Switch chip. The number of connected uplink and downlink devices can be determined by the functionality of the CXL Switch chip.

[0067] Optionally, when the downstream device is a GPU BOX, the GPU BOX supports 16 GPU slots internally and is interconnected with the CXL Switch chip through a CDFP cable. The onboard CPLD is set to control the power-on sequence of the BOX, and the onboard bus master controller BMC (Bus Master Controller) is set to manage the working status of the GPU.

[0068] Optionally, the memory module is a device based on the CXL bus protocol, which can realize remote memory expansion and multi-host memory sharing. The CDFP interface of the memory board is interconnected with the CXL Switch board through a CDFP cable. The onboard BMC and CPLD are responsible for the management of the CXL Switch board, including heat dissipation control, power on and off, and status indication.

[0069] Through the above steps, the control chip in the CXL data transmission board is a CXL-compliant chip and is equipped with both an upstream port and a downstream port. The upstream port is connected to the host, which is either a PCIe-compliant or CXL-compliant device. The downstream port is connected to the processor and / or memory module. The downstream ports are connected to the upstream ports in a corresponding manner, allowing the host to connect to both the processor and the memory module, allowing for flexible configuration of the number of processors and memory modules based on actual needs. This solves the problem of related technologies that prevent resources from being reallocated based on different workloads, achieving flexible resource allocation.

[0070] In one exemplary embodiment, there are N upstream ports and N downstream ports, where N is a natural number greater than 1. The value of N is determined by the function of the control chip. For example, N can be 16 or 4. As shown in Figure 2, the CXL Switch chip has six upstream and downstream ports. This embodiment allows for flexible configuration of connected upstream and downstream devices through the flexible device N value, enabling flexible resource allocation.

[0071] In an exemplary embodiment, before searching a routing table for host routing information in response to a data request, the method further includes: setting a topology of CXL links between N upstream ports and N downstream ports, wherein the CXL links are configured to connect corresponding upstream ports and downstream ports; determining a route between the host and a processor and / or memory module based on the CXL link topology to obtain a routing table. Transmitting data to a processor and / or memory module connected to a downstream port corresponding to an upstream port according to the routing information includes: caching the data in a cache unit via the downstream port; selecting a target route from the routing information; and transmitting the data in the cache unit to the processor and / or memory module connected to the downstream port according to the target route.

[0072] In this embodiment, when the control chip is a CXL switch fabric architecture chip, the control unit may be composed of multiple CXL switch fanouts. CXL switch fanout refers to the process of replicating a CXL link to multiple additional links within a CXL switch fabric. This process allows multiple devices to simultaneously access and share devices on the same CXL link, thereby improving system performance and scalability. The control chip can implement CXL switch fanout because CXL supports a point-to-point topology, allowing multiple devices to communicate with each other over a single CXL link and forwarding data packets within the link. The primary purpose of CXL switch fanout is to improve connection efficiency and data throughput between multiple devices in the system. CXL devices connect to the CXL switch fabric through CXL ports. The CXL switch root maintains a routing table to store and manage routing information between nodes in the network. When a CXL device sends a data request, the routing table selects the optimal path and forwards the data to the destination CXL device, for example, transferring data from HOST1 to the memory module for storage. The traffic manager of the CXL port on the CXL data transmission board stores the data sequentially in a buffer for rapid processing and transmission. Based on the input port and routing table information, the CXL Switch Fabric selects the optimal path within the buffer and forwards the data to the port of the target CXL device. While forwarding data, the CXL Switch Fabric also ensures stable communication speed and consistent performance within the controller chip. When the CXL device needs to return data, the CXL Switch Fabric also uses routing information and the status of the buffer to find the optimal path and transmit the data to the target device.

[0073] In one exemplary embodiment, before transmitting data to a processor and / or memory module connected to a downstream port corresponding to an upstream port according to routing information, the method further includes: when a connection is established between the host and the processor and / or memory module, identifying the protocol type supported by the processor and / or memory module, and transmitting data to the processor and / or memory module according to the protocol type supported by the processor and / or memory module. In this embodiment, BIOS commands are used to identify whether the port is connected to a PCI Express (PCLE) device or a CXL device. For example, the host uses an Intel Eagle Stream series CPU. The CXL interconnect relies entirely on the PCIe 5.0 electrical layer, and all topologies rely on PCIe. Eagle Stream CPUs can support 4x16 CXL lanes. CXL and PCI Express devices can operate simultaneously on a given port, with each device having 8 lanes. Any x16 PCI Express port can be connected to either a PCI Express device or a CXL device. The identification unit can automatically detect whether the other end is a PCI Express card or a CXL device and dynamically configure the link. When connecting to a CXL device, the CXL mode should be set in advance in the BIOS. BIOS commands can also be used to identify whether the port is connected to a PCLE device or a CXL device. This embodiment uses the control chip to control link topology and routing information, as well as identify device types, allowing for rapid resource allocation.

[0074] In one exemplary embodiment, there are M hosts, P processors, and K memory modules, where M, P, and K are all natural numbers greater than or equal to 1. When M is greater than 1, the M hosts share the K memory modules. When N is 16, M is greater than or equal to 2 and less than or equal to 7. When N is 16, M is 7 and P is 7. There is a one-to-one correspondence between processors and hosts, or one host corresponds to multiple processors. Data is transmitted between the hosts and processors via the PCIe protocol.

[0075] For example, if the controller chip uses a CXL 2.0 switch, it is compatible with PCIe 5.0 and supports switching between different firmware (programs written in EPROM (Erasable Programmable Read-Only Memory) or EEPROM (Electrically Erasable Programmable Read-Only Memory)). The controller chip has a total of 16 ports, each of which can be configured as PCIe or CXL, supporting mixed PCIe and CXL scenarios. It can connect up to seven hosts and a minimum of two. In high-speed computing applications, the upstream device can connect to seven hosts and the downstream device can connect to seven GPUs, with each host connected to one GPU for multi-channel parallel data processing. Alternatively, it can connect to two hosts, each with four X16 signals. Host 1 can connect to four GPUs for accelerated data processing, while host 2 can connect to four X16 memory modules for data access. Alternatively, it can connect to four hosts upstream and eight X16 memory modules downstream, using the CXL protocol. Each host has two X16 ports for two X16 memory modules.

[0076] Optionally, as shown in Figure 3, the controller chip's switch layer can consist of multiple VCXLs, which can be mapped to specific physical ports based on host instructions, supporting the allocation of up to 16 logical storage spaces. Each VCXL has its own ID, which is used to bind or unbind the VCXL to a physical port under host control, enabling configuration between different ports.

[0077] The ports in this embodiment can be flexibly configured based on actual application requirements, and the number of hosts and the port resource information of the hosts can also be flexibly configured, thereby achieving the purpose of flexible resource allocation.

[0078] In an exemplary embodiment, when K is greater than 1, one host corresponds to multiple memory modules, and multiple memory modules constitute a memory resource pool of the host. Data is transmitted between the host and the memory modules via the CXL protocol, and the number of hosts is directly proportional to the number of memory modules.

[0079] Through the description of the above implementation methods, those skilled in the art can clearly understand that the method according to the above embodiment can be implemented by means of software plus the necessary general hardware platform, and of course it can also be implemented by hardware, but in many cases the former is a better implementation method. Based on this understanding, the technical solution of the present application, or the part that contributes to the relevant technology, can be embodied in the form of a software product, which is stored in a non-volatile readable storage medium (such as ROM / RAM, magnetic disk, optical disk), and includes a number of instructions for enabling a terminal device (which can be a mobile phone, computer, server, or network device, etc.) to execute the methods of each embodiment of the present application.

[0080] This embodiment further provides a link switching control system, which includes the aforementioned CXL data transmission board. This device is configured to implement the aforementioned embodiment and optional implementations, and details already described will not be repeated.

[0081] An embodiment of the present application further provides a non-volatile readable storage medium, in which a computer program is stored. The computer program is configured to execute the steps of any of the above method embodiments when running.

[0082] In an exemplary embodiment, the above-mentioned non-volatile readable storage medium may include, but is not limited to: a USB flash drive, a read-only memory (ROM), a random access memory (RAM), a mobile hard disk, a magnetic disk or an optical disk, and other non-volatile readable storage media that can store computer programs.

[0083] An embodiment of the present application further provides an electronic device, comprising a memory and a processor, wherein the memory stores a computer program, and the processor is configured to run the computer program to execute the steps in any one of the above method embodiments.

[0084] An embodiment of the present application also provides an electronic device. Figure 7 is a schematic diagram of an electronic device according to an embodiment of the present application. As shown in Figure 7, it includes a memory and a processor. The memory stores a computer program, and the processor is configured to run the computer program to execute the steps in any of the above method embodiments.

[0085] In an exemplary embodiment, the electronic device may further include a transmission device and an input / output device, wherein the transmission device is connected to the processor, and the input / output device is connected to the processor.

[0086] The examples in this embodiment can refer to the examples described in the above embodiments and exemplary implementation modes, and this embodiment will not be described in detail here.

[0087] Obviously, those skilled in the art should understand that the modules or steps of the present application described above can be implemented using a general-purpose computing device, they can be concentrated on a single computing device, or distributed across a network composed of multiple computing devices, they can be implemented using program code executable by the computing device, and thus, they can be stored in a storage device and executed by the computing device, and in some cases, the steps shown or described can be performed in a different order than herein, or they can be fabricated into separate integrated circuit modules, or multiple modules or steps can be fabricated into a single integrated circuit module for implementation. Thus, the present application is not limited to any specific combination of hardware and software.

[0088] The above are merely optional embodiments of the present application and are not intended to limit the present application. For those skilled in the art, the present application may be subject to various modifications and variations. Any modifications, equivalent substitutions, improvements, etc. made within the principles of the present application shall be included in the scope of protection of the present application.

Claims

1. A CXL data transmission board, characterized in that: include: A control chip, wherein the control chip is a chip supporting the open interconnection standard CXL protocol, and an uplink port and a downlink port are deployed on the control chip; The uplink port is connected to a host, wherein the host is a device supporting a high-speed serial computer expansion bus standard PCIe protocol or a device supporting the CXL protocol; The downstream port is connected to the processor and / or the memory module, and the downstream port is correspondingly connected to the upstream port. The host is configured to transmit data to the corresponding downstream port through the upstream port, so as to transmit the data to the processor and / or the memory module through the downstream port, wherein the processor and the memory module are both devices supporting the PCIe protocol or devices supporting the CXL protocol.

2. The CXL data transmission board according to claim 1, characterized in that: The number of the uplink ports and the number of the downlink ports are both N, and N is a natural number greater than 1.

3. The CXL data transmission board according to claim 2, characterized in that: The control chip comprises: A control unit is configured to control a topology of a CXL link between the upstream port and the downstream port, wherein the CXL link is configured to connect the corresponding upstream port and the downstream port.

4. The CXL data transmission board according to claim 2, characterized in that: The control chip comprises: A management unit is configured to manage routing information between the host and the processor and / or the memory module.

5. The CXL data transmission board according to any one of claims 2 to 4, characterized in that: The control chip comprises: An identification unit, wherein the identification unit is connected to the processor and / or the memory module, and the identification unit is configured to identify the protocol type supported by the processor and / or the memory module when the host establishes a connection with the processor and / or the memory module.

6. The CXL data transmission board according to claim 2, characterized in that: The host comprises M, the processor comprises P, and the memory modules comprises K, wherein M, P, and K are all natural numbers greater than or equal to 1.

7. The CXL data transmission board according to claim 6, characterized in that: When M is greater than 1, M hosts share K memory modules.

8. The CXL data transmission board according to claim 6, characterized in that: The N is 16, and the M is greater than or equal to 2 and less than or equal to 7.

9. The CXL data transmission board according to claim 6, characterized in that: The N is 16, the M is 7, the P is 7, the processor and the host correspond one to one, or one host corresponds to multiple processors, wherein data is transmitted between the host and the processor via the PCIe protocol.

10. The CXL data transmission board according to claim 6, characterized in that: When K is greater than 1, one host corresponds to a plurality of memory modules, and the plurality of memory modules constitute a memory resource pool of the host, wherein data is transmitted between the host and the memory module via the CXL protocol, and the number of the hosts is directly proportional to the number of the memory modules.

11. The CXL data transmission board according to claim 1, characterized in that: Also includes: A connector is provided to connect the control chip and the manager, wherein the manager is configured to manage the operation of the control chip through the connector.

12. The CXL data transmission board according to claim 1, characterized in that: Also includes: A clock generator is connected to the control chip and is configured to generate a first initialization clock signal for starting the control chip and to generate a first clock signal for coordinating the clock frequency of the control chip after the control chip is started.

13. The CXL data transmission board according to claim 12, characterized in that: The clock generator is connected to the control chip, the processor and the memory module through a preset interface, and is configured to generate a second initialization clock signal for starting the control chip, the processor and the memory module respectively, and is configured to generate a second clock signal for coordinating the clock frequencies of the control chip, the processor and the memory module after the control chip, the processor and the memory module are started.

14. The CXL data transmission board according to claim 12, characterized in that: The CXL data transmission board also includes: A debugging device is connected to the control chip and is configured to debug the CXL performance of the control chip.

15. The CXL data transmission board according to claim 1, characterized in that: Also includes: The SWITCH layer of the control chip includes multiple virtual CXLs, and the virtual CXLs are used to map to physical ports specified in the control chip according to instructions from the host to perform configurations between different upstream ports and downstream ports, wherein different configurations between the upstream ports and the downstream ports correspond to configurations of different numbers of processors and memory modules.

16. A method for controlling data transmission, characterized in that: include: Receiving a data request sent by a host through an upstream port, wherein the data request includes data to be transmitted, and the host is a device supporting a PCIe protocol or a device supporting a CXL protocol; In response to the data request, searching for routing information of the host from a routing table; The data is transmitted to a processor and / or a memory module connected to a downstream port corresponding to the upstream port according to the routing information, wherein the downstream port is connected correspondingly to the upstream port, and the processor and the memory module are both devices supporting the PCIe protocol or devices supporting the CXL protocol.

17. The method according to claim 16, characterized in that The number of the uplink ports and the number of the downlink ports are both N, and N is a natural number greater than 1.

18. The method according to claim 16, characterized in that Before responding to the data request and searching the routing information of the host from the routing table, the method further includes: Setting a topology of a CXL link between the N upstream ports and the N downstream ports, wherein the CXL link is used to connect the corresponding upstream ports and the downstream ports; The routing between the host and the processor and / or the memory module is determined based on the topology of the CXL link to obtain the routing table.

19. The method according to claim 16, characterized in that Transmitting the data to a processor and / or a memory module connected to a downlink port corresponding to the uplink port according to the routing information includes: Cache the data into a cache unit via the downlink port; Selecting a target route from the routing information; The data in the cache unit is transmitted to the processor and / or the memory module connected to the downstream port according to the target route.

20. The method according to claim 16, characterized in that Before transmitting the data to a processor and / or a memory module connected to a downlink port corresponding to the uplink port according to the routing information, the method further includes: When the host establishes a connection with the processor and / or the memory module, the protocol type supported by the processor and / or the memory module is identified so as to transmit the data to the protocol type supported by the processor and / or the memory module in accordance with the protocol type supported by the processor and / or the memory module.

21. The method according to claim 16, characterized in that The host comprises M, the processor comprises P, and the memory modules comprises K, wherein M, P, and K are all natural numbers greater than or equal to 1.

22. The method according to claim 21, characterized in that When M is greater than 1, M hosts share K memory modules.

23. The method according to claim 21, characterized in that N is 16, and M is greater than or equal to 2 and less than or equal to 7, wherein N is the number of the uplink ports and the downlink ports, and N is a natural number greater than 1.

24. The method according to claim 21, characterized in that N is 16, M is 7, P is 7, the processor and the host correspond one to one, or one host corresponds to multiple processors, wherein data is transmitted between the host and the processor via the PCIe protocol, N is the number of the upstream ports and the downstream ports, and N is a natural number greater than 1.

25. The method according to claim 21, characterized in that When K is greater than 1, one host corresponds to a plurality of memory modules, and the plurality of memory modules constitute a memory resource pool of the host, wherein data is transmitted between the host and the memory module via the CXL protocol, and the number of the hosts is directly proportional to the number of the memory modules.

26. The method according to claim 16, characterized in that The SWITCH layer of the control chip includes multiple virtual CXLs, which are used to map to physical ports specified in the control chip according to the instructions of the host to perform configurations between different upstream ports and downstream ports, wherein different configurations between the upstream ports and the downstream ports correspond to configurations of different numbers of processors and memory modules. The control chip is a chip that supports the open interconnection standard CXL protocol, and upstream ports and downstream ports are deployed on the control chip.

27. A control system for link switching, characterized in that: The link switching control system comprises the CXL data transmission board according to any one of claims 1 to 15.

28. A non-volatile readable storage medium, characterized in that: The non-volatile readable storage medium stores a computer program, wherein the computer program implements the steps of the method described in any one of claims 16 to 26 when executed by a processor.

29. An electronic device comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, characterized in that: When the processor executes the computer program, the steps of the method described in any one of claims 16 to 26 are implemented.

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