SOI semiconductor structure and manufacturing method therefor

Abstract

The present invention relates to an SOI semiconductor structure and a manufacturing method therefor. The method comprises: providing a wafer, wherein the wafer comprises a substrate, a buried dielectric region on the substrate, and a top semiconductor layer in the buried dielectric region; patterning the wafer, and exposing the substrate in a longitudinal device region; forming a first insulating isolation portion on a side face of the longitudinal device region; forming a first conductivity type region in the longitudinal device region by means of epitaxy; by means of a CMOS process, forming a CMOS device in a first device region, and forming a first well region and a first source region in the longitudinal device region, wherein the first well region is formed in the first conductivity type region, and the first source region is formed in the first well region; and forming a first drain region at the bottom of the substrate.

Description

SOI semiconductor structure and manufacturing method thereof

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to Chinese patent application No. 2023107949026, filed on June 29, 2023, entitled “A SOI semiconductor structure with integrated vertical devices and its manufacturing method,” the entire text of which is hereby incorporated by reference. Technical Field

[0003] The present invention relates to the field of semiconductor manufacturing, in particular to an SOI semiconductor structure and a method for manufacturing the SOI semiconductor structure. Background Art

[0004] BCD (Bipolar-CMOS-DMOS) technology is a monolithic integration process that enables the fabrication of bipolar (bipolar transistors), CMOS (metal oxide semiconductor field-effect transistors), and DMOS (double-diffused metal oxide semiconductor field-effect transistors) devices on the same chip. Devices fabricated using this process combine the high transconductance and strong load-driving capability of bipolar devices with the high integration and low power consumption of CMOS. Furthermore, DMOS can handle higher voltages and consume very little power in switching mode, delivering high power to the load without the need for expensive packaging and cooling systems. This technology has been widely used in automotive electronics, power management, lighting, and radio frequency communications. The DMOS, responsible for the power stage, is the core of these circuits. Because it must carry relatively high currents and voltages, it often occupies 30%-90% of the total area, making it the key to the entire integrated circuit.

[0005] In the traditional BCD process, DMOS uses a lateral channel LDMOS (lateral double-diffused metal oxide semiconductor field effect transistor). For LDMOS, the drift region needs to be long enough to withstand the voltage. Therefore, for devices with high voltage requirements, the drift region needs to be long enough to withstand the voltage, resulting in a larger device size.

[0006] Summary of the Invention

[0007] According to some embodiments, a SOI semiconductor structure and a method for manufacturing the same are provided.

[0008] A SOI semiconductor structure comprises: a substrate having a first conductivity type; a buried dielectric region disposed on the substrate; a first conductivity type region disposed in an area of ​​the substrate where the buried dielectric region is not disposed; a second conductivity type region disposed on the buried dielectric region, the first conductivity type and the second conductivity type being opposite conductivity types; a first device disposed on the buried dielectric region; a vertical device comprising a first well region, a first source region, a first drain region, and a first gate, the first well region having the second conductivity type and disposed in the first conductivity type region, the first source region disposed in the first well region, and the first drain region disposed at the bottom of the substrate; and an isolation structure comprising a first insulating isolation portion and a depletion region, the depletion region being located between the second conductivity type region and the first conductivity type region, the bottom of the first insulating isolation portion reaching the substrate, the depletion region and the first conductivity type region being separated by the first insulating isolation portion, the depletion region being located between the first insulating isolation portion and the second conductivity type region, and the depletion region having the second conductivity type.

[0009] The SOI semiconductor structure integrates relatively small vertical devices (for reference, VDMOS is smaller than LDMOS), resulting in a device with higher power density. The isolation structure between the first device and the vertical device utilizes a depletion region of the second conductivity type in conjunction with a first insulating isolation portion. The second conductivity type depletion region optimizes the electric field of the vertical device, thereby reducing the area of ​​the depletion region and the chip area.

[0010] In one embodiment, the withstand voltage of the vertical device is greater than the withstand voltage of the first device.

[0011] In one embodiment, the vertical device is a high voltage device and the first device is a low voltage device.

[0012] In one embodiment, the isolation structure further includes a second insulating isolation portion, the depletion region is located between the first insulating isolation portion and the second insulating isolation portion, and a bottom of the second insulating isolation portion reaches the substrate.

[0013] In one embodiment, the first insulating isolation portion is disposed close to the first conductive type region, and the second insulating isolation portion is disposed close to the second conductive type region.

[0014] In one embodiment, the vertical device is a VDMOS device, the first source region and the first drain region have a first conductivity type, and the doping concentration of the first drain region is greater than the doping concentration of the substrate.

[0015] In one embodiment, the first device includes: a CMOS well region having a second conductivity type, disposed above the buried dielectric region; a CMOS source region having a first conductivity type, disposed in the CMOS well region; a CMOS drain region having a first conductivity type, disposed in the CMOS well region; and a CMOS gate disposed on the CMOS well region between the CMOS source region and the CMOS drain region.

[0016] In one embodiment, the CMOS source region, the CMOS drain region, and the first source region are located at the same level in the SOI semiconductor structure.

[0017] In one embodiment, the second insulating isolation portion is a closed ring structure, surrounding the second conductive type region in a laterally direction.

[0018] In one embodiment, the first conductivity type is N-type, and the second conductivity type is P-type.

[0019] A method for manufacturing an SOI semiconductor structure, comprising: providing a wafer, the wafer comprising a substrate, a buried dielectric region located on the substrate, and a top semiconductor layer located on the buried dielectric region; the substrate having a first conductivity type, the top semiconductor layer having a second conductivity type, the first conductivity type and the second conductivity type being opposite conductivity types; patterning the wafer, removing the top semiconductor layer and the buried dielectric region located in a vertical device region, thereby exposing the substrate located in the vertical device region; forming a first insulating isolation portion on a side of the vertical device region; epitaxially forming a first conductivity type region in the vertical device region; forming a CMOS device on the top semiconductor layer by a CMOS process, forming a first well region and a first source region in the vertical device region; the first well region is formed in the first conductivity type region, the first well region has the second conductivity type, and the first source region is formed in the first well region; in the top semiconductor layer, a portion located between the first insulating isolation portion and the CMOS device serves as a depletion region; and forming a first drain region at the bottom of the substrate.

[0020] The above-mentioned method for manufacturing SOI semiconductor structures can integrate relatively small vertical devices, thereby obtaining devices with higher power density. The second conductivity type depletion region can optimize the electric field of the vertical device, thereby reducing the area of ​​the depletion region and reducing the chip area.

[0021] In one embodiment, patterning the wafer also includes forming an isolation trench, wherein the isolation trench separates the top semiconductor layer into a first device region and the depletion region, and the depletion region is located between the isolation trench and the first insulating isolation portion; forming the first insulating isolation portion on the side of the vertical device region includes: depositing an insulating dielectric material on the front side of the wafer, so that the isolation trench is filled with the insulating dielectric material to form a second insulating isolation portion, and forming the first insulating isolation portion on the side of the vertical device region; forming a CMOS device in the top semiconductor layer through a CMOS process includes: forming a CMOS device in the first device region.

[0022] In one embodiment, the wafer further includes a dielectric layer on the top semiconductor layer; after forming the first conductive type region by epitaxial growth in the vertical device region and before forming a CMOS device on the top semiconductor layer through a CMOS process, the method further includes: removing the dielectric layer.

[0023] In one embodiment, the critical dimension of the isolation trench is 0.8 to 2 microns.

[0024] In one embodiment, the step of forming a CMOS device on the top semiconductor layer by a CMOS process includes: forming a CMOS well region, a CMOS source region, a CMOS drain region and a CMOS gate by a CMOS process; the CMOS well region has a second conductivity type and is formed above the buried dielectric region, the CMOS source region and the CMOS drain region have a first conductivity type and are formed in the CMOS well region, and the CMOS gate is formed on the CMOS well region between the CMOS source region and the CMOS drain region; the first source region and the first drain region have a first conductivity type, and the doping concentration of the first drain region is greater than the doping concentration of the substrate.

[0025] In one embodiment, the wafer is patterned to remove the top semiconductor layer and the buried dielectric region of the vertical device region to expose the substrate of the vertical device region, and at the same time, an isolation trench is formed, wherein the isolation trench separates the first device region from the vertical device region, and the top semiconductor layer between the isolation trench and the vertical device region serves as a depletion region. The removal of the top semiconductor layer and the buried dielectric region of the vertical device region and the formation of the isolation trench are formed by photolithography and etching, and the photolithography and etching of the vertical device region and the isolation trench are performed using the same photomask and are formed in the same etching step.

[0026] In one embodiment, filling the isolation trench with an insulating dielectric material comprises: depositing the insulating dielectric material on the front side of the wafer, wherein the deposition forms second insulating isolation portions on both sides of the vertical device region.

[0027] In one embodiment, the withstand voltage of the vertical device is greater than that of a CMOS device.

[0028] In one embodiment, the vertical device is a VDMOS device, the first source region and the first drain region have a first conductivity type, and the doping concentration of the first drain region is greater than the doping concentration of the substrate.

[0029] In one embodiment, the second groove has a closed ring structure.

[0030] In one embodiment, the first conductivity type is N-type, and the second conductivity type is P-type. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] In order to better describe and illustrate the embodiments and / or examples of the inventions disclosed herein, reference may be made to one or more of the accompanying drawings. The additional details or examples used to describe the accompanying drawings should not be considered to limit the scope of the disclosed inventions, the presently described embodiments and / or examples, and any of the best modes currently understood for these inventions.

[0032] FIG1 is a flow chart of a method for manufacturing an SOI semiconductor structure according to an embodiment of the present application;

[0033] 2a to 2d are schematic cross-sectional views of a device during manufacture according to the method shown in FIG1 ;

[0034] FIG3 is a schematic cross-sectional view of an SOI semiconductor structure according to an embodiment of the present application;

[0035] FIG4 is a flow chart of a method for manufacturing an SOI semiconductor structure in another embodiment of the present application;

[0036] 5a to 5e are schematic cross-sectional views of a device during manufacture according to the method shown in FIG4 ;

[0037] FIG6 is a schematic cross-sectional view of an SOI semiconductor structure according to another embodiment of the present application. DETAILED DESCRIPTION

[0038] To facilitate understanding of the present invention, the present invention will be described more fully below with reference to the accompanying drawings. Preferred embodiments of the present invention are shown in the drawings. However, the present invention may be embodied in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided to provide a more thorough and comprehensive disclosure of the present invention.

[0039] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by those skilled in the art to which this invention pertains. The terms used in this specification of the present invention are for the purpose of describing specific embodiments only and are not intended to limit the present invention. The term "and / or" as used herein includes any and all combinations of one or more of the associated listed items.

[0040] It should be understood that when an element or layer is referred to as being "on," "adjacent to," "connected to," or "coupled to" another element or layer, it may be directly on, adjacent to, connected to, or coupled to the other element or layer, or there may be intervening elements or layers. Conversely, when an element is referred to as being "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" another element or layer, there may be no intervening elements or layers. In this specification, "connected" should be understood as "electrically connected," "communicatively connected," etc., if the connected circuits, modules, units, etc. have electrical signals or data transmission with each other. It should be understood that although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers, and / or parts, these elements, components, regions, layers, and / or parts should not be limited by these terms. These terms are merely used to distinguish one element, component, region, layer, or part from another element, component, region, layer, or part. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present invention.

[0041] Spatially relative terms such as "under," "beneath," "below," "under," "above," "above," etc., may be used herein for convenience of description to describe the relationship of one element or feature shown in the figures to other elements or features. It should be understood that the spatially relative terms are intended to include different orientations of the device in use and operation in addition to the orientations shown in the figures. For example, if the device in the drawings is flipped, then the elements or features described as "under" or "beneath" or "beneath" the other elements will be oriented as "over" the other elements or features. Thus, the exemplary terms "under" and "under" may include both the upper and lower orientations. The device may be oriented otherwise (rotated 90 degrees or in other orientations) and the spatial descriptors used herein are interpreted accordingly.

[0042] The purpose of the terms used herein is only to describe specific embodiments and is not intended to limit the present invention. When used herein, the singular forms "a", "an" and "said / the" are also intended to include the plural forms, unless the context clearly indicates otherwise. It will be understood that "at least one" means one or more, and "a plurality" means two or more. "At least a portion of an element" refers to part or all of an element. It will also be understood that the terms "compose" and / or "comprise", when used in this specification, determine the presence of the features, integers, steps, operations, elements and / or parts, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, parts and / or groups. When used herein, the term "and / or" includes any and all combinations of the relevant listed items.

[0043] Embodiments of the invention are described herein with reference to cross-sectional views which are schematic illustrations of idealized embodiments (and intermediate structures) of the invention. As such, variations from the shapes shown due to, for example, manufacturing techniques and / or tolerances are contemplated. Accordingly, embodiments of the invention should not be limited to the specific shapes of the regions shown herein, but rather include deviations in shapes due to, for example, manufacturing. For example, an implanted region shown as a rectangle typically has rounded or curved features and / or an implant concentration gradient at its edges, rather than a binary change from an implanted region to a non-implanted region. Similarly, a buried region formed by implantation may result in some implantation in the region between the buried region and the surface through which the implantation occurs. Accordingly, the regions shown in the figures are schematic in nature, and their shapes are not intended to illustrate the actual shape of the region of the device and are not intended to limit the scope of the invention.

[0044] The semiconductor field terms used in this article are technical terms commonly used by those skilled in the art. For example, for P-type and N-type impurities, in order to distinguish the doping concentration, P+ type represents P-type with heavy doping concentration, P-type represents P-type with medium doping concentration, P-type represents P-type with light doping concentration, N+ type represents N-type with heavy doping concentration, N-type represents N-type with medium doping concentration, and N-type represents N-type with light doping concentration.

[0045] With the widespread application of ultra-large-scale integrated circuits in various fields, the system has increasingly higher requirements for the development of high-voltage and high-power semiconductor devices. Integrated high-voltage devices using silicon-on-insulator (SOI) technology combine the advantages of SOI technology and the device itself, with fast operating speed, low parasitic effects, high breakdown voltage, simple process preparation, and convenient integration. Therefore, they have been widely studied and applied. This application proposes a process method for integrating vertical channel VDMOS (vertical double-diffused metal oxide semiconductor field-effect transistor) devices on an SOI substrate. VDMOS with low on-resistance, small area, and high withstand voltage can be integrated into a BCD process platform to obtain a DMOS with higher power density. At the same time, because VDMOS can be packaged together with integrated CMOS, complex circuits can be further miniaturized.

[0046] Referring to FIG. 1 , a method for manufacturing an SOI semiconductor structure according to an embodiment of the present application includes the following steps:

[0047] S110, provide wafers.

[0048] 2 a , the wafer includes a substrate 12 , a buried dielectric region 20 located on the substrate 12 , and a top semiconductor layer 14 located on the buried dielectric region 20 .

[0049] In one embodiment, substrate 12 is a silicon substrate with a high doping concentration. In an SOI semiconductor structure, the isolation region between adjacent devices depletes from the device end toward substrate 12. Using a substrate 12 with a high doping concentration results in a narrower depletion region. Therefore, the distance between adjacent devices can be closer (i.e., the isolation region can be narrower), resulting in a smaller device area. In one embodiment, the doping concentration of substrate 12 is controlled to provide a resistivity of 8 to 45 Ω×cm.

[0050] Substrate 12 has a first conductivity type, and top semiconductor layer 14 has a second conductivity type. In one embodiment, the first conductivity type is N-type, and the second conductivity type is P-type. Top semiconductor layer 14 is a P+ region. In other embodiments, the first conductivity type may be P-type, in which case the second conductivity type is N-type. In one embodiment, top semiconductor layer 14 has a thickness of 1 to 5 microns.

[0051] In one embodiment, the buried dielectric region 20 is a buried oxide layer, and its material can be silicon oxide, such as silicon dioxide. In one embodiment, the buried dielectric region 20 has a thickness of 0.5 to 3 microns.

[0052] 2a, the wafer further includes a dielectric layer 22 located on the top semiconductor layer 14. In one embodiment, the dielectric layer 22 may be made of silicon oxide, such as silicon dioxide.

[0053] S120 , patterning the wafer, removing the top semiconductor layer 14 and the buried dielectric region 20 located in the vertical device region, thereby exposing the substrate 12 located in the vertical device region.

[0054] Referring to FIG. 2 b , the patterning in step S120 is performed through photolithography and etching. Specifically, a photoresist is applied to the front side of the wafer, then exposed using a photomask. After development, a photoresist layer 94 is formed. The photoresist layer 94 then serves as an etch barrier to etch away the dielectric layer 22, top semiconductor layer 14, and buried dielectric region 20. The dielectric layer 22, top semiconductor layer 14, and buried dielectric region 20 located in the vertical device region above the substrate 12 are removed, exposing the substrate 12.

[0055] S130 , forming a first insulating isolation portion on a side surface of the vertical device region.

[0056] Referring to FIG. 2c , in one embodiment, step S130 includes removing the photoresist layer 94 and then depositing an insulating dielectric material on the front side of the wafer. In one embodiment, the insulating dielectric material is deposited using a low-pressure chemical vapor deposition (LPCVD) process using TEOS (tetraethyl orthosilicate) as a reactant.

[0057] In one embodiment, after depositing the insulating dielectric material, it is necessary to remove the insulating dielectric material on the surface of substrate 12 located in the vertical device region, thereby exposing substrate 12. In one embodiment, the insulating dielectric material on the surface of substrate 12 is removed by general etching (i.e., direct etching without photolithography). After deposition and general etching, the insulating dielectric material remaining on both sides of the vertical device region serves as the first insulating isolation portion 26.

[0058] S140 , forming a first conductive type region 16 by epitaxial growth in the vertical device region.

[0059] 2 d , a first conductivity type epitaxial layer is grown in the vertical device region by selective epitaxy to form a first conductivity type region 16 . The first conductivity type region 16 is separated from the top semiconductor layer 14 by a first insulating isolation portion 26 .

[0060] Since the dielectric layer 22 is formed on the top semiconductor layer 14 in the previous step, the dielectric layer 22 will prevent the formation of the first conductive type epitaxial layer during selective epitaxy. Therefore, the first conductive type epitaxial layer will only be formed at a position on the substrate 12 that is not covered by the buried dielectric region 20 and the first insulating isolation portion 26, and will not be formed on the top semiconductor layer 14 covered with the dielectric layer 22.

[0061] S150 , forming a CMOS device, a first well region, and a first source region through a CMOS process.

[0062] 3 , the top semiconductor layer 14 includes a first device region and a depletion region. Specifically, after removing the dielectric layer 22 on the front side of the wafer, a first device is formed in the first device region, and a first well region 44 and a first source region 46 are formed in the vertical device region using a CMOS process.

[0063] In one embodiment, the first device is a low-voltage device (e.g., a CMOS device). The vertical device is a high-voltage device and is isolated from the first device by a first insulating isolation portion 26. In one embodiment, the vertical device is a VDMOS device, and the first well region 44 and the first source region 46 are the well and source regions of the VDMOS device. It will be understood that in other embodiments, the vertical device may also be an IGBT (Insulated Gate Bipolar Transistor) device, an SGT (Shielded Gate Trench) device, or the like.

[0064] In one embodiment, a CMOS well region 54, a CMOS source region 562, a CMOS drain region 564, and a CMOS gate 58 can be formed in the first device region using conventional CMOS processes, while the first well region 44 and the first source region 46 are simultaneously formed in the vertical device region. The first well region 44 has the second conductivity type and is formed in the first conductivity type region 16. The first source region 46 is formed in the first well region 44. The CMOS well region 54 has the second conductivity type and is formed in the second conductivity type region 14' of the top semiconductor layer 14 and above the buried dielectric region 20. The CMOS source region 562 and the CMOS drain region 564 have the first conductivity type and are formed in the CMOS well region 54. The CMOS gate 58 is formed on the CMOS well region 54 between the CMOS source region 562 and the CMOS drain region 564.

[0065] In the SOI structure, the electric field lines on the high-voltage side will enter the silicon on the other side of the isolation trench, forming a depletion region. This depletion region will affect the performance of other devices. In the embodiment shown in Figure 3, the CMOS well region 54 only occupies a portion of the top semiconductor layer 14 in the lateral direction. The top semiconductor layer 14 outside the CMOS well region 54 serves as the depletion region, and the top semiconductor layer 14 below the CMOS well region 54 serves as the second conductive type region 14'. Exemplarily, the amplified isolation rule can be used to avoid the influence of the depletion region. First, other devices are kept away from the isolation trench boundary, but the chip area will increase. Second, the number and width of the isolation trenches are increased. However, the more isolation trenches are etched, the higher the warpage of the wafer will be, and the wafer will crack due to increased stress.

[0066] In the above embodiment, after the buried dielectric region 20 of the vertical device region is etched away, a first conductive type region 16 having a conductive type different from that of the top semiconductor layer 14 is regrown in the vertical device region. This can not only optimize the electric field of the vertical device, but also require a smaller area for the depletion region, thereby reducing the chip area. There is no need to set a wider isolation trench between the first device region and the vertical device region, thereby avoiding the increase in stress on the wafer caused by a larger isolation trench size, which may lead to wafer warping or even cracking.

[0067] S160 , forming a first drain region at the bottom of the substrate.

[0068] 3 , a first drain region 42 is formed on the bottom surface of the substrate 12 by an ion implantation process. The doping concentration of the first drain region 42 is greater than the doping concentration of the substrate 12 .

[0069] The above-mentioned SOI semiconductor structure manufacturing method can integrate relatively small vertical devices into the process platform, resulting in devices with higher power density. The second conductivity type depletion region can optimize the electric field of the vertical device, thereby reducing the area of ​​the depletion region and reducing the chip area.

[0070] According to some embodiments, a SOI semiconductor structure with an integrated vertical device is provided. Referring to FIG3 , the SOI semiconductor structure includes a substrate 12, a buried dielectric region 20, a first conductivity type region 16, a second conductivity type region 14′ (i.e., a portion of a top semiconductor layer 14), a first device, a vertical device, and an isolation structure. The substrate 12 has a first conductivity type. The buried dielectric region 20 is disposed on the substrate 12. The first conductivity type region 16 is disposed in an area of ​​the substrate 12 where the buried dielectric region 20 is not disposed. The top semiconductor layer 14 is disposed on the buried dielectric region 20 and includes a second conductivity type region 14′ located in the first device region and a depletion region located between the second conductivity type region 14′ and the first conductivity type region 16. The top semiconductor layer 14 has a second conductivity type. The first device is disposed on the buried dielectric region 20 and is located in the first device region. The vertical device includes a first well region 44, a first source region 46, a first drain region 42, and a first gate 48. The first well region 44 has a second conductivity type and is disposed in the first conductivity type region 16. The first source region 46 is provided in the first well region 44, and the first drain region 42 is provided at the bottom of the substrate 12. The isolation structure includes a first insulating isolation portion 26 and a depletion region, wherein the depletion region is located between the second conductive type region 14' and the first conductive type region 16, and the bottom of the first insulating isolation portion 26 reaches the substrate 12. The depletion region and the first conductive type region 16 are separated by the first insulating isolation portion 26, and the depletion region is located between the first insulating isolation portion 26 and the second conductive type region 14'. In one embodiment, the first conductive type is N-type and the second conductive type is P-type. In other embodiments, the first conductive type may also be P-type, in which case the second conductive type is N-type.

[0071] In one embodiment, the first device is a low-voltage device (e.g., a CMOS device), and the vertical device is a high-voltage device (e.g., a VDMOS device). The low-voltage device and the high-voltage device are isolated by an isolation structure consisting of a first insulating isolation portion 26 and a depletion region. The first source region 46 and the first drain region 42 have a first conductivity type, and the doping concentration of the first drain region 42 is greater than the doping concentration of the substrate 12.

[0072] In one embodiment, the first device includes a CMOS well region 54, a CMOS source region 562, a CMOS drain region 564, and a CMOS gate 58. The CMOS well region 54 has the second conductivity type and is formed in the second conductivity type region and above the buried dielectric region 20. The CMOS source region 562 and the CMOS drain region 564 have the first conductivity type and are formed in the CMOS well region 54. The CMOS gate 58 is formed on the CMOS well region 54 between the CMOS source region 562 and the CMOS drain region 564.

[0073] In the embodiment shown in FIG. 3 , the first source region 46 , the CMOS source region 562 , and the CMOS drain region 564 are located on the same plane in the SOI semiconductor structure.

[0074] In one embodiment, the SOI semiconductor structure comprises a thin top silicon layer and a thin buried oxide layer. The thickness of the top semiconductor layer 14 is 1-5 microns. The thickness of the buried dielectric region 20 is 0.5 to 3 microns.

[0075] In one embodiment, the SOI semiconductor structure adopts a BCD process platform.

[0076] The SOI semiconductor structure integrates relatively small vertical devices, resulting in a device with higher power density. The isolation structure between the first device and the vertical device utilizes a depletion region of the second conductivity type in conjunction with a first insulating isolation portion. This second conductivity type depletion region optimizes the electric field of the vertical device, thereby reducing the area of ​​the depletion region and the chip area.

[0077] Referring to FIG. 4 , a method for manufacturing an SOI semiconductor structure according to another embodiment of the present application includes the following steps:

[0078] S410, providing a wafer.

[0079] 5 a , the wafer includes a substrate 12 , a buried dielectric region 20 on the substrate 12 , and a top semiconductor layer 14 on the buried dielectric region 20 .

[0080] In one embodiment, substrate 12 utilizes a silicon substrate with a high doping concentration. In an SOI semiconductor structure, the isolation region between adjacent devices depletes from the device end toward substrate 12. Using a substrate 12 with a high doping concentration results in a narrower depletion region. Therefore, the distance between adjacent devices can be closer (i.e., the isolation region can be narrower), resulting in a smaller device area. In one embodiment, the doping concentration of substrate 12 is controlled to provide a resistivity of 8 to 45 Ω×cm.

[0081] Substrate 12 has a first conductivity type, and top semiconductor layer 14 has a second conductivity type. In one embodiment, the first conductivity type is N-type, the second conductivity type is P-type, and top semiconductor layer 14 is a P+ region. In other embodiments, the first conductivity type may be P-type, in which case the second conductivity type is N-type. In one embodiment, top semiconductor layer 14 has a thickness of 1 to 5 microns.

[0082] In one embodiment, the buried dielectric region 20 is a buried oxide layer, and its material can be silicon oxide, such as silicon dioxide. In one embodiment, the buried dielectric region 20 has a thickness of 0.5 to 3 microns.

[0083] 5a, the wafer further includes a dielectric layer 22 on the top semiconductor layer 14. In one embodiment, the dielectric layer 22 may be made of silicon oxide, such as silicon dioxide.

[0084] S420 , patterning the wafer to expose the substrate 12 located in the vertical device region, and simultaneously forming an isolation trench and a depletion region.

[0085] Specifically, the top semiconductor layer 14 and buried dielectric region 20 of the vertical device region are removed, exposing the substrate 12 of the vertical device region. Simultaneously with the removal of the top semiconductor layer 14 and buried dielectric region 20 of the vertical device region, the wafer is patterned to form isolation trenches 13. Isolation trenches 13 separate the first device region from the vertical device region, with the top semiconductor layer 14 between isolation trenches 13 and the vertical device region serving as a depletion region 14a.

[0086] Referring to Figures 5a and 5b, the patterned wafer of step S420 is formed by photolithography and etching. Specifically, photoresist is coated on the front side of the wafer, then exposed using a photomask, and a photoresist layer 94 is formed after development. The photoresist layer 94 is then used as an etch barrier to etch the dielectric layer 22, the top semiconductor layer 14, and the buried dielectric region 20 to form the isolation trench 13. Simultaneously, the dielectric layer 22, the top semiconductor layer 14, and the buried dielectric region 20 above the substrate 12 in the vertical device region are etched away, thereby exposing the substrate 12. The photolithography and etching of the vertical device region and the isolation trench 13 are performed using the same photomask and are formed in the same etching step.

[0087] In one embodiment, the critical dimension (CD) of the isolation trench 13 is 0.8 to 2 microns.

[0088] In one embodiment, the isolation trench 13 surrounds the first device region in a lateral direction. In one embodiment, the isolation trench 13 is a closed ring structure, which can be a circular ring, a square ring, or a closed ring of other shapes.

[0089] S430 , filling the isolation trench with an insulating dielectric material.

[0090] Referring to Figure 5c, in one embodiment, the insulating dielectric material is a silicon oxide, such as silicon dioxide. The insulating dielectric material filled in isolation trench 13 serves as second insulating isolation portion 24. In one embodiment, step S430 includes removing photoresist layer 94 and then depositing the insulating dielectric material on the front side of the wafer. After deposition, first insulating isolation portions 26 are formed on both sides of the vertical device region.

[0091] In one embodiment, the process of depositing the insulating dielectric material in step S430 is a low pressure chemical vapor deposition (LPCVD) process using TEOS (tetraethyl orthosilicate) as a reactant.

[0092] 5d , in one embodiment, after depositing the insulating dielectric material, it is necessary to remove the insulating dielectric material on the surface of substrate 12 located in the vertical device region, thereby exposing substrate 12. In one embodiment, the insulating dielectric material on the upper surface of substrate 12 is removed by general etching (i.e., direct etching without photolithography).

[0093] S440 , forming a first conductive type region in the vertical device region by epitaxial growth.

[0094] In the embodiment shown in FIG. 5 e , a first conductivity type epitaxial layer is grown in the vertical device region by selective epitaxy, thereby forming a first conductivity type region 16 .

[0095] Since the dielectric layer 22 is formed on the top semiconductor layer 14 in the previous step, the dielectric layer 22 will prevent the formation of the first conductive type epitaxial layer during selective epitaxy. Therefore, the first conductive type epitaxial layer will only be formed at a position on the substrate 12 that is not covered by the buried dielectric region 20, the first insulating isolation portion 26 and the second insulating isolation portion 24, and will not be formed on the top semiconductor layer 14 covered with the dielectric layer 22.

[0096] In SOI structures, electric field lines on the high-voltage side can penetrate into the silicon on the other side of the isolation trench, forming a depletion region that can affect the performance of other devices. For example, amplified isolation rules can be used to avoid the effects of depletion regions. First, other devices can be moved away from the isolation trench boundary, but this increases the chip area. Second, the number and width of isolation trenches can be increased. However, the more isolation trenches are etched, the greater the wafer warpage, which can lead to wafer cracking due to increased stress.

[0097] In the present application, after etching away the buried dielectric region 20 in the vertical device region, a first conductive type region 16 having a conductive type different from that of the top semiconductor layer 14 is regrown in the vertical device region. This can not only optimize the electric field of the vertical device, but also allow the depletion region 14a to only require a smaller area, thereby reducing the chip area. There is no need to set a wider isolation trench 13 between the first device region and the vertical device region, thereby avoiding the larger isolation trench size causing increased stress on the wafer, which may lead to wafer warping or even cracking.

[0098] S450 , forming a CMOS device, a first well region, and a first source region through a CMOS process.

[0099] 6 , the top semiconductor layer 14 includes a first device region and a depletion region 14a. Specifically, after removing the dielectric layer 22 on the front side of the wafer, a first device is formed in the first device region, and a first well region 44 and a first source region 46 are formed in the vertical device region using a CMOS process.

[0100] In one embodiment, the first device is a low-voltage device (e.g., a CMOS device). The vertical device is a high-voltage device and is isolated from the first device by an isolation structure consisting of a first insulating isolation portion 26, a second insulating isolation portion 24, and a depletion region 14a. In one embodiment, the vertical device is a VDMOS device, and the first well region 44 and the first source region 46 are the well and source regions of the VDMOS device. It will be understood that in other embodiments, the vertical device may also be an IGBT (Insulated Gate Bipolar Transistor) device, an SGT (Shielded Gate Trench) device, or the like.

[0101] Specifically, after removing the dielectric layer 22 on the front side of the wafer, a CMOS device is formed in the first device region using a CMOS process, and a first well region 44 and a first source region 46 are formed in the vertical device region. The first well region 44 is formed in the first conductivity type region 16 and has the second conductivity type. The first source region 46 is formed in the first well region 44.

[0102] In one embodiment, a CMOS well region 54, a CMOS source region 562, a CMOS drain region 564, and a CMOS gate 58 can be formed in the first device region using conventional CMOS processes, while the first well region 44 and the first source region 46 are simultaneously formed in the vertical device region. The first well region 44 has the second conductivity type and is formed in the first conductivity type region 16. The first source region 46 is formed in the first well region 44. The CMOS well region 54 has the second conductivity type and is formed in the second conductivity type region 14' of the top semiconductor layer 14 and above the buried dielectric region 20. The CMOS source region 562 and the CMOS drain region 564 have the first conductivity type and are formed in the CMOS well region 54. The CMOS gate 58 is formed on the CMOS well region 54 between the CMOS source region 562 and the CMOS drain region 564.

[0103] S460 , forming a first drain region at the bottom of the substrate.

[0104] 6 , a first drain region 42 is formed on the bottom surface of the substrate 12 by an ion implantation process. The doping concentration of the first drain region 42 is greater than the doping concentration of the substrate 12 .

[0105] The above-mentioned method for manufacturing SOI semiconductor structures can integrate relatively small vertical devices, thereby obtaining devices with higher power density. The second conductivity type depletion region can optimize the electric field of the vertical device, thereby reducing the area of ​​the depletion region and reducing the chip area.

[0106] According to one embodiment, an SOI semiconductor structure with integrated vertical devices is provided. Referring to FIG6 , the SOI semiconductor structure includes a substrate 12, a buried dielectric region 20, a first conductivity type region 16, a second conductivity type region 14′ (i.e., a portion of the top semiconductor layer 14), a first device, a vertical device, and an isolation structure. The substrate 12 has a first conductivity type. The buried dielectric region 20 is disposed on the substrate 12. The first conductivity type region 16 is disposed in an area of ​​the substrate 12 where the buried dielectric region 20 is not disposed. The second conductivity type region 14′ is disposed on the buried dielectric region 20. The first device is disposed on the buried dielectric region 20 and is located in the first device region. The vertical device includes a first well region 44, a first source region 46, a first drain region 42, and a first gate 48. The first well region 44 has a second conductivity type and is disposed in the first conductivity type region 16. The first source region 46 is disposed in the first well region 44, and the first drain region 42 is disposed at the bottom of the substrate 12. The isolation structure includes a first insulating isolation portion 26, a second insulating isolation portion 24, and a depletion region 14a. The depletion region 14a is located between the second conductivity type region 14' and the first conductivity type region 16. The bottoms of the first insulating isolation portion 26 and the second insulating isolation portion 24 reach the substrate 12. The depletion region 14a and the second conductivity type region 14' are separated by the second insulating isolation portion 24, and the depletion region 14a and the first conductivity type region 16 are separated by the first insulating isolation portion 26. The depletion region 14a has the second conductivity type. In one embodiment, the first conductivity type is N-type and the second conductivity type is P-type; in other embodiments, the first conductivity type may be P-type and the second conductivity type may be N-type.

[0107] The SOI semiconductor structure described above enables the integration of relatively small vertical devices within a process platform, resulting in devices with higher power density. The isolation structure between the first device and the vertical device utilizes a second conductivity type depletion region 14a in conjunction with a first insulating isolation portion 26 and a second insulating isolation portion 24. The second conductivity type depletion region 14a optimizes the electric field of the vertical device, thereby reducing the area of ​​the depletion region 14a and the chip area.

[0108] In one embodiment, the first device is a low-voltage device (e.g., a CMOS device), and the vertical device is a high-voltage device (e.g., a VDMOS device). The low-voltage device and the high-voltage device are isolated from each other by an isolation structure consisting of a first insulating isolation portion 26, a second insulating isolation portion 24, and a depletion region 14a. The first source region 46 and the first drain region 42 have a first conductivity type, and the doping concentration of the first drain region 42 is greater than the doping concentration of the substrate 12.

[0109] In one embodiment, the second insulating isolation portion 24 laterally surrounds the second conductive type region 14'. In one embodiment, the second insulating isolation portion 24 is a closed ring structure that surrounds the second conductive type region 14' to insulate and isolate the first device. The ring structure can be a circular ring, a square ring, or another closed ring shape.

[0110] In one embodiment, the first device includes a CMOS well region 54, a CMOS source region 562, a CMOS drain region 564, and a CMOS gate 58. The CMOS well region 54 has the second conductivity type and is formed in the second conductivity type region and above the buried dielectric region 20. The CMOS source region 562 and the CMOS drain region 564 have the first conductivity type and are formed in the CMOS well region 54. The CMOS gate 58 is formed on the CMOS well region 54 between the CMOS source region 562 and the CMOS drain region 564.

[0111] In the embodiment shown in FIG. 6 , the first source region 46 , the CMOS source region 562 , and the CMOS drain region 564 are located at the same level in the SOI semiconductor structure.

[0112] In one embodiment, the SOI semiconductor structure comprises a thin top silicon layer and a thin buried oxide layer. The thickness of the top semiconductor layer 14 is 1-5 microns. The thickness of the buried dielectric region 20 is 0.5 to 3 microns.

[0113] It should be understood that, although the various steps in the flowchart of the present application are shown in sequence as indicated by the arrows, these steps are not necessarily performed in the order indicated by the arrows. Unless otherwise specified herein, there is no strict order restriction on the execution of these steps, and these steps can be performed in other orders. Moreover, at least a portion of the steps in the flowchart of the present application may include multiple steps or multiple stages, and these steps or stages are not necessarily performed at the same time, but can be performed at different times. The execution order of these steps or stages is not necessarily to be performed in sequence, but can be performed in turn or alternately with other steps or at least a portion of steps or stages in other steps.

[0114] Throughout this specification, references to terms such as "some embodiments," "other embodiments," and "desired embodiments" indicate that a particular feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of the present invention. Although these terms are used interchangeably throughout this specification, they do not necessarily refer to the same embodiment or example.

[0115] The technical features of the above-mentioned embodiments can be combined arbitrarily. In order to make the description concise, not all possible combinations of the technical features in the above-mentioned embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0116] The above-described embodiments merely illustrate several implementations of the present invention, and while their descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the patent. It should be noted that a person skilled in the art would be able to make numerous variations and improvements without departing from the spirit of the present invention, all of which fall within the scope of protection of the present invention. Therefore, the scope of protection of the patent for this invention shall be determined by the appended claims.

Claims

1. A SOI semiconductor structure, comprising: a substrate having a first conductivity type; A buried dielectric region is disposed on the substrate; A first conductive type region is provided in a region of the substrate where the buried dielectric region is not provided; A second conductive type region, disposed on the buried dielectric region, wherein the first conductive type and the second conductive type are opposite conductive types; A first device, disposed on the buried dielectric region; A vertical device, comprising a first well region, a first source region, a first drain region and a first gate, wherein the first well region has a second conductivity type and is disposed in the first conductivity type region, the first source region is disposed in the first well region, and the first drain region is disposed at the bottom of the substrate; and An isolation structure includes a first insulating isolation portion and a depletion region, wherein the depletion region is located between the second conductive type region and the first conductive type region, the bottom of the first insulating isolation portion reaches the substrate, the depletion region and the first conductive type region are separated by the first insulating isolation portion, the depletion region is located between the first insulating isolation portion and the second conductive type region, and the depletion region has the second conductive type.

2. The SOI semiconductor structure according to claim 1, characterized in that: The isolation structure also includes a second insulating isolation portion, the depletion region is located between the first insulating isolation portion and the second insulating isolation portion, the bottom of the second insulating isolation portion reaches the substrate, the first insulating isolation portion is arranged close to the first conductive type region, and the second insulating isolation portion is arranged close to the second conductive type region.

3. The SOI semiconductor structure according to claim 1, characterized in that: The vertical device is a VDMOS device, the first source region and the first drain region have a first conductivity type, and the doping concentration of the first drain region is greater than the doping concentration of the substrate.

4. The SOI semiconductor structure according to claim 1, characterized in that: The first device comprises: A CMOS well region, having a second conductivity type, disposed above the buried dielectric region; A CMOS source region, having a first conductivity type, disposed in the CMOS well region; A CMOS drain region, having a first conductivity type, disposed in the CMOS well region; and The CMOS gate is disposed on the CMOS well region between the CMOS source region and the CMOS drain region.

5. The SOI semiconductor structure according to claim 4, characterized in that: The CMOS source region, the CMOS drain region and the first source region are located at the same level in the SOI semiconductor structure.

6. The SOI semiconductor structure according to claim 2, characterized in that: The second insulating isolation portion is a closed ring structure, surrounding the second conductive type region in a lateral direction.

7. A method for manufacturing a SOI semiconductor structure, comprising: Providing a wafer, the wafer comprising a substrate, a buried dielectric region located on the substrate, and a top semiconductor layer located on the buried dielectric region, the substrate having a first conductivity type, the top semiconductor layer having a second conductivity type, the first conductivity type being opposite to the second conductivity type; Patterning the wafer to remove the top semiconductor layer and the buried dielectric region located in the vertical device region, thereby exposing the substrate located in the vertical device region; forming a first insulating isolation portion on a side of the vertical device region; Epitaxially forming a first conductive type region in the vertical device region; the first conductive type region and the top semiconductor layer are separated by the first insulating isolation portion; A CMOS device is formed on the top semiconductor layer by a CMOS process, and a first well region and a first source region are formed in the vertical device region; the first well region is formed in the first conductive type region, the first well region has a second conductive type, and the first source region is formed in the first well region; In the top semiconductor layer, a portion between the first insulating isolation portion and the CMOS device is a depletion region; and A first drain region is formed at the bottom of the substrate.

8. The method according to claim 7, characterized in that The patterning of the wafer further includes forming an isolation trench, the isolation trench separating the top semiconductor layer into a first device region and the depletion region, the depletion region being located between the isolation trench and the first insulating isolation portion; The forming of the first insulating isolation portion on the side of the vertical device region comprises: depositing an insulating dielectric material on the front side of the wafer, so that the isolation groove is filled with the insulating dielectric material to form a second insulating isolation portion, and forming the first insulating isolation portion on the side of the vertical device region; The forming of a CMOS device in the top semiconductor layer by using a CMOS process includes: forming a CMOS device in the first device area.

9. The method according to claim 7, characterized in that: The wafer also includes a dielectric layer on the top semiconductor layer; After forming the first conductive type region by epitaxial growth in the vertical device region and before forming a CMOS device on the top semiconductor layer by a CMOS process, the method further includes: removing the dielectric layer.

10. The method according to claim 7, characterized in that The forming of the CMOS device on the top semiconductor layer by the CMOS process includes: forming a CMOS well region, a CMOS source region, a CMOS drain region and a CMOS gate by the CMOS process; the CMOS well region has a second conductivity type and is formed above the buried dielectric region, the CMOS source region and the CMOS drain region have a first conductivity type and are formed in the CMOS well region, and the CMOS gate is formed on the CMOS well region between the CMOS source region and the CMOS drain region; the first source region and the first drain region have a first conductivity type, and the doping concentration of the first drain region is greater than the doping concentration of the substrate.

Images