Display panel and manufacturing method therefor, driving method, and display device

Abstract

Provided are a display panel and a manufacturing method therefor, a driving method, and a display device, relating to the technical field of display. The display panel comprises multiple first sub-pixels and multiple second sub-pixels located on a substrate, the first sub-pixels and the second sub-pixels each comprise a pixel circuit layer and a light-emitting unit layer which are sequentially stacked in the direction away from the substrate, and the display panel further comprises a pixel defining layer and light-shielding layers located on one side of the light-emitting unit layer. Light-shielding portions of the light-shielding layers overlap with pixel defining portions defining the first sub-pixels, so that a light emission angle can be adjusted by flexibly lighting up the first sub-pixels and the second sub-pixels, so as to achieve switching between anti-peeping and sharing. In addition, switching circuits, used for controlling a switching element to be connected to / disconnected from a driving circuit, in the first sub-pixels are different from switching circuits, used for controlling the switching element to be connected to / disconnected from the driving circuit, in the second sub-pixels, so that independent light emission control of the first sub-pixels and the second sub-pixels can also be implemented, thereby flexibly adjusting the anti-peeping viewing angle.

Description

Display panel, manufacturing method thereof, driving method thereof, and display device

[0001] This disclosure claims priority to Chinese patent application No. 202310802028.6 filed on June 30, 2023, entitled “Display panel, preparation method thereof, driving method, and display device,” the entire contents of which are incorporated herein by reference. Technical Field

[0002] The present disclosure relates to the field of display technology, and in particular to a display panel, a manufacturing method thereof, a driving method thereof, and a display device. Background Art

[0003] With the development of display technology, display products such as mobile phones and computers are being used more and more widely. When using display products, users hope to share display information with others on the one hand, and on the other hand, they hope to have privacy in some special scenarios to prevent the display information from being peeped by others.

[0004] In related technologies, based on the user's sharing and privacy protection needs, a display technology that achieves sharing and privacy protection switching is proposed. For example, a common method currently includes: attaching a privacy film to the light-emitting side of the display screen. When privacy protection is required, the privacy film is used to block the display screen to achieve the privacy protection effect; when privacy protection is not required, the privacy film is removed. Alternatively, for currently common liquid crystal display panels, an additional liquid crystal layer is added, and the light output angle of the display screen is limited by the rotation of the liquid crystal molecules in the liquid crystal layer, achieving the purpose of privacy protection or sharing.

[0005] However, the methods in the related art can only realize the switching between anti-peeping and sharing, but cannot flexibly control the anti-peeping viewing angle, and the anti-peeping flexibility is poor.

[0006] Summary of the Invention

[0007] Provided are a display panel, a manufacturing method thereof, a driving method, and a display device, which can solve the problem in related technologies of being unable to flexibly control the anti-peeping viewing angle and having poor anti-peeping flexibility. The technical solution is as follows:

[0008] In one aspect, a display panel is provided, comprising:

[0009] A substrate having a plurality of pixel sub-regions, each pixel sub-region including a plurality of pixel unit regions, each pixel unit region including a first pixel unit region and a second pixel unit region;

[0010] A plurality of first sub-pixels and a plurality of second sub-pixels of different colors are located in each pixel sub-region, the plurality of pixel unit regions corresponding one to one and the first sub-pixels are located in the first pixel unit region, the second sub-pixels are located in the second pixel unit region, and the first sub-pixels and the second sub-pixels each include: a pixel circuit layer and a light-emitting unit layer stacked in sequence in a direction away from the substrate;

[0011] Furthermore, the display panel further comprises: a pixel defining layer, an encapsulation layer, and a multi-layer light-shielding layer, which are located on one side of the light-emitting unit layer and stacked in sequence in a direction away from the substrate; the pixel defining layer has a plurality of openings and a pixel defining portion surrounding each opening, and the light-emitting unit layers of any two adjacent sub-pixels among the plurality of first sub-pixels and the plurality of second sub-pixels are located within the openings and are defined by the pixel defining layer; the light-shielding layer comprises a plurality of light-shielding portions spaced apart from each other, and the orthographic projections of the plurality of light-shielding portions on the substrate overlap with the orthographic projections of the pixel defining portions defining the first sub-pixels on the substrate;

[0012] Furthermore, the pixel circuit layer is used to form a pixel circuit, and the light-emitting unit layer is used to form a light-emitting element. The pixel circuit includes: a driving circuit and a switching circuit. Moreover, the pixel circuits in the one-to-one corresponding first sub-pixel and the second sub-pixel include different switching circuits and share the same driving circuit.

[0013] The switching circuit is coupled to the switch control terminal, the driving circuit and the light-emitting element respectively, and is used to control the on and off of the driving circuit and the light-emitting element based on the switch control signal provided by the switch control terminal. The driving circuit is used to generate a driving signal to drive the light-emitting element to emit light.

[0014] Optionally, in the one-to-one corresponding first sub-pixel and the second sub-pixel, the area of ​​the light-emitting element included in the first sub-pixel is smaller than the area of ​​the light-emitting element included in the second sub-pixel.

[0015] Optionally, the first pixel unit area includes a plurality of pixel unit sub-areas defined by the pixel defining portion;

[0016] The light-emitting unit layer includes an anode, a light-emitting layer and a cathode stacked in sequence in a direction away from the substrate; and the anode of the first sub-pixel located in each first pixel unit area includes multiple anode parts located in the multiple pixel unit sub-areas and coupled to each other.

[0017] Optionally, a shape of a pixel unit sub-region in the first pixel unit region is different from a shape of the second pixel unit region.

[0018] Optionally, the display panel further includes:

[0019] A spacer layer located between each two adjacent light-shielding layers in the multi-layer light-shielding layer;

[0020] a first coating layer located on a side of the multi-layer light-shielding layer away from the substrate;

[0021] A touch layer and a second coating layer located between the encapsulation layer and the multi-layer light shielding layer and stacked in sequence in a direction away from the substrate;

[0022] The touch layer includes a plurality of touch electrodes spaced apart from each other, and each touch electrode includes an interlayer defining layer, a first electrode layer, and a second electrode layer stacked in sequence in a direction away from the substrate;

[0023] Furthermore, the orthographic projection of each touch electrode on the substrate overlaps with the orthographic projection of a portion of the pixel definition layer located between two adjacent pixel unit areas on the substrate.

[0024] Optionally, the display panel includes: two light shielding layers, and a distance between the two light shielding layers is greater than 5 microns;

[0025] Furthermore, the light shielding layer includes a black matrix layer or a black pixel defining layer.

[0026] Optionally, the display panel further includes: a filter portion located between every two adjacent light-shielding portions in at least one light-shielding layer.

[0027] Optionally, in the one-to-one corresponding first sub-pixel and the second sub-pixel, the driving circuit of each sub-pixel is further coupled to the gate signal terminal, the data signal terminal, and the driving power terminal, respectively, and is configured to generate the driving signal based on the gate driving signal provided by the gate signal terminal, the data signal provided by the data signal terminal, and the driving power signal provided by the driving power terminal; the switching circuit of each sub-pixel includes: a first switching transistor;

[0028] The gate of the first switch transistor is coupled to the switch control terminal, the first electrode of the first switch transistor is coupled to the drive circuit, and the second electrode of the first switch transistor is coupled to the light-emitting element.

[0029] Optionally, the driving circuit of each sub-pixel includes: a first data writing transistor, a first driving transistor and a first storage capacitor;

[0030] Among them, the gate of the first data writing transistor is coupled to the gate signal terminal, the first electrode of the first data writing transistor is coupled to the data signal terminal, and the second electrode of the first data writing transistor is coupled to the first end of the first storage capacitor; the second end of the first storage capacitor is coupled to the driving power supply terminal; the gate of the first driving transistor is coupled to the first end of the first storage capacitor, the first electrode of the first driving transistor is coupled to the driving power supply terminal, and the second electrode of the first driving transistor is coupled to the first electrode of the first switching transistor.

[0031] Optionally, in the one-to-one corresponding first sub-pixel and the second sub-pixel, the switching circuit of at least one sub-pixel is further coupled to the driving power supply terminal and the driving circuit, respectively, and is further configured to control the connection and disconnection between the driving power supply terminal and the driving circuit based on the switching control signal; the switching circuit of at least one sub-pixel further includes: a second switching transistor;

[0032] The gate of the second switch transistor is coupled to the switch control terminal, the first electrode of the second switch transistor is coupled to the driving power supply terminal, and the second electrode of the second switch transistor is coupled to the driving circuit.

[0033] Optionally, the driving circuit of each sub-pixel includes: a second data writing transistor, a second driving transistor, a compensation transistor and a second storage capacitor;

[0034] In which, the gate of the second data writing transistor and the gate of the compensation transistor are both coupled to the gate signal terminal, the first electrode of the second data writing transistor is coupled to the data signal terminal, and the second electrode of the second data writing transistor is coupled to the first electrode of the second driving transistor; the first electrode of the compensation transistor is coupled to the second electrode of the second driving transistor, and the second electrode of the compensation transistor is coupled to the gate of the second driving transistor; the first electrode of the second driving transistor is coupled to the second electrode of the second switching transistor; the first end of the second storage capacitor is coupled to the gate of the second driving transistor, and the second end of the second storage capacitor is coupled to the driving power supply terminal.

[0035] Optionally, in different switch circuits included in the pixel circuits of the one-to-one corresponding first sub-pixel and the second sub-pixel, the types of switch transistors are the same, and the different switch circuits are respectively coupled to different switch control terminals;

[0036] Alternatively, the pixel circuits in the one-to-one corresponding first sub-pixel and the second sub-pixel include different switching circuits with different switching transistor types, and the different switching circuits share the same switch control terminal.

[0037] Optionally, the display panel includes: a plurality of first pixels located in the plurality of pixel subregions, each first pixel including a plurality of subpixels of different colors, and each subpixel including a first subpixel and a second subpixel in one-to-one correspondence;

[0038] Alternatively, the display panel includes: multiple first pixels and multiple second pixels located in the multiple pixel partitions, each first pixel includes multiple first sub-pixels of different colors, and each second pixel includes multiple second sub-pixels of different colors corresponding one-to-one to the multiple first sub-pixels.

[0039] In another aspect, a method for manufacturing a display panel is provided, for manufacturing the display panel according to the above aspect; the method comprising:

[0040] Providing a substrate, wherein the provided substrate has a plurality of pixel sub-regions, each pixel sub-region includes a plurality of pixel unit regions, and each pixel unit region includes a first pixel unit region and a second pixel unit region;

[0041] In each pixel sub-region, a plurality of first sub-pixels and a plurality of second sub-pixels having one-to-one correspondence and different colors are formed in the plurality of pixel unit regions, and the formed first sub-pixels are located in the first pixel unit region, and the second sub-pixels are located in the second pixel unit region, and the first sub-pixels and the second sub-pixels each include: a pixel circuit layer and a light-emitting unit layer stacked sequentially in a direction away from the substrate, the pixel circuit layer being used to form a pixel circuit, and the light-emitting unit layer being used to form a light-emitting element;

[0042] A pixel defining layer, an encapsulation layer, and a multi-layer light-shielding layer are formed on one side of the light-emitting unit layer, which are sequentially stacked in a direction away from the substrate. The pixel defining layer has a plurality of openings and a pixel defining portion surrounding each opening. The light-emitting unit layers of any two adjacent sub-pixels among the plurality of first sub-pixels and the plurality of second sub-pixels are located within the openings and are defined by the pixel defining portion. The light-shielding layer includes a plurality of light-shielding portions spaced apart from each other, and the orthographic projections of the plurality of light-shielding portions on the substrate overlap with the orthographic projections of the pixel defining portion defining the first sub-pixel on the substrate.

[0043] The pixel circuit formed includes: a driving circuit and a switching circuit, and the pixel circuits in the one-to-one corresponding first sub-pixel and the second sub-pixel include different switching circuits and share the same driving circuit;

[0044] The switching circuit is coupled to the switch control terminal, the driving circuit and the light-emitting element respectively, and is used to control the on and off of the driving circuit and the light-emitting element based on the switch control signal provided by the switch control terminal. The driving circuit is used to generate a driving signal to drive the light-emitting element to emit light.

[0045] In another aspect, a method for driving a display panel is provided, which is applied to the display panel as described in the above aspect; the method comprises:

[0046] In response to the anti-peeping instruction, providing a switch control signal with an effective potential to a switch control terminal coupled to a pixel circuit in a first sub-pixel, so that a switch circuit included in the pixel circuit in the first sub-pixel controls a drive circuit and a light-emitting element included therein to conduct based on the switch control signal with the effective potential;

[0047] In response to the privacy protection instruction, a switch control signal with an invalid potential is provided to a switch control terminal coupled to a pixel circuit in a second sub-pixel corresponding to the first sub-pixel; the switch circuit included in the pixel circuit in the second sub-pixel controls the included drive circuit to disconnect from the light-emitting element based on the switch control signal with the invalid potential; or a switch control signal in the form of a pulse is provided to the switch control terminal coupled to the pixel circuit in the second sub-pixel; the switch circuit included in the pixel circuit in the second sub-pixel controls the included drive circuit to periodically switch on and off with the light-emitting element based on the switch control signal in the form of a pulse;

[0048] In response to the sharing instruction, providing a switch control signal with an effective potential to a switch control terminal coupled to the pixel circuit in the second sub-pixel, so that the switch circuit included in the pixel circuit in the second sub-pixel controls the included driving circuit and the light-emitting element to be turned on based on the switch control signal with the effective potential;

[0049] In response to the sharing instruction, a switch control signal of an effective potential is provided to a switch control terminal coupled to the pixel circuit in the first sub-pixel, and the switch circuit included in the pixel circuit in the first sub-pixel controls the included driving circuit and the light-emitting element to be turned on based on the switch control signal of the effective potential; or a switch control signal in the form of a pulse is provided to the switch control terminal coupled to the pixel circuit in the first sub-pixel, and the switch circuit included in the pixel circuit in the first sub-pixel controls the included driving circuit and the light-emitting element to be periodically turned on and off based on the switch control signal in the form of a pulse;

[0050] When the driving circuit is connected to the light-emitting element, the driving signal generated by the driving circuit is transmitted to the light-emitting element to drive the light-emitting element to emit light.

[0051] In another aspect, a display device is provided, comprising: a power supply component, and the display panel according to the above aspect;

[0052] The power supply component is coupled to the display panel and is used to supply power to the display panel. BRIEF DESCRIPTION OF THE DRAWINGS

[0053] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0054] FIG1 is a schematic structural diagram of a display panel provided by an embodiment of the present disclosure;

[0055] FIG2 is a schematic diagram of a film layer of a display panel provided by an embodiment of the present disclosure;

[0056] FIG3 is a schematic diagram of light emission from a sub-pixel in a display panel provided by an embodiment of the present disclosure;

[0057] FIG4 is a schematic diagram of light emission from a sub-pixel in another display panel provided by an embodiment of the present disclosure;

[0058] FIG5 is a block diagram of a sub-pixel structure provided by an embodiment of the present disclosure;

[0059] FIG6 is a schematic diagram of sub-pixel division in a display panel provided by an embodiment of the present disclosure;

[0060] FIG7 is a schematic diagram of sub-pixel division in another display panel provided by an embodiment of the present disclosure;

[0061] FIG8 is a schematic diagram of sub-pixel division in another display panel provided by an embodiment of the present disclosure;

[0062] FIG9 is a schematic diagram of sub-pixel division in another display panel provided by an embodiment of the present disclosure;

[0063] FIG10 is a schematic diagram of area division in a display panel provided by an embodiment of the present disclosure;

[0064] FIG11 is a schematic diagram of a partial film layer of a display panel provided by an embodiment of the present disclosure;

[0065] FIG12 is a schematic diagram of another area division in a display panel provided by an embodiment of the present disclosure;

[0066] FIG13 is a schematic diagram of area division in another display panel provided by an embodiment of the present disclosure;

[0067] FIG14 is a schematic diagram of area division in another display panel provided by an embodiment of the present disclosure;

[0068] FIG15 is a schematic diagram of a film layer of another display panel provided by an embodiment of the present disclosure;

[0069] FIG16 is a schematic diagram of a film layer of another display panel provided by an embodiment of the present disclosure;

[0070] FIG17 is a schematic diagram of a film layer of another display panel provided by an embodiment of the present disclosure;

[0071] FIG18 is a block diagram of another sub-pixel structure provided by an embodiment of the present disclosure;

[0072] FIG19 is a schematic structural diagram of a pixel circuit in a sub-pixel provided by an embodiment of the present disclosure;

[0073] FIG20 is a schematic structural diagram of a pixel circuit in another sub-pixel provided by an embodiment of the present disclosure;

[0074] FIG21 is a structural block diagram of another sub-pixel provided in an embodiment of the present disclosure;

[0075] FIG22 is a schematic structural diagram of a pixel circuit in another sub-pixel provided by an embodiment of the present disclosure;

[0076] FIG23 is a schematic structural diagram of a pixel circuit in yet another sub-pixel provided by an embodiment of the present disclosure;

[0077] FIG24 is a schematic structural diagram of a pixel circuit in yet another sub-pixel provided by an embodiment of the present disclosure;

[0078] FIG25 is a flow chart of a method for manufacturing a display panel according to an embodiment of the present disclosure;

[0079] FIG26 is a schematic diagram of a portion of film layers in a display panel provided based on the structure shown in FIG2 ;

[0080] FIG27 is a schematic diagram of a portion of film layers in another display panel provided based on the structure shown in FIG2 ;

[0081] FIG28 is a schematic diagram of a portion of film layers in another display panel provided based on the structure shown in FIG2 ;

[0082] FIG29 is a schematic diagram of a portion of film layers in another display panel provided based on the structure shown in FIG2 ;

[0083] FIG30 is a schematic diagram of a portion of film layers in another display panel provided based on the structure shown in FIG2 ;

[0084] FIG31 is a schematic diagram of a portion of film layers in a display panel provided based on the structure shown in FIG16 ;

[0085] FIG32 is a schematic diagram of a portion of film layers in another display panel provided based on the structure shown in FIG16 ;

[0086] FIG33 is a schematic diagram of a portion of film layers in another display panel provided based on the structure shown in FIG16 ;

[0087] FIG34 is a schematic diagram of a portion of film layers in another display panel provided based on the structure shown in FIG16 ;

[0088] FIG35 is a schematic diagram of a portion of film layers in another display panel provided based on the structure shown in FIG16 ;

[0089] FIG36 is a schematic diagram of a portion of film layers in another display panel provided based on the structure shown in FIG16 ;

[0090] FIG37 is a schematic diagram of a portion of film layers in another display panel provided based on the structure shown in FIG16 ;

[0091] FIG38 is a flow chart of a method for driving a display panel according to an embodiment of the present disclosure;

[0092] FIG39 is a signal timing diagram provided based on the structure shown in FIG19;

[0093] FIG40 is a schematic diagram of a viewing angle curve provided based on the timing sequence shown in FIG39;

[0094] FIG41 is another signal timing diagram provided based on the structure shown in FIG19;

[0095] FIG42 is another signal timing diagram provided based on the structure shown in FIG19;

[0096] FIG43 is a signal timing diagram provided based on the structure shown in FIG20;

[0097] FIG44 is a signal timing diagram provided based on the structure shown in FIG22;

[0098] FIG45 is a signal timing diagram provided based on the structure shown in FIG23;

[0099] FIG46 is a signal timing diagram provided based on the structure shown in FIG24;

[0100] FIG47 is a schematic structural diagram of a display device provided in an embodiment of the present disclosure. DETAILED DESCRIPTION

[0101] In order to make the objectives, technical solutions and advantages of the present disclosure more clear, the embodiments of the present disclosure will be further described in detail below with reference to the accompanying drawings.

[0102] FIG1 is a schematic diagram of the structure of a display panel provided by an embodiment of the present disclosure. As shown in FIG1 , the display panel includes:

[0103] Substrate 01. Substrate 01 has multiple pixel sub-areas Q1. Each pixel sub-area Q1 includes multiple pixel unit areas Q11. Each pixel unit area Q11 includes a first pixel unit area Q11-1 and a second pixel unit area Q11-2. Furthermore, within each pixel sub-area Q1, multiple first sub-pixels P1 and multiple second sub-pixels P2, each corresponding to each other and having different colors within the multiple pixel unit areas Q11, are provided. The first sub-pixels P1 are located in the first pixel unit area Q11-1, and the second sub-pixels P2 are located in the second pixel unit area Q11-2.

[0104] For example, in the display panel shown in FIG1 , each pixel sub-area Q1 of substrate 01 includes three pixel unit areas Q11, and three first sub-pixels P1 and three second sub-pixels P2 correspondingly located within the three pixel unit areas Q11. Specifically, each first sub-pixel P1 is located in a first pixel unit area Q11-1 within a pixel unit area Q11, and different first sub-pixels P1 are located in first pixel unit areas Q11-1 within different pixel unit areas Q11. Similarly, each second sub-pixel P2 is located in a second pixel unit area Q11-2 within a pixel unit area Q11, and different second sub-pixels P2 are located in second pixel unit areas Q11-2 within different pixel unit areas Q11. Furthermore, within the same pixel unit area Q11, the first sub-pixel P1 located in the first pixel unit area Q11-1 and the second sub-pixel P2 located in the second pixel unit area Q11-2 have the same color. For example, referring to FIG1 , for each pixel subarea Q1, the colors of the three first subpixels P1 located in its three pixel unit regions Q11 are green (G), red (R), and blue (B), respectively, and are labeled P1-G, P1-R, and P1-B in the figure. The colors of the corresponding three second subpixels P2 are also green (G), red (R), and blue (B), respectively, and are labeled P2-G, P2-R, and P2-B in the figure. Furthermore, the green first subpixel P1-G and the second subpixel P2-G are located in the first pixel unit region Q11-1 and the second pixel unit region Q11-2 included in the same pixel unit region Q11; the red first subpixel P1-R and the second subpixel P2-R are located in the first pixel unit region Q11-1 and the second pixel unit region Q11-2 included in the same pixel unit region Q11; and the blue first subpixel P1-B and the second subpixel P2-B are located in the first pixel unit region Q11-1 and the second pixel unit region Q11-2 included in the same pixel unit region Q11. Of course, the above positional relationship is only a schematic illustration.

[0105] Continuing with FIG2 , based on FIG1 , it can be seen that both first subpixel P1 and second subpixel P2 include: a pixel circuit layer 02 and a light-emitting unit layer 03, stacked sequentially in a direction away from substrate 01. Pixel circuit layer 02 is used to form pixel circuit 021, and light-emitting unit layer 03 is used to form light-emitting element 031. Pixel circuit 021 is coupled to light-emitting element 031 and is used to drive light-emitting element 031 to emit light.

[0106] The display panel also includes: a pixel definition layer (PDL) 04 (also called a PDL layer), located on one side of the light-emitting unit layer 03 and stacked in a direction away from the substrate 01; an encapsulation layer 05; and a multi-layer light shielding layer 06. Optionally, the encapsulation layer 05 can be a thin film encapsulation (TFE), and accordingly, the encapsulation layer 05 can also be called a TFE layer.

[0107] The pixel defining layer 04 has a plurality of openings 04K and a pixel defining portion 041 surrounding each opening 04K. The light-emitting unit layer 03 of any two adjacent sub-pixels among the plurality of first sub-pixels P1 and the plurality of second sub-pixels P2 is located within the opening 04K and is defined by the pixel defining portion 041. Furthermore, the light-shielding layer 06 includes a plurality of light-shielding portions 061 spaced apart from each other, and the orthographic projections of the plurality of light-shielding portions 061 on the substrate 01 overlap with the orthographic projections of the pixel defining portion 041 defining the first sub-pixel P1 on the substrate 01 (referred to as a first overlapping region). Furthermore, the orthographic projections of the plurality of light-shielding portions 061 on each layer of the light-shielding layer 06 on the substrate 01 overlap with the orthographic projections of the pixel defining portion 041 defining the first sub-pixel P1 on the substrate 01, but do not overlap with the orthographic projections of the pixel defining portion 041 defining the second sub-pixel P2 on the substrate 01. Of course, in some embodiments, the orthographic projection of the multiple shading portions 061 of only a portion of the shading layer 06 on the substrate 01 may also overlap with the orthographic projection of the pixel defining portion 041 that defines the second sub-pixel P2 on the substrate 01 (referred to as the second overlapping area), but the area of ​​the second overlapping area here is smaller than the area of ​​the first overlapping area.

[0108] For example, referring to Figures 2 to 4 , the display panels shown therein each include two sequentially stacked light-shielding layers 06. Furthermore, in the two light-shielding layers 06 shown therein, the orthographic projections of the multiple light-shielding portions 061 of each light-shielding layer 06 on the substrate 01 completely overlap with the orthographic projections of the pixel-defining portion 041 defining the first sub-pixel P1 on the substrate 01. Furthermore, in the two light-shielding layers 06 shown in Figure 2 , the orthographic projections of the multiple light-shielding portions 061 of the light-shielding layer 06 closer to the substrate 01 do not overlap with the orthographic projections of the pixel-defining portion 041 defining the second sub-pixel P2 on the substrate 01, while the orthographic projections of the multiple light-shielding portions 061 of the other light-shielding layer 06 farther from the substrate 01 overlap with the orthographic projections of the pixel-defining portion 041 defining the second sub-pixel P2 on the substrate 01, and the orthographic projections of the light-shielding portions 061 on the substrate 01 are located within the orthographic projections of the pixel-defining portion 041 on the substrate 01.

[0109] On this basis, comparing the light rays shown in Figures 3 and 4 also shows that for the first sub-pixel P1, because the pixel defining portion 041 that defines it is completely covered by the light shielding portion 061, the light emitted by the light-emitting unit layer 03 will be blocked by the light shielding portion 061. That is, the light shielding portion 061 will limit the light emission angle to a certain extent, forming an anti-peeping angle. For the second sub-pixel P2, because only a portion of the pixel defining portion 041 that defines it is covered by the smaller light shielding portion 061, the light emission angle is larger than that of the first sub-pixel P1, and the anti-peeping angle is smaller. Based on this, in the embodiment of the present disclosure, the first sub-pixel P1 can also be referred to as the anti-peeping sub-pixel, and the first pixel unit area Q11-1 can be referred to as the anti-peeping area; the second sub-pixel P2 can be referred to as the normal sub-pixel, and the second pixel unit area Q11-2 can be referred to as the normal area. The provision of multiple light shielding layers 06 can also limit the light emission angle, reducing the light emitted at a wide viewing angle. It should be noted that, referring to FIG. 2 , it can be seen that the light emitting unit layer 03 may include an anode Anode, a light emitting layer EL, and a cathode (not shown) stacked in sequence, and the pixel defining portion 041 may define the anode Anode in the light emitting unit layer 03 .

[0110] 5 , based on FIG2 , it can be seen that the pixel circuit 021 in each sub-pixel described in the embodiment of the present disclosure includes a driving circuit 0211 and a switching circuit 0212. Furthermore, the pixel circuits 021 in the first sub-pixel P1 and the second sub-pixel P2, which correspond to each other, include different switching circuits 0212, but share the same driving circuit 0211.

[0111] Among them, the switching circuit 0212 is coupled to the switch control terminal Con1, the driving circuit 0211 and the light-emitting element 031 respectively, and is used to control the on and off of the driving circuit 0211 and the light-emitting element 031 based on the switching control signal provided by the switch control terminal Con1. The driving circuit 0211 is used to generate a driving signal (such as a driving current) to drive the light-emitting element 031 to emit light.

[0112] For example, when the potential of the switch control signal provided by the switch control terminal Con1 is an effective potential (also called a first potential), the switch circuit 0212 can control the drive circuit 0211 to be connected to the light-emitting element 031, so that the drive signal generated by the drive circuit 0211 can be transmitted to the light-emitting element 031, thereby driving the light-emitting element 031 to emit light. When the potential of the switch control signal provided by the switch control terminal Con1 is an inactive potential (also called a second potential), the switch circuit 0212 can control the drive circuit 0211 to be disconnected from the light-emitting element 031.

[0113] When the switch circuit 0212 in the first sub-pixel P1 controls the driving circuit 0211 and the light-emitting element 031 to be turned on, the light-emitting element 031 included in the first sub-pixel P1 can be illuminated, that is, emit light; when the switch circuit 0212 in the second sub-pixel P2 controls the driving circuit 0211 and the light-emitting element 031 to be turned on, the light-emitting element 031 included in the second sub-pixel P2 can be illuminated, that is, emit light. In some embodiments, in combination with the above description, the light-emitting element 031 included in the first sub-pixel P1 and the light-emitting element 031 included in the second sub-pixel P2 can be controlled to be illuminated at the same time to achieve a sharing function; the anti-peeping function can be achieved by controlling only the light-emitting element 031 included in the first sub-pixel P1 in the first sub-pixel P1 and the second sub-pixel P2 to be illuminated. That is, the display panel described in the embodiments of the present disclosure can achieve switching between anti-peeping and sharing. In addition, since the one-to-one corresponding first sub-pixel P1 (anti-peeping sub-pixel) and second sub-pixel P2 (normal sub-pixel) include different switching circuits 0212, the switching control signal provided to the switch control terminal Con1 coupled to different switching circuits 0212 can be flexibly set so that different switching circuits 0212 can flexibly control the luminous state (i.e., luminous or non-luminous) and luminous brightness of the anti-peeping sub-pixel and the normal sub-pixel, thereby realizing independent lighting of the anti-peeping sub-pixel and the normal sub-pixel, thereby achieving the purpose of flexibly controlling the anti-peeping viewing angle.

[0114] That is, in the embodiment of the present disclosure, since the pixel circuits in the one-to-one corresponding first sub-pixel P1 (anti-peeping sub-pixel) and the second sub-pixel P2 (normal sub-pixel) share the same driving circuit 0211 and include different switching circuits 0212, it is possible to ensure better anti-peeping flexibility on the basis of simplifying the pixel structure to save costs and facilitate high-resolution design.

[0115] Optionally, referring to FIG5 , the switch circuit 0212 may be coupled to the anode of the light-emitting element 031, and the cathode of the light-emitting element 031 may also be coupled to the pull-down power supply terminal Vss. The light-emitting layer in the light-emitting element 031 may emit light under the voltage difference between the drive signal received by the anode and the pull-down power supply signal provided by the pull-down power supply terminal Vss received by the cathode. Of the effective potential and the invalid potential, one may be a low potential relative to the other. For example, for a circuit including a P-type transistor, the effective potential received may be a low potential relative to the invalid potential. For a circuit including an N-type transistor, the effective potential received may be a high potential relative to the invalid potential.

[0116] In summary, an embodiment of the present disclosure provides a display panel. The display panel includes a plurality of first sub-pixels and a plurality of second sub-pixels located on a substrate, and the first sub-pixels and the second sub-pixels both include a pixel circuit layer and a light-emitting unit layer stacked in sequence in a direction away from the substrate, and the display panel also includes a pixel defining layer and a light-shielding layer located on one side of the light-emitting unit layer. Because the light-shielding portion of the light-shielding layer overlaps with the pixel defining portion that defines the first sub-pixel, the light emission angle can be adjusted by flexibly lighting the first sub-pixel and the second sub-pixel to achieve switching between anti-peeping and sharing. In addition, because the switch circuits that control the on / off of the switch element and the drive circuit in the first sub-pixel and the second sub-pixel are different, independent control of the light emission of the first sub-pixel and the second sub-pixel can also be achieved, thereby flexibly adjusting the anti-peeping viewing angle and improving anti-peeping flexibility.

[0117] As an optional implementation method: Based on Figure 1, combined with Figures 6 and 7, it can be seen that the display panel recorded in the embodiment of the present disclosure may include: multiple first pixels P-1 located in multiple pixel partitions Q1, each first pixel P-1 may include multiple sub-pixels P0 of different colors, and each sub-pixel P0 may include a one-to-one corresponding first sub-pixel P1 and a second sub-pixel P2. On this basis, it can be seen that the number of multiple pixel partitions Q1 is the same as the number of multiple first pixels P-1, and the multiple first pixels P-1 and the multiple pixel partitions Q1 can correspond one-to-one. That is, a split design can be used to divide each sub-pixel in a pixel into two, as a one-to-one corresponding first sub-pixel P1 and a second sub-pixel P2. It should be noted that this may refer to dividing the anode Anode included in the sub-pixel into two.

[0118] For example, referring to Figures 6 and 7, each first pixel P-1 shown therein includes three sub-pixels P0 of three different colors: a red sub-pixel P0-R, a green sub-pixel P0-G, and a blue sub-pixel P0-B. The red sub-pixel P0-R includes a first red sub-pixel P1-R and a second red sub-pixel P2-R divided into two; the green sub-pixel P0-G includes a first red sub-pixel P1-G and a second red sub-pixel P2-G divided into two; and the blue sub-pixel P0-B includes a first red sub-pixel P1-B and a second red sub-pixel P2-B divided into two. The difference between Figures 6 and 7 lies in the different pixel shapes. The first pixel P-1 shown in Figure 6 is elliptical, while the first pixel P-1 shown in Figure 7 is rectangular. Of course, the shapes here are only schematic illustrations.

[0119] As another optional implementation: With reference to Figures 8 and 9, it can be seen that the display panel described in the embodiment of the present disclosure may include: a plurality of first pixels P-1 and a plurality of second pixels P-2 located in a plurality of pixel partitions Q1, each first pixel P-1 may include a plurality of first sub-pixels P1 of different colors, and each second pixel P-2 may include a plurality of second sub-pixels P2 of different colors corresponding one-to-one to the plurality of first sub-pixels P1. On this basis, it can be seen that the number of the plurality of pixel partitions Q1 is equal to the sum of the number of the plurality of first pixels P-1 and the number of the plurality of second pixels P-2. In other words, a group of two pixels can be directly set to realize anti-peeping and sharing switching, rather than dividing each sub-pixel in a pixel into two to realize anti-peeping and sharing switching. It should be noted that, under the premise that the size of the display panel is certain, the schemes shown in Figures 8 and 9 need to sacrifice a certain resolution relative to the schemes shown in Figures 6 and 7, which is not conducive to high-resolution design.

[0120] For example, referring to Figures 8 and 9, each first pixel P-1 shown therein includes three first sub-pixels P1 of three different colors: a red first sub-pixel P1-R, a green first sub-pixel P1-G, and a blue first sub-pixel P1-B. Each second pixel P-2 includes three second sub-pixels P2 of three different colors: a red second sub-pixel P2-R, a green second sub-pixel P2-G, and a blue second sub-pixel P2-B. The difference between Figures 8 and 9 also lies in the different pixel shapes. The first pixel P-1 and the second pixel P-2 shown in Figure 8 are both elliptical, similar to those in Figure 6, while the first pixel P-1 and the second pixel P-2 shown in Figure 9 are both rectangular, similar to those in Figure 7. Of course, the shapes here are only for schematic illustration.

[0121] Based on Figure 8, referring to Figure 10, it can be seen that in the embodiment of the present disclosure, the first pixel unit area Q11-1 can include multiple pixel unit sub-areas Q11-11 defined by the pixel defining portion 041, which can also be referred to as anti-peeping cells. For example, in the display panel shown in Figure 10, each first pixel unit area Q11-1 includes two pixel unit sub-areas Q11-11. By dividing the anti-peeping area into more anti-peeping cells, the flexible control of the anti-peeping viewing angle can be further improved, thereby improving the anti-peeping flexibility.

[0122] Furthermore, based on FIG. 10 , referring to FIG. 11 , it can be seen that the anode Anode of the first sub-pixel P1 located in each first pixel unit region Q11-1 can include multiple anode portions Anode0 located in multiple pixel unit sub-regions Q11-11 and coupled to each other. That is, the anode Anodes in each pixel unit sub-region Q11-11 in a pixel unit region Q11-1 can be shared, thereby reducing the number of sub-pixels required, which is beneficial for the high-resolution design of the display panel. FIG. 10 also schematically illustrates an anode Anode film layer diagram and a pixel definition layer PDL film layer diagram. Comparing the anode Anode film layer diagram and the pixel definition layer PDL film layer diagram also shows that only the pixel definition layer PDL is divided into two to define and divide each pixel unit sub-region Q11-11, while the anode Anodes belonging to a first pixel unit region Q11-1 are a single-piece structure. Of course, in some embodiments, the anode Anodes in each pixel unit sub-region Q11-11 in a pixel unit region Q11-1 may not be shared.

[0123] Optionally, continuing to refer to Figure 10, it can be seen that the shape of the pixel unit sub-area Q11-11 in the first pixel unit area Q11-1 can be the same as the shape of the second pixel unit area Q11-2, or, referring to Figures 12, 13 and the layout shown in Figure 14 based on Figure 9, the shape of the pixel unit sub-area Q11-11 in the first pixel unit area Q11-1 can be different from the shape of the second pixel unit area Q11-2.

[0124] For example, in Figure 12, the shape of the pixel unit sub-area Q11-11 in each first pixel unit area Q11-1 where the green first sub-pixel P1-G and the red first sub-pixel P1-R are located is a circle, the first pixel unit area Q11-1 where the blue first sub-pixel P1-B is located and each first pixel unit area Q11-1 where the blue first sub-pixel P1-B is located is a quadrilateral with rounded corners, and the shape of the second pixel unit area Q11-2 is a quadrilateral with rounded corners. In Figures 13 and 14, the shape of the pixel unit sub-area Q11-11 in each first pixel unit area Q11-1 is a circle, and the shape of the second pixel unit area Q11-2 is a quadrilateral with rounded corners. Of course, in some other embodiments, the shape of the pixel unit sub-area Q11-11 can also be other shapes such as an octagon, a trapezoid or an ellipse. The difference between Figure 12 and Figure 14 is that the number of divided pixel unit sub-areas Q11-11 (i.e., anti-peeping areas) is different. In Figure 12, each first pixel unit area Q11-1 is divided into two anti-peeping cells. In Figure 13, each first pixel unit area Q11-1 where the green first sub-pixel P1-G and the red first sub-pixel P1-R are located is divided into two anti-peeping cells, and the first pixel unit area Q11-1 where the blue first sub-pixel P1-B is located is divided into four anti-peeping cells. In Figure 14, each first pixel unit area Q11-1 where the green first sub-pixel P1-G and the red first sub-pixel P1-R are located is divided into four anti-peeping cells, and the first pixel unit area Q11-1 where the blue first sub-pixel P1-B is located is divided into eight anti-peeping cells. It should be noted that the number and shape of the above anti-peeping cells are only schematic illustrations.

[0125] Optionally, as shown in FIG2 , the display panel described in the embodiment of the present disclosure may include two light shielding layers 06. In the embodiment of the present disclosure, the distance between the two light shielding layers 06 may be greater than 5 micrometers (μm).

[0126] Optionally, in combination with FIG. 10 , FIG. 12 and FIG. 13 , in an embodiment of the present disclosure, the length (eg, diameter) of each anti-peeping cell in the anti-peeping direction shown in the figures may be less than 15 μm.

[0127] Optionally, in the embodiment of the present disclosure, in the one-to-one corresponding first sub-pixel P1 and the second sub-pixel P2, the area of ​​the light-emitting element 031 included in the first sub-pixel P1 can be smaller than the area of ​​the light-emitting element 031 included in the second sub-pixel P2, which can refer to the area of ​​the anode Anode in the light-emitting element 031. In this way, the light-emitting area of ​​the first sub-pixel P1 can be smaller than the light-emitting area of ​​the second sub-pixel P2, ensuring that the display effect of the display panel is better in the shared mode. Of course, in some embodiments, the area of ​​the first pixel unit area Q11-1 can also be set to be smaller than the area of ​​the second pixel unit area Q11-2.

[0128] For example, referring to FIG2 , in the display panel shown therein, in a one-to-one correspondence between a first subpixel P1 and a second subpixel P2, the area of ​​the first subpixel P1 is equal to the area of ​​the second subpixel P2. Based on FIG2 , referring to FIG15 , in the display panel shown therein, in a one-to-one correspondence between a first subpixel P1 and a second subpixel P2, the area of ​​the first subpixel P1 is smaller than the area of ​​the second subpixel P2.

[0129] Optionally, referring to FIG. 2 and FIG. 15 , and based on FIG. 11 , FIG. 16 and FIG. 17 respectively show two structures of display panels, it can be seen that the display panel described in the embodiment of the present disclosure may further include:

[0130] The spacer layer 07 is located between each adjacent layer of the multi-layer light-shielding layer 06, and the first overcoating (OC) 08, i.e., the OC1 layer, is located on the side of the multi-layer light-shielding layer 06 away from the substrate 01. Optionally, the spacer layer 07 can be formed using an inkjet printing (IJP) process, and accordingly, the spacer layer 07 can also be referred to as an IJP layer.

[0131] Continuing with Figures 16 and 17 , it can be seen that the display panel may further include a touch layer 09 and a second coating layer 10, or OC2 layer, located between the encapsulation layer 05 and the multi-layer light shielding layer 06 and stacked sequentially away from the substrate 01. Touch layer 09, also known as a flexible multi-layer on cell (FMLOC) layer, is used to implement touch detection.

[0132] The touch layer 09 may include a plurality of touch electrodes 091 spaced apart from each other, each touch electrode 091 including a first electrode layer 0911, an interlayer defining layer 0912, and a second electrode layer 0913 stacked sequentially in a direction away from the substrate 01. Furthermore, the orthographic projection of each touch electrode 091 on the substrate 01 overlaps with the orthographic projection of the portion of the pixel defining layer 04 located between two adjacent pixel unit areas Q11 on the substrate 01. That is, in the disclosed embodiments, as shown in Figures 16 and 17, the touch traces may be arranged on the side of the pixel defining layer PDL surrounding the pixel, rather than within the pixel. This not only prevents interference between touch and display signals, but also simplifies trace routing and saves costs.

[0133] It should be noted that the difference between the structures shown in Figures 16 and 17 is that in the display panel shown in Figure 16, the orthographic projection of the light-shielding portion 061 of the two light-shielding layers 06 on substrate 01 overlaps only with the orthographic projection of the pixel-defining portion 041 that defines the first sub-pixel P1 on substrate 01. However, in the display panel shown in Figure 17, the orthographic projection of the light-shielding portion 061 of the light-shielding layer 06 closer to substrate 01 also overlaps with the orthographic projection of the pixel-defining portion 041 that defines the first sub-pixel P1 on substrate 01. Furthermore, Figures 16 and 17 also illustrate schematic diagrams of light propagation emitted by sub-pixels in the privacy protection zone and the normal zone, respectively.

[0134] Furthermore, referring to FIG17 , it can be seen that the display panel may further include: a color filter (CF) located between each two adjacent light-shielding portions 061 in at least one light-shielding layer 06. This structure can be considered as combining the light-shielding portion 061 with the color filter CF as the light-shielding layer 06. It should be noted that by providing the color filter CF, a light-filtering effect can also be achieved, thereby ensuring a better display effect. Alternatively, in some other embodiments, in conjunction with FIG15 and FIG16 , the light-shielding layer 06 may include: a black matrix layer (BM) or a black pixel defining layer PDL, as long as it can achieve a certain light-shielding effect. The material of the black pixel defining layer PDL may be the same as that of the pixel defining layer 04, such as both including: acrylic or polyimide. The material of the OC1 layer and the OC2 layer may also include: acrylic.

[0135] Optionally, referring to FIG2 and FIG15 , it can be seen that the pixel circuit layer 02 may include: an active (active1) layer ACT, a first gate insulator (GI) layer GI1, a first gate metal layer Gate1, a second gate insulator GI2, a second gate metal layer Gate2, an interlayer dielectric (ILD), and a source & drain (SD) metal layer SD stacked in sequence in a direction away from the substrate 01. Alternatively, referring to FIG16 and FIG17 , it can be seen that the pixel circuit layer 02 may include only one gate metal layer Gate (e.g., the first gate metal layer Gate1) without including the second gate metal layer Gate2, and correspondingly, only one gate insulating layer GI (e.g., the first gate insulating layer GI1) without including the second gate insulating layer GI2. The source & drain metal layer SD may overlap the active layer ACT and may be coupled to the anode Anode. In addition, referring to FIG. 2 and FIG. 15 to FIG. 17 , it can be seen that the display panel may further include: a buffer layer Buffer located between the substrate 01 and the active layer ACT, and a planarization layer (PLN) located between the source / drain metal layer SD and the anode Anode.

[0136] Optionally, the substrate 01 may be made of a flexible material, such as polyimide (PI), and accordingly, the substrate 01 may also be referred to as a PI layer. The active layer ACT may be made of a P-silicon Si material.

[0137] Optionally, it can be seen from another pixel circuit shown in reference Figure 18 that in the one-to-one corresponding first sub-pixel P1 and second sub-pixel P2 recorded in the embodiment of the present disclosure, the driving circuit 0211 of each sub-pixel can also be coupled to the gate signal terminal Gate01, the data signal terminal Vdata and the driving power supply terminal Vdd, respectively, and can be used to generate a driving signal based on the gate driving signal provided by the gate signal terminal Gate01, the data signal provided by the data signal terminal Vdata and the driving power supply signal provided by the driving power supply terminal Vdd.

[0138] As an optional implementation: Based on FIG18 , with reference to the pixel circuit diagram shown in FIG19 , it can be seen that the switch circuit 0212 of each sub-pixel recorded in the embodiment of the present disclosure may include: a first switch transistor T1 - 1 .

[0139] The gate of the first switch transistor T1 - 1 may be coupled to the switch control terminal Con1 , the first electrode of the first switch transistor T1 - 1 may be coupled to the drive circuit 0211 , and the second electrode of the first switch transistor T1 - 1 may be coupled to the light emitting element 031 .

[0140] On this basis, it can be seen from FIG19 that the driving circuit 0211 of each sub-pixel may include: a first data writing transistor T2-1, a first driving transistor T3-1 and a first storage capacitor C1-1.

[0141] The gate of the first data write transistor T2-1 can be coupled to the gate signal terminal Gate01, the first electrode of the first data write transistor T2-1 can be coupled to the data signal terminal Vdata, and the second electrode of the first data write transistor T2-1 can be coupled to the first terminal of the first storage capacitor C1-1. The second terminal of the first storage capacitor C1-1 can be coupled to the driving power supply terminal Vdd. The gate of the first drive transistor T3-1 can be coupled to the first terminal of the first storage capacitor C1-1, the first electrode of the first drive transistor T3-1 can be coupled to the driving power supply terminal Vdd, and the second electrode of the first drive transistor T3-1 can be coupled to the first electrode of the first switch transistor T1-1.

[0142] When the gate signal terminal Gate01 provides a gate drive signal with an effective potential, the first data write transistor T2-1 can be turned on. The data signal provided by the data signal terminal Vdata can be transmitted to the first terminal of the first storage capacitor C1-1 through the turned-on first data write transistor T2-1. Under the coupling effect of the first storage capacitor C1-1, the data signal can be further transmitted to the gate of the first drive transistor T3-1. The first drive transistor T3-1 can generate a drive signal based on the received data signal and the drive power signal provided by the drive power terminal Vdd, and transmit the drive signal to the first electrode of the first switch transistor T1-1. When the switch control terminal Con1 provides a switch control signal with an effective potential, the first switch transistor T1-1 can be turned on. The drive signal transmitted to the first electrode of the first switch transistor T1-1 can be further transmitted to the second electrode of the first switch transistor T1-1 through the turned-on first switch transistor T1-1, that is, transmitted to the light-emitting element 031, thereby driving the light-emitting element 031 to emit light.

[0143] It should be noted that, to achieve independent control, the different switch circuits 0212 included in the pixel circuits 021 of the corresponding first sub-pixel P1 and the second sub-pixel P2 have the same type of switch transistors (e.g., both are P-type transistors as shown in FIG19 ), and the different switch circuits 0212 (i.e., different first switch transistors T1-1) can be coupled to different switch control terminals Con1. To distinguish, FIG19 identifies the switch control terminal Con1 to which the switch circuit 0212 of the first sub-pixel P1 is coupled as Con1-1, and the switch control terminal Con1 to which the switch circuit 0212 of the second sub-pixel P2 is coupled as Con1-2. Alternatively, when the different switch circuits 0212 included in the pixel circuits 021 of the corresponding first sub-pixel P1 and the second sub-pixel P2 have different types of switch transistors (e.g., one P-type transistor and one N-type transistor as shown in FIG20 ), the different switch circuits 0212 (i.e., different first switch transistors T1-1) can be coupled to the same switch control terminal Con1. In addition, in the pixel circuits shown in FIG. 19 and FIG. 20 , the first data writing transistor T2 - 1 and the first driving transistor T3 - 1 are both P-type transistors.

[0144] It should also be noted that for the structures shown in Figures 19 and 20, the switch control terminal Con1 can be a signal terminal with the same function as the gate signal terminal Gate01 coupled to the first data write transistor T2-1, and can also be called a gate signal terminal. Figure 19 also labels the switch control terminals Con1-1 and Con1-2 coupled to different first switch transistors T1-1 as Gate02 and Gate03, respectively, and Figure 20 also labels the switch control terminal Con1 coupled to different first switch transistors T1-1 as Gate02.

[0145] As another optional implementation method, it can be seen from the pixel circuit block diagram shown in reference Figure 21 that in the one-to-one corresponding first sub-pixel P1 and the second sub-pixel P2, the switching circuit 0212 of at least one sub-pixel can also be coupled to the driving power supply terminal Vdd and the driving circuit 0211 respectively, and can also be used to control the on and off of the driving power supply terminal Vdd and the driving circuit 0211 based on the switching control signal.

[0146] For example, the switch circuit 0212 can control the driving power supply terminal Vdd and the driving circuit 0211 to be connected when the potential of the switch control signal is a valid potential; and the switch circuit 0212 can control the driving power supply terminal Vdd and the driving circuit 0211 to be disconnected when the potential of the switch control signal is an invalid potential.

[0147] Based on FIG21 , it can be seen from the pixel circuit diagrams shown in FIG22 to FIG24 that, for the structure shown in FIG21 , the switch circuit 0212 of the at least one sub-pixel may further include: a second switch transistor T1-2.

[0148] The gate of the second switch transistor T1-2 can be coupled to the switch control terminal Con1, the first electrode of the second switch transistor T1-2 can be coupled to the driving power supply terminal Vdd, and the second electrode of the second switch transistor T1-2 can be coupled to the driving circuit 0211.

[0149] Furthermore, the driving circuit 0211 of each sub-pixel may include: a second data writing transistor T2-2, a second driving transistor T3-2, a compensation transistor T4, and a second storage capacitor C1-2.

[0150] In which, the gate of the second data write transistor T2-2 and the gate of the compensation transistor T4 can both be coupled to the gate signal terminal Gate01, the first electrode of the second data write transistor T2-2 can be coupled to the data signal terminal Vdata, and the second electrode of the second data write transistor T2-2 can be coupled to the first electrode of the second drive transistor T3-2. The first electrode of the compensation transistor T4 can be coupled to the second electrode of the second drive transistor T3-2, and the second electrode of the compensation transistor T4 can be coupled to the gate of the second drive transistor T3-2. The first electrode of the second drive transistor T3-2 can be coupled to the second electrode of the second switch transistor T1-2. The first end of the second storage capacitor C1-2 can be coupled to the gate of the second drive transistor T3-2, and the second end of the second storage capacitor C1-2 can be coupled to the drive power supply terminal Vdd.

[0151] When the gate signal terminal Gate01 provides a gate drive signal with an effective potential, the second data write transistor T2-2 and the compensation transistor T4 can both be turned on. The data signal provided by the data signal terminal Vdata can be written to the first electrode of the second drive transistor T3-2 via the turned-on second data write transistor T2-2. Upon turning on the second drive transistor T3-2, the data signal can be transmitted to the gate of the second drive transistor T3-2 via the turned-on second drive transistor T3-2 and the compensation transistor T4. The second storage capacitor C1-2 can store the potential of the gate of the second drive transistor T3-2. When the switch control terminal Con1 provides a switch control signal with an effective potential, the first switch transistor T1-1 and the second switch transistor T1-2 can both be turned on. The drive power signal provided by the drive power terminal Vdd can be transmitted to the first electrode of the second drive transistor T3-2. The second drive transistor T3-2 can generate a drive signal based on the received data signal and the drive power signal provided by the drive power terminal Vdd, and further transmit the drive signal to the light-emitting element O31 via the turned-on first switch transistor T1-1, thereby driving the light-emitting element O31 to emit light.

[0152] It should be noted that the difference between Figures 22 to 24 is that in Figures 22 and 24, each transistor included in the pixel circuit is a P-type transistor; in Figure 23, the pixel circuit includes a P-type transistor and an N-type transistor, which can be applied to low-temperature polycrystalline silicon oxide (LTPO) display scenarios. In addition, in Figures 22 and 23, only the switch circuit 0212 in the first sub-pixel P1 includes a second switch transistor T1-2 in addition to the first switch transistor T1-1. In Figure 24, only the first switch transistor T1-1 is included. In Figure 24, the switch circuit 0212 in both the first sub-pixel P1 and the second sub-pixel P2 includes a first switch transistor T1-1 and a second switch transistor T1-2.

[0153] Optionally, referring to Figures 22 to 24 , it can be seen that the pixel circuit of this alternative implementation may further include a first reset transistor T5 and a sixth reset transistor T6. The first subpixel P1 and the second subpixel P2 may share the first reset transistor T5, and each may include a different sixth reset transistor T6. The gates of the first reset transistor T5 and the sixth reset transistor T6 may both be coupled to the reset signal terminal Re, the first electrode of the first reset transistor T5 may be coupled to the first initial power supply terminal Vinit1, the second electrode of the first reset transistor T5 may be coupled to the gate of the second drive transistor T3-2, the first electrode of the sixth reset transistor T6 may be coupled to the second initial power supply terminal Vinit2, and the second electrode of the sixth reset transistor T6 may be coupled to the anode of the light-emitting element O31. When the reset signal terminal Re provides a reset signal with an effective potential, the first reset transistor T5 and the sixth reset transistor T6 can be turned on, and the first initial power signal provided by the first initial power terminal Vinit1 can be transmitted to the gate of the second driving transistor T3-2 through the turned-on first reset transistor T5 to reset the gate of the second driving transistor T3-2; the second initial power signal provided by the second initial power terminal Vinit2 can be transmitted to the anode of the light-emitting element 031 through the turned-on sixth reset transistor T6 to reset the anode of the light-emitting element 031.

[0154] In addition, for LTPO display products, the pixel circuit may further include a seventh reset transistor T7 and a switch control transistor T8. The gate of the seventh reset transistor T7 may be coupled to the reset signal terminal Re, the first electrode of the seventh reset transistor T7 may be coupled to the third initial power supply terminal Vinit3, and the second electrode of the seventh reset transistor T7 may be coupled to the first electrode of the second drive transistor T3-2. When the reset signal terminal Re provides a reset signal with a valid potential, the seventh reset transistor T7 may be turned on, and the third initial power supply signal provided by the third initial power supply terminal Vinit3 may be transmitted to the first electrode of the second drive transistor T3-2 via the turned-on seventh reset transistor T7, thereby resetting the first electrode of the second drive transistor T3-2. The gate of the switch control transistor T8 may be coupled to the gate signal terminal Gate01, the first electrode of the switch control transistor T8 may be coupled to the first electrode of the first reset transistor T5 and the second electrode of the compensation transistor T4, and the second electrode of the switch control transistor T8 may be coupled to the gate of the second drive transistor T3-2. When the gate signal terminal Gate01 provides a gate drive signal with an effective potential, the switch control transistor T8 can be turned on, so that the first electrode of the first reset transistor T5 and the second electrode of the compensation transistor T4 are both connected to the gate of the second drive transistor T3-2, thereby controlling the potential of the gate of the second drive transistor T3-2.

[0155] Optionally, the seventh reset transistor T7 shown in FIG23 is a P-type transistor, and the switch control transistor T8 is an N-type transistor. To distinguish them, the gate signal terminal Gate01 coupled to the N-type switch control transistor T8 is labeled Gate01_P, and the gate signal terminal Gate01 coupled to the P-type second data writing transistor T2-2 and the compensation transistor T4 is labeled Gate01_N. Furthermore, the first reset transistor T5 and the sixth reset transistor T6 shown in FIG22 to FIG24 are both P-type transistors.

[0156] It should be noted that the above only illustrates the on-state of each transistor. When the gate of each transistor receives a signal with an inactive potential, the transistor can be turned off. Furthermore, for the structures shown in Figures 22 to 24 , the switch control terminal Con1 can also be referred to as the light-emitting control terminal. In the figures, the switch control terminals Con1-1 and Con1-2, to which the first and second switch transistors T1-1 and T1-2 are coupled, are also labeled EM1 and EM2, respectively. Furthermore, the above is merely a schematic illustration of the pixel circuit.

[0157] Optionally, the transistors used in the embodiments of the present disclosure may be field-effect transistors or other devices with similar characteristics. Based on their function in the circuit, the transistors used in the embodiments of the present disclosure are primarily switching transistors. Since the source and drain of the switching transistors used here are symmetrical, their source and drain are interchangeable. In the embodiments of the present disclosure, the source is referred to as the first electrode and the drain is referred to as the second electrode, or alternatively, the drain is referred to as the first electrode and the source is referred to as the second electrode. According to the configuration in the accompanying drawings, the middle end of the transistor is defined as the gate, the signal input end as the source, and the signal output end as the drain. Furthermore, the switching transistors used in the embodiments of the present disclosure may include either a P-type switching transistor or an N-type switching transistor, wherein a P-type switching transistor is turned on when the gate is at a low level and turned off when the gate is at a high level, and an N-type switching transistor is turned on when the gate is at a high level and turned off when the gate is at a low level. Furthermore, the multiple signals in each embodiment of the present disclosure correspond to effective potentials and ineffective potentials. The effective potential and ineffective potential simply represent that the potential of the signal has two state variables and do not represent that the effective potential or ineffective potential has a specific value throughout the text.

[0158] In summary, an embodiment of the present disclosure provides a display panel. The display panel includes a plurality of first sub-pixels and a plurality of second sub-pixels located on a substrate, and the first sub-pixels and the second sub-pixels both include a pixel circuit layer and a light-emitting unit layer stacked in sequence in a direction away from the substrate, and the display panel also includes a pixel defining layer and a light-shielding layer located on one side of the light-emitting unit layer. Because the light-shielding portion of the light-shielding layer overlaps with the pixel defining portion that defines the first sub-pixel, the light emission angle can be adjusted by flexibly lighting the first sub-pixel and the second sub-pixel to achieve switching between anti-peeping and sharing. In addition, because the switch circuits that control the on / off of the switch element and the drive circuit in the first sub-pixel and the second sub-pixel are different, independent control of the light emission of the first sub-pixel and the second sub-pixel can also be achieved, thereby flexibly adjusting the anti-peeping viewing angle and improving anti-peeping flexibility.

[0159] The present disclosure also provides a method for manufacturing a display panel, which can be used to manufacture the display panel described in the above embodiment. As shown in FIG25 , the method includes:

[0160] Step 2501: Provide a substrate.

[0161] 1 , a substrate 01 is provided having a plurality of pixel sub-regions Q1 . Each pixel sub-region Q1 includes a plurality of pixel unit regions Q11 . Each pixel unit region Q11 includes a first pixel unit region Q11 - 1 and a second pixel unit region Q11 - 2 .

[0162] Step 2502: In each pixel partition, a plurality of first sub-pixels and a plurality of second sub-pixels that are in one-to-one correspondence and have different colors are formed in a plurality of pixel unit areas.

[0163] Continuing with Figure 1 , the first subpixel P1 is located in the first pixel unit region Q11-1, and the second subpixel P2 is located in the second pixel unit region Q11-2. Furthermore, referring to Figure 2 , both the first subpixel P1 and the second subpixel P2 may include: a pixel circuit layer 02 and a light-emitting unit layer 03 stacked sequentially in a direction away from the substrate 01. Furthermore, referring to Figure 5 , the pixel circuit layer 02 is used to form the pixel circuit 021, and the light-emitting unit layer 03 is used to form the light-emitting element 031.

[0164] Step 2503: forming a pixel defining layer, an encapsulation layer, and a multi-layer light shielding layer stacked in sequence in a direction away from the substrate on one side of the light emitting unit layer.

[0165] Continuing with FIG2 , the formed pixel defining layer 04 has a plurality of openings 04K and a pixel defining portion 041 surrounding each opening 04K. The light-emitting unit layer 03 of any two adjacent sub-pixels among the plurality of first sub-pixels P1 and the plurality of second sub-pixels P2 is located within the opening 04K and defined by the pixel defining portion 041. The formed light-shielding layer 06 includes a plurality of light-shielding portions 061 spaced apart from each other, and the orthographic projections of the plurality of light-shielding portions 061 on the substrate 01 overlap with the orthographic projections of the pixel defining portion 041 defining the first sub-pixel P1 on the substrate 01.

[0166] 5 , the pixel circuit 021 includes a driving circuit 0211 and a switching circuit 0212 . The pixel circuits 021 in the one-to-one corresponding first sub-pixel P1 and second sub-pixel P2 include different switching circuits 0212 and share the same driving circuit 0211 .

[0167] Among them, the switching circuit 0212 is coupled to the switch control terminal Con1, the driving circuit 0211 and the light-emitting element 031 respectively, and is used to control the on and off of the driving circuit 0211 and the light-emitting element 031 based on the switch control signal provided by the switch control terminal Con1. The driving circuit 0211 is used to generate a driving signal to drive the light-emitting element 031 to emit light.

[0168] As an optional implementation, taking the display panel shown in FIG2 as an example, the process flow of the preparation method is described as follows:

[0169] a. Referring to FIG. 26 , a substrate 01 may be provided. On one side of substrate 01, a buffer layer Buffer, an active layer ACT, a first gate insulating layer GI1, a first gate metal layer Gate1, a second gate insulating layer GI2, a second gate metal layer Gate2, an interlayer dielectric layer ILD, a source / drain metal layer SD, a planarization layer PLN, a light-emitting element 031 (only the anode Anode is shown in FIG. 26 ), and a pixel defining layer 04 may be formed. The pixel defining portion 041 of pixel defining layer 04 defines the anodes Anodes of adjacent sub-pixels. In other words, the above layers may be fabricated sequentially according to the backplane process flow. The formed active layer ACT, first gate insulating layer GI1, first gate metal layer Gate1, second gate insulating layer GI2, second gate metal layer Gate2, interlayer dielectric layer ILD, and source / drain metal layer SD can be divided into pixel circuit layer 02. The source / drain metal layer SD is connected to the active layer ACT through vias that penetrate the interlayer dielectric layer ILD, the second gate insulating layer GI2, and the first gate insulating layer GI1. Optionally, the substrate 01 can be a PI substrate; the active layer ACT can be a P-Si layer.

[0170] b. With reference to FIG. 27 , after step a, a packaging process may be performed to form a packaging layer 05 on the side of the pixel defining layer 04 away from the substrate 01 , which may be a thin film encapsulation TFE.

[0171] c. Referring to Figure 28 , after step b, a first light-shielding layer 06 can be formed on the side of the encapsulation layer 05 away from the substrate 01. This first light-shielding layer 06 can have multiple, spaced-apart light-shielding portions 061. These light-shielding portions 061 at least overlap with the pixel-defining portions 041 that define the first sub-pixel P1, thereby limiting the light emission angle and achieving a privacy protection function. Furthermore, Figure 27 schematically illustrates the light-emitting layer EL.

[0172] d. Referring to FIG29 , after step c, a spacer layer 07 , also called an IJP layer, can be formed on the side of the first light shielding layer 06 away from the substrate 01 by inkjet printing (IJP) process, i.e., IJP thick film production is performed.

[0173] e. With reference to Figure 30 , after step d, a second light-shielding layer 06 can be formed on the surface of the IJP layer away from the substrate 01. This second light-shielding layer 06 can also have multiple spaced-apart light-shielding portions 061. These light-shielding portions 061 overlap at least with the pixel-defining portion 041 that defines the first sub-pixel P1, thereby limiting the light emission angle and achieving a privacy protection function. The provision of multiple light-shielding layers 06 can further restrict the light emission angle and reliably control the privacy protection viewing angle. Optionally, both the first and second light-shielding layers 06 can be black BM or black PDL, or in some embodiments, a filter portion CF located between adjacent light-shielding portions 061 can be included, i.e., a COE structure.

[0174] Finally, after step e, a first coating layer 08, also called an OC1 layer, can be formed on the side of the second light-shielding layer 06 facing away from the substrate 01. This is the process of fabricating the OC1 layer. In some embodiments, the IJP layer can also be called an OC layer, meaning it can be made of the same material as the OC layer.

[0175] As another optional implementation, taking the display panel shown in FIG16 as an example, the process flow of the preparation method is described as follows:

[0176] f. Referring to Figure 31 , a substrate 01 can be provided. On one side of the substrate 01, a buffer layer Buffer, an active layer ACT, a gate insulating layer GI, a gate metal layer Gate, an interlayer dielectric layer ILD, a source / drain metal layer SD, a planarization layer PLN, a light-emitting element 031 (only the anode Anode is shown in Figure 31 ), and a pixel definition layer 04 can be sequentially stacked. The pixel definition layer 04 includes a pixel defining portion 041 that defines the anodes Anodes of adjacent sub-pixels. In other words, the above layers can be fabricated sequentially according to the backplane process flow. The formed active layer ACT, gate insulating layer GI, gate metal layer Gate, interlayer dielectric layer ILD, and source / drain metal layer SD can be divided into a pixel circuit layer 02. The source / drain metal layer SD is connected to the active layer ACT via vias that penetrate the interlayer dielectric layer ILD, the second gate insulating layer GI2, and the first gate insulating layer GI1. Optionally, the substrate 01 can be a PI flexible substrate; the active layer ACT can comprise a P-Si layer.

[0177] By comparing Figures 26 and 31 , it can be seen that in some embodiments, the pixel circuit layer 02 formed may include two gate metal layers and, accordingly, two gate insulating layers; or, in some embodiments, the pixel circuit layer 02 formed may include one gate metal layer and, accordingly, one gate insulating layer. The presently disclosed embodiments are not limited to this. In addition, it should be noted that in the display panels shown in Figures 26 and 31 , the pixel circuit layer 02 formed is a bottom-gate structure, while in some other embodiments, it may also be a top-gate structure, that is, the gate metal layer may be located on the side of the source / drain metal layer SD away from the substrate 01.

[0178] g. In conjunction with FIG. 32 , after step f, a packaging process may be performed to form a packaging layer 05 on the side of the pixel defining layer 04 away from the substrate 01 , which may be a thin film encapsulation TFE.

[0179] h. In conjunction with Figure 33, after step g, an FMLOC can be fabricated on the side of the encapsulation layer 05 away from the substrate 01, i.e., a plurality of touch electrodes 091 are formed, and each touch electrode 091 formed includes a first electrode layer 0911, an interlayer defining layer 0912, and a second electrode layer 0913 stacked in sequence in a direction away from the substrate 01. Furthermore, the orthographic projection of each touch electrode 091 on the substrate 01 overlaps with the orthographic projection of the portion of the pixel defining layer 04 located between two adjacent pixel unit areas Q11 on the substrate 01. That is, as shown in Figure 33, the touch traces can be arranged on the side of the pixel defining layer PDL surrounding the pixel. Furthermore, a second coating layer 10, also referred to as an OC2 layer, can be formed on the side of the FMLOC away from the substrate 01.

[0180] i. Referring to Figure 34 , after step h, a first light-shielding layer 06 can be formed on the surface of the OC2 layer away from the substrate 01. This first light-shielding layer 06 can have multiple, spaced-apart light-shielding portions 061. These light-shielding portions 061 at least overlap with the pixel-defining portions 041 that define the first sub-pixel P1, thereby limiting the light emission angle and achieving a privacy protection function. In other words, the first light-shielding layer 06 is fabricated.

[0181] j. Referring to FIG35 , after step i, a spacer layer 07 , also called an IJP layer, can be formed on the side of the first light shielding layer 06 away from the substrate 01 by inkjet printing (IJP) process, i.e., IJP thick film production.

[0182] k. Referring to Figure 36 , after step j, a second light-shielding layer 06 can be formed on the surface of the IJP layer facing away from the substrate 01. This second light-shielding layer 06 can also have multiple, spaced-apart light-shielding portions 061. These light-shielding portions 061 overlap at least with the pixel-defining portions 041 that define the first sub-pixel P1, thereby limiting the light emission angle and achieving a privacy protection function. The provision of multiple light-shielding layers 06 can further restrict the light emission angle and reliably control the privacy protection viewing angle. Optionally, both the first and second light-shielding layers 06 can be black BM or black PDL, or, in some embodiments, further include a filter portion CF located between adjacent light-shielding portions 061.

[0183] 1. Referring to FIG37 , after step k, a first coating layer 08, also called an OC1 layer, can be formed on the side of the second light shielding layer 06 away from the substrate 01. This OC1 layer can serve as the outermost flat layer.

[0184] It should be noted that the processes used in the above-mentioned preparation process may include a deposition process and a patterning process, and the patterning process includes sequentially performing coating, exposure, development and etching.

[0185] In summary, the embodiments of the present disclosure provide a method for preparing a display panel. The display panel formed by the method includes a plurality of first sub-pixels and a plurality of second sub-pixels located on a substrate, and the first sub-pixels and the second sub-pixels both include a pixel circuit layer and a light-emitting unit layer stacked in sequence in a direction away from the substrate, and the display panel also includes a pixel defining layer and a light-shielding layer located on one side of the light-emitting unit layer. Because the light-shielding portion of the light-shielding layer overlaps with the pixel defining portion that defines the first sub-pixel, the light emission angle can be adjusted by flexibly lighting the first sub-pixel and the second sub-pixel to achieve switching between anti-peeping and sharing. In addition, because the switch circuits that control the on / off of the switch element and the drive circuit in the first sub-pixel and the second sub-pixel are different, independent control of the light emission of the first sub-pixel and the second sub-pixel can also be achieved, thereby flexibly adjusting the anti-peeping viewing angle and improving anti-peeping flexibility.

[0186] The present disclosure also provides a method for driving a display panel, which can be applied to the display panel described in the above embodiment. As shown in FIG38 , the method includes:

[0187] Step 3801: In response to an anti-peeping instruction, a switch control signal with an effective potential is provided to a switch control terminal coupled to a pixel circuit in a first sub-pixel, and a switch circuit included in the pixel circuit in the first sub-pixel controls the included driving circuit and the light-emitting element to be turned on based on the switch control signal with an effective potential.

[0188] Step 3802: In response to an anti-peeping instruction, a switch control signal of an invalid potential is provided to a switch control terminal coupled to a pixel circuit in a second sub-pixel corresponding to the first sub-pixel; the switch circuit included in the pixel circuit in the second sub-pixel controls the included drive circuit to disconnect from the light-emitting element based on the switch control signal of the invalid potential; or, a switch control signal in the form of a pulse is provided to the switch control terminal coupled to the pixel circuit in the second sub-pixel; the switch circuit included in the pixel circuit in the second sub-pixel controls the included drive circuit and the light-emitting element to be periodically turned on and off based on the switch control signal in the form of a pulse.

[0189] Step 3803: In response to the sharing instruction, a switch control signal with an effective potential is provided to the switch control terminal coupled to the pixel circuit in the second sub-pixel, and the switch circuit included in the pixel circuit in the second sub-pixel controls the included driving circuit and the light-emitting element to be turned on based on the switch control signal with an effective potential.

[0190] Step 3804: In response to the sharing instruction, a switch control signal of an effective potential is provided to the switch control terminal coupled to the pixel circuit in the first sub-pixel, and the switch circuit included in the pixel circuit in the first sub-pixel controls the included driving circuit and the light-emitting element to be turned on based on the switch control signal of the effective potential; or, a switch control signal in the form of a pulse is provided to the switch control terminal coupled to the pixel circuit in the first sub-pixel, and the switch circuit included in the pixel circuit in the first sub-pixel controls the included driving circuit and the light-emitting element to be periodically turned on and off based on the switch control signal in the form of a pulse.

[0191] When the driving circuit is connected to the light-emitting element, the driving signal generated by the driving circuit is transmitted to the light-emitting element to drive the light-emitting element to emit light.

[0192] Optionally, taking the pixel circuit shown in FIG19 , that is, the transistors in the pixel circuit are all P-type transistors, the effective potential is a low potential, and the ineffective potential is a high potential as an example, the driving principle is described as follows:

[0193] Among them, the anti-peeping instruction can be used to indicate entering the anti-peeping mode, and the sharing instruction can indicate entering the sharing mode. Combined with the signal timing diagram shown in Figure 39, it can be seen that: in the sharing mode, a low-voltage switch control signal can be provided to the switch control terminal Con1-1 (that is, Gate02) coupled to the first sub-pixel P1 (that is, the anti-peeping sub-pixel) and the switch control terminal Con1-2 (that is, Gate03) coupled to the second sub-pixel P2 (that is, the normal sub-pixel), so that the first switch transistor T1-1 included in the first sub-pixel P1 and the first switch transistor T1-1 included in the second sub-pixel P2 are both turned on. Furthermore, the driving circuit 0211 shared by the first sub-pixel P1 and the second sub-pixel P2 and the light-emitting element 031 included therein can both be turned on. Accordingly, the driving signal generated by the driving circuit 0211 can be transmitted to the light-emitting element 031 included in the first sub-pixel P1 and the second sub-pixel P2, so that the first sub-pixel P1 and the second sub-pixel P2 both emit light. That is, in the sharing mode, the first subpixel P1 and the second subpixel P2 may be lit.

[0194] In anti-peeping mode 1, a low-voltage switching control signal can be provided to the switch control terminal Con1-1 (i.e., Gate02) coupled to the first sub-pixel P1 (i.e., the anti-peeping sub-pixel), and a high-voltage switching control signal can be provided to the switch control terminal Con1-2 (i.e., Gate03) coupled to the second sub-pixel P2 (i.e., the normal sub-pixel). This turns on the first switching transistor T1-1 included in the first sub-pixel P1 and turns off the first switching transistor T1-1 included in the second sub-pixel P2. Furthermore, the drive circuit 0211 shared by the first and second sub-pixels P1 and P2 can be electrically conductive only to the light-emitting element 031 included in the first sub-pixel P1, and not to the light-emitting element 031 included in the second sub-pixel P2. Accordingly, the drive signal generated by the drive circuit 0211 can be transmitted to the light-emitting element 031 included in the first sub-pixel P1, causing the first sub-pixel P1 to emit light, but not to the light-emitting element 031 included in the second sub-pixel P2. That is, in an anti-peeping mode, only the first sub-pixel P1 of the first sub-pixel P1 and the second sub-pixel P2 can be lit. Since a light-shielding layer 06 for blocking light is provided on one side of the first sub-pixel P1, a light-shielding effect can be achieved to play an anti-peeping role.

[0195] Of course, referring to FIG. 39 , it can also be seen that in another anti-peeping mode 2-1 and anti-peeping mode 2-2, a low-voltage switching control signal can be provided to the switch control terminal Con1-1 (i.e., Gate02) coupled to the first sub-pixel P1 (i.e., the anti-peeping sub-pixel), and a pulse-type switching control signal (i.e., the provided switching control signal can be a pulse signal including high and low voltages) can be provided to the switch control terminal Con1-2 (i.e., Gate03) coupled to the second sub-pixel P2 (i.e., the normal sub-pixel). This causes the first switching transistor T1-1 included in the first sub-pixel P1 to turn on, while the first switching transistor T1-1 included in the second sub-pixel P2 to be periodically turned on and off (which can also be considered intermittently turned on and off), i.e., turned on when the voltage is high and turned off when the voltage is low. Furthermore, the driving circuit 0211 shared by the first and second sub-pixels P1 and P2 can be turned on and off with the light-emitting element 031 included in the first sub-pixel P1, and periodically turned on and off with the light-emitting element 031 included in the second sub-pixel P2. Correspondingly, the driving signal generated by the driving circuit 0211 can be transmitted to the light-emitting element 031 included in the first sub-pixel P1, so that the first sub-pixel P1 emits light, and is periodically transmitted to the light-emitting element 031 included in the second sub-pixel P2. That is, in an anti-peeping mode, the first sub-pixel P1 of the first sub-pixel P1 and the second sub-pixel P2 can be illuminated, and the second sub-pixel P2 can be illuminated periodically, that is, the second sub-pixel P2 is illuminated by a pulse drive method. On this basis, dimming can be performed by adjusting the duty cycle of the switch control signal in the form of a pulse, that is, controlling the anti-peeping viewing angle, further improving the anti-peeping flexibility. Specifically, the longer the duty cycle, the longer the light-emitting time of the second sub-pixel P2, and the larger the viewing angle that can be seen. The difference between anti-peeping mode 2-1 and anti-peeping mode 2-2 is that the duty cycle of the switch control signal is different. The duty cycle can refer to the duration of the low potential (i.e., the effective potential) between the low potential and the high potential.

[0196] Optionally, FIG40 also schematically shows a viewing angle curve diagram for the sharing mode and three anti-peeping modes shown in FIG39 . The horizontal axis refers to the viewing angle, and the vertical axis refers to the normalized brightness. Referring to FIG40 , it can be seen that in anti-peeping mode 1, since the second sub-pixel P2 will not be illuminated, the anti-peeping viewing angle can be controlled to the minimum, achieving a better anti-peeping effect. In anti-peeping modes 2-1 and 2-2, since the second sub-pixel P2 will be periodically illuminated, the anti-peeping viewing angle is relatively large, and the anti-peeping viewing angle of the anti-peeping mode 2-1 with a longer duty cycle is relatively large compared to the anti-peeping mode 2-2 with a shorter duty cycle.

[0197] Based on the above-described embodiments, it can be seen that in the shared mode and the anti-peeping mode, the first sub-pixel P1 is illuminated for a longer period of time than the second sub-pixel P2, that is, the usage time of the first sub-pixel P1 and the second sub-pixel P2 is different, which will result in inconsistent service lives of the two sub-pixels. To this end, referring to another signal timing diagram shown in Figure 41, it can be seen that in the disclosed embodiments, in the shared mode, the first sub-pixel P1 can also be illuminated using a pulse drive method, that is, a pulse-form switch control signal is provided to the switch control terminal Con1-1 coupled to the first sub-pixel P1, so that the first sub-pixel P1 is periodically illuminated. In this way, the usage time of the first sub-pixel P1 and the second sub-pixel P2 can be balanced, so that the service lives of the first sub-pixel P1 and the second sub-pixel P2 are as consistent as possible, that is, they match each other, ensuring a good product yield.

[0198] Alternatively, in some embodiments, as can be seen with reference to FIG15 , the area of ​​the first sub-pixel P1 can be set to be larger than the area of ​​the second sub-pixel P2, so that the light-emitting area of ​​the first sub-pixel P1 is larger than the light-emitting area of ​​the second sub-pixel P2. On this basis, with reference to another signal timing diagram shown in FIG42 , the second sub-pixel P2 can be illuminated using a pulse driving method, that is, a pulsed switching control signal is provided to the switching control terminal Con1-2 coupled to the second sub-pixel P2, so that the second sub-pixel P2 is periodically illuminated.

[0199] Alternatively, taking the pixel circuit shown in FIG20 , where the transistors in the pixel circuit include both N-type and P-type transistors, as an example, referring to the signal timing diagram shown in FIG43 , it can be seen that, in the sharing mode, a high-voltage switch control signal can be provided to the same switch control terminal Con1 (i.e., Gate02) coupled to the first sub-pixel P1 and the second sub-pixel P2, so that the P-type first switch transistor T1-1 included in the first sub-pixel P1 is turned off, while the N-type first switch transistor T1-1 included in the second sub-pixel P2 is turned on. Furthermore, the drive circuit 0211 shared by the first sub-pixel P1 and the second sub-pixel P2 can be turned on by the light-emitting element 031 included in the second sub-pixel P2, and can be decoupled from the light-emitting element 031 included in the first sub-pixel P1. Accordingly, the drive signal generated by the drive circuit 0211 can be transmitted to the light-emitting element 031 included in the second sub-pixel P2, causing the second sub-pixel P2 to emit light, but will not be transmitted to the light-emitting element 031 included in the first sub-pixel P1. That is, in the sharing mode, only the second sub-pixel P2 can be illuminated. Because in this embodiment, in the sharing mode, only the second sub-pixel P2 is illuminated and the first sub-pixel P1 is not illuminated, the sharing effect in the sharing mode can be ensured by controlling the provided switch control signal to a high voltage for a longer period of time, that is, illuminating the second sub-pixel P2 for a longer period of time.

[0200] In anti-peep mode 1, a low-voltage switch control signal can be provided to the same switch control terminal Con1, turning on the P-type first switch transistor T1-1 included in the first sub-pixel P1 and turning off the N-type first switch transistor T1-1 included in the second sub-pixel P2. Furthermore, the drive circuit 0211 shared by the first and second sub-pixels P1 and P2 can be turned on and off from the light-emitting element 031 included in the first sub-pixel P1 and disconnected from the light-emitting element 031 included in the second sub-pixel P2. Accordingly, the drive signal generated by the drive circuit 0211 can be transmitted to the light-emitting element 031 included in the first sub-pixel P1, causing the first sub-pixel P1 to emit light, while not being transmitted to the light-emitting element 031 included in the second sub-pixel P2. In other words, in anti-peep mode 1, only the first sub-pixel P1 of the first and second sub-pixels P1 and P2 can be illuminated. In anti-peeping mode 2-1, a pulsed switching control signal can be provided to the same switch control terminal Con1, causing the P-type first switching transistor T1-1 included in the first sub-pixel P1 and the N-type first switching transistor T1-1 included in the second sub-pixel P2 to be periodically turned on. Specifically, when the potential of the switching control signal of the pulse signal is high, the N-type first switching transistor T1-1 included in the second sub-pixel P2 is turned on; when the potential of the switching control signal of the pulse signal is low, the P-type first switching transistor T1-1 included in the first sub-pixel P1 is turned on. Furthermore, the driving circuit 0211 shared by the first and second sub-pixels P1 and P2 and the light-emitting elements 031 included in the first and second sub-pixels P1 and P2 can be periodically turned on. Accordingly, when the driving circuit 0211 and the light-emitting element 031 of the first sub-pixel P1 are electrically connected, the driving signal generated by the driving circuit 0211 can be transmitted to the light-emitting element 031 of the first sub-pixel P1, causing the first sub-pixel P1 to emit light. When the driving circuit 0211 and the light-emitting element 031 of the second sub-pixel P2 are electrically connected, the driving signal can be transmitted to the light-emitting element 031 of the second sub-pixel P2, causing the second sub-pixel P2 to emit light. In other words, in the privacy protection mode 2-1, the first sub-pixel P1 and the second sub-pixel P2 can be periodically illuminated.

[0201] Optionally, taking the pixel circuit shown in FIG22 , that is, the transistors in the pixel circuit are all P-type transistors, the effective potential is a low potential, and the ineffective potential is a high potential as an example, the driving principle is described as follows:

[0202] As can be seen from the signal timing diagram shown in FIG44 , in shared mode, a low-voltage switch control signal can be provided to the switch control terminal Con1-1 (i.e., EM1) coupled to the first subpixel P1, and a low-voltage switch control signal can also be provided to the switch control terminal Con1-2 (i.e., EM2) coupled to the second subpixel P2, thereby turning on both the first switch transistor T1-1 and the second switch transistor T1-2 included in the first subpixel P1, and also turning on the first switch transistor T1-1 included in the second subpixel P2. Furthermore, a path can be formed between the drive power supply terminal Vdd and the pull-down power supply terminal Vss coupled to the light-emitting element O31 included in the first subpixel P1 and the second subpixel P2. The drive signal generated by the drive circuit 0211 shared by the first and second subpixels P1 and P2 can be transmitted to the light-emitting element O31 included in the first and second subpixels P1 and P2, causing both the first and second subpixels P1 and P2 to emit light. That is, in shared mode, the first and second subpixels P1 and P2 can be illuminated simultaneously.

[0203] In anti-peeping mode, a low-voltage switch control signal can be provided to the switch control terminal Con1-1 (i.e., EM1) coupled to the first subpixel P1, and a high-voltage switch control signal can be provided to the switch control terminal Con1-2 (i.e., EM2) coupled to the second subpixel P2, so that the first switching transistor T1-1 and the second switching transistor T1-2 included in the first subpixel P1 are both turned on, while the first switching transistor T1-1 included in the second subpixel P2 is turned off. Furthermore, a path can be formed between the driving power supply terminal Vdd and the pull-down power supply terminal Vss coupled to the light-emitting element 031 included in the first subpixel P1. The driving signal generated by the driving circuit 0211 shared by the first and second subpixels P1 and P2 can be transmitted to the light-emitting element 031 included in the first subpixel P1, causing the first subpixel P1 to emit light, while the driving signal is not transmitted to the light-emitting element 031 included in the second subpixel P2. In other words, in anti-peeping mode, only the first subpixel P1 of the first and second subpixels P1 and P2 can be illuminated. The stage of lighting up the first sub-pixel P1 and / or the second sub-pixel P2 may be referred to as a light emitting stage t0 .

[0204] In addition, FIG44 also shows the reset signal provided by the reset signal terminal Re and the gate drive signal provided by the gate signal terminal Gate01. During the reset phase t2, the potential of the provided reset signal can be low, turning on both the first reset transistor T5 and the second reset transistor T6. This allows the first initial power signal provided by the first initial power terminal Vinit1 to be transmitted to the gate of the second driver transistor T3-2, resetting the gate of the second driver transistor T3-2. Furthermore, the second initial power signal provided by the second initial power terminal Vinit2 can be transmitted to the anode of the light-emitting element 031, resetting the anode of the light-emitting element 031. During the data writing phase t1, the potential of the provided gate drive signal can be low, turning on both the second data writing transistor T2-2 and the compensation transistor T4. This allows the data signal provided by the data signal terminal Vdata to be transmitted to the gate of the second driver transistor T3-2. Subsequently, during the light-emitting phase t0 described in the above embodiment, the second driver transistor T3-2 can reliably generate a drive signal to drive the light-emitting element 031 to emit light based on the gate potential and the drive power signal provided by the drive power terminal Vdd.

[0205] Optionally, taking the pixel circuit shown in FIG23 , that is, the transistors in the pixel circuit include P-type transistors and N-type transistors as an example, the driving principle is described as follows:

[0206] As can be seen from the signal timing diagram shown in FIG45 , in the light-emitting phase t0, the switch control signal provided to the switch control terminal Con1 (including EM1 and EM2) is the same as the signal shown in FIG44 , thereby achieving simultaneous lighting of the first subpixel P1 and the second subpixel P2 in the shared mode, and lighting only the first subpixel P1 of the first subpixel P1 and the second subpixel P2 in the anti-peeping mode. In the reset phase t2, the reset signal provided to the reset signal terminal Re is also the same as the signal shown in FIG44 , thereby similarly resetting the gate of the second driver transistor T3-2 and the anode of the light-emitting element O31, and turning on the third reset transistor T7 included therein, so that the third initial power signal provided by the third initial power terminal Vinit3 is transmitted to the first electrode of the second driver transistor T3-2, thereby resetting the first electrode of the second driver transistor T3-2. The difference is that, because it includes N-type transistors in addition to P-type transistors, during the data writing phase t1, referring to FIG45 , a low-potential gate drive signal can be provided to the gate signal terminal Gate01_P coupled to the P-type second driver transistor T3-2 and the compensation transistor T4, and a high-potential gate drive signal can be provided to the gate signal terminal Gate01_N coupled to the N-type switch control transistor T8, so that the second driver transistor T3-2, the compensation transistor T4, and the switch control transistor T8 are all turned on, thereby allowing the data signal provided by the data signal terminal Vdata to be reliably transmitted to the gate of the second driver transistor T3-2. Thereafter, during the light-emitting phase t0, the second driver transistor T3-2 can reliably generate a drive signal to drive the light-emitting element 031 to emit light based on the gate potential and the drive power signal provided by the drive power supply terminal Vdd.

[0207] Optionally, taking the pixel circuit shown in FIG24 as an example, the driving principle is described as follows:

[0208] As can be seen from the signal timing diagram shown in FIG46 , during the light-emitting phase t0, the switch control signal provided to the switch control terminal Con1 (including EM1 and EM2) can be the same as the signal shown in FIG44 . This enables, in the shared mode, both the first switch transistor T1-1 and the second switch transistor T1-2 included in the first subpixel P1 to be turned on, and the first switch transistor T1-1 and the second switch transistor T1-2 included in the second subpixel P2 to be turned on. Furthermore, a path is formed between the drive power supply terminal Vdd and the pull-down power supply terminal Vss coupled to the light-emitting element O31 included in the first subpixel P1 and the second subpixel P2. This allows the drive signal generated by the drive circuit 0211 shared by the first and second subpixels P1 and P2 to be transmitted to the light-emitting element O31 included in the first and second subpixels P1 and P2, causing both the first and second subpixels P1 and P2 to emit light. That is, in the shared mode, the first and second subpixels P1 and P2 can be illuminated simultaneously. Alternatively, in some embodiments, in the sharing mode, a low-voltage switch control signal may be provided only to the switch control terminal Con1-2 (i.e., EM2) coupled to the second sub-pixel P2, and a high-voltage switch control signal may be provided to the switch control terminal Con1-1 (i.e., EM1) coupled to the first sub-pixel P1, so that the first switch transistor T1-1 and the second switch transistor T1-2 included in the second sub-pixel P2 are both turned on, while the first switch transistor T1-1 and the second switch transistor T1-2 included in the first sub-pixel P1 are both turned off. Consequently, a path is formed only between the driving power supply terminal Vdd and the pull-down power supply terminal Vss coupled to the light-emitting element 031 included in the second sub-pixel P2. The driving signal generated by the driving circuit 0211 shared by the first and second sub-pixels P1 and P2 can be transmitted to the light-emitting element 031 included in the second sub-pixel P2, causing the second sub-pixel P2 to emit light, without being transmitted to the light-emitting element 031 included in the first sub-pixel P1. That is, in one sharing mode, only the second subpixel P2 of the first subpixel P1 and the second subpixel P2 can be illuminated. In the figure, the sharing mode in which the first subpixel P1 and the second subpixel P2 are illuminated at the same time is identified as sharing mode 1, and the sharing mode in which only the second subpixel P2 is illuminated is identified as sharing mode 2.

[0209] In anti-peeping mode, the first switching transistor T1-1 and the second switching transistor T1-2 included in the first sub-pixel P1 are both turned on, while the first switching transistor T1-1 and the second switching transistor T1-2 included in the second sub-pixel P2 are both turned off. Consequently, a path is formed between the driving power supply terminal Vdd and only the pull-down power supply terminal Vss coupled to the light-emitting element 031 included in the first sub-pixel P1. The driving signal generated by the driving circuit 0211 shared by the first and second sub-pixels P1, P2, can be transmitted to the light-emitting element 031 included in the first sub-pixel P1, causing the first sub-pixel P1 to emit light, while the signal is not transmitted to the light-emitting element 031 included in the second sub-pixel P2. That is, in anti-peeping mode, only the first sub-pixel P1 of the first and second sub-pixels P1, P2, can be illuminated.

[0210] In addition, it can be seen from the signal timing diagram shown in reference Figure 46 that in the reset stage t2, the reset signal provided to the reset signal terminal Re is also the same as the signal shown in Figure 44, thereby similarly achieving the resetting of the gate of the second driving transistor T3-2 and the anode of the light-emitting element 031; in the data writing stage t1, the gate driving signal provided to the gate signal terminal Gate01 is also the same as the signal shown in Figure 44, thereby similarly achieving the writing of the data signal, so that the second driving transistor T3-2 can reliably generate the driving signal.

[0211] It should be noted that for the pixel circuits shown in Figures 22 to 24, a pulsed method can also be used to drive the sub-pixels to emit light to flexibly control the anti-peeping viewing angle. The above signal timing is only a schematic illustration. In addition, the signal terminals coupled to the above pixel circuits can be coupled to a driver chip to receive the above signals provided by the driver chip.

[0212] In summary, the embodiments of the present disclosure provide a method for driving a display panel. Because this method can flexibly illuminate a one-to-one correspondence between a first sub-pixel and a second sub-pixel in both anti-peeping mode and sharing mode, and because the switching circuits controlling the switching element and the driving circuit in the first and second sub-pixels are different, the method can flexibly illuminate the first and second sub-pixels and adjust the light emission angle to achieve switching between anti-peeping mode and sharing mode. Furthermore, the method can independently control the light emission of the first and second sub-pixels, thereby flexibly adjusting the anti-peeping viewing angle and improving anti-peeping flexibility.

[0213] FIG47 is a schematic diagram of the structure of a display device provided by an embodiment of the present disclosure. As shown in FIG47 , the display device includes: a power supply component J1 and a display panel 00 as described in the above embodiment.

[0214] The power supply component J1 is coupled to the display panel 00 and is used to supply power to the display panel 00 .

[0215] Optionally, the display device may be any product or component having a display function, such as an organic light-emitting diode (OLED) display device or an active-matrix organic light-emitting diode (AMOLED) display device.

[0216] The terms used in the embodiments of the present disclosure are only used to explain the embodiments of the present disclosure and are not intended to limit the present disclosure. Unless otherwise defined, the technical terms or scientific terms used in the embodiments of the present disclosure should have the common meanings understood by people with ordinary skills in the field to which the present disclosure belongs.

[0217] For example, the words "first", "second" or "third" and similar words used in the patent application specification and claims of this disclosure do not indicate any order, quantity or importance, but are only used to distinguish different components.

[0218] Likewise, the words “a” or “an” and the like do not denote a limitation of quantity, but rather denote the presence of at least one.

[0219] Words such as “include” or “comprising” mean that the elements or objects preceding “include” or “comprising” include the elements or objects listed after “include” or “comprising” and their equivalents, and do not exclude other elements or objects.

[0220] "Up," "down," "left," or "right" are only used to indicate relative positional relationships. When the absolute position of the object being described changes, the relative positional relationship may also change accordingly. "Connected" or "coupled" refers to an electrical connection.

[0221] "And / or" indicates that three relationships can exist. For example, A and / or B can represent: A exists alone, A and B exist simultaneously, and B exists alone. The character " / " generally indicates that the related objects are in an "or" relationship.

[0222] Those skilled in the art will clearly understand that, for the convenience and brevity of description, the specific working processes of the circuits and sub-circuits described above can refer to the corresponding processes in the method embodiments and will not be repeated here.

[0223] The above description is merely an optional embodiment of the present disclosure and is not intended to limit the present disclosure. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principles of the present disclosure shall be included in the scope of protection of the present disclosure.

Claims

1. A display panel, comprising: A substrate having a plurality of pixel sub-regions, each pixel sub-region comprising a plurality of pixel unit regions, each pixel unit region comprising a first pixel unit region and a second pixel unit region; A plurality of first sub-pixels and a plurality of second sub-pixels in each pixel sub-area, which correspond to each other one by one and have different colors in the plurality of pixel unit areas, wherein the first sub-pixels are located in the first pixel unit area, and the second sub-pixels are located in the second pixel unit area, and the first sub-pixels and the second sub-pixels each include: a pixel circuit layer and a light-emitting unit layer sequentially stacked in a direction away from the substrate; Furthermore, the display panel further comprises: a pixel defining layer, an encapsulation layer and a multi-layer light shielding layer which are located on one side of the light emitting unit layer and are sequentially stacked in a direction away from the substrate; the pixel defining layer has a plurality of openings and a pixel defining portion surrounding each opening, and the light emitting unit layers of any two adjacent sub-pixels among the plurality of first sub-pixels and the plurality of second sub-pixels are located in the openings and are defined by the pixel defining layer; the light shielding layer comprises a plurality of light shielding portions spaced apart from each other, and the orthographic projections of the plurality of light shielding portions on the substrate overlap with the orthographic projections of the pixel defining portions defining the first sub-pixels on the substrate; And, the pixel circuit layer is used to form a pixel circuit, the light-emitting unit layer is used to form a light-emitting element, the pixel circuit includes: a driving circuit and a switching circuit, and the pixel circuits in the one-to-one corresponding first sub-pixel and the second sub-pixel include different switching circuits and share the same driving circuit; Among them, the switching circuit is coupled to the switch control end, the driving circuit and the light-emitting element respectively, and is used to control the on and off of the driving circuit and the light-emitting element based on the switch control signal provided by the switch control end, and the driving circuit is used to generate a driving signal to drive the light-emitting element to emit light.

2. The display panel according to claim 1, wherein: In the one-to-one corresponding first sub-pixel and the second sub-pixel, the area of ​​the light-emitting element included in the first sub-pixel is smaller than the area of ​​the light-emitting element included in the second sub-pixel.

3. The display panel according to claim 1, wherein: The first pixel unit area includes a plurality of pixel unit sub-areas defined by the pixel defining portion; The light-emitting unit layer includes an anode, a light-emitting layer and a cathode stacked in sequence in a direction away from the substrate; and the anode of the first sub-pixel located in each first pixel unit area includes a cathode located in the plurality of A plurality of anode portions are within the pixel unit sub-region and coupled to each other.

4. The display panel according to claim 3, wherein: The shape of the pixel unit sub-area in the first pixel unit area is different from the shape of the second pixel unit area.

5. The display panel according to any one of claims 1 to 4, wherein: The display panel further includes: A spacer layer located between every two adjacent light-shielding layers in the multi-layer light-shielding layer; A first coating layer located on a side of the multi-layer light-shielding layer away from the substrate; A touch layer and a second coating layer located between the encapsulation layer and the multi-layer light shielding layer and sequentially stacked in a direction away from the substrate; The touch layer includes a plurality of touch electrodes spaced apart from each other, and each touch electrode includes an interlayer defining layer, a first electrode layer, and a second electrode layer stacked in sequence in a direction away from the substrate; Furthermore, an orthographic projection of each touch electrode on the substrate overlaps with an orthographic projection of a portion of the pixel defining layer located between two adjacent pixel unit regions on the substrate.

6. The display panel according to any one of claims 1 to 5, wherein: The display panel comprises: two light shielding layers, and the distance between the two light shielding layers is greater than 5 microns; Furthermore, the light shielding layer includes: a black matrix layer or a black pixel defining layer.

7. The display panel according to any one of claims 1 to 6, wherein: The display panel further comprises: a light filtering portion located between every two adjacent light shielding portions in at least one light shielding layer.

8. The display panel according to any one of claims 1 to 7, wherein: In the one-to-one corresponding first sub-pixel and the second sub-pixel, the driving circuit of each sub-pixel is also coupled to the gate signal terminal, the data signal terminal and the driving power terminal respectively, and is used to generate the driving signal based on the gate driving signal provided by the gate signal terminal, the data signal provided by the data signal terminal and the driving power signal provided by the driving power terminal; The switch circuit of each sub-pixel includes: a first switch transistor; The gate of the first switch transistor is coupled to the switch control terminal, the first electrode of the first switch transistor is coupled to the drive circuit, and the second electrode of the first switch transistor is coupled to the light emitting element.

9. The display panel according to claim 8, wherein: The driving circuit of each sub-pixel includes: a first data writing transistor, a first driving transistor and a first storage capacitor; Among them, the gate of the first data write transistor is coupled to the gate signal terminal, the first electrode of the first data write transistor is coupled to the data signal terminal, the second electrode of the first data write transistor is coupled to the first end of the first storage capacitor; the second end of the first storage capacitor is coupled to the driving power supply terminal; the gate of the first driving transistor is coupled to the first end of the first storage capacitor, the first electrode of the first driving transistor is coupled to the driving power supply terminal, and the second electrode of the first driving transistor is coupled to the first electrode of the first switching transistor.

10. The display panel according to claim 8, wherein: In the one-to-one corresponding first sub-pixel and the second sub-pixel, the switch circuit of at least one sub-pixel is also coupled to the driving power supply terminal and the driving circuit respectively, and is also used to control the on-off of the driving power supply terminal and the driving circuit based on the switch control signal; The switch circuit of at least one sub-pixel further includes: a second switch transistor; The gate of the second switch transistor is coupled to the switch control terminal, the first electrode of the second switch transistor is coupled to the driving power supply terminal, and the second electrode of the second switch transistor is coupled to the driving circuit.

11. The display panel according to claim 10, wherein: The driving circuit of each sub-pixel includes: a second data writing transistor, a second driving transistor, a compensation transistor and a second storage capacitor; Among them, the gate of the second data writing transistor and the gate of the compensation transistor are both coupled to the gate signal terminal, the first electrode of the second data writing transistor is coupled to the data signal terminal, and the second electrode of the second data writing transistor is coupled to the first electrode of the second driving transistor; the first electrode of the compensation transistor is coupled to the second electrode of the second driving transistor, and the second electrode of the compensation transistor is coupled to the gate of the second driving transistor; the first electrode of the second driving transistor is coupled to the second electrode of the second switching transistor; the first end of the second storage capacitor is coupled to the gate of the second driving transistor, and the second end of the second storage capacitor is coupled to the driving power supply terminal.

12. The display panel according to any one of claims 9 to 11, wherein: In different switch circuits included in the pixel circuits in the one-to-one corresponding first sub-pixel and the second sub-pixel, the types of switch transistors are the same, and the different switch circuits are respectively coupled to different switch control terminals; Alternatively, different switch circuits included in the pixel circuits in the one-to-one corresponding first sub-pixel and the second sub-pixel have different types of switch transistors, and the different switch circuits share the same switch control terminal.

13. The display panel according to any one of claims 1 to 12, wherein: The display panel comprises: a plurality of first pixels located in the plurality of pixel sub-regions, each of the first pixels comprises a plurality of sub-pixels of different colors, and each of the sub-pixels comprises a first sub-pixel and a second sub-pixel corresponding to each other; Alternatively, the display panel includes: multiple first pixels and multiple second pixels located in the multiple pixel partitions, each first pixel includes multiple first sub-pixels of different colors, and each second pixel includes multiple second sub-pixels of different colors corresponding one-to-one to the multiple first sub-pixels.

14. A method for preparing a display panel, for preparing the display panel according to any one of claims 1 to 13; the method comprising: Providing a substrate, wherein the provided substrate has a plurality of pixel sub-regions, each pixel sub-region includes a plurality of pixel unit regions, and each pixel unit region includes a first pixel unit region and a second pixel unit region; In each pixel sub-area, a plurality of first sub-pixels and a plurality of second sub-pixels corresponding to each other and having different colors are formed in the plurality of pixel unit areas, and the formed first sub-pixels are located in the first pixel unit area, and the second sub-pixels are located in the second pixel unit area, and the first sub-pixels and the second sub-pixels each include: a pixel circuit layer and a light-emitting unit layer sequentially stacked in a direction away from the substrate, the pixel circuit layer is used to form a pixel circuit, and the light-emitting unit layer is used to form a light-emitting element; A pixel defining layer, an encapsulation layer and a multi-layer light shielding layer are formed on one side of the light emitting unit layer, which are stacked in sequence in a direction away from the substrate, and the formed pixel defining layer has a plurality of openings and a pixel defining portion surrounding each opening, and the light emitting unit layers of any two adjacent sub-pixels among the plurality of first sub-pixels and the plurality of second sub-pixels are located in the openings and defined by the pixel defining portion; the formed light shielding layer includes a plurality of light shielding portions spaced apart from each other, and the orthographic projections of the plurality of light shielding portions on the substrate overlap with the orthographic projections of the pixel defining portion defining the first sub-pixel on the substrate; The pixel circuit formed includes: a driving circuit and a switching circuit, and the pixel circuits in the one-to-one corresponding first sub-pixel and the second sub-pixel include different switching circuits and share the same driving circuit; The switch circuit is respectively coupled to the switch control terminal, the drive circuit and the light emitting element, and is used to control the drive circuit and the light emitting element based on the switch control signal provided by the switch control terminal. The driving circuit is used to generate a driving signal for driving the light emitting element to emit light.

15. A method for driving a display panel, applied to the display panel according to any one of claims 1 to 13; the method comprising: In response to the anti-peeping instruction, a switch control signal of an effective potential is provided to a switch control terminal coupled to a pixel circuit in a first sub-pixel, and a switch circuit included in the pixel circuit in the first sub-pixel controls the included driving circuit and the light-emitting element to be turned on based on the switch control signal of the effective potential; In response to the anti-peeping instruction, a switch control signal of an invalid potential is provided to a switch control terminal coupled to a pixel circuit in a second sub-pixel corresponding to the first sub-pixel; the switch circuit included in the pixel circuit in the second sub-pixel controls the included drive circuit to disconnect from the light-emitting element based on the switch control signal of the invalid potential; or, a switch control signal in the form of a pulse is provided to the switch control terminal coupled to the pixel circuit in the second sub-pixel; the switch circuit included in the pixel circuit in the second sub-pixel controls the included drive circuit to periodically switch on and off with the light-emitting element based on the switch control signal in the form of a pulse; In response to the sharing instruction, a switch control signal of an effective potential is provided to a switch control terminal coupled to the pixel circuit in the second sub-pixel, and the switch circuit included in the pixel circuit in the second sub-pixel controls the included driving circuit and the light-emitting element to be turned on based on the switch control signal of the effective potential; In response to the sharing instruction, a switch control signal of an effective potential is provided to a switch control terminal coupled to the pixel circuit in the first sub-pixel, and the switch circuit included in the pixel circuit in the first sub-pixel controls the included driving circuit and the light-emitting element to be turned on based on the switch control signal of the effective potential; or, a switch control signal in the form of a pulse is provided to the switch control terminal coupled to the pixel circuit in the first sub-pixel, and the switch circuit included in the pixel circuit in the first sub-pixel controls the included driving circuit and the light-emitting element to be turned on and off periodically based on the switch control signal in the form of a pulse; When the driving circuit is connected to the light-emitting element, the driving signal generated by the driving circuit is transmitted to the light-emitting element to drive the light-emitting element to emit light.

16. A display device, comprising: A power supply component, and a display panel as claimed in any one of claims 1 to 13; Wherein, the power supply component is coupled to the display panel and is used to supply power to the display panel.

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