Display panel, manufacturing method therefor and display apparatus

Abstract

Provided are a display panel, a manufacturing method therefor and a display apparatus, belonging to the technical field of display. In the display panel, a side wire is connected to a first surface wire by means of an electrode structure, and further extends to a second surface after successively passing a first surface and a side surface, the electrode structure comprising at least one conductive pattern layer successively stacked in a direction away from the substrate, and at least one passivation layer located on the side of each conductive pattern layer away from the substrate. A first included angle between any passivation layer and a bearing surface of the substrate is smaller than or equal to a second included angle between a conductive pattern close to the substrate and the bearing surface of the substrate, thus avoiding the problem of peeling caused by climbing of film layers due to overlarge included angles caused by manufacturing processes, and ensuring good product yield.

Description

Display panel and manufacturing method thereof, and display device

[0001] This disclosure claims priority to Chinese patent application No. 202310789282.7 filed on June 29, 2023, entitled “Display panel, method for manufacturing the same, and display device,” the entire contents of which are incorporated herein by reference. Technical Field

[0002] The present disclosure relates to the field of display technology, and in particular to a display panel and a manufacturing method thereof, and a display device. Background Art

[0003] Mini light emitting diodes (mini LEDs) have gradually become the mainstream of the market due to their advantages such as self-luminescence, high brightness and small size. They can be used in both direct display and backlight scenarios.

[0004] In related technologies, large-scale display products, including mini LEDs, often include multiple spliced ​​display panels. Considering the impact of the seams on the display, the driver chip is currently placed on the back of the display panel, and the light-emitting element and electrode structure are placed on the front of the display panel. Side traces are arranged on the sides of the display panel, and one end of the side trace is electrically connected to the light-emitting element through the electrode structure. The other end of the side trace is extended through the front and side surfaces to the back to electrically connect to the driver chip, thereby indirectly connecting the driver chip and the light-emitting element, thereby driving the light-emitting element to emit light. Furthermore, the current electrode structure generally includes a buffer layer, a conductive pattern, and a passivation layer stacked in sequence.

[0005] However, due to the influence of the manufacturing process, peeling is prone to occur between adjacent film layers in the current electrode structure, which leads to poor yield of display products.

[0006] Summary of the Invention

[0007] Provided are a display panel, a method for manufacturing the same, and a display device. The technical solution is as follows:

[0008] In one aspect, a display panel is provided, comprising:

[0009] a substrate having a first surface and a second surface opposite to each other, and a plurality of side surfaces connecting the first surface and the second surface, wherein the first surface includes a display area and a peripheral area surrounding the display area;

[0010] a first surface wiring located in a display area of ​​the first surface, an electrode structure located in a peripheral area of ​​the first surface, and a side wiring located on at least one side surface of the plurality of side surfaces;

[0011] One end of the side wiring is electrically connected to the electrode structure, and the other end of the side wiring extends to the second surface through the first surface and the at least one side surface in sequence, and the electrode structure is also electrically connected to the first surface wiring;

[0012] In addition, the electrode structure includes: a buffer layer located on one side of the substrate and stacked in sequence in a direction away from the substrate, at least one conductive pattern, and at least one passivation layer located on the side of each conductive pattern away from the substrate, and the first angle between any one of the at least one passivation layer and the supporting surface of the substrate is less than or equal to the second angle between the conductive pattern close to the substrate in the at least one conductive pattern and the supporting surface of the substrate.

[0013] Optionally, the first angle is equal to the second angle, and the angle is 0; and the electrode structure includes:

[0014] A first conductive pattern, a first passivation layer, and a second passivation layer are sequentially stacked in a direction away from the substrate;

[0015] a through hole penetrating the first passivation layer and the second passivation layer and exposing the first conductive pattern;

[0016] and a protection layer located in the through hole and covering the first conductive pattern.

[0017] Optionally, the first angle is smaller than the second angle, and both angles are greater than 0 and less than 90 degrees; the electrode structure includes:

[0018] A first conductive pattern, a first passivation layer, a second conductive pattern, and a second passivation layer are sequentially stacked in a direction away from the substrate, wherein an orthographic projection of the first conductive pattern on the substrate is located within an orthographic projection of the second conductive pattern on the substrate;

[0019] a through hole penetrating the second passivation layer and exposing the second conductive pattern;

[0020] a protection layer located in the through hole and covering the second conductive pattern;

[0021] a connecting hole penetrating the first passivation layer and exposing the first conductive pattern, wherein the second conductive pattern is connected to the first conductive pattern through the connecting hole, and the connecting hole is farther away from the at least one side surface than the through hole;

[0022] And, a spacer layer located between the first conductive pattern and the first passivation layer, the orthographic projection of the spacer layer on the substrate is located within the orthographic projection of the first passivation layer on the substrate, and covers the side surface of the first conductive pattern in contact with the buffer layer and the top surface away from the buffer layer, and the thickness of the spacer layer is greater than the thickness of any other film layer in the electrode structure.

[0023] Optionally, a third angle between the spacer layer and the supporting surface of the substrate is smaller than the second angle, and the first angle is equal to the third angle;

[0024] Furthermore, the first angles between each passivation layer and the supporting surface of the substrate are equal, and the fourth angle between the second conductive pattern and the supporting surface of the substrate is equal to the first angle.

[0025] Optionally, the thickness of the spacer layer is greater than 3 microns.

[0026] Optionally, the material of the spacer layer includes: resin material.

[0027] Optionally, the electrode structure further includes:

[0028] A third passivation layer is located between the first conductive pattern and the spacer layer, and the via hole further penetrates the third passivation layer to expose the first conductive pattern.

[0029] Optionally, the first surface routing includes: a first routing layer and a second routing layer stacked in sequence in a direction away from the substrate;

[0030] Wherein, the electrode structure includes a first conductive pattern layer and the first wiring layer located in the same layer;

[0031] The electrode structure includes two layers of conductive patterns, namely, a first conductive pattern and a second conductive pattern stacked sequentially. The first conductive pattern and the first routing layer are located in the same layer, and the second conductive pattern and the second routing layer are located in the same layer.

[0032] Optionally, the thickness of the protective layer included in the electrode structure is greater than the thickness of the through hole, and the material of the protective layer includes: metal material.

[0033] Optionally, the material of the protective layer includes: nickel and / or gold.

[0034] Optionally, in the electrode structure, at least one layer of the conductive pattern includes: multiple layers of sub-conductive patterns stacked sequentially in a direction away from the substrate.

[0035] Optionally, in the electrode structure, at least one layer of the conductive pattern comprises: three layers of sub-conductive patterns stacked sequentially in a direction away from the substrate;

[0036] Furthermore, the materials of the three-layer sub-conductive pattern include: metal molybdenum, metal copper and metal molybdenum; or metal molybdenum-niobium, metal copper and metal molybdenum-niobium.

[0037] Optionally, the at least one layer of conductive patterns includes: a conductive pattern in the at least one layer of conductive patterns that is close to a side of the substrate.

[0038] Optionally, in the electrode structure, the thickness of at least one passivation layer is greater than 2000 angstroms and less than or equal to 4000 angstroms.

[0039] Optionally, the at least one passivation layer includes: a passivation layer on a side of the at least one passivation layer away from the substrate.

[0040] In another aspect, a method for manufacturing a display panel is provided, for manufacturing the display panel according to the above aspect; the method comprising:

[0041] Providing a substrate, wherein the substrate has a first surface and a second surface opposite to each other, and a plurality of side surfaces connecting the first surface and the second surface, wherein the first surface includes a display area and a peripheral area surrounding the display area;

[0042] forming a first surface wiring in a display area of ​​the first surface, and forming an electrode structure in a peripheral area of ​​the first surface, wherein the electrode structure is electrically connected to the first surface wiring;

[0043] forming a side trace on at least one side surface among the plurality of side surfaces, electrically connecting one end of the side trace to the electrode structure, and extending the other end of the side trace sequentially through the first surface and the at least one side surface to the second surface;

[0044] Among them, the formed electrode structure includes: a buffer layer located on one side of the substrate and stacked in sequence in a direction away from the substrate, at least one conductive pattern, and at least one passivation layer located on the side of each conductive pattern away from the substrate, and the first angle between any passivation layer in the at least one passivation layer and the supporting surface of the substrate is less than or equal to the second angle between the conductive pattern close to the substrate in the at least one conductive pattern and the supporting surface of the substrate.

[0045] Optionally, the first angle is equal to the second angle and is 0; and forming an electrode structure in a peripheral area of ​​the first surface includes:

[0046] forming a first conductive pattern, a first passivation layer, and a second passivation layer sequentially stacked in a direction away from the substrate on one side of the substrate;

[0047] forming a through hole penetrating the first passivation layer and the second passivation layer and exposing the first conductive pattern;

[0048] And, forming a protection layer in the through hole to cover the first conductive pattern.

[0049] Optionally, the first angle is smaller than the second angle, and both angles are greater than 0 and less than 90 degrees; forming an electrode structure in a peripheral area of ​​the first surface includes:

[0050] forming a first conductive pattern, a first passivation layer, a second conductive pattern, and a second passivation layer stacked in sequence in a direction away from the substrate on one side of the substrate, wherein an orthographic projection of the first conductive pattern on the substrate is located within an orthographic projection of the second conductive pattern on the substrate;

[0051] forming a through hole penetrating the second passivation layer and exposing the second conductive pattern;

[0052] forming a protection layer covering the second conductive pattern in the through hole;

[0053] forming a via hole penetrating the first passivation layer and exposing the first conductive pattern, wherein the via hole is formed away from the at least one side surface relative to the through hole;

[0054] connecting the second conductive pattern to the first conductive pattern through the connecting hole;

[0055] A spacer layer is formed between the first conductive pattern and the first passivation layer, and the orthographic projection of the formed spacer layer on the substrate is located within the orthographic projection of the first passivation layer on the substrate, and covers the side surface of the first conductive pattern in contact with the buffer layer and the top surface away from the buffer layer, and the thickness of the formed spacer layer is greater than the thickness of any other film layer in the electrode structure.

[0056] Optionally, forming a first surface wiring in the display area of ​​the first surface includes: forming a film of a conductive material in a corresponding area, and then forming the first surface wiring in the display area of ​​the first surface using a yellow light process;

[0057] Forming a side wiring on at least one of the plurality of side surfaces comprises: forming a film of conductive material in a corresponding area, and then forming the side wiring on at least one of the plurality of side surfaces using a laser etching process.

[0058] In another aspect, a display device is provided, comprising: a power supply component, and the display panel according to the above aspect;

[0059] The power supply component is coupled to the display panel and is used to supply power to the display panel. BRIEF DESCRIPTION OF THE DRAWINGS

[0060] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0061] FIG1 is a schematic diagram of the front structure of a display panel provided by an embodiment of the present disclosure;

[0062] FIG2 is a schematic cross-sectional view of a display panel based on the structure shown in FIG1 ;

[0063] FIG3 is a schematic cross-sectional view of another display panel based on the structure shown in FIG1 ;

[0064] FIG4 is a film layer structure diagram of an electrode structure in a display panel provided by an embodiment of the present disclosure;

[0065] FIG5 is a film layer structure diagram of an electrode structure in a display panel in the related art;

[0066] FIG6 is a top view of a display panel based on the structure shown in FIG4 ;

[0067] FIG7 is a schematic cross-sectional view of another display panel based on the structure shown in FIG6 ;

[0068] FIG8 is a schematic structural diagram of a pixel in a display panel provided by an embodiment of the present disclosure;

[0069] FIG9 is a schematic diagram of an SEM slice of a display panel provided by an embodiment of the present disclosure;

[0070] FIG10 is a schematic diagram of a process for forming a conductive pattern according to an embodiment of the present disclosure;

[0071] FIG11 is a film layer structure diagram of an electrode structure in another display panel provided by an embodiment of the present disclosure;

[0072] FIG12 is a diagram showing a film structure of an electrode structure in another display panel provided by an embodiment of the present disclosure;

[0073] FIG13 is a film layer structure diagram of a first wiring layer in a display panel provided by an embodiment of the present disclosure;

[0074] FIG14 is a schematic SEM slice diagram of another display panel provided by an embodiment of the present disclosure;

[0075] FIG15 is a schematic SEM slice diagram of another display panel provided by an embodiment of the present disclosure;

[0076] FIG16 is a flow chart of a method for manufacturing a display panel according to an embodiment of the present disclosure;

[0077] FIG17 is a schematic structural diagram of a display device provided in an embodiment of the present disclosure. DETAILED DESCRIPTION

[0078] In order to make the objectives, technical solutions and advantages of the present disclosure more clear, the embodiments of the present disclosure will be further described in detail below with reference to the accompanying drawings.

[0079] FIG1 is a schematic diagram of the structure of a display panel provided by an embodiment of the present disclosure. FIG2 is a cross-sectional view of a display panel in the mm' direction based on FIG1 , and FIG3 is a cross-sectional view of another display panel in the mm' direction based on FIG1 . It can be seen from FIG1 to FIG3 that the display panel described in the embodiment of the present disclosure includes:

[0080] Substrate 01. The substrate 01 has a first surface A and a second surface B that are opposite to each other, and a plurality of side surfaces C connecting the first surface A and the second surface B. The first surface A includes a display area A1 and a peripheral area A2 that is closer to the side surface C than the display area A1. For example, FIG1 shows substrate 01 having four side surfaces C.

[0081] Optionally, the peripheral area A2 may be located around the rectangular display area A1 as shown in FIG1 , surrounding the display area A1; or, in some embodiments, the peripheral area A2 may also partially surround the display area A1, such as the peripheral area A2 may be located on the lower side of the rectangular display area A1 as shown in FIG1 . The embodiments of the present disclosure are not limited to this. In addition, the display area A1 and the peripheral area A2 may both be rectangular as shown in FIG1 ; or, in some embodiments, the display area A1 and the peripheral area A2 may also be circular or elliptical. The embodiments of the present disclosure are not limited to this either. Moreover, as shown in FIG1 , the shape of the peripheral area A2 and the shape outline of the display area A1 may be regular figures; or, in some embodiments, the shape of the peripheral area A2 and the shape of the display area A1 may also be irregular figures. Of course, to ensure the display effect, the area of ​​the display area A1 is generally larger than the area of ​​the peripheral area A2.

[0082] Continuing with FIG. 1 to FIG. 3 , it can be seen that the display panel described in the embodiment of the present disclosure further includes:

[0083] A first surface trace L1 located in a display area A1 of the first surface A, an electrode structure O2 located in a peripheral area A2 of the first surface A, and a side trace L2 located on at least one side surface C among a plurality of side surfaces C. For example, in the display panel shown in FIG1 , the at least one side surface C is two opposing side surfaces among the four side surfaces. One end of the side trace L2 is electrically connected to the electrode structure O2, and the other end of the side trace L2 extends sequentially through the first surface A and the at least one side surface C to the second surface B. The electrode structure O2 is also electrically connected to the first surface trace L1.

[0084] Optionally, referring to Figures 1 to 3 , it can be seen that the display panel described in the embodiments of the present disclosure may further include a plurality of light-emitting elements L01 located in the display area A1 and an external circuit board located on the second surface B. The first surface traces L1 may also be electrically connected to the light-emitting elements L01, and the side traces L2 may also be electrically connected to the external circuit board where they extend to the second surface B. This achieves the purpose of connecting the external circuit board to the light-emitting elements L01, enabling the external circuit board to reliably drive the light-emitting elements L01 to emit light.

[0085] Optionally, in some embodiments, as shown in Figure 2, the portion of the side trace L2 located on the second surface B may have a fan-out line structure, and its free end extending through the first surface A and at least one side surface C to the second surface B may be electrically connected to the gold finger structure of the external circuit board, thereby achieving the purpose of connecting the external circuit board to the light-emitting element L01 through the side trace L2 and the first surface trace L1 in sequence.

[0086] Alternatively, in some other embodiments, as shown in FIG3 , the display panel described in the embodiments of the present disclosure may further include: a second surface trace L3 located on the second surface B. The second surface trace L3 may have a fan-out structure, and one end of the second surface trace L3 having the fan-out structure may be electrically connected to the gold finger structure of the external circuit board, and the other end of the second surface trace L3 may be electrically connected to the side trace L2, thereby achieving the purpose of connecting the external circuit board to the light-emitting element L01 through the second surface trace L3, the side trace L2, and the first surface trace L1 in sequence. That is, in some other embodiments, the free end of the side trace L2 extending through the first surface A and at least one side surface C to the second surface B may be electrically connected to the second surface trace L3 on the second surface B, thereby indirectly electrically connecting to the external circuit board through the second surface trace L3.

[0087] Optionally, the display panel may include multiple first surface traces L1, multiple electrode structures 02, multiple side traces L2, and multiple second surface traces L3. The multiple first surface traces L1 may be connected to the multiple electrode structures 02 in a one-to-one correspondence, that is, each first surface trace L1 is electrically connected to one electrode structure 02, and each first surface trace L1 is electrically connected to a different electrode structure 02. The multiple side traces L2 may be connected to the multiple electrode structures 02 in a one-to-one correspondence, and may be connected to the multiple second surface traces L3 in a one-to-one correspondence. That is, each side trace L2 is electrically connected to one electrode structure 02 and one second surface trace L3, and each side trace L2 is electrically connected to a different electrode structure 02 and a different second surface trace L3.

[0088] Optionally, in conjunction with FIG2 , in the embodiment of the present disclosure, the first surface trace L1 and the electrically connected electrode structure 02 may be an integrated structure; the second surface trace L3 and the electrically connected side trace L2 may be an integrated structure. This simplifies the process and saves costs.

[0089] Optionally, the light-emitting element L01 includes, but is not limited to, a mini LED, an organic light-emitting diode (OLED), and a micro light-emitting diode (micro LED). The size of a mini LED is between an OLED and a micro LED, approximately 100 to 200 microns (μm). The disclosed embodiments are described using a mini LED as the light-emitting element L01.

[0090] It should be noted that, under the premise that the light-emitting element L01 located in the display area A1 in the first surface A emits light, it can be known that the first surface A is the light-emitting surface of the display panel, and correspondingly, the second surface B opposite to the first surface A is the backlight surface of the display panel. Optionally, in the embodiment of the present disclosure, the first surface A serving as the light-emitting surface can also be referred to as the front surface, and the second surface B serving as the backlight surface can be referred to as the back surface. Correspondingly, the first surface trace L1 located on the first surface A can also be referred to as the front trace, and the second surface trace L3 located on the second surface B can be referred to as the back trace. Based on the above embodiment, it can be known that the embodiment of the present disclosure is to transfer the binding area between the light-emitting element L01 and the external circuit board to the back of the display panel, and realize the binding connection between the light-emitting element L01 and the external circuit board through the front + side + back lines. It is often used in scenarios where all four sides of direct display products can be spliced ​​to avoid the seam affecting the display uniformity of the product.

[0091] In addition, in some embodiments, the front wiring can be manufactured using a yellow light process, and the side wiring and back wiring can be manufactured using a laser etching process. The process in this embodiment can be referred to as a single-sided backplane (BP) process. Alternatively, in some embodiments, both the front wiring and the back wiring can be manufactured using a yellow light process, and only the side wiring can be manufactured using a laser etching process. The process in this embodiment can be referred to as a double-sided BP process. The embodiments of this disclosure do not limit the panel manufacturing process.

[0092] Based on the structures shown in FIG. 1 to FIG. 3 , with reference to the film layer structure diagram shown in FIG. 4 , it can be seen that in the display panel provided by the embodiment of the present disclosure, the electrode structure 02 located in the peripheral area A2 includes:

[0093] A buffer layer 021, at least one conductive pattern 022, and at least one passivation layer 023 located on a side of each conductive pattern 022 away from the substrate 01 are stacked sequentially in a direction away from the substrate 01.

[0094] The first angle α1 between any of the at least one passivation layer 023 and the supporting surface of the substrate 01 is less than or equal to (i.e., not greater than) the second angle α2 between the conductive pattern 022 closer to the substrate 01 and the supporting surface of the substrate 01 in the at least one conductive pattern 022. That is, in the disclosed embodiment, even if the conductive pattern 022 closer to the substrate 01 is thicker and has a steeper slope due to the manufacturing process and film material, and has a larger angle with the substrate 01, the other film layers located on the side of the steeper conductive pattern 022 farther from the substrate 01 can still have a smaller slope and a smaller angle with the substrate 01 to prevent peeling between the film layers.

[0095] Optionally, in some embodiments, the electrode structure 02 may further include a wiring protection layer located on at least one side surface C and covering the side wiring L2. This layer protects the side wiring L2, provides electrical insulation, and prevents oxygen corrosion, thereby preventing the side wiring L2 from being damaged by external factors such as peeling, disconnection, or oxidation. In some embodiments, the wiring protection layer is, for example, a protective adhesive layer or an ink layer.

[0096] In summary, an embodiment of the present disclosure provides a display panel. In this display panel, the side wiring is connected to the first surface wiring through the electrode structure, and further extends to the second surface through the first surface and the side surface in sequence. The electrode structure includes at least one layer of conductive pattern stacked in sequence in a direction away from the substrate and at least one passivation layer located on the side of each conductive pattern away from the substrate. Because the first angle between any passivation layer and the supporting surface of the substrate is less than or equal to the second angle between the conductive pattern close to the substrate and the supporting surface of the substrate, it is possible to avoid the problem of the angle being too large due to the influence of the preparation process, thereby causing the film layer to climb and fall off, thereby ensuring a good product yield.

[0097] As an optional implementation, the first angle α1 between any passivation layer 023 and the supporting surface of the substrate 01 can be smaller than the second angle α2 between the conductive pattern 022 close to the substrate 01 and the supporting surface of the substrate 01, and the first angle α1 and the second angle α2 can both be greater than 0 and less than 90 degrees. On this basis, as shown in FIG4 , in this implementation, the electrode structure 02 may include:

[0098] 1. A first conductive pattern 022a, a first passivation layer 023a, a second conductive pattern 022b, and a second passivation layer 023b are sequentially stacked in a direction away from substrate 01, and the orthographic projection of the first conductive pattern 022a on substrate 01 can be located within the orthographic projection of the second conductive pattern 022b on substrate 01. Electrode structure 02 can include two layers of conductive patterns 022 and two layers of passivation layers 023.

[0099] Optionally, the thickness of the first conductive pattern 022a is generally between 1.8 μm and 2.8 μm, such as 2 μm; the thickness of the first passivation layer 023a and the second passivation layer 023b is generally between 2000 angstroms. to Between, such as The thickness of the second conductive pattern 022b is generally between 0.6 μm and 0.9 μm, such as 0.9 μm. It should be noted that in the embodiment of the present disclosure, the thickness direction may be a direction perpendicular to the supporting surface of the substrate 01 .

[0100] 2. A through hole K1 that penetrates the second passivation layer 023b and exposes the second conductive pattern 022b.

[0101] 3. The protective layer 024 located in the through hole K1 and covering the second conductive pattern 022b. The protective layer 024 can be used to protect the exposed second conductive pattern 022b and prevent moisture in the air from corroding the second conductive pattern 022b.

[0102] 4. A transfer hole K2 penetrates the first passivation layer 023a and exposes the first conductive pattern 022a. The second conductive pattern 022b is connected to the first conductive pattern 022a through the transfer hole K2. The first conductive pattern 022a and the second conductive pattern 022b that are connected to each other can also be called a transfer portion of the electrode structure 02.

[0103] It should be noted that the transfer hole K2 can be away from at least one side surface C relative to the through hole K1. That is, as shown in FIG4 , the through hole K1 can be close to at least one side surface C, and its orthographic projection on the substrate 01 does not overlap with the orthographic projection of the first conductive pattern 022a on the substrate 01, and they are spaced apart from each other.

[0104] Based on Figure 4 and the film layer structure diagram shown in Figure 5, it can be seen that the electrode structure 02 located in the peripheral area A2 generally includes: a buffer layer 021, a first conductive pattern 022a, a first passivation layer 023a, a second conductive pattern 022b, and a second passivation layer 023b, stacked in a sequence away from the substrate 01. In other words, the first passivation layer 023a directly overlaps the side of the first conductive pattern 022a away from the substrate 01. At the transfer hole K2 of the transfer portion, a structure exists where the first passivation layer 023a and the second conductive pattern 022b overlap the first conductive pattern 022a. Since the thickness of the first passivation layer 023a and the second conductive pattern 022b are relatively thin (e.g., 0.4 μm and 0.9 μm, respectively), and the thickness of the first conductive pattern 022a is relatively thick (e.g., 2 μm), the first passivation layer 023a and the second conductive pattern 022b have poor coverage at the climbing part of the first conductive pattern 022, which may cause peeling between the film layers or even film breakage in severe cases.

[0105] In the embodiment of the present disclosure, referring to the film layer structure diagram shown in FIG4 , it can be seen that in the display panel described in the embodiment of the present disclosure, the electrode structure 02 includes, in addition to the above film layers, further including:

[0106] 5. A spacer layer 025 located between the first conductive pattern 022a and the first passivation layer 023a.

[0107] The orthographic projection of the spacer layer 025 on the substrate 01 may be located within the orthographic projection of the first passivation layer 023a on the substrate 01, and cover the side surface C of the first conductive pattern 022a that contacts the buffer layer 021 and the top surface away from the buffer layer 021. The thickness of the spacer layer 025 may be greater than the thickness of any other film layer in the electrode structure 02. For example, the thickness of the spacer layer 025 may be greater than 3 μm. For example, in some embodiments, the thickness of the spacer layer 025 may be 4 μm.

[0108] That is, in the disclosed embodiment, a spacer layer 025 can be provided to wrap around the edge of the first conductive pattern 022a, so that the step difference of the second conductive pattern 022b is formed by the spacer layer 025, rather than directly by the first passivation layer 023a. Due to the relatively thick spacer layer 025, on the one hand, it can achieve good coverage at the slope of the first conductive pattern 022a, eliminating the risk of film fracture. On the other hand, it can also reduce the angle α3 between it and the supporting surface of the substrate 01, that is, the slope is relatively gentle, which is more suitable for covering and wrapping thinner film layers. On this basis, the first angle α1 between any passivation layer 023 and the bearing surface of the substrate 01 can be made smaller than the second angle α2 between the conductive pattern 022 close to the substrate 01 and the bearing surface of the substrate 01, thereby preventing the first passivation layer 023a and the second conductive pattern 022b from climbing the steep slope of the first conductive pattern 022a. That is, a gentle slope can be formed by the thicker spacer layer 025, which facilitates the coverage of the first passivation layer 023a and the second conductive pattern 022b, thereby improving the peeling problem caused by the first passivation layer 023a and the second conductive pattern 022b at the transfer via K2.

[0109] That is, in the embodiment of the present disclosure, the third angle α3 between the spacer layer 025 and the bearing surface of the substrate 01 may also be smaller than the second angle α2. Furthermore, in some embodiments, the first angle α1 between any passivation layer 023 and the bearing surface of the substrate 01 may also be equal to the third angle α3. Furthermore, the first angle α1 between each passivation layer 023 and the bearing surface of the substrate 01 is equal, and the fourth angle (not marked in the figure) between the second conductive pattern 022b and the bearing surface of the substrate 01 may also be equal to the first angle α1. In this way, better coverage between adjacent film layers can be further ensured to avoid peeling between film layers.

[0110] Optionally, in the embodiment of the present disclosure, the material of the spacer layer 025 can be a resin material with a relatively thick thickness that can be set and a smooth surface. It should be noted that the position that is easy to peel can refer to the area Q1 marked in Figure 5. In this area Q1, at the boundary of the transfer hole K2 where the first conductive pattern 022a and the second conductive pattern 022b are transferred in the current display panel, there is a structure in which the first passivation layer 023a, the second conductive pattern 022b, the second passivation layer 023b and other film layers climb the side of the first conductive pattern 022a. The embodiment of the present disclosure introduces a thicker spacer layer 025 between the first conductive pattern 022a and the first passivation layer 023a to better cover the side of the first conductive pattern 022a, so that the subsequent second conductive pattern 022b and the second passivation layer 023b and other film layers can maintain good coverage at the side climbing of the spacer layer 025, thereby better improving the problem of poor peeling between the film layers.

[0111] Optionally, Figure 6 shows a front view of a display panel, Figure 4 is a cross-sectional view of the structure shown in Figure 6 along the nn' direction, and Figure 7 shows a cross-sectional view of the structure shown in Figure 6 along the kk' direction.

[0112] As can be seen from Figures 6 and 7 , the display area A1 on the front of the display panel provided by the embodiment of the present disclosure may include: a buffer layer 021, a first wiring layer M1, a first resin layer Resin1, a first passivation layer 023a, a second wiring layer M2, a second resin layer Resin2, and a second passivation layer 023b, stacked sequentially in a direction away from the substrate 01. The first wiring layer M1 and the second wiring layer M2 can be used to form a plurality of front wiring lines L1.

[0113] Furthermore, referring to FIG6 , it can be seen that in the display panel provided by the embodiment of the present disclosure, the first resin layer Resin1 in the display area A1 can be extended to the peripheral area A2 as the spacer layer 025 of the electrode structure 02. That is, in the embodiment of the present disclosure, the resin layer is not only located in the display area A1 on the front, but also in the peripheral area A2 on the front, overlapping with the orthographic projection of the electrode structure 02 on the substrate 01. Moreover, as shown in FIG4 , the resin layer also covers the side of the first conductive pattern 022a and does not block the transfer hole K2. In this way, the subsequent film layers such as the second conductive pattern 022b and the second passivation layer 023b can maintain good coverage at the side slope of the spacer layer 025, thereby better improving the peeling problem between the film layers. In combination with Figure 5, in the display panel of the related art, the first resin layer Resin1 is only located in the display area A1 on the front, and does not extend to the peripheral area A2. That is, in the related art, the orthographic projection of the first resin layer Resin1 on the substrate 01 and the orthographic projection of the first conductive pattern 022a on the substrate 01 do not overlap, and the resin layer is far away from at least one side surface C relative to the electrode structure 02. Therefore, the above-mentioned film peeling problem is very likely to occur in area Q1.

[0114] Optionally, in some embodiments, continuing to refer to Figure 6, it can be seen that the minimum distance d2_min between the side of the spacer layer 025 close to at least one side surface C and the side of the electrode structure 02 close to at least one side surface C is generally about 105 μm, and the maximum distance d2_max between the side of the spacer layer 025 close to at least one side surface C and the side of the electrode structure 02 close to at least one side surface C is generally about 170 μm.

[0115] Optionally, in some embodiments, based on FIG6 , in combination with the partial schematic diagrams of a display panel shown in FIG1 and FIG8 , it can be seen that the display panel described in the embodiments of the present disclosure may include a plurality of pixels P arranged in an array as shown in FIG1 . The plurality of pixels P may be arranged in N rows and M columns. Each pixel P includes at least three sub-pixels SP of different colors and a driving element that drives each sub-pixel SP to emit light. Each sub-pixel SP includes at least one light-emitting element L01. The light-emitting element L01 and the driving element may be located on the side of the second passivation layer 023b away from the substrate 01 as shown in FIG7 .

[0116] For example, as shown in FIG8 , the present disclosure is described using the example of each pixel P including three sub-pixels SP, each sub-pixel SP including one light-emitting element L01. The three light-emitting elements L01 in the figure are arranged in three rows, and the light-emitting elements L01 in the three rows, from top to bottom, may be light-emitting elements L01 of a first color (e.g., red), light-emitting elements L01 of a second color (e.g., green), and light-emitting elements L01 of a first color (e.g., blue).

[0117] Optionally, in some embodiments, the second wiring layer M2 may further form a plurality of connection pads (not shown in the figure), and the plurality of connection pads may be used to electrically connect the light-emitting element L01 and the driving element. For example, the pins of the light-emitting element L01 and the pins of the driving element may be electrically connected to the corresponding connection pads through a welding material S (e.g., solder, tin-silver-copper alloy, or tin-copper alloy, etc.), and as shown in FIG7 , a protective layer 024 as described in the above embodiment is further provided on the connection pads. The pins of the light-emitting element L01 may be electrically connected to the two connection pads through vias penetrating the second passivation layer 023 b and the second resin layer Resin2, and the pins of the driving element may be connected to the six connection pads through vias penetrating the second passivation layer 023 b and the second resin layer Resin2, so that the light-emitting element L01 can emit light under the control of the signal transmitted by the signal line and the driving element.

[0118] Optionally, in some embodiments, with continued reference to Figures 6 and 7, it can be seen that the front wiring L1 formed by the first wiring layer M1 may include a data line Dm, a first positive signal line Hm1, a second positive signal line Hm2, a reference signal line Vm, and a scan signal adapter line Cn. The front wiring L1 formed by the second wiring layer M2 may include multiple scan signal lines Sn, each of which may be electrically connected to a scan signal adapter line Cn. Furthermore, the driving element may be electrically connected to the cathode of the light-emitting element L01 in each sub-pixel SP it drives, at least one data signal line Dm from the multiple data lines, at least one scan signal line Sn from the multiple scan lines, and at least one reference signal line Vm from the multiple reference signal lines. The driving element may be configured to, under the control of the scan signal line Sn, time-share the signal of the data signal line Dm into sub-pixels SP of different colors, wherein the reference signal line Vm is used to provide a negative signal to the driving element to form a current path between the driving element and the light-emitting element L01. That is, driven by the signal transmitted by the front line L1 , the light-emitting element L01 can emit light reliably.

[0119] Alternatively, in some embodiments, referring to FIG. 8 , the driving element may include a first signal terminal O1, a second signal terminal O2, a third signal terminal O3, a fourth signal terminal O4, a fifth signal terminal O5, and a sixth signal terminal O6. The first signal terminal O1 is connected to the cathode - of the first-color light-emitting element L01, the second signal terminal O2 is connected to the cathode - of the second-color light-emitting element L01, the third signal terminal O3 is connected to the cathode - of the third-color light-emitting element L01, the fourth signal terminal O4 is electrically connected to the data signal line Dm, the fifth signal terminal O5 is connected to the scan signal line Sn, and the sixth signal terminal O6 is connected to the reference signal line Vm. The anode + of the first-color light-emitting element L01 is connected to the second positive signal line Hm2, the anode + of the second-color light-emitting element L01 is connected to the first positive signal line Hm1, and the anode + of the third-color light-emitting element L01 is connected to the first positive signal line Hm1. The scan signal line Sn is connected to the scan signal adapter line Cn.

[0120] Based on the above-mentioned embodiment, FIG10 shows a microscope photograph of a display panel after setting a spacer layer 025 to cover the side of the first conductive pattern 022a. In combination with FIG10, it can be seen that for the current solution shown in FIG5, the angle of the first passivation layer 023a at the climbing position of the first conductive pattern 022a is relatively large, generally averaging 69.8 degrees, and the maximum can even reach 77.4 degrees. After adopting the solution shown in FIG4 provided by the embodiment of the present disclosure, the angle at the climbing position is significantly reduced, which can be reduced to an average of about 35 degrees, and the maximum value is also about 41.2 degrees, which is not too large. It can be seen that the angle is reduced by about 35 degrees, so that the slope can be reduced to half of the original, ensuring that the first passivation layer 023a can better cover the side of the first conductive pattern 022a.

[0121] Taking the angle profile of a conductive pattern (such as the first conductive pattern 022a located in the same layer as the first wiring layer M1) as an example, the definition of the angle profile of any film layer in the embodiment of the present disclosure is explained as follows in conjunction with Figure 9: In the preparation process, a conductive film layer as shown in step (1) in Figure 9 can first be formed on the substrate 01; then a patterned photoresist (PR) can be set on the side of the conductive film layer away from the substrate 01; then the patterned PR is used to expose, develop, etch and other processes on the conductive film layer to pattern the conductive film layer to obtain the desired conductive pattern. Due to the anisotropy of etching, a conductive pattern with an angle profile as shown in step (2) is finally formed. For example, in conjunction with Figure 9, it can also be seen that the angle profile finally formed can satisfy: tan(profile) = h / x, where x = x1-x2.

[0122] Among them, X1 is the lateral etching amount at the Po1 point of the conductive pattern, also known as the top lateral etching amount. This lateral etching amount is mainly related to the strength of the adhesion between the conductive film layer and the photoresist; h refers to the thickness of the conductive film layer, which is determined by the coating process; X2 refers to the lateral etching amount at the Po2 point of the conductive pattern, which is a single-sided etching deviation (CD bias) and is related to the etching time, etching solution concentration, conductive film layer material, and the adhesion between the conductive film layer and the photoresist PR. It can be seen that the formed angle profile is related to the top lateral etching amount, CD bias and the thickness of the conductive film layer. Under the same etching conditions, the greater the thickness of the conductive film layer, the larger the angle profile of the formed conductive pattern; conversely, the smaller the thickness of the conductive film layer, the smaller the angle profile of the formed conductive pattern. That is, the angle profile of the formed conductive pattern is positively correlated with the thickness of the conductive film layer. Under the premise that the thickness of the conductive film layer is fixed, the angle profile of the conductive pattern can be changed by adjusting the top lateral etching amount and CD bias.

[0123] It should be noted that, in conjunction with the microscope photograph shown in FIG10 , the third angle α3 between the spacer layer 025 and the supporting surface of the substrate 01 is used as an example to illustrate the angle measurement method described in the embodiment of the present disclosure. It can be seen that the spacer layer 025 does not have a cross-section with a straight line segment on the side, as in the metal pattern in FIG9 . The side of the cross-section of the spacer layer 025 is a curved segment, and each point on the curved segment has a corresponding tangent. Therefore, the angle between each film layer and the supporting surface of the substrate 01 described in the embodiment of the present disclosure can refer to: the angle profile of the line connecting the highest point Po1 and the lowest point Po2 of the curved segment. Moreover, the highest point Po1 is not the point Po3 with the greatest distance from the substrate 01 in the curved segment as shown in FIG10 , but the point where the slope of the tangent line among the points on the curved segment undergoes a sudden change (that is, the point with the greatest change in slope), such as the point Po1 shown in FIG10 . This point Po1 can also be defined as the highest point on the side of the cross-section of the spacer layer 025.

[0124] Optionally, as shown in FIG11 , the electrode structure 02 in the embodiment of the present disclosure may further include:

[0125] A third passivation layer 023c is located between the first conductive pattern 022a and the spacer layer 025. The via K2 penetrates the third passivation layer 023c to expose the first conductive pattern 022a. By providing the third passivation layer 023c between the spacer layer 025 and the first conductive pattern 022a in addition to the spacer layer 025, the first conductive pattern 022a can be protected.

[0126] It should be noted that the structures shown in FIG11 and FIG4 can be considered as two parallel implementations proposed based on the above-mentioned optional implementation method (i.e., the angles of the first angle α1 and the second angle α2 can both be greater than 0 and less than 90 degrees). That is, in some embodiments, as shown in FIG4, the electrode structure 02 can be provided to include a first conductive pattern 022a, a spacer layer 025, a first passivation layer 023a, a second conductive pattern 022b, and a second passivation layer 023b stacked in sequence; in other embodiments, as shown in FIG11, the electrode structure 02 can be provided to include a first conductive pattern 022a, a third passivation layer 023c, a spacer layer 025, a first passivation layer 023a, a second conductive pattern 022b, and a second passivation layer 023b stacked in sequence.

[0127] As another optional implementation: the first angle α1 between any passivation layer 023 and the supporting surface of the substrate 01 can be equal to the second angle α2 between the conductive pattern 022 close to the substrate 01 and the supporting surface of the substrate 01, and the angles of the first angle α1 and the second angle α2 can both be 0. In other words, any passivation layer 023 and the conductive pattern 022 close to the substrate 01 can be parallel to the substrate 01. On this basis, as shown in Figure 12, in this implementation, the electrode structure 02 may include:

[0128] 1. A first conductive pattern 022a, a first passivation layer 023a, and a second passivation layer 023b are sequentially stacked in a direction away from the substrate 01. That is, the electrode structure 02 may include one conductive pattern 022 and two passivation layers 023.

[0129] 2. A through hole K1 that penetrates the first passivation layer 023a and the second passivation layer 023b and exposes the first conductive pattern 022a. As described in the above embodiment, the through hole K1 can be close to at least one side surface C. Generally, the distance between the side edge of the through hole K1 close to the at least one side surface and the boundary of the at least one side surface is about 11 μm.

[0130] 3. The protection layer 024 is located in the through hole K1 and covers the first conductive pattern 022a.

[0131] In this alternative implementation, the second conductive pattern 022b described in the above embodiment is eliminated, and the first conductive pattern 022a is directly used as a binding terminal to electrically connect to the side trace L2. Comparing Figures 3 and 11, it can be seen that compared to the above alternative implementation, this alternative implementation eliminates the need for the transition hole connecting the first conductive pattern 022a and the second conductive pattern 022b. In other words, no transition portion is required. Consequently, the structure described in the above embodiment where the second conductive pattern 022b is sloped to the side of the first conductive pattern 022a is also eliminated. This essentially solves the peeling problem between film layers caused by the sloped arrangement.

[0132] Optionally, referring to FIG. 6 and FIG. 7 , it can be seen that the first surface trace L1 described in the embodiment of the present disclosure may include: a first trace layer M1 and a second trace layer M2 sequentially stacked in a direction away from the substrate 01 .

[0133] On this basis, combined with the film layer structure diagram shown in FIG4 , it can be seen that in one of the aforementioned optional implementations, the electrode structure 02 described in the embodiment of the present disclosure includes a first conductive pattern 022a and a second conductive pattern 022b stacked sequentially, totaling two layers of conductive patterns 022. The first conductive pattern 022a is located on the same layer as the first routing layer M1, and the second conductive pattern 022b is located on the same layer as the second routing layer M2. Combined with the film layer structure diagram shown in FIG11 , it can be seen that in another of the aforementioned optional implementations, the electrode structure 02 described in the embodiment of the present disclosure includes a first conductive pattern 022a located on the same layer as the first routing layer M1.

[0134] It should be noted that being located in the same layer may refer to a layer structure formed by using the same film-forming process to form a film layer for forming a specific pattern, and then using the same mask to pattern the film layer through a single patterning process. Depending on the specific pattern, a single patterning process may include multiple exposure, development, or etching processes, and the specific pattern in the formed layer structure may be continuous or discontinuous. That is, multiple elements, components, structures, and / or parts located in the "same layer" are made of the same material and are formed through the same patterning process. In this way, manufacturing processes and manufacturing costs can be saved, and manufacturing efficiency can be accelerated.

[0135] It should also be noted that, as described in the above embodiment, the thickness of the first routing layer M1 is generally greater than the thickness of the second routing layer M2. Therefore, in the above-mentioned alternative implementation method in which the electrode structure 02 includes only the first conductive pattern 022a located on the same layer as the first routing layer M1, compared to the alternative implementation method in which the first conductive pattern 022a and the second conductive pattern 022b are located on the same layer as the first routing layer M1 and the second routing layer M2, respectively, the overall thickness of the film layer of the electrode structure 02 near at least one side surface C is thicker, generally about 1.1 μm thick. For example, in the above-mentioned alternative implementation method, the electrode structure 02 near at least one side surface C mainly includes: a buffer layer 021 + a first passivation layer 023a + a second conductive pattern 022b (i.e., the second routing layer M2) + a second passivation layer 023b. For the alternative implementation described above, the electrode structure 02 near at least one side surface C primarily comprises: a buffer layer 021 + a first passivation layer 023a + a first conductive pattern 022a (i.e., the first routing layer M1) + a second passivation layer 023b. Furthermore, another buffer layer may be included on the side of the second passivation layer 023b near the substrate 01. A thicker layer is less conducive to subsequent edge grinding.

[0136] Optionally, referring to Figures 4, 11, and 12, it can be seen that in the electrode structure 02 described in the embodiment of the present disclosure, the thickness of the protective layer 024 can be greater than the thickness of the through hole K1. For example, the thickness of the protective layer 024 can be about 3 to 4 μm.

[0137] Optionally, the material of the protective layer 024 may include a metal material. For example, the material of the protective layer 024 may include nickel and / or gold.

[0138] It should be noted that the peeling improvement method described in the above embodiment can be considered as an improvement method from the design perspective. The following embodiment proposes another improvement method from the process perspective:

[0139] First, in the embodiment of the present disclosure, the film structure of at least one conductive pattern 022 in the electrode structure 02 can be improved to reduce the slope, thereby improving the film coverage effect and improving the film peeling problem.

[0140] Optionally, as shown in FIG13 , in the electrode structure 02 described in the embodiment of the present disclosure, at least one layer of conductive pattern 022 may include: multiple layers of sub-conductive patterns 0221 stacked sequentially in a direction away from the substrate 01 .

[0141] For example, in the electrode structure 02 shown in FIG13 , at least one conductive pattern 022 includes: three layers of sub-conductive patterns 0221 stacked in sequence in a direction away from the substrate 01. Moreover, in the embodiment of the present disclosure, the materials of the three-layer sub-conductive pattern 0221 may include: metal molybdenum Mo, metal copper Cu, and metal molybdenum Mo, that is, a Mo / Cu / Mo structure; or metal molybdenum niobium MoNb, metal copper Cu, and metal molybdenum niobium MoNb, that is, a MoNb / Cu / MoNb structure. Optionally, the thickness of each layer in the Mo / Cu / Mo structure may be: and The thickness of each layer in the MoCuMo structure can be and Here, the thickness and material are merely schematic illustrations.

[0142] Optionally, in the embodiment of the present disclosure, the at least one layer of conductive pattern 022 may include: a conductive pattern 022 on the side closer to the substrate 01 among the at least one layer of conductive pattern 022 included in the electrode structure 02. For example, the first conductive pattern 022a (i.e., the first routing layer M1) described in the above embodiment. Of course, in some other embodiments, the at least one layer of conductive pattern 022 may also include: a conductive pattern 022 on the side farther from the substrate 01 among the at least one layer of conductive pattern 022 included in the electrode structure 02, such as the second conductive pattern 022b described in the above embodiment. Accordingly, in the embodiment of the present disclosure, the first conductive pattern 022a may also be referred to as the Cu1 layer, and the second conductive pattern 022b may be referred to as the Cu2 layer.

[0143] It should be noted that in current display panels, the structure of the first routing layer M1 usually includes, at most, Mo / Cu stacked in sequence in a direction away from the substrate 01. In conjunction with Figure 5 , a first passivation layer 023a is directly provided on one side of the first conductive pattern 022a located on the same layer as the first routing layer M1. Due to the influence of the material, the adhesion between the first passivation layer 023a and the metal copper Cu is poor, and peeling is also prone to occur. However, the disclosed embodiment improves the structure of the first routing layer M1 by providing it with Mo / Cu / Mo or MoNb / Cu / MoNb stacked in sequence in a direction away from the substrate 01. This can directly reduce the angle between the first conductive pattern 022a located on the same layer as the first routing layer M1 and the bearing surface of the substrate 01, and slow down the slope of the first conductive pattern 022a, thereby facilitating the coverage of the film layer on the side of the first conductive pattern 022a away from the substrate 01, ensuring the coverage integrity of the first passivation layer 023a at the slope of the first conductive pattern 022a, and improving the peeling problem of the film layer.

[0144] For example, on the basis of the structure of the first wiring layer M1 (ie, the first conductive pattern 022a) including sequentially stacked Mo / Cu, the thickness of the Mo / Cu structure is respectively and For example, FIG14 shows a schematic diagram of an SEM slice; on the basis of the first wiring layer M1 including the structure of Mo / Cu / Mo stacked in sequence, the thickness of the Mo / Cu / Mo structure is respectively and For example, Figure 15 shows another microscope photograph. Comparing Figures 14 and 15, it can be seen that the angle α2 of the first conductive pattern 022a currently comprising only a Mo / Cu structure is approximately 71 degrees, while the angle α2 of the first conductive pattern 022a comprising a Mo / Cu / Mo structure in the disclosed embodiment can be reduced to 32.6 degrees. The angles here are merely schematic. Furthermore, Figures 14 and 15 also respectively illustrate the PR provided on one side of the first conductive pattern 022a.

[0145] Optionally, the materials and thicknesses of other film layers are described as follows: the materials of the buffer layer 021 and the passivation layer 022 may include silicon nitride SiNx and / or silicon oxide SiOx. The thickness of the buffer layer 021 may be approximately to As a general rule,

[0146] Secondly, in the embodiment of the present disclosure, at least one passivation layer 023 in the electrode structure 02 may be thicker to improve the coverage of the passivation layer 023 and alleviate the subsequent film peeling problem caused by the step difference of the first conductive pattern 022a.

[0147] Optionally, in the electrode structure 02, the thickness of at least one passivation layer 023 may be greater than and less than or equal to For example, the thickness of at least one passivation layer 023 may be set to

[0148] Optionally, the at least one passivation layer 023 with a greater thickness may include the passivation layer 023 on the side away from the substrate 01, such as the second passivation layer 023b described in the above embodiment. Of course, in other embodiments, the at least one passivation layer 023 with a greater thickness may also include the passivation layer 023 on the side closer to the substrate 01, such as the first passivation layer 023a described in the above embodiment. This can also improve film coverage and alleviate film peeling issues.

[0149] Based on the records of the above embodiments, it can be seen that the embodiments of the present disclosure can improve the peeling problem of the film layer by adding a spacer layer or directly eliminating the transfer hole from the design end, and on the other hand, improve the film layer structure and / or film layer thickness from the process end to improve the peeling problem of the film layer, ultimately ensuring a good product yield.

[0150] In summary, an embodiment of the present disclosure provides a display panel. In this display panel, the side wiring is connected to the first surface wiring through the electrode structure, and further extends to the second surface through the first surface and the side surface in sequence. The electrode structure includes at least one layer of conductive pattern stacked in sequence in a direction away from the substrate and at least one passivation layer located on the side of each conductive pattern away from the substrate. Because the first angle between any passivation layer and the supporting surface of the substrate is less than or equal to the second angle between the conductive pattern close to the substrate and the supporting surface of the substrate, it is possible to avoid the problem of the angle being too large due to the influence of the preparation process, thereby causing the film layer to climb and fall off, thereby ensuring a good product yield.

[0151] FIG16 is a flow chart of a method for manufacturing a display panel according to an embodiment of the present disclosure, which is used to manufacture the display panel described in the above embodiment of the present disclosure. As shown in FIG16 , the method includes:

[0152] Step 1601: Provide a substrate, wherein the provided substrate has a first surface and a second surface opposite to each other, and a plurality of side surfaces connecting the first surface and the second surface, wherein the first surface includes a display area and a peripheral area surrounding the display area.

[0153] Step 1602: forming a first surface trace in the display area of ​​the first surface, and forming an electrode structure in the peripheral area of ​​the first surface, wherein the formed electrode structure includes: a buffer layer located on one side of the substrate and stacked sequentially in a direction away from the substrate, at least one conductive pattern, and at least one passivation layer located on the side of each conductive pattern away from the substrate, wherein a first angle between any one of the at least one passivation layer and the bearing surface of the substrate is less than or equal to a second angle between the conductive pattern close to the substrate in the at least one conductive pattern and the bearing surface of the substrate.

[0154] Step 1603: Form a side trace on at least one side surface among the multiple side surfaces, and electrically connect one end of the side trace to the electrode structure, extend the other end of the side trace through the first surface and at least one side surface to the second surface in sequence, and electrically connect the electrode structure to the first surface trace.

[0155] Among them, the formed electrode structure includes: a buffer layer located on one side of the substrate and stacked in sequence in a direction away from the substrate, at least one conductive pattern and at least one passivation layer located on the side of each conductive pattern away from the substrate, and the first angle between any passivation layer in the at least one passivation layer and the supporting surface of the substrate is less than or equal to the second angle between the conductive pattern close to the substrate in the at least one conductive pattern and the supporting surface of the substrate.

[0156] As an optional implementation: As shown in FIG4 , in the formed electrode structure 02 , the first angle α1 can be smaller than the second angle α2 , and both the first angle α1 and the second angle α2 can be greater than 0 and less than 90 degrees. In this implementation, in step 1602 , forming the electrode structure in the peripheral area of ​​the first surface can include the following steps:

[0157] a1. A first conductive pattern, a first passivation layer, a second conductive pattern, and a second passivation layer are formed on one side of a substrate, which are stacked in sequence in a direction away from the substrate, and the orthographic projection of the first conductive pattern on the substrate is located within the orthographic projection of the second conductive pattern on the substrate.

[0158] b1. Forming a through hole penetrating the second passivation layer and exposing the second conductive pattern.

[0159] c1. Forming a protection layer in the through hole to cover the second conductive pattern.

[0160] d1. Forming a via hole penetrating the first passivation layer and exposing the first conductive pattern, wherein the formed via hole is away from at least one side surface relative to the through hole.

[0161] e1. Connect the second conductive pattern to the first conductive pattern through the connecting hole.

[0162] f1. A spacer layer is formed between the first conductive pattern and the first passivation layer, and the orthographic projection of the formed spacer layer on the substrate is located within the orthographic projection of the first passivation layer on the substrate, and covers the side surface of the first conductive pattern in contact with the buffer layer and the top surface away from the buffer layer, and the thickness of the formed spacer layer is greater than the thickness of any other film layer in the electrode structure.

[0163] As another optional implementation: as shown in FIG12 , in the formed electrode structure 02 , the first angle α1 is equal to the second angle α2, and the first angle α1 and the second angle α2 can both be 0. In this implementation, in the above step 1602 , forming the electrode structure in the peripheral area of ​​the first surface can include the following steps:

[0164] a2. Forming a first conductive pattern, a first passivation layer, and a second passivation layer on one side of the substrate, which are sequentially stacked in a direction away from the substrate.

[0165] b2. Forming a through hole penetrating the first passivation layer and the second passivation layer and exposing the first conductive pattern.

[0166] c2. Form a protection layer in the through hole to cover the first conductive pattern.

[0167] Optionally, as described in the above embodiment, in the above step 1602, forming a first surface trace in the display area of ​​the first surface may include: forming the first surface trace in the display area of ​​the first surface using a yellow light process. Forming a side trace on at least one side surface among the multiple side surfaces may include: forming the side trace on at least one side surface among the multiple side surfaces using a laser etching process. Optionally, as described in the above embodiment, in some embodiments, a second surface trace may also be formed on the second surface to electrically connect the side trace to an external circuit board located on the second surface. Furthermore, forming a second surface trace on the second surface may include: forming the second surface trace on the second surface using a yellow light process or a laser etching process.

[0168] Among them, the process of using yellow light process to form front and back routing, and using laser etching process to form side routing can be called double-sided BP process; the process of using yellow light process to form front routing, and using laser etching process to form side and back routing can be called single-sided BP process.

[0169] Optionally, taking the film layer structure shown in FIG11 , which is an optional implementation method described above, as an example, the following embodiment briefly describes the manufacturing process of the display panel:

[0170] 1) A buffer layer 021 can be formed on the provided substrate 01. Optionally, the substrate 01 provided here can be a glass substrate; and the buffer layer 021 can be formed by magnetron sputtering process, and the thickness of the buffer layer 021 can be about

[0171] 2) Next, a Cu1 layer, i.e., a first conductive pattern 022a, can be formed on the side of the buffer layer 021 away from the substrate 01. Optionally, the first conductive pattern 022a can be formed through a process including magnetron sputtering, cleaning, coating, baking, photo exposure, development, hard baking, etching, and lift-off. The thickness of the first conductive pattern 022a is approximately 2 μm.

[0172] 3) Next, a third passivation layer 023c may be formed on the side of the Cu1 layer away from the substrate 01. Optionally, the third passivation layer 023c may be formed by a magnetron sputtering process, or, in some embodiments, by chemical vapor deposition (CVD). The thickness of the third passivation layer 023c may be approximately

[0173] 4) Next, a spacer layer 025 can be formed on the side of the third passivation layer 023c away from the substrate 01. Optionally, the material of the spacer layer 025 can include a resin material and can be formed through a coating, photo, and development process. The thickness of the spacer layer 025 can be about 4 μm.

[0174] 5) Next, a first passivation layer 023a can be formed on the side of the spacer layer 025 away from the substrate 01. Similarly, the first passivation layer 023a can also be formed by a magnetron sputtering process or a chemical vapor deposition process, and the thickness of the first passivation layer 023a can be about Thereafter, the first passivation layer 023 a may be etched through an etching process to form a via hole K1 exposing the first conductive pattern 022 a .

[0175] 6) Next, a Cu2 layer, i.e., a second conductive pattern 022b, can be formed on the side of the first passivation layer 023a away from the substrate 01. Similarly, the second conductive pattern 022b can be formed using a process flow including magnetron sputtering, cleaning, coating, baking, photolithography, developing, hard baking, etching, and lift-off. The thickness of the second conductive pattern 022b can be approximately 0.9 μm.

[0176] 7) Next, a second passivation layer 023b may be formed on the side of the second conductive pattern 022b away from the substrate 01. Similarly, the second passivation layer 023b may also be formed by a magnetron sputtering process or a chemical vapor deposition process. It should be noted that, in some embodiments, the second passivation layer 023b may also include two passivation sublayers stacked in sequence in a direction away from the substrate 01, and may also include a resin layer located between the two passivation sublayers. The thickness of the passivation sublayers may be respectively and The thickness of the resin layer can be about 2 μm. At this point, the front surface process is completed.

[0177] 8) Place the second surface of the substrate horizontally with the second surface facing upwards, and make at least a backside trace and a trace protection layer on the second surface. Optionally, the thickness of the backside trace can be about The thickness of the trace protection layer can be approximately The material of the back wiring may include Cu, and the material of the wiring protection layer may include a transparent conductive material, such as indium tin oxide (ITO). Finally, a layer with a thickness of about 100 nm can be formed on the wiring protection layer by the magnetron sputtering process or chemical vapor deposition process as described in the above embodiment. The passivation protective layer 023b is then patterned to expose a portion of the surface of the stacked structure consisting of the backside wiring and / or wiring protection layer. This completes the backside processing. After the backside processing is completed, the substrate can be flipped over a second time, placed horizontally with the first surface facing upward, and the second passivation layer 023b is etched using a dry etching process to expose a portion of the surface of the electrode structure. A protective layer 024 is then applied to this exposed surface.

[0178] 9) Make side traces to connect the electrode structure with the corresponding back traces.

[0179] It should be noted that the above process flow is merely an illustrative description and does not limit the display panel structure described in the embodiments of the present disclosure.

[0180] In summary, the embodiments of the present disclosure provide a method for preparing a display panel. In the display panel prepared by this method, the side wiring is connected to the first surface wiring through the electrode structure, and also extends to the second surface through the first surface and the side surface in sequence. The electrode structure includes at least one layer of conductive pattern stacked in sequence in a direction away from the substrate and at least one passivation layer located on the side of each conductive pattern away from the substrate. Because the first angle between any passivation layer and the supporting surface of the substrate is less than or equal to the second angle between the conductive pattern close to the substrate and the supporting surface of the substrate, it is possible to avoid the problem of the angle being too large due to the influence of the preparation process, thereby causing the film layer to climb and fall off, thereby ensuring a good product yield.

[0181] Fig. 17 is a schematic diagram of the structure of a display device provided by an embodiment of the present disclosure. As shown in Fig. 17, the display device includes: a power supply component J1 and a display panel 00 as described in the above embodiment.

[0182] The power supply component J1 is coupled to the display panel 00 and is used to supply power to the display panel 00 .

[0183] Optionally, the display device may be any product or component with a display function, such as a mini LED display device, an OLED display device, or a micro LED display device.

[0184] The terms used in the embodiments of the present disclosure are only used to explain the embodiments of the present disclosure and are not intended to limit the present disclosure. Unless otherwise defined, the technical terms or scientific terms used in the embodiments of the present disclosure should have the common meanings understood by people with ordinary skills in the field to which the present disclosure belongs.

[0185] For example, the words "first", "second" or "third" and similar terms used in the patent application specification and claims of this disclosure do not indicate any order, quantity or importance, but are only used to distinguish different components.

[0186] Likewise, the words “a” or “an” and the like do not denote a limitation of quantity, but rather denote the presence of at least one.

[0187] Words such as “include” or “comprising” mean that the elements or objects preceding “include” or “comprising” include the elements or objects listed after “include” or “comprising” and their equivalents, and do not exclude other elements or objects.

[0188] “Up,” “down,” “left,” or “right” are only used to indicate relative positional relationships. When the absolute position of the object being described changes, the relative positional relationship may also change accordingly.

[0189] "And / or" indicates that three relationships can exist. For example, A and / or B can represent: A exists alone, A and B exist simultaneously, and B exists alone. The character " / " generally indicates that the related objects are in an "or" relationship.

[0190] The above description is merely an optional embodiment of the present disclosure and is not intended to limit the present disclosure. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principles of the present disclosure shall be included in the scope of protection of the present disclosure.

Claims

1. A display panel, comprising: A substrate having a first surface and a second surface opposite to each other, and a plurality of side surfaces connecting the first surface and the second surface, wherein the first surface includes a display area and a peripheral area surrounding the display area; A first surface wiring located in a display area of ​​the first surface, an electrode structure located in a peripheral area of ​​the first surface, and a side wiring located on at least one side surface of the plurality of side surfaces; One end of the side wiring is electrically connected to the electrode structure, and the other end of the side wiring sequentially passes through the first surface and the at least one side surface and extends to the second surface, and the electrode structure is also electrically connected to the first surface wiring; Furthermore, the electrode structure includes: a buffer layer located on one side of the substrate and stacked in sequence in a direction away from the substrate, at least one conductive pattern, and at least one passivation layer located on a side of each conductive pattern away from the substrate, and a first angle between any one of the at least one passivation layer and the supporting surface of the substrate is less than or equal to a second angle between the conductive pattern of the at least one conductive pattern close to the substrate and the supporting surface of the substrate.

2. The display panel according to claim 1, wherein: The first angle is equal to the second angle, and the angle is 0; the electrode structure includes: A first conductive pattern, a first passivation layer, and a second passivation layer sequentially stacked in a direction away from the substrate; a through hole penetrating the first passivation layer and the second passivation layer and exposing the first conductive pattern; and a protection layer located in the through hole and covering the first conductive pattern.

3. The display panel according to claim 1, wherein: The first angle is smaller than the second angle, and both angles are greater than 0 and less than 90 degrees; the electrode structure includes: A first conductive pattern, a first passivation layer, a second conductive pattern, and a second passivation layer are sequentially stacked in a direction away from the substrate, and an orthographic projection of the first conductive pattern on the substrate is located within an orthographic projection of the second conductive pattern on the substrate; a through hole penetrating the second passivation layer and exposing the second conductive pattern; a protection layer located in the through hole and covering the second conductive pattern; a transfer hole penetrating the first passivation layer and exposing the first conductive pattern, the second conductive pattern being transferred to the first conductive pattern through the transfer hole, and the transfer hole being away from the at least one side surface relative to the through hole; And, a spacer layer located between the first conductive pattern and the first passivation layer, the orthographic projection of the spacer layer on the substrate is located within the orthographic projection of the first passivation layer on the substrate, and covers the side surface of the first conductive pattern in contact with the buffer layer and the top surface away from the buffer layer, and the thickness of the spacer layer is greater than the thickness of any other film layer in the electrode structure.

4. The display panel according to claim 3, wherein: A third angle between the spacer layer and the supporting surface of the substrate is smaller than the second angle, and the first angle is equal to the third angle; Furthermore, the first angles between each passivation layer and the bearing surface of the substrate are equal, and the fourth angle between the second conductive pattern and the bearing surface of the substrate is equal to the first angle.

5. The display panel according to claim 3, wherein: The thickness of the spacer layer is greater than 3 microns.

6. The display panel according to claim 3, wherein: The material of the spacer layer includes: resin material.

7. The display panel according to claim 3, wherein: The electrode structure further comprises: A third passivation layer is located between the first conductive pattern and the spacer layer, and the via hole also penetrates the third passivation layer to expose the first conductive pattern.

8. The display panel according to any one of claims 2 to 7, wherein: The first surface routing includes: a first routing layer and a second routing layer stacked in sequence in a direction away from the substrate; Wherein, a first conductive pattern layer included in the electrode structure is located in the same layer as the first wiring layer; Alternatively, the electrode structure includes two layers of conductive patterns, namely, a first conductive pattern and a second conductive pattern stacked sequentially, wherein the first conductive pattern and the first routing layer are located in the same layer, and the second conductive pattern and the second routing layer are located in the same layer.

9. The display panel according to any one of claims 2 to 8, wherein: The thickness of the protection layer included in the electrode structure is greater than the thickness of the through hole, and the material of the protection layer includes: metal material.

10. The display panel according to claim 9, wherein: The material of the protection layer includes: nickel and / or gold.

11. The display panel according to any one of claims 1 to 10, wherein: In the electrode structure, at least one layer of the conductive pattern comprises: a plurality of sub-conductive patterns stacked in sequence in a direction away from the substrate.

12. The display panel according to claim 11, wherein: In the electrode structure, at least one layer of the conductive pattern comprises: three layers of sub-conductive patterns stacked in sequence in a direction away from the substrate; Furthermore, the materials of the three-layer sub-conductive pattern include, in sequence: metal molybdenum, metal copper and metal molybdenum; or metal molybdenum-niobium, metal copper and metal molybdenum-niobium.

13. The display panel according to claim 11, wherein: The at least one layer of conductive patterns includes: a conductive pattern close to one side of the substrate in the at least one layer of conductive patterns.

14. The display panel according to any one of claims 1 to 13, wherein: In the electrode structure, the thickness of at least one passivation layer is greater than 2000 angstroms and less than or equal to 4000 angstroms.

15. The display panel according to claim 14, wherein: The at least one passivation layer comprises: a passivation layer on a side of the at least one passivation layer away from the substrate.

16. A method for preparing a display panel, for preparing the display panel according to any one of claims 1 to 15; the method comprising: Providing a substrate, wherein the substrate has a first surface and a second surface opposite to each other, and a plurality of side surfaces connecting the first surface and the second surface, wherein the first surface includes a display area and a peripheral area surrounding the display area; A first surface wiring is formed in a display area of ​​the first surface, and an electrode structure is formed in a peripheral area of ​​the first surface, wherein the electrode structure is electrically connected to the first surface wiring; At least one of the plurality of side surfaces forms a side wiring, one end of the side wiring is connected to The electrode structures are electrically connected, and the other end of the side wiring sequentially passes through the first surface and the at least one side surface and extends to the second surface; Among them, the formed electrode structure includes: a buffer layer located on one side of the substrate and stacked in sequence in a direction away from the substrate, at least one conductive pattern, and at least one passivation layer located on the side of each conductive pattern away from the substrate, and the first angle between any passivation layer in the at least one passivation layer and the supporting surface of the substrate is less than or equal to the second angle between the conductive pattern in the at least one conductive pattern close to the substrate and the supporting surface of the substrate.

17. The method according to claim 16, wherein: The first angle is equal to the second angle, and the angle is 0; an electrode structure is formed in the peripheral area of ​​the first surface, including: Forming a first conductive pattern, a first passivation layer, and a second passivation layer sequentially stacked in a direction away from the substrate on one side of the substrate; forming a through hole penetrating the first passivation layer and the second passivation layer and exposing the first conductive pattern; And, a protection layer covering the first conductive pattern is formed in the through hole.

18. The method according to claim 16, wherein: The first angle is smaller than the second angle, and both angles are greater than 0 and less than 90 degrees; an electrode structure is formed in the peripheral area of ​​the first surface, including: A first conductive pattern, a first passivation layer, a second conductive pattern, and a second passivation layer are sequentially stacked in a direction away from the substrate, and an orthographic projection of the first conductive pattern on the substrate is located within an orthographic projection of the second conductive pattern on the substrate; forming a through hole penetrating the second passivation layer and exposing the second conductive pattern; forming a protection layer covering the second conductive pattern in the through hole; forming a via hole penetrating the first passivation layer and exposing the first conductive pattern, wherein the via hole is formed away from the at least one side surface relative to the through hole; Connecting the second conductive pattern to the first conductive pattern through the connecting hole; and forming a spacer layer between the first conductive pattern and the first passivation layer, wherein the orthographic projection of the formed spacer layer on the substrate is located within the orthographic projection of the first passivation layer on the substrate, and covers the side surface of the first conductive pattern in contact with the buffer layer and the top surface of the side away from the buffer layer, and the thickness of the formed spacer layer is greater than any other film layer in the electrode structure Thickness.

19. A display device, comprising: A power supply component, and a display panel as claimed in any one of claims 1 to 15; Wherein, the power supply component is coupled to the display panel and is used to supply power to the display panel.

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